[GitHub] [incubator-nuttx] pkarashchenko commented on a diff in pull request #6117: arch/risc-v/riscv_misaligned: Implement float load/store support

[GitBox <gi...@apache.org>]

pkarashchenko commented on code in PR #6117:
URL: https://github.com/apache/incubator-nuttx/pull/6117#discussion_r855011378


##########
arch/risc-v/src/common/riscv_misaligned.c:
##########
@@ -443,9 +518,32 @@ static bool decode_insn(uintptr_t *regs, riscv_insn_ctx_t *ctx)
 
       case INSN_FLW:
       case INSN_FLD:
+
+        ctx->dest = (uint8_t *)&regs[REG_F0 + insn.l.rd];
+        ctx->src = (uint8_t *)regs[insn.l.rs1] +
+                   sext(insn.l.imm, 12);
+
+        /* Is instruction flw or fld ? */
+
+        ctx->len = insn.l.funct3 == 0x2 ? 4 : 8;
+        break;
+
       case INSN_FSW:
       case INSN_FSD:
-        _alert("Misaligned float instruction not support yet\n");
+
+        /* Fetch signed imm */
+
+        imm = sext(insn.s.imm2 | insn.s.imm1 << 5, 12);
+
+        ctx->dest = (uint8_t *)regs[insn.s.rs1] + imm;
+        ctx->src = (uint8_t *)&regs[REG_F0 + insn.s.rs2];
+
+        /* Is instruction fsw or fsd ? */
+
+        ctx->len = insn.s.funct3 == 0x2 ? 4 : 8;
+

Review Comment:
   ```suggestion
   ```



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