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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/11/03 10:24:04 UTC

[GitHub] [incubator-nuttx] pussuw commented on pull request #6134: RISC-V: Fix system crash when FPU is in use

pussuw commented on PR #6134:
URL: https://github.com/apache/incubator-nuttx/pull/6134#issuecomment-1301895125

   @masayuki2009 It has been a while but I was revisiting the context saving code and remembered you had an issue with FPU on QEMU. I found at least one issue, that might be the cause for my crashes:
   
   The int/fpu register restoration ordering in exception_common:
   ```
     load_ctx   sp
     riscv_loadfpu sp
   ```
   is bad, because riscv_loadfpu uses registers t0,t1,t2
   ```
   .macro riscv_loadfpu out
   
   #ifdef CONFIG_ARCH_FPU
     REGLOAD      t0, REG_INT_CTX(\out)
     li           t1, MSTATUS_FS
     and          t2, t0, t1
     li           t1, MSTATUS_FS_INIT
     ble          t2, t1, skip_load_fpu
   ```
   
   So the bad ordering restores the original integer registers including t0,t1,t2, and then these are immediately destroyed by riscv_loadfpu.
   
   One potential fix would be use the "bad" ordering above, but to restore t0,t1,t2 from the context after the FPU context is restored:
   
   ```
   skip_load_fpu:
   ... restore t0,t1,t2
   ```
   
   I will try this again when I have time, but if you ever get the urge to get FPU working on QEMU this might be a potential fix.


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