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Posted to commits@nuttx.apache.org by bt...@apache.org on 2021/03/28 20:34:58 UTC
[incubator-nuttx] 02/04: arch: arm: sam: fix nxstyle errors
This is an automated email from the ASF dual-hosted git repository.
btashton pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 60424bc762d1a299e85774fbf3387ac2dbdf69bc
Author: Alin Jerpelea <al...@sony.com>
AuthorDate: Wed Mar 24 09:35:15 2021 +0100
arch: arm: sam: fix nxstyle errors
Fix nxstyle errors to pass CI
Signed-off-by: Alin Jerpelea <al...@sony.com>
---
arch/arm/src/sam34/chip.h | 23 +-
arch/arm/src/sam34/hardware/sam3u_memorymap.h | 28 +-
arch/arm/src/sam34/hardware/sam3u_pinmap.h | 30 +-
arch/arm/src/sam34/hardware/sam3u_pio.h | 32 +-
arch/arm/src/sam34/hardware/sam3x_memorymap.h | 30 +-
arch/arm/src/sam34/hardware/sam3x_pinmap.h | 49 +-
arch/arm/src/sam34/hardware/sam4cm_aes.h | 18 +-
arch/arm/src/sam34/hardware/sam4cm_ipc.h | 16 +-
arch/arm/src/sam34/hardware/sam4cm_memorymap.h | 31 +-
arch/arm/src/sam34/hardware/sam4cm_pinmap.h | 54 +-
arch/arm/src/sam34/hardware/sam4cm_slcdc.h | 18 +-
arch/arm/src/sam34/hardware/sam4cm_supc.h | 35 +-
arch/arm/src/sam34/hardware/sam4e_memorymap.h | 30 +-
arch/arm/src/sam34/hardware/sam4e_pinmap.h | 50 +-
arch/arm/src/sam34/hardware/sam4e_pio.h | 37 +-
arch/arm/src/sam34/hardware/sam4l_bpm.h | 38 +-
arch/arm/src/sam34/hardware/sam4l_bscif.h | 50 +-
arch/arm/src/sam34/hardware/sam4l_flashcalw.h | 37 +-
arch/arm/src/sam34/hardware/sam4l_gpio.h | 49 +-
arch/arm/src/sam34/hardware/sam4l_lcdca.h | 57 +-
arch/arm/src/sam34/hardware/sam4l_memorymap.h | 34 +-
arch/arm/src/sam34/hardware/sam4l_pdca.h | 43 +-
arch/arm/src/sam34/hardware/sam4l_picouart.h | 33 +-
arch/arm/src/sam34/hardware/sam4l_pinmap.h | 47 +-
arch/arm/src/sam34/hardware/sam4l_pm.h | 37 +-
arch/arm/src/sam34/hardware/sam4l_scif.h | 54 +-
arch/arm/src/sam34/hardware/sam4l_usart.h | 44 +-
arch/arm/src/sam34/hardware/sam4l_wdt.h | 36 +-
arch/arm/src/sam34/hardware/sam4s_memorymap.h | 31 +-
arch/arm/src/sam34/hardware/sam4s_pinmap.h | 50 +-
arch/arm/src/sam34/hardware/sam4s_pio.h | 37 +-
arch/arm/src/sam34/hardware/sam_acc.h | 40 +-
arch/arm/src/sam34/hardware/sam_adc.h | 55 +-
arch/arm/src/sam34/hardware/sam_aes.h | 42 +-
arch/arm/src/sam34/hardware/sam_afec.h | 48 +-
arch/arm/src/sam34/hardware/sam_can.h | 39 +-
arch/arm/src/sam34/hardware/sam_chipid.h | 38 +-
arch/arm/src/sam34/hardware/sam_cmcc.h | 40 +-
arch/arm/src/sam34/hardware/sam_dacc.h | 41 +-
arch/arm/src/sam34/hardware/sam_dmac.h | 72 +-
arch/arm/src/sam34/hardware/sam_eefc.h | 33 +-
arch/arm/src/sam34/hardware/sam_emac.h | 65 +-
arch/arm/src/sam34/hardware/sam_gpbr.h | 32 +-
arch/arm/src/sam34/hardware/sam_hsmci.h | 44 +-
arch/arm/src/sam34/hardware/sam_matrix.h | 26 +-
arch/arm/src/sam34/hardware/sam_memorymap.h | 8 +-
arch/arm/src/sam34/hardware/sam_pdc.h | 40 +-
arch/arm/src/sam34/hardware/sam_pinmap.h | 8 +-
arch/arm/src/sam34/hardware/sam_pmc.h | 59 +-
arch/arm/src/sam34/hardware/sam_pwm.h | 87 +-
arch/arm/src/sam34/hardware/sam_rstc.h | 37 +-
arch/arm/src/sam34/hardware/sam_rswdt.h | 33 +-
arch/arm/src/sam34/hardware/sam_rtc.h | 35 +-
arch/arm/src/sam34/hardware/sam_rtt.h | 33 +-
arch/arm/src/sam34/hardware/sam_smc.h | 51 +-
arch/arm/src/sam34/hardware/sam_spi.h | 42 +-
arch/arm/src/sam34/hardware/sam_ssc.h | 60 +-
arch/arm/src/sam34/hardware/sam_supc.h | 34 +-
arch/arm/src/sam34/hardware/sam_tc.h | 55 +-
arch/arm/src/sam34/hardware/sam_twi.h | 33 +-
arch/arm/src/sam34/hardware/sam_uart.h | 42 +-
arch/arm/src/sam34/hardware/sam_udp.h | 42 +-
arch/arm/src/sam34/hardware/sam_udphs.h | 63 +-
arch/arm/src/sam34/hardware/sam_wdt.h | 33 +-
arch/arm/src/sam34/sam3u_gpio.h | 36 +-
arch/arm/src/sam34/sam3u_periphclks.h | 29 +-
arch/arm/src/sam34/sam3x_gpio.h | 36 +-
arch/arm/src/sam34/sam3x_periphclks.h | 29 +-
arch/arm/src/sam34/sam4cm_freerun.c | 6 +-
arch/arm/src/sam34/sam4cm_gpio.h | 36 +-
arch/arm/src/sam34/sam4cm_oneshot.c | 26 +-
arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c | 4 +-
arch/arm/src/sam34/sam4cm_periphclks.h | 29 +-
arch/arm/src/sam34/sam4cm_supc.h | 22 +-
arch/arm/src/sam34/sam4cm_tc.c | 4 +-
arch/arm/src/sam34/sam4cm_tc.h | 1 +
arch/arm/src/sam34/sam4cm_tickless.c | 15 +-
arch/arm/src/sam34/sam4e_gpio.h | 36 +-
arch/arm/src/sam34/sam4e_periphclks.h | 29 +-
arch/arm/src/sam34/sam4l_clockconfig.c | 81 +-
arch/arm/src/sam34/sam4l_gpio.c | 52 +-
arch/arm/src/sam34/sam4l_gpio.h | 50 +-
arch/arm/src/sam34/sam4l_periphclks.c | 4 +-
arch/arm/src/sam34/sam4l_periphclks.h | 90 +-
arch/arm/src/sam34/sam4s_gpio.h | 36 +-
arch/arm/src/sam34/sam4s_periphclks.h | 29 +-
arch/arm/src/sam34/sam_aes.h | 20 +-
arch/arm/src/sam34/sam_allocateheap.c | 12 +-
arch/arm/src/sam34/sam_clockconfig.c | 47 +-
arch/arm/src/sam34/sam_clockconfig.h | 38 +-
arch/arm/src/sam34/sam_cmcc.c | 18 +-
arch/arm/src/sam34/sam_cmcc.h | 32 +-
arch/arm/src/sam34/sam_dmac.c | 12 +-
arch/arm/src/sam34/sam_dmac.h | 52 +-
arch/arm/src/sam34/sam_emac.h | 33 +-
arch/arm/src/sam34/sam_gpio.c | 66 +-
arch/arm/src/sam34/sam_gpio.h | 56 +-
arch/arm/src/sam34/sam_gpioirq.c | 24 +-
arch/arm/src/sam34/sam_hsmci.h | 31 +-
arch/arm/src/sam34/sam_lowputc.c | 14 +-
arch/arm/src/sam34/sam_lowputc.h | 39 +-
arch/arm/src/sam34/sam_mpuinit.h | 32 +-
arch/arm/src/sam34/sam_periphclks.h | 28 +-
arch/arm/src/sam34/sam_rtc.c | 216 +-
arch/arm/src/sam34/sam_rtc.h | 30 +-
arch/arm/src/sam34/sam_rtt.c | 47 +-
arch/arm/src/sam34/sam_rtt.h | 3 +-
arch/arm/src/sam34/sam_spi.h | 6 +-
arch/arm/src/sam34/sam_start.h | 24 +-
arch/arm/src/sam34/sam_tc.c | 51 +-
arch/arm/src/sam34/sam_tc.h | 2 +-
arch/arm/src/sam34/sam_timerisr.c | 1 +
arch/arm/src/sam34/sam_twi.h | 8 +-
arch/arm/src/sam34/sam_udp.h | 37 +-
arch/arm/src/sam34/sam_userspace.h | 28 +-
arch/arm/src/sam34/sam_wdt.h | 2 +-
arch/arm/src/sama5/chip.h | 16 +-
arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h | 104 +-
arch/arm/src/sama5/hardware/_sama5d2x_pio.h | 46 +-
arch/arm/src/sama5/hardware/_sama5d3x4x_pio.h | 35 +-
arch/arm/src/sama5/hardware/_sama5d3x_memorymap.h | 179 +-
arch/arm/src/sama5/hardware/_sama5d3x_mpddrc.h | 37 +-
arch/arm/src/sama5/hardware/_sama5d3x_pinmap.h | 31 +-
arch/arm/src/sama5/hardware/_sama5d4x_memorymap.h | 162 +-
arch/arm/src/sama5/hardware/_sama5d4x_mpddrc.h | 69 +-
arch/arm/src/sama5/hardware/_sama5d4x_pinmap.h | 31 +-
arch/arm/src/sama5/hardware/sam_adc.h | 46 +-
arch/arm/src/sama5/hardware/sam_aic.h | 21 +-
arch/arm/src/sama5/hardware/sam_aximx.h | 25 +-
arch/arm/src/sama5/hardware/sam_bsc.h | 19 +-
arch/arm/src/sama5/hardware/sam_can.h | 42 +-
arch/arm/src/sama5/hardware/sam_dbgu.h | 42 +-
arch/arm/src/sama5/hardware/sam_dmac.h | 71 +-
arch/arm/src/sama5/hardware/sam_ehci.h | 4 +-
arch/arm/src/sama5/hardware/sam_emac.h | 18 +-
arch/arm/src/sama5/hardware/sam_emaca.h | 43 +-
arch/arm/src/sama5/hardware/sam_emacb.h | 73 +-
arch/arm/src/sama5/hardware/sam_flexcom.h | 24 +-
arch/arm/src/sama5/hardware/sam_flexcom_spi.h | 18 +-
arch/arm/src/sama5/hardware/sam_flexcom_twi.h | 18 +-
arch/arm/src/sama5/hardware/sam_flexcom_usart.h | 50 +-
arch/arm/src/sama5/hardware/sam_gmac.h | 70 +-
arch/arm/src/sama5/hardware/sam_gpbr.h | 21 +-
arch/arm/src/sama5/hardware/sam_hsmc.h | 53 +-
arch/arm/src/sama5/hardware/sam_hsmci.h | 45 +-
arch/arm/src/sama5/hardware/sam_isi.h | 48 +-
arch/arm/src/sama5/hardware/sam_lcdc.h | 100 +-
arch/arm/src/sama5/hardware/sam_matrix.h | 68 +-
arch/arm/src/sama5/hardware/sam_memorymap.h | 8 +-
arch/arm/src/sama5/hardware/sam_mpddrc.h | 8 +-
arch/arm/src/sama5/hardware/sam_ohci.h | 5 +-
arch/arm/src/sama5/hardware/sam_pinmap.h | 8 +-
arch/arm/src/sama5/hardware/sam_pio.h | 8 +-
arch/arm/src/sama5/hardware/sam_pit.h | 20 +-
arch/arm/src/sama5/hardware/sam_pmc.h | 71 +-
arch/arm/src/sama5/hardware/sam_pwm.h | 68 +-
arch/arm/src/sama5/hardware/sam_rstc.h | 1 +
arch/arm/src/sama5/hardware/sam_rtc.h | 34 +-
arch/arm/src/sama5/hardware/sam_rxlp.h | 32 +-
arch/arm/src/sama5/hardware/sam_sckc.h | 19 +-
arch/arm/src/sama5/hardware/sam_sdmmc.h | 16 +-
arch/arm/src/sama5/hardware/sam_sfr.h | 37 +-
arch/arm/src/sama5/hardware/sam_spi.h | 43 +-
arch/arm/src/sama5/hardware/sam_ssc.h | 34 +-
arch/arm/src/sama5/hardware/sam_tc.h | 47 +-
arch/arm/src/sama5/hardware/sam_trng.h | 22 +-
arch/arm/src/sama5/hardware/sam_twi.h | 33 +-
arch/arm/src/sama5/hardware/sam_uart.h | 52 +-
arch/arm/src/sama5/hardware/sam_udphs.h | 133 +-
arch/arm/src/sama5/hardware/sam_wdt.h | 33 +-
arch/arm/src/sama5/hardware/sam_xdmac.h | 72 +-
arch/arm/src/sama5/hardware/sama5d2_sdmmc.h | 41 +-
arch/arm/src/sama5/sam_allocateheap.c | 13 +-
arch/arm/src/sama5/sam_boot.c | 12 +-
arch/arm/src/sama5/sam_boot.h | 24 +-
arch/arm/src/sama5/sam_can.c | 4 +-
arch/arm/src/sama5/sam_can.h | 29 +-
arch/arm/src/sama5/sam_clockconfig.c | 4 +-
arch/arm/src/sama5/sam_config.h | 2 +-
arch/arm/src/sama5/sam_dmac.h | 194 +-
arch/arm/src/sama5/sam_ethernet.h | 34 +-
arch/arm/src/sama5/sam_freerun.c | 5 +-
arch/arm/src/sama5/sam_gf1024.c | 6171 ++++++++++++++-------
arch/arm/src/sama5/sam_gf512.c | 3099 +++++++----
arch/arm/src/sama5/sam_hsmci.h | 31 +-
arch/arm/src/sama5/sam_irq.c | 43 +-
arch/arm/src/sama5/sam_isi.c | 5 +-
arch/arm/src/sama5/sam_isi.h | 19 +-
arch/arm/src/sama5/sam_lcd.h | 52 +-
arch/arm/src/sama5/sam_lowputc.c | 11 +-
arch/arm/src/sama5/sam_memorymap.c | 12 +-
arch/arm/src/sama5/sam_memorymap.h | 22 +-
arch/arm/src/sama5/sam_nand.c | 20 +-
arch/arm/src/sama5/sam_nand.h | 24 +-
arch/arm/src/sama5/sam_oneshot.c | 17 +-
arch/arm/src/sama5/sam_oneshot_lowerhalf.c | 4 +-
arch/arm/src/sama5/sam_pck.c | 6 +-
arch/arm/src/sama5/sam_pck.h | 23 +-
arch/arm/src/sama5/sam_periphclks.h | 8 +-
arch/arm/src/sama5/sam_pgalloc.c | 4 +-
arch/arm/src/sama5/sam_pio.c | 12 +-
arch/arm/src/sama5/sam_pio.h | 90 +-
arch/arm/src/sama5/sam_pmc.c | 6 +-
arch/arm/src/sama5/sam_pmc.h | 2 +-
arch/arm/src/sama5/sam_pwm.c | 48 +-
arch/arm/src/sama5/sam_pwm.h | 33 +-
arch/arm/src/sama5/sam_rtc.c | 167 +-
arch/arm/src/sama5/sam_rtc.h | 30 +-
arch/arm/src/sama5/sam_sckc.c | 1 +
arch/arm/src/sama5/sam_sckc.h | 2 +-
arch/arm/src/sama5/sam_spi.h | 25 +-
arch/arm/src/sama5/sam_ssc.h | 28 +-
arch/arm/src/sama5/sam_tc.c | 4 +-
arch/arm/src/sama5/sam_tickless.c | 12 +-
arch/arm/src/sama5/sam_timerisr.c | 1 +
arch/arm/src/sama5/sam_trng.h | 2 +-
arch/arm/src/sama5/sam_tsd.h | 4 +-
arch/arm/src/sama5/sam_twi.h | 8 +-
arch/arm/src/sama5/sam_udphs.h | 26 +-
arch/arm/src/sama5/sam_usbhost.c | 400 +-
arch/arm/src/sama5/sam_usbhost.h | 82 +-
arch/arm/src/sama5/sam_wdt.c | 51 +-
arch/arm/src/sama5/sam_wdt.h | 2 +-
arch/arm/src/sama5/sama5d2x_memorymap.c | 35 +-
arch/arm/src/sama5/sama5d2x_periphclks.h | 28 +-
arch/arm/src/sama5/sama5d2x_pio.h | 24 +-
arch/arm/src/sama5/sama5d3x4x_pio.c | 71 +-
arch/arm/src/sama5/sama5d3x4x_pio.h | 27 +-
arch/arm/src/sama5/sama5d3x_memorymap.c | 51 +-
arch/arm/src/sama5/sama5d3x_periphclks.h | 29 +-
arch/arm/src/sama5/sama5d4x_memorymap.c | 53 +-
arch/arm/src/sama5/sama5d4x_periphclks.h | 29 +-
arch/arm/src/samd2l2/chip.h | 34 +-
arch/arm/src/samd2l2/hardware/samd20_memorymap.h | 27 +-
arch/arm/src/samd2l2/hardware/samd20_pinmap.h | 51 +-
arch/arm/src/samd2l2/hardware/samd21_memorymap.h | 27 +-
arch/arm/src/samd2l2/hardware/samd21_pinmap.h | 48 +-
arch/arm/src/samd2l2/hardware/samd_ac.h | 37 +-
arch/arm/src/samd2l2/hardware/samd_adc.h | 46 +-
arch/arm/src/samd2l2/hardware/samd_dac.h | 38 +-
arch/arm/src/samd2l2/hardware/samd_dmac.h | 71 +-
arch/arm/src/samd2l2/hardware/samd_eic.h | 39 +-
arch/arm/src/samd2l2/hardware/samd_evsys.h | 38 +-
arch/arm/src/samd2l2/hardware/samd_fuses.h | 62 +-
arch/arm/src/samd2l2/hardware/samd_gclk.h | 33 +-
arch/arm/src/samd2l2/hardware/samd_i2c_master.h | 45 +-
arch/arm/src/samd2l2/hardware/samd_i2c_slave.h | 44 +-
arch/arm/src/samd2l2/hardware/samd_i2s.h | 40 +-
arch/arm/src/samd2l2/hardware/samd_nvmctrl.h | 38 +-
arch/arm/src/samd2l2/hardware/samd_pm.h | 37 +-
arch/arm/src/samd2l2/hardware/samd_port.h | 41 +-
arch/arm/src/samd2l2/hardware/samd_sercom.h | 41 +-
arch/arm/src/samd2l2/hardware/samd_spi.h | 44 +-
arch/arm/src/samd2l2/hardware/samd_sysctrl.h | 46 +-
arch/arm/src/samd2l2/hardware/samd_tc.h | 33 +-
arch/arm/src/samd2l2/hardware/samd_tcc.h | 40 +-
arch/arm/src/samd2l2/hardware/samd_usart.h | 44 +-
arch/arm/src/samd2l2/hardware/samd_wdt.h | 98 +-
arch/arm/src/samd2l2/hardware/saml21_memorymap.h | 27 +-
arch/arm/src/samd2l2/hardware/saml21_pinmap.h | 51 +-
arch/arm/src/samd2l2/hardware/saml_adc.h | 24 +-
arch/arm/src/samd2l2/hardware/saml_aes.h | 46 +-
arch/arm/src/samd2l2/hardware/saml_dac.h | 40 +-
arch/arm/src/samd2l2/hardware/saml_dmac.h | 72 +-
arch/arm/src/samd2l2/hardware/saml_eic.h | 40 +-
arch/arm/src/samd2l2/hardware/saml_evsys.h | 44 +-
arch/arm/src/samd2l2/hardware/saml_fuses.h | 34 +-
arch/arm/src/samd2l2/hardware/saml_gclk.h | 38 +-
arch/arm/src/samd2l2/hardware/saml_i2c_master.h | 46 +-
arch/arm/src/samd2l2/hardware/saml_i2c_slave.h | 45 +-
arch/arm/src/samd2l2/hardware/saml_mclk.h | 38 +-
arch/arm/src/samd2l2/hardware/saml_nvmctrl.h | 39 +-
arch/arm/src/samd2l2/hardware/saml_opamp.h | 48 +-
arch/arm/src/samd2l2/hardware/saml_osc32kctrl.h | 42 +-
arch/arm/src/samd2l2/hardware/saml_oscctrl.h | 43 +-
arch/arm/src/samd2l2/hardware/saml_pm.h | 42 +-
arch/arm/src/samd2l2/hardware/saml_port.h | 42 +-
arch/arm/src/samd2l2/hardware/saml_rstc.h | 33 +-
arch/arm/src/samd2l2/hardware/saml_sercom.h | 26 +-
arch/arm/src/samd2l2/hardware/saml_spi.h | 45 +-
arch/arm/src/samd2l2/hardware/saml_supc.h | 43 +-
arch/arm/src/samd2l2/hardware/saml_trng.h | 37 +-
arch/arm/src/samd2l2/hardware/saml_usart.h | 51 +-
arch/arm/src/samd2l2/hardware/saml_usb.h | 67 +-
arch/arm/src/samd2l2/hardware/saml_wdt.h | 98 +-
arch/arm/src/samd2l2/sam_ac.c | 8 +-
arch/arm/src/samd2l2/sam_ac.h | 1 -
arch/arm/src/samd2l2/sam_adc.c | 40 +-
arch/arm/src/samd2l2/sam_clockconfig.h | 30 +-
arch/arm/src/samd2l2/sam_config.h | 32 +-
arch/arm/src/samd2l2/sam_dac.h | 1 -
arch/arm/src/samd2l2/sam_dmac.h | 168 +-
arch/arm/src/samd2l2/sam_i2c_master.c | 219 +-
arch/arm/src/samd2l2/sam_i2c_master.h | 4 +-
arch/arm/src/samd2l2/sam_lowputc.c | 1 +
arch/arm/src/samd2l2/sam_pinmap.h | 8 +-
arch/arm/src/samd2l2/sam_port.c | 30 +-
arch/arm/src/samd2l2/sam_port.h | 9 +-
arch/arm/src/samd2l2/sam_sercom.c | 4 +-
arch/arm/src/samd2l2/sam_sercom.h | 1 +
arch/arm/src/samd2l2/sam_serial.h | 2 +-
arch/arm/src/samd2l2/sam_spi.h | 7 +-
arch/arm/src/samd2l2/sam_start.h | 24 +-
arch/arm/src/samd2l2/sam_usart.h | 51 +-
arch/arm/src/samd2l2/sam_usb.h | 23 +-
arch/arm/src/samd2l2/sam_userspace.h | 26 +-
arch/arm/src/samd2l2/samd_clockconfig.c | 38 +-
arch/arm/src/samd2l2/saml_clockconfig.c | 73 +-
arch/arm/src/samd5e5/chip.h | 32 +-
arch/arm/src/samd5e5/hardware/sam_aes.h | 45 +-
arch/arm/src/samd5e5/hardware/sam_cmcc.h | 39 +-
arch/arm/src/samd5e5/hardware/sam_dmac.h | 65 +-
arch/arm/src/samd5e5/hardware/sam_eic.h | 35 +-
arch/arm/src/samd5e5/hardware/sam_evsys.h | 52 +-
arch/arm/src/samd5e5/hardware/sam_fuses.h | 56 +-
arch/arm/src/samd5e5/hardware/sam_gclk.h | 37 +-
arch/arm/src/samd5e5/hardware/sam_gmac.h | 116 +-
arch/arm/src/samd5e5/hardware/sam_i2c_master.h | 34 +-
arch/arm/src/samd5e5/hardware/sam_i2c_slave.h | 45 +-
arch/arm/src/samd5e5/hardware/sam_mclk.h | 83 +-
arch/arm/src/samd5e5/hardware/sam_memorymap.h | 8 +-
arch/arm/src/samd5e5/hardware/sam_nvmctrl.h | 30 +-
arch/arm/src/samd5e5/hardware/sam_osc32kctrl.h | 41 +-
arch/arm/src/samd5e5/hardware/sam_oscctrl.h | 49 +-
arch/arm/src/samd5e5/hardware/sam_pac.h | 32 +-
arch/arm/src/samd5e5/hardware/sam_pinmap.h | 8 +-
arch/arm/src/samd5e5/hardware/sam_pm.h | 38 +-
arch/arm/src/samd5e5/hardware/sam_port.h | 41 +-
arch/arm/src/samd5e5/hardware/sam_rstc.h | 33 +-
arch/arm/src/samd5e5/hardware/sam_spi.h | 48 +-
arch/arm/src/samd5e5/hardware/sam_supc.h | 40 +-
arch/arm/src/samd5e5/hardware/sam_trng.h | 36 +-
arch/arm/src/samd5e5/hardware/sam_usart.h | 50 +-
arch/arm/src/samd5e5/hardware/samd5e5_memorymap.h | 26 +-
arch/arm/src/samd5e5/hardware/samd5e5_pinmap.h | 51 +-
arch/arm/src/samd5e5/sam_clockconfig.h | 40 +-
arch/arm/src/samd5e5/sam_cmcc.c | 18 +-
arch/arm/src/samd5e5/sam_cmcc.h | 32 +-
arch/arm/src/samd5e5/sam_config.h | 31 +-
arch/arm/src/samd5e5/sam_dmac.h | 163 +-
arch/arm/src/samd5e5/sam_ethernet.h | 4 +-
arch/arm/src/samd5e5/sam_gclk.c | 4 +-
arch/arm/src/samd5e5/sam_gclk.h | 3 +-
arch/arm/src/samd5e5/sam_i2c_master.c | 200 +-
arch/arm/src/samd5e5/sam_mpuinit.h | 32 +-
arch/arm/src/samd5e5/sam_port.c | 30 +-
arch/arm/src/samd5e5/sam_serial.h | 2 +-
arch/arm/src/samd5e5/sam_spi.h | 7 +-
arch/arm/src/samd5e5/sam_start.h | 24 +-
arch/arm/src/samd5e5/sam_usart.h | 38 +-
arch/arm/src/samd5e5/sam_userspace.h | 28 +-
arch/arm/src/samv7/chip.h | 31 +-
arch/arm/src/samv7/hardware/sam_afec.h | 48 +-
arch/arm/src/samv7/hardware/sam_chipid.h | 38 +-
arch/arm/src/samv7/hardware/sam_dacc.h | 50 +-
arch/arm/src/samv7/hardware/sam_eefc.h | 34 +-
arch/arm/src/samv7/hardware/sam_emac.h | 92 +-
arch/arm/src/samv7/hardware/sam_hsmci.h | 47 +-
arch/arm/src/samv7/hardware/sam_matrix.h | 40 +-
arch/arm/src/samv7/hardware/sam_mcan.h | 57 +-
arch/arm/src/samv7/hardware/sam_memorymap.h | 8 +-
arch/arm/src/samv7/hardware/sam_pinmap.h | 8 +-
arch/arm/src/samv7/hardware/sam_pio.h | 43 +-
arch/arm/src/samv7/hardware/sam_pmc.h | 67 +-
arch/arm/src/samv7/hardware/sam_qspi.h | 45 +-
arch/arm/src/samv7/hardware/sam_rstc.h | 33 +-
arch/arm/src/samv7/hardware/sam_rtc.h | 35 +-
arch/arm/src/samv7/hardware/sam_sdramc.h | 41 +-
arch/arm/src/samv7/hardware/sam_smc.h | 35 +-
arch/arm/src/samv7/hardware/sam_spi.h | 42 +-
arch/arm/src/samv7/hardware/sam_ssc.h | 41 +-
arch/arm/src/samv7/hardware/sam_supc.h | 36 +-
arch/arm/src/samv7/hardware/sam_sysc.h | 33 +-
arch/arm/src/samv7/hardware/sam_tc.h | 48 +-
arch/arm/src/samv7/hardware/sam_trng.h | 23 +-
arch/arm/src/samv7/hardware/sam_twihs.h | 39 +-
arch/arm/src/samv7/hardware/sam_uart.h | 50 +-
arch/arm/src/samv7/hardware/sam_usbhs.h | 88 +-
arch/arm/src/samv7/hardware/sam_utmi.h | 33 +-
arch/arm/src/samv7/hardware/sam_wdt.h | 33 +-
arch/arm/src/samv7/hardware/sam_xdmac.h | 73 +-
arch/arm/src/samv7/hardware/same70_memorymap.h | 27 +-
arch/arm/src/samv7/hardware/same70_pinmap.h | 49 +-
arch/arm/src/samv7/hardware/samv71_memorymap.h | 27 +-
arch/arm/src/samv7/hardware/samv71_pinmap.h | 49 +-
arch/arm/src/samv7/sam_allocateheap.c | 11 +-
arch/arm/src/samv7/sam_clockconfig.c | 37 +-
arch/arm/src/samv7/sam_clockconfig.h | 39 +-
arch/arm/src/samv7/sam_config.h | 10 +-
arch/arm/src/samv7/sam_dac.c | 32 +-
arch/arm/src/samv7/sam_dac.h | 5 +-
arch/arm/src/samv7/sam_ethernet.h | 34 +-
arch/arm/src/samv7/sam_freerun.c | 7 +-
arch/arm/src/samv7/sam_gpio.c | 68 +-
arch/arm/src/samv7/sam_gpio.h | 82 +-
arch/arm/src/samv7/sam_gpioirq.c | 25 +-
arch/arm/src/samv7/sam_hsmci.h | 31 +-
arch/arm/src/samv7/sam_lowputc.c | 2 +-
arch/arm/src/samv7/sam_lowputc.h | 50 +-
arch/arm/src/samv7/sam_mcan.h | 2 +-
arch/arm/src/samv7/sam_oneshot.c | 9 +-
arch/arm/src/samv7/sam_oneshot_lowerhalf.c | 4 +-
arch/arm/src/samv7/sam_pck.c | 10 +-
arch/arm/src/samv7/sam_pck.h | 23 +-
arch/arm/src/samv7/sam_periphclks.h | 28 +-
arch/arm/src/samv7/sam_rswdt.c | 69 +-
arch/arm/src/samv7/sam_spi.h | 9 +-
arch/arm/src/samv7/sam_ssc.h | 28 +-
arch/arm/src/samv7/sam_start.h | 35 +-
arch/arm/src/samv7/sam_tc.c | 4 +-
arch/arm/src/samv7/sam_tc.h | 1 +
arch/arm/src/samv7/sam_tickless.c | 16 +-
arch/arm/src/samv7/sam_timerisr.c | 6 +-
arch/arm/src/samv7/sam_trng.h | 2 +-
arch/arm/src/samv7/sam_twihs.h | 8 +-
arch/arm/src/samv7/sam_usbdev.h | 27 +-
arch/arm/src/samv7/sam_userspace.h | 28 +-
arch/arm/src/samv7/sam_wdt.c | 77 +-
arch/arm/src/samv7/sam_wdt.h | 2 +-
arch/arm/src/samv7/sam_xdmac.h | 159 +-
arch/arm/src/samv7/same70_periphclks.h | 29 +-
arch/arm/src/samv7/samv71_periphclks.h | 29 +-
422 files changed, 15477 insertions(+), 9979 deletions(-)
diff --git a/arch/arm/src/sam34/chip.h b/arch/arm/src/sam34/chip.h
index b577ff1..26ebb25 100644
--- a/arch/arm/src/sam34/chip.h
+++ b/arch/arm/src/sam34/chip.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,19 +16,20 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_CHIP_H
#define __ARCH_ARM_SRC_SAM34_CHIP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/* Include the memory map and the chip definitions file. Other chip hardware files
- * should then include this file for the proper setup.
+/* Include the memory map and the chip definitions file.
+ * Other chip hardware files should then include this file for the proper
+ * setup.
*/
#include <arch/sam34/chip.h>
@@ -38,13 +39,13 @@
#include <arch/sam34/irq.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/* Provide the required number of peripheral interrupt vector definitions as well.
- * The definition SAM_IRQ_NEXTINT simply comes from the chip-specific IRQ header
- * file included by arch/sam34/irq.h.
+/* Provide the required number of peripheral interrupt vector definitions as
+ * well. The definition SAM_IRQ_NEXTINT simply comes from the chip-specific
+ * IRQ header file included by arch/sam34/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS SAM_IRQ_NEXTINT
diff --git a/arch/arm/src/sam34/hardware/sam3u_memorymap.h b/arch/arm/src/sam34/hardware/sam3u_memorymap.h
index 4d7090b..eeee517 100644
--- a/arch/arm/src/sam34/hardware/sam3u_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam3u_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam3u_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
#define SAM_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: Code space */
# define SAM_BOOTMEMORY_BASE 0x00000000 /* 0x00000000-0x0007ffff: Boot Memory */
@@ -113,18 +113,18 @@
#define SAM_WDT_BASE 0x400e1250 /* 0x400e1250-0x400e125f: Watchdog Timer */
#define SAM_RTC_BASE 0x400e1260 /* 0x400e1260-0x400e128f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1290 /* 0x400e1290-0x400e13ff: GPBR */
- /* 0x490e1400-0x4007ffff: Reserved */
+ /* 0x490e1400-0x4007ffff: Reserved */
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/hardware/sam3u_pinmap.h b/arch/arm/src/sam34/hardware/sam3u_pinmap.h
index f56d084..0c52cad 100644
--- a/arch/arm/src/sam34/hardware/sam3u_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam3u_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam3u_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/* GPIO pin definitions *************************************************************/
+/* GPIO pin definitions *****************************************************/
#define GPIO_ADC0_AD0 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN21)
#define GPIO_ADC0_AD1 (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN30)
@@ -172,19 +172,19 @@
#define GPIO_USB_VBUS (GPIO_INPUT|GPIO_CFG_DEFAULT|GPIO_PORT_PIOA|GPIO_PIN0)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -195,9 +195,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam3u_pio.h b/arch/arm/src/sam34/hardware/sam3u_pio.h
index dd50eb1..d014ca0 100644
--- a/arch/arm/src/sam34/hardware/sam3u_pio.h
+++ b/arch/arm/src/sam34/hardware/sam3u_pio.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam3u_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PIO register offsets *****************************************************************/
+/* PIO register offsets *****************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
@@ -93,7 +93,7 @@
/* 0x00ec-0x00f8: Reserved */
/* 0x0100-0x0144: Reserved */
-/* PIO register addresses ***************************************************************/
+/* PIO register addresses ***************************************************/
#define PIOA (0)
#define PIOB (1)
@@ -417,7 +417,7 @@
# define SAM_PIOF_WPSR (SAM_PIOF_BASE+SAM_PIO_WPSR_OFFSET)
#endif
-/* PIO register bit definitions *********************************************************/
+/* PIO register bit definitions *********************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
@@ -436,16 +436,16 @@
#define PIO_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define PIO_WPSR_WPVSRC_MASK (0xffff << PIO_WPSR_WPVSRC_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PIO_H */
diff --git a/arch/arm/src/sam34/hardware/sam3x_memorymap.h b/arch/arm/src/sam34/hardware/sam3x_memorymap.h
index 1773e7e..b0adc10 100644
--- a/arch/arm/src/sam34/hardware/sam3x_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam3x_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam3x_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
/* Address regions */
@@ -47,6 +47,7 @@
#define SAM_INTFLASH1_BASE (0x00080000 + SAM34_FLASH_SIZE/2)
#define SAM_INTROM_BASE 0x00100000 /* 0x00100000-0x001fffff: Internal ROM */
/* 0x00200000-0x1fffffff: Reserved */
+
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: Internal SRAM 0 */
@@ -56,6 +57,7 @@
/* 0x20200000-0x201fffff: Undefined */
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32Mb bit-band alias */
/* 0x24000000-0x3fffffff: Undefined */
+
/* Peripherals address region */
#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
@@ -101,6 +103,7 @@
/* 0x41000000-0x41ffffff: Undefined */
#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32Mb bit-band alias */
/* 0x44000000-0x5fffffff: Undefined */
+
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
@@ -127,6 +130,7 @@
#define SAM_RTC_BASE 0x400e1a60 /* 0x400e1a60-0x400e1a8f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1a90 /* 0x400e1a90-0x400e1aaf: GPBR */
/* 0x400e1ab0-0x4007ffff: Reserved */
+
/* External RAM memory region */
#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
@@ -144,16 +148,16 @@
#define SAM_SDRAMCS_BASE 0x70000000 /* 0x70000000-0x7fffffff: SDRAM chip select */
/* 0x80000000-0x9fffffff: Reserved */
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/hardware/sam3x_pinmap.h b/arch/arm/src/sam34/hardware/sam3x_pinmap.h
index ad2c97d..1f5e170 100644
--- a/arch/arm/src/sam34/hardware/sam3x_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam3x_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam3x_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,43 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3X_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
+/* GPIO pin definitions *****************************************************/
-/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
- * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
- * Drivers, however, will use the pin selection without the numeric suffix.
- * Additional definitions are required in the board.h file. For example, if we
- * wanted the PWM0 Output high on PE15, then the following definition should appear
- * in the board.h header file for that board:
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if we wanted the PWM0 Output high on PE15, then the following
+ * definition should appear in the board.h header file for that board:
*
* #define GPIO_PWM0_H GPIO_PWM0_H_1
*
* The driver will then automatically configure RE15 as the PWM0 H pin.
*/
-/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
- * Additional effort is required to select specific GPIO options such as frequency,
- * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
- * pins in this file.
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
*/
/* 12-bit Analog-to-Digital Conververt (ADC) */
@@ -408,19 +409,19 @@
#define GPIO_SWI_SWDIO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN31)
#define GPIO_SWI_TRACESWO (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOB | GPIO_PIN30)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -431,9 +432,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam4cm_aes.h b/arch/arm/src/sam34/hardware/sam4cm_aes.h
index 749fbac..8d63e0f 100644
--- a/arch/arm/src/sam34/hardware/sam4cm_aes.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_aes.h
@@ -1,4 +1,4 @@
-/********************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_aes.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ********************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_AES_H
-/********************************************************************************************
+/****************************************************************************
* Included Files
- ********************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/********************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ********************************************************************************************/
+ ****************************************************************************/
-/* AES register offsets *********************************************************************/
+/* AES register offsets *****************************************************/
#define SAM_AES_CR_OFFSET 0x0000 /* Control Register */
#define SAM_AES_MR_OFFSET 0x0004 /* Control Register */
@@ -53,7 +53,7 @@
#define SAM_AES_CTRR_OFFSET 0x0098 /* GCM Encryption Counter Value Register */
#define SAM_AES_GCMHR_OFFSET 0x009C /* GCM H World Register */
-/* AES register addresses *******************************************************************/
+/* AES register addresses ***************************************************/
#define SAM_AES_CR (SAM_AES_BASE + SAM_AES_CR_OFFSET)
#define SAM_AES_MR (SAM_AES_BASE + SAM_AES_MR_OFFSET)
@@ -72,7 +72,7 @@
#define SAM_AES_CTRR (SAM_AES_BASE + SAM_AES_CTRR_OFFSET)
#define SAM_AES_GCMHR (SAM_AES_BASE + SAM_AES_GCMHR_OFFSET)
-/* AES register bit definitions *************************************************************/
+/* AES register bit definitions *********************************************/
/* AES Control Register */
diff --git a/arch/arm/src/sam34/hardware/sam4cm_ipc.h b/arch/arm/src/sam34/hardware/sam4cm_ipc.h
index 5ca6f30..6556648 100644
--- a/arch/arm/src/sam34/hardware/sam4cm_ipc.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_ipc.h
@@ -1,4 +1,4 @@
-/***********************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_ipc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ***********************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_IPC_H
-/***********************************************************************************
+/****************************************************************************
* Included Files
- ***********************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/***********************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ***********************************************************************************/
+ ****************************************************************************/
-/* IPC register offsets ************************************************************/
+/* IPC register offsets *****************************************************/
#define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */
@@ -44,7 +44,7 @@
#define SAM_IPC_IMR_OFFSET 0x0014 /* Interrupt Mask Register */
#define SAM_IPC_ISR_OFFSET 0x0018 /* Interrupt Status Register */
-/* IPC register addresses **********************************************************/
+/* IPC register addresses ***************************************************/
#define SAM_IPC0_ISCR (SAM_IPC0_BASE + SAM_IPC_ISCR_OFFSET)
#define SAM_IPC0_ICCR (SAM_IPC0_BASE + SAM_IPC_ICCR_OFFSET)
diff --git a/arch/arm/src/sam34/hardware/sam4cm_memorymap.h b/arch/arm/src/sam34/hardware/sam4cm_memorymap.h
index e89b19b..b58da79 100644
--- a/arch/arm/src/sam34/hardware/sam4cm_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_MEMORYMAP_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
/* Address regions */
@@ -53,6 +53,7 @@
#define SAM_INTSRAM1_BASE 0x20080000 /* 0x20080000-0x200fffff: Internal SRAM 1 */
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */
/* 0x24000000-0x3fffffff: Undefined */
+
/* Peripherals address region */
#define SAM_AES_BASE 0x40000000
@@ -113,20 +114,21 @@
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x9fffffff: Reserved */
+
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -139,7 +141,8 @@ extern "C"
static inline unsigned long SAM_PION_BASE(int n)
{
- switch(n) {
+ switch (n)
+ {
case 0:
return SAM_PIOA_BASE;
case 1:
@@ -148,12 +151,12 @@ static inline unsigned long SAM_PION_BASE(int n)
return SAM_PIOC_BASE;
default:
return 0;
- }
+ }
}
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam4cm_pinmap.h b/arch/arm/src/sam34/hardware/sam4cm_pinmap.h
index be03966..516f5d6 100644
--- a/arch/arm/src/sam34/hardware/sam4cm_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,44 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
+/* GPIO pin definitions *****************************************************/
-/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
- * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
- * Drivers, however, will use the pin selection without the numeric suffix.
- * Additional definitions are required in the board.h file. For example, if we
- * wanted the programmable clock output PCK0 on PA6, then the following definition
- * should appear in the board.h header file for that board:
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if we wanted the programmable clock output PCK0 on PA6, then the
+ * following definition should appear in the board.h header file for that
+ * board:
*
* #define GPIO_PCK0 GPIO_PCK0_1
*
* The driver will then automatically configure PA6 as the PCK0 pin.
*/
-/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
- * Additional effort is required to select specific GPIO options such as frequency,
- * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
- * pins in this file.
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
*/
/* 12-bit Analog-to-Digital Converter (ADC) */
@@ -237,7 +239,8 @@
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
/* Segment LCD Controller (SLCDC) */
-//TODO: add rest of segment pins
+
+/* TODO: add rest of segment pins */
#define GPIO_SLCDC_COM0 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN0)
#define GPIO_SLCDC_COM1 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN1)
@@ -270,20 +273,19 @@
#define GPIO_SLCDC_SEG21 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN27)
#define GPIO_SLCDC_SEG22 (GPIO_PERIPHD | GPIO_PORT_PIOA | GPIO_PIN28)
-
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -294,9 +296,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam4cm_slcdc.h b/arch/arm/src/sam34/hardware/sam4cm_slcdc.h
index e529e47..579dfd2 100644
--- a/arch/arm/src/sam34/hardware/sam4cm_slcdc.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_slcdc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_slcdc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SLCDC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* SLCDC register offsets ************************************************************/
+/* SLCDC register offsets ***************************************************/
#define SAM_SLCDC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_SLCDC_MR_OFFSET 0x0004 /* Mode Register */
@@ -54,7 +54,7 @@
#define SAM_SLCDC_LMEMR_OFFSET(com) (0x200 + (com)*8 + 0x0)
#define SAM_SLCDC_MMEMR_OFFSET(com) (0x200 + (com)*8 + 0x4)
-/* SLCDC register addresses **********************************************************/
+/* SLCDC register addresses *************************************************/
#define SAM_SLCDC_CR (SAM_SLCDC_BASE + SAM_SLCDC_CR_OFFSET)
#define SAM_SLCDC_MR (SAM_SLCDC_BASE + SAM_SLCDC_MR_OFFSET)
@@ -74,7 +74,7 @@
#define SAM_SLCDC_LMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_LMEMR_OFFSET(com))
#define SAM_SLCDC_MMEMR(com) (SAM_SLCDC_BASE + SAM_SLCDC_MMEMR_OFFSET(com))
-/* SLCDC register bit definitions ****************************************************/
+/* SLCDC register bit definitions *******************************************/
/* Control Register */
diff --git a/arch/arm/src/sam34/hardware/sam4cm_supc.h b/arch/arm/src/sam34/hardware/sam4cm_supc.h
index 0670ea8..f3629e3 100644
--- a/arch/arm/src/sam34/hardware/sam4cm_supc.h
+++ b/arch/arm/src/sam34/hardware/sam4cm_supc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4cm_supc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* SUPC register offsets ****************************************************************/
+/* SUPC register offsets ****************************************************/
#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
@@ -43,7 +43,7 @@
#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
-/* SUPC register addresses **************************************************************/
+/* SUPC register addresses **************************************************/
#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
@@ -52,7 +52,8 @@
#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET)
#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET)
-/* SUPC register bit definitions ********************************************************/
+/* SUPC register bit definitions ********************************************/
+
/* Supply Controller Control Register */
#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */
@@ -89,6 +90,7 @@
# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
+
#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */
#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */
@@ -116,6 +118,7 @@
# define SUPC_WUMR_FWUPDBC_512SCLK (3 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 512 SLCK periods */
# define SUPC_WUMR_FWUPDBC_4096SCLK (4 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 4096 SLCK periods */
# define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
+
#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
@@ -146,16 +149,16 @@
#define SUPC_SR_WKUPIS_SHIFT (16) /* Bits 16-31: WKUP Input Status 0 to 15 */
#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4CM_SUPC_H */
diff --git a/arch/arm/src/sam34/hardware/sam4e_memorymap.h b/arch/arm/src/sam34/hardware/sam4e_memorymap.h
index c98302c..099b438 100644
--- a/arch/arm/src/sam34/hardware/sam4e_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4e_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4e_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
/* Address regions */
@@ -47,6 +47,7 @@
#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */
#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */
/* 0x00c00000-0x1fffffff: Reserved */
+
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */
@@ -111,7 +112,7 @@
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
- /* 0x400e0000-0x400e01ff: Reserved */
+ /* 0x400e0000-0x400e01ff: Reserved */
#define SAM_MATRIX_BASE 0x400e0200 /* 0x400e0200-0x400e03ff: MATRIX */
#define SAM_PMC_BASE 0x400e0400 /* 0x400e0400-0x400e05ff: Power Management Controller */
#define SAM_UART0_BASE 0x400e0600 /* 0x400e0600-0x400e073f: UART 0 */
@@ -144,21 +145,22 @@
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x9fffffff: Reserved */
+
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/hardware/sam4e_pinmap.h b/arch/arm/src/sam34/hardware/sam4e_pinmap.h
index 48ab04c..f2e7c92 100644
--- a/arch/arm/src/sam34/hardware/sam4e_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4e_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4e_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,44 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
+/* GPIO pin definitions *****************************************************/
-/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
- * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
- * Drivers, however, will use the pin selection without the numeric suffix.
- * Additional definitions are required in the board.h file. For example, if we
- * wanted the programmable clock output PCK0 on PA6, then the following definition
- * should appear in the board.h header file for that board:
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if we wanted the programmable clock output PCK0 on PA6, then the
+ * following definition should appear in the board.h header file for that
+ * board:
*
* #define GPIO_PCK0 GPIO_PCK0_1
*
* The driver will then automatically configure PA6 as the PCK0 pin.
*/
-/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
- * Additional effort is required to select specific GPIO options such as frequency,
- * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
- * pins in this file.
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
*/
/* Analog Front End (AFE) */
@@ -286,19 +288,19 @@
#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -309,9 +311,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam4e_pio.h b/arch/arm/src/sam34/hardware/sam4e_pio.h
index 003a3d8..c3c0e2f 100644
--- a/arch/arm/src/sam34/hardware/sam4e_pio.h
+++ b/arch/arm/src/sam34/hardware/sam4e_pio.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4e_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PIO register offsets *****************************************************************/
+/* PIO register offsets *****************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
@@ -107,7 +107,7 @@
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
-/* PIO register addresses ***************************************************************/
+/* PIO register addresses ***************************************************/
#define PIOA (0)
#define PIOB (1)
@@ -450,7 +450,7 @@
#define SAM_PIOE_PCISR (SAM_PIOE_BASE+SAM_PIO_PCISR_OFFSET)
#define SAM_PIOE_PCRHR (SAM_PIOE_BASE+SAM_PIO_PCRHR_OFFSET
-/* PIO register bit definitions *********************************************************/
+/* PIO register bit definitions *********************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
@@ -512,27 +512,30 @@
# define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */
+
#define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */
#define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */
#define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */
-/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */
+/* PIO Parallel Capture Interrupt Enable, Disable, Mask,
+ * and Status Registers
+ */
#define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */
#define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */
#define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */
#define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4E_PIO_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_bpm.h b/arch/arm/src/sam34/hardware/sam4l_bpm.h
index 12f7372..03809ef 100644
--- a/arch/arm/src/sam34/hardware/sam4l_bpm.h
+++ b/arch/arm/src/sam34/hardware/sam4l_bpm.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_bpm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* BPM register offsets ****************************************************************/
+/* BPM register offsets *****************************************************/
#define SAM_BPM_IER_OFFSET 0x0000 /* Interrupt Enable Register */
#define SAM_BPM_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
@@ -50,7 +50,7 @@
#define SAM_BPM_IORET_OFFSET 0x0034 /* Input Output Retention Register */
#define SAM_BPM_VERSION_OFFSET 0x00fc /* Version Register */
-/* BPM register addresses **************************************************************/
+/* BPM register addresses ***************************************************/
#define SAM_BPM_IER (SAM_BPM_BASE+SAM_BPM_IER_OFFSET)
#define SAM_BPM_IDR (SAM_BPM_BASE+SAM_BPM_IDR_OFFSET)
@@ -66,13 +66,18 @@
#define SAM_BPM_IORET (SAM_BPM_BASE+SAM_BPM_IORET_OFFSET)
#define SAM_BPM_VERSION (SAM_BPM_BASE+SAM_BPM_VERSION_OFFSET)
-/* BPM register bit definitions ********************************************************/
+/* BPM register bit definitions *********************************************/
/* Interrupt Enable Register */
+
/* Interrupt Disable Register */
+
/* Interrupt Mask Register */
+
/* Interrupt Status Register */
+
/* Interrupt Clear Register */
+
/* Status Register */
#define BPM_INT_PSOK (1 << 0) /* Bit 0: Power Scaling OK */
@@ -104,6 +109,7 @@
# define BPM_PMCON_SLEEP_SLEEP1 (1 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP2 (2 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK clocks stopped */
# define BPM_PMCON_SLEEP_SLEEP3 (3 << BPM_PMCON_SLEEP_SHIFT) /* CPU+AHB+PB+GCLK+sources stopped */
+
#define BPM_PMCON_CK32S (1 << 16) /* Bit 16: 32kHz-1kHz Clock Source Selection */
#define BPM_PMCON_FASTWKUP (1 << 24) /* Bit 24: Fast Wakeup */
@@ -148,16 +154,16 @@
#define BPM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define BPM_VERSION_VARIANT_MASK (15 << BPM_VERSION_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BPM_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_bscif.h b/arch/arm/src/sam34/hardware/sam4l_bscif.h
index f3eb716..df85dc0 100644
--- a/arch/arm/src/sam34/hardware/sam4l_bscif.h
+++ b/arch/arm/src/sam34/hardware/sam4l_bscif.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_bscif.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* BSCIF register offsets ***************************************************************/
+/* BSCIF register offsets ***************************************************/
#define SAM_BSCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */
#define SAM_BSCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
@@ -70,7 +70,7 @@
#define SAM_BSCIF_OSC32IFAVERSION_OFFSET 0x03f8 /* 32 kHz Oscillator Version Register */
#define SAM_BSCIF_VERSION_OFFSET 0x03fc /* BSCIF Version Register */
-/* BSCIF register addresses *************************************************************/
+/* BSCIF register addresses *************************************************/
#define SAM_BSCIF_IER (SAM_BSCIF_BASE+SAM_BSCIF_IER_OFFSET)
#define SAM_BSCIF_IDR (SAM_BSCIF_BASE+SAM_BSCIF_IDR_OFFSET)
@@ -106,12 +106,16 @@
#define SAM_BSCIF_OSC32IFAVERSION (SAM_BSCIF_BASE+SAM_BSCIF_OSC32IFAVERSION_OFFSET)
#define SAM_BSCIF_VERSION (SAM_BSCIF_BASE+SAM_BSCIF_VERSION_OFFSET)
-/* BSCIF register bit definitions *******************************************************/
+/* BSCIF register bit definitions *******************************************/
/* Interrupt Enable Register */
+
/* Interrupt Disable Register */
+
/* Interrupt Mask Register */
+
/* Interrupt Status Register */
+
/* Interrupt Clear Register */
#define BSCIF_INT_OSC32RDY (1 << 0) /* Bit 0 */
@@ -167,6 +171,7 @@
# define BSCIF_OSCCTRL32_MODE_XTALAC (3 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + amplitude controlled mode */
# define BSCIF_OSCCTRL32_MODE_XTALHC (4 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current mode */
# define BSCIF_OSCCTRL32_MODE_XTALHCAC (5 << BSCIF_OSCCTRL32_MODE_SHIFT) /* Crystal + high current + amplitude controlled mode */
+
#define BSCIF_OSCCTRL32_SELCURR_SHIFT (12) /* Bits 12-15: Current Selection */
#define BSCIF_OSCCTRL32_SELCURR_MASK (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
# define BSCIF_OSCCTRL32_SELCURR_50 (0 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
@@ -185,6 +190,7 @@
# define BSCIF_OSCCTRL32_SELCURR_375 (13 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
# define BSCIF_OSCCTRL32_SELCURR_400 (14 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
# define BSCIF_OSCCTRL32_SELCURR_425 (15 << BSCIF_OSCCTRL32_SELCURR_SHIFT)
+
#define BSCIF_OSCCTRL32_STARTUP_SHIFT (16) /* Bits 16-18: Oscillator Start-up Time */
#define BSCIF_OSCCTRL32_STARTUP_MASK (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT)
# define BSCIF_OSCCTRL32_STARTUP_0 (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT)
@@ -195,6 +201,7 @@
# define BSCIF_OSCCTRL32_STARTUP_128K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 131072 1.1 s */
# define BSCIF_OSCCTRL32_STARTUP_256K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 262144 2.3 s */
# define BSCIF_OSCCTRL32_STARTUP_512K (7 << BSCIF_OSCCTRL32_STARTUP_SHIFT) /* 524288 4.6 s */
+
#define BSCIF_OSCCTRL32_RESERVED (1 << 31) /* Bit 31: Reserved, must always be written as zero */
/* 32kHz RC Oscillator Control Register */
@@ -215,18 +222,22 @@
#define BSCIF_RC32KTUNE_COARSE_MASK (0x7f << BSCIF_RC32KTUNE_COARSE_SHIFT)
/* BOD33 Control Register */
+
/* BOD18 Control Register */
#define BSCIF_BODCTRL_EN (1 << 0) /* Bit 0: Enable */
#define BSCIF_BODCTRL_HYST (1 << 1) /* Bit 1: BOD Hysteresis */
#define BSCIF_BODCTRL_ACTION_SHIFT (8) /* Bits 8-9: Action */
+
# define BSCIF_BODCTRL_ACTION_RESET (1 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates a reset */
# define BSCIF_BODCTRL_ACTION_INTR (2 << BSCIF_BODCTRL_ACTION_SHIFT) /* The BOD generates an interrupt */
+
#define BSCIF_BODCTRL_MODE (1 << 0) /* Bit 0: Operation modes */
#define BSCIF_BODCTRL_FCD (1 << 0) /* Bit 0: BOD Fuse Calibration Done */
#define BSCIF_BODCTRL_SFV (1 << 0) /* Bit 0: BOD Control Register Store Final Value */
/* BOD33 Level Register */
+
/* BOD18 Level Register */
#define BSCIF_BODLEVEL_CEN (1 << 0) /* Bit 0: Clock Enable */
@@ -235,6 +246,7 @@
#define BSCIF_BODLEVEL_PSEL_MASK (15 << BSCIF_BODLEVEL_PSEL_SHIFT)
/* BOD33 Sampling Control Register */
+
/* BOD18 Sampling Control Register */
#define BSCIF_BODSAMPLING_VAL_SHIFT (0) /* Bits 0-5: BOD Value */
@@ -274,11 +286,17 @@
/* 0x0078-0x0084 Backup register n=0..3 (32-bit data) */
/* Backup Register Interface Version Register */
+
/* BGREFIF Version Register */
+
/* Voltage Regulator Version Register */
+
/* BOD Version Register */
+
/* 32kHz RC Oscillator Version Register */
+
/* 32 kHz Oscillator Version Register */
+
/* BSCIF Version Register */
#define BSCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
@@ -286,16 +304,16 @@
#define BSCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define BSCIF_VARIANT_MASK (15 << BSCIF_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_BSCIF_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_flashcalw.h b/arch/arm/src/sam34/hardware/sam4l_flashcalw.h
index 01508b5..d70863e 100644
--- a/arch/arm/src/sam34/hardware/sam4l_flashcalw.h
+++ b/arch/arm/src/sam34/hardware/sam4l_flashcalw.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_flashcalw.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
-/* Register offsets *****************************************************************/
/* Relative to SAM_FLASHCALW_BASE */
#define SAM_FLASHCALW_FCR_OFFSET 0x0000 /* Flash Control Register */
@@ -57,7 +58,7 @@
#define SAM_PICOCACHE_MSR_OFFSET 0x0034 /* PicoCache Monitor Status Register */
#define SAM_PICOCACHE_PVR_OFFSET 0x00fc /* Version Register */
-/* Register Addresses ***************************************************************/
+/* Register Addresses *******************************************************/
#define SAM_FLASHCALW_FCR (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCR_OFFSET)
#define SAM_FLASHCALW_FCMD (SAM_FLASHCALW_BASE+SAM_FLASHCALW_FCMD_OFFSET)
@@ -77,7 +78,7 @@
#define SAM_PICOCACHE_MSR (SAM_PICOCACHE_BASE+SAM_PICOCACHE_MSR_OFFSET)
#define SAM_PICOCACHE_PVR (SAM_PICOCACHE_BASE+SAM_PICOCACHE_PVR_OFFSET)
-/* Register Bit-field Definitions ***************************************************/
+/* Register Bit-field Definitions *******************************************/
/* Flash Control Register */
@@ -110,6 +111,7 @@
# define FLASHCALW_FCMD_CMD_QPRUP (15 << FLASHCALW_FCMD_CMD_SHIFT) /* Quick Page Read User Page */
# define FLASHCALW_FCMD_CMD_HSEN (16 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Enable */
# define FLASHCALW_FCMD_CMD_HSDIS (17 << FLASHCALW_FCMD_CMD_SHIFT) /* High Speed Mode Disable */
+
#define FLASHCALW_FCMD_PAGEN_SHIFT (8) /* Bits 8-23: Page number */
#define FLASHCALW_FCMD_PAGEN_MASK (0xffff << FLASHCALW_FCMD_PAGEN_SHIFT)
#define FLASHCALW_FCMD_KEY_SHIFT (14) /* Bits 24-31: Write protection key */
@@ -163,6 +165,7 @@
# define FLASHCALW_FPR_FSZ_768KB (12 << FLASHCALW_FPR_FSZ_SHIFT) /* 768 Kbytes */
# define FLASHCALW_FPR_FSZ_1MB (13 << FLASHCALW_FPR_FSZ_SHIFT) /* 1024 Kbytes */
# define FLASHCALW_FPR_FSZ_2MB (14 << FLASHCALW_FPR_FSZ_SHIFT) /* 2048 Kbytes */
+
#define FLASHCALW_FPR_PSZ_SHIFT (8) /* Bits 8-9: Page Size */
#define FLASHCALW_FPR_PSZ_MASK (7 << FLASHCALW_FPR_PSZ_SHIFT)
# define FLASHCALW_FPR_PSZ_32KB (0 << FLASHCALW_FPR_PSZ_SHIFT) /* 32 Kbytes */
@@ -295,7 +298,7 @@
#define PICOCACHE_PVR_MFN_SHIFT (16) /* Bits 16-19: MFN */
#define PICOCACHE_PVR_MFN_MASK (15 << PICOCACHE_PVR_FVR_MFN_SHIFT)
-/* Flash Command Set ****************************************************************/
+/* Flash Command Set ********************************************************/
#define FLASH_CMD_NOP 0 /* No operation */
#define FLASH_CMD_WP 1 /* Write Page */
@@ -346,16 +349,16 @@
#define FLASH_MAXFREQ_PS2_HSEN_FWS0 (24000000ul)
#define FLASH_MAXFREQ_PS2_HSEN_FWS1 (48000000ul)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_FLASHCALW_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_gpio.h b/arch/arm/src/sam34/hardware/sam4l_gpio.h
index 757c6f8..e3c0334 100644
--- a/arch/arm/src/sam34/hardware/sam4l_gpio.h
+++ b/arch/arm/src/sam34/hardware/sam4l_gpio.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PIO register offsets *****************************************************************/
+/* PIO register offsets *****************************************************/
#define SAM_GPIO_GPER_OFFSET 0x0000 /* GPIO Enable Register Read/Write */
#define SAM_GPIO_GPERS_OFFSET 0x0004 /* GPIO Enable Register Set */
@@ -48,10 +48,11 @@
* 010 C 110 G
* 011 D 111 H
*
- * NOTE: Labeling in the data sheet is inconsistent. In the pin multiplexing table,
- * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO. In the
- * register description, it should A-H with presumably A corresponding to 000. Here
- * we adopt the above convention.
+ * NOTE:
+ * Labeling in the data sheet is inconsistent. In the pin multiplexing table,
+ * It shows GPIO functions A-G with 000 apparently corresponding to the GPIO.
+ * In the register description, it should A-H with presumably A
+ * corresponding to 000. Here we adopt the above convention.
*/
#define SAM_GPIO_PMR0_OFFSET 0x0010 /* Peripheral Mux Register 0 Read/Write */
@@ -166,7 +167,7 @@
#define SAM_GPIO_PARAMETER_OFFSET 0x01f8 /* Parameter Register Read */
#define SAM_GPIO_VERSION_OFFSET 0x01fc /* Version Register Read */
-/* GPIO port offsets and addresses ******************************************************/
+/* GPIO port offsets and addresses ******************************************/
#define SAM_GPIOA 0
#define SAM_GPIOB 1
@@ -179,7 +180,7 @@
#define SAM_GPIOB_BASE SAM_GPION_BASE(SAM_GPIOB)
#define SAM_GPIOC_BASE SAM_GPION_BASE(SAM_GPIOC)
-/* GPIO register addresses **************************************************************/
+/* GPIO register addresses **************************************************/
#define SAM_GPIO_GPER(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIO_GPERS(n) (SAM_GPION_BASE(n)+SAM_GPIO_GPERS_OFFSET)
@@ -274,7 +275,7 @@
#define SAM_GPIO_PARAMETER(n) (SAM_GPION_BASE(n)+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIO_VERSION (n) (SAM_GPION_BASE(n)+SAM_GPIO_VERSION_OFFSET)
-/* GPIO PORTA register addresses ********************************************************/
+/* GPIO PORTA register addresses ********************************************/
#define SAM_GPIOA_GPER (SAM_GPIOA_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOA_GPERS (SAM_GPIOA_BASE+SAM_GPIO_GPERS_OFFSET)
@@ -369,7 +370,7 @@
#define SAM_GPIOA_PARAMETER (SAM_GPIOA_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOA_VERSION (SAM_GPIOA_BASE+SAM_GPIO_VERSION_OFFSET)
-/* GPIO PORTB register addresses ********************************************************/
+/* GPIO PORTB register addresses ********************************************/
#define SAM_GPIOB_GPER (SAM_GPIOB_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOB_GPERS (SAM_GPIOB_BASE+SAM_GPIO_GPERS_OFFSET)
@@ -464,7 +465,7 @@
#define SAM_GPIOB_PARAMETER (SAM_GPIOB_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOB_VERSION (SAM_GPIOB_BASE+SAM_GPIO_VERSION_OFFSET)
-/* GPIO PORTC register addresses ********************************************************/
+/* GPIO PORTC register addresses ********************************************/
#define SAM_GPIOC_GPER (SAM_GPIOC_BASE+SAM_GPIO_GPER_OFFSET)
#define SAM_GPIOC_GPERS (SAM_GPIOC_BASE+SAM_GPIO_GPERS_OFFSET)
@@ -559,22 +560,22 @@
#define SAM_GPIOC_PARAMETER (SAM_GPIOC_BASE+SAM_GPIO_PARAMETER_OFFSET)
#define SAM_GPIOC_VERSION (SAM_GPIOC_BASE+SAM_GPIO_VERSION_OFFSET)
-/* GPIO register bit definitions ********************************************************/
+/* GPIO register bit definitions ********************************************/
/* Common bit definitions for all GPIO registers */
#define PIN(n) (1 << (n)) /* Bit n: PIO n */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_GPIO_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_lcdca.h b/arch/arm/src/sam34/hardware/sam4l_lcdca.h
index c84702a..7407879 100644
--- a/arch/arm/src/sam34/hardware/sam4l_lcdca.h
+++ b/arch/arm/src/sam34/hardware/sam4l_lcdca.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_lcdca.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* LCDCA register offsets ************************************************************/
+/* LCDCA register offsets ***************************************************/
#define SAM_LCDCA_CR_OFFSET 0x0000 /* Control Register */
#define SAM_LCDCA_CFG_OFFSET 0x0004 /* Configuration Register */
@@ -67,7 +67,7 @@
#define SAM_LCDCA_IMR_OFFSET 0x0060 /* Interrupt Mask Register */
#define SAM_LCDCA_VERSION_OFFSET 0x0064 /* Version Register */
-/* LCDCA register addresses **********************************************************/
+/* LCDCA register addresses *************************************************/
#define SAM_LCDCA_CR (SAM_LCDCA_BASE+SAM_LCDCA_CR_OFFSET)
#define SAM_LCDCA_CFG (SAM_LCDCA_BASE+SAM_LCDCA_CFG_OFFSET)
@@ -100,7 +100,7 @@
#define SAM_LCDCA_IMR (SAM_LCDCA_BASE+SAM_LCDCA_IMR_OFFSET)
#define SAM_LCDCA_VERSION (SAM_LCDCA_BASE+SAM_LCDCA_VERSION_OFFSET)
-/* LCDCA register bit definitions ****************************************************/
+/* LCDCA register bit definitions *******************************************/
/* Control Register */
@@ -132,9 +132,11 @@
# define LCDCA_CFG_DUTY_STATIC (1 << LCDCA_CFG_DUTY_SHIFT) /* Static, Static, COM0 */
# define LCDCA_CFG_DUTY_1TO2 (2 << LCDCA_CFG_DUTY_SHIFT) /* 1/2, 1/3, COM[0:1] */
# define LCDCA_CFG_DUTY_1TO3 (3 << LCDCA_CFG_DUTY_SHIFT) /* 1/3, 1/3, COM[0:2] */
+
#define LCDCA_CFG_FCST_SHIFT (16) /* Bits 16-21: Fine Contrast */
#define LCDCA_CFG_FCST_MASK (63 << LCDCA_CFG_FCST_SHIFT)
# define LCDCA_CFG_FCST(n) (((uint32_t)(n) & 63) << LCDCA_CFG_FCST_SHIFT) /* n = -32..31 */
+
#define LCDCA_CFG_NSU_SHIFT (24) /* Bits 24-29: Number of Segment Terminals in Use */
#define LCDCA_CFG_NSU_MASK (63 << LCDCA_CFG_NSU_SHIFT)
# define LCDCA_CFG_NSU(n) ((n) << LCDCA_CFG_NSU_SHIFT) /* n=0-40 */
@@ -145,13 +147,16 @@
#define LCDCA_TIM_CLKDIV_SHIFT (1) /* Bits 1-3: LCD Clock Division */
#define LCDCA_TIM_CLKDIV_MASK (7 << LCDCA_TIM_CLKDIV_SHIFT)
# define LCDCA_TIM_CLKDIV(n) (((n)-1) << LCDCA_TIM_CLKDIV_SHIFT) /* n=1..8 */
+
#define LCDCA_TIM_FC0_SHIFT (8) /* Bits 8-12: Frame Counter 0 */
#define LCDCA_TIM_FC0_MASK (31 << LCDCA_TIM_FC0_SHIFT)
# define LCDCA_TIM_FC0(n) ((n) << LCDCA_TIM_FC0_SHIFT) /* n=0-31 */
+
#define LCDCA_TIM_FC0PB (1 << 13) /* Bit 13: Frame Counter 0 Prescaler Bypass */
#define LCDCA_TIM_FC1_SHIFT (16) /* Bits 16-20: Frame Counter 1 */
#define LCDCA_TIM_FC1_MASK (31 << LCDCA_TIM_FC1_SHIFT)
# define LCDCA_TIM_FC1(n) ((n) << LCDCA_TIM_FC1_SHIFT) /* n=0-31 */
+
#define LCDCA_TIM_FC2_SHIFT (24) /* Bits 24-28: Frame Counter 2 */
#define LCDCA_TIM_FC2_MASK (31 << LCDCA_TIM_FC2_SHIFT)
# define LCDCA_TIM_FC2(n) ((n) << LCDCA_TIM_FC2_SHIFT) /* n=0-31 */
@@ -172,14 +177,14 @@
#define LCDCA_SCR_FC0R (1 << 0) /* Bit 0: Frame Counter 0 Rollover */
-/* Data Register Low 0-3 (32-bit data, each bit defines a segment value in display
- * memory for segments 0-31).
+/* Data Register Low 0-3 (32-bit data, each bit defines a segment value in
+ * display memory for segments 0-31).
*/
#define LCDCA_DRL_MASK 0xffffffff
-/* Data Register High 0-3 (8 bits data, each bit defines a segment value in display
- * memory for segments 32-39)
+/* Data Register High 0-3 (8 bits data, each bit defines a segment value in
+ * display memory for segments 32-39)
*/
#define LCDCA_DRH_MASK 0xff
@@ -221,6 +226,7 @@
# define LCDCA_BCFG_FCS0 (0 << LCDCA_BCFG_FCS_SHIFT)
# define LCDCA_BCFG_FCS1 (1 << LCDCA_BCFG_FCS_SHIFT)
# define LCDCA_BCFG_FCS2 (2 << LCDCA_BCFG_FCS_SHIFT)
+
#define LCDCA_BCFG_BSS0_SHIFT (8) /* Bits 8-11: Blink Segment Selection 0 */
#define LCDCA_BCFG_BSS0_MASK (15 << LCDCA_BCFG_BSS0_SHIFT)
# define LCDCA_BCFG_BSS0(n) ((n) << LCDCA_BCFG_BSS0_SHIFT) /* n=bitset */
@@ -228,6 +234,7 @@
# define LCDCA_BCFG_BSS01 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM1 selected */
# define LCDCA_BCFG_BSS02 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM2 selected */
# define LCDCA_BCFG_BSS03 (0 << LCDCA_BCFG_BSS0_SHIFT) /* Segment SEG0/COM3 selected */
+
#define LCDCA_BCFG_BSS1_SHIFT (12) /* Bits 12-15: Blink Segment Selection 1 */
#define LCDCA_BCFG_BSS1_MASK (15 << LCDCA_BCFG_BSS1_SHIFT)
# define LCDCA_BCFG_BSS1(n) ((n) << LCDCA_BCFG_BSS1_SHIFT) /* n=bitset */
@@ -245,9 +252,11 @@
# define LCDCA_CSRCFG_FCS0 (0 << LCDCA_CSRCFG_FCS_SHIFT)
# define LCDCA_CSRCFG_FCS1 (1 << LCDCA_CSRCFG_FCS_SHIFT)
# define LCDCA_CSRCFG_FCS2 (2 << LCDCA_CSRCFG_FCS_SHIFT)
+
#define LCDCA_CSRCFG_SIZE_SHIFT (3) /* Bits 3-5: Size */
#define LCDCA_CSRCFG_SIZE_MASK (7 << LCDCA_CSRCFG_SIZE_SHIFT)
# define LCDCA_CSRCFG_SIZE(n) (((n)-1) << LCDCA_CSRCFG_SIZE_SHIFT) /* n=1..8 */
+
#define LCDCA_CSRCFG_DATA_SHIFT (8) /* Bits 8-15: Circular Shift Register Value */
#define LCDCA_CSRCFG_DATA_MASK (0xff << LCDCA_CSRCFG_DATA_SHIFT)
# define LCDCA_CSRCFG_DATA(n) ((n) << LCDCA_CSRCFG_DATA_SHIFT)
@@ -261,6 +270,7 @@
# define LCDCA_CMCFG_TDG_7S4C (1 << LCDCA_CMCFG_TDG_SHIFT) /* 7-segment with 4 common terminals */
# define LCDCA_CMCFG_TDG_14S4C (2 << LCDCA_CMCFG_TDG_SHIFT) /* 14-segment with 4 common terminals */
# define LCDCA_CMCFG_TDG_14S3C (3 << LCDCA_CMCFG_TDG_SHIFT) /* 16-segment with 3 common terminals */
+
#define LCDCA_CMCFG_STSEG_SHIFT (8) /* Bits 8-13: Start Segment */
#define LCDCA_CMCFG_STSEG_MASK (63 << LCDCA_CMCFG_STSEG_SHIFT)
# define LCDCA_CMCFG_STSEG(n) ((n) << LCDCA_CMCFG_STSEG_SHIFT)
@@ -278,6 +288,7 @@
# define LCDCA_ACMCFG_FCS0 (0 << LCDCA_ACMCFG_FCS_SHIFT)
# define LCDCA_ACMCFG_FCS1 (1 << LCDCA_ACMCFG_FCS_SHIFT)
# define LCDCA_ACMCFG_FCS2 (2 << LCDCA_ACMCFG_FCS_SHIFT)
+
#define LCDCA_ACMCFG_MODE (1 << 3) /* Bit 3: Mode */
#define LCDCA_ACMCFG_DREV (1 << 4) /* Bit 4: Digit Reverse */
#define LCDCA_ACMCFG_TDG_SHIFT (5) /* Bits 5-6: Type of Digit */
@@ -286,12 +297,15 @@
# define LCDCA_ACMCFG_TDG_7S4C (1 << LCDCA_ACMCFG_TDG_SHIFT) /* 7-segment with 4 common terminals */
# define LCDCA_ACMCFG_TDG_14S4C (2 << LCDCA_ACMCFG_TDG_SHIFT) /* 14-segment with 4 common terminals */
# define LCDCA_ACMCFG_TDG_14S3C (3 << LCDCA_ACMCFG_TDG_SHIFT) /* 16-segment with 3 common terminals */
+
#define LCDCA_ACMCFG_STSEG_SHIFT (8) /* Bits 8-13: Start Segment */
#define LCDCA_ACMCFG_STSEG_MASK (63 << LCDCA_ACMCFG_STSEG_SHIFT)
# define LCDCA_ACMCFG_STSEG(n) ((n) << LCDCA_ACMCFG_STSEG_SHIFT)
+
#define LCDCA_ACMCFG_STEPS_SHIFT (16) /* Bits 16-23: Scrolling Steps */
#define LCDCA_ACMCFG_STEPS_MASK (0xff << LCDCA_ACMCFG_STEPS_SHIFT)
# define LCDCA_ACMCFG_STEPS(n) ((n) << LCDCA_ACMCFG_STEPS_SHIFT) /* n = string length - DIGN + 1 */
+
#define LCDCA_ACMCFG_DIGN_SHIFT (24) /* Bits 24-27: Digit Number */
#define LCDCA_ACMCFG_DIGN_MASK (15 << LCDCA_ACMCFG_DIGN_SHIFT)
# define LCDCA_ACMCFG_DIGN(n) ((n) << LCDCA_ACMCFG_DIGN_SHIFT) /* n=1..15 */
@@ -309,6 +323,7 @@
# define LCDCA_ABMCFG_FCS0 (0 << LCDCA_ABMCFG_FCS_SHIFT)
# define LCDCA_ABMCFG_FCS1 (1 << LCDCA_ABMCFG_FCS_SHIFT)
# define LCDCA_ABMCFG_FCS2 (2 << LCDCA_ABMCFG_FCS_SHIFT)
+
#define LCDCA_ABMCFG_SIZE_SHIFT (8) /* Bits 8-12: Size */
#define LCDCA_ABMCFG_SIZE_MASK (31 << LCDCA_ABMCFG_SIZE_SHIFT)
# define LCDCA_ABMCFG_SIZE(n) (((n)-1) << LCDCA_ABMCFG_SIZE_SHIFT) /* n=1..31 */
@@ -342,7 +357,9 @@
# define LCDCA_ABMDR_OFF(n) (31 << LCDCA_ABMDR_OFF_SHIFT)
/* Interrupt Enable Register */
+
/* Interrupt Disable Register */
+
/* Interrupt Mask Register */
#define LCDCA_INT_FC0R (1 << 0) /* Bit 0: Frame Counter 0 Rollover */
@@ -354,16 +371,16 @@
#define LCDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define LCDCA_VARIANT_MASK (15 << LCDCA_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_LCDCA_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_memorymap.h b/arch/arm/src/sam34/hardware/sam4l_memorymap.h
index 8cc3d1d..6c38a01 100644
--- a/arch/arm/src/sam34/hardware/sam4l_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4l_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
/* Global Memory Space */
@@ -45,12 +45,14 @@
#define SAM_INTFLASH_BASE 0x00000000 /* 0x00000000-0x003fffff: Internal FLASH */
/* 0x00400000-0x1fffffff: Reserved */
+
/* Internal SRAM Space */
#define SAM_INTSRAM0_BASE 0x20000000 /* 0x20000000-0x2007ffff: HRAMC0 (see chip.h) */
/* 0x20008000-0x20ffffff: Reserved */
#define SAM_INTSRAM1_BASE 0x21000000 /* 0x21000000-0x210007ff: HRAMC1 (see chip.h) */
/* 0x21000800-0x21ffffff: Reserved */
+
/* Peripherals Space */
#define SAM_PERIPHA_BASE 0x40000000 /* 0x40000000-0x4009ffff: Peripheral Bridge A */
@@ -60,7 +62,9 @@
#define SAM_PERIPHC_BASE 0x400e0000 /* 0x400e0000-0x400effff: Peripheral Bridge C */
#define SAM_PERIPHD_BASE 0x400e0000 /* 0x400f0000-0x400fffff: Peripheral Bridge D */
/* 0x40100000-0x5fffffff: Reserved */
+
/* Peripheral Bridge A */
+
/* 0x40000000-0x40003fff: Reserved */
#define SAM_I2SC_BASE 0x40004000 /* 0x40004000-0x40007fff: I2S Controller */
#define SAM_SPI0_BASE 0x40008000 /* 0x40008000-0x4000bfff: Serial Peripheral Interface */
@@ -93,6 +97,7 @@
#define SAM_TWIM3_BASE 0x4007c000 /* 0x4007c000-0x4007ffff: Two-wire Master Interface 3 */
#define SAM_LCDCA_BASE 0x40080000 /* 0x40080000-0x40083fff: LCD Controller A */
/* 0x40084000-0x4009ffff: Reserved */
+
/* Peripheral Bridge B */
#define SAM_FLASHCALW_BASE 0x400a0000 /* 0x400a0000-0x400a03ff: FLASHCALW */
@@ -104,6 +109,7 @@
#define SAM_USBC_BASE 0x400a5000 /* 0x400a5000-0x400a5fff: USB 2.0 Interface */
#define SAM_PEVC_BASE 0x400a6000 /* 0x400a6000-0x400a63ff: Peripheral Event Controller */
/* 0x400a6400-0x400affff: Reserved */
+
/* Peripheral Bridge C */
#define SAM_PM_BASE 0x400e0000 /* 0x400e0000-0x400e073f: Power Manager */
@@ -112,6 +118,7 @@
#define SAM_FREQM_BASE 0x400e0c00 /* 0x400e0c00-0x400e0fff: Frequency Meter */
#define SAM_GPIO_BASE 0x400e1000 /* 0x400e1000-0x400e17ff: GPIO */
/* 0x400e1800-0x400effff: Reserved */
+
/* Peripheral Bridge D */
#define SAM_BPM_BASE 0x400f0000 /* 0x400f0000-0x400f03ff: Backup Power Manager */
@@ -121,6 +128,7 @@
#define SAM_EIC_BASE 0x400f1000 /* 0x400f1000-0x400f13ff: External Interrupt Controller */
#define SAM_PICOUART_BASE 0x400f1400 /* 0x400f1400-0x400f17ff: PICOUART */
/* 0x400f1800-0x400fffff: Reserved */
+
/* System Space */
#define SAM_ITM_BASE 0xe0000000 /* 0xe0000000-0xe0000fff: ITM */
@@ -135,16 +143,16 @@
#define SAM_ROMTAB_BASE 0xe00ff000 /* 0xe00ff000-0xe00fffff: ROM Table */
/* 0xe0100000-0xffffffff: Reserved */
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_pdca.h b/arch/arm/src/sam34/hardware/sam4l_pdca.h
index 3b1550d..04d5c7b 100644
--- a/arch/arm/src/sam34/hardware/sam4l_pdca.h
+++ b/arch/arm/src/sam34/hardware/sam4l_pdca.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_pdca.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PDCA channel offsets *****************************************************************/
+/* PDCA channel offsets *****************************************************/
#define SAM_PDCA_CHAN_OFFSET(n) ((n) << 6)
#define SAM_PDCA_CHAN0_OFFSET 0x0000
@@ -54,7 +54,8 @@
#define SAM_PDCA_CHAN14_OFFSET 0x0380
#define SAM_PDCA_CHAN15_OFFSET 0x03c0
-/* PDCA register offsets ****************************************************************/
+/* PDCA register offsets ****************************************************/
+
/* Channel register offsets */
#define SAM_PDCA_MAR_OFFSET 0x0000 /* Memory Address Register */
@@ -74,7 +75,8 @@
#define SAM_PDCA_VERSION_OFFSET 0x834 /* Version Register */
-/* PDCA channel addresses ***************************************************************/
+/* PDCA channel addresses ***************************************************/
+
/* Channel register base addresses */
#define SAM_PDCA_CHAN(n) (SAM_PDCA_BASE+SAM_PDCA_CHAN_OFFSET(n))
@@ -95,7 +97,8 @@
#define SAM_PDCA_CHAN14 (SAM_PDCA_BASE+SAM_PDCA_CHAN14_OFFSET)
#define SAM_PDCA_CHAN15 (SAM_PDCA_BASE+SAM_PDCA_CHAN15_OFFSET)
-/* PDCA register addresses **************************************************************/
+/* PDCA register addresses **************************************************/
+
/* Channel register addresses */
#define SAM_PDCA_MAR(n) (SAM_PDCA_CHAN(n)+SAM_PDCA_MAR_OFFSET)
@@ -115,7 +118,7 @@
#define SAM_PDCA_VERSION (SAM_PDCA_BASE+SAM_PDCA_VERSION_OFFSET)
-/* PDCA register bit definitions ********************************************************/
+/* PDCA register bit definitions ********************************************/
/* Memory Address Register (32-bit address) */
@@ -125,7 +128,7 @@
/* Transfer Counter Register */
-#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value
+#define PDCA_TCR_MASK 0xffff /* Bits 0-15: Transfer Counter Value */
/* Memory Address Reload Register (32-bit address) */
@@ -158,7 +161,9 @@
#define PDCA_IER_
/* Interrupt Disable Register */
+
/* Interrupt Mask Register */
+
/* Interrupt Status Register */
#define PDCA_INT_RCZ (1 << 2) /* Bit 0: Reload Counter Zero */
@@ -174,16 +179,16 @@
#define PDCA_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define PDCA_VARIANT_MASK (15 << PDCA_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PDCA_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_picouart.h b/arch/arm/src/sam34/hardware/sam4l_picouart.h
index 6498cd8..4a6821a 100644
--- a/arch/arm/src/sam34/hardware/sam4l_picouart.h
+++ b/arch/arm/src/sam34/hardware/sam4l_picouart.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_picouart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PICOUART register offsets ************************************************************/
+/* PICOUART register offsets ************************************************/
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_PICOUART_CFG_OFFSET 0x0004 /* Configuration Register */
@@ -42,7 +42,7 @@
#define SAM_PICOUART_RHR_OFFSET 0x000c /* Receive Holding Register */
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
-/* PICOUART register addresses **********************************************************/
+/* PICOUART register addresses **********************************************/
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_PICOUART_CR_OFFSET 0x0000 /* Control Register */
@@ -55,7 +55,7 @@
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
#define SAM_PICOUART_VERSION_OFFSET 0x0020 /* Version Register */
-/* PICOUART register bit definitions ****************************************************/
+/* PICOUART register bit definitions ****************************************/
/* Control Register */
@@ -70,6 +70,7 @@
# define PICOUART_CFG_SOURCE_WESB (1 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on start bit detection */
# define PICOUART_CFG_SOURCE_WEFF (2 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on full frame reception */
# define PICOUART_CFG_SOURCE_WECH (3 << PICOUART_CFG_SOURCE_SHIFT) /* Wake up or event enable on character recognition */
+
#define PICOUART_CFG_ACTION (1 << 0) /* Bit 0: Action to perform */
#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */
#define PICOUART_CFG_MATCH_SHIFT (8) /* Bit 8-15: Data Match */
@@ -91,16 +92,16 @@
#define PICOUART_VARIANT_SHIFT (16) /* Bits 16-18: Reserved */
#define PICOUART_VARIANT_MASK (7 << PICOUART_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PICOUART_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_pinmap.h b/arch/arm/src/sam34/hardware/sam4l_pinmap.h
index 19bd175..c4b1831 100644
--- a/arch/arm/src/sam34/hardware/sam4l_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4l_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,40 +16,41 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM3U_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
/* Alternate Pin Functions.
*
- * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
- * Drivers, however, will use the pin selection without the numeric suffix.
- * Additional definitions are required in the board.h file. For example, if
- * SPI MSIO connects vis PA21 on some board, then the following definition should
- * appear in the board.h header file for that board:
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if SPI MSIO connects vis PA21 on some board, then the following
+ * definition should appear in the board.h header file for that board:
*
* #define GPIO_SPI_MISO GPIO_SPI_MISO_1
*
* The driver will then automatically configure PA21 as the SPI MISO pin.
*/
-/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
- * Additional effort is required to select specific GPIO options such as frequency,
- * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
- * pins in this file.
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
*/
/* Audio Bitstream DAC */
@@ -528,19 +529,19 @@
#define GPIO_USBC_DM (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN25)
#define GPIO_USBC_DP (GPIO_FUNCA | GPIO_PORTA | GPIO_PIN26)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -551,9 +552,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam4l_pm.h b/arch/arm/src/sam34/hardware/sam4l_pm.h
index a3cba58..654fd8a 100644
--- a/arch/arm/src/sam34/hardware/sam4l_pm.h
+++ b/arch/arm/src/sam34/hardware/sam4l_pm.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_pm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/* Register offsets *****************************************************************/
+/* Register offsets *********************************************************/
#define SAM_PM_MCCTRL_OFFSET 0x0000 /* Main Clock Control Register */
#define SAM_PM_CPUSEL_OFFSET 0x0004 /* CPU Clock Select Register */
@@ -66,7 +66,7 @@
#define SAM_PM_CONFIG_OFFSET 0x03f8 /* Configuration Register */
#define SAM_PM_VERSION_OFFSET 0x03fc /* Version Register */
-/* Register Addresses ***************************************************************/
+/* Register Addresses *******************************************************/
#define SAM_PM_MCCTRL (SAM_PM_BASE+SAM_PM_MCCTRL_OFFSET)
#define SAM_PM_CPUSEL (SAM_PM_BASE+SAM_PM_CPUSEL_OFFSET)
@@ -98,7 +98,7 @@
#define SAM_PM_CONFIG (SAM_PM_BASE+SAM_PM_CONFIG_OFFSET)
#define SAM_PM_VERSION (SAM_PM_BASE+SAM_PM_VERSION_OFFSET)
-/* Register Bit-field Definitions ***************************************************/
+/* Register Bit-field Definitions *******************************************/
/* Main Clock Control Register Bit-field Definitions */
@@ -231,10 +231,15 @@
# define PM_UNLOCK_KEY(n) ((n) << PM_UNLOCK_KEY_SHIFT)
/* Interrupt Enable Register Bit-field Definitions */
+
/* Interrupt Disable Register Bit-field Definitions */
+
/* Interrupt Mask Register Bit-field Definitions */
+
/* Interrupt Status Register Bit-field Definitions */
+
/* Interrupt Clear Register Bit-field Definitions */
+
/* Status Register Register */
#define PM_INT_CFD (1 << 0) /* Bit 0: CFD */
@@ -318,16 +323,16 @@
#define PM_VERSION_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define PM_VERSION_VARIANT_MASK (15 << PM_VERSION_VARIANT_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_PM_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_scif.h b/arch/arm/src/sam34/hardware/sam4l_scif.h
index 6c5f075..755ccc9 100644
--- a/arch/arm/src/sam34/hardware/sam4l_scif.h
+++ b/arch/arm/src/sam34/hardware/sam4l_scif.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_scif.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* SCIF register offsets ****************************************************************/
+/* SCIF register offsets ****************************************************/
#define SAM_SCIF_IER_OFFSET 0x0000 /* Interrupt Enable Register */
#define SAM_SCIF_IDR_OFFSET 0x0004 /* Interrupt Disable Register */
@@ -83,7 +83,7 @@
#define SAM_SCIF_GCLKVERSION_OFFSET 0x03f8 /* Generic Clock Version Register */
#define SAM_SCIF_VERSION_OFFSET 0x03fc /* SCIF Version Register */
-/* SCIF register addresses **************************************************************/
+/* SCIF register addresses **************************************************/
#define SAM_SCIF_IER (SAM_SCIF_BASE+SAM_SCIF_IER_OFFSET)
#define SAM_SCIF_IDR (SAM_SCIF_BASE+SAM_SCIF_IDR_OFFSET)
@@ -132,13 +132,18 @@
#define SAM_SCIF_GCLKVERSION (SAM_SCIF_BASE+SAM_SCIF_GCLKVERSION_OFFSET)
#define SAM_SCIF_VERSION (SAM_SCIF_BASE+SAM_SCIF_VERSION_OFFSET)
-/* SCIF register bit definitions ********************************************************/
+/* SCIF register bit definitions ********************************************/
/* Interrupt Enable Register */
+
/* Interrupt Disable Register */
+
/* Interrupt Mask Register */
+
/* Interrupt Status Register */
+
/* Interrupt Clear Register */
+
/* Power and Clocks Status Register */
#define SCIF_INT_OSC0RDY (1 << 0) /* Bit 0: OSC0 Ready */
@@ -187,6 +192,7 @@
# define SCIF_OSCCTRL0_STARTUP_512 (13 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 512 4.5 ms */
# define SCIF_OSCCTRL0_STARTUP_1K (14 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 1024 8.9 ms */
# define SCIF_OSCCTRL0_STARTUP_32K2 (15 << SCIF_OSCCTRL0_STARTUP_SHIFT) /* 2768 285 ms */
+
#define SCIF_OSCCTRL0_OSCEN (1 << 16) /* Bit 16: Oscillator Enable */
/* PLL0 Control Register */
@@ -196,11 +202,13 @@
#define SCIF_PLL0_PLLOSC_MASK (3 << SCIF_PLL0_PLLOSC_SHIFT)
# define SCIF_PLL0_PLLOSC_OSC0 (0 << SCIF_PLL0_PLLOSC_SHIFT) /* Output clock from Oscillator0 */
# define SCIF_PLL0_PLLOSC_GCLK9 (1 << SCIF_PLL0_PLLOSC_SHIFT) /* Generic clock 9 */
+
#define SCIF_PLL0_PLLOPT_SHIFT (3) /* Bits 3-5: PLL Option */
#define SCIF_PLL0_PLLOPT_MASK (7 << SCIF_PLL0_PLLOPT_SHIFT)
# define SCIF_PLL0_PLLOPT_FVO (1 << SCIF_PLL0_PLLOPT_SHIFT) /* Selects the VCO frequency range (fvco) */
# define SCIF_PLL0_PLLOPT_DIV2 (2 << SCIF_PLL0_PLLOPT_SHIFT) /* Divides the output frequency by 2 */
# define SCIF_PLL0_PLLOPT_WBM (4 << SCIF_PLL0_PLLOPT_SHIFT) /* Wide-Bandwidth mode */
+
#define SCIF_PLL0_PLLDIV_SHIFT (8) /* Bits 8-11: PLL Division Factor */
#define SCIF_PLL0_PLLDIV_MASK (15 << SCIF_PLL0_PLLDIV_SHIFT)
#define SCIF_PLL0_PLLMUL_SHIFT (16) /* Bits 16-19: PLL Multiply Factor */
@@ -209,7 +217,8 @@
#define SCIF_PLL0_PLLCOUNT_MASK (63 << SCIF_PLL0_PLLCOUNT_SHIFT)
# define SCIF_PLL0_PLLCOUNT_MAX (63 << SCIF_PLL0_PLLCOUNT_SHIFT)
-/* PLL0 operates in two frequency ranges as determined by SCIF_PLL0_PLLOPT_FVO:
+/* PLL0 operates in two frequency ranges as determined by
+ * SCIF_PLL0_PLLOPT_FVO:
*
* 0: 80MHz < fvco < 180MHz
* 1: 160MHz < fvco < 240MHz
@@ -240,6 +249,7 @@
# define SCIF_DFLL0CONF_RANGE1 (1 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 50-110MHz */
# define SCIF_DFLL0CONF_RANGE2 (2 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 25-55MHz */
# define SCIF_DFLL0CONF_RANGE3 (3 << SCIF_DFLL0CONF_RANGE_SHIFT) /* 20-30MHz */
+
#define SCIF_DFLL0CONF_FCD (1 << 23) /* Bit 23: Fuse Calibration Done */
#define SCIF_DFLL0CONF_CALIB_SHIFT (24) /* Bits 24-27: Calibration Value */
#define SCIF_DFLL0CONF_CALIB_MASK (15 << SCIF_DFLL0CONF_CALIB_SHIFT)
@@ -311,6 +321,7 @@
# define SCIF_RCFASTCFG_FRANGE_4MHZ (0 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 4MHz range selected */
# define SCIF_RCFASTCFG_FRANGE_8MHZ (1 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 8MHz range selected */
# define SCIF_RCFASTCFG_FRANGE_12MHZ (2 << SCIF_RCFASTCFG_FRANGE_SHIFT) /* 12MHz range selected */
+
#define SCIF_RCFASTCFG_LOCKMARGIN_SHIFT (12) /* Bits 12-15: Accepted Count Error for Lock */
#define SCIF_RCFASTCFG_LOCKMARGIN_MASK (15 << SCIF_RCFASTCFG_LOCKMARGIN_SHIFT)
#define SCIF_RCFASTCFG_CALIB_SHIFT (16) /* Bits 16-22: Oscillator Calibration Value */
@@ -383,18 +394,27 @@
# define SCIF_GCCTRL_OSCSEL_GCLKIN0 (19 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN0 */
# define SCIF_GCCTRL_OSCSEL_GCLKIN1 (20 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLKIN1 */
# define SCIF_GCCTRL_OSCSEL_GCLK11 (21 << SCIF_GCCTRL_OSCSEL_SHIFT) /* GCLK11 */
+
#define SCIF_GCCTRL_DIV_SHIFT (16) /* Bits 16-31: Division Factor */
#define SCIF_GCCTRL_DIV_MASK (0xffff << SCIF_GCCTRL_DIV_SHIFT)
# define SCIF_GCCTRL_DIV(n) ((n) << SCIF_GCCTRL_DIV_SHIFT)
/* 4/8/12MHz RC Oscillator Version Register */
+
/* Generic Clock Prescaler Version Register */
+
/* PLL Version Register */
+
/* Oscillator0 Version Register */
+
/* DFLL Version Register */
+
/* System RC Oscillator Version Register */
+
/* 80MHz RC Oscillator Version Register */
+
/* Generic Clock Version Register */
+
/* SCIF Version Register */
#define SCIF_VERSION_SHIFT (0) /* Bits 0-11: Version Number */
@@ -402,16 +422,16 @@
#define SCIF_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define SCIF_VARIANT_MASK (15 << SCIF_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_SCIF_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_usart.h b/arch/arm/src/sam34/hardware/sam4l_usart.h
index 8654713..bbfaee3 100644
--- a/arch/arm/src/sam34/hardware/sam4l_usart.h
+++ b/arch/arm/src/sam34/hardware/sam4l_usart.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_usart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
-/* USART register offsets ***********************************************************************/
+/* USART register offsets ***************************************************/
#define SAM_UART_CR_OFFSET 0x0000 /* Control Register */
#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register */
@@ -63,7 +63,7 @@
#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register */
/* 0x0100-0x0124: PDC Area */
-/* USART register addresses *********************************************************************/
+/* USART register addresses *************************************************/
#define SAM_USART_CR(n) (SAM_USARTN_BASE(n)+SAM_UART_CR_OFFSET)
#define SAM_USART_MR(n) (SAM_USARTN_BASE(n)+SAM_UART_MR_OFFSET)
@@ -175,7 +175,7 @@
#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET)
-/* USART register bit definitions ***************************************************************/
+/* USART register bit definitions *******************************************/
/* USART Control Register */
@@ -214,17 +214,20 @@
# define UART_MR_MODE_IRDA (8 << UART_MR_MODE_SHIFT) /* IrDA */
# define UART_MR_MODE_SPIMSTR (14 << UART_MR_MODE_SHIFT) /* SPI Master */
# define UART_MR_MODE_SPISLV (15 << UART_MR_MODE_SHIFT) /* SPI Slave */
+
#define UART_MR_USCLKS_SHIFT (4) /* Bits 4-5: Clock Selection */
#define UART_MR_USCLKS_MASK (3 << UART_MR_USCLKS_SHIFT)
# define UART_MR_USCLKS_USART (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART */
# define UART_MR_USCLKS_USARTDIV (0 << UART_MR_USCLKS_SHIFT) /* CLK_USART/DIV(1) */
# define UART_MR_USCLKS_CLK (0 << UART_MR_USCLKS_SHIFT) /* CLK */
+
#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length */
#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT)
# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */
# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */
# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */
# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */
+
#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select */
#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase */
#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type */
@@ -235,17 +238,20 @@
# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 */
# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity */
# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode */
+
#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits */
#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT)
# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */
# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */
+
#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode */
#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT)
# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */
# define UART_MR_CHMODE_ECHO (1 << UART_MR_CHMODE_SHIFT) /* Automatic Echo */
# define UART_MR_CHMODE_LLPBK (2 << UART_MR_CHMODE_SHIFT) /* Local Loopback */
# define UART_MR_CHMODE_RLPBK (3 << UART_MR_CHMODE_SHIFT) /* Remote Loopback */
+
#define UART_MR_MSBF (1 << 16) /* Bit 16: Most Significant Bit first */
#define UART_MR_CPOL (1 << 16) /* Bit 16: SPI Clock Polarity */
#define UART_MR_MODE9 (1 << 17) /* Bit 17: 9-bit Character Length */
@@ -262,7 +268,8 @@
#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode */
#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector */
-/* USART Interrupt Enable Register, USART Interrupt Disable Register, USART Interrupt Mask
+/* USART Interrupt Enable Register
+ * USART Interrupt Disable Register, USART Interrupt Mask
* Register, and USART Status Register common bit field definitions.
*
* - Bits that provide interrupts with UART_INT_
@@ -357,6 +364,7 @@
# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */
# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */
# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */
+
#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity */
#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length */
#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT)
@@ -366,6 +374,7 @@
# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */
# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */
# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */
+
#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity */
#define UART_MAN_DRIFT (1 << 30) /* Bit 30: Drift compensation */
@@ -376,6 +385,7 @@
# define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */
# define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */
# define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does neither */
+
#define UART_LINMR_PARDIS (1 << 2) /* Bit 0: Parity Disable */
#define UART_LINMR_CHKDIS (1 << 3) /* Bit 0: Checksum Disable */
#define UART_LINMR_CHKTYP (1 << 4) /* Bit 0: Checksum Type */
@@ -417,16 +427,16 @@
#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved */
#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT)
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_UART_H */
diff --git a/arch/arm/src/sam34/hardware/sam4l_wdt.h b/arch/arm/src/sam34/hardware/sam4l_wdt.h
index ef7ff74..dd8554b 100644
--- a/arch/arm/src/sam34/hardware/sam4l_wdt.h
+++ b/arch/arm/src/sam34/hardware/sam4l_wdt.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4l_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* WDT register offsets ****************************************************************/
+/* WDT register offsets *****************************************************/
#define SAM_WDT_CTRL_OFFSET 0x0000 /* Control Register */
#define SAM_WDT_CLR_OFFSET 0x0004 /* Clear Register */
@@ -46,7 +46,7 @@
#define SAM_WDT_ICR_OFFSET 0x001c /* Interrupt Clear Register */
#define SAM_WDT_VERSION_OFFSET 0x03fc /* Version Register */
-/* WDT register addresses **************************************************************/
+/* WDT register addresses ***************************************************/
#define SAM_WDT_CTRL (SAM_WDT_BASE+SAM_WDT_CTRL_OFFSET)
#define SAM_WDT_CLR (SAM_WDT_BASE+SAM_WDT_CLR_OFFSET)
@@ -58,7 +58,7 @@
#define SAM_WDT_ICR (SAM_WDT_BASE+SAM_WDT_ICR_OFFSET)
#define SAM_WDT_VERSION (SAM_WDT_BASE+SAM_WDT_VERSION_OFFSET)
-/* WDT register bit definitions ********************************************************/
+/* WDT register bit definitions *********************************************/
/* Control Register */
@@ -93,9 +93,13 @@
#define WDT_SR_CLEARED (1 << 1) /* Bit 1: WDT Counter Cleared */
/* Interrupt Enable Register */
+
/* Interrupt Disable Register */
+
/* Interrupt Mask Register */
+
/* Interrupt Status Register */
+
/* Interrupt Clear Register */
#define WDT_WINT (1 << 2) /* Bit 2: WINT */
@@ -107,16 +111,16 @@
#define WDT_VARIANT_SHIFT (16) /* Bits 16-19: Variant Number */
#define WDT_VARIANT_MASK (15 << WDT_VARIANT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4L_WDT_H */
diff --git a/arch/arm/src/sam34/hardware/sam4s_memorymap.h b/arch/arm/src/sam34/hardware/sam4s_memorymap.h
index 5922b77..7e1d500 100644
--- a/arch/arm/src/sam34/hardware/sam4s_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam4s_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4s_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,21 +16,21 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
/* Address regions */
@@ -47,11 +47,13 @@
#define SAM_INTFLASH_BASE 0x00400000 /* 0x00400000-0x007fffff: Internal FLASH */
#define SAM_INTROM_BASE 0x00800000 /* 0x00180000-0x00bfffff: Internal ROM */
/* 0x00c00000-0x1fffffff: Reserved */
+
/* Internal SRAM memory region */
#define SAM_INTSRAM0_BASE 0x20000000 /* For SAM3U compatibility */
#define SAM_BBSRAM_BASE 0x22000000 /* 0x22000000-0x23ffffff: 32MB bit-band region */
/* 0x24000000-0x3fffffff: Undefined */
+
/* Peripherals address region */
#define SAM_HSMCI_BASE 0x40000000 /* 0x40000000-0x400003ff: High Speed Multimedia Card Interface */
@@ -89,6 +91,7 @@
/* 0x40100000-0x4002ffff: Reserved */
#define SAM_BBPERIPH_BASE 0x42000000 /* 0x42000000-0x43ffffff: 32MB bit-band region */
/* 0x44000000-0x5fffffff: Reserved */
+
/* System Controller Register Blocks: 0x400e0000-0x4007ffff */
#define SAM_SMC_BASE 0x400e0000 /* 0x400e0000-0x400e01ff: Static Memory Controller */
@@ -112,6 +115,7 @@
#define SAM_RTC_BASE 0x400e1460 /* 0x400e1460-0x400e148f: Real Time Clock */
#define SAM_GPBR_BASE 0x400e1490 /* 0x400e1490-0x400e15ff: GPBR */
/* 0x400e1600-0x4007ffff: Reserved */
+
/* External RAM memory region */
#define SAM_EXTCS_BASE 0x60000000 /* 0x60000000-0x63ffffff: Chip selects */
@@ -121,21 +125,22 @@
# define SAM_EXTCS2_BASE 0x62000000 /* 0x62000000-0x62ffffff: Chip select 2 */
# define SAM_EXTCS3_BASE 0x63000000 /* 0x63000000-0x63ffffff: Chip select 3 */
/* 0x64000000-0x9fffffff: Reserved */
+
/* System memory region */
#define SAM_PRIVPERIPH_BASE 0xe0000000 /* 0xe0000000-0xe00fffff: Private peripheral bus */
#define SAM_VENDOR_BASE 0xe0100000 /* 0ex0100000-0xffffffff: Vendor-specific memory */
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_MEMORYMAP_H */
diff --git a/arch/arm/src/sam34/hardware/sam4s_pinmap.h b/arch/arm/src/sam34/hardware/sam4s_pinmap.h
index 9c18dcc..d8a751d 100644
--- a/arch/arm/src/sam34/hardware/sam4s_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam4s_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4s_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,42 +16,44 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "sam_gpio.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
+/* GPIO pin definitions *****************************************************/
-/* GPIO pin definitions *************************************************************/
/* Alternate Pin Functions.
*
- * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.
- * Drivers, however, will use the pin selection without the numeric suffix.
- * Additional definitions are required in the board.h file. For example, if we
- * wanted the programmable clock output PCK0 on PA6, then the following definition
- * should appear in the board.h header file for that board:
+ * Alternative pin selections are provided with a numeric suffix like _1, _2,
+ * etc. Drivers, however, will use the pin selection without the numeric
+ * suffix. Additional definitions are required in the board.h file. For
+ * example, if we wanted the programmable clock output PCK0 on PA6, then the
+ * following definition should appear in the board.h header file for that
+ * board:
*
* #define GPIO_PCK0 GPIO_PCK0_1
*
* The driver will then automatically configure PA6 as the PCK0 pin.
*/
-/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
- * Additional effort is required to select specific GPIO options such as frequency,
- * open-drain/push-pull, and pull-up/down! Just the basics are defined for most
- * pins in this file.
+/* WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, open-drain/push-pull, and pull-up/down! Just the basics are
+ * defined for most pins in this file.
*/
/* 12-bit Analog-to-Digital Converter (ADC) */
@@ -263,19 +265,19 @@
#define GPIO_USART1_SCK (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN23)
#define GPIO_USART1_TXD (GPIO_PERIPHA | GPIO_CFG_DEFAULT | GPIO_PORT_PIOA | GPIO_PIN22)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -286,9 +288,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/hardware/sam4s_pio.h b/arch/arm/src/sam34/hardware/sam4s_pio.h
index 396cae6..42d1c63 100644
--- a/arch/arm/src/sam34/hardware/sam4s_pio.h
+++ b/arch/arm/src/sam34/hardware/sam4s_pio.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam4s_pio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PIO register offsets *****************************************************************/
+/* PIO register offsets *****************************************************/
#define SAM_PIO_PER_OFFSET 0x0000 /* PIO Enable Register */
#define SAM_PIO_PDR_OFFSET 0x0004 /* PIO Disable Register */
@@ -105,7 +105,7 @@
#define SAM_PIO_PCRHR_OFFSET 0x0164 /* Parallel Capture Reception Holding Register */
/* 0x0168-0x018c: Reserved for PDC registers */
-/* PIO register addresses ***************************************************************/
+/* PIO register addresses ***************************************************/
#define PIOA (0)
#define PIOB (1)
@@ -332,7 +332,7 @@
#define SAM_PIOC_PCISR (SAM_PIOC_BASE+SAM_PIO_PCISR_OFFSET)
#define SAM_PIOC_PCRHR (SAM_PIOC_BASE+SAM_PIO_PCRHR_OFFSET
-/* PIO register bit definitions *********************************************************/
+/* PIO register bit definitions *********************************************/
/* Common bit definitions for ALMOST all IO registers (exceptions follow) */
@@ -359,27 +359,30 @@
# define PIO_PCMR_DSIZE_BYTE (0 << PIO_PCMR_DSIZE_SHIFT) /* 8-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_HWORD (1 << PIO_PCMR_DSIZE_SHIFT) /* 16-bit data in PIO_PCRHR */
# define PIO_PCMR_DSIZE_WORD (2 << PIO_PCMR_DSIZE_SHIFT) /* 32-bit data in PIO_PCRHR */
+
#define PIO_PCMR_ALWYS (1 << 9) /* Bit 9: Parallel Capture Mode Always Sampling */
#define PIO_PCMR_HALFS (1 << 10) /* Bit 10: Parallel Capture Mode Half Sampling */
#define PIO_PCMR_FRSTS (1 << 11) /* Bit 11: Parallel Capture Mode First Sample */
-/* PIO Parallel Capture Interrupt Enable, Disable, Mask, and Status Registers */
+/* PIO Parallel Capture Interrupt Enable, Disable, Mask,
+ * and Status Registers
+ */
#define PIOC_PCINT_DRDY (1 << 0) /* Bit 0: Parallel Capture Mode Data Ready Interrupt Enable */
#define PIOC_PCINT_OVRE (1 << 1) /* Bit 1: Parallel Capture Mode Overrun Error Interrupt Enable */
#define PIOC_PCINT_ENDRX (1 << 2) /* Bit 2: End of Reception Transfer Interrupt Enable */
#define PIOC_PCINT_RXBUFF (1 << 3) /* Bit 3: Reception Buffer Full Interrupt Enable */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM4S_PIO_H */
diff --git a/arch/arm/src/sam34/hardware/sam_acc.h b/arch/arm/src/sam34/hardware/sam_acc.h
index e1d8e3d..3bfae73 100644
--- a/arch/arm/src/sam34/hardware/sam_acc.h
+++ b/arch/arm/src/sam34/hardware/sam_acc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_acc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* ACC register offsets *****************************************************************/
+/* ACC register offsets *****************************************************/
#define SAM_ACC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_ACC_MR_OFFSET 0x0004 /* Mode Register */
@@ -46,7 +46,7 @@
#define SAM_ACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_ACC_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
-/* ACC register addresses **************************************************************/
+/* ACC register addresses ***************************************************/
#define SAM_ACC_CR (SAM_ACC_BASE+SAM_ACC_CR_OFFSET)
#define SAM_ACC_MR (SAM_ACC_BASE+SAM_ACC_MR_OFFSET)
@@ -58,7 +58,7 @@
#define SAM_ACC_WPMR (SAM_ACC_BASE+SAM_ACC_WPMR_OFFSET)
#define SAM_ACC_WPSR (SAM_ACC_BASE+SAM_ACC_WPSR_OFFSET
-/* ACC register bit definitions ********************************************************/
+/* ACC register bit definitions *********************************************/
/* Control Register */
@@ -76,9 +76,11 @@
# define ACC_MR_SELMINUS_AD1 (5 << ACC_MR_SELMINUS_SHIFT) /* Select AD1 */
# define ACC_MR_SELMINUS_AD2 (6 << ACC_MR_SELMINUS_SHIFT) /* Select AD2 */
# define ACC_MR_SELMINUS_AD3 (7 << ACC_MR_SELMINUS_SHIFT) /* Select AD3 */
+
#define ACC_MR_SELPLUS_SHIFT (4) /* Bits 4-6: Selection for plus comparator input */
#define ACC_MR_SELPLUS_MASK (7 << ACC_MR_SELPLUS_SHIFT)
# define ACC_MR_SELPLUS_AD(n) ((uint32_t)(n) << ACC_MR_SELPLUS_SHIFT) /* Select and, n=0-7 */
+
# define ACC_MR_SELPLUS_AD0 (0 << ACC_MR_SELPLUS_SHIFT) /* Select AD0 */
# define ACC_MR_SELPLUS_AD1 (1 << ACC_MR_SELPLUS_SHIFT) /* Select AD1 */
# define ACC_MR_SELPLUS_AD2 (2 << ACC_MR_SELPLUS_SHIFT) /* Select AD2 */
@@ -87,17 +89,21 @@
# define ACC_MR_SELPLUS_AD5 (5 << ACC_MR_SELPLUS_SHIFT) /* Select AD5 */
# define ACC_MR_SELPLUS_AD6 (6 << ACC_MR_SELPLUS_SHIFT) /* Select AD6 */
# define ACC_MR_SELPLUS_AD7 (7 << ACC_MR_SELPLUS_SHIFT) /* Select AD7 */
+
#define ACC_MR_ACEN (1 << 8) /* Bit 8: Analog comparator enable */
#define ACC_MR_EDGETYP_SHIFT (9) /* Bits 9-10: Edge type */
#define ACC_MR_EDGETYP_MASK (3 << ACC_MR_EDGETYP_SHIFT)
# define ACC_MR_EDGETYP_RISING (0 << ACC_MR_EDGETYP_SHIFT) /* Only rising edge of comparator output */
# define ACC_MR_EDGETYP_FALLING (1 << ACC_MR_EDGETYP_SHIFT) /* Falling edge of comparator output */
# define ACC_MR_EDGETYP_ANY (2 << ACC_MR_EDGETYP_SHIFT) /* Any edge of comparator output */
+
#define ACC_MR_INV (1 << 12) /* Bit 12: Invert comparator output */
#define ACC_MR_SELFS (1 << 13) /* Bit 13: Selection of fault source */
#define ACC_MR_FE (1 << 14) /* Bit 14: Fault enable */
-/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status */
+/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
+ * and Interrupt Status
+ */
#define ACC_INT_CE (1 << 0) /* Bit 0: Comparison edge interrupt */
@@ -123,16 +129,16 @@
#define ACC_WPSR_WPROTERR (1 << 0) /* Bit 0: Write protection error */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ACC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_adc.h b/arch/arm/src/sam34/hardware/sam_adc.h
index 15b99b0..68b782d 100644
--- a/arch/arm/src/sam34/hardware/sam_adc.h
+++ b/arch/arm/src/sam34/hardware/sam_adc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_adc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
-/* General definitions ******************************************************************/
+ ****************************************************************************/
+
+/* General definitions ******************************************************/
#define SAM_ADC_NCHANNELS 8 /* 8 ADC Channels */
-/* ADC register offsets *****************************************************************/
+/* ADC register offsets *****************************************************/
#define SAM_ADC_CR_OFFSET 0x00 /* Control Register (Both) */
#define SAM_ADC_MR_OFFSET 0x04 /* Mode Register (Both) */
@@ -63,7 +64,7 @@
#define SAM_ADC12B_ACR_OFFSET 0x64 /* Analog Control Register (ADC12B only) */
#define SAM_ADC12B_EMR_OFFSET 0x68 /* Extended Mode Register (ADC12B only) */
-/* ADC register addresses ***************************************************************/
+/* ADC register addresses ***************************************************/
#define SAM_ADC12B_CR (SAM_ADC12B_BASE+SAM_ADC_CR_OFFSET)
#define SAM_ADC12B_MR (SAM_ADC12B_BASE+SAM_ADC_MR_OFFSET)
@@ -107,14 +108,18 @@
# define SAM_ADC_CDR6 (SAM_ADC_BASE+SAM_ADC_CDR6_OFFSET)
# define SAM_ADC_CDR7 (SAM_ADC_BASE+SAM_ADC_CDR7_OFFSET)
-/* ADC register bit definitions *********************************************************/
+/* ADC register bit definitions *********************************************/
-/* ADC12B Control Register and ADC(10B) Control Register common bit-field definitions */
+/* ADC12B Control Register and ADC(10B) Control Register common bit-field
+ * definitions
+ */
#define ADC_CR_SWRST (1 << 0) /* Bit 0: Software Reset */
#define ADC_CR_START (1 << 1) /* Bit 1: Start Conversion */
-/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field definitions */
+/* ADC12B Mode Register and ADC(10B) Mode Register common bit-field
+ * definitions
+ */
#define ADC_MR_TRGEN (1 << 0) /* Bit 0: Trigger Enable */
#define ADC_MR_TRGSEL_SHIFT (1) /* Bits 1-3: Trigger Selection */
@@ -135,8 +140,9 @@
#define ADC_MR_SHTIM_MASK (15 << ADC_MR_SHTIM_SHIFT)
# define ADC_MR_SHTIM(n) ((uint32_t)(n) << ADC_MR_SHTIM_SHIFT)
-/* ADC12B Channel Enable Register, ADC12B Channel Disable Register, ADC12B Channel
- * Status Register, ADC(10B) Channel Enable Register, ADC(10B) Channel Disable Register,
+/* ADC12B Channel Enable Register, ADC12B Channel Disable Register,
+ * ADC12B Channel Status Register, ADC(10B) Channel Enable Register,
+ * ADC(10B) Channel Disable Register,
* and ADC(10B) Channel Status Register common bit-field definitions
*/
@@ -168,9 +174,10 @@
#define ADC12B_EMR_OFFMSTIME_MASK (0xff << ADC12B_EMR_OFFMSTIME_SHIFT)
# define ADC12B_EMR_OFFMSTIME(n) ((uint32_t)(n) << ADC12B_EMR_OFFMSTIME_SHIFT)
-/* ADC12B Status Register , ADC12B Interrupt Enable Register, ADC12B Interrupt
- * Disable Register, ADC12B Interrupt Mask Register, ADC(10B) Status Register,
- * ADC(10B) Interrupt Enable Register, ADC(10B) Interrupt Disable Register, and
+/* ADC12B Status Register , ADC12B Interrupt Enable Register,
+ * ADC12B Interrupt Disable Register, ADC12B Interrupt Mask Register,
+ * ADC(10B) Status Register, ADC(10B) Interrupt Enable Register,
+ * ADC(10B) Interrupt Disable Register, and
* ADC(10B) Interrupt Mask Register common bit-field definitions
*/
@@ -217,16 +224,16 @@
#define ADC10B_CDR_DATA_SHIFT (0) /* Bits 0-9: Converted Data */
#define ADC10B_CDR_DATA_MASK (0x1ff << ADC10B_CDR_DATA_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_ADC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_aes.h b/arch/arm/src/sam34/hardware/sam_aes.h
index 56c4180..cde72ae 100644
--- a/arch/arm/src/sam34/hardware/sam_aes.h
+++ b/arch/arm/src/sam34/hardware/sam_aes.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_aes.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* AES register offsets *****************************************************************/
+/* AES register offsets *****************************************************/
#define SAM_AES_CR_OFFSET 0x0000 /* Control Register */
#define SAM_AES_MR_OFFSET 0x0004 /* Mode Register */
@@ -65,7 +65,7 @@
#define SAM_AES_IVR3_OFFSET 0x006c /* Initialization Vector Register 3 */
/* 0x0070-0x00fc: Reserved */
-/* AES register addresses ***************************************************************/
+/* AES register addresses ***************************************************/
#define SAM_AES_CR (SAM_AES_BASE+SAM_AES_CR_OFFSET)
#define SAM_AES_MR (SAM_AES_BASE+SAM_AES_MR_OFFSET)
@@ -94,7 +94,7 @@
#define SAM_AES_IVR2 (SAM_AES_BASE+SAM_AES_IVR2_OFFSET)
#define SAM_AES_IVR3 (SAM_AES_BASE+SAM_AES_IVR3_OFFSET)
-/* AES register bit definitions ********************************************************/
+/* AES register bit definitions *********************************************/
/* Control Register */
@@ -113,11 +113,13 @@
# define AES_MR_SMOD_MANUAL (0 << AES_MR_SMOD_SHIFT) /* Manual Mode */
# define AES_MR_SMOD_AUTO (1 << AES_MR_SMOD_SHIFT) /* Auto Mode */
# define AES_MR_SMOD_IDATR0 (2 << AES_MR_SMOD_SHIFT) /* AES_IDATAR0 access only Auto Mode */
+
#define AES_MR_KEYSIZE_SHIFT (10) /* Bits 10-11: Key Size */
#define AES_MR_KEYSIZE_MASK (2 << AES_MR_KEYSIZE_SHIFT)
# define AES_MR_KEYSIZE_AES128 (0 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 128 bits */
# define AES_MR_KEYSIZE_AES192 (1 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 192 bits */
# define AES_MR_KEYSIZE_AES256 (2 << AES_MR_KEYSIZE_SHIFT) /* AES Key Size is 256 bits */
+
#define AES_MR_OPMOD_SHIFT (12) /* Bits 12-14: Operation Mode */
#define AES_MR_OPMOD_MASK (7 << AES_MR_OPMOD_SHIFT)
# define AES_MR_OPMOD_ECB (0 << AES_MR_OPMOD_SHIFT) /* ECB: Electronic Code Book mode */
@@ -125,6 +127,7 @@
# define AES_MR_OPMOD_OFB (2 << AES_MR_OPMOD_SHIFT) /* OFB: Output Feedback mode */
# define AES_MR_OPMOD_CFB (3 << AES_MR_OPMOD_SHIFT) /* CFB: Cipher Feedback mode */
# define AES_MR_OPMOD_CTR (4 << AES_MR_OPMOD_SHIFT) /* CTR: Counter mode (16-bit counter) */
+
#define AES_MR_LOD (1 << 15) /* Bit 15: Last Output Data Mode */
#define AES_MR_CFBS_SHIFT (16) /* Bits 16-18: Cipher Feedback Data Size */
#define AES_MR_CFBS_MASK (7 << AES_MR_CFBS_SHIFT)
@@ -133,11 +136,14 @@
# define AES_MR_CFBS_32BIT (2 << AES_MR_CFBS_SHIFT) /* 32-bit */
# define AES_MR_CFBS_16BIT (3 << AES_MR_CFBS_SHIFT) /* 16-bit */
# define AES_MR_CFBS_8BIT (4 << AES_MR_CFBS_SHIFT) /* 8-bit */
+
#define AES_MR_CKEY_SHIFT (20) /* Bits 20-23: Key */
#define AES_MR_CKEY_MASK (15 << AES_MR_CKEY_SHIFT)
# define AES_MR_CKEY (14 << AES_MR_CKEY_SHIFT)
-/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
+/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
+ * and Interrupt Status Register
+ */
#define AES_INT_DATRDY (1 << 0) /* Bit 0: Data Ready Interrupt */
#define AES_INT_URAD (1 << 8) /* Bit 8: Unspecified Register Access Detection Interrupt */
@@ -154,19 +160,21 @@
# define AES_ISR_URAT_WORRDACC (5 << AES_ISR_URAT_SHIFT) /* WRONLY register read access */
/* Key Word Register 0-7 (32-bit value) */
+
/* Input Data Register 0-7 (32-bit value) */
+
/* Initialization Vector Register 0-7 (32-bit value) */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AES_H */
diff --git a/arch/arm/src/sam34/hardware/sam_afec.h b/arch/arm/src/sam34/hardware/sam_afec.h
index 2399b29..cafb4e6 100644
--- a/arch/arm/src/sam34/hardware/sam_afec.h
+++ b/arch/arm/src/sam34/hardware/sam_afec.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_afec.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
-/* General definitions ******************************************************************/
+ ****************************************************************************/
+
+/* General definitions ******************************************************/
#define SAM_ADC_NCHANNELS 16 /* 16 ADC Channels */
-/* AFEC register offsets ****************************************************************/
+/* AFEC register offsets ****************************************************/
#define SAM_AFEC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_AFEC_MR_OFFSET 0x0004 /* Mode Register */
@@ -73,7 +74,7 @@
/* 0x0fc Reserved */
/* 0x0100-0x0124 Reserved for PDC */
-/* AFEC register addresses **************************************************************/
+/* AFEC register addresses **************************************************/
#define SAM_AFEC0_CR (SAM_AFEC0_BASE+SAM_AFEC_CR_OFFSET)
#define SAM_AFEC0_MR (SAM_AFEC0_BASE+SAM_AFEC_MR_OFFSET)
@@ -129,7 +130,7 @@
#define SAM_AFEC1_WPMR (SAM_AFEC1_BASE+SAM_AFEC_WPMR_OFFSET)
#define SAM_AFEC1_WPSR (SAM_AFEC1_BASE+SAM_AFEC_WPSR_OFFSET)
-/* AFEC register bit definitions *******************************************************/
+/* AFEC register bit definitions ********************************************/
/* Control Register */
@@ -148,6 +149,7 @@
# define AFEC_MR_TRGSEL_TIOA2 (3 << AFEC_MR_TRGSEL_SHIFT) /* TIOA2 */
# define AFEC_MR_TRGSEL_PWM0 (4 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */
# define AFEC_MR_TRGSEL_PWM1 (5 << AFEC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */
+
#define AFEC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define AFEC_MR_FWUP (1 << 6) /* Bit 6: Fast Wake Up */
#define AFEC_MR_FREERUN (1 << 7) /* Bit 7: Free Run Mode */
@@ -172,12 +174,14 @@
# define AFEC_MR_STARTUP_832 (13 << AFEC_MR_STARTUP_SHIFT) /* 832 periods of ADCClock */
# define AFEC_MR_STARTUP_896 (14 << AFEC_MR_STARTUP_SHIFT) /* 896 periods of ADCClock */
# define AFEC_MR_STARTUP_960 (15 << AFEC_MR_STARTUP_SHIFT) /* 960 periods of ADCClock */
+
#define AFEC_MR_SETTLING_SHIFT (20) /* Bits 20-21: Analog Settling Time */
#define AFEC_MR_SETTLING_MASK (15 << AFEC_MR_SETTLING_SHIFT)
# define AFEC_MR_SETTLING_3 (0 << AFEC_MR_SETTLING_SHIFT) /* 3 periods of ADCClock */
# define AFEC_MR_SETTLING_5 (1 << AFEC_MR_SETTLING_SHIFT) /* 5 periods of ADCClock */
# define AFEC_MR_SETTLING_9 (2 << AFEC_MR_SETTLING_SHIFT) /* 9 periods of ADCClock */
# define AFEC_MR_SETTLING_17 (3 << AFEC_MR_SETTLING_SHIFT) /* 17 periods of ADCClock */
+
#define AFEC_MR_ANACH (1 << 23) /* Bit 23: Analog Change */
#define AFEC_MR_TRACKTIM_SHIFT (24) /* Bits 24-27: Tracking Time */
#define AFEC_MR_TRACKTIM_MASK (15 << AFEC_MR_TRACKTIM_SHIFT)
@@ -195,6 +199,7 @@
# define AFEC_EMR_CMPMODE_HIGH (1 << AFEC_EMR_CMPMODE_SHIFT) /* Event when higher than high window threshold */
# define AFEC_EMR_CMPMODE_IN (2 << AFEC_EMR_CMPMODE_SHIFT) /* Event when in comparison window */
# define AFEC_EMR_CMPMODE_OUT (3 << AFEC_EMR_CMPMODE_SHIFT) /* Event when out of comparison window */
+
#define AFEC_EMR_CMPSEL_SHIFT (3) /* Bit 3-7: Comparison Selected Channel */
#define AFEC_EMR_CMPSEL_MASK (31 << AFEC_EMR_CMPSEL_SHIFT)
# define AFEC_EMR_CMPSEL(n) ((uint32_t)(n) << AFEC_EMR_CMPSEL_SHIFT)
@@ -210,6 +215,7 @@
# define AFEC_EMR_RES_OSR16 (3 << AFEC_EMR_RES_SHIFT) /* 14-bit resolution, AFEC sample rate divided by 16 (averaging) */
# define AFEC_EMR_RES_OSR64 (4 << AFEC_EMR_RES_SHIFT) /* 15-bit resolution, AFEC sample rate divided by 64 (averaging) */
# define AFEC_EMR_RES_OSR256 (5 << AFEC_EMR_RES_SHIFT) /* 16-bit resolution, AFEC sample rate divided by 256 (averaging) */
+
#define AFEC_EMR_TAG (1 << 24) /* Bit 24: TAG of the AFEC_LDCR register */
#define AFEC_EMR_STM (1 << 25) /* Bit 25: Single Trigger Mode */
@@ -301,7 +307,9 @@
#define AFEC_LCDR_CHANB_SHIFT (24) /* Bits 24-27: Channel number */
#define AFEC_LCDR_CHANB_MASK (15 << AFEC_LCDR_CHANB_SHIFT)
-/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Registers */
+/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
+ * and Interrupt Status Registers
+ */
#define AFEC_INT_EOC(n) (1 << (n))
# define AFEC_INT_EOC0 (1 << 0) /* Bit 0: End of Conversion 0 */
@@ -415,7 +423,9 @@
#define AFEC_CGR_GAIN15_MASK (3 << AFEC_CGR_GAIN15_SHIFT)
# define AFEC_CGR_GAIN15(v) ((uint32_t)(v) << AFEC_CGR_GAIN15_SHIFT)
-/* Channel Calibration DC Offset Register (Used in Automatic Calibration Procedure) */
+/* Channel Calibration DC Offset Register
+ * (Used in Automatic Calibration Procedure)
+ */
#define AFEC_CDOR_OFF(n) (1 << (n))
# define AFEC_CDOR_OFF0 (1 << 0) /* Bit 0: Offset for channel 0 */
@@ -507,16 +517,16 @@
#define AFEC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define AFEC_WPSR_WPVSRC_MASK (0x0000ffff << AFEC_WPSR_WPVSRC_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_AFEC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_can.h b/arch/arm/src/sam34/hardware/sam_can.h
index e9b1611..7992716 100644
--- a/arch/arm/src/sam34/hardware/sam_can.h
+++ b/arch/arm/src/sam34/hardware/sam_can.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_can.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
#define SAM_CAN_NMBOXES 8 /* 8 Mailboxes */
#define SAM_CAN_MBOX(n) (n)
@@ -45,7 +45,7 @@
#define SAM_CAN_MBOX6 6
#define SAM_CAN_MBOX7 7
-/* CAN register offsets *****************************************************************/
+/* CAN register offsets *****************************************************/
#define SAM_CAN_MR_OFFSET 0x0000 /* Mode Register */
#define SAM_CAN_IER_OFFSET 0x0004 /* Interrupt Enable Register */
@@ -58,10 +58,13 @@
#define SAM_CAN_ECR_OFFSET 0x0020 /* Error Counter Register */
#define SAM_CAN_TCR_OFFSET 0x0024 /* Transfer Command Register */
#define SAM_CAN_ACR_OFFSET 0x0028 /* Abort Command Register */
+
/* 0x002c-0x00e0: Reserved */
#define SAM_CAN_WPMR_OFFSET 0x00e4 /* Write Protect Mode Register */
#define SAM_CAN_WPSR_OFFSET 0x00e8 /* Write Protect Status Register */
+
/* 0x00eC-0x01fc: Reserved */
+
/* Mailbox Registers */
#define SAM_CAN_MBOX_OFFSET(n) (0x0200+((n) << 5))
@@ -74,7 +77,7 @@
#define SAM_CAN_MDH_OFFSET 0x0018 /* Mailbox Data High Register */
#define SAM_CAN_MCR_OFFSET 0x001c /* Mailbox Control Register */
-/* CAN register addresses ***************************************************************/
+/* CAN register addresses ***************************************************/
#define SAM_CAN0_MR (SAM_CAN0_BASE+SAM_CAN_MR_OFFSET)
#define SAM_CAN0_IER (SAM_CAN0_BASE+SAM_CAN_IER_OFFSET)
@@ -128,7 +131,7 @@
#define SAM_CAN1_MDH(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MDH_OFFSET)
#define SAM_CAN1_MCR(n) (SAM_CAN1_MBOX_BASE(n)+SAM_CAN_MCR_OFFSET)
-/* CAN register bit definitions *********************************************************/
+/* CAN register bit definitions *********************************************/
/* Mode Register */
@@ -144,6 +147,7 @@
/* Interrupt Enable, Interrupt Disable, Interrupt Mask and Status Register */
#define CAN_INT_MB(n) (1 << (n)) /* Bit n: Mailbox n Interrupt */
+
#define CAN_INT_ERRA (1 << 16) /* Bit 16: Error Active Mode Interrupt */
#define CAN_INT_WARN (1 << 17) /* Bit 17: Warning Limit Interrupt */
#define CAN_INT_ERRP (1 << 18) /* Bit 18: Error Passive Mode Interrupt */
@@ -179,7 +183,7 @@
#define CAN_BR_BRP_SHIFT (16) /* Bits 16-22: Baudrate Prescaler */
#define CAN_BR_BRP_MASK (127 << CAN_BR_BRP_SHIFT)
# define CAN_BR_BRP(n) ((uint32_t)(n) << CAN_BR_BRP_SHIFT)
-#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode
+#define CAN_BR_SMP (1 << 24) /* Bit 24: Sampling Mode */
/* Timer Register */
@@ -277,6 +281,7 @@
#define CAN_MSR_MMI (1 << 24) /* Bit 24: Mailbox Message Ignored */
/* Mailbox Data Low Register (32-bit value) */
+
/* Mailbox Data High Register (32-bit value) */
/* Mailbox Control Register */
@@ -288,16 +293,16 @@
#define CAN_MCR_MACR (1 << 22) /* Bit 22: Abort Request for Mailbox n */
#define CAN_MCR_MTCR (1 << 23) /* Bit 23: Mailbox Transfer Command */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CAN_H */
diff --git a/arch/arm/src/sam34/hardware/sam_chipid.h b/arch/arm/src/sam34/hardware/sam_chipid.h
index 1c7ca43..cea2114 100644
--- a/arch/arm/src/sam34/hardware/sam_chipid.h
+++ b/arch/arm/src/sam34/hardware/sam_chipid.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_chipid.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,35 +16,35 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* CHIPID register offsets **************************************************************/
+/* CHIPID register offsets **************************************************/
#define SAM_CHIPID_CIDR 0x00 /* Chip ID Register */
#define SAM_CHIPID_EXID 0x04 /* Chip ID Extension Register */
-/* CHIPID register addresses ************************************************************/
+/* CHIPID register addresses ************************************************/
#define SAM_CHIPID_CIDR (SAM_CHIPID_BASE+SAM_CHIPID_CIDR)
#define SAM_CHIPID_EXID (SAM_CHIPID_BASE+SAM_CHIPID_EXID)
-/* CHIPID register bit definitions ******************************************************/
+/* CHIPID register bit definitions ******************************************/
#define CHIPID_CIDR_VERSION_SHIFT (0) /* Bits 0-4: Version of the Device */
#define CHIPID_CIDR_VERSION_MASK (0x1f << CHIPID_CIDR_VERSION_SHIFT)
@@ -57,6 +57,7 @@
# define CHIPID_CIDR_EPROC_ARM926EJS (5 << CHIPID_CIDR_EPROC_SHIFT) /* ARM926EJ-S */
# define CHIPID_CIDR_EPROC_CORTEXA5 (6 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-A5 */
# define CHIPID_CIDR_EPROC_CORTEXM4 (7 << CHIPID_CIDR_EPROC_SHIFT) /* Cortex-M4 */
+
#define CHIPID_CIDR_NVPSIZ_SHIFT (8) /* Bits 8-11: Nonvolatile Program Memory Size */
#define CHIPID_CIDR_NVPSIZ_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
# define CHIPID_CIDR_NVPSIZ_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
@@ -69,6 +70,7 @@
# define CHIPID_CIDR_NVPSIZ_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */
# define CHIPID_CIDR_NVPSIZ_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
# define CHIPID_CIDR_NVPSIZ_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
+
#define CHIPID_CIDR_NVPSIZ2_SHIFT (12) /* Bits 12-15: Nonvolatile Program Memory Size */
#define CHIPID_CIDR_NVPSIZ2_MASK (15 << CHIPID_CIDR_NVPSIZ_SHIFT)
# define CHIPID_CIDR_NVPSIZ2_NONE (0 << CHIPID_CIDR_NVPSIZ_SHIFT) /* None */
@@ -81,6 +83,7 @@
# define CHIPID_CIDR_NVPSIZ2_512KB (10 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 512K bytes */
# define CHIPID_CIDR_NVPSIZ2_1MB (12 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 1024K bytes */
# define CHIPID_CIDR_NVPSIZ2_2MB (14 << CHIPID_CIDR_NVPSIZ_SHIFT) /* 2048K bytes */
+
#define CHIPID_CIDR_SRAMSIZ_SHIFT (16) /* Bits 16-19: Internal SRAM Size */
#define CHIPID_CIDR_SRAMSIZ_MASK (15 << CHIPID_CIDR_SRAMSIZ_SHIFT)
# define CHIPID_CIDR_SRAMSIZ_48KB (0 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 48K bytes */
@@ -101,6 +104,7 @@
# define CHIPID_CIDR_SRAMSIZ_256KB (13 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 256K bytes */
# define CHIPID_CIDR_SRAMSIZ_96KB (14 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 96K bytes */
# define CHIPID_CIDR_SRAMSIZ_512KB (15 << CHIPID_CIDR_SRAMSIZ_SHIFT) /* 512K bytes */
+
#define CHIPID_CIDR_ARCH_SHIFT (20) /* Bits 20-27: Architecture Identifier */
#define CHIPID_CIDR_ARCH_MASK (0xff << CHIPID_CIDR_ARCH_SHIFT)
# define CHIPID_CIDR_ARCH_AT91SAM9XX (0x19 << CHIPID_CIDR_ARCH_SHIFT) /* AT91SAM9xx Series */
@@ -144,6 +148,7 @@
# define CHIPID_CIDR_ARCH_SAM4LB (0xb1 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxB Series */
# define CHIPID_CIDR_ARCH_SAM4LC (0xb2 << CHIPID_CIDR_ARCH_SHIFT) /* SAM4LxC Series */
# define CHIPID_CIDR_ARCH_AT75CXX (0xf0 << CHIPID_CIDR_ARCH_SHIFT) /* AT75Cxx Series */
+
#define CHIPID_CIDR_NVPTYP_SHIFT (28) /* Bits 28-30: Nonvolatile Program Memory Type */
#define CHIPID_CIDR_NVPTYP_MASK (7 << CHIPID_CIDR_NVPTYP_SHIFT)
# define CHIPID_CIDR_NVPTYP_ROM (0 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM */
@@ -151,6 +156,7 @@
# define CHIPID_CIDR_NVPTYP_SRAM (4 << CHIPID_CIDR_NVPTYP_SHIFT) /* SRAM emulating ROM */
# define CHIPID_CIDR_NVPTYP_EFLASH (2 << CHIPID_CIDR_NVPTYP_SHIFT) /* Embedded Flash Memory */
# define CHIPID_CIDR_NVPTYP_REFLASH (3 << CHIPID_CIDR_NVPTYP_SHIFT) /* ROM and Embedded Flash Memory */
+
#define CHIPID_CIDR_EXT (1 << 31) /* Bit 31: Extension Flag */
/* Chip ID Extension Register (32-bit value for SAM3U and SAM4S) */
@@ -170,16 +176,16 @@
# define CHIPID_EXID_PACKAGE_144PIN (5 << CHIPID_EXID_PACKAGE_SHIFT) /* 144-pin package */
#endif
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CHIPID_H */
diff --git a/arch/arm/src/sam34/hardware/sam_cmcc.h b/arch/arm/src/sam34/hardware/sam_cmcc.h
index 470b7fa..b44bd4a 100644
--- a/arch/arm/src/sam34/hardware/sam_cmcc.h
+++ b/arch/arm/src/sam34/hardware/sam_cmcc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_cmcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,27 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
-/* This information is available in the Cache Type Register. How every, it is more
- * efficient if we do not to do the decoding on each cache access.
+ ****************************************************************************/
+
+/* This information is available in the Cache Type Register.
+ * How ever, it is more efficient if we do not to do the decoding on each
+ * cache access.
*
* CacheSize = CacheLineSize * NCacheLines * NWays
* CacheAddressRange = CacheLineSize * NCacheLines = CacheSize / NWays
@@ -46,7 +48,7 @@
# define CMCC_NWAYS 4
#endif
-/* CMCC register offsets ****************************************************************/
+/* CMCC register offsets ****************************************************/
#define SAM_CMCC_TYPE_OFFSET 0x0000 /* Cache Type Register */
#define SAM_CMCC_CFG_OFFSET 0x0004 /* Cache Configuration Register */
@@ -61,7 +63,7 @@
#define SAM_CMCC_MSR_OFFSET 0x0034 /* Cache Monitor Status Register */
/* 0x0038-0x00fc Reserved */
-/* CMCC register addresses **************************************************************/
+/* CMCC register addresses **************************************************/
#define SAM_CMCC_TYPE (SAM_CMCC_BASE+SAM_CMCC_TYPE_OFFSET)
#define SAM_CMCC_CFG (SAM_CMCC_BASE+SAM_CMCC_CFG_OFFSET)
@@ -74,7 +76,7 @@
#define SAM_CMCC_MCTRL (SAM_CMCC_BASE+SAM_CMCC_MCTRL_OFFSET)
#define SAM_CMCC_MSR (SAM_CMCC_BASE+SAM_CMCC_MSR_OFFSET)
-/* CMCC register bit definitions ********************************************************/
+/* CMCC register bit definitions ********************************************/
/* Cache Type Register */
@@ -89,6 +91,7 @@
# define CMCC_TYPE_WAYNUM_ARCH2WAY (1 << CMCC_TYPE_WAYNUM_SHIFT) /* 2-WAY set associative */
# define CMCC_TYPE_WAYNUM_ARCH4WAY (2 << CMCC_TYPE_WAYNUM_SHIFT) /* 4-WAY set associative */
# define CMCC_TYPE_WAYNUM_ARCH8WAY (3 << CMCC_TYPE_WAYNUM_SHIFT) /* 8-WAY set associative */
+
#define CMCC_TYPE_LCKDOWN (1 << 7) /* Bit 7: Lock Down Supported */
#define CMCC_TYPE_CSIZE_SHIFT (8) /* Bits 8-10: Cache Size */
#define CMCC_TYPE_CSIZE_MASK (7 << CMCC_TYPE_CSIZE_SHIFT)
@@ -96,6 +99,7 @@
# define CMCC_TYPE_CSIZE_2KB (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */
# define CMCC_TYPE_CSIZE_4KB (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */
# define CMCC_TYPE_CSIZE_8KB (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */
+
#define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Line Size */
#define CMCC_TYPE_CLSIZE_MASK (7 << CMCC_TYPE_CLSIZE_SHIFT)
# define CMCC_TYPE_CLSIZE_4B (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */
@@ -150,16 +154,16 @@
/* Cache Monitor Status Register -- 32-bit event count */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_CMCC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_dacc.h b/arch/arm/src/sam34/hardware/sam_dacc.h
index 96a445a..cdd8476 100644
--- a/arch/arm/src/sam34/hardware/sam_dacc.h
+++ b/arch/arm/src/sam34/hardware/sam_dacc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_dacc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* DACC register offsets *****************************************************************/
+/* DACC register offsets ****************************************************/
#define SAM_DACC_CR_OFFSET 0x0000 /* Control Register */
#define SAM_DACC_MR_OFFSET 0x0004 /* Mode Register */
@@ -50,7 +50,7 @@
#define SAM_DACC_WPMR_OFFSET 0x00e4 /* Write Protect Mode register */
#define SAM_DACC_WPSR_OFFSET 0x00e8 /* Write Protect Status register */
-/* DACC register addresses **************************************************************/
+/* DACC register addresses **************************************************/
#define SAM_DACC_CR (SAM_DACC_BASE+SAM_DACC_CR_OFFSET)
#define SAM_DACC_MR (SAM_DACC_BASE+SAM_DACC_MR_OFFSET)
@@ -66,7 +66,7 @@
#define SAM_DACC_WPMR (SAM_DACC_BASE+SAM_DACC_WPMR_OFFSET)
#define SAM_DACC_WPSR (SAM_DACC_BASE+SAM_DACC_WPSR_OFFSET)
-/* DACC register bit definitions ********************************************************/
+/* DACC register bit definitions ********************************************/
/* Control Register */
@@ -83,6 +83,7 @@
# define DACC_MR_TRGSEL_TIO2 (3 << DACC_MR_TRGSEL_SHIFT) /* TIO Output of the TC Channel 2 */
# define DACC_MR_TRGSEL_PWM0 (4 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 0 */
# define DACC_MR_TRGSEL_PWM1 (5 << DACC_MR_TRGSEL_SHIFT) /* PWM Event Line 1 */
+
#define DACC_MR_WORD (1 << 4) /* Bit 4: Word Transfer */
#define DACC_MR_SLEEP (1 << 5) /* Bit 5: Sleep Mode */
#define DACC_MR_FASTWKUP (1 << 6) /* Bit 6: Fast Wake up Mode */
@@ -92,13 +93,17 @@
#define DACC_MR_USERSEL_MASK (3 << DACC_MR_USERSEL_SHIFT)
# define DACC_MR_USERSEL_CHAN0 (0 << DACC_MR_USERSEL_SHIFT) /* Channel 0 */
# define DACC_MR_USERSEL_CHAN1 (1 << DACC_MR_USERSEL_SHIFT) /* Channel 1 */
+
#define DACC_MR_TAG (1 << 20) /* Bit 20: Tag Selection Mode */
#define DACC_MR_MAXS (1 << 21) /* Bit 21: Max Speed Mode */
#define DACC_MR_CLKDIV (1 << 22) /* Bit 22: Clock Divider */
+
# define DACC_MR_CLKDIV_2 (0) /* DAC clock is MCK divided by 2 */
# define DACC_MR_CLKDIV_4 DACC_MR_CLKDIV /* DAC clock is MCK divided by 4 */
+
#define DACC_MR_STARTUP_SHIFT (24) /* Bits 24-29: Startup Time Select */
#define DACC_MR_STARTUP_MASK (63 << DACC_MR_STARTUP_SHIFT)
+
# define DACC_MR_STARTUP_0 (0 << DACC_MR_STARTUP_SHIFT) /* 0 periods of DACClock */
# define DACC_MR_STARTUP_8 (1 << DACC_MR_STARTUP_SHIFT) /* 8 periods of DACClock */
# define DACC_MR_STARTUP_16 (2 << DACC_MR_STARTUP_SHIFT) /* 16 periods of DACClock */
@@ -171,7 +176,9 @@
/* Conversion Data Register -- 32-bit data */
-/* Interrupt Enable, Interrupt Disable, Interrupt Mask, and Interrupt Status Register */
+/* Interrupt Enable, Interrupt Disable, Interrupt Mask,
+ * and Interrupt Status Register
+ */
#define DACC_INT_TXRDY (1 << 0) /* Bit 0: Transmit Ready Interrupt */
#define DACC_INT_EOC (1 << 1) /* Bit 1: End of Conversion Interrupt Flag */
@@ -201,16 +208,16 @@
#define DACC_WPSR_WPROTADDR_SHIFT (8) /* Bits 8-15: Write protection error address */
#define DACC_WPSR_WPROTADDR_MASK (0xff << DACC_WPSR_WPROTADDR_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DACC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_dmac.h b/arch/arm/src/sam34/hardware/sam_dmac.h
index 5661aca..1e279d9 100644
--- a/arch/arm/src/sam34/hardware/sam_dmac.h
+++ b/arch/arm/src/sam34/hardware/sam_dmac.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_dmac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* DMAC register offsets ****************************************************************/
+/* DMAC register offsets ****************************************************/
/* Global Registers */
@@ -52,6 +52,7 @@
#define SAM_DMAC_CHDR_OFFSET 0x002c /* DMAC Channel Handler Disable Register */
#define SAM_DMAC_CHSR_OFFSET 0x0030 /* DMAC Channel Handler Status Register */
/* 0x034-0x38: Reserved */
+
/* DMA channel registers */
#define SAM_DMACHAN_OFFSET(n) (0x003c+((n)*0x28))
@@ -68,7 +69,7 @@
#define SAM_DMACHAN_CTRLA_OFFSET 0x000c /* DMAC Channel Control A Register */
#define SAM_DMACHAN_CTRLB_OFFSET 0x0010 /* DMAC Channel Control B Register */
#define SAM_DMACHAN_CFG_OFFSET 0x0014 /* DMAC Channel Configuration Register */
- /* 0x18-0x24: Reserved */
+ /* 0x18-0x24: Reserved */
/* More Global Registers */
@@ -77,7 +78,7 @@
# define SAM_DMAC_WPSR_OFFSET 0x01e8 /* DMAC Write Protect Status Register DMAC_WPSR */
#endif
-/* DMAC register addresses **************************************************************/
+/* DMAC register addresses **************************************************/
/* Global Registers */
@@ -146,7 +147,7 @@
# define SAM_DMAC_WPSR (SAM_DMAC_BASE+SAM_DMAC_WPSR_OFFSET)
#endif
-/* DMAC register bit definitions ********************************************************/
+/* DMAC register bit definitions ********************************************/
/* Global Registers */
@@ -236,10 +237,14 @@
# define DMAC_LAST_DLAST2 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST2_SHIFT)
# define DMAC_LAST_DLAST3 (1 << (DMAC_LAST_DLAST_SHIFT+DMAC_LAST3_SHIFT)
-/* DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Enable Register,
- * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Disable Register,
- * DMAC Error, Buffer Transfer and Chained Buffer Transfer Interrupt Mask Register, and
- * DMAC Error, Buffer Transfer and Chained Buffer Transfer Status Register common
+/* DMAC Error, Buffer Transfer and Chained Buffer
+ * Transfer Interrupt Enable Register,
+ * DMAC Error, Buffer Transfer and Chained Buffer
+ * Transfer Interrupt Disable Register,
+ * DMAC Error, Buffer Transfer and Chained Buffer
+ * Transfer Interrupt Mask Register, and
+ * DMAC Error, Buffer Transfer and Chained Buffer
+ * Transfer Status Register common
* bit field definitions
*/
@@ -344,10 +349,22 @@
# define DMAC_CHSR_STAL3 (1 << (DMAC_CHSR_STAL_SHIFT+3))
/* DMA channel registers */
-/* DMAC Channel n [n = 0..3] Source Address Register -- 32-bit address*/
-/* DMAC Channel n [n = 0..3] Destination Address Register -- 32-bit address*/
-/* DMAC Channel n [n = 0..3] Descriptor Address Register -- 32-bit address*/
-/* DMAC Channel n [n = 0..3] Control A Register */
+
+/* DMAC Channel n [n = 0..3]
+ * Source Address Register -- 32-bit address
+ */
+
+/* DMAC Channel n [n = 0..3]
+ * Destination Address Register -- 32-bit address
+ */
+
+/* DMAC Channel n [n = 0..3]
+ * Descriptor Address Register -- 32-bit address
+ */
+
+/* DMAC Channel n [n = 0..3]
+ * Control A Register
+ */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -395,6 +412,7 @@
# define DMACHAN_CTRLB_FC_M2P (1 << DMACHAN_CTRLB_FC_SHIFT) /* Memory-to-Peripheral */
# define DMACHAN_CTRLB_FC_P2M (2 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Memory */
# define DMACHAN_CTRLB_FC_P2P (3 << DMACHAN_CTRLB_FC_SHIFT) /* Peripheral-to-Peripheral */
+
#define DMACHAN_CTRLB_SRCINCR_SHIFT (24) /* Bits 24-25 */
#define DMACHAN_CTRLB_SRCINCR_MASK (3 << DMACHAN_CTRLB_SRCINCR_SHIFT)
# define DMACHAN_CTRLB_SRCINCR_INCR (0 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Incrementing address */
@@ -402,6 +420,7 @@
# define DMACHAN_CTRLB_SRCINCR_DECR (1 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Decrementing address */
# endif
# define DMACHAN_CTRLB_SRCINCR_FIXED (2 << DMACHAN_CTRLB_SRCINCR_SHIFT) /* Fixed address */
+
#define DMACHAN_CTRLB_DSTINCR_SHIFT (28) /* Bits 28-29 */
#define DMACHAN_CTRLB_DSTINCR_MASK (3 << DMACHAN_CTRLB_DSTINCR_SHIFT)
# define DMACHAN_CTRLB_DSTINCR_INCR (0 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Incrementing address */
@@ -409,6 +428,7 @@
# define DMACHAN_CTRLB_DSTINCR_DECR (1 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Decrementing address */
# endif
# define DMACHAN_CTRLB_DSTINCR_FIXED (2 << DMACHAN_CTRLB_DSTINCR_SHIFT) /* Fixed address */
+
#define DMACHAN_CTRLB_IEN (1 << 30) /* Bit 30: Clear sets BTC[n] flag in EBCISR */
/* DMAC Channel n [n = 0..3] Configuration Register */
@@ -453,7 +473,7 @@
# define DMAC_WPSR_WPVSRC_MASK (0xffff << DMAC_WPSR_WPVSRC_SHIFT)
#endif
-/* DMA Hardware interface numbers *******************************************************/
+/* DMA Hardware interface numbers *******************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U)
@@ -496,9 +516,9 @@
#endif
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
/* DMA multi buffer transfer link list entry structure */
@@ -511,12 +531,12 @@ struct dma_linklist_s
uint32_t next; /* Next descriptor address */
};
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_DMAC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_eefc.h b/arch/arm/src/sam34/hardware/sam_eefc.h
index b606450..ed87938 100644
--- a/arch/arm/src/sam34/hardware/sam_eefc.h
+++ b/arch/arm/src/sam34/hardware/sam_eefc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_eefc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,32 +16,32 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* EEFC register offsets ****************************************************************/
+/* EEFC register offsets ****************************************************/
#define SAM_EEFC_FMR_OFFSET 0x00 /* EEFC Flash Mode Register */
#define SAM_EEFC_FCR_OFFSET 0x04 /* EEFC Flash Command Register */
#define SAM_EEFC_FSR_OFFSET 0x08 /* EEFC Flash Status Register */
#define SAM_EEFC_FRR_OFFSET 0x0c /* EEFC Flash Result Register */
-/* EEFC register addresses **************************************************************/
+/* EEFC register addresses **************************************************/
#define SAM_EEFC_FMR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FMR_OFFSET)
#define SAM_EEFC_FCR(n) (SAM_EEFCN_BASE(n)+SAM_EEFC_FCR_OFFSET)
@@ -60,7 +60,8 @@
# define SAM_EEFC1_FRR (SAM_EEFC1_BASE+SAM_EEFC_FRR_OFFSET)
#endif
-/* EEFC register bit definitions ********************************************************/
+/* EEFC register bit definitions ********************************************/
+
/* EEFC Flash Mode Register */
#define EEFC_FMR_FRDY (1 << 0) /* Bit 0: Ready Interrupt Enable */
@@ -135,16 +136,16 @@
/* EEFC Flash Result Register -- 32-bit value */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EEFC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_emac.h b/arch/arm/src/sam34/hardware/sam_emac.h
index 32fa773..72e5c7b 100644
--- a/arch/arm/src/sam34/hardware/sam_emac.h
+++ b/arch/arm/src/sam34/hardware/sam_emac.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_emac.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,22 +16,23 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_EMAC_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "hardware/sam_memorymap.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* EMAC Register Offsets ************************************************************/
+ ****************************************************************************/
+
+/* EMAC Register Offsets ****************************************************/
#define SAM_EMAC_NCR_OFFSET 0x0000 /* Network Control Register */
#define SAM_EMAC_NCFGR_OFFSET 0x0004 /* Network Configuration Register */
@@ -71,6 +72,7 @@
#define SAM_EMAC_SAMB1_OFFSET 0x00c8 /* Specific Address 1 Mask Bottom [31:0] Register */
#define SAM_EMAC_SAMT1_OFFSET 0x00cc /* Specific Address 1 Mask Top [47:32] Register */
/* 0x00fc: Reserved */
+
/* Statistics registers */
#define SAM_EMAC_OTLO_OFFSET 0x0100 /* Octets Transmitted [31:0] Register */
@@ -137,7 +139,7 @@
#define SAM_EMAC_PEFRN_OFFSET 0x01fc /* PTP Peer Event Frame Received Nanoseconds */
/* 0x0280-0x0298: Reserved */
-/* EMAC Register Addresses **********************************************************/
+/* EMAC Register Addresses **************************************************/
#define SAM_EMAC_NCR (SAM_EMAC_BASE+SAM_EMAC_NCR_OFFSET)
#define SAM_EMAC_NCFGR (SAM_EMAC_BASE+SAM_EMAC_NCFGR_OFFSET)
@@ -240,7 +242,7 @@
#define SAM_EMAC_PEFRS (SAM_EMAC_BASE+SAM_EMAC_PEFRS_OFFSET)
#define SAM_EMAC_PEFRN (SAM_EMAC_BASE+SAM_EMAC_PEFRN_OFFSET)
-/* EMAC Register Bit Definitions ****************************************************/
+/* EMAC Register Bit Definitions ********************************************/
/* Network Control Register */
@@ -282,6 +284,7 @@
# define EMAC_NCFGR_RXBUFO_1 (1 << EMAC_NCFGR_RXBUFO_SHIFT) /* One-byte offset from RX buffer start */
# define EMAC_NCFGR_RXBUFO_2 (2 << EMAC_NCFGR_RXBUFO_SHIFT) /* Two-byte offset from RX buffer start */
# define EMAC_NCFGR_RXBUFO_3 (3 << EMAC_NCFGR_RXBUFO_SHIFT) /* Three-byte offset fromRX buffer start */
+
#define EMAC_NCFGR_LFERD (1 << 16) /* Bit 16: Length Field Error Frame Discard */
#define EMAC_NCFGR_RFCS (1 << 17) /* Bit 17: Remove FCS */
#define EMAC_NCFGR_CLK_SHIFT (18) /* Bits 18-20: MDC clock divider */
@@ -292,9 +295,11 @@
# define EMAC_NCFGR_CLK_DIV48 (3 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 48 (MCK up to 120 MHz) */
# define EMAC_NCFGR_CLK_DIV64 (4 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 64 (MCK up to 160 MHz) */
# define EMAC_NCFGR_CLK_DIV96 (5 << EMAC_NCFGR_CLK_SHIFT) /* MCK divided by 96 (MCK up to 240 MHz) */
+
#define EMAC_NCFGR_DBW_SHIFT (21) /* Bit 21-22: Data Bus Width */
#define EMAC_NCFGR_DBW_MASK (3 << EMAC_NCFGR_DBW_SHIFT)
# define EMAC_NCFGR_DBW_ZERO (0 << EMAC_NCFGR_DBW_SHIFT) /* Must be zero */
+
#define EMAC_NCFGR_DCPF (1 << 23) /* Bit 23: Disable Copy of Pause Frames */
#define EMAC_NCFGR_RXCOEN (1 << 24) /* Bit 24: Receive Checksum Offload Enable */
#define EMAC_NCFGR_EFRHD (1 << 25) /* Bit 25: Enable Frames Received in Half Duplex */
@@ -316,10 +321,11 @@
#define EMAC_DCFGR_FBLDO_SHIFT (0) /* Bits 0-4: Fixed Burst Length for DMA Data Operations */
#define EMAC_DCFGR_FBLDO_MASK (31 << EMAC_DCFGR_FBLDO_SHIFT)
-# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */
-# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */
-# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */
+# define EMAC_DCFGR_FBLDO_SINGLE (1 << EMAC_DCFGR_FBLDO_SHIFT) /* Always use SINGLE AHB bursts */
+# define EMAC_DCFGR_FBLDO_INCR4 (4 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR4 AHB bursts */
+# define EMAC_DCFGR_FBLDO_INCR8 (8 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR8 AHB bursts */
# define EMAC_DCFGR_FBLDO_INCR16 (16 << EMAC_DCFGR_FBLDO_SHIFT) /* Attempt to use INCR16 AHB bursts */
+
#define EMAC_DCFGR_ESMA (1 << 6) /* Bit 6: Endian Swap Mode Enable for Management Descriptor Accesses */
#define EMAC_DCFGR_ESPA (1 << 7) /* Bit 7: Endian Swap Mode Enable for Packet Data Accesses */
#define EMAC_DCFGR_TXCOEN (1 << 11) /* Bit 11: Transmitter Checksum Generation Offload Enable */
@@ -352,7 +358,9 @@
#define EMAC_RSR_RXOVR (1 << 2) /* Bit 2: Receive Overrun */
#define EMAC_RSR_HNO (1 << 3) /* Bit 3: HRESP Not OK */
-/* Interrupt Status Register (ISR), Interrupt Enable Register (IER), Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR) */
+/* Interrupt Status Register (ISR), Interrupt Enable Register (IER),
+ * Interrupt Disable Register (IDR) and Interrupt Mask Register (IMR)
+ */
#define EMAC_INT_MFS (1 << 0) /* Bit 0: Management Frame Sent */
#define EMAC_INT_RCOMP (1 << 1) /* Bit 1: Receive Complete */
@@ -412,24 +420,29 @@
#define EMAC_TPQ_MASK (0x0000ffff) /* Bits 0-15: Transmit Pause Quantum */
/* Hash Register Bottom [31:0] Register (LS 32-bit hash address) */
+
/* Hash Register Top [63:32] Register (MS 32-bit hash address) */
/* Specific Address 1 Bottom [31:0] Register (LS 32-bit address) */
+
/* Specific Address 1 Top [47:32] Register */
#define EMAC_SAT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
/* Specific Address 2 Bottom [31:0] Register (LS 32-bit address) */
+
/* Specific Address 2 Top [47:32] Register */
#define EMAC_SAT2_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
/* Specific Address 3 Bottom [31:0] Register (LS 32-bit address) */
+
/* Specific Address 3 Top [47:32] Register */
#define EMAC_SAT3_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
/* Specific Address 4 Bottom [31:0] Register (LS 32-bit address) */
+
/* Specific Address 4 Top [47:32] Register */
#define EMAC_SAT4_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of the destination address */
@@ -461,6 +474,7 @@
#define EMAC_TPFCP_PQ_MASK (0xff << EMAC_TPFCP_PQ_SHIFT)
/* Specific Address 1 Mask Bottom [31:0] Register (LS 32-bit address) */
+
/* Specific Address 1 Mask Top [47:32] Register (MS 16-bit address) */
#define EMAC_SAMT1_MASK (0x0000ffff) /* Bits 0-15: Bits 32-47 of Specific Address 1 Mask */
@@ -517,11 +531,13 @@
/* PTP/1588 Timer Registers */
/* 1588 Timer Sync Strobe Seconds Register (32-bit timer value) */
+
/* 1588 Timer Sync Strobe Nanoseconds Register (30-bit timer value) */
#define EMAC_TSSN_MASK (0x3fffffff) /* Bit 0-29: Value Timer Nanoseconds Register Capture */
/* 1588 Timer Seconds Register (32-bit timer value) */
+
/* 1588 Timer Nanoseconds Register (30-bit timer value) */
#define EMAC_TN_MASK (0x3fffffff) /* Bit 0-29: Timer Count in Nanoseconds */
@@ -546,31 +562,35 @@
# define EMAC_TI_NIT(n) ((uint32_t)(n) << EMAC_TI_NIT_SHIFT)
/* PTP Event Frame Transmitted Seconds (32-bit timer value) */
+
/* PTP Event Frame Transmitted Nanoseconds (30-bit timer value) */
#define EMAC_EFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* PTP Event Frame Received Seconds (32-bit timer value) */
+
/* PTP Event Frame Received Nanoseconds (30-bit timer value) */
#define EMAC_EFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* PTP Peer Event Frame Transmitted Seconds (32-bit timer value) */
+
/* PTP Peer Event Frame Transmitted Nanoseconds (30-bit timer value) */
#define EMAC_PEFTN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
/* PTP Peer Event Frame Received Seconds (32-bit timer value) */
+
/* PTP Peer Event Frame Received Nanoseconds (30-bit timer value) */
#define EMAC_PEFRN_MASK (0x3fffffff) /* Bit 0-29: Register Update */
-/* Descriptors **********************************************************************/
+/* Descriptors **************************************************************/
/* Receive buffer descriptor: Address word */
-#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */
-#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
+#define EMACRXD_ADDR_OWNER (1 << 0) /* Bit 0: 1=Software owns; 0=EMAC owns */
+#define EMACRXD_ADDR_WRAP (1 << 1) /* Bit 1: Last descriptor in list */
#define EMACRXD_ADDR_MASK (0xfffffffc) /* Bits 2-31: Aligned buffer address */
/* Receive buffer descriptor: Control word */
@@ -587,20 +607,22 @@
#define EMACRXD_STA_VLPRIO_MASK (7 << EMACRXD_STA_VLANPRIO_SHIFT)
#define EMACRXD_STA_PRIODET (1 << 20) /* Bit 20: Priority tag detected */
#define EMACRXD_STA_VLANTAG (1 << 21) /* Bit 21: VLAN tag detected */
-#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */
+#define EMACRXD_STA_TYPEID_SHIFT (22) /* Bit 22-23: Specific address register */
#define EMACRXD_STA_TYPEID_MASK (3 << EMACRXD_STA_TYPEID_SHIFT)
# define EMACRXD_STA_TYPEID1 (0 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 1 match */
# define EMACRXD_STA_TYPEID2 (1 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 2 match */
# define EMACRXD_STA_TYPEID3 (2 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 3 match */
# define EMACRXD_STA_TYPEID4 (3 << EMACRXD_STA_TYPEID_SHIFT) /* Type ID register 4 match */
+
#define EMACRXD_STA_TYPEIDMATCH (1 << 24) /* Bit 24: Type ID register match found */
#define EMACRXD_STA_SNAP (1 << 24) /* Bit 24: Frame was SNAP encoded */
-#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */
+#define EMACRXD_STA_ADDR_SHIFT (25) /* Bit 25-26: Specific address register */
#define EMACRXD_STA_ADDR_MASK (3 << EMACRXD_STA_ADDR_SHIFT)
# define EMACRXD_STA_ADDR1 (0 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 1 match */
# define EMACRXD_STA_ADDR2 (1 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 2 match */
# define EMACRXD_STA_ADDR3 (2 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 3 match */
# define EMACRXD_STA_ADDR4 (3 << EMACRXD_STA_ADDR_SHIFT) /* Specific address register 4 match */
+
#define EMACRXD_STA_ADDRMATCH (1 << 27) /* Bit 27: Specific address match found */
/* Bit 28: Reserved */
#define EMACRXD_STA_UCAST (1 << 29) /* Bit 29: Unicast hash match */
@@ -608,6 +630,7 @@
#define EMACRXD_STA_BCAST (1 << 31) /* Bit 31: Global all ones broadcast address detected */
/* Transmit buffer descriptor: Address word (un-aligned, 32-bit address */
+
/* Transmit buffer descriptor: Control word */
#define EMACTXD_STA_BUFLEN_SHIFT (0) /* Bits 0-13: Length of buffer */
@@ -626,6 +649,7 @@
# define EMACTXD_STA_CHKERR_BADFRAG (5 << EMACTXD_STA_CHKERR_SHIFT) /* Unsupported fragmentation */
# define EMACTXD_STA_CHKERR_PKTTYPE (6 << EMACTXD_STA_CHKERR_SHIFT) /* Not TCP or UDP */
# define EMACTXD_STA_CHKERR_EPKT (7 << EMACTXD_STA_CHKERR_SHIFT) /* Premature end of packet */
+
/* Bits 23-25: Reserved */
#define EMACTXD_STA_LCOL (1 << 26) /* Bit 26: Late collision, transmit error detected */
#define EMACTXD_STA_TFC (1 << 27) /* Bit 27: Transmit frame corruption due to AHB error */
@@ -634,9 +658,10 @@
#define EMACTXD_STA_WRAP (1 << 30) /* Bit 30: Last descriptor in descriptor list */
#define EMACTXD_STA_USED (1 << 31) /* Bit 31: Zero for the EMAC to read from buffer */
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
+
/* Receive buffer descriptor */
struct emac_rxdesc_s
diff --git a/arch/arm/src/sam34/hardware/sam_gpbr.h b/arch/arm/src/sam34/hardware/sam_gpbr.h
index d02c9bd..05e98ad 100644
--- a/arch/arm/src/sam34/hardware/sam_gpbr.h
+++ b/arch/arm/src/sam34/hardware/sam_gpbr.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_gpbr.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* GPBR register offsets ****************************************************************/
+/* GPBR register offsets ****************************************************/
#define SAM_GPBR_OFFSET(n) ((n)<<2) /* General purpose back-up registers */
#define SAM_GPBR0_OFFSET 0x00
@@ -61,7 +61,7 @@
# define SAM_GPBR19_OFFSET 0x4c
#endif
-/* GPBR register addresses **************************************************************/
+/* GPBR register addresses **************************************************/
#define SAM_GPBR(n)) (SAM_GPBR_BASE+SAM_GPBR_OFFSET(n))
#define SAM_GPBR0 (SAM_GPBR_BASE+SAM_GPBR0_OFFSET)
@@ -88,20 +88,20 @@
# define SAM_GPBR19 (SAM_GPBR_BASE+SAM_GPBR19_OFFSET)
#endif
-/* GPBR register bit definitions ********************************************************/
+/* GPBR register bit definitions ********************************************/
/* All 32-bit values */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_GPBR_H */
diff --git a/arch/arm/src/sam34/hardware/sam_hsmci.h b/arch/arm/src/sam34/hardware/sam_hsmci.h
index 0bef7ce..006446a 100644
--- a/arch/arm/src/sam34/hardware/sam_hsmci.h
+++ b/arch/arm/src/sam34/hardware/sam_hsmci.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_hsmci.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
@@ -31,11 +31,11 @@
#include "hardware/sam_pdc.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* HSMCI register offsets ***************************************************************/
+/* HSMCI register offsets ***************************************************/
#define SAM_HSMCI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_HSMCI_MR_OFFSET 0x0004 /* Mode Register */
@@ -69,7 +69,7 @@
/* 0x0100-0x0124: Reserved for PCD registers */
#define SAM_HSMCI_FIFO_OFFSET 0x0200 /* 0x0200-0x3ffc FIFO Memory Aperture */
-/* HSMCI register addresses *************************************************************/
+/* HSMCI register addresses *************************************************/
#define SAM_HSMCI_CR (SAM_HSMCI_BASE+SAM_HSMCI_CR_OFFSET)
#define SAM_HSMCI_MR (SAM_HSMCI_BASE+SAM_HSMCI_MR_OFFSET)
@@ -112,7 +112,7 @@
# define SAM_HSMCI_PDC_PTSR (SAM_HSMCI_BASE+SAM_PDC_PTSR_OFFSET)
#endif
-/* HSMCI register bit definitions *******************************************************/
+/* HSMCI register bit definitions *******************************************/
/* HSMCI Control Register */
@@ -191,6 +191,7 @@
# define HSMCI_CMDR_RSPTYP_48BIT (1 << HSMCI_CMDR_RSPTYP_SHIFT) /* 48-bit response */
# define HSMCI_CMDR_RSPTYP_136BIT (2 << HSMCI_CMDR_RSPTYP_SHIFT) /* 136-bit response */
# define HSMCI_CMDR_RSPTYP_R1B (3 << HSMCI_CMDR_RSPTYP_SHIFT) /* R1b response type */
+
#define HSMCI_CMDR_SPCMD_SHIFT (8) /* Bits 8-10: Special Command */
#define HSMCI_CMDR_SPCMD_MASK (7 << HSMCI_CMDR_SPCMD_SHIFT)
# define HSMCI_CMDR_SPCMD_NORMAL (0 << HSMCI_CMDR_SPCMD_SHIFT) /* Not a special CMD */
@@ -201,6 +202,7 @@
# define HSMCI_CMDR_SPCMD_INTRESP (5 << HSMCI_CMDR_SPCMD_SHIFT) /* Interrupt response */
# define HSMCI_CMDR_SPCMD_BOOTOP (6 << HSMCI_CMDR_SPCMD_SHIFT) /* Boot Operation Request */
# define HSMCI_CMDR_SPCMD_BOOTEND (7 << HSMCI_CMDR_SPCMD_SHIFT) /* End Boot Operation */
+
#define HSMCI_CMDR_OPDCMD (1 << 11) /* Bit 11: Open Drain Command */
#define HSMCI_CMDR_MAXLAT (1 << 12) /* Bit 12: Max Latency for Command to Response */
#define HSMCI_CMDR_TRCMD_SHIFT (16) /* Bits 16-17: Transfer Command */
@@ -208,6 +210,7 @@
# define HSMCI_CMDR_TRCMD_NONE (0 << HSMCI_CMDR_TRCMD_SHIFT) /* No data transfer */
# define HSMCI_CMDR_TRCMD_START (1 << HSMCI_CMDR_TRCMD_SHIFT) /* Start data transfer */
# define HSMCI_CMDR_TRCMD_STOP (2 << HSMCI_CMDR_TRCMD_SHIFT) /* Stop data transfer */
+
#define HSMCI_CMDR_TRDIR (1 << 18) /* Bit 18: Transfer Direction */
# define HSMCI_CMDR_TRDIR_WRITE (0 << 18)
# define HSMCI_CMDR_TRDIR_READ (1 << 18)
@@ -218,11 +221,13 @@
# define HSMCI_CMDR_TRTYP_STREAM (2 << HSMCI_CMDR_TRTYP_SHIFT) /* MMC Stream */
# define HSMCI_CMDR_TRTYP_SDIOBYTE (4 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Byte */
# define HSMCI_CMDR_TRTYP_SDIOBLK (5 << HSMCI_CMDR_TRTYP_SHIFT) /* SDIO Block */
+
#define HSMCI_CMDR_IOSPCMD_SHIFT (24) /* Bits 24-25: SDIO Special Command */
#define HSMCI_CMDR_IOSPCMD_MASK (3 << HSMCI_CMDR_IOSPCMD_SHIFT)
# define HSMCI_CMDR_IOSPCMD_NORMAL (0 << HSMCI_CMDR_IOSPCMD_SHIFT) /* Not an SDIO Special Command */
# define HSMCI_CMDR_IOSPCMD_SUSP (1 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Suspend Command */
# define HSMCI_CMDR_IOSPCMD_RESUME (2 << HSMCI_CMDR_IOSPCMD_SHIFT) /* SDIO Resume Command */
+
#define HSMCI_CMDR_ATACS (1 << 26) /* Bit 26: ATA with Command Completion Signal */
#define HSMCI_CMDR_BOOTACK (1 << 27) /* Bit 27: Boot Operation Acknowledge */
@@ -252,11 +257,14 @@
# define HSMCI_CSTOR_CSTOMUL_1048576 (7 << HSMCI_CSTOR_CSTOMUL_SHIFT)
/* HSMCI Response Registers (32-bit data) */
+
/* HSMCI Receive Data Registers (32-bit data) */
+
/* HSMCI Transmit Data Registers (32-bit data) */
-/* HSMCI Status Register, HSMCI Interrupt Enable Register, HSMCI Interrupt Disable
- * Register, and HSMCI Interrupt Mask Register common bit-field definitions
+/* HSMCI Status Register, HSMCI Interrupt Enable Register,
+ * HSMCI Interrupt Disable Register, and HSMCI Interrupt Mask Register
+ * common bit-field definitions
*/
#define HSMCI_INT_CMDRDY (1 << 0) /* Bit 0: Command Ready */
@@ -336,16 +344,16 @@
#define HSMCI_WPSR_VSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define HSMCI_WPSR_VSRC_MASK (0xffff << HSMCI_WPSR_VSRC_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_HSMCI_H */
diff --git a/arch/arm/src/sam34/hardware/sam_matrix.h b/arch/arm/src/sam34/hardware/sam_matrix.h
index 6cde8c1..66058b4 100644
--- a/arch/arm/src/sam34/hardware/sam_matrix.h
+++ b/arch/arm/src/sam34/hardware/sam_matrix.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_matrix.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* MATRIX register offsets **************************************************************/
+/* MATRIX register offsets **************************************************/
#define SAM_MATRIX_MCFG_OFFSET(n) ((n)<<2)
#define SAM_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
@@ -110,7 +110,7 @@
#define SAM_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
/* 0x0110 - 0x01fc: Reserved */
-/* MATRIX register addresses ************************************************************/
+/* MATRIX register addresses ************************************************/
#define SAM_MATRIX_MCFG(n) (SAM_MATRIX_BASE+SAM_MATRIX_MCFG_OFFSET(n))
#define SAM_MATRIX_MCFG0 (SAM_MATRIX_BASE+SAM_MATRIX_MCFG0_OFFSET)
@@ -183,7 +183,7 @@
#define SAM_MATRIX_WPMR (SAM_MATRIX_BASE+SAM_MATRIX_WPMR_OFFSET)
#define SAM_MATRIX_WPSR (SAM_MATRIX_BASE+SAM_MATRIX_WPSR_OFFSET)
-/* MATRIX register bit definitions ******************************************************/
+/* MATRIX register bit definitions ******************************************/
/* Master Configuration Registers */
@@ -342,12 +342,12 @@
#define MATRIX_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define MATRIX_WPSR_WPVSRC_MASK (0xffff << MATRIX_WPSR_WPVSRC_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MATRIX_H */
diff --git a/arch/arm/src/sam34/hardware/sam_memorymap.h b/arch/arm/src/sam34/hardware/sam_memorymap.h
index a6f39fe..05f9e4b 100644
--- a/arch/arm/src/sam34/hardware/sam_memorymap.h
+++ b/arch/arm/src/sam34/hardware/sam_memorymap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_MEMORYMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include <arch/sam34/chip.h>
diff --git a/arch/arm/src/sam34/hardware/sam_pdc.h b/arch/arm/src/sam34/hardware/sam_pdc.h
index 60de492..a76cb96 100644
--- a/arch/arm/src/sam34/hardware/sam_pdc.h
+++ b/arch/arm/src/sam34/hardware/sam_pdc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pdc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PDC register offsets *****************************************************************/
+/* PDC register offsets *****************************************************/
#define SAM_PDC_RPR_OFFSET 0x100 /* Receive Pointer Register */
#define SAM_PDC_RCR_OFFSET 0x104 /* Receive Counter Register */
@@ -47,31 +47,37 @@
#define SAM_PDC_PTCR_OFFSET 0x120 /* Transfer Control Register */
#define SAM_PDC_PTSR_OFFSET 0x124 /* Transfer Status Register */
-/* PDC register addresses ***************************************************************/
+/* PDC register addresses ***************************************************/
-/* These 10 registers are mapped in the peripheral memory space at the same offset. */
+/* These 10 registers are mapped in the peripheral memory space at the same
+ * offset.
+ */
-/* PDC register bit definitions *********************************************************/
+/* PDC register bit definitions *********************************************/
/* Receive Pointer Register -- 32-bit address value */
+
/* Receive Counter Register -- 16-bit counter value */
#define PDC_RCR_RXCTR_SHIFT (0) /* Bits 0-15: Receive Counter Register */
#define PDC_RCR_RXCTR_MASK (0xffff << PDC_RCR_RXCTR_SHIFT)
/* Transmit Pointer Register -- 32-bit address value */
+
/* Transmit Counter Register -- 16-bit counter value */
#define PDC_TCR_TXCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Register */
#define PDC_TCR_TXCTR_MASK (0xffff << PDC_TCR_TXCTR_SHIFT)
/* Receive Next Pointer Register -- 32-bit address value */
+
/* Receive Next Counter Register -- 16-bit counter value */
#define PDC_RNCR_RXNCTR_SHIFT (0) /* Bits 0-15: Receive Next Counter */
#define PDC_RNCR_RXNCTR_MASK (0xffff << PDC_RNCR_RXNCTR_SHIFT)
/* Transmit Next Pointer Register -- 32-bit address value */
+
/* Transmit Next Counter Register -- 16-bit counter value */
#define PDC_TNCR_TXNCTR_SHIFT (0) /* Bits 0-15: Transmit Counter Next */
@@ -89,16 +95,16 @@
#define PDC_PTSR_RXTEN (1 << 0) /* Bit 0: Receiver Transfer Enable */
#define PDC_PTSR_TXTEN (1 << 8) /* Bit 8: Transmitter Transfer Enable */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PDC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_pinmap.h b/arch/arm/src/sam34/hardware/sam_pinmap.h
index 3b795eb..ebe448a 100644
--- a/arch/arm/src/sam34/hardware/sam_pinmap.h
+++ b/arch/arm/src/sam34/hardware/sam_pinmap.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PINMAP_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
diff --git a/arch/arm/src/sam34/hardware/sam_pmc.h b/arch/arm/src/sam34/hardware/sam_pmc.h
index e935372..2509d9d 100644
--- a/arch/arm/src/sam34/hardware/sam_pmc.h
+++ b/arch/arm/src/sam34/hardware/sam_pmc.h
@@ -1,4 +1,4 @@
-/********************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ********************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H
-/********************************************************************************************
+/****************************************************************************
* Included Files
- ********************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/********************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ********************************************************************************************/
+ ****************************************************************************/
-/* PMC register offsets *********************************************************************/
+/* PMC register offsets *****************************************************/
#define SAM_PMC_SCER_OFFSET 0x0000 /* System Clock Enable Register */
#define SAM_PMC_SCDR_OFFSET 0x0004 /* System Clock Disable Register */
@@ -56,7 +56,7 @@
defined(CONFIG_ARCH_CHIP_SAM3A)
# define SAM_PMC_CKGR_UCKR_OFFSET 0x001c /* UTMI Clock Register */
#endif
- /* 0x001c: Reserved (SAM4S)*/
+ /* 0x001c: Reserved (SAM4S) */
#define SAM_PMC_CKGR_MOR_OFFSET 0x0020 /* Main Oscillator Register */
#define SAM_PMC_CKGR_MCFR_OFFSET 0x0024 /* Main Clock Frequency Register */
#define SAM_PMC_CKGR_PLLAR_OFFSET 0x0028 /* PLLA Register */
@@ -64,7 +64,7 @@
#if defined(CONFIG_ARCH_CHIP_SAM4CM) || defined(CONFIG_ARCH_CHIP_SAM4S)
# define SAM_PMC_CKGR_PLLBR_OFFSET 0x002c /* PLLB Register */
#endif
- /* 0x002c: Reserved (SAM3U)*/
+ /* 0x002c: Reserved (SAM3U) */
#define SAM_PMC_MCKR_OFFSET 0x0030 /* Master Clock Register */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3A) || \
@@ -111,7 +111,7 @@
# define SAM_PMC_PMMR_OFFSET 0x0130 /* PLL Maximum Multiplier Value Register */
#endif
-/* PMC register addresses *******************************************************************/
+/* PMC register addresses ***************************************************/
#define SAM_PMC_SCER (SAM_PMC_BASE+SAM_PMC_SCER_OFFSET)
#define SAM_PMC_SCDR (SAM_PMC_BASE+SAM_PMC_SCDR_OFFSET)
@@ -182,10 +182,10 @@
# define SAM_PMC_PMMR (SAM_PMC_BASE+SAM_PMC_PMMR_OFFSET)
#endif
-/* PMC register bit definitions *************************************************************/
+/* PMC register bit definitions *********************************************/
-/* PMC System Clock Enable Register, PMC System Clock Disable Register, and PMC System
- * Clock Status Register common bit-field definitions
+/* PMC System Clock Enable Register, PMC System Clock Disable Register,
+ * and PMC System Clock Status Register common bit-field definitions
*/
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM4S)
@@ -207,8 +207,9 @@
# define PMC_CPKEY (0xa << 20)
#endif
-/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable Register, and PMC
- * Peripheral Clock Status Register common bit-field definitions.
+/* PMC Peripheral Clock Enable Register, PMC Peripheral Clock Disable
+ * Register, and PMC Peripheral Clock Status Register common bit-field
+ * definitions.
*/
#define PMC_PIDL(n) (1 << (n))
@@ -267,6 +268,7 @@
# define PMC_CKGR_MOR_MOSCRCF_4MHz (0 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 4MHz (default) */
# define PMC_CKGR_MOR_MOSCRCF_8MHz (1 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 8MHz */
# define PMC_CKGR_MOR_MOSCRCF_12MHz (2 << PMC_CKGR_MOR_MOSCRCF_SHIFT) /* Fast RC Osc is 12MHz */
+
#define PMC_CKGR_MOR_MOSCXTST_SHIFT (8) /* Bits 8-15: Main Crystal Oscillator Start-up Time */
#define PMC_CKGR_MOR_MOSCXTST_MASK (0xff << PMC_CKGR_MOR_MOSCXTST_SHIFT)
# define PMC_CKGR_MOR_MOSCXTST(n) ((uint32_t)(n) << PMC_CKGR_MOR_MOSCXTST_SHIFT)
@@ -317,6 +319,7 @@
# define PMC_CKGR_PLLBR_DIV_ZERO (0 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is 0 */
# define PMC_CKGR_PLLBR_DIV_BYPASS (1 << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider is bypassed (DIV=1) */
# define PMC_CKGR_PLLBR_DIV(n) ((n) << PMC_CKGR_PLLBR_DIV_SHIFT) /* Divider output is DIV=n, n=2..255 */
+
# define PMC_CKGR_PLLBR_COUNT_SHIFT (8) /* Bits 8-13: PLLA Counter */
# define PMC_CKGR_PLLBR_COUNT_MASK (63 << PMC_CKGR_PLLBR_COUNT_SHIFT)
# define PMC_CKGR_PLLBR_MUL_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
@@ -421,8 +424,8 @@
# define PMC_PCK_PRES_DIV32 (5 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 32 */
# define PMC_PCK_PRES_DIV64 (6 << PMC_PCK_PRES_SHIFT) /* Selected clock divided by 64 */
-/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status Register,
- * and PMC Interrupt Mask Register common bit-field definitions
+/* PMC Interrupt Enable Register, PMC Interrupt Disable Register, PMC Status
+ * Register, and PMC Interrupt Mask Register common bit-field definitions
*/
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
@@ -450,8 +453,8 @@
#define PMC_SR_CFDS (1 << 19) /* Bit 19: Clock Failure Detector Status (SR only) */
#define PMC_SR_FOS (1 << 20) /* Bit 20: Clock Failure Detector Fault Output Status (SR only) */
-/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register common bit-field
- * definitions
+/* PMC Fast Startup Mode Register and PMC Fast Startup Polarity Register
+ * common bit-field definitions
*/
#define PMC_FSTI(n) (1 << (n))
@@ -491,6 +494,7 @@
/* Fast Startup Polarity Register */
#define PMC_FSTP(n) (1 << (n)) /* Fast Startup Input Polarity n, n=0..15 */
+
# define PMC_FSTP0 (1 << 0) /* Bit 0: Fast Startup Input Polarity 0 */
# define PMC_FSTP1 (1 << 1) /* Bit 1: Fast Startup Input Polarity 1 */
# define PMC_FSTP2 (1 << 2) /* Bit 2: Fast Startup Input Polarity 2 */
@@ -526,7 +530,9 @@
#define PMC_WPSR_WPVSRC_MASK (0xffff << PMC_WPSR_WPVSRC_SHIFT)
/* Peripheral Clock Enable Register 1 */
+
/* Peripheral Clock Disable Register 1 */
+
/* Peripheral Clock Status Register 1 */
#if defined(CONFIG_ARCH_CHIP_SAM3X) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
@@ -567,6 +573,7 @@
# define PMC_PCR_DIV1 (0 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK */
# define PMC_PCR_DIV2 (1 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/2 */
# define PMC_PCR_DIV4 (2 < PMC_PCR_DIV_SHIFT) /* Peripheral clock is MCK/4 */
+
# define PMC_PCR_EN (1 << 28) /* Bit 28: Enable */
#endif
@@ -593,16 +600,16 @@
# define PMC_PMMR_MASK (0x7ff) /* Bits 0-10: PLLA Maximum Allowed Multiplier */
#endif
-/********************************************************************************************
+/****************************************************************************
* Public Types
- ********************************************************************************************/
+ ****************************************************************************/
-/********************************************************************************************
+/****************************************************************************
* Public Data
- ********************************************************************************************/
+ ****************************************************************************/
-/********************************************************************************************
- * Public Functions
- ********************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PMC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_pwm.h b/arch/arm/src/sam34/hardware/sam_pwm.h
index 5fe5850..a3a7e6f 100644
--- a/arch/arm/src/sam34/hardware/sam_pwm.h
+++ b/arch/arm/src/sam34/hardware/sam_pwm.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_pwm.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* PWM register offsets *****************************************************************/
+/* PWM register offsets *****************************************************/
#define SAM_PWM_CLK_OFFSET 0x000 /* PWM Clock Register */
#define SAM_PWM_ENA_OFFSET 0x004 /* PWM Enable Register */
@@ -91,6 +91,7 @@
#define SAM_PWM_WPSR_OFFSET 0x0e8 /* PWM Write Protect Status Register */
/* 0x100-0x128: Reserved for PDC registers */
/* 0x12c: Reserved */
+
/* PWM Comparison Registers */
#define SAM_PWMCMP_OFFSET(n) (0x130+((n)<<4))
@@ -138,7 +139,8 @@
#define SAM_PWMCMP7_VUPD_OFFSET 0x1a4 /* PWM Comparison 7 Value Update Register */
#define SAM_PWMCMP7_M_OFFSET 0x1a8 /* PWM Comparison 7 Mode Register */
#define SAM_PWMCMP7_MUPD_OFFSET 0x1ac /* PWM Comparison 7 Mode Update Register */
- /* 0x1b0-0x1fc: Reserved */
+ /* 0x1b0-0x1fc: Reserved */
+
/* PWM Channel Registers */
#define SAM_PWMCH_OFFSET(n) (0x200+((n)<< 5))
@@ -210,7 +212,7 @@
# define SAM_PWMCH3_CAEUPD_OFFSET 0x0468 /* PWM Channel 3 Additional Edge Update Register */
#endif
-/* PWM register addresses ***************************************************************/
+/* PWM register addresses ***************************************************/
#define SAM_PWM_CLK (SAM_PWM_BASE+SAM_PWM_CLK_OFFSET)
#define SAM_PWM_ENA (SAM_PWM_BASE+SAM_PWM_ENA_OFFSET)
@@ -388,7 +390,7 @@
# define SAM_PWMCH3_CAEUPD (SAM_PWMCH3_BASE2+SAM_PWMCH0_CAEUPD_OFFSET)
#endif
-/* PWM register bit definitions *********************************************************/
+/* PWM register bit definitions *********************************************/
/* PWM Clock Register */
@@ -410,6 +412,7 @@
# define PWM_CLK_PREA_MCKDIV256 (8 << PWM_CLK_PREA_SHIFT) /* MCK/256 */
# define PWM_CLK_PREA_MCKDIV512 (9 << PWM_CLK_PREA_SHIFT) /* MCK/512 */
# define PWM_CLK_PREA_MCKDIV1024 (10 << PWM_CLK_PREA_SHIFT) /* MCK/1024 */
+
#define PWM_CLK_DIVB_SHIFT (16) /* Bits 16-23: CLKB Divide Factor */
#define PWM_CLK_DIVB_MASK (0xff << PWM_CLK_DIVB_SHIFT)
# define PWM_CLK_DIVB_OFF (0 << PWM_CLK_DIVB_SHIFT)
@@ -429,7 +432,9 @@
# define PWM_CLK_PREB_MCKDIV512 (9 << PWM_CLK_PREB_SHIFT) /* MCK/512 */
# define PWM_CLK_PREB_MCKDIV1024 (10 << PWM_CLK_PREB_SHIFT) /* MCK/1024 */
-/* PWM Enable Register, PWM Disable Register, and PWM Status Register common bit-field definitions */
+/* PWM Enable Register, PWM Disable Register, and
+ * PWM Status Register common bit-field definitions
+ */
#define SAM_ENAB_CHID(n) (1 << ((n))
# define SAM_ENAB_CHID0 (1 << 0) /* Bit 0: Counter Event Channel 0 Interrupt */
@@ -437,8 +442,9 @@
# define SAM_ENAB_CHID2 (1 << 2) /* Bit 2: Counter Event Channel 2 Interrupt */
# define SAM_ENAB_CHID3 (1 << 3) /* Bit 3: Counter Event Channel 3 Interrupt */
-/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1, PWM Interrupt
- * Mask Register 1, and PWM Interrupt Status Register 1 common bit definitions
+/* PWM Interrupt Enable Register 1, PWM Interrupt Disable Register 1,
+ * PWM Interrupt Mask Register 1, and PWM Interrupt Status Register 1
+ * common bit definitions
*/
#define SAM_INT_CHID(n) (1 << (n))
@@ -464,6 +470,7 @@
# define PWM_SCM_UPDM_MANMAN (0 << PWM_SCM_UPDM_SHIFT) /* Manual write/manual update */
# define PWM_SCM_UPDM_MANAUTO (1 << PWM_SCM_UPDM_SHIFT) /* Manual write/automatic update */
# define PWM_SCM_UPDM_AUTOAUTO (2 << PWM_SCM_UPDM_SHIFT) /* Auto write/automatic update */
+
#define PWM_SCM_PTRM (1 << 20) /* Bit 20: PDC Transfer Request Mode */
#define PWM_SCM_PTRCS_SHIFT (21) /* Bits 21-23: PDC Transfer Request Comparison Selection */
#define PWM_SCM_PTRCS_MASK (7 << PWM_SCM_PTRCS_SHIFT)
@@ -488,7 +495,10 @@
#define PWM_SCUPUPD_MASK (15 << PWM_SCUPUPD_SHIFT)
# define PWM_SCUPUPD(n) ((uint32_t)(n) << PWM_SCUPUPD_SHIFT)
-/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2, PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2 common bit-field definitions */
+/* PWM Interrupt Enable Register 2, PWM Interrupt Disable Register 2,
+ * PWM Interrupt Mask Register 2, and PWM Interrupt Status Register 2
+ * common bit-field definitions
+ */
#define SAM_INT_WRDY (1 << 0) /* Bit 0: Write Ready Update Interrupt */
#define SAM_INT_ENDTX (1 << 1) /* Bit 1: PDC End of TX Buffer Interrupt */
@@ -513,10 +523,10 @@
# define SAM_INT_CMPU6 (1 << 22) /* Bit 22: Comparison 6 Update Interrupt */
# define SAM_INT_CMPU7 (1 << 23) /* Bit 23: Comparison 7 Update Interrupt */
-/* PWM Output Override Value Register, PWM Output Selection Register, PWM Output
- * Selection Set Register, PWM Output Selection Clear Register, PWM Output Selection
- * Set Update Register, and PWM Output Selection Clear Update Register common bit-field
- * definitions
+/* PWM Output Override Value Register, PWM Output Selection Register,
+ * PWM Output Selection Set Register, PWM Output Selection Clear Register,
+ * PWM Output Selection Set Update Register, and PWM Output Selection Clear
+ * Update Register common bit-field definitions
*/
#define PWM_OUT_OH(n) (1 << (n))
@@ -720,13 +730,17 @@
#define PWM_WPSR_WPVSRC_SHIFT (16) /* Bits 16-31: Write Protect Violation Source */
#define PWM_WPSR_WPVSRC_MASK (0xffff << PWM_WPSR_WPVSRC_SHIFT)
-/* PWM Comparison x Value Register and PWM Comparison x Value Update Register */
+/* PWM Comparison x Value Register and
+ * PWM Comparison x Value Update Register
+ */
#define PWMCMP_CV_SHIFT (0) /* Bits 0-23: Comparison x Value */
#define PWMCMP_CV_MASK (0x00ffffff << PWMCMP_CV_SHIFT)
#define PWMCMP_CVM (1 << 24) /* Bit 24: Comparison x Value Mode */
-/* PWM Comparison x Mode Register and PWM Comparison x Mode Update Register */
+/* PWM Comparison x Mode Register and
+ * PWM Comparison x Mode Update Register
+ */
#define PWMCMP_CEN (1 << 0) /* Bit 0: Comparison x Enable */
#define PWMCMP_CTR_SHIFT (4) /* Bits 4-7: Comparison x Trigger */
@@ -760,8 +774,9 @@
# define PWMCH_MR_CPRE_MCKDIV256 (8 << PWMCH_MR_CPRE_SHIFT) /* MCK/256 */
# define PWMCH_MR_CPRE_MCKDIV512 (9 << PWMCH_MR_CPRE_SHIFT) /* MCK/512 */
# define PWMCH_MR_CPRE_MCKDIV1024 (10 << PWMCH_MR_CPRE_SHIFT) /* MCK/1024 */
-# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /*CLKA */
+# define PWMCH_MR_CPRE_CLKA (11 << PWMCH_MR_CPRE_SHIFT) /* CLKA */
# define PWMCH_MR_CPRE_CLKB (12 << PWMCH_MR_CPRE_SHIFT) /* CLKB */
+
#define PWMCH_MR_CALG (1 << 8) /* Bit 8: Channel Alignment */
#define PWMCH_MR_CPOL (1 << 9) /* Bit 9: Channel Polarity */
#define PWMCH_MR_CES (1 << 10) /* Bit 10: Counter Event Selection */
@@ -774,12 +789,16 @@
#define PWMCH_MR_DTHI (1 << 17) /* Bit 17: Dead-Time PWMHx Output Inverted */
#define PWMCH_MR_DTLI (1 << 18) /* Bit 18: Dead-Time PWMLx Output Inverted */
-/* PWM Channel Duty Cycle Register and PWM Channel Duty Cycle Update Register common bit-field definitions */
+/* PWM Channel Duty Cycle Register and
+ * PWM Channel Duty Cycle Update Register common bit-field definitions
+ */
#define PWMCH_DTY_SHIFT (0) /* Bits 0-23: Channel Duty-Cycle */
#define PWMCH_DTY_MASK (0x00ffffff << PWMCH_DTY_SHIFT)
-/* PWM Channel Period Register and PWM Channel Period Update Register common bit-field definitions */
+/* PWM Channel Period Register and
+ * PWM Channel Period Update Register common bit-field definitions
+ */
#define PWMCH_PRD_SHIFT (0) /* Bits 0-23: Channel Period */
#define PWMCH_PRD_MASK (0x00ffffff << PWMCH_PRD_SHIFT)
@@ -789,7 +808,9 @@
#define PWMCH_CCNT_SHIFT (0) /* Bits 0-23: Channel Counter Register */
#define PWMCH_CCNT_MASK (0x00ffffff << PWMCH_CCNT_SHIFT)
-/* PWM Channel Dead Time Register and PWM Channel Dead Time Update Register common bit-field definitions */
+/* PWM Channel Dead Time Register and
+ * PWM Channel Dead Time Update Register common bit-field definitions
+ */
#define PWMCH_DTH_SHIFT (0) /* Bits 0-15: Dead-Time Value for PWMHx Output */
#define PWMCH_DTH_MASK (0xffff << PWMCH_DTH_SHIFT)
@@ -805,7 +826,9 @@
# define PWMCH_CMUPD_CPOLINVUP (1 << 13) /* Bit 13: Channel Polarity Inversion Update */
#endif
-/* PWM Channel Additional Edge Register and PWM Channel Additional Edge Update Register */
+/* PWM Channel Additional Edge Register and
+ * PWM Channel Additional Edge Update Register
+ */
#if defined(CONFIG_ARCH_CHIP_SAM4E)
# define PWMCH_CAE_ADEDGV_SHIFT (0) /* Bits 0-23: Channel Additional Edge Value */
@@ -818,16 +841,16 @@
# define PWMCH_CAE_ADEDGM_BOTH (2 << PWMCH_CAE_ADEDGM_SHIFT)
#endif
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_PWM_H */
diff --git a/arch/arm/src/sam34/hardware/sam_rstc.h b/arch/arm/src/sam34/hardware/sam_rstc.h
index c7769cc..63fb5c6 100644
--- a/arch/arm/src/sam34/hardware/sam_rstc.h
+++ b/arch/arm/src/sam34/hardware/sam_rstc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_rstc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* RSTC register offsets ****************************************************************/
+/* RSTC register offsets ****************************************************/
#define SAM_RSTC_CR_OFFSET 0x00 /* Control Register */
#define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */
@@ -44,7 +44,7 @@
# define SAM_RSTC_CPMR_OFFSET 0x0c /* Coprocessor Mode Register */
#endif
-/* RSTC register addresses **************************************************************/
+/* RSTC register addresses **************************************************/
#define SAM_RSTC_CR (SAM_RSTC_BASE+SAM_RSTC_CR_OFFSET)
#define SAM_RSTC_SR (SAM_RSTC_BASE+SAM_RSTC_SR_OFFSET)
@@ -54,7 +54,7 @@
# define SAM_RSTC_CPMR (SAM_RSTC_BASE+SAM_RSTC_CPMR_OFFSET)
#endif
-/* RSTC register bit definitions ********************************************************/
+/* RSTC register bit definitions ********************************************/
/* Reset Controller Control Register */
@@ -75,6 +75,7 @@
# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */
# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */
# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */
+
#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */
#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */
@@ -92,21 +93,21 @@
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
/* Coprocessor Mode Register */
-# define RSTC_CPMR_CPROCEN (1 << 0) /* Coprocessor (second processor) Enable */
-# define RSTC_CPMR_CPEREN (1 << 4) /* Coprocessor Peripheral Enable */
+# define RSTC_CPMR_CPROCEN (1 << 0) /* Coprocessor (second processor) Enable */
+# define RSTC_CPMR_CPEREN (1 << 4) /* Coprocessor Peripheral Enable */
# define RSTC_CPMR_CPKEY (0x5a << 24) /* Key */
#endif
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSTC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_rswdt.h b/arch/arm/src/sam34/hardware/sam_rswdt.h
index b6c0578..644bb18 100644
--- a/arch/arm/src/sam34/hardware/sam_rswdt.h
+++ b/arch/arm/src/sam34/hardware/sam_rswdt.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_rswdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,37 +16,38 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* RSWDT register offsets ***************************************************************/
+/* RSWDT register offsets ***************************************************/
#define SAM_RSWDT_CR_OFFSET 0x0000 /* Control Register */
#define SAM_RSWDT_MR_OFFSET 0x0004 /* Mode Register */
#define SAM_RSWDT_SR_OFFSET 0x0008 /* Status Register */
-/* RSWDT register addresses *************************************************************/
+/* RSWDT register addresses *************************************************/
#define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_RSWDT_CR_OFFSET)
#define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_RSWDT_MR_OFFSET)
#define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_RSWDT_SR_OFFSET)
-/* RSWDT register bit definitions *******************************************************/
+/* RSWDT register bit definitions *******************************************/
+
/* Watchdog Timer Control Register */
#define RSWDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
@@ -74,16 +75,16 @@
#define RSWDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
#define RSWDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RSWDT_H */
diff --git a/arch/arm/src/sam34/hardware/sam_rtc.h b/arch/arm/src/sam34/hardware/sam_rtc.h
index 11f2775..42d9444 100644
--- a/arch/arm/src/sam34/hardware/sam_rtc.h
+++ b/arch/arm/src/sam34/hardware/sam_rtc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_rtc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* RTC register offsets *****************************************************************/
+/* RTC register offsets *****************************************************/
#define SAM_RTC_CR_OFFSET 0x00 /* Control Register */
#define SAM_RTC_MR_OFFSET 0x04 /* Mode Register */
@@ -49,7 +49,7 @@
#define SAM_RTC_IMR_OFFSET 0x28 /* Interrupt Mask Register */
#define SAM_RTC_VER_OFFSET 0x2c /* Valid Entry Register */
-/* RTC register addresses ***************************************************************/
+/* RTC register addresses ***************************************************/
#define SAM_RTC_CR (SAM_RTC_BASE+SAM_RTC_CR_OFFSET)
#define SAM_RTC_MR (SAM_RTC_BASE+SAM_RTC_MR_OFFSET)
@@ -64,7 +64,7 @@
#define SAM_RTC_IMR (SAM_RTC_BASE+SAM_RTC_IMR_OFFSET)
#define SAM_RTC_VER (SAM_RTC_BASE+SAM_RTC_VER_OFFSET)
-/* RTC register bit definitions *********************************************************/
+/* RTC register bit definitions *********************************************/
/* RTC Control Register */
@@ -103,6 +103,7 @@
# define RTC_MR_OUT0_ALARM_TOGGLE (5 << RTC_MR_OUT0_SHIFT) /* Output toggles when alarm flag rises */
# define RTC_MR_OUT0_ALARM_FLAG (6 << RTC_MR_OUT0_SHIFT) /* Output is a copy of the alarm flag */
# define RTC_MR_OUT0_PROG_PULSE (7 << RTC_MR_OUT0_SHIFT) /* Duty cycle programmable pulse */
+
# define RTC_MR_OUT1_SHIFT (20) /* Bits 20-22: RTCOUT1 Output Source Selection */
# define RTC_MR_OUT1_MASK (7 << RTC_MR_OUT1_SHIFT)
# define RTC_MR_OUT1_NOWAVE (0 << RTC_MR_OUT1_SHIFT) /* No waveform, stuck at 0 */
@@ -113,6 +114,7 @@
# define RTC_MR_OUT1_ALARM_TOGGLE (5 << RTC_MR_OUT1_SHIFT) /* Output toggles when alarm flag rises */
# define RTC_MR_OUT1_ALARM_FLAG (6 << RTC_MR_OUT1_SHIFT) /* Output is a copy of the alarm flag */
# define RTC_MR_OUT1_PROG_PULSE (7 << RTC_MR_OUT1_SHIFT) /* Duty cycle programmable pulse */
+
# define RTC_MR_THIGH_SHIFT (24) /* Bits 24-26: High Duration of the Output Pulse */
# define RTC_MR_THIGH_MASK (7 << RTC_MR_THIGH_SHIFT)
# define RTC_MR_THIGH_31MS (0 << RTC_MR_THIGH_SHIFT) /* 31.2 ms */
@@ -123,6 +125,7 @@
# define RTC_MR_THIGH_22US (5 << RTC_MR_THIGH_SHIFT) /* 122 �s */
# define RTC_MR_THIGH_0US (6 << RTC_MR_THIGH_SHIFT) /* 30.5 �s */
# define RTC_MR_THIGH_15US (7 << RTC_MR_THIGH_SHIFT) /* 15.2 �s */
+
# define RTC_MR_TPERIOD_SHIFT (28) /* Bits 28-29: Period of the Output Pulse */
# define RTC_MR_TPERIOD_MASK (3 << RTC_MR_TPERIOD_SHIFT)
# define RTC_MR_TPERIOD_1S (0 << RTC_MR_TPERIOD_SHIFT) /* 1 second */
@@ -252,16 +255,16 @@
#define RTC_VER_NVTIMALR (1 << 2) /* Bit 2: Non-valid Time Alarm */
#define RTC_VER_NVCALALR (1 << 3) /* Bit 3: Non-valid Calendar Alarm */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_rtt.h b/arch/arm/src/sam34/hardware/sam_rtt.h
index 123e8fd..294c823 100644
--- a/arch/arm/src/sam34/hardware/sam_rtt.h
+++ b/arch/arm/src/sam34/hardware/sam_rtt.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_rtt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,39 +16,39 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* RTT register offsets *****************************************************************/
+/* RTT register offsets *****************************************************/
#define SAM_RTT_MR_OFFSET 0x00 /* Mode Register */
#define SAM_RTT_AR_OFFSET 0x04 /* Alarm Register */
#define SAM_RTT_VR_OFFSET 0x08 /* Value Register */
#define SAM_RTT_SR_OFFSET 0x0c /* Status Register */
-/* RTT register addresses ***************************************************************/
+/* RTT register addresses ***************************************************/
#define SAM_RTT_MR (SAM_RTT_BASE+SAM_RTT_MR_OFFSET)
#define SAM_RTT_AR (SAM_RTT_BASE+SAM_RTT_AR_OFFSET)
#define SAM_RTT_VR (SAM_RTT_BASE+SAM_RTT_VR_OFFSET)
#define SAM_RTT_SR (SAM_RTT_BASE+SAM_RTT_SR_OFFSET)
-/* RTT register bit definitions ********************************************************/
+/* RTT register bit definitions *********************************************/
/* Real-time Timer Mode Register */
@@ -65,6 +65,7 @@
#endif
/* Real-time Timer Alarm Register (32-bit alarm value) */
+
/* Real-time Timer Value Register (32-bit timer value) */
/* Real-time Timer Status Register */
@@ -72,16 +73,16 @@
#define RTT_SR_ALMS (1 << 0) /* Bit 0: Real-time Alarm Status */
#define RTT_SR_RTTINC (1 << 1) /* Bit 1: Real-time Timer Increment */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_RTT_H */
diff --git a/arch/arm/src/sam34/hardware/sam_smc.h b/arch/arm/src/sam34/hardware/sam_smc.h
index 92813ba..9ebf055 100644
--- a/arch/arm/src/sam34/hardware/sam_smc.h
+++ b/arch/arm/src/sam34/hardware/sam_smc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_smc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* SMC register offsets *****************************************************************/
+/* SMC register offsets *****************************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -107,7 +107,7 @@
# error Unrecognized SAM architecture
#endif
-/* SMC register addresses ***************************************************************/
+/* SMC register addresses ***************************************************/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -208,7 +208,7 @@
#define SAM_SMC_WPCR (SAM_SMC_BASE+SAM_SMC_WPCR_OFFSET)
#define SAM_SMC_WPSR (SAM_SMC_BASE+SAM_SMC_WPSR_OFFSET)
-/* SMC register bit definitions *********************************************************/
+/* SMC register bit definitions *********************************************/
/* SMC NFC Configuration Register */
@@ -220,6 +220,7 @@
# define SMC_CFG_PAGESIZE_1056 (1 << SMC_CFG_PAGESIZE_SHIFT) /* 1024 Bytes + 32 bytes spare */
# define SMC_CFG_PAGESIZE_2122 (2 << SMC_CFG_PAGESIZE_SHIFT) /* 2048 Bytes + 64 bytes spare */
# define SMC_CFG_PAGESIZE_4224 (3 << SMC_CFG_PAGESIZE_SHIFT) /* 4096 Bytes + 128 bytes spare */
+
# define SMC_CFG_WSPARE (1 << 8) /* Bit 8: Write Spare Area */
# define SMC_CFG_RSPARE (1 << 9) /* Bit 9: Read Spare Area */
# define SMC_CFG_EDGECTRL (1 << 12) /* Bit 12: Rising/Falling Edge Detection Control */
@@ -246,8 +247,9 @@
# define SMC_CTRL_NFCDIS (1 << 1) /* Bit 1: NAND Flash Controller Disable */
#endif
-/* SMC NFC Status Register, SMC NFC Interrupt Enable Register, SMC NFC Interrupt
- * Disable Register, and SMC NFC Interrupt Mask Register common bit-field definitions
+/* SMC NFC Status Register, SMC NFC Interrupt Enable Register,
+ * SMC NFC Interrupt Disable Register, and SMC NFC Interrupt Mask Register
+ * common bit-field definitions
*/
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
@@ -314,6 +316,7 @@
# define SMC_ECCMD_ECC_PAGESIZE_1056 (1 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 1024 Bytes + 32 bytes spare */
# define SMC_ECCMD_ECC_PAGESIZE_2112 (2 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 2048 Bytes + 64 bytes spare */
# define SMC_ECCMD_ECC_PAGESIZE_4224 (3 << SMC_ECCMD_ECC_PAGESIZE_SHIFT) /* 4096 Bytes + 128 bytes spare */
+
# define SMC_ECCMD_TYPCORREC_SHIFT (4) /* Bits 4-5: type of correction */
# define SMC_ECCMD_TYPCORREC_MASK (3 << SMC_ECCMD_TYPCORREC_SHIFT)
# define SMC_ECCMD_TYPCORREC_PAGE (0 << SMC_ECCMD_TYPCORREC_SHIFT) /* 1 bit correction for a page */
@@ -394,6 +397,7 @@
#endif
/* Registers for 1 ECC for a page of 512/1024/2048/4096 bytes */
+
/* SMC_ECC_PR0 */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
@@ -409,7 +413,9 @@
#endif
#endif
-/* Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word */
+/* Registers for 1 ECC per 512 bytes for a page of
+ * 512/2048/4096 bytes, 8-bit word
+ */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -421,7 +427,9 @@
# define SMC_ECCPR512_NPARITY_MASK (0xfff << SMC_ECCPR512_NPARITY_SHIFT)
#endif
-/* Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word */
+/* Registers for 1 ECC per 256 bytes for a page of
+ * 512/2048/4096 bytes, 8-bit word
+ */
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -535,7 +543,7 @@
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM4S) || \
defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMCCS_MODE_PMEN (1 << 24) /* Bit 24: Page Mode Enabled */
-# define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
+# define SMCCS_MODE_PS_SHIFT (28) /* Bits 28-29: Page Size */
# define SMCCS_MODE_PS_MASK (3 << SMCCS_MODE_PS_SHIFT)
# define SMCCS_MODE_PS_SIZE_4BYTES (0 << SMCCS_MODE_PS_SHIFT) /* 4 bytes */
# define SMCCS_MODE_PS_SIZE_8BYTES (1 << SMCCS_MODE_PS_SHIFT) /* 8 bytes */
@@ -553,6 +561,7 @@
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
# define SMC_OCMS_CSSE(n) (1 << ((n)+16)) /* Chip Select (n=0-3) Scrambling Enable */
+
# define SMC_OCMS_CS0SE (1 << 16) /* Bit 16: Chip Select 0 Scrambling Enable */
# define SMC_OCMS_CS1SE (1 << 17) /* Bit 17: Chip Select 1 Scrambling Enable */
# define SMC_OCMS_CS2SE (1 << 18) /* Bit 18: Chip Select 2 Scrambling Enable */
@@ -585,16 +594,16 @@
#define SMC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protection Violation Source */
#define SMC_WPSR_WPVSRC_MASK (0xffff << SMC_WPSR_WPVSRC_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SMC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_spi.h b/arch/arm/src/sam34/hardware/sam_spi.h
index b245654..e753781 100644
--- a/arch/arm/src/sam34/hardware/sam_spi.h
+++ b/arch/arm/src/sam34/hardware/sam_spi.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
-/* General definitions ******************************************************************/
+ ****************************************************************************/
+
+/* General definitions ******************************************************/
#define SAM_SPI_NCS 4 /* Four chip selects */
-/* SPI register offsets *****************************************************************/
+/* SPI register offsets *****************************************************/
#define SAM_SPI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_SPI_MR_OFFSET 0x0004 /* Mode Register */
@@ -62,7 +63,7 @@
#endif
/* 0x100-0x124 Reserved for PDC Registers */
-/* SPI register addresses ***************************************************************/
+/* SPI register addresses ***************************************************/
#define SAM_SPI0_CR (SAM_SPI0_BASE+SAM_SPI_CR_OFFSET) /* Control Register */
#define SAM_SPI0_MR (SAM_SPI0_BASE+SAM_SPI_MR_OFFSET) /* Mode Register */
@@ -104,7 +105,7 @@
# define SAM_SPI1_VERSION (SAM_SPI1_BASE+SAM_SPI_VERSION_OFFSET)
#endif
-/* SPI register bit definitions *********************************************************/
+/* SPI register bit definitions *********************************************/
/* SPI Control Register */
@@ -137,6 +138,7 @@
# define SPI_MR_PCS1 (1 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
# define SPI_MR_PCS2 (3 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
# define SPI_MR_PCS3 (7 << SPI_MR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
+
#define SPI_MR_DLYBCS_SHIFT (24) /* Bits 24-31: Delay Between Chip Selects */
#define SPI_MR_DLYBCS_MASK (0xff << SPI_MR_DLYBCS_SHIFT)
@@ -161,9 +163,11 @@
# define SPI_TDR_PCS1 (1 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1101 (w/PCSDEC=0) */
# define SPI_TDR_PCS2 (3 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 1011 (w/PCSDEC=0) */
# define SPI_TDR_PCS3 (7 << SPI_TDR_PCS_SHIFT) /* NPCS[3:0] = 0111 (w/PCSDEC=0) */
+
#define SPI_TDR_LASTXFER (1 << 24) /* Bit 24: Last Transfer */
-/* SPI Status Register, SPI Interrupt Enable Register, SPI Interrupt Disable Register,
+/* SPI Status Register, SPI Interrupt Enable Register,
+ * SPI Interrupt Disable Register,
* and SPI Interrupt Mask Register (common bit fields)
*/
@@ -193,6 +197,7 @@
#define SPI_CSR_BITS_SHIFT (4) /* Bits 4-7: Bits Per Transfer */
#define SPI_CSR_BITS_MASK (15 << SPI_CSR_BITS_SHIFT)
# define SPI_CSR_BITS(n) (((n)-8) << SPI_CSR_BITS_SHIFT) /* n, n=8-16 */
+
# define SPI_CSR_BITS8 (0 << SPI_CSR_BITS_SHIFT) /* 8 */
# define SPI_CSR_BITS9 (1 << SPI_CSR_BITS_SHIFT) /* 9 */
# define SPI_CSR_BITS10 (2 << SPI_CSR_BITS_SHIFT) /* 10 */
@@ -202,6 +207,7 @@
# define SPI_CSR_BITS14 (6 << SPI_CSR_BITS_SHIFT) /* 14 */
# define SPI_CSR_BITS15 (7 << SPI_CSR_BITS_SHIFT) /* 15 */
# define SPI_CSR_BITS16 (8 << SPI_CSR_BITS_SHIFT) /* 16 */
+
#define SPI_CSR_SCBR_SHIFT (8) /* Bits 8-15: Serial Clock Baud Rate */
#define SPI_CSR_SCBR_MASK (0xff << SPI_CSR_SCBR_SHIFT)
# define SPI_CSR_SCBR(n) ((uint32_t)(n) << SPI_CSR_SCBR_SHIFT)
@@ -259,16 +265,16 @@
# define SPI_VERSION_MFN_MASK (7 << SPI_VERSION_MFN_SHIFT)
#endif
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SPI_H */
diff --git a/arch/arm/src/sam34/hardware/sam_ssc.h b/arch/arm/src/sam34/hardware/sam_ssc.h
index aa5e102..801651b 100644
--- a/arch/arm/src/sam34/hardware/sam_ssc.h
+++ b/arch/arm/src/sam34/hardware/sam_ssc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_ssc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,38 +16,42 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* SSC register offsets *****************************************************************/
+/* SSC register offsets *****************************************************/
#define SAM_SSC_CR_OFFSET 0x000 /* Control Register */
#define SAM_SSC_CMR_OFFSET 0x004 /* Clock Mode Register */
- /* 0x008: Reserved */
- /* 0x00c: Reserved */
+
+ /* 0x008: Reserved */
+
+ /* 0x00c: Reserved */
#define SAM_SSC_RCMR_OFFSET 0x010 /* Receive Clock Mode Register */
#define SAM_SSC_RFMR_OFFSET 0x014 /* Receive Frame Mode Register */
#define SAM_SSC_TCMR_OFFSET 0x018 /* Transmit Clock Mode Register */
#define SAM_SSC_TFMR_OFFSET 0x01c /* Transmit Frame Mode Register */
#define SAM_SSC_RHR_OFFSET 0x020 /* Receive Holding Register */
#define SAM_SSC_THR_OFFSET 0x024 /* Transmit Holding Register */
- /* 0x028: Reserved */
- /* 0x02c: Reserved */
+
+ /* 0x028: Reserved */
+
+ /* 0x02c: Reserved */
#define SAM_SSC_RSHR_OFFSET 0x030 /* Receive Sync. Holding Register */
#define SAM_SSC_TSHR_OFFSET 0x034 /* Transmit Sync. Holding Register */
#define SAM_SSC_RC0R_OFFSET 0x038 /* Receive Compare 0 Register */
@@ -58,10 +62,12 @@
#define SAM_SSC_IMR_OFFSET 0x04c /* Interrupt Mask Register */
#define SAM_SSC_WPMR_OFFSET 0x0e4 /* Write Protect Mode Register */
#define SAM_SSC_WPSR_OFFSET 0x0e8 /* Write Protect Status Register */
- /* 0x050-0x0fc: Reserved */
- /* 0x100-0x124: Reserved for PDC registers */
-/* SSC register addresses ***************************************************************/
+ /* 0x050-0x0fc: Reserved */
+
+ /* 0x100-0x124: Reserved for PDC registers */
+
+/* SSC register addresses ***************************************************/
#define SAM_SSC_CR (SAM_SSC_BASE+SAM_SSC_CR_OFFSET)
#define SAM_SSC_CMR (SAM_SSC_BASE+SAM_SSC_CMR_OFFSET)
@@ -82,7 +88,7 @@
#define SAM_SSC_WPMR (SAM_SSC_BASE+SAM_SSC_WPMR_OFFSET)
#define SAM_SSC_WPSR (SAM_SSC_BASE+SAM_SSC_WPSR_OFFSET)
-/* SSC register bit definitions *********************************************************/
+/* SSC register bit definitions *********************************************/
/* SSC Control Register */
@@ -104,17 +110,20 @@
# define SSC_RCMR_CKS_DIVIDED (0 << SSC_RCMR_CKS_SHIFT) /* Divided Clock */
# define SSC_RCMR_CKS_TK (1 << SSC_RCMR_CKS_SHIFT) /* TK Clock signal */
# define SSC_RCMR_CKS_RK (2 << SSC_RCMR_CKS_SHIFT) /* RK pin */
+
#define SSC_RCMR_CKO_SHIFT (2) /* Bits 2-4: Receive Clock Output Mode Selection */
#define SSC_RCMR_CKO_MASK (7 << SSC_RCMR_CKO_SHIFT)
# define SSC_RCMR_CKO_NONE (0 << SSC_RCMR_CKO_SHIFT) /* None */
# define SSC_RCMR_CKO_CONTINUOUS (1 << SSC_RCMR_CKO_SHIFT) /* Continuous Receive Clock */
# define SSC_RCMR_CKO_XFERS (2 << SSC_RCMR_CKO_SHIFT) /* Receive Clock only during data transfers */
+
#define SSC_RCMR_CKI (1 << 5) /* Bit 5: Receive Clock Inversion */
#define SSC_RCMR_CKG_SHIFT (6) /* Bits 6-7: Receive Clock Gating Selection */
#define SSC_RCMR_CKG_MASK (3 << SSC_RCMR_CKG_SHIFT)
# define SSC_RCMR_CKG_NONE (0 << SSC_RCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_RCMR_CKG_RFLOW (1 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF Low */
# define SSC_RCMR_CKG_RFHIGH (2 << SSC_RCMR_CKG_SHIFT) /* Receive Clock enabled only if RF High */
+
#define SSC_RCMR_START_SHIFT (8) /* Bits 8-11: Receive Start Selection */
#define SSC_RCMR_START_MASK (15 << SSC_RCMR_START_SHIFT)
# define SSC_RCMR_START_CONTINOUS (0 << SSC_RCMR_START_SHIFT) /* Continuous */
@@ -126,6 +135,7 @@
# define SSC_RCMR_START_ANYLEVEL (6 << SSC_RCMR_START_SHIFT) /* Any level change on RF signal */
# define SSC_RCMR_START_ANYEDGE (7 << SSC_RCMR_START_SHIFT) /* Any edge on RF signal */
# define SSC_RCMR_START_CMP0 (8 << SSC_RCMR_START_SHIFT) /* Compare 0 */
+
#define SSC_RCMR_STOP (1 << 12) /* Bit 12: Receive Stop Select */
#define SSC_RCMR_STTDLY_SHIFT (16) /* Bits 16-23: Receive Start Delay */
#define SSC_RCMR_STTDLY_MASK (0xff << SSC_RCMR_STTDLY_SHIFT)
@@ -150,6 +160,7 @@
# define SSC_RFMR_FSOS_LOW (3 << SSC_RFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_RFMR_FSOS_HIGH (4 << SSC_RFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_RFMR_FSOS_TOGGLE (5 << SSC_RFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
+
#define SSC_RFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detect */
#define SSC_RFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
#define SSC_RFMR_FSLENEXT_MASK (15 << SSC_RFMR_FSLENEXT_SHIFT)
@@ -161,17 +172,20 @@
# define SSC_TCMR_CKS_DIVIDED (0 << SSC_TCMR_CKS_SHIFT) /* Divided Clock */
# define SSC_TCMR_CKS_RK (2 << SSC_TCMR_CKS_SHIFT) /* RK Clock signal */
# define SSC_TCMR_CKS_TK (1 << SSC_TCMR_CKS_SHIFT) /* TK Pin */
+
#define SSC_TCMR_CKO_SHIFT (2) /* Bits 2-4: Transmit Clock Output Mode Selection */
#define SSC_TCMR_CKO_MASK (7 << SSC_TCMR_CKO_SHIFT)
# define SSC_TCMR_CKO_NONE (0 << SSC_TCMR_CKO_SHIFT) /* None */
# define SSC_TCMR_CKO_CONTINUOUS (1 << SSC_TCMR_CKO_SHIFT) /* Continuous Transmit Clock */
# define SSC_TCMR_CKO_XFERS (2 << SSC_TCMR_CKO_SHIFT) /* Transmit Clock only during data transfers */
+
#define SSC_TCMR_CKI (1 << 5) /* Bit 5: Transmit Clock Inversion */
#define SSC_TCMR_CKG_SHIFT (6) /* Bits 6-7: Transmit Clock Gating Selection */
#define SSC_TCMR_CKG_MASK (3 << SSC_TCMR_CKG_SHIFT)
# define SSC_TCMR_CKG_NONE (0 << SSC_TCMR_CKG_SHIFT) /* None, continuous clock */
# define SSC_tCMR_CKG_TFLOW (1 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF Low */
# define SSC_TCMR_CKG_TFHIGH (2 << SSC_TCMR_CKG_SHIFT) /* Receive Clock enabled only if TF High */
+
#define SSC_TCMR_START_SHIFT (8) /* Bits 8-11: Transmit Start Selection */
#define SSC_TCMR_START_MASK (15 << SSC_TCMR_START_SHIFT)
# define SSC_TCMR_START_CONTINOUS (0 << SSC_TCMR_START_SHIFT) /* Continuous */
@@ -182,6 +196,7 @@
# define SSC_TCMR_START_TFRISE (5 << SSC_TCMR_START_SHIFT) /* Rising edge on TF signal */
# define SSC_TCMR_START_ANYLEVEL (6 << SSC_TCMR_START_SHIFT) /* Any level change on TF signal */
# define SSC_TCMR_START_ANYEDGE (7 << SSC_TCMR_START_SHIFT) /* Any edge on TF signal */
+
#define SSC_TCMR_STTDLY_SHIFT (16) /* Bits 16-23: Transmit Start Delay */
#define SSC_TCMR_STTDLY_MASK (0xff << SSC_TCMR_STTDLY_SHIFT)
#define SSC_TCMR_PERIOD_SHIFT (24) /* Bits 24-31: Transmit Period Divider Selection */
@@ -205,6 +220,7 @@
# define SSC_TFMR_FSOS_LOW (3 << SSC_TFMR_FSOS_SHIFT) /* 0x3 Driven Low during data transfer */
# define SSC_TFMR_FSOS_HIGH (4 << SSC_TFMR_FSOS_SHIFT) /* 0x4 Driven High during data transfer */
# define SSC_TFMR_FSOS_TOGGLE (5 << SSC_TFMR_FSOS_SHIFT) /* 0x5 Toggling at each start of data transfer */
+
#define SSC_TFMR_FSDEN (1 << 23) /* Bit 23: Frame Sync Data Enable */
#define SSC_TFMR_FSEDGE (1 << 24) /* Bit 24: Frame Sync Edge Detection */
#define SSC_TFMR_FSLENEXT_SHIFT (28) /* Bits 28-31: FSLEN Field Extension */
@@ -264,16 +280,16 @@
#define SSC_WPSR_WPVSRC_SHIFT (8) /* Bits 8-23: Write Protect Violation Source */
#define SSC_WPSR_WPVSRC_MASK (0xffff << SSC_WPSR_WPVSRC_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SSC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_supc.h b/arch/arm/src/sam34/hardware/sam_supc.h
index 885340e..592dbb6 100644
--- a/arch/arm/src/sam34/hardware/sam_supc.h
+++ b/arch/arm/src/sam34/hardware/sam_supc.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_supc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* SUPC register offsets ****************************************************************/
+/* SUPC register offsets ****************************************************/
#define SAM_SUPC_CR_OFFSET 0x00 /* Supply Controller Control Register */
#define SAM_SUPC_SMMR_OFFSET 0x04 /* Supply Controller Supply Monitor Mode Register */
@@ -43,7 +43,7 @@
#define SAM_SUPC_WUIR_OFFSET 0x10 /* Supply Controller Wake Up Inputs Register */
#define SAM_SUPC_SR_OFFSET 0x14 /* Supply Controller Status Register */
-/* SUPC register addresses **************************************************************/
+/* SUPC register addresses **************************************************/
#define SAM_SUPC_CR (SAM_SUPC_BASE+SAM_SUPC_CR_OFFSET)
#define SAM_SUPC_SMMR (SAM_SUPC_BASE+SAM_SUPC_SMMR_OFFSET)
@@ -52,7 +52,8 @@
#define SAM_SUPC_WUIR (SAM_SUPC_BASE+SAM_SUPC_WUIR_OFFSET)
#define SAM_SUPC_SR (SAM_SUPC_BASE+SAM_SUPC_SR_OFFSET)
-/* SUPC register bit definitions ********************************************************/
+/* SUPC register bit definitions ********************************************/
+
/* Supply Controller Control Register */
#define SUPC_CR_VROFF (1 << 2) /* Bit 2: Voltage Regulator Off */
@@ -112,6 +113,7 @@
# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
+
#define SUPC_SMMR_SMRSTEN (1 << 12) /* Bit 12: Supply Monitor Reset Enable */
#define SUPC_SMMR_SMIEN (1 << 13) /* Bit 13: Supply Monitor Interrupt Enable */
@@ -256,16 +258,16 @@
#define SUPC_SR_WKUPIS_MASK (0xffff << SUPC_SR_WKUPIS_SHIFT)
# define SUPC_SR_WKUPIS(n) (1 << (SUPC_SR_WKUPIS_SHIFT+(n)))
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_SUPC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_tc.h b/arch/arm/src/sam34/hardware/sam_tc.h
index 2f63708..d783d19 100644
--- a/arch/arm/src/sam34/hardware/sam_tc.h
+++ b/arch/arm/src/sam34/hardware/sam_tc.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_tc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,27 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
-/* TC register offsets **************************************************************************/
+/* TC register offsets ******************************************************/
-/* Timer channel offsets (with respect to timer base offset at 0x00, 0x40, and 0x80 */
+/* Timer channel offsets
+ *(with respect to timer base offset at 0x00, 0x40, and 0x80
+ */
#define SAM_TC_CCR_OFFSET 0x0000 /* Channel Control Register */
#define SAM_TC_CMR_OFFSET 0x0004 /* Channel Mode Register */
@@ -76,7 +78,7 @@
# define SAM_TC_WPMR_OFFSET 0xe4 /* Write Protect Mode Register */
#endif
-/* TC register addresses ************************************************************************/
+/* TC register addresses ****************************************************/
#define SAM_TC0_CCR (SAM_TC0_BASE+SAM_TC_CCR_OFFSET)
#define SAM_TC0_CMR (SAM_TC0_BASE+SAM_TC_CMR_OFFSET)
@@ -296,8 +298,9 @@
# define SAM_TC_QISR (SAM_TC_BASE+SAM_TC_QISR_OFFSET)
#endif
-/* TC register bit definitions ******************************************************************/
-/* Timer channel registers **********************************************************************/
+/* TC register bit definitions **********************************************/
+
+/* Timer channel registers **************************************************/
/* TC Channel Control Register */
@@ -325,6 +328,7 @@
# define TC_CMR_BURST_XC0 (1 << TC_CMR_BURST_SHIFT) /* XC0 ANDed with selected clock */
# define TC_CMR_BURST_XC1 (2 << TC_CMR_BURST_SHIFT) /* XC1 ANDed with selected clock */
# define TC_CMR_BURST_XC2 (3 << TC_CMR_BURST_SHIFT) /* XC2 ANDed with selected clock */
+
#define TC_CMR_WAVE (1 << 15) /* Bit 15: Waveform Mode */
/* TC Channel Mode Register -- Capture mode only */
@@ -337,6 +341,7 @@
# define TC_CMR_ETRGEDG_REDGE (1 << TC_CMR_ETRGEDG_SHIFT) /* Rising edge */
# define TC_CMR_ETRGEDG_FEDGE (2 << TC_CMR_ETRGEDG_SHIFT) /* Falling edge */
# define TC_CMR_ETRGEDG_EACH (3 << TC_CMR_ETRGEDG_SHIFT) /* Each */
+
#define TC_CMR_ABETRG (1 << 10) /* Bit 10: TIOA or TIOB External Trigger Selection */
#define TC_CMR_CPCTRG (1 << 14) /* Bit 14: RC Compare Trigger Enable */
#define TC_CMR_LDRA_SHIFT (16) /* Bits 16-17: RA Loading Selection */
@@ -345,6 +350,7 @@
# define TC_CMR_LDRA_REDGE (1 << TC_CMR_LDRA_SHIFT) /* Rising edge of TIOA */
# define TC_CMR_LDRA_FEDGE (2 << TC_CMR_LDRA_SHIFT) /* Falling edge of TIOA */
# define TC_CMR_LDRA_EACH (3 << TC_CMR_LDRA_SHIFT) /* Each edge of TIOA */
+
#define TC_CMR_LDRB_SHIFT (18) /* Bits 18-19: RB Loading Selection */
#define TC_CMR_LDRB_MASK (3 << TC_CMR_LDRB_SHIFT)
# define TC_CMR_LDRB_NONE (0 << TC_CMR_LDRB_SHIFT) /* None */
@@ -372,12 +378,14 @@
# define TC_CMR_EEVTEDG_REDGE (1 << TC_CMR_EEVTEDG_SHIFT) /* Rising edge */
# define TC_CMR_EEVTEDG_FEDGE (2 << TC_CMR_EEVTEDG_SHIFT) /* Falling edge */
# define TC_CMR_EEVTEDG_EACH (3 << TC_CMR_EEVTEDG_SHIFT) /* Each edge */
+
#define TC_CMR_EEVT_SHIFT (10) /* Bits 10-11: External Event Selection (Waveform mode) */
#define TC_CMR_EEVT_MASK (3 << TC_CMR_EEVT_SHIFT)
# define TC_CMR_EEVT_TIOB (0 << TC_CMR_EEVT_SHIFT) /* TIOB input */
# define TC_CMR_EEVT_XC0 (1 << TC_CMR_EEVT_SHIFT) /* XC0 output */
# define TC_CMR_EEVT_XC1 (2 << TC_CMR_EEVT_SHIFT) /* XC1 output */
# define TC_CMR_EEVT_XC2 (3 << TC_CMR_EEVT_SHIFT) /* XC2 output */
+
#define TC_CMR_ENETRG (1 << 12) /* Bit 12: External Event Trigger Enable (Waveform mode) */
#define TC_CMR_WAVSEL_SHIFT (13) /* Bits 13-14: Waveform Selection (Waveform mode) */
#define TC_CMR_WAVSEL_MASK (3 << TC_CMR_WAVSEL_SHIFT)
@@ -385,6 +393,7 @@
# define TC_CMR_WAVSEL_UPDWN (1 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode w/o auto trigger (Waveform mode) */
# define TC_CMR_WAVSEL_UPAUTO (2 << TC_CMR_WAVSEL_SHIFT) /* UP mode with auto trigger (Waveform mode) */
# define TC_CMR_WAVSEL_UPDWNAUTO (3 << TC_CMR_WAVSEL_SHIFT) /* UPDOWN mode with auto trigger (Waveform mode) */
+
#define TC_CMR_ACPA_SHIFT (16) /* Bits 16-17: RA Compare Effect on TIOA (Waveform mode) */
#define TC_CMR_ACPA_MASK (3 << TC_CMR_ACPA_SHIFT)
# define TC_CMR_ACPA_NONE (0 << TC_CMR_ACPA_SHIFT)
@@ -463,7 +472,10 @@
# define TC_RVALUE_MASK (0x0000ffff)
#endif
-/* TC Status Register, TC Interrupt Enable Register, TC Interrupt Disable Register, and TC Interrupt Mask Register common bit-field definitions */
+/* TC Status Register, TC Interrupt Enable Register,
+ * TC Interrupt Disable Register, and
+ * TC Interrupt Mask Register common bit-field definitions
+ */
#define TC_INT_COVFS (1 << 0) /* Bit 0: Counter Overflow */
#define TC_INT_LOVRS (1 << 1) /* Bit 1: Load Overrun */
@@ -493,14 +505,17 @@
# define TC_EMR_TRIGSRCA_MASK (3 << TC_EMR_TRIGSRCA_SHIFT)
# define TC_EMR_TRIGSRCA_TIOA (0 << TC_EMR_TRIGSRCA_SHIFT) /* Input A driven by pin TIOAx */
# define TC_EMR_TRIGSRCA_PWM (1 << TC_EMR_TRIGSRCA_SHIFT) /* Input A driven by PWMx */
+
# define TC_EMR_TRIGSRCB_SHIFT (5) /* Bits 4-5: Trigger source for input B */
# define TC_EMR_TRIGSRCB_MASK (3 << TC_EMR_TRIGSRCB_SHIFT)
# define TC_EMR_TRIGSRCB_TIOA (0 << TC_EMR_TRIGSRCB_SHIFT) /* Input B driven by pin TIOBx */
# define TC_EMR_TRIGSRCB_PWM (1 << TC_EMR_TRIGSRCB_SHIFT) /* Input B driven by PWMx */
+
# define TC_EMR_NODIVCLK (1 << 8) /* Bit 8: NO DIVided CLocK */
#endif
-/* Timer common registers ***********************************************************************/
+/* Timer common registers ***************************************************/
+
/* TC Block Control Register */
#define TC_BCR_SYNC (1 << 0) /* Bit 0: Synchro Command */
@@ -566,16 +581,16 @@
# define TC_WPMR_WPKEY (0x0054494d << TC_WPMR_WPKEY_SHIFT)
#endif
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TC_H */
diff --git a/arch/arm/src/sam34/hardware/sam_twi.h b/arch/arm/src/sam34/hardware/sam_twi.h
index dd4ecef..c6231ab 100644
--- a/arch/arm/src/sam34/hardware/sam_twi.h
+++ b/arch/arm/src/sam34/hardware/sam_twi.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_twi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* TWI register offsets *****************************************************************/
+/* TWI register offsets *****************************************************/
#define SAM_TWI_CR_OFFSET 0x0000 /* Control Register */
#define SAM_TWI_MMR_OFFSET 0x0004 /* Master Mode Register */
@@ -53,7 +53,7 @@
# define SAM_TWI_WPSR_OFFSET 0x00e8 /* Protection Status Register */
#endif
-/* TWI register addresses ***************************************************************/
+/* TWI register addresses ***************************************************/
#define SAM_TWI_CR(n) (SAM_TWIN_BASE(n)+SAM_TWI_CR_OFFSET)
#define SAM_TWI_MMR(n) (SAM_TWIN_BASE(n)+SAM_TWI_MMR_OFFSET)
@@ -103,7 +103,7 @@
# define SAM_TWI1_WPSR (SAM_TWI1_BASE)+SAM_TWI_WPSR_OFFSET)
#endif
-/* TWI register bit definitions *********************************************************/
+/* TWI register bit definitions *********************************************/
/* TWI Control Register */
@@ -124,6 +124,7 @@
# define TWI_MMR_IADRSZ_1BYTE (1 << TWI_MMR_IADRSZ_SHIFT) /* One-byte internal device address */
# define TWI_MMR_IADRSZ_2BYTE (2 << TWI_MMR_IADRSZ_SHIFT) /* Two-byte internal device address */
# define TWI_MMR_IADRSZ_3BYTE (3 << TWI_MMR_IADRSZ_SHIFT) /* Three-byte internal device address */
+
#define TWI_MMR_MREAD (1 << 12) /* Bit 12: Master Read Direction */
#define TWI_MMR_DADR_SHIFT (16) /* Bits 16-22: Device Address */
#define TWI_MMR_DADR_MASK (0x7f << TWI_MMR_DADR_SHIFT)
@@ -201,16 +202,16 @@
# define TWI_WPSR_WPVSRC_MASK (0xffff << TWI_WPSR_WPVSRC_SHIFT)
#endif
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_TWI_H */
diff --git a/arch/arm/src/sam34/hardware/sam_uart.h b/arch/arm/src/sam34/hardware/sam_uart.h
index 0616be3..213fb0f 100644
--- a/arch/arm/src/sam34/hardware/sam_uart.h
+++ b/arch/arm/src/sam34/hardware/sam_uart.h
@@ -1,4 +1,4 @@
-/************************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_uart.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H
-/************************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/************************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************************/
+ ****************************************************************************/
-/* UART register offsets ************************************************************************/
+/* UART register offsets ****************************************************/
#define SAM_UART_CR_OFFSET 0x0000 /* Control Register (Common) */
#define SAM_UART_MR_OFFSET 0x0004 /* Mode Register (Common) */
@@ -66,7 +66,7 @@
#define SAM_UART_VERSION_OFFSET 0x00fc /* Version Register (USART only, Not SAM4E) */
/* 0x0100-0x0124: PDC Area (Common) */
-/* UART register addresses **********************************************************************/
+/* UART register addresses **************************************************/
#define SAM_UART0_CR (SAM_UART0_BASE+SAM_UART_CR_OFFSET)
#define SAM_UART0_MR (SAM_UART0_BASE+SAM_UART_MR_OFFSET)
@@ -213,7 +213,7 @@
#define SAM_USART3_WPSR (SAM_USART3_BASE+SAM_UART_WPSR_OFFSET)
#define SAM_USART3_VERSION (SAM_USART3_BASE+SAM_UART_VERSION_OFFSET)
-/* UART register bit definitions ****************************************************************/
+/* UART register bit definitions ********************************************/
/* UART Control Register */
@@ -269,12 +269,14 @@
# define UART_MR_USCLKS_MCK (0 << UART_MR_USCLKS_SHIFT) /* MCK */
# define UART_MR_USCLKS_MCKDIV (1 << UART_MR_USCLKS_SHIFT) /* MCK/DIV (DIV = 8) */
# define UART_MR_USCLKS_SCK (3 << UART_MR_USCLKS_SHIFT) /* SCK */
+
#define UART_MR_CHRL_SHIFT (6) /* Bits 6-7: Character Length (USART only) */
#define UART_MR_CHRL_MASK (3 << UART_MR_CHRL_SHIFT)
# define UART_MR_CHRL_5BITS (0 << UART_MR_CHRL_SHIFT) /* 5 bits */
# define UART_MR_CHRL_6BITS (1 << UART_MR_CHRL_SHIFT) /* 6 bits */
# define UART_MR_CHRL_7BITS (2 << UART_MR_CHRL_SHIFT) /* 7 bits */
# define UART_MR_CHRL_8BITS (3 << UART_MR_CHRL_SHIFT) /* 8 bits */
+
#define UART_MR_SYNC (1 << 8) /* Bit 8: Synchronous Mode Select (USART only) */
#define UART_MR_CPHA (1 << 8) /* Bit 8: SPI Clock Phase (USART SPI mode only) */
#define UART_MR_PAR_SHIFT (9) /* Bits 9-11: Parity Type (Common) */
@@ -285,11 +287,13 @@
# define UART_MR_PAR_MARK (3 << UART_MR_PAR_SHIFT) /* Mark: parity forced to 1 (Common) */
# define UART_MR_PAR_NONE (4 << UART_MR_PAR_SHIFT) /* No parity (Common) */
# define UART_MR_PAR_MULTIDROP (6 << UART_MR_PAR_SHIFT) /* Multidrop mode (USART only) */
+
#define UART_MR_NBSTOP_SHIFT (12) /* Bits 12-13: Number of Stop Bits (USART only) */
#define UART_MR_NBSTOP_MASK (3 << UART_MR_NBSTOP_SHIFT)
# define UART_MR_NBSTOP_1 (0 << UART_MR_NBSTOP_SHIFT) /* 1 stop bit 1 stop bit */
# define UART_MR_NBSTOP_1p5 (1 << UART_MR_NBSTOP_SHIFT) /* 1.5 stop bits */
# define UART_MR_NBSTOP_2 (2 << UART_MR_NBSTOP_SHIFT) /* 2 stop bits 2 stop bits */
+
#define UART_MR_CHMODE_SHIFT (14) /* Bits 14-15: Channel Mode (Common) */
#define UART_MR_CHMODE_MASK (3 << UART_MR_CHMODE_SHIFT)
# define UART_MR_CHMODE_NORMAL (0 << UART_MR_CHMODE_SHIFT) /* Normal Mode */
@@ -343,7 +347,8 @@
#define UART_MR_MODSYNC (1 << 30) /* Bit 30: Manchester Synchronization Mode (USART only) */
#define UART_MR_ONEBIT (1 << 31) /* Bit 31: Start Frame Delimiter Selector (USART only) */
-/* UART Interrupt Enable Register, UART Interrupt Disable Register, UART Interrupt Mask
+/* UART Interrupt Enable Register,
+ * UART Interrupt Disable Register, UART Interrupt Mask
* Register, and UART Status Register common bit field definitions
*/
@@ -475,6 +480,7 @@
# define UART_MAN_TXPP_ALLZERO (1 << UART_MAN_TXPP_SHIFT) /* ALL_ZERO */
# define UART_MAN_TXPP_ZEROONE (2 << UART_MAN_TXPP_SHIFT) /* ZERO_ONE */
# define UART_MAN_TXPP_ONEZERO (3 << UART_MAN_TXPP_SHIFT) /* ONE_ZERO */
+
#define UART_MAN_TXMPOL (1 << 12) /* Bit 12: Transmitter Manchester Polarity (USART only) */
#define UART_MAN_RXPL_SHIFT (16) /* Bits 16-19: Receiver Preamble Length (USART only) */
#define UART_MAN_RXPL_MASK (15 << UART_MAN_RXPL_SHIFT)
@@ -485,6 +491,7 @@
# define UART_MAN_RXPP_ALLZERO (1 << UART_MAN_RXPP_SHIFT) /* ALL_ZERO */
# define UART_MAN_RXPP_ZEROONE (2 << UART_MAN_RXPP_SHIFT) /* ZERO_ONE */
# define UART_MAN_RXPP_ONEZERO (3 << UART_MAN_RXPP_SHIFT) /* ONE_ZERO */
+
#define UART_MAN_RXMPOL (1 << 28) /* Bit 28: Receiver Manchester Polarity (USART only) */
#if defined(CONFIG_ARCH_CHIP_SAM4S) || defined(CONFIG_ARCH_CHIP_SAM4E)
@@ -501,6 +508,7 @@
# define UART_LINMR_NACT_PUBLISH (0 << UART_LINMR_NACT_SHIFT) /* USART transmits response */
# define UART_LINMR_NACT_SUBSCRIBE (1 << UART_LINMR_NACT_SHIFT) /* USART receives response */
# define UART_LINMR_NACT_IGNORE (2 << UART_LINMR_NACT_SHIFT) /* USART does not transmit or receive response */
+
# define UART_LINMR_PARDIS (1 << 2) /* Bit 2: Parity Disable */
# define UART_LINMR_CHKDIS (1 << 3) /* Bit 3: Checksum Disable */
# define UART_LINMR_CHKTYP (1 << 4) /* Bit 4: Checksum Type */
@@ -540,16 +548,16 @@
#define UART_VERSION_MFN_SHIFT (16) /* Bits 16-18: Reserved (USART only) */
#define UART_VERSION_MFN_MASK (7 << UART_VERSION_MFN_SHIFT)
-/************************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************************
- * Public Functions
- ************************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UART_H */
diff --git a/arch/arm/src/sam34/hardware/sam_udp.h b/arch/arm/src/sam34/hardware/sam_udp.h
index 2c9fd59..ec7130f 100644
--- a/arch/arm/src/sam34/hardware/sam_udp.h
+++ b/arch/arm/src/sam34/hardware/sam_udp.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_udp.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,24 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
-/* General Definitions ******************************************************************/
+ ****************************************************************************/
+
+/* General Definitions ******************************************************/
+
/* Capabilities and characteristics of endpoints
*
* EP EP BANKS EP SIZE EP TYPE
@@ -56,7 +58,7 @@
#define SAM_UDP_ISOCHRONOUS(ep) (((unsigned)(ep) != 0 && (unsigned)(ep) != 3))
#define SAM_UDP_INTERRUPT(ep) (true)
-/* UDP register offsets *****************************************************************/
+/* UDP register offsets *****************************************************/
/* Global Registers */
@@ -72,6 +74,7 @@
/* 0x0024: Reserved */
#define SAM_UDP_RSTEP_OFFSET 0x0028 /* UDP Reset Endpoint Register */
/* 0x002c: Reserved */
+
/* Endpoint registers */
#define SAM_UDPEP_CSR_OFFSET(n) (0x0030+((n)<<2))
@@ -96,7 +99,7 @@
#define SAM_UDP_TXVC_OFFSET 0x0074 /* Transceiver Control Register */
/* 0x0078-0x00fc: Reserved */
-/* UDP register addresses ***************************************************************/
+/* UDP register addresses ***************************************************/
/* Global Registers */
@@ -133,7 +136,7 @@
#define SAM_UDP_TXVC (SAM_UDP_BASE+SAM_UDP_TXVC_OFFSET)
-/* UDP register bit definitions *********************************************************/
+/* UDP register bit definitions *********************************************/
/* Global Registers */
@@ -159,7 +162,8 @@
# define UDP_FADDR(n) ((uint32_t)(n))
#define UDP_FADDR_FEN (1 << 8) /* Bit 8: Function Enable */
-/* UDP Interrupt Enable, UDP Interrupt Disable, UDP Interrupt Mask, UDP Interrupt
+/* UDP Interrupt Enable, UDP Interrupt Disable,
+ * UDP Interrupt Mask, UDP Interrupt
* Status, and UDP Interrupt Clear Registers.
*/
@@ -195,6 +199,7 @@
# define UDP_RSTEP7 (1 << 7) /* Bit 7: Reset Endpoint 7 */
/* Endpoint registers */
+
/* Endpoint Control and Status Registers */
#define UDPEP_CSR_TXCOMP (1 << 0) /* Bit 0: Generates an IN packet with data */
@@ -216,6 +221,7 @@
# define UDPEP_CSR_EPTYPE_BULKIN (6 << UDPEP_CSR_EPTYPE_SHIFT) /* Bulk IN */
# define UDPEP_CSR_EPTYPE_INTOUT (3 << UDPEP_CSR_EPTYPE_SHIFT) /* Interrupt OUT */
# define UDPEP_CSR_EPTYPE_INTIN (7 << UDPEP_CSR_EPTYPE_SHIFT) /* Interrupt IN */
+
#define UDPEP_CSR_DTGLE (1 << 11) /* Bit 11: Data Toggle */
#define UDPEP_CSR_EPEDS (1 << 15) /* Bit 15: Endpoint Enable Disable */
#define UDPEP_CSR_RXBYTECNT_SHIFT (16) /* Bits 16-26: Number of Bytes Available in the FIFO */
@@ -230,16 +236,16 @@
#define UDP_TXVC_TXVDIS (1 << 8) /* Bit 8: Transceiver Disable */
#define UDP_TXVC_PUON (1 << 9) /* Bit 9: Pull-up On */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDP_H */
diff --git a/arch/arm/src/sam34/hardware/sam_udphs.h b/arch/arm/src/sam34/hardware/sam_udphs.h
index 82cf827..c2f951b 100644
--- a/arch/arm/src/sam34/hardware/sam_udphs.h
+++ b/arch/arm/src/sam34/hardware/sam_udphs.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_udphs.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,25 +16,25 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* UDPHS register offsets ***************************************************************/
+/* UDPHS register offsets ***************************************************/
#define SAM_UDPHS_CTRL_OFFSET 0x00 /* UDPHS Control Register */
#define SAM_UDPHS_FNUM_OFFSET 0x04 /* UDPHS Frame Number Register */
@@ -50,7 +50,8 @@
#define SAM_UDPHS_IPNAME2_OFFSET 0xf4 /* UDPHS Name2 Register */
#define SAM_UDPHS_IPFEATURES_OFFSET 0xf8 /* UDPHS Features Register */
-/* Endpoint registers: Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180,
+/* Endpoint registers:
+ * Offsets for Endpoints 0-6: 0x100, 0x120, 0x140, 0x160, 0x180,
* 0x1a0, and 0x1c0
*/
@@ -65,8 +66,10 @@
#define SAM_UDPHSEP_STA_OFFSET 0x1c /* UDPHS Endpoint Status Register */
/* 0x1e0-0x300: Reserved */
/* 0x300-0x30c: Reserved */
-/* DMA Channel Registers: Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and
- * 0x360. NOTE that there is no DMA channel 0.
+
+/* DMA Channel Registers:
+ * Offsets for DMA channels 1-6 0x320, 0x330, 0x340, 0x350, and 0x360.
+ * NOTE that there is no DMA channel 0.
*/
#define SAM_UDPHSDMA_OFFSET(n) (0x310+((n)<<4))
@@ -75,7 +78,7 @@
#define SAM_UDPHSDMA_CONTROL_OFFSET 0x08 /* UDPHS DMA Channel Control Register */
#define SAM_UDPHSDMA_STATUS_OFFSET 0x0c /* UDPHS DMA Channel Status Register */
-/* UDPHS register addresses *************************************************************/
+/* UDPHS register addresses *************************************************/
#define SAM_UDPHS_CTRL (SAM_UDPHS_BASE+SAM_UDPHS_CTRL_OFFSET)
#define SAM_UDPHS_FNUM (SAM_UDPHS_BASE+SAM_UDPHS_FNUM_OFFSET)
@@ -99,7 +102,7 @@
#define SAM_UDPHSEP_CLRSTA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_CLRSTA_OFFSET)
#define SAM_UDPHSEP_STA(n) (SAM_UDPHSEP_BASE(n)+SAM_UDPHSEP_STA_OFFSET)
-/* DMA Channel Registers*/
+/* DMA Channel Registers */
#define SAM_UDPHSDMA_BASE(n) (SAM_UDPHS_BASE+SAM_UDPHSDMA_OFFSET(n))
#define SAM_UDPHSDMA_NXTDSC(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_NXTDSC_OFFSET)
@@ -107,7 +110,8 @@
#define SAM_UDPHSDMA_CONTROL(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_CONTROL_OFFSET)
#define SAM_UDPHSDMA_STATUS(n) (SAM_UDPHSDMA_BASE(n)+SAM_UDPHSDMA_STATUS_OFFSET)
-/* UDPHS register bit definitions *******************************************************/
+/* UDPHS register bit definitions *******************************************/
+
/* UDPHS Control Register */
#define UDPHS_CTRL_DEVADDR_SHIFT (0) /* Bits 0-6: UDPHS Address */
@@ -127,8 +131,8 @@
#define UDPHS_FNUM_FNUMERR_SHIFT (8) /* Bits 8-13: Frame Number CRC Error */
#define UDPHS_FNUM_FNUMERR_MASK (63 << UDPHS_FNUM_FNUMERR_SHIFT)
-/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register, and UDPHS Clear
- * Interrupt Register common bit-field definitions
+/* UDPHS Interrupt Enable Register, UDPHS Interrupt Status Register,
+ * and UDPHS Clear Interrupt Register common bit-field definitions
*/
#define USBPHS_INT_DETSUSPD (1 << 1) /* Bit 1: Suspend Interrupt (Common) */
@@ -165,6 +169,7 @@
# define UDPHS_TST_SPEEDCFG_NORMAL (0 << UDPHS_TST_SPEEDCFG_SHIFT) /* Normal Mode */
# define UDPHS_TST_SPEEDCFG_HIGH (2 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force High Speed */
# define UDPHS_TST_SPEEDCFG_FULL (3 << UDPHS_TST_SPEEDCFG_SHIFT) /* Force Full Speed */
+
#define UDPHS_TST_TSTJ (1 << 2) /* Bit 2: Test J Mode */
#define UDPHS_TST_TSTK (1 << 3) /* Bit 3: Test K Mode */
#define UDPHS_TST_TSTPKT (1 << 4) /* Bit 4: Test Packet Mo */
@@ -190,6 +195,7 @@
# define UDPHS_IPFEATURES_FIFOMAXSIZE_4Kb (5 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 4096 bytes */
# define UDPHS_IPFEATURES_FIFOMAXSIZE_8Kb (6 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 8192 bytes */
# define UDPHS_IPFEATURES_FIFOMAXSIZE_16Kb (7 << UDPHS_IPFEATURES_FIFOMAXSIZE_SHIFT) /* DPRAM 16384 bytes */
+
#define UDPHS_IPFEATURES_BWDPRAM (1 << 15) /* Bit 15: DPRAM Byte Write Capability */
#define UDPHS_IPFEATURES_DATAB168 (1 << 15) /* Bit 15: UTMI DataBus16_8 */
#define UDPHS_IPFEATURES_ISOEPT(n) (1<<((n)+16)
@@ -221,6 +227,7 @@
# define UDPHSEP_CFG_SIZE_256b (5 << UDPHSEP_CFG_SIZE_SHIFT) /* 256 bytes */
# define UDPHSEP_CFG_SIZE_512b (6 << UDPHSEP_CFG_SIZE_SHIFT) /* 512 bytes */
# define UDPHSEP_CFG_SIZE_1Kb (7 << UDPHSEP_CFG_SIZE_SHIFT) /* 1024 bytes */
+
#define UDPHSEP_CFG_DIR (1 << 3) /* Bit 3: Endpoint Direction */
#define UDPHSEP_CFG_TYPE_SHIFT (4) /* Bits 4-5: Endpoint Type */
#define UDPHSEP_CFG_TYPE_MASK (3 << UDPHSEP_CFG_TYPE_SHIFT)
@@ -228,18 +235,21 @@
# define UDPHSEP_CFG_TYPE_ISOC (1 << UDPHSEP_CFG_TYPE_SHIFT) /* Isochronous endpoint */
# define UDPHSEP_CFG_TYPE_BULK (2 << UDPHSEP_CFG_TYPE_SHIFT) /* Bulk endpoint */
# define UDPHSEP_CFG_TYPE_INTR (3 << UDPHSEP_CFG_TYPE_SHIFT) /* Interrupt endpoint */
+
#define UDPHSEP_CFG_BKNUMBER_SHIFT (6) /* Bits 6-7: Number of Banks */
#define UDPHSEP_CFG_BKNUMBER_MASK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT)
# define UDPHSEP_CFG_BKNUMBER_0BANK (0 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Zero bank (unmapped) */
# define UDPHSEP_CFG_BKNUMBER_1BANK (1 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* One bank (bank 0) */
# define UDPHSEP_CFG_BKNUMBER_2BANK (2 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Double bank (bank 0-1) */
# define UDPHSEP_CFG_BKNUMBER_3BANK (3 << UDPHSEP_CFG_BKNUMBER_SHIFT) /* Triple bank (bank 0-2) */
-#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */
+
+#define UDPHSEP_CFG_NBTRANS_SHIFT (8) /* Bits 8-9: Number Of Transaction per Microframe */
#define UDPHSEP_CFG_NBTRANS_MASK (3 << UDPHSEP_CFG_NBTRANS_SHIFT)
-#define UDPHSEP_CFG_MAPD (1 << 31) /*Bit 31: Endpoint Mapped */
+#define UDPHSEP_CFG_MAPD (1 << 31) /* Bit 31: Endpoint Mapped */
-/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control Disable Register,
- * and UDPHS Endpoint Control Register common bit-field definitions
+/* UDPHS Endpoint Control Enable Register, UDPHS Endpoint Control
+ * Disable Register, and UDPHS Endpoint Control Register common
+ * bit-field definitions
*/
#define UDPHSEP_INT_EPT (1 << 0) /* Bit 0: Endpoint Enable/Disable */
@@ -293,6 +303,7 @@
# define UDPHSEP_STA_TOGGLESQSTA_DATA1 (1 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data1 */
# define UDPHSEP_STA_TOGGLESQSTA_DATA2 (2 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* Data2 (High B/W Isoc EP) */
# define UDPHSEP_STA_TOGGLESQSTA_MDATA (3 << UDPHSEP_STA_TOGGLESQSTA_SHIFT) /* MData (High B/W Isoc EP) */
+
#define UDPHSEP_STA_ERROVFLW (1 << 8) /* Bit 8: Overflow Error */
#define UDPHSEP_STA_RXBKRDY (1 << 9) /* Bit 9: Received OUT Data */
#define UDPHSEP_STA_KILLBANK (1 << 9) /* Bit 9: KILL Bank */
@@ -340,16 +351,16 @@
#define UDPHSDMA_STATUS_BUFFCOUNT_SHIFT (16) /* Bits 16-31: Buffer Byte Count */
#define UDPHSDMA_STATUS_BUFFCOUNT_MASK (0xffff << UDPHSDMA_STATUS_BUFFCOUNT_SHIFT)
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_UDPHS_H */
diff --git a/arch/arm/src/sam34/hardware/sam_wdt.h b/arch/arm/src/sam34/hardware/sam_wdt.h
index 69e43f2..cc07003 100644
--- a/arch/arm/src/sam34/hardware/sam_wdt.h
+++ b/arch/arm/src/sam34/hardware/sam_wdt.h
@@ -1,4 +1,4 @@
-/****************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/hardware/sam_wdt.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,37 +16,38 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ****************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H
#define __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H
-/****************************************************************************************
+/****************************************************************************
* Included Files
- ****************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#include "hardware/sam_memorymap.h"
-/****************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ****************************************************************************************/
+ ****************************************************************************/
-/* WDT register offsets *****************************************************************/
+/* WDT register offsets *****************************************************/
#define SAM_WDT_CR_OFFSET 0x00 /* Control Register */
#define SAM_WDT_MR_OFFSET 0x04 /* Mode Register */
#define SAM_WDT_SR_OFFSET 0x08 /* Status Register */
-/* WDT register addresses ***************************************************************/
+/* WDT register addresses ***************************************************/
#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET)
#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET)
#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET)
-/* WDT register bit definitions *********************************************************/
+/* WDT register bit definitions *********************************************/
+
/* Watchdog Timer Control Register */
#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
@@ -76,16 +77,16 @@
#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error */
-/****************************************************************************************
+/****************************************************************************
* Public Types
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
+/****************************************************************************
* Public Data
- ****************************************************************************************/
+ ****************************************************************************/
-/****************************************************************************************
- * Public Functions
- ****************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_HARDWARE_SAM_WDT_H */
diff --git a/arch/arm/src/sam34/sam3u_gpio.h b/arch/arm/src/sam34/sam3u_gpio.h
index 6edcd56..694d68e 100644
--- a/arch/arm/src/sam34/sam3u_gpio.h
+++ b/arch/arm/src/sam34/sam3u_gpio.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam3u_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM3U_GPIO_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
#undef GPIO_HAVE_PULLDOWN
#undef GPIO_HAVE_PERIPHCD
#undef GPIO_HAVE_SCHMITT
#undef GPIO_HAVE_DELAYR
-/* Bit-encoded input to sam_configgpio() ********************************************/
+/* Bit-encoded input to sam_configgpio() ************************************/
/* 16-bit Encoding:
*
@@ -87,7 +88,8 @@
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
# define GPIO_INT_BOTHEDGES (0)
-/* If the pin is an GPIO output, then this identifies the initial output value:
+/* If the pin is an GPIO output, then this identifies the initial
+ * output value:
*
* .... .... V... ....
*/
@@ -146,23 +148,23 @@
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
/* Must be big enough to hold the 16-bit encoding */
typedef uint16_t gpio_pinset_t;
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -173,9 +175,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam3u_periphclks.h b/arch/arm/src/sam34/sam3u_periphclks.h
index b3031bd..8209c49 100644
--- a/arch/arm/src/sam34/sam3u_periphclks.h
+++ b/arch/arm/src/sam34/sam3u_periphclks.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam3u_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM3U_PERIPHCLKS_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
/* Helper macros */
#define sam_enableperipheral(s) putreg32((1 << (s)), SAM_PMC_PCER)
@@ -98,19 +99,19 @@
#define sam_dmac_disableclk() sam_disableperipheral(SAM_PID_DMAC)
#define sam_udphs_disableclk() sam_disableperipheral(SAM_PID_UDPHS)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -121,9 +122,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam3x_gpio.h b/arch/arm/src/sam34/sam3x_gpio.h
index 157becf..9fe275c 100644
--- a/arch/arm/src/sam34/sam3x_gpio.h
+++ b/arch/arm/src/sam34/sam3x_gpio.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam3x_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3X_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM3X_GPIO_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
#undef GPIO_HAVE_PULLDOWN
#undef GPIO_HAVE_PERIPHCD
#undef GPIO_HAVE_SCHMITT
#undef GPIO_HAVE_DELAYR
-/* Bit-encoded input to sam_configgpio() ********************************************/
+/* Bit-encoded input to sam_configgpio() ************************************/
/* 32-bit Encoding:
*
@@ -87,7 +88,8 @@
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
# define GPIO_INT_BOTHEDGES (0)
-/* If the pin is an GPIO output, then this identifies the initial output value:
+/* If the pin is an GPIO output, then this identifies the initial
+ * output value:
*
* .... .... ...V .... ....
*/
@@ -149,23 +151,23 @@
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -176,9 +178,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam3x_periphclks.h b/arch/arm/src/sam34/sam3x_periphclks.h
index f145407..f2983ef 100644
--- a/arch/arm/src/sam34/sam3x_periphclks.h
+++ b/arch/arm/src/sam34/sam3x_periphclks.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam3x_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM3X_PERIPHCLKS_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
@@ -132,19 +133,19 @@
#define sam_can0_disableclk() sam_disableperiph1(SAM_PID_CAN0)
#define sam_can1_disableclk() sam_disableperiph1(SAM_PID_CAN1)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -155,9 +156,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4cm_freerun.c b/arch/arm/src/sam34/sam4cm_freerun.c
index 51834ea..a8b09db 100644
--- a/arch/arm/src/sam34/sam4cm_freerun.c
+++ b/arch/arm/src/sam34/sam4cm_freerun.c
@@ -64,6 +64,7 @@
/****************************************************************************
* Private Functions
****************************************************************************/
+
/****************************************************************************
* Name: sam_freerun_handler
*
@@ -226,8 +227,9 @@ int sam_freerun_counter(struct sam_freerun_s *freerun, struct timespec *ts)
DEBUGASSERT(freerun && freerun->tch && ts);
- /* Temporarily disable the overflow counter. NOTE that we have to be careful
- * here because sam_tc_getpending() will reset the pending interrupt status.
+ /* Temporarily disable the overflow counter.
+ * NOTE that we have to be careful here because sam_tc_getpending()
+ * will reset the pending interrupt status.
* If we do not handle the overflow here then, it will be lost.
*/
diff --git a/arch/arm/src/sam34/sam4cm_gpio.h b/arch/arm/src/sam34/sam4cm_gpio.h
index 06ae32e..a71e6c3 100644
--- a/arch/arm/src/sam34/sam4cm_gpio.h
+++ b/arch/arm/src/sam34/sam4cm_gpio.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4cm_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM4CM_GPIO_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
#undef GPIO_HAVE_DELAYR
-/* Bit-encoded input to sam_configgpio() ********************************************/
+/* Bit-encoded input to sam_configgpio() ************************************/
/* 32-bit Encoding:
*
@@ -92,7 +93,8 @@
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
# define GPIO_INT_BOTHEDGES (0)
-/* If the pin is an GPIO output, then this identifies the initial output value:
+/* If the pin is an GPIO output, then this identifies the initial
+ * output value:
*
* .... .... .... V... ....
*/
@@ -151,23 +153,23 @@
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -178,9 +180,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4cm_oneshot.c b/arch/arm/src/sam34/sam4cm_oneshot.c
index 296f2a8..2008d27 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot.c
+++ b/arch/arm/src/sam34/sam4cm_oneshot.c
@@ -193,10 +193,12 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
* TC_CMR_BSWTRG_NONE - No software trigger effect on TIOB
*/
- cmr |= (TC_CMR_BURST_NOTGATED | TC_CMR_CPCSTOP | TC_CMR_EEVTEDG_NONE |
- TC_CMR_EEVT_TIOB | TC_CMR_WAVSEL_UPAUTO | TC_CMR_WAVE |
- TC_CMR_ACPA_NONE | TC_CMR_ACPC_NONE | TC_CMR_AEEVT_NONE |
- TC_CMR_ASWTRG_NONE | TC_CMR_BCPB_NONE | TC_CMR_BCPC_NONE |
+ cmr |= (TC_CMR_BURST_NOTGATED | TC_CMR_CPCSTOP |
+ TC_CMR_EEVTEDG_NONE | TC_CMR_EEVT_TIOB |
+ TC_CMR_WAVSEL_UPAUTO | TC_CMR_WAVE |
+ TC_CMR_ACPA_NONE | TC_CMR_ACPC_NONE |
+ TC_CMR_AEEVT_NONE | TC_CMR_ASWTRG_NONE |
+ TC_CMR_BCPB_NONE | TC_CMR_BCPC_NONE |
TC_CMR_BEEVT_NONE | TC_CMR_BSWTRG_NONE);
oneshot->tch = sam_tc_allocate(chan, cmr);
@@ -232,7 +234,8 @@ int sam_oneshot_initialize(struct sam_oneshot_s *oneshot, int chan,
int sam_oneshot_max_delay(struct sam_oneshot_s *oneshot, uint64_t *usec)
{
DEBUGASSERT(oneshot && usec);
- *usec = (0xffffull * USEC_PER_SEC) / (uint64_t)sam_tc_divfreq(oneshot->tch);
+ *usec = (0xffffull * USEC_PER_SEC) /
+ (uint64_t)sam_tc_divfreq(oneshot->tch);
return OK;
}
@@ -266,7 +269,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
irqstate_t flags;
tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n",
- handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec);
+ handler, arg, (unsigned long)ts->tv_sec,
+ (unsigned long)ts->tv_nsec);
DEBUGASSERT(oneshot && handler && ts);
/* Was the oneshot already running? */
@@ -287,9 +291,11 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
/* Express the delay in microseconds */
- usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
+ usec = (uint64_t)ts->tv_sec * USEC_PER_SEC +
+ (uint64_t)(ts->tv_nsec / NSEC_PER_USEC);
- /* Get the timer counter frequency and determine the number of counts need to achieve the requested delay.
+ /* Get the timer counter frequency and determine the number of counts need
+ * to achieve the requested delay.
*
* frequency = ticks / second
* ticks = seconds * frequency
@@ -331,8 +337,8 @@ int sam_oneshot_start(struct sam_oneshot_s *oneshot,
* of the oneshot timer/counter.
*
* The function up_timer_gettime() could also be used for this but it takes
- * too long. If up_timer_gettime() is called within this function the problem
- * vanishes at least if compiled with no optimisation.
+ * too long. If up_timer_gettime() is called within this function the
+ * problem vanishes at least if compiled with no optimisation.
*/
if (freerun != NULL)
diff --git a/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
index 2dc7a16..6befdca 100644
--- a/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
+++ b/arch/arm/src/sam34/sam4cm_oneshot_lowerhalf.c
@@ -39,7 +39,9 @@
* Private Types
****************************************************************************/
-/* This structure describes the state of the oneshot timer lower-half driver */
+/* This structure describes the state of the oneshot timer lower-half
+ * driver
+ */
struct sam_oneshot_lowerhalf_s
{
diff --git a/arch/arm/src/sam34/sam4cm_periphclks.h b/arch/arm/src/sam34/sam4cm_periphclks.h
index 441f1ce..971f0b6 100644
--- a/arch/arm/src/sam34/sam4cm_periphclks.h
+++ b/arch/arm/src/sam34/sam4cm_periphclks.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4cm_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM4CM_PERIPHCLKS_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
@@ -118,19 +119,19 @@
#define sam_sram_disableclk() sam_disableperiph1(SAM_PID_SRAM)
#define sam_smc1_disableclk() sam_disableperiph1(SAM_PID_SMC1)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -141,9 +142,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4cm_supc.h b/arch/arm/src/sam34/sam4cm_supc.h
index b8526c9..91d5183 100644
--- a/arch/arm/src/sam34/sam4cm_supc.h
+++ b/arch/arm/src/sam34/sam4cm_supc.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4cm_supc.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -32,11 +32,11 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H
#define __ARCH_ARM_SRC_SAM34_SAM4CM_SUPC_H
@@ -47,13 +47,13 @@
#if defined(CONFIG_ARCH_CHIP_SAM4CM)
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
@@ -66,9 +66,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
uint32_t supc_get_slcd_power_mode(void);
void supc_set_slcd_power_mode(uint32_t mode);
diff --git a/arch/arm/src/sam34/sam4cm_tc.c b/arch/arm/src/sam34/sam4cm_tc.c
index 5069b18..6c61dbd 100644
--- a/arch/arm/src/sam34/sam4cm_tc.c
+++ b/arch/arm/src/sam34/sam4cm_tc.c
@@ -313,7 +313,9 @@ static const struct sam_chconfig_s g_configs[] =
static struct sam_chan_s g_channels[ENABLED_CHANNELS];
-/* TC frequency data. This table provides the frequency for each selection of TCCLK */
+/* TC frequency data.
+ * This table provides the frequency for each selection of TCCLK
+ */
#define TC_NDIVIDERS 4
#define TC_NDIVOPTIONS 5
diff --git a/arch/arm/src/sam34/sam4cm_tc.h b/arch/arm/src/sam34/sam4cm_tc.h
index 33663a3..ccc529f 100644
--- a/arch/arm/src/sam34/sam4cm_tc.h
+++ b/arch/arm/src/sam34/sam4cm_tc.h
@@ -67,6 +67,7 @@
/****************************************************************************
* Public Types
****************************************************************************/
+
/* An opaque handle used to represent a timer channel */
typedef void *TC_HANDLE;
diff --git a/arch/arm/src/sam34/sam4cm_tickless.c b/arch/arm/src/sam34/sam4cm_tickless.c
index 4f68b77..5fb1214 100644
--- a/arch/arm/src/sam34/sam4cm_tickless.c
+++ b/arch/arm/src/sam34/sam4cm_tickless.c
@@ -25,8 +25,8 @@
* is suppressed and the platform specific code is expected to provide the
* following custom functions.
*
- * void up_timer_initialize(void): Initializes the timer facilities. Called
- * early in the initialization sequence (by up_initialize()).
+ * void up_timer_initialize(void): Initializes the timer facilities.
+ * Called early in the initialization sequence (by up_initialize()).
* int up_timer_gettime(FAR struct timespec *ts): Returns the current
* time from the platform specific time source.
* int up_timer_cancel(void): Cancels the interval timer.
@@ -40,6 +40,7 @@
* logic when the interval timer expires.
*
****************************************************************************/
+
/****************************************************************************
* SAM34 Timer Usage
*
@@ -351,9 +352,10 @@ int up_timer_gettime(FAR struct timespec *ts)
int up_timer_cancel(FAR struct timespec *ts)
{
- return ONESHOT_INITIALIZED(&g_tickless.oneshot) && FREERUN_INITIALIZED(&g_tickless.freerun) ?
- sam_oneshot_cancel(&g_tickless.oneshot, &g_tickless.freerun, ts) :
- -EAGAIN;
+ return ONESHOT_INITIALIZED(&g_tickless.oneshot) &&
+ FREERUN_INITIALIZED(&g_tickless.freerun) ?
+ sam_oneshot_cancel(&g_tickless.oneshot,
+ &g_tickless.freerun, ts) : -EAGAIN;
}
/****************************************************************************
@@ -384,7 +386,8 @@ int up_timer_cancel(FAR struct timespec *ts)
int up_timer_start(FAR const struct timespec *ts)
{
return ONESHOT_INITIALIZED(&g_tickless.oneshot) ?
- sam_oneshot_start(&g_tickless.oneshot, &g_tickless.freerun, sam_oneshot_handler, NULL, ts) :
+ sam_oneshot_start(&g_tickless.oneshot,
+ &g_tickless.freerun, sam_oneshot_handler, NULL, ts) :
-EAGAIN;
}
#endif /* CONFIG_SCHED_TICKLESS */
diff --git a/arch/arm/src/sam34/sam4e_gpio.h b/arch/arm/src/sam34/sam4e_gpio.h
index 747a58c..7b1cfe9 100644
--- a/arch/arm/src/sam34/sam4e_gpio.h
+++ b/arch/arm/src/sam34/sam4e_gpio.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4e_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM4E_GPIO_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
#define GPIO_HAVE_DELAYR 1
-/* Bit-encoded input to sam_configgpio() ********************************************/
+/* Bit-encoded input to sam_configgpio() ************************************/
/* 32-bit Encoding:
*
@@ -92,7 +93,8 @@
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
# define GPIO_INT_BOTHEDGES (0)
-/* If the pin is an GPIO output, then this identifies the initial output value:
+/* If the pin is an GPIO output, then this identifies the initial output
+ * value:
*
* .... .... ...V .... ....
*/
@@ -153,23 +155,23 @@
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -180,9 +182,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4e_periphclks.h b/arch/arm/src/sam34/sam4e_periphclks.h
index 76ef9b3..17de80c 100644
--- a/arch/arm/src/sam34/sam4e_periphclks.h
+++ b/arch/arm/src/sam34/sam4e_periphclks.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4e_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM4E_PERIPHCLKS_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
@@ -128,19 +129,19 @@
#define sam_emac_disableclk() sam_disableperiph1(SAM_PID_EMAC)
#define sam_uart1_disableclk() sam_disableperiph1(SAM_PID_UART1)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -151,9 +152,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4l_clockconfig.c b/arch/arm/src/sam34/sam4l_clockconfig.c
index e462539..3702ee8 100644
--- a/arch/arm/src/sam34/sam4l_clockconfig.c
+++ b/arch/arm/src/sam34/sam4l_clockconfig.c
@@ -45,13 +45,15 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* Configuration ************************************************************/
#ifndef CONFIG_ARCH_RAMFUNCS
# error "CONFIG_ARCH_RAMFUNCS must be defined"
#endif
-/* Board/Clock Setup *******************************************************/
+/* Board/Clock Setup ********************************************************/
+
/* Verify dividers */
#if ((BOARD_CPU_SHIFT > BOARD_PBA_SHIFT) || (BOARD_CPU_SHIFT > BOARD_PBB_SHIFT) || \
@@ -185,8 +187,8 @@
/* RC80M. This might be the system clock or the source clock for the DFPLL
* or it could be the source for GCLK9 that drives PLL0.
*
- * By selecting CONFIG_SAM34_RC80M, you can also force the clock to be enabled
- * at boot time.
+ * By selecting CONFIG_SAM34_RC80M, you can also force the clock to be
+ * enabled at boot time.
*/
#if defined(CONFIG_SAM34_RC80M) || defined(BOARD_SYSCLK_SOURCE_RC80M) || \
@@ -480,15 +482,15 @@ static inline void sam_enableosc0(void)
/* Enable and configure OSC0 */
- regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE | SAM_OSC0_MODE_VALUE |
- SCIF_OSCCTRL0_OSCEN;
- putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET),
- SAM_SCIF_UNLOCK);
+ regval = SAM_OSC0_STARTUP_VALUE | SAM_OSC0_GAIN_VALUE |
+ SAM_OSC0_MODE_VALUE | SCIF_OSCCTRL0_OSCEN;
+ putreg32(SCIF_UNLOCK_KEY(0xaa) |
+ SCIF_UNLOCK_ADDR(SAM_SCIF_OSCCTRL0_OFFSET), SAM_SCIF_UNLOCK);
putreg32(regval, SAM_SCIF_OSCCTRL0);
/* Wait for OSC0 to be ready */
- while (getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0);
+ while ((getreg32(SAM_SCIF_PCLKSR) & SCIF_INT_OSC0RDY) == 0);
}
#endif
@@ -507,14 +509,16 @@ static inline void sam_enableosc32(void)
uint32_t regval;
/* Set up the OSCCTRL32 register using settings from the board.h file.
- * Also enable the oscillator and provide bother the 32KHz and 1KHz output.
+ * Also enable the oscillator and provide bother the 32KHz and 1KHz
+ * output.
*/
- regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR | SAM_OSC32_MODE_VALUE |
- BSCIF_OSCCTRL32_EN1K | BSCIF_OSCCTRL32_EN32K |
- BSCIF_OSCCTRL32_OSC32EN;
+ regval = SAM_OSC32_STARTUP_VALUE | BOARD_OSC32_SELCURR |
+ SAM_OSC32_MODE_VALUE | BSCIF_OSCCTRL32_EN1K |
+ BSCIF_OSCCTRL32_EN32K | BSCIF_OSCCTRL32_OSC32EN;
- putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET),
+ putreg32(BSCIF_UNLOCK_KEY(0xaa) |
+ BSCIF_UNLOCK_ADDR(SAM_BSCIF_OSCCTRL32_OFFSET),
SAM_BSCIF_UNLOCK);
putreg32(regval, SAM_BSCIF_OSCCTRL32);
@@ -547,7 +551,7 @@ static inline void sam_enablerc80m(void)
/* Wait for OSC32 to be ready */
- while (getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0);
+ while ((getreg32(SAM_SCIF_RC80MCR) & SCIF_RC80MCR_EN) == 0);
}
#endif
@@ -571,13 +575,14 @@ static inline void sam_enablercfast(void)
regval &= ~SCIF_RCFASTCFG_FRANGE_MASK;
regval |= (SAM_RCFAST_RANGE | SCIF_RCFASTCFG_EN);
- putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET),
+ putreg32(SCIF_UNLOCK_KEY(0xaa) |
+ SCIF_UNLOCK_ADDR(SAM_SCIF_RCFASTCFG_OFFSET),
SAM_SCIF_UNLOCK);
putreg32(regval, SAM_SCIF_RCFASTCFG);
/* Wait for RCFAST to be ready */
- while (getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0);
+ while ((getreg32(SAM_SCIF_RCFASTCFG) & SCIF_RCFASTCFG_EN) == 0);
}
#endif
@@ -601,13 +606,14 @@ static inline void sam_enablerc1m(void)
regval &= ~BSCIF_RCFASTCFG_FRANGE_MASK;
regval |= (SAM_RCFAST_RANGE | BSCIF_RCFASTCFG_EN);
- putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET),
+ putreg32(BSCIF_UNLOCK_KEY(0xaa) |
+ BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC1MCR_OFFSET),
SAM_BSCIF_UNLOCK);
putreg32(regval | BSCIF_RC1MCR_CLKOEN, SAM_BSCIF_RC1MCR);
/* Wait for RCFAST to be ready */
- while (getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0);
+ while ((getreg32(SAM_BSCIF_RC1MCR) & BSCIF_RC1MCR_CLKOEN) == 0);
}
#endif
@@ -628,13 +634,15 @@ static inline void sam_enablerc32k(void)
/* Configure and enable RC32K */
regval = getreg32(SAM_BSCIF_RC32KCR);
- putreg32(BSCIF_UNLOCK_KEY(0xaa) | BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET),
+ putreg32(BSCIF_UNLOCK_KEY(0xaa) |
+ BSCIF_UNLOCK_ADDR(SAM_BSCIF_RC32KCR_OFFSET),
SAM_BSCIF_UNLOCK);
- putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN, SAM_BSCIF_RC32KCR);
+ putreg32(regval | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN,
+ SAM_BSCIF_RC32KCR);
/* Wait for RCFAST to be ready */
- while (getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0);
+ while ((getreg32(SAM_BSCIF_RC32KCR) & BSCIF_RC32KCR_EN) == 0);
}
#endif
@@ -693,7 +701,9 @@ static inline void sam_enablepll0(void)
/* Set up the multiers and dividers */
regval = getreg32(SAM_SCIF_PLL0);
- regval &= ~(SCIF_PLL0_PLLOSC_MASK | SCIF_PLL0_PLLDIV_MASK | SCIF_PLL0_PLLMUL_MASK);
+ regval &= ~(SCIF_PLL0_PLLOSC_MASK |
+ SCIF_PLL0_PLLDIV_MASK |
+ SCIF_PLL0_PLLMUL_MASK);
regval |= ((SAM_PLL0_MUL - 1) << SCIF_PLL0_PLLMUL_SHIFT) |
(BOARD_DFLL0_DIV << SCIF_PLL0_PLLDIV_SHIFT) |
SCIF_PLL0_PLLCOUNT_MAX | SAM_PLL0_SOURCE;
@@ -797,7 +807,8 @@ static inline void sam_enabledfll0(void)
* before this function was called.
*/
- putreg32(SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET),
+ putreg32(SCIF_UNLOCK_KEY(0xaa) |
+ SCIF_UNLOCK_ADDR(SAM_SCIF_DFLL0CONF_OFFSET),
SAM_SCIF_UNLOCK);
putreg32(SCIF_DFLL0CONF_EN, SAM_SCIF_DFLL0CONF);
@@ -882,19 +893,24 @@ static inline void sam_setdividers(void)
/* Then set the divider values. */
- putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET), SAM_PM_UNLOCK);
+ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_CPUSEL_OFFSET),
+ SAM_PM_UNLOCK);
putreg32(cpusel, SAM_PM_CPUSEL);
- putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET), SAM_PM_UNLOCK);
+ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBASEL_OFFSET),
+ SAM_PM_UNLOCK);
putreg32(pbasel, SAM_PM_PBASEL);
- putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET), SAM_PM_UNLOCK);
+ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBBSEL_OFFSET),
+ SAM_PM_UNLOCK);
putreg32(pbbsel, SAM_PM_PBBSEL);
- putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET), SAM_PM_UNLOCK);
+ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBCSEL_OFFSET),
+ SAM_PM_UNLOCK);
putreg32(pbcsel, SAM_PM_PBCSEL);
- putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET), SAM_PM_UNLOCK);
+ putreg32(PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(SAM_PM_PBDSEL_OFFSET),
+ SAM_PM_UNLOCK);
putreg32(pbdsel, SAM_PM_PBDSEL);
}
@@ -981,7 +997,8 @@ static inline void sam_flash_readmode(uint32_t command)
* Description:
* Configure FLASH read mode and wait states.
*
- * Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various modes
+ * Maximum CPU frequency for 0 and 1 FLASH wait states (FWS) in various
+ * modes
* (Table 42-30 in the big data sheet).
*
* ------- ------------------- ---------- ----------
@@ -1001,7 +1018,8 @@ static inline void sam_flash_readmode(uint32_t command)
*
****************************************************************************/
-static inline void sam_flash_config(uint32_t cpuclock, uint32_t psm, bool fastwkup)
+static inline void sam_flash_config(uint32_t cpuclock,
+ uint32_t psm, bool fastwkup)
{
bool waitstate;
uint32_t command;
@@ -1178,7 +1196,6 @@ static inline void sam_usbclock(void)
#endif
#if SAM_CLOCK_USB_DIV > 0
-
u_avr32_pm_gcctrl.GCCTRL.diven = diven;
u_avr32_pm_gcctrl.GCCTRL.div = div;
#endif
@@ -1327,7 +1344,7 @@ void sam_clockconfig(void)
* already running from RCSYS.
*/
- // sam_mainclk(PM_MCCTRL_MCSEL_RCSYS);
+ /* sam_mainclk(PM_MCCTRL_MCSEL_RCSYS); */
#elif defined(BOARD_SYSCLK_SOURCE_OSC0)
/* Configure FLASH read mode and wait states */
diff --git a/arch/arm/src/sam34/sam4l_gpio.c b/arch/arm/src/sam34/sam4l_gpio.c
index a765928..89645b7 100644
--- a/arch/arm/src/sam34/sam4l_gpio.c
+++ b/arch/arm/src/sam34/sam4l_gpio.c
@@ -45,7 +45,10 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
-static const char g_portchar[4] = { 'A', 'B', 'C', 'D' };
+static const char g_portchar[4] =
+{
+ 'A', 'B', 'C', 'D'
+};
#endif
/****************************************************************************
@@ -89,7 +92,9 @@ static inline int sam_gpiopin(gpio_pinset_t cfgset)
*
****************************************************************************/
-static int sam_configinput(uintptr_t base, uint32_t pin, gpio_pinset_t cfgset)
+static int sam_configinput(uintptr_t base,
+ uint32_t pin,
+ gpio_pinset_t cfgset)
{
/* Disable interrupts on the pin */
@@ -176,9 +181,9 @@ static inline int sam_configinterrupt(uintptr_t base, uint32_t pin,
{
int ret;
- /* Just configure the pin as an input, then set the interrupt configuration.
- * Here we exploit the fact that sam_configinput() enabled both rising and
- * falling edges.
+ /* Just configure the pin as an input, then set the interrupt
+ * configuration. Here we exploit the fact that sam_configinput() enabled
+ * both rising and falling edges.
*/
ret = sam_configinput(base, pin, cfgset);
@@ -499,13 +504,14 @@ bool sam_gpioread(gpio_pinset_t pinset)
return (getreg32(base + SAM_GPIO_PVR_OFFSET) & pin) != 0;
}
-/************************************************************************************
+/****************************************************************************
* Function: sam_dumpgpio
*
* Description:
- * Dump all GPIO registers associated with the base address of the provided pinset.
+ * Dump all GPIO registers associated with the base address of the provided
+ * pinset.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_DEBUG_GPIO_INFO
int sam_dumpgpio(uint32_t pinset, const char *msg)
@@ -528,20 +534,30 @@ int sam_dumpgpio(uint32_t pinset, const char *msg)
gpioinfo("GPIO%c pinset: %08x base: %08x -- %s\n",
g_portchar[port], pinset, base, msg);
gpioinfo(" GPER: %08x PMR0: %08x PMR1: %08x PMR2: %08x\n",
- getreg32(base + SAM_GPIO_GPER_OFFSET), getreg32(base + SAM_GPIO_PMR0_OFFSET),
- getreg32(base + SAM_GPIO_PMR1_OFFSET), getreg32(base + SAM_GPIO_PMR2_OFFSET));
+ getreg32(base + SAM_GPIO_GPER_OFFSET),
+ getreg32(base + SAM_GPIO_PMR0_OFFSET),
+ getreg32(base + SAM_GPIO_PMR1_OFFSET),
+ getreg32(base + SAM_GPIO_PMR2_OFFSET));
gpioinfo(" ODER: %08x OVR: %08x PVR: %08x PUER: %08x\n",
- getreg32(base + SAM_GPIO_ODER_OFFSET), getreg32(base + SAM_GPIO_OVR_OFFSET),
- getreg32(base + SAM_GPIO_PVR_OFFSET), getreg32(base + SAM_GPIO_PUER_OFFSET));
+ getreg32(base + SAM_GPIO_ODER_OFFSET),
+ getreg32(base + SAM_GPIO_OVR_OFFSET),
+ getreg32(base + SAM_GPIO_PVR_OFFSET),
+ getreg32(base + SAM_GPIO_PUER_OFFSET));
gpioinfo(" PDER: %08x IER: %08x IMR0: %08x IMR1: %08x\n",
- getreg32(base + SAM_GPIO_PDER_OFFSET), getreg32(base + SAM_GPIO_IER_OFFSET),
- getreg32(base + SAM_GPIO_IMR0_OFFSET), getreg32(base + SAM_GPIO_IMR1_OFFSET));
+ getreg32(base + SAM_GPIO_PDER_OFFSET),
+ getreg32(base + SAM_GPIO_IER_OFFSET),
+ getreg32(base + SAM_GPIO_IMR0_OFFSET),
+ getreg32(base + SAM_GPIO_IMR1_OFFSET));
gpioinfo(" GFER: %08x IFR: %08x ODCR0: %08x ODCR1: %08x\n",
- getreg32(base + SAM_GPIO_GFER_OFFSET), getreg32(base + SAM_GPIO_IFR_OFFSET),
- getreg32(base + SAM_GPIO_ODCR0_OFFSET), getreg32(base + SAM_GPIO_ODCR1_OFFSET));
+ getreg32(base + SAM_GPIO_GFER_OFFSET),
+ getreg32(base + SAM_GPIO_IFR_OFFSET),
+ getreg32(base + SAM_GPIO_ODCR0_OFFSET),
+ getreg32(base + SAM_GPIO_ODCR1_OFFSET));
gpioinfo(" OSRR0: %08x EVER: %08x PARAM: %08x VERS: %08x\n",
- getreg32(base + SAM_GPIO_OSRR0_OFFSET), getreg32(base + SAM_GPIO_EVER_OFFSET),
- getreg32(base + SAM_GPIO_PARAMETER_OFFSET), getreg32(base + SAM_GPIO_VERSION_OFFSET));
+ getreg32(base + SAM_GPIO_OSRR0_OFFSET),
+ getreg32(base + SAM_GPIO_EVER_OFFSET),
+ getreg32(base + SAM_GPIO_PARAMETER_OFFSET),
+ getreg32(base + SAM_GPIO_VERSION_OFFSET));
leave_critical_section(flags);
return OK;
diff --git a/arch/arm/src/sam34/sam4l_gpio.h b/arch/arm/src/sam34/sam4l_gpio.h
index 2292c80..0e17280 100644
--- a/arch/arm/src/sam34/sam4l_gpio.h
+++ b/arch/arm/src/sam34/sam4l_gpio.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4l_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,26 +16,26 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM4L_GPIO_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/* Bit-encoded input to sam_configgpio() ********************************************/
+/* Bit-encoded input to sam_configgpio() ************************************/
-/* 24-bit Encoding. This could be compacted into 16-bits by making the bit usage
- * mode specific. However, by giving each bit field a unique position, we handle
- * bad combinations of properties safely.
+/* 24-bit Encoding. This could be compacted into 16-bits by making the bit
+ * usage mode specific. However, by giving each bit field a unique position,
+ * we handle bad combinations of properties safely.
*
* MODE BITFIELDS
* ------------ -----------------------------
@@ -158,7 +158,8 @@
*/
#define GPIO_DRIVE_SHIFT (14) /* Bits 14-15: Interrupting input control */
-#define GPIO_DRIVE_MASK (3 << GPIO_INT_SHIFT) /* Lowest drive strength*/
+
+#define GPIO_DRIVE_MASK (3 << GPIO_INT_SHIFT) /* Lowest drive strength */
# define GPIO_DRIVE_LOW (0 << GPIO_INT_SHIFT)
# define GPIO_DRIVE_MEDLOW (1 << GPIO_INT_SHIFT)
# define GPIO_DRIVE_MEDHIGH (2 << GPIO_INT_SHIFT)
@@ -178,7 +179,8 @@
#define GPIO_SLEW (1 << 13) /* Bit 13: Enable output slew control */
-/* If the pin is an GPIO output, then this identifies the initial output value:
+/* If the pin is an GPIO output, then this identifies the initial
+ * output value:
*
* MODE BITFIELDS
* ------------ -----------------------------
@@ -211,10 +213,12 @@
# define GPIO_INT_RISING (1 << GPIO_INT_SHIFT) /* Rising edge */
# define GPIO_INT_FALLING (2 << GPIO_INT_SHIFT) /* Falling edge */
-/* These combinations control events. These help to clean up pin definitions. */
+/* These combinations control events.
+ * These help to clean up pin definitions.
+ */
-#define GPIO_EVENT_CHANGE (GPIO_PERIPH_EVENTS | GPIO_INT_CHANGE) /* Pin change */
-#define GPIO_EVENT_RISING (GPIO_PERIPH_EVENTS | GPIO_INT_RISING) /* Rising edge */
+#define GPIO_EVENT_CHANGE (GPIO_PERIPH_EVENTS | GPIO_INT_CHANGE) /* Pin change */
+#define GPIO_EVENT_RISING (GPIO_PERIPH_EVENTS | GPIO_INT_RISING) /* Rising edge */
#define GPIO_EVENT_FALLING (GPIO_PERIPH_EVENTS | GPIO_INT_FALLING) /* Falling edge */
/* Enable input/periphal glitch filter
@@ -310,23 +314,23 @@
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
/* Must be big enough to hold the 24-bit encoding */
typedef uint32_t gpio_pinset_t;
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -337,9 +341,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4l_periphclks.c b/arch/arm/src/sam34/sam4l_periphclks.c
index fcf4b3a..1f3fb7c 100644
--- a/arch/arm/src/sam34/sam4l_periphclks.c
+++ b/arch/arm/src/sam34/sam4l_periphclks.c
@@ -37,6 +37,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* USBC source clock selection */
#ifdef CONFIG_SAM34_USBC
@@ -594,7 +595,8 @@ void sam_pbb_disableperipheral(uint32_t bitset)
* Name: sam_usbc_enableclk
*
* Description:
- * Enable clocking for the USBC using settings from the board.h header files.
+ * Enable clocking for the USBC using settings from the board.h header
+ * files.
*
* "The USBC has two bus clocks connected: One High Speed Bus clock
* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
diff --git a/arch/arm/src/sam34/sam4l_periphclks.h b/arch/arm/src/sam34/sam4l_periphclks.h
index 8c5aa12..d975a05 100644
--- a/arch/arm/src/sam34/sam4l_periphclks.h
+++ b/arch/arm/src/sam34/sam4l_periphclks.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4l_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM4L_PERIPHCLKS_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
@@ -31,9 +31,9 @@
#ifdef CONFIG_ARCH_CHIP_SAM4L
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
/* SAM4L helper macros */
@@ -212,19 +212,19 @@
#define sam_eic_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_EIC)
#define sam_picouart_disableclk() sam_pbd_disableperipheral(PM_PBDMASK_PICOUART)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -235,87 +235,93 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Name: sam_init_periphclks
*
* Description:
* Called during boot to enable clocking on all selected peripherals.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_init_periphclks(void);
-/************************************************************************************
+/****************************************************************************
* Name: sam_modifyperipheral
*
* Description:
- * This is a convenience function that is intended to be used to enable or disable
- * module clocking.
+ * This is a convenience function that is intended to be used to enable or
+ * disable module clocking.
*
- ************************************************************************************/
+ ****************************************************************************/
-void sam_modifyperipheral(uintptr_t regaddr, uint32_t clrbits, uint32_t setbits);
+void sam_modifyperipheral(uintptr_t regaddr,
+ uint32_t clrbits, uint32_t setbits);
-/************************************************************************************
+/****************************************************************************
* Name: sam_pba_modifydivmask
*
* Description:
- * This is a convenience function that is intended to be used to modify bits in
- * the PBA divided clock (DIVMASK) register.
+ * This is a convenience function that is intended to be used to modify
+ * bits in the PBA divided clock (DIVMASK) register.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pba_modifydivmask(uint32_t clrbits, uint32_t setbits);
-/************************************************************************************
+/****************************************************************************
* Name: sam_pba_enableperipheral
*
* Description:
- * This is a convenience function to enable a peripheral on the APBA bridge.
+ * This is a convenience function to enable a peripheral on the APBA
+ * bridge.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pba_enableperipheral(uint32_t bitset);
-/************************************************************************************
+/****************************************************************************
* Name: sam_pba_disableperipheral
*
* Description:
- * This is a convenience function to disable a peripheral on the APBA bridge.
+ * This is a convenience function to disable a peripheral on the APBA
+ * bridge.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pba_disableperipheral(uint32_t bitset);
-/************************************************************************************
+/****************************************************************************
* Name: sam_pbb_enableperipheral
*
* Description:
- * This is a convenience function to enable a peripheral on the APBB bridge.
+ * This is a convenience function to enable a peripheral on the APBB
+ * bridge.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pbb_enableperipheral(uint32_t bitset);
-/************************************************************************************
+/****************************************************************************
* Name: sam_pbb_disableperipheral
*
* Description:
- * This is a convenience function to disable a peripheral on the APBA bridge.
+ * This is a convenience function to disable a peripheral on the APBA
+ * bridge.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_pbb_disableperipheral(uint32_t bitset);
-/************************************************************************************
+/****************************************************************************
* Name: sam_usbc_enableclk
*
* Description:
- * Enable clocking for the USBC using settings from the board.h header files.
+ * Enable clocking for the USBC using settings from the board.h header
+ * files.
*
* "The USBC has two bus clocks connected: One High Speed Bus clock
* (CLK_USBC_AHB) and one Peripheral Bus clock (CLK_USBC_APB). These clocks
@@ -331,19 +337,19 @@ void sam_pbb_disableperipheral(uint32_t bitset);
* the SCIF module. Before using the USB, the user must ensure that the
* USB generic clock (GCLK_USBC) is enabled at 48MHz in the SCIF module."
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_SAM34_USBC
void sam_usbc_enableclk(void);
#endif
-/************************************************************************************
+/****************************************************************************
* Name: sam_usbc_disableclk
*
* Description:
* Disable clocking to the USBC.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifdef CONFIG_SAM34_USBC
void sam_usbc_disableclk(void);
diff --git a/arch/arm/src/sam34/sam4s_gpio.h b/arch/arm/src/sam34/sam4s_gpio.h
index be8f917..57197d5 100644
--- a/arch/arm/src/sam34/sam4s_gpio.h
+++ b/arch/arm/src/sam34/sam4s_gpio.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4s_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,28 +16,29 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
#define __ARCH_ARM_SRC_SAM34_SAM4S_GPIO_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
-/* Configuration ********************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
#define GPIO_HAVE_PULLDOWN 1
#define GPIO_HAVE_PERIPHCD 1
#define GPIO_HAVE_SCHMITT 1
#undef GPIO_HAVE_DELAYR
-/* Bit-encoded input to sam_configgpio() ********************************************/
+/* Bit-encoded input to sam_configgpio() ************************************/
/* 32-bit Encoding:
*
@@ -92,7 +93,8 @@
# define GPIO_INT_FALLING (_GIO_INT_AIM | _GPIO_INT_EDGE | _GPIO_INT_FL)
# define GPIO_INT_BOTHEDGES (0)
-/* If the pin is an GPIO output, then this identifies the initial output value:
+/* If the pin is an GPIO output, then this identifies the initial
+ * output value:
*
* .... .... .... V... ....
*/
@@ -151,23 +153,23 @@
#define GPIO_PIN30 (30 << GPIO_PIN_SHIFT)
#define GPIO_PIN31 (31 << GPIO_PIN_SHIFT)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
/* Must be big enough to hold the 32-bit encoding */
typedef uint32_t gpio_pinset_t;
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -178,9 +180,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam4s_periphclks.h b/arch/arm/src/sam34/sam4s_periphclks.h
index 626d62d..25b0fa3 100644
--- a/arch/arm/src/sam34/sam4s_periphclks.h
+++ b/arch/arm/src/sam34/sam4s_periphclks.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam4s_periphclks.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,23 +16,24 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H
#define __ARCH_ARM_SRC_SAM34_SAM4S_PERIPHCLKS_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <arch/irq.h>
#include "hardware/sam_pmc.h"
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
/* Helper macros */
#define sam_enableperiph0(s) putreg32((1 << (s)), SAM_PMC_PCER0)
@@ -108,19 +109,19 @@
#define sam_acc_disableclk() sam_disableperiph1(SAM_PID_ACC)
#define sam_udp_disableclk() sam_disableperiph1(SAM_PID_UDP)
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -131,9 +132,9 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam34/sam_aes.h b/arch/arm/src/sam34/sam_aes.h
index b8ad8bd..8d983e1 100644
--- a/arch/arm/src/sam34/sam_aes.h
+++ b/arch/arm/src/sam34/sam_aes.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam_aes.h
*
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
@@ -31,14 +31,14 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM_AES_H
#define __ARCH_ARM_SRC_SAM34_SAM_AES_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
@@ -52,16 +52,16 @@
# error "Unknown chip for AES"
#endif
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#endif /* __ARCH_ARM_SRC_SAM34_SAM_AES_H */
diff --git a/arch/arm/src/sam34/sam_allocateheap.c b/arch/arm/src/sam34/sam_allocateheap.c
index 08c9778..2b58ef7 100644
--- a/arch/arm/src/sam34/sam_allocateheap.c
+++ b/arch/arm/src/sam34/sam_allocateheap.c
@@ -44,6 +44,7 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* All SAM's have SRAM0. The SAM3U family also have SRAM1 and possibly
* NFCSRAM. NFCSRAM may not be used, however, if NAND support is enabled.
* In addition, the SAM3U and SAM4S have external SRAM at CS0 (EXTSRAM0).
@@ -179,7 +180,8 @@
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
- * Kernel IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
+ * Kernel IDLE thread stack. Size determined by
+ * CONFIG_IDLETHREAD_STACKSIZE.
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
@@ -196,7 +198,8 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
- uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
+ uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+ CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = CONFIG_RAM_END - ubase;
int log2;
@@ -221,7 +224,7 @@ void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
/* Allow user-mode access to the user heap memory */
- sam_mpu_uheap((uintptr_t)ubase, usize);
+ sam_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
@@ -250,7 +253,8 @@ void up_allocate_kheap(FAR void **heap_start, size_t *heap_size)
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
- uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
+ uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
+ CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = CONFIG_RAM_END - ubase;
int log2;
diff --git a/arch/arm/src/sam34/sam_clockconfig.c b/arch/arm/src/sam34/sam_clockconfig.c
index b8baa37..883e897 100644
--- a/arch/arm/src/sam34/sam_clockconfig.c
+++ b/arch/arm/src/sam34/sam_clockconfig.c
@@ -138,7 +138,8 @@ static inline void sam_supcsetup(void)
putreg32((SUPC_CR_XTALSEL | SUPR_CR_KEY), SAM_SUPC_CR);
for (delay = 0;
- (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
+ (getreg32(SAM_SUPC_SR) & SUPC_SR_OSCSEL) == 0 &&
+ delay < UINT32_MAX;
delay++);
}
}
@@ -178,10 +179,10 @@ static inline void sam_pmcsetup(void)
{
/* "When the MOSCXTEN bit and the MOSCXTCNT are written in CKGR_MOR to
* enable the main oscillator, the MOSCXTS bit in the Power Management
- * Controller Status Register (PMC_SR) is cleared and the counter starts
- * counting down on the slow clock divided by 8 from the MOSCXTCNT
- * value. ... When the counter reaches 0, the MOSCXTS bit is set,
- * indicating that the main clock is valid."
+ * Controller Status Register (PMC_SR) is cleared and the counter
+ * starts counting down on the slow clock divided by 8 from the
+ * MOSCXTCNT value. ... When the counter reaches 0, the MOSCXTS bit is
+ * set, indicating that the main clock is valid."
*/
putreg32(BOARD_CKGR_MOR, SAM_PMC_CKGR_MOR);
@@ -191,9 +192,9 @@ static inline void sam_pmcsetup(void)
/* "Switch to the main oscillator. The selection is made by writing the
* MOSCSEL bit in the Main Oscillator Register (CKGR_MOR). The switch of
* the Main Clock source is glitch free, so there is no need to run out
- * of SLCK, PLLACK or UPLLCK in order to change the selection. The MOSCSELS
- * bit of the power Management Controller Status Register (PMC_SR) allows
- * knowing when the switch sequence is done."
+ * of SLCK, PLLACK or UPLLCK in order to change the selection. The
+ * MOSCSELS bit of the power Management Controller Status Register
+ * (PMC_SR) allows knowing when the switch sequence is done."
*
* MOSCSELS: Main Oscillator Selection Status
* 0 = Selection is done
@@ -204,12 +205,12 @@ static inline void sam_pmcsetup(void)
sam_pmcwait(PMC_INT_MOSCSELS);
/* "Select the master clock. "The Master Clock selection is made by writing
- * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock Register).
- * The prescaler supports the division by a power of 2 of the selected clock
- * between 1 and 64, and the division by 3. The PRES field in PMC_MCKR programs
- * the prescaler. Each time PMC_MCKR is written to define a new Master Clock,
- * the MCKRDY bit is cleared in PMC_SR. It reads 0 until the Master Clock is
- * established.
+ * the CSS field (Clock Source Selection) in PMC_MCKR (Master Clock
+ * Register). The prescaler supports the division by a power of 2 of the
+ * selected clock between 1 and 64, and the division by 3. The PRES field
+ * in PMC_MCKR programs the prescaler. Each time PMC_MCKR is written to
+ * define a new Master Clock, the MCKRDY bit is cleared in PMC_SR. It
+ * reads 0 until the Master Clock is established.
*/
regval = getreg32(SAM_PMC_MCKR);
@@ -225,7 +226,7 @@ static inline void sam_pmcsetup(void)
* to PLLA_MMAX.
*/
- //putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR);
+ /* putreg32(PMC_PMMR_MASK, SAM_PMC_PMMR); */
#endif
/* Setup PLLA and wait for LOCKA */
@@ -340,18 +341,18 @@ static inline void sam_disabledefaultmaster(void)
* Public Functions
****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Name: sam_clockconfig
*
* Description:
- * Called to initialize the SAM3/4. This does whatever setup is needed to put the
- * SoC in a usable state. This includes the initialization of clocking using the
- * settings in board.h. (After power-on reset, the SAM3/4 is initially running on
- * a 4MHz internal RC clock). This function also performs other low-level chip
- * initialization of the chip including EFC, master clock, IRQ & watchdog
- * configuration.
+ * Called to initialize the SAM3/4. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h. (After power-on reset, the
+ * SAM3/4 is initially running on a 4MHz internal RC clock). This
+ * function also performs other low-level chip initialization of the chip
+ * including EFC, master clock, IRQ & watchdog configuration.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_clockconfig(void)
{
diff --git a/arch/arm/src/sam34/sam_clockconfig.h b/arch/arm/src/sam34/sam_clockconfig.h
index f6fb9cf..86012e7 100644
--- a/arch/arm/src/sam34/sam_clockconfig.h
+++ b/arch/arm/src/sam34/sam_clockconfig.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam_clockconfig.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,34 +16,34 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_SAM34_SAM_CLOCKCONFIG_H
-/************************************************************************************
+/****************************************************************************
* Included Files
- ************************************************************************************/
+ ****************************************************************************/
#include <nuttx/config.h>
-/************************************************************************************
+/****************************************************************************
* Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Public Types
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Inline Functions
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ASSEMBLY__
-/************************************************************************************
+/****************************************************************************
* Public Data
- ************************************************************************************/
+ ****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
@@ -54,19 +54,19 @@ extern "C"
#define EXTERN extern
#endif
-/************************************************************************************
+/****************************************************************************
* Public Function Prototypes
- ************************************************************************************/
+ ****************************************************************************/
-/************************************************************************************
+/****************************************************************************
* Name: sam_clockconfig
*
* Description:
- * Called to initialize the SAM3/4. This does whatever setup is needed to put the
- * SoC in a usable state. This includes the initialization of clocking using the
- * settings in board.h.
+ * Called to initialize the SAM3/4. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
*
- ************************************************************************************/
+ ****************************************************************************/
void sam_clockconfig(void);
diff --git a/arch/arm/src/sam34/sam_cmcc.c b/arch/arm/src/sam34/sam_cmcc.c
index 2f1c1a2..bfdd3f4 100644
--- a/arch/arm/src/sam34/sam_cmcc.c
+++ b/arch/arm/src/sam34/sam_cmcc.c
@@ -78,16 +78,16 @@
void sam_cmcc_enable(void)
{
/* "On reset, the cache controller data entries are all invalidated and the
- * cache is disabled. The cache is transparent to processor operations. The
- * cache controller is activated with its configuration registers. The
+ * cache is disabled. The cache is transparent to processor operations.
+ * The cache controller is activated with its configuration registers. The
* configuration interface is memory mapped in the private peripheral bus.
*
* "Use the following sequence to enable the cache controller.
*
- * "1. Verify that the cache controller is disabled, reading the value of the
- * CSTS (cache status) field of the CMCC_SR register.
- * "2. Enable the cache controller, writing 1 to the CEN (cache enable) field
- * of the CMCC_CTRL register."
+ * "1. Verify that the cache controller is disabled, reading the value of
+ * the CSTS (cache status) field of the CMCC_SR register.
+ * "2. Enable the cache controller, writing 1 to the CEN (cache enable)
+ * field of the CMCC_CTRL register."
*/
if ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) == 0)
@@ -160,9 +160,9 @@ void sam_cmcc_invalidate(uintptr_t start, uintptr_t end)
return;
}
- /* "When an invalidate by line command is issued the cache controller resets
- * the valid bit information of the decoded cache line. As the line is no
- * longer valid the replacement counter points to that line.
+ /* "When an invalidate by line command is issued the cache controller
+ * resets the valid bit information of the decoded cache line. As the
+ * line is no longer valid the replacement counter points to that line.
*
* "Use the following sequence to invalidate one line of cache.
*
diff --git a/arch/arm/src/sam34/sam_cmcc.h b/arch/arm/src/sam34/sam_cmcc.h
index e0b8a7a..cb3b155 100644
--- a/arch/arm/src/sam34/sam_cmcc.h
+++ b/arch/arm/src/sam34/sam_cmcc.h
@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/src/sam34/sam_cmcc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
@@ -16,14 +16,14 @@
* License for the specific language governing permissions and limitations
* under the License.
*
- ************************************************************************************/
+ ****************************************************************************/
#ifndef __ARCH_ARM_SRC_SAM34_SAM_CMCC_H
#define __ARCH_ARM_SRC_SAM34_SAM_CMCC_H
-/************************************************************************************
+/****************************************************************************
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