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Posted to commits@mynewt.apache.org by st...@apache.org on 2016/09/29 01:34:35 UTC
[28/49] incubator-mynewt-core git commit: directory re-org
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/src/ext/core_ca_mmu.h
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/src/ext/core_ca_mmu.h b/libs/cmsis-core/src/ext/core_ca_mmu.h
deleted file mode 100644
index 1fb99c5..0000000
--- a/libs/cmsis-core/src/ext/core_ca_mmu.h
+++ /dev/null
@@ -1,848 +0,0 @@
-;/**************************************************************************//**
-; * @file core_ca_mmu.h
-; * @brief MMU Startup File for
-; * VE_A9_MP Device Series
-; * @version V1.01
-; * @date 25 March 2013
-; *
-; * @note
-; *
-; ******************************************************************************/
-;/* Copyright (c) 2012 ARM LIMITED
-;
-; All rights reserved.
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-; - Redistributions of source code must retain the above copyright
-; notice, this list of conditions and the following disclaimer.
-; - Redistributions in binary form must reproduce the above copyright
-; notice, this list of conditions and the following disclaimer in the
-; documentation and/or other materials provided with the distribution.
-; - Neither the name of ARM nor the names of its contributors may be used
-; to endorse or promote products derived from this software without
-; specific prior written permission.
-; *
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
-; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-; POSSIBILITY OF SUCH DAMAGE.
-; ---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef _MMU_FUNC_H
-#define _MMU_FUNC_H
-
-#define SECTION_DESCRIPTOR (0x2)
-#define SECTION_MASK (0xFFFFFFFC)
-
-#define SECTION_TEXCB_MASK (0xFFFF8FF3)
-#define SECTION_B_SHIFT (2)
-#define SECTION_C_SHIFT (3)
-#define SECTION_TEX0_SHIFT (12)
-#define SECTION_TEX1_SHIFT (13)
-#define SECTION_TEX2_SHIFT (14)
-
-#define SECTION_XN_MASK (0xFFFFFFEF)
-#define SECTION_XN_SHIFT (4)
-
-#define SECTION_DOMAIN_MASK (0xFFFFFE1F)
-#define SECTION_DOMAIN_SHIFT (5)
-
-#define SECTION_P_MASK (0xFFFFFDFF)
-#define SECTION_P_SHIFT (9)
-
-#define SECTION_AP_MASK (0xFFFF73FF)
-#define SECTION_AP_SHIFT (10)
-#define SECTION_AP2_SHIFT (15)
-
-#define SECTION_S_MASK (0xFFFEFFFF)
-#define SECTION_S_SHIFT (16)
-
-#define SECTION_NG_MASK (0xFFFDFFFF)
-#define SECTION_NG_SHIFT (17)
-
-#define SECTION_NS_MASK (0xFFF7FFFF)
-#define SECTION_NS_SHIFT (19)
-
-
-#define PAGE_L1_DESCRIPTOR (0x1)
-#define PAGE_L1_MASK (0xFFFFFFFC)
-
-#define PAGE_L2_4K_DESC (0x2)
-#define PAGE_L2_4K_MASK (0xFFFFFFFD)
-
-#define PAGE_L2_64K_DESC (0x1)
-#define PAGE_L2_64K_MASK (0xFFFFFFFC)
-
-#define PAGE_4K_TEXCB_MASK (0xFFFFFE33)
-#define PAGE_4K_B_SHIFT (2)
-#define PAGE_4K_C_SHIFT (3)
-#define PAGE_4K_TEX0_SHIFT (6)
-#define PAGE_4K_TEX1_SHIFT (7)
-#define PAGE_4K_TEX2_SHIFT (8)
-
-#define PAGE_64K_TEXCB_MASK (0xFFFF8FF3)
-#define PAGE_64K_B_SHIFT (2)
-#define PAGE_64K_C_SHIFT (3)
-#define PAGE_64K_TEX0_SHIFT (12)
-#define PAGE_64K_TEX1_SHIFT (13)
-#define PAGE_64K_TEX2_SHIFT (14)
-
-#define PAGE_TEXCB_MASK (0xFFFF8FF3)
-#define PAGE_B_SHIFT (2)
-#define PAGE_C_SHIFT (3)
-#define PAGE_TEX_SHIFT (12)
-
-#define PAGE_XN_4K_MASK (0xFFFFFFFE)
-#define PAGE_XN_4K_SHIFT (0)
-#define PAGE_XN_64K_MASK (0xFFFF7FFF)
-#define PAGE_XN_64K_SHIFT (15)
-
-
-#define PAGE_DOMAIN_MASK (0xFFFFFE1F)
-#define PAGE_DOMAIN_SHIFT (5)
-
-#define PAGE_P_MASK (0xFFFFFDFF)
-#define PAGE_P_SHIFT (9)
-
-#define PAGE_AP_MASK (0xFFFFFDCF)
-#define PAGE_AP_SHIFT (4)
-#define PAGE_AP2_SHIFT (9)
-
-#define PAGE_S_MASK (0xFFFFFBFF)
-#define PAGE_S_SHIFT (10)
-
-#define PAGE_NG_MASK (0xFFFFF7FF)
-#define PAGE_NG_SHIFT (11)
-
-#define PAGE_NS_MASK (0xFFFFFFF7)
-#define PAGE_NS_SHIFT (3)
-
-#define OFFSET_1M (0x00100000)
-#define OFFSET_64K (0x00010000)
-#define OFFSET_4K (0x00001000)
-
-#define DESCRIPTOR_FAULT (0x00000000)
-
-/* ########################### MMU Function Access ########################### */
-/** \ingroup MMU_FunctionInterface
- \defgroup MMU_Functions MMU Functions Interface
- @{
- */
-
-/* Attributes enumerations */
-
-/* Region size attributes */
-typedef enum
-{
- SECTION,
- PAGE_4k,
- PAGE_64k,
-} mmu_region_size_Type;
-
-/* Region type attributes */
-typedef enum
-{
- NORMAL,
- DEVICE,
- SHARED_DEVICE,
- NON_SHARED_DEVICE,
- STRONGLY_ORDERED
-} mmu_memory_Type;
-
-/* Region cacheability attributes */
-typedef enum
-{
- NON_CACHEABLE,
- WB_WA,
- WT,
- WB_NO_WA,
-} mmu_cacheability_Type;
-
-/* Region parity check attributes */
-typedef enum
-{
- ECC_DISABLED,
- ECC_ENABLED,
-} mmu_ecc_check_Type;
-
-/* Region execution attributes */
-typedef enum
-{
- EXECUTE,
- NON_EXECUTE,
-} mmu_execute_Type;
-
-/* Region global attributes */
-typedef enum
-{
- GLOBAL,
- NON_GLOBAL,
-} mmu_global_Type;
-
-/* Region shareability attributes */
-typedef enum
-{
- NON_SHARED,
- SHARED,
-} mmu_shared_Type;
-
-/* Region security attributes */
-typedef enum
-{
- SECURE,
- NON_SECURE,
-} mmu_secure_Type;
-
-/* Region access attributes */
-typedef enum
-{
- NO_ACCESS,
- RW,
- READ,
-} mmu_access_Type;
-
-/* Memory Region definition */
-typedef struct RegionStruct {
- mmu_region_size_Type rg_t;
- mmu_memory_Type mem_t;
- uint8_t domain;
- mmu_cacheability_Type inner_norm_t;
- mmu_cacheability_Type outer_norm_t;
- mmu_ecc_check_Type e_t;
- mmu_execute_Type xn_t;
- mmu_global_Type g_t;
- mmu_secure_Type sec_t;
- mmu_access_Type priv_t;
- mmu_access_Type user_t;
- mmu_shared_Type sh_t;
-
-} mmu_region_attributes_Type;
-
-/** \brief Set section execution-never attribute
-
- The function sets section execution-never attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] xn Section execution-never attribute : EXECUTE , NON_EXECUTE.
-
- \return 0
- */
-__STATIC_INLINE int __xn_section(uint32_t *descriptor_l1, mmu_execute_Type xn)
-{
- *descriptor_l1 &= SECTION_XN_MASK;
- *descriptor_l1 |= ((xn & 0x1) << SECTION_XN_SHIFT);
- return 0;
-}
-
-/** \brief Set section domain
-
- The function sets section domain
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] domain Section domain
-
- \return 0
- */
-__STATIC_INLINE int __domain_section(uint32_t *descriptor_l1, uint8_t domain)
-{
- *descriptor_l1 &= SECTION_DOMAIN_MASK;
- *descriptor_l1 |= ((domain & 0xF) << SECTION_DOMAIN_SHIFT);
- return 0;
-}
-
-/** \brief Set section parity check
-
- The function sets section parity check
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
- \return 0
- */
-__STATIC_INLINE int __p_section(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
- *descriptor_l1 &= SECTION_P_MASK;
- *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
- return 0;
-}
-
-/** \brief Set section access privileges
-
- The function sets section access privileges
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] user User Level Access: NO_ACCESS, RW, READ
- \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
- \param [in] afe Access flag enable
-
- \return 0
- */
-__STATIC_INLINE int __ap_section(uint32_t *descriptor_l1, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-{
- uint32_t ap = 0;
-
- if (afe == 0) { //full access
- if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
- else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == READ)) { ap = 0x2; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x6; }
- }
-
- else { //Simplified access
- if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x7; }
- }
-
- *descriptor_l1 &= SECTION_AP_MASK;
- *descriptor_l1 |= (ap & 0x3) << SECTION_AP_SHIFT;
- *descriptor_l1 |= ((ap & 0x4)>>2) << SECTION_AP2_SHIFT;
-
- return 0;
-}
-
-/** \brief Set section shareability
-
- The function sets section shareability
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] s_bit Section shareability: NON_SHARED, SHARED
-
- \return 0
- */
-__STATIC_INLINE int __shared_section(uint32_t *descriptor_l1, mmu_shared_Type s_bit)
-{
- *descriptor_l1 &= SECTION_S_MASK;
- *descriptor_l1 |= ((s_bit & 0x1) << SECTION_S_SHIFT);
- return 0;
-}
-
-/** \brief Set section Global attribute
-
- The function sets section Global attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] g_bit Section attribute: GLOBAL, NON_GLOBAL
-
- \return 0
- */
-__STATIC_INLINE int __global_section(uint32_t *descriptor_l1, mmu_global_Type g_bit)
-{
- *descriptor_l1 &= SECTION_NG_MASK;
- *descriptor_l1 |= ((g_bit & 0x1) << SECTION_NG_SHIFT);
- return 0;
-}
-
-/** \brief Set section Security attribute
-
- The function sets section Global attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] s_bit Section Security attribute: SECURE, NON_SECURE
-
- \return 0
- */
-__STATIC_INLINE int __secure_section(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
- *descriptor_l1 &= SECTION_NS_MASK;
- *descriptor_l1 |= ((s_bit & 0x1) << SECTION_NS_SHIFT);
- return 0;
-}
-
-/* Page 4k or 64k */
-/** \brief Set 4k/64k page execution-never attribute
-
- The function sets 4k/64k page execution-never attribute
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] xn Page execution-never attribute : EXECUTE , NON_EXECUTE.
- \param [in] page Page size: PAGE_4k, PAGE_64k,
-
- \return 0
- */
-__STATIC_INLINE int __xn_page(uint32_t *descriptor_l2, mmu_execute_Type xn, mmu_region_size_Type page)
-{
- if (page == PAGE_4k)
- {
- *descriptor_l2 &= PAGE_XN_4K_MASK;
- *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_4K_SHIFT);
- }
- else
- {
- *descriptor_l2 &= PAGE_XN_64K_MASK;
- *descriptor_l2 |= ((xn & 0x1) << PAGE_XN_64K_SHIFT);
- }
- return 0;
-}
-
-/** \brief Set 4k/64k page domain
-
- The function sets 4k/64k page domain
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] domain Page domain
-
- \return 0
- */
-__STATIC_INLINE int __domain_page(uint32_t *descriptor_l1, uint8_t domain)
-{
- *descriptor_l1 &= PAGE_DOMAIN_MASK;
- *descriptor_l1 |= ((domain & 0xf) << PAGE_DOMAIN_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page parity check
-
- The function sets 4k/64k page parity check
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] p_bit Parity check: ECC_DISABLED, ECC_ENABLED
-
- \return 0
- */
-__STATIC_INLINE int __p_page(uint32_t *descriptor_l1, mmu_ecc_check_Type p_bit)
-{
- *descriptor_l1 &= SECTION_P_MASK;
- *descriptor_l1 |= ((p_bit & 0x1) << SECTION_P_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page access privileges
-
- The function sets 4k/64k page access privileges
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] user User Level Access: NO_ACCESS, RW, READ
- \param [in] priv Privilege Level Access: NO_ACCESS, RW, READ
- \param [in] afe Access flag enable
-
- \return 0
- */
-__STATIC_INLINE int __ap_page(uint32_t *descriptor_l2, mmu_access_Type user, mmu_access_Type priv, uint32_t afe)
-{
- uint32_t ap = 0;
-
- if (afe == 0) { //full access
- if ((priv == NO_ACCESS) && (user == NO_ACCESS)) { ap = 0x0; }
- else if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == READ)) { ap = 0x2; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x6; }
- }
-
- else { //Simplified access
- if ((priv == RW) && (user == NO_ACCESS)) { ap = 0x1; }
- else if ((priv == RW) && (user == RW)) { ap = 0x3; }
- else if ((priv == READ) && (user == NO_ACCESS)) { ap = 0x5; }
- else if ((priv == READ) && (user == READ)) { ap = 0x7; }
- }
-
- *descriptor_l2 &= PAGE_AP_MASK;
- *descriptor_l2 |= (ap & 0x3) << PAGE_AP_SHIFT;
- *descriptor_l2 |= ((ap & 0x4)>>2) << PAGE_AP2_SHIFT;
-
- return 0;
-}
-
-/** \brief Set 4k/64k page shareability
-
- The function sets 4k/64k page shareability
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] s_bit 4k/64k page shareability: NON_SHARED, SHARED
-
- \return 0
- */
-__STATIC_INLINE int __shared_page(uint32_t *descriptor_l2, mmu_shared_Type s_bit)
-{
- *descriptor_l2 &= PAGE_S_MASK;
- *descriptor_l2 |= ((s_bit & 0x1) << PAGE_S_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page Global attribute
-
- The function sets 4k/64k page Global attribute
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] g_bit 4k/64k page attribute: GLOBAL, NON_GLOBAL
-
- \return 0
- */
-__STATIC_INLINE int __global_page(uint32_t *descriptor_l2, mmu_global_Type g_bit)
-{
- *descriptor_l2 &= PAGE_NG_MASK;
- *descriptor_l2 |= ((g_bit & 0x1) << PAGE_NG_SHIFT);
- return 0;
-}
-
-/** \brief Set 4k/64k page Security attribute
-
- The function sets 4k/64k page Global attribute
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] s_bit 4k/64k page Security attribute: SECURE, NON_SECURE
-
- \return 0
- */
-__STATIC_INLINE int __secure_page(uint32_t *descriptor_l1, mmu_secure_Type s_bit)
-{
- *descriptor_l1 &= PAGE_NS_MASK;
- *descriptor_l1 |= ((s_bit & 0x1) << PAGE_NS_SHIFT);
- return 0;
-}
-
-
-/** \brief Set Section memory attributes
-
- The function sets section memory attributes
-
- \param [out] descriptor_l1 L1 descriptor.
- \param [in] mem Section memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
- \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
- \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
- \return 0
- */
-__STATIC_INLINE int __memory_section(uint32_t *descriptor_l1, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner)
-{
- *descriptor_l1 &= SECTION_TEXCB_MASK;
-
- if (STRONGLY_ORDERED == mem)
- {
- return 0;
- }
- else if (SHARED_DEVICE == mem)
- {
- *descriptor_l1 |= (1 << SECTION_B_SHIFT);
- }
- else if (NON_SHARED_DEVICE == mem)
- {
- *descriptor_l1 |= (1 << SECTION_TEX1_SHIFT);
- }
- else if (NORMAL == mem)
- {
- *descriptor_l1 |= 1 << SECTION_TEX2_SHIFT;
- switch(inner)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l1 |= (1 << SECTION_B_SHIFT);
- break;
- case WT:
- *descriptor_l1 |= 1 << SECTION_C_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l1 |= (1 << SECTION_B_SHIFT) | (1 << SECTION_C_SHIFT);
- break;
- }
- switch(outer)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT);
- break;
- case WT:
- *descriptor_l1 |= 1 << SECTION_TEX1_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l1 |= (1 << SECTION_TEX0_SHIFT) | (1 << SECTION_TEX0_SHIFT);
- break;
- }
- }
-
- return 0;
-}
-
-/** \brief Set 4k/64k page memory attributes
-
- The function sets 4k/64k page memory attributes
-
- \param [out] descriptor_l2 L2 descriptor.
- \param [in] mem 4k/64k page memory type: NORMAL, DEVICE, SHARED_DEVICE, NON_SHARED_DEVICE, STRONGLY_ORDERED
- \param [in] outer Outer cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
- \param [in] inner Inner cacheability: NON_CACHEABLE, WB_WA, WT, WB_NO_WA,
-
- \return 0
- */
-__STATIC_INLINE int __memory_page(uint32_t *descriptor_l2, mmu_memory_Type mem, mmu_cacheability_Type outer, mmu_cacheability_Type inner, mmu_region_size_Type page)
-{
- *descriptor_l2 &= PAGE_4K_TEXCB_MASK;
-
- if (page == PAGE_64k)
- {
- //same as section
- __memory_section(descriptor_l2, mem, outer, inner);
- }
- else
- {
- if (STRONGLY_ORDERED == mem)
- {
- return 0;
- }
- else if (SHARED_DEVICE == mem)
- {
- *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
- }
- else if (NON_SHARED_DEVICE == mem)
- {
- *descriptor_l2 |= (1 << PAGE_4K_TEX1_SHIFT);
- }
- else if (NORMAL == mem)
- {
- *descriptor_l2 |= 1 << PAGE_4K_TEX2_SHIFT;
- switch(inner)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT);
- break;
- case WT:
- *descriptor_l2 |= 1 << PAGE_4K_C_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l2 |= (1 << PAGE_4K_B_SHIFT) | (1 << PAGE_4K_C_SHIFT);
- break;
- }
- switch(outer)
- {
- case NON_CACHEABLE:
- break;
- case WB_WA:
- *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT);
- break;
- case WT:
- *descriptor_l2 |= 1 << PAGE_4K_TEX1_SHIFT;
- break;
- case WB_NO_WA:
- *descriptor_l2 |= (1 << PAGE_4K_TEX0_SHIFT) | (1 << PAGE_4K_TEX0_SHIFT);
- break;
- }
- }
- }
-
- return 0;
-}
-
-/** \brief Create a L1 section descriptor
-
- The function creates a section descriptor.
-
- Assumptions:
- - 16MB super sections not suported
- - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- - Functions always return 0
-
- \param [out] descriptor L1 descriptor
- \param [out] descriptor2 L2 descriptor
- \param [in] reg Section attributes
-
- \return 0
- */
-__STATIC_INLINE int __get_section_descriptor(uint32_t *descriptor, mmu_region_attributes_Type reg)
-{
- *descriptor = 0;
-
- __memory_section(descriptor, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t);
- __xn_section(descriptor,reg.xn_t);
- __domain_section(descriptor, reg.domain);
- __p_section(descriptor, reg.e_t);
- __ap_section(descriptor, reg.priv_t, reg.user_t, 1);
- __shared_section(descriptor,reg.sh_t);
- __global_section(descriptor,reg.g_t);
- __secure_section(descriptor,reg.sec_t);
- *descriptor &= SECTION_MASK;
- *descriptor |= SECTION_DESCRIPTOR;
-
- return 0;
-
-}
-
-
-/** \brief Create a L1 and L2 4k/64k page descriptor
-
- The function creates a 4k/64k page descriptor.
- Assumptions:
- - TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor
- - Functions always return 0
-
- \param [out] descriptor L1 descriptor
- \param [out] descriptor2 L2 descriptor
- \param [in] reg 4k/64k page attributes
-
- \return 0
- */
-__STATIC_INLINE int __get_page_descriptor(uint32_t *descriptor, uint32_t *descriptor2, mmu_region_attributes_Type reg)
-{
- *descriptor = 0;
- *descriptor2 = 0;
-
- switch (reg.rg_t)
- {
- case PAGE_4k:
- __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_4k);
- __xn_page(descriptor2, reg.xn_t, PAGE_4k);
- __domain_page(descriptor, reg.domain);
- __p_page(descriptor, reg.e_t);
- __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
- __shared_page(descriptor2,reg.sh_t);
- __global_page(descriptor2,reg.g_t);
- __secure_page(descriptor,reg.sec_t);
- *descriptor &= PAGE_L1_MASK;
- *descriptor |= PAGE_L1_DESCRIPTOR;
- *descriptor2 &= PAGE_L2_4K_MASK;
- *descriptor2 |= PAGE_L2_4K_DESC;
- break;
-
- case PAGE_64k:
- __memory_page(descriptor2, reg.mem_t, reg.outer_norm_t, reg.inner_norm_t, PAGE_64k);
- __xn_page(descriptor2, reg.xn_t, PAGE_64k);
- __domain_page(descriptor, reg.domain);
- __p_page(descriptor, reg.e_t);
- __ap_page(descriptor2, reg.priv_t, reg.user_t, 1);
- __shared_page(descriptor2,reg.sh_t);
- __global_page(descriptor2,reg.g_t);
- __secure_page(descriptor,reg.sec_t);
- *descriptor &= PAGE_L1_MASK;
- *descriptor |= PAGE_L1_DESCRIPTOR;
- *descriptor2 &= PAGE_L2_64K_MASK;
- *descriptor2 |= PAGE_L2_64K_DESC;
- break;
-
- case SECTION:
- //error
- break;
-
- }
-
- return 0;
-
-}
-
-/** \brief Create a 1MB Section
-
- \param [in] ttb Translation table base address
- \param [in] base_address Section base address
- \param [in] count Number of sections to create
- \param [in] descriptor_l1 L1 descriptor (region attributes)
-
- */
-__STATIC_INLINE void __TTSection(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1)
-{
- uint32_t offset;
- uint32_t entry;
- uint32_t i;
-
- offset = base_address >> 20;
- entry = (base_address & 0xFFF00000) | descriptor_l1;
-
- //4 bytes aligned
- ttb = ttb + offset;
-
- for (i = 0; i < count; i++ )
- {
- //4 bytes aligned
- *ttb++ = entry;
- entry += OFFSET_1M;
- }
-}
-
-/** \brief Create a 4k page entry
-
- \param [in] ttb L1 table base address
- \param [in] base_address 4k base address
- \param [in] count Number of 4k pages to create
- \param [in] descriptor_l1 L1 descriptor (region attributes)
- \param [in] ttb_l2 L2 table base address
- \param [in] descriptor_l2 L2 descriptor (region attributes)
-
- */
-__STATIC_INLINE void __TTPage_4k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
-
- uint32_t offset, offset2;
- uint32_t entry, entry2;
- uint32_t i;
-
-
- offset = base_address >> 20;
- entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
- //4 bytes aligned
- ttb += offset;
- //create l1_entry
- *ttb = entry;
-
- offset2 = (base_address & 0xff000) >> 12;
- ttb_l2 += offset2;
- entry2 = (base_address & 0xFFFFF000) | descriptor_l2;
- for (i = 0; i < count; i++ )
- {
- //4 bytes aligned
- *ttb_l2++ = entry2;
- entry2 += OFFSET_4K;
- }
-}
-
-/** \brief Create a 64k page entry
-
- \param [in] ttb L1 table base address
- \param [in] base_address 64k base address
- \param [in] count Number of 64k pages to create
- \param [in] descriptor_l1 L1 descriptor (region attributes)
- \param [in] ttb_l2 L2 table base address
- \param [in] descriptor_l2 L2 descriptor (region attributes)
-
- */
-__STATIC_INLINE void __TTPage_64k(uint32_t *ttb, uint32_t base_address, uint32_t count, uint32_t descriptor_l1, uint32_t *ttb_l2, uint32_t descriptor_l2 )
-{
- uint32_t offset, offset2;
- uint32_t entry, entry2;
- uint32_t i,j;
-
-
- offset = base_address >> 20;
- entry = ((int)ttb_l2 & 0xFFFFFC00) | descriptor_l1;
-
- //4 bytes aligned
- ttb += offset;
- //create l1_entry
- *ttb = entry;
-
- offset2 = (base_address & 0xff000) >> 12;
- ttb_l2 += offset2;
- entry2 = (base_address & 0xFFFF0000) | descriptor_l2;
- for (i = 0; i < count; i++ )
- {
- //create 16 entries
- for (j = 0; j < 16; j++)
- //4 bytes aligned
- *ttb_l2++ = entry2;
- entry2 += OFFSET_64K;
- }
-}
-
-/*@} end of MMU_Functions */
-#endif
-
-#ifdef __cplusplus
-}
-#endif
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/6a7432f4/libs/cmsis-core/src/ext/core_cm0.h
----------------------------------------------------------------------
diff --git a/libs/cmsis-core/src/ext/core_cm0.h b/libs/cmsis-core/src/ext/core_cm0.h
deleted file mode 100644
index dc821ba..0000000
--- a/libs/cmsis-core/src/ext/core_cm0.h
+++ /dev/null
@@ -1,682 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif