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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/03/14 06:19:41 UTC
[GitHub] [incubator-nuttx] anchao commented on a change in pull request #5734: arm/armv7-a/r: set the default CPU mode to System
anchao commented on a change in pull request #5734:
URL: https://github.com/apache/incubator-nuttx/pull/5734#discussion_r825620627
##########
File path: arch/arm/src/armv7-r/arm_vectors.S
##########
@@ -233,53 +174,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
/* Get the values for r15(pc) and CPSR in r3 and r4 */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
-#ifdef CONFIG_BUILD_PROTECTED
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lsvcentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lsvccontinue
-
-.Lsvcentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lsvccontinue:
-
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0
+
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -279,53 +220,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
/* Get the values for r15(pc) and CPSR in r3 and r4 */
mov r3, r14 /* Save r14 as the PC as well */
mrs r4, spsr /* Get the saved CPSR */
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lsvcentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lsvccontinue
-
-.Lsvcentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lsvccontinue:
-
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0
+
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -141,50 +141,15 @@ arm_vectorirq:
sub r3, lr, #4
mrs r4, spsr
- /* Then switch back to SVC mode */
+ /* Then switch back to SYS mode */
#ifdef CONFIG_ARMV7A_DECODEFIQ
- orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
#else
- orr r0, r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ orr r0, r0, #(PSR_MODE_SYS | PSR_I_BIT)
#endif
msr cpsr_c, r0
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Lirqentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Lirqcontinue
-
-.Lirqentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Lirqcontinue:
-
-#else
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -346,46 +240,11 @@ arm_vectordata:
sub r3, lr, #8
mrs r4, spsr
- /* Then switch back to SVC mode */
+ /* Then switch back to SYS mode */
- mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+ mov r0, #(PSR_MODE_SYS | PSR_I_BIT)
msr cpsr_c, r0
-#ifdef CONFIG_BUILD_KERNEL
- /* Did we enter from user mode? If so then we need get the values of
- * USER mode r13(sp) and r14(lr).
- */
-
- and r1, r4, #PSR_MODE_MASK /* Interrupted mode */
- cmp r1, #PSR_MODE_USR /* User mode? */
- bne .Ldabtentersvc /* Branch if not user mode */
-
- /* ldmia with ^ will return the user mode registers (provided that r15
- * is not in the register list).
- */
-
- add r0, sp, #(4*REG_SP) /* Offset to sp/lr storage */
- stmia r0, {r13, r14}^ /* Save user mode r13(sp) and r14(lr) */
- add r0, sp, #(4*REG_R15) /* Offset to pc/cpsr storage */
- stmia r0, {r3, r4} /* Save r15(pc), and the CPSR */
- b .Ldabtcontinue
-
-.Ldabtentersvc:
- /* Otherwise, get the correct values of SVC r13(sp) and r14(lr) in r1
- * and r2.
- */
-
- add r1, sp, #XCPTCONTEXT_SIZE
- mov r2, r14
-
- /* Save r13(sp), r14(lr), r15(pc), and the CPSR */
-
- add r0, sp, #(4*REG_SP) /* Offset to pc, cpsr storage */
- stmia r0, {r1-r4}
-
-.Ldabtcontinue:
-
-#else
/* Get the correct values of SVC r13(sp) and r14(lr) in r1 and r2 */
Review comment:
Done
##########
File path: arch/arm/src/armv7-a/arm_vectors.S
##########
@@ -279,53 +220,39 @@ arm_vectorirq:
arm_vectorsvc:
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r13, #(PSR_MODE_SYS | PSR_I_BIT)
+#endif
+ msr cpsr_c, r13 /* Switch to SYS mode */
+
/* Create a context structure. First set aside a stack frame
* and store r0-r12 into the frame.
*/
sub sp, sp, #XCPTCONTEXT_SIZE
- stmia sp, {r0-r12} /* Save the SVC mode regs */
+ stmia sp, {r0-r12} /* Save the SYS mode regs */
+
+#ifdef CONFIG_ARMV7A_DECODEFIQ
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT)
+#else
+ mov r0, #(PSR_MODE_SVC | PSR_I_BIT)
+#endif
+ msr cpsr_c, r0 /* Switch back IRQ mode */
Review comment:
Done
##########
File path: arch/arm/src/arm/arm_vectors.S
##########
@@ -207,54 +147,33 @@ arm_vectorirq:
.type arm_vectorsvc, %function
arm_vectorsvc:
+ /* On entry, we are in IRQ mode. We are free to use the IRQ mode r13
+ * and r14.
Review comment:
Done
--
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