[GitHub] [tvm] alter-xp commented on pull request #12534: [Docker][CI][RISC-V] Build riscv-isa-sim (spike) in ci_riscv Docker image to enable RISC-V unit testing

[GitBox <gi...@apache.org>]

alter-xp commented on PR #12534:
URL: https://github.com/apache/tvm/pull/12534#issuecomment-1223472292

   @PhilippvK @areusch 
   > cc @alter-xp can you take a look at the compiler used here and see if it would also work for you (or whether there's one in Zephyr we should consider)?
   for baremetal we have the other newlib toolchain. Its instruction support is the same as that of Linux tools.It may solve the compilation problem here.
   
   > I got in touch with @alter-xp a while ago regarding the multilib limitations in their toolchain but if i remember correctly I did not get a response.
   I'm sorry I didn't fully understand your question at that time. you can try this tool [Xuantie-900-gcc-elf-newlib-x86_64-V2.6.0-20220715.tar.gz](https://occ-oss-prod.oss-cn-hangzhou.aliyuncs.com/resource//1659318201401/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.0-20220715.tar.gz)
   
   > Having a single toolchain for both strategies is desirable to keep maintenance low, but not a requirement for now IMHO.
   It should be a common practice in the industry to provide two sets of compilation tools for baremetal and Linux driven.
   


-- 
This is an automated message from the Apache Git Service.
To respond to the message, please log on to GitHub and use the
URL above to go to the specific comment.

To unsubscribe, e-mail: commits-unsubscribe@tvm.apache.org

For queries about this service, please contact Infrastructure at:
users@infra.apache.org