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Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/09/21 10:07:10 UTC
[incubator-nuttx] branch master updated (f4812e0a83 -> 6903f02d41)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from f4812e0a83 net: Implement SO_RCVBUF and SO_SNDBUF for getsockopt
new c866b6be9a armv7a/r: add common operation CP15_SET/GET()
new 6d92810d5a armv7a/r: refact cp15_cache functions
new 3477c347e8 armv7a/r: add isb to cp15_invalidate_icache()
new 6903f02d41 armv7-r: add VBAR cp15 opearation
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/armv7-a/Make.defs | 8 +-
arch/arm/src/armv7-a/arm_scu.c | 97 +-------
arch/arm/src/armv7-a/arm_timer.c | 80 +------
arch/arm/src/armv7-a/barriers.h | 2 +
arch/arm/src/armv7-a/cp15.h | 72 +++++-
arch/arm/src/armv7-a/cp15_cache_size.S | 85 -------
arch/arm/src/armv7-a/cp15_cacheops.c | 245 ++++++++++++++++++++
arch/arm/src/armv7-a/cp15_cacheops.h | 171 ++++----------
arch/arm/src/armv7-a/cp15_clean_dcache.S | 116 ----------
arch/arm/src/armv7-a/cp15_clean_dcache_all.S | 127 -----------
arch/arm/src/armv7-a/cp15_coherent_dcache.S | 138 ------------
arch/arm/src/armv7-a/cp15_flush_dcache.S | 116 ----------
arch/arm/src/armv7-a/cp15_flush_dcache_all.S | 128 -----------
arch/arm/src/armv7-a/cp15_invalidate_dcache.S | 123 ----------
arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S | 128 -----------
arch/arm/src/armv7-a/mmu.h | 116 ++++------
arch/arm/src/armv7-a/sctlr.h | 259 ++++------------------
arch/arm/src/armv7-r/Make.defs | 9 +-
arch/arm/src/armv7-r/arm_timer.c | 80 +------
arch/arm/src/armv7-r/barriers.h | 2 +
arch/arm/src/armv7-r/cp15.h | 85 ++++++-
arch/arm/src/armv7-r/cp15_cache_size.S | 84 -------
arch/arm/src/armv7-r/cp15_cacheops.c | 245 ++++++++++++++++++++
arch/arm/src/armv7-r/cp15_cacheops.h | 169 ++++----------
arch/arm/src/armv7-r/cp15_clean_dcache.S | 116 ----------
arch/arm/src/armv7-r/cp15_clean_dcache_all.S | 129 -----------
arch/arm/src/armv7-r/cp15_coherent_dcache.S | 140 ------------
arch/arm/src/armv7-r/cp15_flush_dcache.S | 116 ----------
arch/arm/src/armv7-r/cp15_flush_dcache_all.S | 129 -----------
arch/arm/src/armv7-r/cp15_invalidate_dcache.S | 123 ----------
arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S | 128 -----------
arch/arm/src/armv7-r/mpu.h | 71 +-----
arch/arm/src/armv7-r/sctlr.h | 257 +++++----------------
33 files changed, 891 insertions(+), 3003 deletions(-)
delete mode 100644 arch/arm/src/armv7-a/cp15_cache_size.S
create mode 100644 arch/arm/src/armv7-a/cp15_cacheops.c
delete mode 100644 arch/arm/src/armv7-a/cp15_clean_dcache.S
delete mode 100644 arch/arm/src/armv7-a/cp15_clean_dcache_all.S
delete mode 100644 arch/arm/src/armv7-a/cp15_coherent_dcache.S
delete mode 100644 arch/arm/src/armv7-a/cp15_flush_dcache.S
delete mode 100644 arch/arm/src/armv7-a/cp15_flush_dcache_all.S
delete mode 100644 arch/arm/src/armv7-a/cp15_invalidate_dcache.S
delete mode 100644 arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
delete mode 100644 arch/arm/src/armv7-r/cp15_cache_size.S
create mode 100644 arch/arm/src/armv7-r/cp15_cacheops.c
delete mode 100644 arch/arm/src/armv7-r/cp15_clean_dcache.S
delete mode 100644 arch/arm/src/armv7-r/cp15_clean_dcache_all.S
delete mode 100644 arch/arm/src/armv7-r/cp15_coherent_dcache.S
delete mode 100644 arch/arm/src/armv7-r/cp15_flush_dcache.S
delete mode 100644 arch/arm/src/armv7-r/cp15_flush_dcache_all.S
delete mode 100644 arch/arm/src/armv7-r/cp15_invalidate_dcache.S
delete mode 100644 arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
[incubator-nuttx] 03/04: armv7a/r: add isb to cp15_invalidate_icache()
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 3477c347e805c74e3879b408156dbc817f9cd45a
Author: ligd <li...@xiaomi.com>
AuthorDate: Fri Sep 16 23:29:37 2022 +0800
armv7a/r: add isb to cp15_invalidate_icache()
Incase invalidate_icache hasn't done
Signed-off-by: ligd <li...@xiaomi.com>
---
arch/arm/src/armv7-a/cp15_cacheops.h | 2 ++
arch/arm/src/armv7-r/cp15_cacheops.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h
index cf827c88d8..63a495a4d6 100644
--- a/arch/arm/src/armv7-a/cp15_cacheops.h
+++ b/arch/arm/src/armv7-a/cp15_cacheops.h
@@ -339,6 +339,7 @@
.macro cp15_invalidate_icache, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */
+ isb
.endm
/****************************************************************************
@@ -679,6 +680,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
static inline void cp15_invalidate_icache(void)
{
CP15_SET(ICIALLU, 0);
+ ARM_ISB();
}
/****************************************************************************
diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h
index 1be45e32e4..dca33154e3 100644
--- a/arch/arm/src/armv7-r/cp15_cacheops.h
+++ b/arch/arm/src/armv7-r/cp15_cacheops.h
@@ -346,6 +346,7 @@
.macro cp15_invalidate_icache, tmp
mov \tmp, #0
mrc p15, 0, \tmp, c7, c5, 0 /* ICIALLU */
+ isb
.endm
/****************************************************************************
@@ -686,6 +687,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
static inline void cp15_invalidate_icache(void)
{
CP15_SET(ICIALLU, 0);
+ ARM_ISB();
}
/****************************************************************************
[incubator-nuttx] 01/04: armv7a/r: add common operation CP15_SET/GET()
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit c866b6be9ae5af8516b55008fe307810b4077def
Author: ligd <li...@xiaomi.com>
AuthorDate: Thu Sep 15 22:10:12 2022 +0800
armv7a/r: add common operation CP15_SET/GET()
Signed-off-by: ligd <li...@xiaomi.com>
---
arch/arm/src/armv7-a/arm_scu.c | 97 +------------
arch/arm/src/armv7-a/arm_timer.c | 80 ++---------
arch/arm/src/armv7-a/barriers.h | 2 +
arch/arm/src/armv7-a/cp15.h | 72 +++++++++-
arch/arm/src/armv7-a/cp15_cacheops.h | 169 +++++------------------
arch/arm/src/armv7-a/mmu.h | 116 ++++++----------
arch/arm/src/armv7-a/sctlr.h | 259 +++++++----------------------------
arch/arm/src/armv7-r/arm_timer.c | 80 ++---------
arch/arm/src/armv7-r/cp15.h | 82 +++++++++--
arch/arm/src/armv7-r/cp15_cacheops.h | 167 +++++-----------------
arch/arm/src/armv7-r/mpu.h | 71 ++--------
arch/arm/src/armv7-r/sctlr.h | 257 ++++++++--------------------------
12 files changed, 388 insertions(+), 1064 deletions(-)
diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c
index 9f889ecfbf..2668e88896 100755
--- a/arch/arm/src/armv7-a/arm_scu.c
+++ b/arch/arm/src/armv7-a/arm_scu.c
@@ -31,94 +31,7 @@
#include "barriers.h"
#include "sctlr.h"
#include "scu.h"
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: arm_get_sctlr
- *
- * Description:
- * Get the contents of the SCTLR register
- *
- ****************************************************************************/
-
-static inline uint32_t arm_get_sctlr(void)
-{
- uint32_t sctlr;
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c1, c0, 0\n" /* Read SCTLR */
- : "=r"(sctlr)
- :
- :
- );
-
- return sctlr;
-}
-
-/****************************************************************************
- * Name: arm_set_sctlr
- *
- * Description:
- * Set the contents of the SCTLR register
- *
- ****************************************************************************/
-
-static inline void arm_set_sctlr(uint32_t sctlr)
-{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c1, c0, 0\n" /* Write SCTLR */
- :
- : "r"(sctlr)
- :
- );
-}
-
-/****************************************************************************
- * Name: arm_get_actlr
- *
- * Description:
- * Get the contents of the ACTLR register
- *
- ****************************************************************************/
-
-static inline uint32_t arm_get_actlr(void)
-{
- uint32_t actlr;
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c1, c0, 1\n" /* Read ACTLR */
- : "=r"(actlr)
- :
- :
- );
-
- return actlr;
-}
-
-/****************************************************************************
- * Name: arm_set_actlr
- *
- * Description:
- * Set the contents of the ACTLR register
- *
- ****************************************************************************/
-
-static inline void arm_set_actlr(uint32_t actlr)
-{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c1, c0, 1\n" /* Write ACTLR */
- :
- : "r"(actlr)
- :
- );
-}
+#include "cp15.h"
/****************************************************************************
* Public Functions
@@ -195,14 +108,14 @@ void arm_enable_smp(int cpu)
* FW - Cache and TLB maintenance broadcast.
*/
- regval = arm_get_actlr();
+ regval = CP15_GET(ACTLR);
regval |= ACTLR_SMP;
#ifdef CONFIG_ARCH_CORTEXA9
regval |= ACTLR_FW;
#endif
- arm_set_actlr(regval);
+ CP15_SET(ACTLR, regval);
- regval = arm_get_sctlr();
+ regval = CP15_GET(SCTLR);
regval |= SCTLR_C | SCTLR_I | SCTLR_M;
- arm_set_sctlr(regval);
+ CP15_SET(SCTLR, regval);
}
diff --git a/arch/arm/src/armv7-a/arm_timer.c b/arch/arm/src/armv7-a/arm_timer.c
index 007030d2a5..0e86c2ca27 100644
--- a/arch/arm/src/armv7-a/arm_timer.c
+++ b/arch/arm/src/armv7-a/arm_timer.c
@@ -30,6 +30,7 @@
#include "arm_timer.h"
#include "barriers.h"
#include "gic.h"
+#include "cp15.h"
/****************************************************************************
* Pre-processor Definitions
@@ -88,108 +89,43 @@ static const struct oneshot_operations_s g_arm_timer_ops =
static inline uint32_t arm_timer_get_freq(void)
{
- uint32_t freq;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c14, c0, 0\n" /* Read CNTFRQ */
- : "=r"(freq)
- :
- :
- );
-
- return freq;
+ return CP15_GET(CNTFRQ);
}
static inline void arm_timer_set_freq(uint32_t freq)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c14, c0, 0\n" /* Write CNTFRQ */
- :
- : "r"(freq)
- :
- );
-
+ CP15_SET(CNTFRQ, freq);
ARM_ISB();
}
static inline uint64_t arm_timer_get_count(void)
{
- uint64_t count;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrrc p15, 0, %Q0, %R0, c14\n" /* Read CNTPCT */
- : "=r"(count)
- :
- :
- );
-
- return count;
+ return CP15_GET64(CNTPCT);
}
static inline uint32_t arm_timer_get_ctrl(void)
{
- uint32_t ctrl;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c14, c2, 1\n" /* Read CNTP_CTL */
- : "=r"(ctrl)
- :
- :
- );
-
- return ctrl;
+ return CP15_GET(CNTP_CTL);
}
static inline void arm_timer_set_ctrl(uint32_t ctrl)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c14, c2, 1\n" /* Write CNTP_CTL */
- :
- : "r"(ctrl)
- :
- );
-
+ CP15_SET(CNTP_CTL, ctrl);
ARM_ISB();
}
static inline uint32_t arm_timer_get_tval(void)
{
- uint32_t tval;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c14, c2, 0\n" /* Read CNTP_TVAL */
- : "=r"(tval)
- :
- :
- );
-
- return tval;
+ return CP15_GET(CNTP_TVAL);
}
static inline void arm_timer_set_tval(uint32_t tval)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c14, c2, 0\n" /* Write CNTP_TVAL */
- :
- : "r"(tval)
- :
- );
-
+ CP15_SET(CNTP_TVAL, tval);
ARM_ISB();
}
diff --git a/arch/arm/src/armv7-a/barriers.h b/arch/arm/src/armv7-a/barriers.h
index 70e98e5d48..b3a242c52f 100644
--- a/arch/arm/src/armv7-a/barriers.h
+++ b/arch/arm/src/armv7-a/barriers.h
@@ -34,9 +34,11 @@
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
+#define arm_nop(n) __asm__ __volatile__ ("nop\n")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
+#define ARM_NOP() arm_nop(15)
#endif /* __ARCH_ARM_SRC_ARMV7_A_BARRIERS_H */
diff --git a/arch/arm/src/armv7-a/cp15.h b/arch/arm/src/armv7-a/cp15.h
index 47da92da89..587e883e6a 100644
--- a/arch/arm/src/armv7-a/cp15.h
+++ b/arch/arm/src/armv7-a/cp15.h
@@ -58,7 +58,13 @@
* Reference: Cortex-A5� MPCore, Technical Reference Manual, Paragraph 4.2.
*/
-#define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
+#ifdef __ASSEMBLY__
+# define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
+# define _CP15_64(op1,lo,hi,op2) p15, op1, lo, hi, op2
+#else
+# define _CP15(op1,rd,crn,crm,op2) "p15, " #op1 ", %0, " #crn ", " #crm ", " #op2
+# define _CP15_64(op1,lo,hi,op2) "p15, " #op1 ", %Q0, %R0, " #op2
+#endif
#define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */
#define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
@@ -182,6 +188,15 @@
#define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3)
#define CP15_TPIDRPRW(r) _CP15(0, r, c13, c0, 4)
+#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */
+#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */
+#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */
+#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 1) /* PL1 Physical Timer Control register */
+#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */
+#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */
+
+#define CP15_CNTPCT(lo,hi) _CP15_64(0, lo, hi, c14) /* Physical Count register */
+
#define CP15_PWRCTRL(r) _CP15(0, r, c15, c0, 0) /* Power Control Register (Cortex-A9) */
#define CP15_NEONBUSY(r) _CP15(0, r, c15, c1, 1) /* NEON Busy Register (Cortex-A9) */
#define CP15_DR0(r) _CP15(3, r, c15, c0, 0) /* Data Register (Cortex-A5) */
@@ -199,4 +214,59 @@
#define CP15_MAINTLBPA(r) _CP15(5, r, c15, c6, 2) /* Main TLB PA register (Cortex-A9) */
#define CP15_MAINTLBAT(r) _CP15(5, r, c15, c7, 2) /* Main TLB Attribute register (Cortex-A9) */
+#define CP15_SET(reg, value) \
+ do \
+ { \
+ __asm__ __volatile__ \
+ ( \
+ "mcr " CP15_ ## reg(0) "\n" \
+ :: "r"(value): "memory" \
+ ); \
+ } \
+ while(0) \
+
+#define CP15_SET2(reg, op, value) \
+ do \
+ { \
+ __asm__ __volatile__ \
+ ( \
+ "mcr " CP15_ ## reg(0, op) "\n" \
+ :: "r"(value): "memory" \
+ ); \
+ } \
+ while(0) \
+
+#define CP15_GET(reg) \
+ ({ \
+ uint32_t value; \
+ __asm__ __volatile__ \
+ ( \
+ "mrc " CP15_ ## reg(0) "\n" \
+ : "=r"(value) :: "memory" \
+ ); \
+ value; \
+ }) \
+
+#define CP15_SET64(reg, value) \
+ do \
+ { \
+ __asm__ __volatile__ \
+ ( \
+ "mcrr " CP15_ ## reg(0,0) "\n" \
+ :: "r"(value): "memory" \
+ ); \
+ } \
+ while(0) \
+
+#define CP15_GET64(reg) \
+ ({ \
+ uint64_t value; \
+ __asm__ __volatile__ \
+ ( \
+ "mrrc " CP15_ ## reg(0,0) "\n" \
+ : "=r"(value) :: "memory" \
+ ); \
+ value; \
+ }) \
+
#endif /* __ARCH_ARM_SRC_ARMV7_A_CP15_H */
diff --git a/arch/arm/src/armv7-a/cp15_cacheops.h b/arch/arm/src/armv7-a/cp15_cacheops.h
index 18fad4d8c1..cf827c88d8 100644
--- a/arch/arm/src/armv7-a/cp15_cacheops.h
+++ b/arch/arm/src/armv7-a/cp15_cacheops.h
@@ -55,6 +55,8 @@
* Included Files
****************************************************************************/
+#include "sctlr.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -324,7 +326,7 @@
*
* Description:
* Invalidate all instruction caches to PoU, also flushes branch target
- * cache
+ * cache
*
* Input Parameters:
* None
@@ -545,15 +547,11 @@
static inline void cp15_enable_dcache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr |= SCTLR_C;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -572,15 +570,11 @@ static inline void cp15_enable_dcache(void)
static inline void cp15_disable_dcache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr &= ~SCTLR_C;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -599,15 +593,11 @@ static inline void cp15_disable_dcache(void)
static inline void cp15_enable_icache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr |= SCTLR_I;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -626,15 +616,11 @@ static inline void cp15_enable_icache(void)
static inline void cp15_disable_icache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr &= ~SCTLR_I;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -653,14 +639,7 @@ static inline void cp15_disable_icache(void)
static inline void cp15_invalidate_icache_inner_sharable(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(ICIALLUIS, 0);
}
/****************************************************************************
@@ -679,14 +658,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
static inline void cp15_invalidate_btb_inner_sharable(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(BPIALLIS, 0);
}
/****************************************************************************
@@ -706,14 +678,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
static inline void cp15_invalidate_icache(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(ICIALLU, 0);
}
/****************************************************************************
@@ -732,13 +697,7 @@ static inline void cp15_invalidate_icache(void)
static inline void cp15_invalidate_icache_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(ICIMVAU, va);
}
/****************************************************************************
@@ -757,14 +716,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
static inline void cp15_flush_btb(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(BPIALL, 0);
}
/****************************************************************************
@@ -783,14 +735,7 @@ static inline void cp15_flush_btb(void)
static inline void cp15_flush_btb_bymva(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(BPIMVA, 0);
}
/****************************************************************************
@@ -811,13 +756,7 @@ static inline void cp15_flush_btb_bymva(void)
static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(DCIMVAC, va);
}
/****************************************************************************
@@ -838,13 +777,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCISW, setway);
}
/****************************************************************************
@@ -865,13 +798,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
static inline void cp15_clean_dcache_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(DCCMVAC, va);
}
/****************************************************************************
@@ -890,13 +817,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
static inline void cp15_clean_dcache_bysetway(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCCSW, setway);
}
/****************************************************************************
@@ -915,13 +836,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
static inline void cp15_clean_ucache_bymva(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCCMVAU, setway);
}
/****************************************************************************
@@ -940,13 +855,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway)
static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(DCCIMVAC, va);
}
/****************************************************************************
@@ -965,13 +874,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCCISW, setway);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h
index a6e9b54dd3..093a56018e 100644
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
@@ -35,10 +35,12 @@
#include <nuttx/config.h>
#include <sys/types.h>
+#include "sctlr.h"
#ifndef __ASSEMBLY__
# include <stdint.h>
# include "chip.h"
+# include "barriers.h"
#endif /* __ASSEMBLY__ */
/****************************************************************************
@@ -1195,15 +1197,11 @@ struct section_mapping_s
static inline void cp15_disable_mmu(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n"
- "\tbic r0, r0, #1\n"
- "\tmcr p15, 0, r0, c1, c0, 0\n"
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr &= ~SCTLR_M;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -1225,22 +1223,16 @@ static inline void cp15_disable_mmu(void)
static inline void cp15_invalidate_tlbs(void)
{
- __asm__ __volatile__
- (
- "\tdsb\n"
+ ARM_DSB();
#ifdef CONFIG_ARM_HAVE_MPCORE
- "\tmcr p15, 0, r0, c8, c3, 0\n" /* TLBIALLIS */
- "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
+ CP15_SET(TLBIALLIS, 0);
+ CP15_SET(BPIALLIS, 0);
#else
- "\tmcr p15, 0, r0, c8, c7, 0\n" /* TLBIALL */
- "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
+ CP15_SET2(TLBIALL, c7, 0);
+ CP15_SET(BPIALL, 0);
#endif
- "\tdsb\n"
- "\tisb\n"
- :
- :
- : "r0", "memory"
- );
+ ARM_DSB();
+ ARM_ISB();
}
/****************************************************************************
@@ -1256,22 +1248,16 @@ static inline void cp15_invalidate_tlbs(void)
static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
{
- __asm__ __volatile__
- (
- "\tdsb\n"
+ ARM_DSB();
#ifdef CONFIG_ARM_HAVE_MPCORE
- "\tmcr p15, 0, %0, c8, c3, 3\n" /* TLBIMVAAIS */
- "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
+ CP15_SET(TLBIMVAAIS, vaddr);
+ CP15_SET(BPIALLIS, 0);
#else
- "\tmcr p15, 0, %0, c8, c7, 1\n" /* TLBIMVA */
- "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
+ CP15_SET2(TLBIMVA, c7, vaddr);
+ CP15_SET(BPIALL, 0);
#endif
- "\tdsb\n"
- "\tisb\n"
- :
- : "r" (vaddr)
- : "r1", "memory"
- );
+ ARM_DSB();
+ ARM_ISB();
}
/****************************************************************************
@@ -1287,21 +1273,15 @@ static inline void cp15_invalidate_tlb_bymva(uint32_t vaddr)
static inline void cp15_wrdacr(unsigned int dacr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c3, c0, 0\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- :
- : "r" (dacr)
- : "memory"
- );
+ CP15_SET(DACR, dacr);
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
}
/****************************************************************************
@@ -1321,23 +1301,16 @@ static inline void cp15_wrdacr(unsigned int dacr)
static inline void cp15_wrttb(unsigned int ttb)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c2, c0, 0\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tmov r1, #0\n"
- "\tmcr p15, 0, r1, c2, c0, 2\n"
- :
- : "r" (ttb)
- : "r1", "memory"
- );
+ CP15_SET(TTBR0, ttb);
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ CP15_SET(TTBCR, 0);
}
/****************************************************************************
@@ -1359,14 +1332,7 @@ static inline uint32_t *mmu_l1_pgtable(void)
uint32_t ttbr0;
uint32_t pgtable;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c2, c0, 0\n"
- : "=r" (ttbr0)
- :
- :
- );
-
+ ttbr0 = CP15_GET(TTBR0);
pgtable = ttbr0 & TTBR0_BASE_MASK(0);
return (uint32_t *)(pgtable - PGTABLE_BASE_PADDR + PGTABLE_BASE_VADDR);
#else
diff --git a/arch/arm/src/armv7-a/sctlr.h b/arch/arm/src/armv7-a/sctlr.h
index cd8c52d627..6d12e49167 100644
--- a/arch/arm/src/armv7-a/sctlr.h
+++ b/arch/arm/src/armv7-a/sctlr.h
@@ -34,6 +34,9 @@
* Included Files
****************************************************************************/
+#include "barriers.h"
+#include "cp15.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -455,94 +458,58 @@
static inline unsigned int cp15_rdid(void)
{
- unsigned int id;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c0, c0, 0\n"
- : "=r" (id)
- :
- : "memory"
- );
-
- return id;
+ return CP15_GET(MIDR);
}
/* Get the Multiprocessor Affinity Register (MPIDR) */
static inline unsigned int cp15_rdmpidr(void)
{
- unsigned int mpidr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c0, c0, 5\n"
- : "=r" (mpidr)
- :
- : "memory"
- );
-
- return mpidr;
+ return CP15_GET(MPIDR);
}
/* Read/write the system control register (SCTLR) */
static inline unsigned int cp15_rdsctlr(void)
{
- unsigned int sctlr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c1, c0, 0\n"
- : "=r" (sctlr)
- :
- : "memory"
- );
-
- return sctlr;
+ return CP15_GET(SCTLR);
}
static inline void cp15_wrsctlr(unsigned int sctlr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c1, c0, 0\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- :
- : "r" (sctlr)
- : "memory"
- );
+ CP15_SET(SCTLR, sctlr);
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
}
/* Read/write the vector base address register (VBAR) */
static inline unsigned int cp15_rdvbar(void)
{
- unsigned int sctlr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c12, c0, 0\n"
- : "=r" (sctlr)
- :
- : "memory"
- );
+ return CP15_GET(VBAR);
+}
+
+static inline void cp15_wrvbar(unsigned int vbar)
+{
+ CP15_SET(VBAR, vbar);
+}
+
+/* Read/write the implementation defined Auxiliary Control Register (ACTLR) */
- return sctlr;
+static inline unsigned int cp15_rdactlr(void)
+{
+ return CP15_GET(ACTLR);
}
-static inline void cp15_wrvbar(unsigned int sctlr)
+static inline void cp15_wractlr(unsigned int actlr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c12, c0, 0\n"
- :
- : "r" (sctlr)
- : "memory"
- );
+ CP15_SET(ACTLR, actlr);
}
/****************************************************************************
@@ -555,27 +522,12 @@ static inline void cp15_wrvbar(unsigned int sctlr)
static inline unsigned int cp15_pmu_rdpmcr(void)
{
- unsigned int pmcr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 0\n"
- : "=r" (pmcr)
- :
- : "memory"
- );
-
- return pmcr;
+ return CP15_GET(PMCR);
}
static inline void cp15_pmu_wrpmcr(unsigned int pmcr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 0\n"
- :
- : "r" (pmcr)
- : "memory"
- );
+ CP15_SET(PMCR, pmcr);
}
static inline void cp15_pmu_pmcr(unsigned int pmcr)
@@ -594,27 +546,12 @@ static inline void cp15_pmu_pmcr(unsigned int pmcr)
static inline unsigned int cp15_pmu_rdcesr(void)
{
- unsigned int cesr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 1\n"
- : "=r" (cesr)
- :
- : "memory"
- );
-
- return cesr;
+ return CP15_GET(PMCNTENSET);
}
static inline void cp15_pmu_wrcesr(unsigned int cesr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 1\n"
- :
- : "r" (cesr)
- : "memory"
- );
+ CP15_SET(PMCNTENSET, cesr);
}
static inline void cp15_pmu_cesr(unsigned int cesr)
@@ -633,27 +570,12 @@ static inline void cp15_pmu_cesr(unsigned int cesr)
static inline unsigned int cp15_pmu_rdcecr(void)
{
- unsigned int cecr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 2\n"
- : "=r" (cecr)
- :
- : "memory"
- );
-
- return cecr;
+ return CP15_GET(PMCNTENCLR);
}
static inline void cp15_pmu_wrcecr(unsigned int cecr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 2\n"
- :
- : "r" (cecr)
- : "memory"
- );
+ CP15_SET(PMCNTENCLR, cecr);
}
static inline void cp15_pmu_cecr(unsigned int cecr)
@@ -672,27 +594,12 @@ static inline void cp15_pmu_cecr(unsigned int cecr)
static inline unsigned int cp15_pmu_rdofsr(void)
{
- unsigned int ofsr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 3\n"
- : "=r" (ofsr)
- :
- : "memory"
- );
-
- return ofsr;
+ return CP15_GET(PMOVSR);
}
static inline void cp15_pmu_wrofsr(unsigned int ofsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 3\n"
- :
- : "r" (ofsr)
- : "memory"
- );
+ CP15_SET(PMOVSR, ofsr);
}
static inline void cp15_pmu_ofsr(unsigned int ofsr)
@@ -711,27 +618,12 @@ static inline void cp15_pmu_ofsr(unsigned int ofsr)
static inline unsigned int cp15_pmu_rdsir(void)
{
- unsigned int sir;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 4\n"
- : "=r" (sir)
- :
- : "memory"
- );
-
- return sir;
+ return CP15_GET(PMSWINC);
}
static inline void cp15_pmu_wrsir(unsigned int sir)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 4\n"
- :
- : "r" (sir)
- : "memory"
- );
+ CP15_SET(PMSWINC, sir);
}
static inline void cp15_pmu_sir(unsigned int sir)
@@ -749,13 +641,7 @@ static inline void cp15_pmu_sir(unsigned int sir)
static inline void cp15_pmu_wrecsr(unsigned int ecsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 5\n"
- :
- : "r" (ecsr)
- : "memory"
- );
+ CP15_SET(PMSELR, ecsr);
}
/****************************************************************************
@@ -768,13 +654,7 @@ static inline void cp15_pmu_wrecsr(unsigned int ecsr)
static inline void cp15_pmu_wretsr(unsigned int etsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c13, 1\n"
- :
- : "r" (etsr)
- : "memory"
- );
+ CP15_SET(PMXEVTYPER, etsr);
}
/****************************************************************************
@@ -787,27 +667,12 @@ static inline void cp15_pmu_wretsr(unsigned int etsr)
static inline unsigned int cp15_pmu_rduer(void)
{
- unsigned int uer;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c14, 0\n"
- : "=r" (uer)
- :
- : "memory"
- );
-
- return uer;
+ return CP15_GET(PMUSERENR);
}
static inline void cp15_pmu_wruer(unsigned int uer)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c14, 0\n"
- :
- : "r" (uer)
- : "memory"
- );
+ CP15_SET(PMUSERENR, uer);
}
static inline void cp15_pmu_uer(unsigned int uer)
@@ -826,13 +691,7 @@ static inline void cp15_pmu_uer(unsigned int uer)
static inline void cp15_pmu_wriesr(unsigned int iesr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c14, 1\n"
- :
- : "r" (iesr)
- : "memory"
- );
+ CP15_SET(PMINTENSET, iesr);
}
/****************************************************************************
@@ -846,13 +705,7 @@ static inline void cp15_pmu_wriesr(unsigned int iesr)
static inline void cp15_pmu_wriecr(unsigned int iecr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c14, 2\n"
- :
- : "r" (iecr)
- : "memory"
- );
+ CP15_SET(PMINTENCLR, iecr);
}
/****************************************************************************
@@ -865,16 +718,7 @@ static inline void cp15_pmu_wriecr(unsigned int iecr)
static inline unsigned int cp15_pmu_rdccr(void)
{
- unsigned int ccr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c13, 0\n"
- : "=r" (ccr)
- :
- : "memory"
- );
-
- return ccr;
+ return CP15_GET(PMCCNTR);
}
/****************************************************************************
@@ -887,16 +731,7 @@ static inline unsigned int cp15_pmu_rdccr(void)
static inline unsigned int cp15_pmu_rdecr(void)
{
- unsigned int ecr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c13, 2"
- : "=r" (ecr)
- :
- : "memory"
- );
-
- return ecr;
+ return CP15_GET(PMXEVCNTR);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/src/armv7-r/arm_timer.c b/arch/arm/src/armv7-r/arm_timer.c
index 42c5e6d95e..2486d90f2c 100644
--- a/arch/arm/src/armv7-r/arm_timer.c
+++ b/arch/arm/src/armv7-r/arm_timer.c
@@ -30,6 +30,7 @@
#include "arm_timer.h"
#include "barriers.h"
#include "gic.h"
+#include "cp15.h"
/****************************************************************************
* Pre-processor Definitions
@@ -88,108 +89,43 @@ static const struct oneshot_operations_s g_arm_timer_ops =
static inline uint32_t arm_timer_get_freq(void)
{
- uint32_t freq;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c14, c0, 0\n" /* Read CNTFRQ */
- : "=r"(freq)
- :
- :
- );
-
- return freq;
+ return CP15_GET(CNTFRQ);
}
static inline void arm_timer_set_freq(uint32_t freq)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c14, c0, 0\n" /* Write CNTFRQ */
- :
- : "r"(freq)
- :
- );
-
+ CP15_SET(CNTFRQ, freq);
ARM_ISB();
}
static inline uint64_t arm_timer_get_count(void)
{
- uint64_t count;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrrc p15, 0, %Q0, %R0, c14\n" /* Read CNTPCT */
- : "=r"(count)
- :
- :
- );
-
- return count;
+ return CP15_GET64(CNTPCT);
}
static inline uint32_t arm_timer_get_ctrl(void)
{
- uint32_t ctrl;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c14, c2, 1\n" /* Read CNTP_CTL */
- : "=r"(ctrl)
- :
- :
- );
-
- return ctrl;
+ return CP15_GET(CNTP_CTL);
}
static inline void arm_timer_set_ctrl(uint32_t ctrl)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c14, c2, 1\n" /* Write CNTP_CTL */
- :
- : "r"(ctrl)
- :
- );
-
+ CP15_SET(CNTP_CTL, ctrl);
ARM_ISB();
}
static inline uint32_t arm_timer_get_tval(void)
{
- uint32_t tval;
-
ARM_ISB();
-
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c14, c2, 0\n" /* Read CNTP_TVAL */
- : "=r"(tval)
- :
- :
- );
-
- return tval;
+ return CP15_GET(CNTP_TVAL);
}
static inline void arm_timer_set_tval(uint32_t tval)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c14, c2, 0\n" /* Write CNTP_TVAL */
- :
- : "r"(tval)
- :
- );
-
+ CP15_SET(CNTP_TVAL, tval);
ARM_ISB();
}
diff --git a/arch/arm/src/armv7-r/cp15.h b/arch/arm/src/armv7-r/cp15.h
index 4c5bd42698..b51ac20d4b 100644
--- a/arch/arm/src/armv7-r/cp15.h
+++ b/arch/arm/src/armv7-r/cp15.h
@@ -55,7 +55,13 @@
* Reference: Cortex-A5� MPCore, Technical Reference Manual, Paragraph 4.2.
*/
-#define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
+#ifdef __ASSEMBLY__
+# define _CP15(op1,rd,crn,crm,op2) p15, op1, rd, crn, crm, op2
+# define _CP15_64(op1,lo,hi,op2) p15, op1, lo, hi, op2
+#else
+# define _CP15(op1,rd,crn,crm,op2) "p15, " #op1 ", %0, " #crn ", " #crm ", " #op2
+# define _CP15_64(op1,lo,hi,op2) "p15, " #op1 ", %Q0, %R0, " #op2
+#endif
#define CP15_MIDR(r) _CP15(0, r, c0, c0, 0) /* Main ID Register */
#define CP15_CTR(r) _CP15(0, r, c0, c0, 1) /* Cache Type Register */
@@ -141,16 +147,70 @@
#define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3)
#define CP15_TPIDRPRW(r) _CP15(0, r, c13, c0, 4)
-#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */
-#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */
-#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */
-#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical Timer Control register */
-#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */
-#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */
-#define CP15_CNTPCT(r,n) _CP15(0, r, c14, c14, n) /* 64-bit Physical Count register */
-#define CP15_CNTVCT(r,n) _CP15(1, r, c14, c14, n) /* Virtual Count register */
-#define CP15_CNTP_CVAL(r,n) _CP15(2, r, c14, c14, n) /* PL1 Physical Timer CompareValue register */
-#define CP15_CNTV_CVAL(r,n) _CP15(3, r, c14, c14, n) /* Virtual Timer CompareValue register */
+#define CP15_CNTFRQ(r) _CP15(0, r, c14, c0, 0) /* Counter Frequency register */
+#define CP15_CNTKCTL(r) _CP15(0, r, c14, c1, 0) /* Timer PL1 Control register */
+#define CP15_CNTP_TVAL(r) _CP15(0, r, c14, c2, 0) /* PL1 Physical TimerValue register */
+#define CP15_CNTP_CTL(r) _CP15(0, r, c14, c2, 1) /* PL1 Physical Timer Control register */
+#define CP15_CNTV_TVAL(r) _CP15(0, r, c14, c3, 0) /* Virtual TimerValue register */
+#define CP15_CNTV_CTL(r) _CP15(0, r, c14, c3, 0) /* Virtual Timer Control register */
+
+#define CP15_CNTPCT(lo,hi) _CP15_64(0, lo, hi, c14) /* Physical Count register */
+
#define CP15_DCIALLU(r) _CP15(0, r, c15, c5, 0) /* Invalidate data cache */
+#define CP15_SET(reg, value) \
+ do \
+ { \
+ __asm__ __volatile__ \
+ ( \
+ "mcr " CP15_ ## reg(0) "\n" \
+ :: "r"(value): "memory" \
+ ); \
+ } \
+ while(0) \
+
+#define CP15_SET2(reg, op, value) \
+ do \
+ { \
+ __asm__ __volatile__ \
+ ( \
+ "mcr " CP15_ ## reg(0, op) "\n" \
+ :: "r"(value): "memory" \
+ ); \
+ } \
+ while(0) \
+
+#define CP15_GET(reg) \
+ ({ \
+ uint32_t value; \
+ __asm__ __volatile__ \
+ ( \
+ "mrc " CP15_ ## reg(0) "\n" \
+ : "=r"(value) :: "memory" \
+ ); \
+ value; \
+ }) \
+
+#define CP15_SET64(reg, value) \
+ do \
+ { \
+ __asm__ __volatile__ \
+ ( \
+ "mcrr " CP15_ ## reg(0,0) "\n" \
+ :: "r"(value): "memory" \
+ ); \
+ } \
+ while(0) \
+
+#define CP15_GET64(reg) \
+ ({ \
+ uint64_t value; \
+ __asm__ __volatile__ \
+ ( \
+ "mrrc " CP15_ ## reg(0,0) "\n" \
+ : "=r"(value) :: "memory" \
+ ); \
+ value; \
+ }) \
+
#endif /* __ARCH_ARM_SRC_ARMV7_R_CP15_H */
diff --git a/arch/arm/src/armv7-r/cp15_cacheops.h b/arch/arm/src/armv7-r/cp15_cacheops.h
index 7d0bfdc7a8..1be45e32e4 100644
--- a/arch/arm/src/armv7-r/cp15_cacheops.h
+++ b/arch/arm/src/armv7-r/cp15_cacheops.h
@@ -53,6 +53,8 @@
* Included Files
****************************************************************************/
+#include "sctlr.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -552,15 +554,11 @@
static inline void cp15_enable_dcache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\torr r0, r0, #(1 << 2)\n" /* Enable D cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr |= SCTLR_C;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -579,15 +577,11 @@ static inline void cp15_enable_dcache(void)
static inline void cp15_disable_dcache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\tbic r0, r0, #(1 << 2)\n" /* Disable D cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr &= ~SCTLR_C;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -606,15 +600,11 @@ static inline void cp15_disable_dcache(void)
static inline void cp15_enable_icache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\torr r0, r0, #(1 << 12)\n" /* Enable I cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr |= SCTLR_I;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -633,15 +623,11 @@ static inline void cp15_enable_icache(void)
static inline void cp15_disable_icache(void)
{
- __asm__ __volatile__
- (
- "\tmrc p15, 0, r0, c1, c0, 0\n" /* Read SCTLR */
- "\tbic r0, r0, #(1 << 12)\n" /* Disable I cache */
- "\tmcr p15, 0, r0, c1, c0, 0\n" /* Update the SCTLR */
- :
- :
- : "r0", "memory"
- );
+ uint32_t sctlr;
+
+ sctlr = CP15_GET(SCTLR);
+ sctlr &= ~SCTLR_I;
+ CP15_SET(SCTLR, sctlr);
}
/****************************************************************************
@@ -660,14 +646,7 @@ static inline void cp15_disable_icache(void)
static inline void cp15_invalidate_icache_inner_sharable(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c1, 0\n" /* ICIALLUIS */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(ICIALLUIS, 0);
}
/****************************************************************************
@@ -686,14 +665,7 @@ static inline void cp15_invalidate_icache_inner_sharable(void)
static inline void cp15_invalidate_btb_inner_sharable(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c1, 6\n" /* BPIALLIS */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(BPIALLIS, 0);
}
/****************************************************************************
@@ -713,14 +685,7 @@ static inline void cp15_invalidate_btb_inner_sharable(void)
static inline void cp15_invalidate_icache(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c5, 0\n" /* ICIALLU */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(ICIALLU, 0);
}
/****************************************************************************
@@ -739,13 +704,7 @@ static inline void cp15_invalidate_icache(void)
static inline void cp15_invalidate_icache_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c5, 1\n" /* ICIMVAU */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(ICIMVAU, va);
}
/****************************************************************************
@@ -764,14 +723,7 @@ static inline void cp15_invalidate_icache_bymva(unsigned int va)
static inline void cp15_flush_btb(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c5, 6\n" /* BPIALL */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(BPIALL, 0);
}
/****************************************************************************
@@ -790,14 +742,7 @@ static inline void cp15_flush_btb(void)
static inline void cp15_flush_btb_bymva(void)
{
- __asm__ __volatile__
- (
- "\tmov r0, #0\n"
- "\tmcr p15, 0, r0, c7, c5, 7\n" /* BPIMVA */
- :
- :
- : "r0", "memory"
- );
+ CP15_SET(BPIMVA, 0);
}
/****************************************************************************
@@ -818,13 +763,7 @@ static inline void cp15_flush_btb_bymva(void)
static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c6, 1\n" /* DCIMVAC */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(DCIMVAC, va);
}
/****************************************************************************
@@ -845,13 +784,7 @@ static inline void cp15_invalidate_dcacheline_bymva(unsigned int va)
static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c6, 2\n" /* DCISW */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCISW, setway);
}
/****************************************************************************
@@ -872,13 +805,7 @@ static inline void cp15_invalidate_dcacheline_bysetway(unsigned int setway)
static inline void cp15_clean_dcache_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c10, 1\n" /* DCCMVAC */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(DCCMVAC, va);
}
/****************************************************************************
@@ -897,13 +824,7 @@ static inline void cp15_clean_dcache_bymva(unsigned int va)
static inline void cp15_clean_dcache_bysetway(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c10, 2\n" /* DCCSW */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCCSW, setway);
}
/****************************************************************************
@@ -922,13 +843,7 @@ static inline void cp15_clean_dcache_bysetway(unsigned int setway)
static inline void cp15_clean_ucache_bymva(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c11, 1\n" /* DCCMVAU */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCCMVAU, setway);
}
/****************************************************************************
@@ -947,13 +862,7 @@ static inline void cp15_clean_ucache_bymva(unsigned int setway)
static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, r0, c7, c14, 1\n" /* DCCIMVAC */
- :
- : "r" (va)
- : "memory"
- );
+ CP15_SET(DCCIMVAC, va);
}
/****************************************************************************
@@ -972,13 +881,7 @@ static inline void cp15_cleaninvalidate_dcacheline_bymva(unsigned int va)
static inline void cp15_cleaninvalidate_dcacheline(unsigned int setway)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c7, c14, 2\n" /* DCCISW */
- :
- : "r" (setway)
- : "memory"
- );
+ CP15_SET(DCCISW, setway);
}
#endif /* __ASSEMBLY__ */
diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h
index 5029b12fdc..e7e05d7a59 100644
--- a/arch/arm/src/armv7-r/mpu.h
+++ b/arch/arm/src/armv7-r/mpu.h
@@ -215,16 +215,7 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
static inline unsigned int mpu_get_mpuir(void)
{
- unsigned int mpuir;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c0, c0, 4"
- : "=r" (mpuir)
- :
- : "memory"
- );
-
- return mpuir;
+ return CP15_GET(MPUIR);
}
/****************************************************************************
@@ -237,13 +228,7 @@ static inline unsigned int mpu_get_mpuir(void)
static inline void mpu_set_drbar(unsigned int drbar)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c1, 0"
- :
- : "r" (drbar)
- : "memory"
- );
+ CP15_SET(DRBAR, drbar);
}
/****************************************************************************
@@ -256,13 +241,7 @@ static inline void mpu_set_drbar(unsigned int drbar)
static inline void mpu_set_drsr(unsigned int drsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c1, 2"
- :
- : "r" (drsr)
- : "memory"
- );
+ CP15_SET(DRSR, drsr);
}
/****************************************************************************
@@ -275,13 +254,7 @@ static inline void mpu_set_drsr(unsigned int drsr)
static inline void mpu_set_dracr(unsigned int dracr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c1, 4"
- :
- : "r" (dracr)
- : "memory"
- );
+ CP15_SET(DRACR, dracr);
}
/****************************************************************************
@@ -295,13 +268,7 @@ static inline void mpu_set_dracr(unsigned int dracr)
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
static inline void mpu_set_irbar(unsigned int irbar)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c1, 1"
- :
- : "r" (irbar)
- : "memory"
- );
+ CP15_SET(IRBAR, irbar);
}
#endif
@@ -316,13 +283,7 @@ static inline void mpu_set_irbar(unsigned int irbar)
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
static inline void mpu_set_irsr(unsigned int irsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c1, 3"
- :
- : "r" (irsr)
- : "memory"
- );
+ CP15_SET(IRSR, irsr);
}
#endif
@@ -330,20 +291,14 @@ static inline void mpu_set_irsr(unsigned int irsr)
* Name: mpu_set_iracr
*
* Description:
- * Write to the IRCR register
+ * Write to the IRACR register
*
****************************************************************************/
#ifndef CONFIG_ARM_HAVE_MPU_UNIFIED
static inline void mpu_set_iracr(unsigned int iracr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c1, 5"
- :
- : "r" (iracr)
- : "memory"
- );
+ CP15_SET(IRACR, iracr);
}
#endif
@@ -351,19 +306,13 @@ static inline void mpu_set_iracr(unsigned int iracr)
* Name: mpu_set_rgnr
*
* Description:
- * Write to the IRCR register
+ * Write to the RGNR register
*
****************************************************************************/
static inline void mpu_set_rgnr(unsigned int rgnr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c6, c2, 0"
- :
- : "r" (rgnr)
- : "memory"
- );
+ CP15_SET(RGNR, rgnr);
}
/****************************************************************************
diff --git a/arch/arm/src/armv7-r/sctlr.h b/arch/arm/src/armv7-r/sctlr.h
index b5497f96cc..78c589e03c 100644
--- a/arch/arm/src/armv7-r/sctlr.h
+++ b/arch/arm/src/armv7-r/sctlr.h
@@ -32,6 +32,9 @@
* Included Files
****************************************************************************/
+#include "barriers.h"
+#include "cp15.h"
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
@@ -492,82 +495,62 @@
#ifndef __ASSEMBLY__
-/* Get the device ID */
+/* Get the device ID register */
static inline unsigned int cp15_rdid(void)
{
- unsigned int id;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c0, c0, 0"
- : "=r" (id)
- :
- : "memory"
- );
+ return CP15_GET(MIDR);
+}
- return id;
+/* Get the Multiprocessor Affinity Register (MPIDR) */
+
+static inline unsigned int cp15_rdmpidr(void)
+{
+ return CP15_GET(MPIDR);
}
/* Read/write the system control register (SCTLR) */
static inline unsigned int cp15_rdsctlr(void)
{
- unsigned int sctlr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c1, c0, 0\n"
- : "=r" (sctlr)
- :
- : "memory"
- );
-
- return sctlr;
+ return CP15_GET(SCTLR);
}
static inline void cp15_wrsctlr(unsigned int sctlr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c1, c0, 0\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- "\tnop\n"
- :
- : "r" (sctlr)
- : "memory"
- );
+ CP15_SET(SCTLR, sctlr);
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+ ARM_NOP();
+}
+
+/* Read/write the vector base address register (VBAR) */
+
+static inline unsigned int cp15_rdvbar(void)
+{
+ return CP15_GET(VBAR);
+}
+
+static inline void cp15_wrvbar(unsigned int vbar)
+{
+ CP15_SET(VBAR, vbar);
}
/* Read/write the implementation defined Auxiliary Control Register (ACTLR) */
static inline unsigned int cp15_rdactlr(void)
{
- unsigned int actlr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c1, c0, 1\n"
- : "=r" (actlr)
- :
- : "memory"
- );
-
- return actlr;
+ return CP15_GET(ACTLR);
}
static inline void cp15_wractlr(unsigned int actlr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c1, c0, 1\n"
- :
- : "r" (actlr)
- : "memory"
- );
+ CP15_SET(ACTLR, actlr);
}
/****************************************************************************
@@ -580,27 +563,12 @@ static inline void cp15_wractlr(unsigned int actlr)
static inline unsigned int cp15_pmu_rdpmcr(void)
{
- unsigned int pmcr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 0\n"
- : "=r" (pmcr)
- :
- : "memory"
- );
-
- return pmcr;
+ return CP15_GET(PMCR);
}
static inline void cp15_pmu_wrpmcr(unsigned int pmcr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 0\n"
- :
- : "r" (pmcr)
- : "memory"
- );
+ CP15_SET(PMCR, pmcr);
}
static inline void cp15_pmu_pmcr(unsigned int pmcr)
@@ -619,27 +587,12 @@ static inline void cp15_pmu_pmcr(unsigned int pmcr)
static inline unsigned int cp15_pmu_rdcesr(void)
{
- unsigned int cesr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 1\n"
- : "=r" (cesr)
- :
- : "memory"
- );
-
- return cesr;
+ return CP15_GET(PMCNTENSET);
}
static inline void cp15_pmu_wrcesr(unsigned int cesr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 1\n"
- :
- : "r" (cesr)
- : "memory"
- );
+ CP15_SET(PMCNTENSET, cesr);
}
static inline void cp15_pmu_cesr(unsigned int cesr)
@@ -658,27 +611,12 @@ static inline void cp15_pmu_cesr(unsigned int cesr)
static inline unsigned int cp15_pmu_rdcecr(void)
{
- unsigned int cecr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 2\n"
- : "=r" (cecr)
- :
- : "memory"
- );
-
- return cecr;
+ return CP15_GET(PMCNTENCLR);
}
static inline void cp15_pmu_wrcecr(unsigned int cecr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 2\n"
- :
- : "r" (cecr)
- : "memory"
- );
+ CP15_SET(PMCNTENCLR, cecr);
}
static inline void cp15_pmu_cecr(unsigned int cecr)
@@ -697,27 +635,12 @@ static inline void cp15_pmu_cecr(unsigned int cecr)
static inline unsigned int cp15_pmu_rdofsr(void)
{
- unsigned int ofsr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 3\n"
- : "=r" (ofsr)
- :
- : "memory"
- );
-
- return ofsr;
+ return CP15_GET(PMOVSR);
}
static inline void cp15_pmu_wrofsr(unsigned int ofsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 3\n"
- :
- : "r" (ofsr)
- : "memory"
- );
+ CP15_SET(PMOVSR, ofsr);
}
static inline void cp15_pmu_ofsr(unsigned int ofsr)
@@ -736,27 +659,12 @@ static inline void cp15_pmu_ofsr(unsigned int ofsr)
static inline unsigned int cp15_pmu_rdsir(void)
{
- unsigned int sir;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c12, 4\n"
- : "=r" (sir)
- :
- : "memory"
- );
-
- return sir;
+ return CP15_GET(PMSWINC);
}
static inline void cp15_pmu_wrsir(unsigned int sir)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 4\n"
- :
- : "r" (sir)
- : "memory"
- );
+ CP15_SET(PMSWINC, sir);
}
static inline void cp15_pmu_sir(unsigned int sir)
@@ -774,32 +682,20 @@ static inline void cp15_pmu_sir(unsigned int sir)
static inline void cp15_pmu_wrecsr(unsigned int ecsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c12, 5\n"
- :
- : "r" (ecsr)
- : "memory"
- );
+ CP15_SET(PMSELR, ecsr);
}
/****************************************************************************
* Name: cp15_pmu_wretsr
*
* Description:
- * Write the Performance Monitors Event Type Select Register (PMETSR)
+ * Write the Performance Monitors Event Type Select Register (PMXEVTYPER)
*
****************************************************************************/
static inline void cp15_pmu_wretsr(unsigned int etsr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c13, 1\n"
- :
- : "r" (etsr)
- : "memory"
- );
+ CP15_SET(PMXEVTYPER, etsr);
}
/****************************************************************************
@@ -812,27 +708,12 @@ static inline void cp15_pmu_wretsr(unsigned int etsr)
static inline unsigned int cp15_pmu_rduer(void)
{
- unsigned int uer;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c14, 0\n"
- : "=r" (uer)
- :
- : "memory"
- );
-
- return uer;
+ return CP15_GET(PMUSERENR);
}
static inline void cp15_pmu_wruer(unsigned int uer)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c14, 0\n"
- :
- : "r" (uer)
- : "memory"
- );
+ CP15_SET(PMUSERENR, uer);
}
static inline void cp15_pmu_uer(unsigned int uer)
@@ -851,13 +732,7 @@ static inline void cp15_pmu_uer(unsigned int uer)
static inline void cp15_pmu_wriesr(unsigned int iesr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c14, 1\n"
- :
- : "r" (iesr)
- : "memory"
- );
+ CP15_SET(PMINTENSET, iesr);
}
/****************************************************************************
@@ -871,13 +746,7 @@ static inline void cp15_pmu_wriesr(unsigned int iesr)
static inline void cp15_pmu_wriecr(unsigned int iecr)
{
- __asm__ __volatile__
- (
- "\tmcr p15, 0, %0, c9, c14, 2\n"
- :
- : "r" (iecr)
- : "memory"
- );
+ CP15_SET(PMINTENCLR, iecr);
}
/****************************************************************************
@@ -890,16 +759,7 @@ static inline void cp15_pmu_wriecr(unsigned int iecr)
static inline unsigned int cp15_pmu_rdccr(void)
{
- unsigned int ccr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c13, 0\n"
- : "=r" (ccr)
- :
- : "memory"
- );
-
- return ccr;
+ return CP15_GET(PMCCNTR);
}
/****************************************************************************
@@ -912,16 +772,7 @@ static inline unsigned int cp15_pmu_rdccr(void)
static inline unsigned int cp15_pmu_rdecr(void)
{
- unsigned int ecr;
- __asm__ __volatile__
- (
- "\tmrc p15, 0, %0, c9, c13, 2"
- : "=r" (ecr)
- :
- : "memory"
- );
-
- return ecr;
+ return CP15_GET(PMXEVCNTR);
}
#endif /* __ASSEMBLY__ */
[incubator-nuttx] 02/04: armv7a/r: refact cp15_cache functions
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 6d92810d5a8d6a02e8737a91821f7ef82c8ee1b2
Author: ligd <li...@xiaomi.com>
AuthorDate: Fri Sep 16 14:31:52 2022 +0800
armv7a/r: refact cp15_cache functions
Signed-off-by: ligd <li...@xiaomi.com>
---
arch/arm/src/armv7-a/Make.defs | 8 +-
arch/arm/src/armv7-a/cp15_cache_size.S | 85 --------
arch/arm/src/armv7-a/cp15_cacheops.c | 245 ++++++++++++++++++++++
arch/arm/src/armv7-a/cp15_clean_dcache.S | 116 ----------
arch/arm/src/armv7-a/cp15_clean_dcache_all.S | 127 -----------
arch/arm/src/armv7-a/cp15_coherent_dcache.S | 138 ------------
arch/arm/src/armv7-a/cp15_flush_dcache.S | 116 ----------
arch/arm/src/armv7-a/cp15_flush_dcache_all.S | 128 -----------
arch/arm/src/armv7-a/cp15_invalidate_dcache.S | 123 -----------
arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S | 128 -----------
arch/arm/src/armv7-r/Make.defs | 9 +-
arch/arm/src/armv7-r/cp15_cache_size.S | 84 --------
arch/arm/src/armv7-r/cp15_cacheops.c | 245 ++++++++++++++++++++++
arch/arm/src/armv7-r/cp15_clean_dcache.S | 116 ----------
arch/arm/src/armv7-r/cp15_clean_dcache_all.S | 129 ------------
arch/arm/src/armv7-r/cp15_coherent_dcache.S | 140 -------------
arch/arm/src/armv7-r/cp15_flush_dcache.S | 116 ----------
arch/arm/src/armv7-r/cp15_flush_dcache_all.S | 129 ------------
arch/arm/src/armv7-r/cp15_invalidate_dcache.S | 123 -----------
arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S | 128 -----------
20 files changed, 494 insertions(+), 1939 deletions(-)
diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs
index 2ab71d59b2..791275125d 100644
--- a/arch/arm/src/armv7-a/Make.defs
+++ b/arch/arm/src/armv7-a/Make.defs
@@ -36,11 +36,7 @@ endif
# Common assembly language files
-CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S
-CMN_ASRCS += arm_vectors.S cp15_cache_size.S cp15_clean_dcache_all.S
-CMN_ASRCS += cp15_clean_dcache.S cp15_coherent_dcache.S
-CMN_ASRCS += cp15_flush_dcache_all.S cp15_flush_dcache.S
-CMN_ASRCS += cp15_invalidate_dcache_all.S cp15_invalidate_dcache.S
+CMN_ASRCS += arm_cpuhead.S arm_vectoraddrexcptn.S arm_vectors.S
# Common C source files
@@ -49,7 +45,7 @@ CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_gicv2_dump.c
CMN_CSRCS += arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_syscall.c arm_tcbinfo.c arm_undefinedinsn.c
-CMN_CSRCS += arm_perf.c
+CMN_CSRCS += arm_perf.c cp15_cacheops.c
ifeq ($(CONFIG_ARMV7A_HAVE_PTM), y)
CMN_CSRCS += arm_timer.c
diff --git a/arch/arm/src/armv7-a/cp15_cache_size.S b/arch/arm/src/armv7-a/cp15_cache_size.S
deleted file mode 100644
index e53aac1d72..0000000000
--- a/arch/arm/src/armv7-a/cp15_cache_size.S
+++ /dev/null
@@ -1,85 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_cache_size.S
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_cache_size.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_cache_size
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_cache_size
- *
- * Description:
- * Get cp15 cache size in byte
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * Cache size in byte
- *
- ****************************************************************************/
-
- .globl cp15_cache_size
- .type cp15_cache_size, function
-
-cp15_cache_size:
-
- mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r2, r3, r0, lsr #13 /* r2=NumSets (number of sets - 1) */
- add r2, #1
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r0, lsr #3 /* r1=(number of ways - 1) */
- add r1, #1
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r0, r3 /* r0=(Log2LineSize - 2) in word */
- add r0, #4 /* r0=Log2lineSize in byte */
-
- mul r2, r1, r2 /* r2=Sets*Ways */
- lsl r0, r2, r0 /* r0=Sets*Ways*LineSize */
-
- bx lr
-
- .size cp15_cache_size, . - cp15_cache_size
- .end
diff --git a/arch/arm/src/armv7-a/cp15_cacheops.c b/arch/arm/src/armv7-a/cp15_cacheops.c
new file mode 100644
index 0000000000..fcdf566caa
--- /dev/null
+++ b/arch/arm/src/armv7-a/cp15_cacheops.c
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/cp15_cacheops.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include "cp15_cacheops.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CP15_CACHE_INVALIDATE 0
+#define CP15_CACHE_CLEAN 1
+#define CP15_CACHE_CLEANINVALIDATE 2
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline uint32_t ilog2(uint32_t u)
+{
+ int i = 0;
+
+ while (u >>= 1)
+ {
+ i++;
+ }
+
+ return i;
+}
+
+static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
+{
+ uint32_t ccsidr = CP15_GET(CCSIDR);
+
+ if (sets)
+ {
+ *sets = ((ccsidr >> 13) & 0x7fff) + 1;
+ }
+
+ if (ways)
+ {
+ *ways = ((ccsidr >> 3) & 0x3ff) + 1;
+ }
+
+ return (1 << ((ccsidr & 0x7) + 2)) * 4;
+}
+
+static void cp15_dcache_op_level(uint32_t level, int op)
+{
+ uint32_t sets;
+ uint32_t ways;
+ uint32_t set;
+ uint32_t way;
+ uint32_t line;
+ uint32_t way_shift;
+ uint32_t set_shift;
+ uint32_t val = level << 1;
+
+ /* Select by CSSELR */
+
+ CP15_SET(CSSELR, val);
+
+ /* Get cache info */
+
+ line = cp15_cache_get_info(&sets, &ways);
+
+ way_shift = 32 - ilog2(ways);
+ set_shift = ilog2(line);
+
+ ARM_DSB();
+
+ /* A: Log2(ways)
+ * B: L+S
+ * L: Log2(line)
+ * S: Log2(sets)
+ *
+ * The bits are packed as follows:
+ * 31 31-A B B-1 L L-1 4 3 1 0
+ * |---|-------------|--------|-------|-----|-|
+ * |Way| zeros | Set | zeros |level|0|
+ * |---|-------------|--------|-------|-----|-|
+ */
+
+ for (way = 0; way < ways; way++)
+ {
+ for (set = 0; set < sets; set++)
+ {
+ val = level << 1;
+ val |= way << way_shift;
+ val |= set << set_shift;
+
+ switch (op)
+ {
+ case CP15_CACHE_INVALIDATE:
+ cp15_invalidate_dcacheline_bysetway(val);
+ break;
+ case CP15_CACHE_CLEAN:
+ cp15_clean_dcache_bysetway(val);
+ break;
+ case CP15_CACHE_CLEANINVALIDATE:
+ cp15_cleaninvalidate_dcacheline(val);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ ARM_ISB();
+}
+
+static void cp15_dcache_op(int op)
+{
+ uint32_t clidr = CP15_GET(CLIDR);
+ int level;
+
+ for (level = 0; level < 7; level++)
+ {
+ uint32_t ctype = clidr & 0x7;
+
+ switch (ctype)
+ {
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ cp15_dcache_op_level(level, op);
+ break;
+ default:
+ break;
+ }
+
+ clidr >>= 3;
+ if (clidr == 0)
+ {
+ break;
+ }
+ }
+}
+
+static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
+{
+ uint32_t line;
+
+ line = cp15_cache_get_info(NULL, NULL);
+ start &= ~(line - 1);
+
+ ARM_DSB();
+
+ while (start < end)
+ {
+ switch (op)
+ {
+ case CP15_CACHE_INVALIDATE:
+ cp15_invalidate_dcacheline_bymva(start);
+ break;
+ case CP15_CACHE_CLEAN:
+ cp15_clean_dcache_bymva(start);
+ break;
+ case CP15_CACHE_CLEANINVALIDATE:
+ cp15_cleaninvalidate_dcacheline_bymva(start);
+ break;
+ default:
+ break;
+ }
+
+ start += line;
+ }
+
+ ARM_ISB();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+ cp15_invalidate_icache();
+}
+
+void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_INVALIDATE);
+}
+
+void cp15_invalidate_dcache_all(void)
+{
+ cp15_dcache_op(CP15_CACHE_INVALIDATE);
+}
+
+void cp15_clean_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_CLEAN);
+}
+
+void cp15_clean_dcache_all(void)
+{
+ cp15_dcache_op(CP15_CACHE_CLEAN);
+}
+
+void cp15_flush_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+}
+
+void cp15_flush_dcache_all(void)
+{
+ cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
+}
+
+uint32_t cp15_cache_size(void)
+{
+ uint32_t sets;
+ uint32_t ways;
+ uint32_t line;
+
+ line = cp15_cache_get_info(&sets, &ways);
+
+ return sets * ways * line;
+}
diff --git a/arch/arm/src/armv7-a/cp15_clean_dcache.S b/arch/arm/src/armv7-a/cp15_clean_dcache.S
deleted file mode 100644
index 89f980eb67..0000000000
--- a/arch/arm/src/armv7-a/cp15_clean_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_clean_dcache.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_clean_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_clean_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_clean_dcache
- *
- * Description:
- * Clean the data cache within the specified region by flushing the
- * contents of the data cache to memory.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_clean_dcache
- .type cp15_clean_dcache, function
-
-cp15_clean_dcache:
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r0, r0, r3 /* R0=aligned start address */
-
- /* Loop, cleaning each cache line by writing its contents to memory */
-
-1:
- mcr CP15_DCCMVAC(r0) /* Clean data cache line to PoC by VA */
- add r0, r0, r2 /* R12=Next cache line */
- cmp r0, r1 /* Loop until all cache lines have been cleaned */
- blo 1b
-
- dsb
- bx lr
- .size cp15_clean_dcache, . - cp15_clean_dcache
- .end
diff --git a/arch/arm/src/armv7-a/cp15_clean_dcache_all.S b/arch/arm/src/armv7-a/cp15_clean_dcache_all.S
deleted file mode 100644
index d95d31e73e..0000000000
--- a/arch/arm/src/armv7-a/cp15_clean_dcache_all.S
+++ /dev/null
@@ -1,127 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_clean_dcache_all.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_clean_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_clean_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_clean_dcache_all
- *
- * Description:
- * Clean the entire contents of D cache.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_clean_dcache_all
- .type cp15_clean_dcache_all, function
-
-cp15_clean_dcache_all:
-
- push {r4, r5}
-
- mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
- add r5, #4 /* r4=Set/way operation line shfit */
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
-
- add r4, r1, #1
- clz r4, r4
- add r4, #1 /* r4=Set/way operation Way shift */
-
-way_loop:
- mov r3, r0 /* Init Sets */
-set_loop:
- mov r2, r1, lsl r4 /* r2 = way loop counter << way shift */
- orr r2, r3, lsl r5 /* r2 = set/way cache operation format */
- mcr CP15_DCCSW(r2) /* Data Cache Clean by Set/Way */
- subs r3, r3, #1 /* Subtraction set counter */
- bcs set_loop /* Keep looping if not */
-
- subs r1, r1, #1 /* Subtraction the way counter */
- bcs way_loop /* Keep looping if not */
-
- dsb
- pop {r4, r5}
- bx lr
- .size cp15_clean_dcache_all, . - cp15_clean_dcache_all
- .end
diff --git a/arch/arm/src/armv7-a/cp15_coherent_dcache.S b/arch/arm/src/armv7-a/cp15_coherent_dcache.S
deleted file mode 100644
index 88c5feb4c3..0000000000
--- a/arch/arm/src/armv7-a/cp15_coherent_dcache.S
+++ /dev/null
@@ -1,138 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_coherent_dcache.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_coherent_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_coherent_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_coherent_dcache
- *
- * Description:
- * Ensure that the I and D caches are coherent within specified region
- * by cleaning the D cache (i.e., flushing the D cache contents to memory
- * and invalidating the I cache. This is typically used when code has been
- * written to a memory region, and will be executed.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_coherent_dcache
- .type cp15_coherent_dcache, function
-
-cp15_coherent_dcache:
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r12, r0, r3 /* R12=aligned start address */
-
- /* Loop, flushing each D cache line to memory */
-1:
- mcr CP15_DCCMVAU(r12) /* Clean data or unified cache line by VA to PoU */
- add r12, r12, r2 /* R12=Next cache line */
- cmp r12, r1 /* Loop until all cache lines have been cleaned */
- blo 1b
-
- dsb
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- and r3, r3, #0xf /* Isolate the IminLine field */
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r12, r0, r3 /* R12=aligned start address */
-
- /* Loop, invalidating each I cache line to memory */
-1:
- mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */
- add r12, r12, r2 /* R12=Next cache line */
- cmp r12, r1 /* Loop until all cache lines have been invalidated */
- blo 1b
-
- mov r0, #0
- mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */
- mcr CP15_BPIALL(r0) /* Invalidate entire branch predictor array Inner Shareable */
-
- dsb
- isb
- bx lr
- .size cp15_coherent_dcache, . - cp15_coherent_dcache
- .end
diff --git a/arch/arm/src/armv7-a/cp15_flush_dcache.S b/arch/arm/src/armv7-a/cp15_flush_dcache.S
deleted file mode 100644
index 88423cb246..0000000000
--- a/arch/arm/src/armv7-a/cp15_flush_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_flush_dcache.S
- *
- * Copyright (C) 2013, 2018 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_flush_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_flush_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_flush_dcache
- *
- * Description:
- * Flush the data cache within the specified region by cleaning and
- * invalidating the D cache.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_flush_dcache
- .type cp15_flush_dcache, function
-
-cp15_flush_dcache:
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r0, r0, r3 /* R0=aligned start address */
-
- /* Loop, cleaning and invaliding each D cache line in the address range */
-
-1:
- mcr CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
- add r0, r0, r2 /* R12=Next cache line */
- cmp r0, r1 /* Loop until all cache lines have been cleaned */
- blo 1b
-
- dsb
- bx lr
- .size cp15_flush_dcache, . - cp15_flush_dcache
- .end
diff --git a/arch/arm/src/armv7-a/cp15_flush_dcache_all.S b/arch/arm/src/armv7-a/cp15_flush_dcache_all.S
deleted file mode 100644
index ddb5d70637..0000000000
--- a/arch/arm/src/armv7-a/cp15_flush_dcache_all.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_flush_dcache_all.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_flush_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_flush_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_flush_dcache_all
- *
- * Description:
- * Flush the entire contents of D cache.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_flush_dcache_all
- .type cp15_flush_dcache_all, function
-
-cp15_flush_dcache_all:
-
- push {r4, r5}
-
- mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
- add r5, #4 /* r4=Set/way operation line shfit */
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
-
- add r4, r1, #1
- clz r4, r4
- add r4, #1 /* r4=Set/way operation Way shift */
-
-way_loop:
- mov r3, r0 /* Init Sets */
-set_loop:
- mov r2, r1, lsl r4 /* r2 = way loop counter << way shift */
- orr r2, r3, lsl r5 /* r2 = set/way cache operation format */
- mcr CP15_DCCISW(r2) /* Data Cache Clean and Invalidate by Set/Way */
- subs r3, r3, #1 /* Subtraction set counter */
- bcs set_loop /* Keep looping if not */
-
- subs r1, r1, #1 /* Subtraction the way counter */
- bcs way_loop /* Keep looping if not */
-
- dsb
- pop {r4, r5}
- bx lr
- .size cp15_flush_dcache_all, . - cp15_flush_dcache_all
- .end
diff --git a/arch/arm/src/armv7-a/cp15_invalidate_dcache.S b/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
deleted file mode 100644
index 4f04a5e74e..0000000000
--- a/arch/arm/src/armv7-a/cp15_invalidate_dcache.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_invalidate_dcache.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_invalidate_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache
- *
- * Description:
- * Invalidate the data cache within the specified region; we will be
- * performing a DMA operation in this region and we want to purge old data
- * in the cache.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache
- .type cp15_invalidate_dcache, function
-
-cp15_invalidate_dcache:
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- tst r0, r3
- bic r0, r0, r3 /* R0=aligned start address */
-
- mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
-
- tst r1, r3
- bic r1, r1, r3 /* R0=aligned end address */
- mcrne CP15_DCCIMVAC(r1) /* Clean and invalidate data cache line by VA to PoC */
-
- /* Loop, invalidating each D cache line */
-1:
- mcr CP15_DCIMVAC(r0) /* Invalidate data cache line by VA to PoC */
- add r0, r0, r2 /* R12=Next cache line */
- cmp r0, r1 /* Loop until all cache lines have been invalidate */
- blo 1b
-
- dsb
- bx lr
- .size cp15_invalidate_dcache, . - cp15_invalidate_dcache
- .end
diff --git a/arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S b/arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
deleted file mode 100644
index 9b5f95491e..0000000000
--- a/arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-a/cp15_invalidate_dcache_all.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_invalidate_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache_all
- *
- * Description:
- * Invalidate the entire contents of D cache.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache_all
- .type cp15_invalidate_dcache_all, function
-
-cp15_invalidate_dcache_all:
-
- push {r4, r5}
-
- mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
- add r5, #4 /* r4=Set/way operation line shfit */
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
-
- add r4, r1, #1
- clz r4, r4
- add r4, #1 /* r4=Set/way operation Way shift */
-
-way_loop:
- mov r3, r0 /* Init Sets */
-set_loop:
- mov r2, r1, lsl r4 /* r2 = way loop counter << way shift */
- orr r2, r3, lsl r5 /* r2 = set/way cache operation format */
- mcr CP15_DCISW(r2) /* Data Cache Invalidate by Set/Way */
- subs r3, r3, #1 /* Subtraction set counter */
- bcs set_loop /* Keep looping if not */
-
- subs r1, r1, #1 /* Subtraction the way counter */
- bcs way_loop /* Keep looping if not */
-
- dsb
- pop {r4, r5}
- bx lr
- .size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
- .end
diff --git a/arch/arm/src/armv7-r/Make.defs b/arch/arm/src/armv7-r/Make.defs
index 749c0ad60f..faece6ac8b 100644
--- a/arch/arm/src/armv7-r/Make.defs
+++ b/arch/arm/src/armv7-r/Make.defs
@@ -33,16 +33,11 @@ CMN_CSRCS += arm_cache.c arm_dataabort.c arm_doirq.c arm_gicv2.c
CMN_CSRCS += arm_initialstate.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
CMN_CSRCS += arm_syscall.c arm_tcbinfo.c arm_undefinedinsn.c
-CMN_CSRCS += arm_perf.c
+CMN_CSRCS += arm_perf.c cp15_cacheops.c
# Common C source files
-CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S
-CMN_ASRCS += arm_vectors.S cp15_cache_size.S
-CMN_ASRCS += cp15_clean_dcache_all.S cp15_clean_dcache.S
-CMN_ASRCS += cp15_coherent_dcache.S cp15_flush_dcache_all.S
-CMN_ASRCS += cp15_flush_dcache.S cp15_invalidate_dcache_all.S
-CMN_ASRCS += cp15_invalidate_dcache.S
+CMN_ASRCS += arm_head.S arm_vectoraddrexcptn.S arm_vectors.S
ifeq ($(CONFIG_ARMV7R_HAVE_PTM), y)
CMN_CSRCS += arm_timer.c
diff --git a/arch/arm/src/armv7-r/cp15_cache_size.S b/arch/arm/src/armv7-r/cp15_cache_size.S
deleted file mode 100644
index a1e6a328cc..0000000000
--- a/arch/arm/src/armv7-r/cp15_cache_size.S
+++ /dev/null
@@ -1,84 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_cache_size.S
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements. See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership. The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_cache_size.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_cache_size
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_cache_size
- *
- * Description:
- * Get cp15 cache size in byte
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * Cache size in byte
- *
- ****************************************************************************/
-
- .globl cp15_cache_size
- .type cp15_cache_size, function
-
-cp15_cache_size:
-
- mrc CP15_CCSIDR(r0) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r2, r3, r0, lsr #13 /* r2=NumSets (number of sets - 1) */
- add r2, #1
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r0, lsr #3 /* r1=(number of ways - 1) */
- add r1, #1
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r0, r3 /* r0=(Log2LineSize - 2) in word */
- add r0, #4 /* r0=Log2lineSize in byte */
-
- mul r2, r1, r2 /* r2=Sets*Ways */
- lsl r0, r2, r0 /* r0=Sets*Ways*LineSize */
-
- bx lr
-
- .size cp15_cache_size, . - cp15_cache_size
- .end
diff --git a/arch/arm/src/armv7-r/cp15_cacheops.c b/arch/arm/src/armv7-r/cp15_cacheops.c
new file mode 100644
index 0000000000..7938d3bd05
--- /dev/null
+++ b/arch/arm/src/armv7-r/cp15_cacheops.c
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/src/armv7-r/cp15_cacheops.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/cache.h>
+#include <nuttx/irq.h>
+
+#include "cp15_cacheops.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define CP15_CACHE_INVALIDATE 0
+#define CP15_CACHE_CLEAN 1
+#define CP15_CACHE_CLEANINVALIDATE 2
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline uint32_t ilog2(uint32_t u)
+{
+ int i = 0;
+
+ while (u >>= 1)
+ {
+ i++;
+ }
+
+ return i;
+}
+
+static inline uint32_t cp15_cache_get_info(uint32_t *sets, uint32_t *ways)
+{
+ uint32_t ccsidr = CP15_GET(CCSIDR);
+
+ if (sets)
+ {
+ *sets = ((ccsidr >> 13) & 0x7fff) + 1;
+ }
+
+ if (ways)
+ {
+ *ways = ((ccsidr >> 3) & 0x3ff) + 1;
+ }
+
+ return (1 << ((ccsidr & 0x7) + 2)) * 4;
+}
+
+static void cp15_dcache_op_level(uint32_t level, int op)
+{
+ uint32_t sets;
+ uint32_t ways;
+ uint32_t set;
+ uint32_t way;
+ uint32_t line;
+ uint32_t way_shift;
+ uint32_t set_shift;
+ uint32_t val = level << 1;
+
+ /* Select by CSSELR */
+
+ CP15_SET(CSSELR, val);
+
+ /* Get cache info */
+
+ line = cp15_cache_get_info(&sets, &ways);
+
+ way_shift = 32 - ilog2(ways);
+ set_shift = ilog2(line);
+
+ ARM_DSB();
+
+ /* A: Log2(ways)
+ * B: L+S
+ * L: Log2(line)
+ * S: Log2(sets)
+ *
+ * The bits are packed as follows:
+ * 31 31-A B B-1 L L-1 4 3 1 0
+ * |---|-------------|--------|-------|-----|-|
+ * |Way| zeros | Set | zeros |level|0|
+ * |---|-------------|--------|-------|-----|-|
+ */
+
+ for (way = 0; way < ways; way++)
+ {
+ for (set = 0; set < sets; set++)
+ {
+ val = level << 1;
+ val |= way << way_shift;
+ val |= set << set_shift;
+
+ switch (op)
+ {
+ case CP15_CACHE_INVALIDATE:
+ cp15_invalidate_dcacheline_bysetway(val);
+ break;
+ case CP15_CACHE_CLEAN:
+ cp15_clean_dcache_bysetway(val);
+ break;
+ case CP15_CACHE_CLEANINVALIDATE:
+ cp15_cleaninvalidate_dcacheline(val);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
+ ARM_ISB();
+}
+
+static void cp15_dcache_op(int op)
+{
+ uint32_t clidr = CP15_GET(CLIDR);
+ int level;
+
+ for (level = 0; level < 7; level++)
+ {
+ uint32_t ctype = clidr & 0x7;
+
+ switch (ctype)
+ {
+ case 0x2:
+ case 0x3:
+ case 0x4:
+ cp15_dcache_op_level(level, op);
+ break;
+ default:
+ break;
+ }
+
+ clidr >>= 3;
+ if (clidr == 0)
+ {
+ break;
+ }
+ }
+}
+
+static void cp15_dcache_op_mva(uintptr_t start, uintptr_t end, int op)
+{
+ uint32_t line;
+
+ line = cp15_cache_get_info(NULL, NULL);
+ start &= ~(line - 1);
+
+ ARM_DSB();
+
+ while (start < end)
+ {
+ switch (op)
+ {
+ case CP15_CACHE_INVALIDATE:
+ cp15_invalidate_dcacheline_bymva(start);
+ break;
+ case CP15_CACHE_CLEAN:
+ cp15_clean_dcache_bymva(start);
+ break;
+ case CP15_CACHE_CLEANINVALIDATE:
+ cp15_cleaninvalidate_dcacheline_bymva(start);
+ break;
+ default:
+ break;
+ }
+
+ start += line;
+ }
+
+ ARM_ISB();
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void cp15_coherent_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+ cp15_invalidate_icache();
+}
+
+void cp15_invalidate_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_INVALIDATE);
+}
+
+void cp15_invalidate_dcache_all(void)
+{
+ cp15_dcache_op(CP15_CACHE_INVALIDATE);
+}
+
+void cp15_clean_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_CLEAN);
+}
+
+void cp15_clean_dcache_all(void)
+{
+ cp15_dcache_op(CP15_CACHE_CLEAN);
+}
+
+void cp15_flush_dcache(uintptr_t start, uintptr_t end)
+{
+ cp15_dcache_op_mva(start, end, CP15_CACHE_CLEANINVALIDATE);
+}
+
+void cp15_flush_dcache_all(void)
+{
+ cp15_dcache_op(CP15_CACHE_CLEANINVALIDATE);
+}
+
+uint32_t cp15_cache_size(void)
+{
+ uint32_t sets;
+ uint32_t ways;
+ uint32_t line;
+
+ line = cp15_cache_get_info(&sets, &ways);
+
+ return sets * ways * line;
+}
diff --git a/arch/arm/src/armv7-r/cp15_clean_dcache.S b/arch/arm/src/armv7-r/cp15_clean_dcache.S
deleted file mode 100644
index 71a9534d8e..0000000000
--- a/arch/arm/src/armv7-r/cp15_clean_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_clean_dcache.S
- *
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_clean_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_clean_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_clean_dcache
- *
- * Description:
- * Clean the data cache within the specified region by flushing the
- * contents of the data cache to memory.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_clean_dcache
- .type cp15_clean_dcache, function
-
-cp15_clean_dcache:
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r0, r0, r3 /* R0=aligned start address */
-
- /* Loop, cleaning each cache line by writing its contents to memory */
-
-1:
- mcr CP15_DCCMVAC(r0) /* Clean data cache line to PoC by VA */
- add r0, r0, r2 /* R12=Next cache line */
- cmp r0, r1 /* Loop until all cache lines have been cleaned */
- blo 1b
-
- dsb
- bx lr
- .size cp15_clean_dcache, . - cp15_clean_dcache
- .end
diff --git a/arch/arm/src/armv7-r/cp15_clean_dcache_all.S b/arch/arm/src/armv7-r/cp15_clean_dcache_all.S
deleted file mode 100644
index 4a08dfbc70..0000000000
--- a/arch/arm/src/armv7-r/cp15_clean_dcache_all.S
+++ /dev/null
@@ -1,129 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_clean_dcache_all.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_clean_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_clean_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_clean_dcache_all
- *
- * Description:
- * clean the entire contents of D cache.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_clean_dcache_all
- .type cp15_clean_dcache_all, function
-
-cp15_clean_dcache_all:
-
- push {r4, r5}
-
- mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
- add r5, #4 /* r4=Set/way operation line shfit */
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
-
- add r4, r1, #1
- clz r4, r4
- add r4, #1 /* r4=Set/way operation Way shift */
-
-way_loop:
- mov r3, r0 /* Init Sets */
-set_loop:
- mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
- orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
- mcr CP15_DCCSW(r2) /* Data Cache Clean by Set/Way */
- subs r3, r3, #1 /* Subtraction set counter */
- bcs set_loop /* Keep looping if not */
-
- subs r1, r1, #1 /* Subtraction the way counter */
- bcs way_loop /* Keep looping if not */
-
- dsb
- pop {r4, r5}
- bx lr
- .size cp15_clean_dcache_all, . - cp15_clean_dcache_all
- .end
-
diff --git a/arch/arm/src/armv7-r/cp15_coherent_dcache.S b/arch/arm/src/armv7-r/cp15_coherent_dcache.S
deleted file mode 100644
index cb4589452b..0000000000
--- a/arch/arm/src/armv7-r/cp15_coherent_dcache.S
+++ /dev/null
@@ -1,140 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_coherent_dcache.S
- *
- * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_coherent_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_coherent_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_coherent_dcache
- *
- * Description:
- * Ensure that the I and D caches are coherent within specified region
- * by cleaning the D cache (i.e., flushing the D cache contents to memory
- * and invalidating the I cache. This is typically used when code has been
- * written to a memory region, and will be executed.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_coherent_dcache
- .type cp15_coherent_dcache, function
-
-cp15_coherent_dcache:
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r12, r0, r3 /* R12=aligned start address */
-
- /* Loop, flushing each D cache line to memory */
-1:
- mcr CP15_DCCMVAU(r12) /* Clean data or unified cache line by VA to PoU */
- add r12, r12, r2 /* R12=Next cache line */
- cmp r12, r1 /* Loop until all cache lines have been cleaned */
- blo 1b
-
- dsb
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- and r3, r3, #0xf /* Isolate the IminLine field */
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r12, r0, r3 /* R12=aligned start address */
-
- /* Loop, invalidating each I cache line to memory */
-1:
- mcr CP15_ICIMVAU(r12) /* Invalidate instruction cache by VA to PoU */
- add r12, r12, r2 /* R12=Next cache line */
- cmp r12, r1 /* Loop until all cache lines have been invalidated */
- blo 1b
-
- mov r0, #0
-#ifdef CONFIG_SMP
- mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */
-#endif
- mcr CP15_BPIALL(r0) /* Invalidate all branch predictors */
-
- dsb
- isb
- bx lr
- .size cp15_coherent_dcache, . - cp15_coherent_dcache
- .end
diff --git a/arch/arm/src/armv7-r/cp15_flush_dcache.S b/arch/arm/src/armv7-r/cp15_flush_dcache.S
deleted file mode 100644
index 2bdc4e5474..0000000000
--- a/arch/arm/src/armv7-r/cp15_flush_dcache.S
+++ /dev/null
@@ -1,116 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_flush_dcache.S
- *
- * Copyright (C) 2015, 2018 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_flush_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_flush_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_flush_dcache
- *
- * Description:
- * Flush the data cache within the specified region by cleaning and
- * invalidating the D cache.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_flush_dcache
- .type cp15_flush_dcache, function
-
-cp15_flush_dcache:
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- bic r0, r0, r3 /* R0=aligned start address */
-
- /* Loop, cleaning and invaliding each D cache line in the address range */
-
-1:
- mcr CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
- add r0, r0, r2 /* R12=Next cache line */
- cmp r0, r1 /* Loop until all cache lines have been cleaned */
- blo 1b
-
- dsb
- bx lr
- .size cp15_flush_dcache, . - cp15_flush_dcache
- .end
diff --git a/arch/arm/src/armv7-r/cp15_flush_dcache_all.S b/arch/arm/src/armv7-r/cp15_flush_dcache_all.S
deleted file mode 100644
index 747d12271d..0000000000
--- a/arch/arm/src/armv7-r/cp15_flush_dcache_all.S
+++ /dev/null
@@ -1,129 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_flush_dcache_all.S
- *
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_flush_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_flush_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_flush_dcache_all
- *
- * Description:
- * Flush the entire contents of D cache.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_flush_dcache_all
- .type cp15_flush_dcache_all, function
-
-cp15_flush_dcache_all:
-
- push {r4, r5}
-
- mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
- add r5, #4 /* r4=Set/way operation line shfit */
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
-
- add r4, r1, #1
- clz r4, r4
- add r4, #1 /* r4=Set/way operation Way shift */
-
-way_loop:
- mov r3, r0 /* Init Sets */
-set_loop:
- mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
- orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
- mcr CP15_DCCISW(r2) /* Data Cache Clean and Invalidate by Set/Way */
- subs r3, r3, #1 /* Subtraction set counter */
- bcs set_loop /* Keep looping if not */
-
- subs r1, r1, #1 /* Subtraction the way counter */
- bcs way_loop /* Keep looping if not */
-
- dsb
- pop {r4, r5}
- bx lr
- .size cp15_flush_dcache_all, . - cp15_flush_dcache_all
- .end
-
diff --git a/arch/arm/src/armv7-r/cp15_invalidate_dcache.S b/arch/arm/src/armv7-r/cp15_invalidate_dcache.S
deleted file mode 100644
index 67d11603c8..0000000000
--- a/arch/arm/src/armv7-r/cp15_invalidate_dcache.S
+++ /dev/null
@@ -1,123 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_invalidate_dcache.S
- *
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_invalidate_dcache.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache
- *
- * Description:
- * Invalidate the data cache within the specified region; we will be
- * performing a DMA operation in this region and we want to purge old data
- * in the cache.
- *
- * Input Parameters:
- * start - virtual start address of region
- * end - virtual end address of region + 1
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache
- .type cp15_invalidate_dcache, function
-
-cp15_invalidate_dcache:
-
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
- lsr r3, r3, #16 /* Isolate the DMinLine field */
- and r3, r3, #0xf
- mov r2, #4
- mov r2, r2, lsl r3 /* Get the cache line size in bytes */
-
- sub r3, r2, #1 /* R3=Cache line size mask */
- tst r0, r3
- bic r0, r0, r3 /* R0=aligned start address */
-
- mcrne CP15_DCCIMVAC(r0) /* Clean and invalidate data cache line by VA to PoC */
-
- tst r1, r3
- bic r1, r1, r3 /* R0=aligned end address */
- mcrne CP15_DCCIMVAC(r1) /* Clean and invalidate data cache line by VA to PoC */
-
- /* Loop, invalidating each D cache line */
-1:
- mcr CP15_DCIMVAC(r0) /* Invalidate data cache line by VA to PoC */
- add r0, r0, r2 /* R12=Next cache line */
- cmp r0, r1 /* Loop until all cache lines have been invalidate */
- blo 1b
-
- dsb
- bx lr
- .size cp15_invalidate_dcache, . - cp15_invalidate_dcache
- .end
diff --git a/arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S b/arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
deleted file mode 100644
index 399e8cf8e2..0000000000
--- a/arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
+++ /dev/null
@@ -1,128 +0,0 @@
-/****************************************************************************
- * arch/arm/src/armv7-r/cp15_invalidate_dcache_all.S
- *
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <gn...@nuttx.org>
- *
- * Portions of this file derive from Atmel sample code for the SAMA5D3
- * Cortex-A5 which also has a modified BSD-style license:
- *
- * Copyright (c) 2012, Atmel Corporation
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor Atmel nor the names of the contributors may
- * be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/* References:
- *
- * "Cortex-A5 MPCore, Technical Reference Manual", Revision: r0p1,
- * Copyright (c) 2010 ARM. All rights reserved. ARM DDI 0434B (ID101810)
- * "ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition",
- * Copyright (c) 1996-1998, 2000, 2004-2012 ARM. All rights reserved. ARM
- * DDI 0406C.b (ID072512)
- */
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include "cp15.h"
-
- .file "cp15_invalidate_dcache_all.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Symbols
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache_all
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
- .text
-
-/****************************************************************************
- * Name: cp15_invalidate_dcache_all
- *
- * Description:
- * Invalidate the entire contents of D cache.
- *
- * Input Parameters:
- * None
- *
- * Returned Value:
- * None
- *
- ****************************************************************************/
-
- .globl cp15_invalidate_dcache_all
- .type cp15_invalidate_dcache_all, function
-
-cp15_invalidate_dcache_all:
-
- push {r4, r5}
-
- mrc CP15_CCSIDR(r1) /* Read the Cache Size Identification Register */
-
- ldr r3, =0x7fff /* Isolate the NumSets field (bits 13-27) */
- and r0, r3, r1, lsr #13 /* r0=NumSets (number of sets - 1) */
-
- ldr r3,=0x7 /* Isolate the LineSize field (bits 0-2) */
- and r5, r3, r1 /* r4=(Log2LineSize - 2) in word */
- add r5, #4 /* r4=Set/way operation line shfit */
-
- ldr r3, =0x3ff /* Isolate the way field (bits 3-12) */
- and r1, r3, r1, lsr #3 /* r1=(number of ways - 1) */
-
- add r4, r1, #1
- clz r4, r4
- add r4, #1 /* r4=Set/way operation Way shift */
-
-way_loop:
- mov r3, r0 /* Init Sets */
-set_loop:
- mov r2, r1, lsl #30 /* r2 = way loop counter << 30 */
- orr r2, r3, lsl #5 /* r2 = set/way cache operation format */
- mcr CP15_DCISW(r2) /* Data Cache Invalidate by Set/Way */
- subs r3, r3, #1 /* Subtraction set counter */
- bcs set_loop /* Keep looping if not */
-
- subs r1, r1, #1 /* Subtraction the way counter */
- bcs way_loop /* Keep looping if not */
-
- dsb
- pop {r4, r5}
- bx lr
- .size cp15_invalidate_dcache_all, . - cp15_invalidate_dcache_all
- .end
[incubator-nuttx] 04/04: armv7-r: add VBAR cp15 opearation
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 6903f02d4111b9815aa77159132ebd86c9276a6a
Author: ligd <li...@xiaomi.com>
AuthorDate: Mon Sep 19 12:00:54 2022 +0800
armv7-r: add VBAR cp15 opearation
Signed-off-by: ligd <li...@xiaomi.com>
---
arch/arm/src/armv7-r/barriers.h | 2 ++
arch/arm/src/armv7-r/cp15.h | 3 +++
2 files changed, 5 insertions(+)
diff --git a/arch/arm/src/armv7-r/barriers.h b/arch/arm/src/armv7-r/barriers.h
index dbdd232713..030b5f4a50 100644
--- a/arch/arm/src/armv7-r/barriers.h
+++ b/arch/arm/src/armv7-r/barriers.h
@@ -34,9 +34,11 @@
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
+#define arm_nop(n) __asm__ __volatile__ ("nop\n")
#define ARM_DSB() arm_dsb(15)
#define ARM_ISB() arm_isb(15)
#define ARM_DMB() arm_dmb(15)
+#define ARM_NOP() arm_nop(15)
#endif /* __ARCH_ARM_SRC_ARMV7_R_BARRIERS_H */
diff --git a/arch/arm/src/armv7-r/cp15.h b/arch/arm/src/armv7-r/cp15.h
index b51ac20d4b..074d10314a 100644
--- a/arch/arm/src/armv7-r/cp15.h
+++ b/arch/arm/src/armv7-r/cp15.h
@@ -142,6 +142,9 @@
#define CP15_PMINTENSET(r) _CP15(0, r, c9, c14, 1) /* Interrupt Enable Set Register */
#define CP15_PMINTENCLR(r) _CP15(0, r, c9, c14, 2) /* Interrupt Enable Clear Register */
+#define CP15_VBAR(r) _CP15(0, r, c12, c0, 0) /* Vector Base Address Register */
+#define CP15_MVBAR(r) _CP15(0, r, c12, c0, 1) /* Monitor Vector Base Address Register */
+
#define CP15_CONTEXTIDR(r) _CP15(0, r, c13, c0, 1) /* Context ID Register */
#define CP15_TPIDRURW(r) _CP15(0, r, c13, c0, 2) /* Software Thread ID Registers */
#define CP15_TPIDRURO(r) _CP15(0, r, c13, c0, 3)