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Posted to commits@nuttx.apache.org by "jasonbu (via GitHub)" <gi...@apache.org> on 2026/03/06 10:01:59 UTC
[PR] imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing, verify use i.mx95-FRDM EVK [nuttx]
jasonbu opened a new pull request, #18501:
URL: https://github.com/apache/nuttx/pull/18501
## Summary
Add GPIO and eMMC (USDHC) support for the i.MX95 A55 EVK board, enabling 8-bit eMMC access with MBR/GPT partition table parsing.
## Changes
### 1. `imx9: add GPIO support for imx95`
- Add imx95 GPIO register definitions (same IP block as imx93)
- Fill `g_gpio_base[]` array for imx95
- Include `imx95_gpio.h` from the common header
- Compile `imx9_gpio.c` / `imx9_gpiobase.c` for imx95 in cmake
### 2. `imx95-a55-evk: add USDHC eMMC driver support`
- Create `imx95_pinmux.h` / `imx95_ccm.h` / `imx95_pll.h` hardware definitions for imx95
- Add USDHC1 8-bit eMMC pin mux and clock macros to `board.h`
- Create board-level `imx9_usdhc.c` glue code
- Update `imx9_bringup.c` with DMA allocator and USDHC init
- Add `CONFIG_IMX9_CLK_OVER_SCMI` compile-time guards in `imx9_usdhc.c` to isolate the IMX95 SCMI clock path from the existing IMX93 direct-CCM path — no functional change for IMX93
### 3. `imx9: usdhc fix dmapreflight rejecting small unaligned buffers`
- `imx9_dmapreflight()` rejected unaligned buffers unconditionally, but `dmarecvsetup()` has a bounce path via `priv->rxbuffer` for small transfers
- Add a `buflen > sizeof(priv->rxbuffer)` check so that small reads (e.g. ext_csd 512-byte stack buffer) can use the bounce buffer instead of failing with `-EFAULT`
### 4. `imx95-a55-evk: add MBR/GPT partition table parsing on eMMC`
- Parse the partition table on `/dev/mmcsd0` during board bringup and register each partition as `/dev/mmcsd0pN`
- Add custom MBR handler for unnamed partition entries
## Impact
- IMX93 code paths are fully preserved behind `#ifndef CONFIG_IMX9_CLK_OVER_SCMI` guards — zero functional change for existing IMX93 boards
- The `dmapreflight` fix is a generic improvement that benefits all imx9 USDHC users
- If using i.mx95-FRDM EVK, able to mount the /boot partition same with uboot/linux, after patch.
## Testing
Verified on i.MX95 FRDM EVK:
- eMMC device recognized and initialized (8-bit mode)
- Partition table parsed, partitions registered
- `mount -t vfat /dev/mmcsd0p0 /data` works
```bash
nsh> mount -t vfat /dev/mmcsd0p0 /data
nsh> ls -l /data/nuttx.bin
-rw-rw-rw- 515184 /data/nuttx.bin
```
ostest passed in i.MX95 FRDM EVK
```
[2026-03-06 17:57:11] user_main: Exiting
[2026-03-06 17:57:11] ostest_main: Exiting with status 0
[2026-03-06 17:57:11] nsh>
```
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on code in PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#discussion_r2909193160
##########
arch/arm64/src/imx9/CMakeLists.txt:
##########
@@ -24,7 +24,9 @@ set(SRCS imx9_boot.c imx9_clockconfig.c imx9_iomuxc.c imx9_lpuart.c
imx9_lowputc.c)
if(CONFIG_ARCH_CHIP_IMX93)
- list(APPEND SRCS imx9_ccm.c imx9_gpio.c)
+ list(APPEND SRCS imx9_ccm.c imx9_gpio.c imx9_gpiobase.c)
Review Comment:
Done, let's remove the .c include as it's not critical requirements
##########
arch/arm64/src/imx9/imx9_usdhc.c:
##########
@@ -1897,13 +1917,15 @@ static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
struct imx9_dev_s *priv = (struct imx9_dev_s *)dev;
uint32_t regval;
+#ifndef CONFIG_IMX9_CLK_OVER_SCMI
unsigned speed;
+#endif
/* Clear the old prescaler and divisor values so that new ones can be
* ORed in.
*/
- regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
+ regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
Review Comment:
yes, align with next line should prefer?
##########
arch/arm64/src/imx9/CMakeLists.txt:
##########
Review Comment:
Done, let's remove the .c include as it's not critical requirements
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "mzanders (via GitHub)" <gi...@apache.org>.
mzanders commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4024993189
There are some other options out there, for instance:
https://www.compulab.com/products/som-evaluation-kits/ucm-imx95-evaluation-kit/
This SoC is targeting safety critical and 'high end' automotive/industrial applications. Pricing is accordingly. These chips are on a complexity level both for HW and SW that require serious investments for companies who are going to implement them. And that's _after_ NXP has done most of the heavy lifting in terms of SW ecosystem.
I'm very interested to hear about use cases for the A55 cores in NuttX on iMX9x. In my current opinion those should really be running Linux to take full advantage of the hardware features. But I'm happy to adjust said opinion. :-)
If you're looking to host the SoC on a NuttX module, I would strongly advise to look at soldered SOM's. That avoids 12-16 layer boards, DDR routing, etc etc.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "simbit18 (via GitHub)" <gi...@apache.org>.
simbit18 commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4108486677
Hi @jasonbu, thanks for your feedback
I've updated the workflow by adding the parallel -j option for the Make build
The build times are now similar. Please note that the V=1 option is also enabled for the Make build
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "cederom (via GitHub)" <gi...@apache.org>.
cederom commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4025983978
Yup these modules are what we may look for.. NXP did not have anything like this but today I asked only at chat ;-)
https://www.compulab.com/products/system-on-modules/
$75 https://www.compulab.com/products/computer-on-modules/ucm-imx95-nxp-i-mx-95-som-system-on-module/
> NXP i.MX95 @2.0GHz
Up to 16GB LPDDR5, 128GB eMMC
ARM Mali GPU, 4K VPU and AI/ML NPU
2x LVDS, MIPI-DSI, 2x MIPI-CSI
GbE + 10GbE, 2x PCIe, USB3.0
Certified 802.11ax WiFi and BT 5.3
5x CAN, 8x UART, 8x SPI, 75x GPIO
28 x 40 mm, UCM pin2pin family
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "cederom (via GitHub)" <gi...@apache.org>.
cederom commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4023079647
Thank you @mzanders !! I got my FRDM-IMX93 but need to find some time to play maybe this week :-)
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "cederom (via GitHub)" <gi...@apache.org>.
cederom commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4026146556
ci internal failure, restarted failed jobs.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4023879894
> Manual review done, some smaller items noted. Except maybe for the inclusion of imx9_gpiobase.c by imx9_gpio.c which is rather ugly (but which was already present).
>
> To check for regressions on the iMX93, I tried building and running the A55 part of IMX93-EVK on an IMX93-QSB board for the current master ([43f65ce](https://github.com/apache/nuttx/commit/43f65ce751a08c3065040fb0866657718c46e98b) ("build(deps): bump docker/build-push-action from 6 to 7", 2026-03-09)) first. Unfortunately without succes. So it doesn't make a lot of sense to try and test this PR on target..
>
> ```
> u-boot=> fatload mmc 0:1 0x80000000 nuttx_a55.bin
> 585728 bytes read in 400 ms (1.4 MiB/s)
> u-boot=> go 0x80000000
> ## Starting application at 0x80000000 ...
> - Ready to Boot Primary CPU
> - Boot from EL2
> - Boot from EL1
> - Boot to C runtime for OS Initialize
> "Synchronous Abort" handler, esr 0x02000000
> elr: 0000000080202580 lr : 00000000012f3700 (reloc)
> elr: 00000000fef10580 lr : 0000000080001700
> x0 : 000000008008ec10 x1 : 0000000080065d38
> x2 : 0000000096000021 x3 : 0000000000000000
> x4 : 00000000443c0180 x5 : 00000000800047d8
> x6 : 0000000000003fc4 x7 : 0000000000000006
> x8 : 0000000000000003 x9 : 0000000096000021
> x10: 0000000000000025 x11: 0000000000000000
> x12: 000000000000001c x13: 00000000fcf0dd86
> x14: 0000000000000008 x15: 00000000fcefef5d
> x16: 0000000080000000 x17: 0000000000000004
> x18: 00000000fcf0dd70 x19: 000000008008ec10
> x20: 0000000000000000 x21: 0000000000000002
> x22: 00000000fcf1b390 x23: 0000000080000068
> x24: 000000008008f000 x25: 0000000080000e38
> x26: 0000000000000000 x27: 0000000000000000
> x28: 00000000fcf33650 x29: 00000000fceff7f0
>
> Code: f9403e41 1400a056 801ffe10 00000000 (feff7040)
> Resetting CPU ...
>
> resetting ...
> ```
guess crash with the CLOCK_SDIO_DISABLED place modify, but when I test with my board, the emmc break, and mount cause uboot erased, will do verify again after use uuu recover the image.
my private fork worked before #18403 , if you have a plan add support for i.mx 95, please continue, as I did not have environment to double check if i.mx 93 work as expected.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4095276360
@acassis hi Alan, the board I'm currently used is not fully public, will add board description/image later.
add emmc/defconfig to help user more easy to use, actually I have two imx95 EVK, the emmc feature is compatible.
Also update tutorial rst to help user do flash with uboot only.
hi, @mzanders could you please help evaluate the imx93 already fixed in this version? CC @cederom
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "mzanders (via GitHub)" <gi...@apache.org>.
mzanders commented on code in PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#discussion_r2904642615
##########
arch/arm64/src/imx9/imx9_usdhc.c:
##########
@@ -1897,13 +1917,15 @@ static void imx9_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
struct imx9_dev_s *priv = (struct imx9_dev_s *)dev;
uint32_t regval;
+#ifndef CONFIG_IMX9_CLK_OVER_SCMI
unsigned speed;
+#endif
/* Clear the old prescaler and divisor values so that new ones can be
* ORed in.
*/
- regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
+ regval = getreg32(priv->addr + IMX9_USDHC_SYSCTL_OFFSET);
Review Comment:
alignment change on purpose?
##########
arch/arm64/src/imx9/CMakeLists.txt:
##########
Review Comment:
Same change required on Make.defs?
##########
arch/arm64/src/imx9/CMakeLists.txt:
##########
@@ -24,7 +24,9 @@ set(SRCS imx9_boot.c imx9_clockconfig.c imx9_iomuxc.c imx9_lpuart.c
imx9_lowputc.c)
if(CONFIG_ARCH_CHIP_IMX93)
- list(APPEND SRCS imx9_ccm.c imx9_gpio.c)
+ list(APPEND SRCS imx9_ccm.c imx9_gpio.c imx9_gpiobase.c)
Review Comment:
imx9_gpiobase.c is included in imx9_gpio.c!
I don't like it either, but adding it here should give issues?
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Re: [PR] imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing, verify use i.mx95-FRDM EVK [nuttx]
Posted by "cederom (via GitHub)" <gi...@apache.org>.
cederom commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4011986141
Very nice @jasonbu thank you.. lets just wait for the CI fix :-)
@mzanders you are user of this hw too can you please take a look? :-)
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Re: [PR] imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing, verify use i.mx95-FRDM EVK [nuttx]
Posted by "simbit18 (via GitHub)" <gi...@apache.org>.
simbit18 commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4011903808
Hi @fdcavalcanti @tmedicci @eren-terzioglu We are receiving this error on all PRs. Can you check it?
```
Error: board/esp32_bringup.c:275:9: error: implicit declaration of function 'btn_lower_initialize'; did you mean 'nullmtd_initialize'? [-Wimplicit-function-declaration]
275 | ret = btn_lower_initialize("/dev/buttons");
| ^~~~~~~~~~~~~~~~~~~
```~
Boards
```
Cleaning...
HEAD detached at pull/18501/merge
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git restore <file>..." to discard changes in working directory)
modified: boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig
modified: boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig
modified: boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig
modified: boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig
modified: boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig
modified: boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig
```
```
====================================================================================
Configuration/Tool: esp32-ethernet-kit/buttons
2026-03-06 10:13:47
------------------------------------------------------------------------------------
Cleaning...
Configuring...
Building NuttX...
board/esp32_bringup.c: In function 'esp32_bringup':
Error: board/esp32_bringup.c:275:9: error: implicit declaration of function 'btn_lower_initialize'; did you mean 'nullmtd_initialize'? [-Wimplicit-function-declaration]
275 | ret = btn_lower_initialize("/dev/buttons");
| ^~~~~~~~~~~~~~~~~~~~
| nullmtd_initialize
make[1]: *** [/github/workspace/sources/nuttx/boards/Board.mk:83: esp32_bringup.o] Error 1
make[1]: Target 'libboard.a' not remade because of errors.
make: *** [tools/LibTargets.mk:89: arch/xtensa/src/board/libboard.a] Error 2
make: Target 'all' not remade because of errors.
/github/workspace/sources/nuttx/tools/testbuild.sh: line 385: /github/workspace/sources/nuttx/../nuttx/nuttx.manifest: No such file or directory
[1/1] Normalize esp32-ethernet-kit/buttons
18d17
< CONFIG_ARCH_IRQBUTTONS=y
34d32
< CONFIG_INPUT_BUTTONS_LOWER=y
Saving the new configuration file
HEAD detached at pull/18501/merge
Changes not staged for commit:
(use "git add <file>..." to update what will be committed)
(use "git restore <file>..." to discard changes in working directory)
modified: boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig
no changes added to commit (use "git add" and/or "git commit -a")
====================================================================================
```
https://github.com/apache/nuttx/actions/runs/22758561387/job/66009383296#logs
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "lupyuen (via GitHub)" <gi...@apache.org>.
lupyuen commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4097546359
Hi @jasonbu: I'm testing a new way to Build PRs in Our Own NuttX Repos, wonder if you would like to try out, and give your feedback to @simbit18 and me? Thank you so much :-)
1. [Demo Video in YouTube](https://youtu.be/19w_CeaANLw) <br> [Demo Video in Google Drive](https://drive.google.com/file/d/10RUJ2gnj2UqmTZZrKCmwhEw8DT3LYFh0/view?usp=drive_link)
2. Browse to [github.com/NuttX/manual-nuttx-ci](http://github.com/NuttX/manual-nuttx-ci)
3. Click "Fork" to clone the repo
4. Click "Actions > Enable GitHub Actions"
5. Click "Manually Build NuttX > Run Workflow"
6. Enter the following:
- Repo for NuttX: jasonbu/nuttx
- NuttX Branch: imx95_emmc8bit
- Repo for NuttX Apps: apache/nuttx-apps
- NuttX Apps Branch: master
- Host Platform: all
7. And the PR Build should start. Lemme know if it doesn't work thanks!
8. Why are we doing this? Earlier this year, we saw very high usage of GitHub Runners. By building PRs in Our Own NuttX Repos, we will greatly reduce our usage of GitHub Runners, so that ASF Infrastructure Team won't revoke our access to GitHub CI. So we hope everyone can help out thanks :-)
<img width="2144" height="1669" alt="Screenshot 2026-03-20 at 5 00 45 PM" src="https://github.com/user-attachments/assets/3d006d00-b0c2-4161-9919-3c0240f164e6" />
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "lupyuen (via GitHub)" <gi...@apache.org>.
lupyuen commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4108406435
Thank you so much @jasonbu! Hi @simbit18 anything you would like to add? :-)
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4108350310
> Thanks @jasonbu! Yes you are correct, if our PR involves One Single Defconfig, it's definitely easier to run Docker to test the PR.
>
> The method that I suggested (manual-nuttx-ci) is more suitable for PRs that affect Multiple Architectures, so manual-nuttx-ci is simpler than running Multiple Docker Builds. Or maybe we have devs who are not familiar with Docker, then they can use manual-nuttx-ci too.
>
> We have just implemented a new feature to build One Single Defconfig, it might be helpful too. Thanks :-)
>
> <img alt="Screenshot 2026-03-23 at 12 33 24 PM" width="1906" height="1653" src="https://private-user-images.githubusercontent.com/9960133/567524100-682061d0-c9fa-4371-8eb2-fe3891f2b9c8.png?jwt=eyJ0eXAiOiJKV1QiLCJhbGciOiJIUzI1NiJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NzQyNDc0NjgsIm5iZiI6MTc3NDI0NzE2OCwicGF0aCI6Ii85OTYwMTMzLzU2NzUyNDEwMC02ODIwNjFkMC1jOWZhLTQzNzEtOGViMi1mZTM4OTFmMmI5YzgucG5nP1gtQW16LUFsZ29yaXRobT1BV1M0LUhNQUMtU0hBMjU2JlgtQW16LUNyZWRlbnRpYWw9QUtJQVZDT0RZTFNBNTNQUUs0WkElMkYyMDI2MDMyMyUyRnVzLWVhc3QtMSUyRnMzJTJGYXdzNF9yZXF1ZXN0JlgtQW16LURhdGU9MjAyNjAzMjNUMDYyNjA4WiZYLUFtei1FeHBpcmVzPTMwMCZYLUFtei1TaWduYXR1cmU9NjQyNGFlMTk0Y2YwZDM1ZTljNjcxZTdkYzFmYjFmNDMwNGQ3NjhlYmYwZjIzZDVhMjg2Y2MyZWI4ZTk1NTllZCZYLUFtei1TaWduZWRIZWFkZXJzPWhvc3QifQ.mIgLItzo-BxFjNjY9earz1wI4--_dezP096_n7SdYHc">
https://github.com/jasonbu/manual-nuttx-ci/actions/runs/23424198384
Thanks for your effort, it worked for my fork. @lupyuen
<img width="755" height="392" alt="image" src="https://github.com/user-attachments/assets/3ba2f5bf-f01c-46a6-91fd-ab513584a800" />
Also it show the cmake is faster than Makefile.
CMake with 3m46s VS Make 5m12s.
These speed looks like the triggered ci job did not enable the -j parallel compile. Don't know if it's expected or limitation by github action performace.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "cederom (via GitHub)" <gi...@apache.org>.
cederom commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4095291093
I just lost contract, need to do some things first, will play with iMX a bit later, sorry, I am sure this update is good if it works for you, go ahead do not wait for me :-)
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4024400907
@jasonbu is that one: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX95
Seems like it is not available for selling yet
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Re: [PR] imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing, verify use i.mx95-FRDM EVK [nuttx]
Posted by "fdcavalcanti (via GitHub)" <gi...@apache.org>.
fdcavalcanti commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4011918395
> Hi @fdcavalcanti @tmedicci @eren-terzioglu We are receiving this error on all PRs. Can you check it?
>
> ```
> Error: board/esp32_bringup.c:275:9: error: implicit declaration of function 'btn_lower_initialize'; did you mean 'nullmtd_initialize'? [-Wimplicit-function-declaration]
> 275 | ret = btn_lower_initialize("/dev/buttons");
> | ^~~~~~~~~~~~~~~~~~~
> ```
>
> Boards
>
> ```
> Cleaning...
> HEAD detached at pull/18501/merge
> Changes not staged for commit:
> (use "git add <file>..." to update what will be committed)
> (use "git restore <file>..." to discard changes in working directory)
> modified: boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig
> modified: boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig
> modified: boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig
> modified: boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig
> modified: boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig
> modified: boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig
> ```
>
> ```
> ====================================================================================
> Configuration/Tool: esp32-ethernet-kit/buttons
> 2026-03-06 10:13:47
> ------------------------------------------------------------------------------------
> Cleaning...
> Configuring...
> Building NuttX...
> board/esp32_bringup.c: In function 'esp32_bringup':
> Error: board/esp32_bringup.c:275:9: error: implicit declaration of function 'btn_lower_initialize'; did you mean 'nullmtd_initialize'? [-Wimplicit-function-declaration]
> 275 | ret = btn_lower_initialize("/dev/buttons");
> | ^~~~~~~~~~~~~~~~~~~~
> | nullmtd_initialize
> make[1]: *** [/github/workspace/sources/nuttx/boards/Board.mk:83: esp32_bringup.o] Error 1
> make[1]: Target 'libboard.a' not remade because of errors.
> make: *** [tools/LibTargets.mk:89: arch/xtensa/src/board/libboard.a] Error 2
> make: Target 'all' not remade because of errors.
> /github/workspace/sources/nuttx/tools/testbuild.sh: line 385: /github/workspace/sources/nuttx/../nuttx/nuttx.manifest: No such file or directory
> [1/1] Normalize esp32-ethernet-kit/buttons
> 18d17
> < CONFIG_ARCH_IRQBUTTONS=y
> 34d32
> < CONFIG_INPUT_BUTTONS_LOWER=y
> Saving the new configuration file
> HEAD detached at pull/18501/merge
> Changes not staged for commit:
> (use "git add <file>..." to update what will be committed)
> (use "git restore <file>..." to discard changes in working directory)
> modified: boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig
>
> no changes added to commit (use "git add" and/or "git commit -a")
> ====================================================================================
> ```
>
> https://github.com/apache/nuttx/actions/runs/22758561387/job/66009383296#logs
There's a fix coming very soon.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4107856317
> Hi @jasonbu: I'm testing a new way to Build PRs in Our Own NuttX Repos, wonder if you would like to try out, and give your feedback to @simbit18 and me? Thank you so much :-)
>
> 1. [Demo Video in YouTube](https://youtu.be/19w_CeaANLw) [Demo Video in Google Drive](https://drive.google.com/file/d/10RUJ2gnj2UqmTZZrKCmwhEw8DT3LYFh0/view?usp=drive_link)
> 2. Browse to [github.com/NuttX/manual-nuttx-ci](https://github.com/NuttX/manual-nuttx-ci)
> 3. Click "Fork" to clone the repo
> 4. Click "Actions > Enable GitHub Actions"
> 5. Click "Manually Build NuttX > Run Workflow"
> 6. Enter the following:
>
> * Repo for NuttX: jasonbu/nuttx
> * NuttX Branch: imx95_emmc8bit
> * Repo for NuttX Apps: apache/nuttx-apps
> * NuttX Apps Branch: master
> * Host Platform: all
> 7. And the PR Build should start. Lemme know if it doesn't work thanks!
> 8. Why are we doing this? Earlier this year, we saw very high usage of GitHub Runners. By building PRs in Our Own NuttX Repos, we will greatly reduce our usage of GitHub Runners, so that ASF Infrastructure Team won't revoke our access to GitHub CI. So we hope everyone can help out thanks :-)
>
> <img alt="Screenshot 2026-03-20 at 5 00 45 PM" width="2000" height="1669" src="https://private-user-images.githubusercontent.com/9960133/566811366-3d006d00-b0c2-4161-9919-3c0240f164e6.png?jwt=eyJ0eXAiOiJKV1QiLCJhbGciOiJIUzI1NiJ9.eyJpc3MiOiJnaXRodWIuY29tIiwiYXVkIjoicmF3LmdpdGh1YnVzZXJjb250ZW50LmNvbSIsImtleSI6ImtleTUiLCJleHAiOjE3NzQyMzg3MjIsIm5iZiI6MTc3NDIzODQyMiwicGF0aCI6Ii85OTYwMTMzLzU2NjgxMTM2Ni0zZDAwNmQwMC1iMGMyLTQxNjEtOTkxOS0zYzAyNDBmMTY0ZTYucG5nP1gtQW16LUFsZ29yaXRobT1BV1M0LUhNQUMtU0hBMjU2JlgtQW16LUNyZWRlbnRpYWw9QUtJQVZDT0RZTFNBNTNQUUs0WkElMkYyMDI2MDMyMyUyRnVzLWVhc3QtMSUyRnMzJTJGYXdzNF9yZXF1ZXN0JlgtQW16LURhdGU9MjAyNjAzMjNUMDQwMDIyWiZYLUFtei1FeHBpcmVzPTMwMCZYLUFtei1TaWduYXR1cmU9ODJmYzU1N2IzNjliY2NhZDYxOGUwZmM4OGU0NGRhM2IzNjBlOTMwNjgwZDlmM2NiMDU0N2ZmOGM3ZjU5ZjEyOCZYLUFtei1TaWduZWRIZWFkZXJzPWhvc3QifQ.R9K0gruaKh7xcuHniWEOo8Som4NS0MM9D_i1OUK_Ffg">
Hi, @lupyuen , will try today, I found my ci error maybe defconfig refresh required. and if I just force push to this pr/branch. maybe trigger a new apache/nuttx CI, so guess I need to new a branch to avoid the github action auto retrigger. will give a feedback to you.
By the way. I see the action in your picture is try run whole action ci in personal fork. and when I fork the repo, it need to choose specific defconfig? Is it due to the personal ci job cost? it is a real problem.
but if only run single defconfig/ci job, the local docker container should more easy to use?
Also the personal fork will more difficult to do the ensure ready before trigger apache nuttx CI.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "anchao (via GitHub)" <gi...@apache.org>.
anchao commented on code in PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#discussion_r2963874395
##########
arch/arm64/src/imx9/hardware/imx9_ccm.h:
##########
@@ -34,6 +34,7 @@
# include "hardware/imx93/imx93_ccm.h"
# include "hardware/imx93/imx93_pll.h"
#elif defined(CONFIG_ARCH_CHIP_IMX95)
+# include "hardware/imx95/imx95_ccm.h"
Review Comment:
```suggestion
# include "hardware/imx95/imx95_ccm.h"
# include "hardware/imx95/imx95_pll.h"
```
##########
arch/arm64/src/imx9/hardware/imx95/imx95_pll.h:
##########
@@ -0,0 +1,197 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx95/imx95_pll.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX95_IMX95_PLL_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX95_IMX95_PLL_H
+
+/* All registers besides STATUS have SET, CLR, TGL and VAL shadow registers */
+
+#define PLL_REG_VAL_OFFSET (0x00)
+#define PLL_REG_SET_OFFSET (0x04)
+#define PLL_REG_CLR_OFFSET (0x08)
+#define PLL_REG_TGL_OFFSET (0x0c)
+
+/* User can access the individual registers via these macros */
+
+#define PLL_VAL(n) ((n) + PLL_REG_VAL_OFFSET) /* Same as the register itself */
+#define PLL_SET(n) ((n) + PLL_REG_SET_OFFSET)
+#define PLL_CLR(n) ((n) + PLL_REG_CLR_OFFSET)
+#define PLL_TGL(n) ((n) + PLL_REG_TGL_OFFSET)
+
+/* Common offsets for all PLL registers, existence depends on the register
+ * itself
+ */
+
+#define PLL_CTRL_OFFSET (0x00) /* PLL Control */
+#define PLL_SPREAD_SPECTRUM_OFFSET (0x30) /* Spread Spectrum */
+#define PLL_NUMERATOR_OFFSET (0x40) /* Numerator */
+#define PLL_DENOMINATOR_OFFSET (0x50) /* Denominator */
+#define PLL_DIV_OFFSET (0x60) /* PLL Dividers */
+#define PLL_DFS_CTRL_0_OFFSET (0x70) /* DFS Control */
+#define PLL_DFS_DIV_0_OFFSET (0x80) /* DFS Division_0 */
+#define PLL_DFS_CTRL_1_OFFSET (0x90) /* DFS Control */
+#define PLL_DFS_DIV_1_OFFSET (0xa0) /* DFS Division_1 */
+#define PLL_DFS_CTRL_2_OFFSET (0xb0) /* DFS Control */
+#define PLL_DFS_DIV_2_OFFSET (0xc0) /* DFS Division_2 */
+#define PLL_PLL_STATUS_OFFSET (0xf0) /* PLL Status */
+#define PLL_DFS_STATUS_OFFSET (0xf4) /* DFS Status */
+
+/* Register addresses */
+
+#define PLL_CTRL(n) ((n) + PLL_CTRL_OFFSET)
+#define PLL_SPREAD_SPECTRUM(n) ((n) + PLL_SPREAD_SPECTRUM_OFFSET)
+#define PLL_NUMERATOR(n) ((n) + PLL_NUMERATOR_OFFSET)
+#define PLL_DENOMINATOR(n) ((n) + PLL_DENOMINATOR_OFFSET)
+#define PLL_DIV(n) ((n) + PLL_DIV_OFFSET)
+#define PLL_DFS_CTRL_0(n) ((n) + PLL_DFS_CTRL_0_OFFSET)
+#define PLL_DFS_DIV_0(n) ((n) + PLL_DFS_DIV_0_OFFSET)
+#define PLL_DFS_CTRL_1(n) ((n) + PLL_DFS_CTRL_1_OFFSET)
+#define PLL_DFS_DIV_1(n) ((n) + PLL_DFS_DIV_1_OFFSET)
+#define PLL_DFS_CTRL_2(n) ((n) + PLL_DFS_CTRL_2_OFFSET)
+#define PLL_DFS_DIV_2(n) ((n) + PLL_DFS_DIV_2_OFFSET)
+#define PLL_PLL_STATUS(n) ((n) + PLL_PLL_STATUS_OFFSET)
+#define PLL_DFS_STATUS(n) ((n) + PLL_DFS_STATUS_OFFSET)
+
+/* SYSPLL registers */
+
+#define SYSPLL_CTRL (IMX9_SYSPLL_BASE + PLL_CTRL_OFFSET)
+#define SYSPLL_SPREAD_SPECTRUM (IMX9_SYSPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
+#define SYSPLL_NUMERATOR (IMX9_SYSPLL_BASE + PLL_NUMERATOR_OFFSET)
+#define SYSPLL_DENOMINATOR (IMX9_SYSPLL_BASE + PLL_DENOMINATOR_OFFSET)
+#define SYSPLL_DIV (IMX9_SYSPLL_BASE + PLL_DIV_OFFSET)
+#define SYSPLL_DFS_CTRL_0 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_0_OFFSET)
+#define SYSPLL_DFS_DIV_0 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_0_OFFSET)
+#define SYSPLL_DFS_CTRL_1 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_1_OFFSET)
+#define SYSPLL_DFS_DIV_1 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_1_OFFSET)
+#define SYSPLL_DFS_CTRL_2 (IMX9_SYSPLL_BASE + PLL_DFS_CTRL_2_OFFSET)
+#define SYSPLL_DFS_DIV_2 (IMX9_SYSPLL_BASE + PLL_DFS_DIV_2_OFFSET)
+#define SYSPLL_PLL_STATUS (IMX9_SYSPLL_BASE + PLL_PLL_STATUS_OFFSET)
+#define SYSPLL_DFS_STATUS (IMX9_SYSPLL_BASE + PLL_DFS_STATUS_OFFSET)
+
+/* ARMPLL registers */
+
+#define ARMPLL_CTRL (IMX9_ARMPLL_BASE + PLL_CTRL_OFFSET)
+#define ARMPLL_DIV (IMX9_ARMPLL_BASE + PLL_DIV_OFFSET)
+#define ARMPLL_PLL_STATUS (IMX9_ARMPLL_BASE + PLL_PLL_STATUS_OFFSET)
+
+/* AUDIOPLL registers */
+
+#define AUDIOPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET)
+#define AUDIOPLL_SPREAD_SPECTRUM (IMX9_AUDIOPLL_BASE + PLL_SPREAD_SPECTRUM_OFFSET)
+#define AUDIOPLL_NUMERATOR (IMX9_AUDIOPLL_BASE + PLL_NUMERATOR_OFFSET)
+#define AUDIOPLL_DENOMINATOR (IMX9_AUDIOPLL_BASE + PLL_DENOMINATOR_OFFSET)
+#define AUDIOPLL_DIV (IMX9_AUDIOPLL_BASE + PLL_DIV_OFFSET)
+#define AUDIOPLL_PLL_STATUS (IMX9_AUDIOPLL_BASE + PLL_PLL_STATUS_OFFSET)
+
+/* DRAMPLL registers */
+
+#define DRAMPLL_CTRL (IMX9_AUDIOPLL_BASE + PLL_CTRL_OFFSET)
Review Comment:
```suggestion
#define DRAMPLL_CTRL (IMX9_DRAMPLL_BASE + PLL_CTRL_OFFSET)
```
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4024022898
> @jasonbu is that board? https://www.nxp.com/part/IMX95LPD5EVK-19
>
> wow, U$ 1,200.00, I think this company didn't learn anything from ST!
hi, @acassis searched the public website, did not found the board, maybe later.
it's verify similar with https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX93 this one.
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4023946091
@jasonbu is that board? https://www.nxp.com/part/IMX95LPD5EVK-19
wow, U$ 1,200.00, I think this company didn't learn anything from ST!
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "cederom (via GitHub)" <gi...@apache.org>.
cederom commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4024380232
> > @acassis: @jasonbu is that board? https://www.nxp.com/part/IMX95LPD5EVK-19
> > wow, U$ 1,200.00, I think this company didn't learn anything from ST!
>
> @jasonbu: hi, @acassis searched the public website, did not found the board, maybe later. it's verify similar with https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX93 this one.
@mzanders recommended me that board too and it just arrived, at reasonable price ~80EUR, available at Mouser https://www.mouser.pl/ProductDetail/NXP-Semiconductors/FRDM-IMX93?qs=%252BXxaIXUDbq3oe%252BtsgKnJ3Q%3D%3D :-)
I just asked NXP today if they have some EVK/EVB devkits available as free samples but they can only provide free samples for the bare chips.. so we may use that option at NuttX Base Board SOM :-)
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 commented on code in PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#discussion_r2964451710
##########
arch/arm64/src/imx9/hardware/imx95/imx95_ccm.h:
##########
@@ -0,0 +1,753 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx95/imx95_ccm.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX95_IMX95_CCM_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX95_IMX95_CCM_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define IMX9_CCM_CR_CTRL_OFFSET(n) (0x0000 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */
+#define IMX9_CCM_CR_CTRL_SET_OFFSET(n) (0x0004 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_SET, n=0..94) */
+#define IMX9_CCM_CR_CTRL_CLR_OFFSET(n) (0x0008 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_CLR, n=0..94) */
+#define IMX9_CCM_CR_CTRL_TOG_OFFSET(n) (0x000c + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_TOG, n=0..94) */
+#define IMX9_CCM_CR_STAT0_OFFSET(n) (0x0020 + ((n) << 7)) /* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */
+#define IMX9_CCM_CR_AUTH_OFFSET(n) (0x0030 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */
+#define IMX9_CCM_CR_AUTH_SET_OFFSET(n) (0x0034 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_SET, n=0..94) */
+#define IMX9_CCM_CR_AUTH_CLR_OFFSET(n) (0x0038 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_CLR, n=0..94) */
+#define IMX9_CCM_CR_AUTH_TOG_OFFSET(n) (0x003c + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_TOG, n=0..94) */
+
+#define IMX9_CCM_GPR_SH_OFFSET(n) (0x4800 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn, n=0..7) */
+#define IMX9_CCM_GPR_SH_SET_OFFSET(n) (0x4804 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_SET, n=0..7) */
+#define IMX9_CCM_GPR_SH_CLR_OFFSET(n) (0x4808 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_CLR, n=0..7) */
+#define IMX9_CCM_GPR_SH_TOG_OFFSET(n) (0x480c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_TOG, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_OFFSET(n) (0x4810 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n) (0x4814 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_SET, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n) (0x4818 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_CLR, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n) (0x481c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_TOG, n=0..7) */
+
+#define IMX9_CCM_GPR_PR_OFFSET(n) (0x4c00 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn, n=1..7) */
+#define IMX9_CCM_GPR_PR_SET_OFFSET(n) (0x4c04 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_SET, n=1..7) */
+#define IMX9_CCM_GPR_PR_CLR_OFFSET(n) (0x4c08 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_CLR, n=1..7) */
+#define IMX9_CCM_GPR_PR_TOG_OFFSET(n) (0x4c0c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_TOG, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_OFFSET(n) (0x4c10 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n) (0x4c14 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_SET, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n) (0x4c18 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_CLR, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n) (0x4c1c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_TOG, n=1..7) */
+
+#define IMX9_CCM_OSCPLL_DIR_OFFSET(n) (0x5000 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n) (0x5004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n) (0x5008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM0_OFFSET(n) (0x5010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM1_OFFSET(n) (0x5014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM_CUR_OFFSET(n) (0x501C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_STAT0_OFFSET(n) (0x5020 + ((n) << 6)) /* Clock source working status (OSCPLLn_STATUS0, n=0..18) */
+#define IMX9_CCM_OSCPLL_STAT1_OFFSET(n) (0x5024 + ((n) << 6)) /* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */
+#define IMX9_CCM_OSCPLL_AUTH_OFFSET(n) (0x5030 + ((n) << 6)) /* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */
+
+#define IMX9_CCM_LPCG_DIR_OFFSET(n) (0x8000 + ((n) << 6)) /* LPCG direct control (LPCGn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n) (0x8004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n) (0x8008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM0_OFFSET(n) (0x8010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM1_OFFSET(n) (0x8014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM_CUR_OFFSET(n) (0x801C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_STAT0_OFFSET(n) (0x8020 + ((n) << 6)) /* LPCG working status (LPCGn_STATUS0, n=0..126) */
+#define IMX9_CCM_LPCG_STAT1_OFFSET(n) (0x8024 + ((n) << 6)) /* LPCG low power status (LPCGn_STATUS1, n=0..126) */
+#define IMX9_CCM_LPCG_AUTH_OFFSET(n) (0x8030 + ((n) << 6)) /* LPCG access control (LPCGn_AUTHEN, n=0..126) */
+
+/* Register addresses *******************************************************/
+
+#define IMX9_CCM_CR_CTRL(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_OFFSET(n))
+#define IMX9_CCM_CR_CTRL_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_SET_OFFSET(n))
+#define IMX9_CCM_CR_CTRL_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_CLR_OFFSET(n))
+#define IMX9_CCM_CR_CTRL_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_TOG_OFFSET(n))
+#define IMX9_CCM_CR_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_STAT0_OFFSET(n))
+#define IMX9_CCM_CR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_OFFSET(n))
+#define IMX9_CCM_CR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_SET_OFFSET(n))
+#define IMX9_CCM_CR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_CLR_OFFSET(n))
+#define IMX9_CCM_CR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_TOG_OFFSET(n))
+
+#define IMX9_CCM_GPR_SH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_OFFSET(n))
+#define IMX9_CCM_GPR_SH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_SET_OFFSET(n))
+#define IMX9_CCM_GPR_SH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_SH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_TOG_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n))
+
+#define IMX9_CCM_GPR_PR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_OFFSET(n))
+#define IMX9_CCM_GPR_PR_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_SET_OFFSET(n))
+#define IMX9_CCM_GPR_PR_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_PR_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_TOG_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n))
+
+#define IMX9_CCM_OSCPLL_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_DIR_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM0_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT0_OFFSET(n))
+#define IMX9_CCM_OSCPLL_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_AUTH_OFFSET(n))
+
+#define IMX9_CCM_LPCG_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_DIR_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM0_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n))
+#define IMX9_CCM_LPCG_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT0_OFFSET(n))
+#define IMX9_CCM_LPCG_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT1_OFFSET(n))
+#define IMX9_CCM_LPCG_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_AUTH_OFFSET(n))
+
+/* Register bit definitions *************************************************/
+
+/* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */
+
+#define CCM_CR_CTRL_DIV_SHIFT (0) /* Bits 0-7: Divide selected clock by DIV+1 (DIV) */
+#define CCM_CR_CTRL_DIV_MASK (0xff << CCM_CR_CTRL_DIV_SHIFT)
+# define CCM_CR_CTRL_DIV(n) (((n)-1) << CCM_CR_CTRL_DIV_SHIFT) /* Divide selected clock by n */
+
+#define CCM_CR_CTRL_MUX_SHIFT (8) /* Bits 8-9: Select clock from 8 clock sources (MUX) */
+#define CCM_CR_CTRL_MUX_MASK (0x03 << CCM_CR_CTRL_MUX_SHIFT)
+# define CCM_CR_CTRL_MUX_SRCSEL(n) ((n) << CCM_CR_CTRL_MUX_SHIFT) /* Select clock source n */
+
+ /* Bits 11-23: Reserved */
+#define CCM_CR_CTRL_OFF (1 << 24) /* Bit 24: Shutdown clock root (OFF) */
+ /* Bits 25-31: Reserved */
+
+/* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */
+
+#define CCM_CR_STAT0_DIV_SHIFT (0) /* Bits 0-7: Current clock root DIV setting (DIV) */
+#define CCM_CR_STAT0_DIV_MASK (0xff << CCM_CR_STAT0_DIV_SHIFT)
+#define CCM_CR_STAT0_MUX_SHIFT (8) /* Bits 8-9: Current clock root MUX setting (MUX) */
+#define CCM_CR_STAT0_MUX_MASK (0x03 << CCM_CR_STAT0_MUX_SHIFT)
+ /* Bits 11-23: Reserved */
+#define CCM_CR_STAT0_OFF (1 << 24) /* Bit 24: Current clock root OFF setting (OFF) */
+ /* Bits 25-27: Reserved */
+#define CCM_CR_STAT0_SLICE_BUSY (1 << 28) /* Bit 28: Clock generation logic is applying the new setting (SLICE_BUSY) */
+#define CCM_CR_STAT0_CHANGING (1 << 31) /* Bit 31: Clock generation logic is updating currently (CHANGING) */
+
+/* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */
+
+#define CCM_CR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */
+#define CCM_CR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_CR_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_CR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_CR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_CR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT)
+
+/* General Purpose Register (GPR_SHAREDn, n=0..7) */
+
+#define CCM_GPR_SH_GPR_SHIFT (0) /* Bits 0-31: General purpose register, shared for all CPU domains (GPR) */
+#define CCM_GPR_SH_GPR_MASK (0xffffffff << CCM_GPR_SH_GPR_SHIFT)
+#define CCM_GPR_A55_CLK_SEL_SHIFT (0)
+#define CCM_GPR_A55_CLK_SEL_MASK (0x01 << CCM_GPR_A55_CLK_SEL_SHIFT)
+#define CCM_GPR_A55_CLK_SEL_CCM (0 << 0)
+#define CCM_GPR_A55_CLK_SEL_PLL (1 << 0)
+
+/* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */
+
+#define CCM_GPR_SH_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */
+#define CCM_GPR_SH_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_GPR_SH_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_GPR_SH_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_GPR_SH_AUTH_WHITE_LIST_MASK (0xffff << CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT)
+
+/* General Purpose Register (GPR_PRIVATEn, n=1..7) */
+
+#define CCM_GPR_PR_GPR_SHIFT (0) /* Bits 0-31: General purpose register, with dedicated bits for each domain (GPR) */
+#define CCM_GPR_PR_GPR_MASK (0xffffffff << CCM_GPR_PR_GPR_SHIFT)
+
+/* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */
+
+#define CCM_GPR_PR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */
+#define CCM_GPR_PR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_GPR_PR_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_GPR_PR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_GPR_PR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_GPR_PR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT)
+
+/* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+
+#define CCM_OSCPLL_DIR_ON (1 << 0) /* Bit 0: Turn on clock source (ON) */
+ /* Bits 1-31: Reserved */
+
+/* Clock source LPM status (OSCPLLn_LPM_STATUS0/1, n=0..18) */
+
+#define CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */
+#define CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT)
+#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */
+#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT)
+# define CCM_OSCPLL_LPM_STAT_ON (0) /* CPU is in RUN mode */
+# define CCM_OSCPLL_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */
+# define CCM_OSCPLL_LPM_STAT_STOP (2) /* CPU is in STOP mode */
+# define CCM_OSCPLL_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */
+
+/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */
+
+#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT (4)
+#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT)
+#define CCM_OSCPLL_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK)
+
+/* Clock source LPM mode (OSCPLLn_LPM_0/1 and _CUR, n=0..18) */
+
+#define CCM_OSCPLL_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */
+#define CCM_OSCPLL_LPM_MODE_MASK (0x07 << CCM_OSCPLL_LPM_MODE_SHIFT)
+# define CCM_OSCPLL_LPM_MODE_OFF (0) /* Clock is off during all modes */
+# define CCM_OSCPLL_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */
+# define CCM_OSCPLL_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */
+# define CCM_OSCPLL_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */
+# define CCM_OSCPLL_LPM_MODE_ALL (4) /* Clock is on during all modes */
+
+/* CPU domain[n] from OSCPLLn_LPM_0/1 */
+
+#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT (4)
+#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT)
+#define CCM_OSCPLL_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_OSCPLL_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n))
+#define CCM_OSCPLL_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_MODE_MASK)
+
+/* Clock source working status (OSCPLLn_STATUS0, n=0..18) */
+
+#define CCM_OSCPLL_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */
+ /* Bits 1-3: Reserved */
+#define CCM_OSCPLL_STAT0_STATUS_EARLY (1 << 4) /* Bit 4: Clock source is active (STATUS_EARLY) */
+#define CCM_OSCPLL_STAT0_STATUS_LATE (1 << 5) /* Bit 5: Clock source is ready to use (STATUS_LATE) */
+ /* Bits 6-11: Reserved */
+#define CCM_OSCPLL_STAT0_IN_USE (1 << 12) /* Bit 28: Indicates whether the clock source is being used by active clock roots (IN_USE) */
+ /* Bits 16-31: Reserved */
+
+/* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */
+
+#define CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT (0) /* Bits 0-15: Domain active */
+#define CCM_OSCPLL_STAT1_DOM_ACTIVE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT)
+#define CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT (16) /* Bits 16-32: Domain enabled */
+#define CCM_OSCPLL_STAT1_DOM_ENABLE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT)
+
+/* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */
+
+#define CCM_OSCPLL_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */
+#define CCM_OSCPLL_AUTH_AUTO_CTRL (1 << 3) /* Bit 2: Auto mode (AUTO_CTRL) */
+#define CCM_OSCPLL_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */
+#define CCM_OSCPLL_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */
+#define CCM_OSCPLL_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_OSCPLL_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_OSCPLL_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_OSCPLL_AUTH_WHITE_LIST_MASK (0xffff << CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT)
+
+/* LPCG direct control (LPCGn_DIRECT, n=0..126) */
+
+#define CCM_LPCG_DIR_ON (1 << 0) /* Bit 0: LPCG on (ON) */
+ /* Bit 1: Reserved */
+#define CCM_LPCG_ACK_TIMEOUT_EN (1 << 2) /* Bit 2: Ack timeout enable */
+ /* Bits 3-31: Reserved */
+
+/* Clock source LPM status (LPCGn_LPM_STATUS0/1, n=0..18) */
+
+#define CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */
+#define CCM_LPCG_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT)
+#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */
+#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT)
+# define CCM_LPCG_LPM_STAT_ON (0) /* CPU is in RUN mode */
+# define CCM_LPCG_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */
+# define CCM_LPCG_LPM_STAT_STOP (2) /* CPU is in STOP mode */
+# define CCM_LPCG_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */
+
+/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */
+
+#define CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT (4)
+#define CCM_LPCG_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT)
+#define CCM_LPCG_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_LPCG_LPM_STAT_CPU_MODE_MASK)
+
+/* Clock source LPM mode (LPCGn_LPM_0/1 and _CUR, n=0..18) */
+
+#define CCM_LPCG_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */
+#define CCM_LPCG_LPM_MODE_MASK (0x07 << CCM_LPCG_LPM_MODE_SHIFT)
+# define CCM_LPCG_LPM_MODE_OFF (0) /* Clock is off during all modes */
+# define CCM_LPCG_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */
+# define CCM_LPCG_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */
+# define CCM_LPCG_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */
+# define CCM_LPCG_LPM_MODE_ALL (4) /* Clock is on during all modes */
+
+/* CPU domain[n] from LPCGn_LPM_0/1 */
+
+#define CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT (4)
+#define CCM_LPCG_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT)
+#define CCM_LPCG_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_LPCG_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n))
+#define CCM_LPCG_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) & CCM_LPCG_LPM_MODE_MASK)
+
+/* LPCG working status (LPCGn_STATUS0, n=0..126) */
+
+#define CCM_LPCG_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */
+ /* Bits 1-31 Reserved */
+
+/* LPCG low power status (LPCGn_STATUS1, n=0..126) */
+
+#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT (8) /* Bits 8-11: Domains that own this clock source according to whitelist (ACTIVE_DOMAIN) */
+#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_MASK (0x0f << CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT)
+#define CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT (8) /* Bits 12-15: Enable status from each domain (DOMAIN_ENABLE) */
+#define CCM_LPCG_STAT0_DOMAIN_ENABLE_MASK (0x0f << CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* LPCG access control (LPCGn_AUTHEN, n=0..126) */
+
+#define CCM_LPCG_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */
+#define CCM_LPCG_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */
+#define CCM_LPCG_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */
+#define CCM_LPCG_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_LPCG_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_LPCG_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_LPCG_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_LPCG_AUTH_WHITE_LIST_MASK (0xffff << CCM_LPCG_AUTH_WHITE_LIST_SHIFT)
+
+/* Auth access bits */
+
+#define CCM_AUTH_TZ_USER(n) ((n) << 8)
+#define CCM_AUTH_TZ_NS(n) ((n) << 9)
+#define CCM_AUTH_LOCK_TZ(n) ((n) << 11)
+
+/* Clock roots */
+
+#define CCM_CR_A55PERIPH 0 /* CLOCK Root Arm A55 Periph. */
+#define CCM_CR_A55MTRBUS 1 /* CLOCK Root Arm A55 MTR BUS. */
+#define CCM_CR_A55 2 /* CLOCK Root Arm A55. */
+#define CCM_CR_M33 3 /* CLOCK Root M33. */
+#define CCM_CR_SENTINEL 4 /* CLOCK Root Sentinel. */
+#define CCM_CR_BUSWAKEUP 5 /* CLOCK Root Bus Wakeup. */
+#define CCM_CR_BUSAON 6 /* CLOCK Root Bus Aon. */
+#define CCM_CR_WAKEUPAXI 7 /* CLOCK Root Wakeup Axi. */
+#define CCM_CR_SWOTRACE 8 /* CLOCK Root Swo Trace. */
+#define CCM_CR_M33SYSTICK 9 /* CLOCK Root M33 Systick. */
+#define CCM_CR_FLEXIO1 10 /* CLOCK Root Flexio1. */
+#define CCM_CR_FLEXIO2 11 /* CLOCK Root Flexio2. */
+#define CCM_CR_LPIT1 12 /* CLOCK Root Lpit1. */
+#define CCM_CR_LPIT2 13 /* CLOCK Root Lpit2. */
+#define CCM_CR_LPTMR1 14 /* CLOCK Root Lptmr1. */
+#define CCM_CR_LPTMR2 15 /* CLOCK Root Lptmr2. */
+#define CCM_CR_TPM1 16 /* CLOCK Root Tpm1. */
+#define CCM_CR_TPM2 17 /* CLOCK Root Tpm2. */
+#define CCM_CR_TPM3 18 /* CLOCK Root Tpm3. */
+#define CCM_CR_TPM4 19 /* CLOCK Root Tpm4. */
+#define CCM_CR_TPM5 20 /* CLOCK Root Tpm5. */
+#define CCM_CR_TPM6 21 /* CLOCK Root Tpm6. */
+#define CCM_CR_FLEXSPI1 22 /* CLOCK Root Flexspi1. */
+#define CCM_CR_CAN1 23 /* CLOCK Root Can1. */
+#define CCM_CR_CAN2 24 /* CLOCK Root Can2. */
+#define CCM_CR_LPUART1 25 /* CLOCK Root Lpuart1. */
+#define CCM_CR_LPUART2 26 /* CLOCK Root Lpuart2. */
+#define CCM_CR_LPUART3 27 /* CLOCK Root Lpuart3. */
+#define CCM_CR_LPUART4 28 /* CLOCK Root Lpuart4. */
+#define CCM_CR_LPUART5 29 /* CLOCK Root Lpuart5. */
+#define CCM_CR_LPUART6 30 /* CLOCK Root Lpuart6. */
+#define CCM_CR_LPUART7 31 /* CLOCK Root Lpuart7. */
+#define CCM_CR_LPUART8 32 /* CLOCK Root Lpuart8. */
+#define CCM_CR_LPI2C1 33 /* CLOCK Root Lpi2c1. */
+#define CCM_CR_LPI2C2 34 /* CLOCK Root Lpi2c2. */
+#define CCM_CR_LPI2C3 35 /* CLOCK Root Lpi2c3. */
+#define CCM_CR_LPI2C4 36 /* CLOCK Root Lpi2c4. */
+#define CCM_CR_LPI2C5 37 /* CLOCK Root Lpi2c5. */
+#define CCM_CR_LPI2C6 38 /* CLOCK Root Lpi2c6. */
+#define CCM_CR_LPI2C7 39 /* CLOCK Root Lpi2c7. */
+#define CCM_CR_LPI2C8 40 /* CLOCK Root Lpi2c8. */
+#define CCM_CR_LPSPI1 41 /* CLOCK Root Lpspi1. */
+#define CCM_CR_LPSPI2 42 /* CLOCK Root Lpspi2. */
+#define CCM_CR_LPSPI3 43 /* CLOCK Root Lpspi3. */
+#define CCM_CR_LPSPI4 44 /* CLOCK Root Lpspi4. */
+#define CCM_CR_LPSPI5 45 /* CLOCK Root Lpspi5. */
+#define CCM_CR_LPSPI6 46 /* CLOCK Root Lpspi6. */
+#define CCM_CR_LPSPI7 47 /* CLOCK Root Lpspi7. */
+#define CCM_CR_LPSPI8 48 /* CLOCK Root Lpspi8. */
+#define CCM_CR_I3C1 49 /* CLOCK Root I3c1. */
+#define CCM_CR_I3C2 50 /* CLOCK Root I3c2. */
+#define CCM_CR_USDHC1 51 /* CLOCK Root Usdhc1. */
+#define CCM_CR_USDHC2 52 /* CLOCK Root Usdhc2. */
+#define CCM_CR_USDHC3 53 /* CLOCK Root Usdhc3. */
+#define CCM_CR_SAI1 54 /* CLOCK Root Sai1. */
+#define CCM_CR_SAI2 55 /* CLOCK Root Sai2. */
+#define CCM_CR_SAI3 56 /* CLOCK Root Sai3. */
+#define CCM_CR_CCMCKO1 57 /* CLOCK Root Ccm Cko1. */
+#define CCM_CR_CCMCKO2 58 /* CLOCK Root Ccm Cko2. */
+#define CCM_CR_CCMCKO3 59 /* CLOCK Root Ccm Cko3. */
+#define CCM_CR_CCMCKO4 60 /* CLOCK Root Ccm Cko4. */
+#define CCM_CR_HSIO 61 /* CLOCK Root Hsio. */
+#define CCM_CR_HSIOUSBTEST60M 62 /* CLOCK Root Hsio Usb Test 60M. */
+#define CCM_CR_HSIOACSCAN80M 63 /* CLOCK Root Hsio Acscan 80M. */
+#define CCM_CR_HSIOACSCAN480M 64 /* CLOCK Root Hsio Acscan 480M. */
+#define CCM_CR_NIC 65 /* CLOCK Root Nic. */
+#define CCM_CR_NICAPB 66 /* CLOCK Root Nic Apb. */
+#define CCM_CR_MLAPB 67 /* CLOCK Root Ml Apb. */
+#define CCM_CR_ML 68 /* CLOCK Root Ml. */
+#define CCM_CR_MEDIAAXI 69 /* CLOCK Root Media Axi. */
+#define CCM_CR_MEDIAAPB 70 /* CLOCK Root Media Apb. */
+#define CCM_CR_MEDIALDB 71 /* CLOCK Root Media Ldb. */
+#define CCM_CR_MEDIADISPPIX 72 /* CLOCK Root Media Disp Pix. */
+#define CCM_CR_CAMPIX 73 /* CLOCK Root Cam Pix. */
+#define CCM_CR_MIPITESTBYTE 74 /* CLOCK Root Mipi Test Byte. */
+#define CCM_CR_MIPIPHYCFG 75 /* CLOCK Root Mipi Phy Cfg. */
+#define CCM_CR_DRAMALT 76 /* CLOCK Root Dram Alt. */
+#define CCM_CR_DRAMAPB 77 /* CLOCK Root Dram Apb. */
+#define CCM_CR_ADC 78 /* CLOCK Root Adc. */
+#define CCM_CR_PDM 79 /* CLOCK Root Pdm. */
+#define CCM_CR_TSTMR1 80 /* CLOCK Root Tstmr1. */
+#define CCM_CR_TSTMR2 81 /* CLOCK Root Tstmr2. */
+#define CCM_CR_MQS1 82 /* CLOCK Root MQS1. */
+#define CCM_CR_MQS2 83 /* CLOCK Root MQS2. */
+#define CCM_CR_AUDIOXCVR 84 /* CLOCK Root Audio XCVR. */
+#define CCM_CR_SPDIF 85 /* CLOCK Root Spdif. */
+#define CCM_CR_ENET 86 /* CLOCK Root Enet. */
+#define CCM_CR_ENETTIMER1 87 /* CLOCK Root Enet Timer1. */
+#define CCM_CR_ENETTIMER2 88 /* CLOCK Root Enet Timer2. */
+#define CCM_CR_ENETREF 89 /* CLOCK Root Enet Ref. */
+#define CCM_CR_ENETREFPHY 90 /* CLOCK Root Enet Ref Phy. */
+#define CCM_CR_I3C1SLOW 91 /* CLOCK Root I3c1Slow. */
+#define CCM_CR_I3C2SLOW 92 /* CLOCK Root I3c2Slow. */
+#define CCM_CR_USBPHYBURUNIN 93 /* CLOCK Root Usb Phy Burunin. */
+#define CCM_CR_PALCAMESCAN 94 /* CLOCK Root Pal Came Scan. */
+
+/* Clock gates */
+
+#define CCM_LPCG_A55 0
+#define CCM_LPCG_CM33 1
+#define CCM_LPCG_ARM_TROUT 2
+#define CCM_LPCG_SENTINEL 3
+#define CCM_LPCG_SIM_WAKEUP 4
+#define CCM_LPCG_SIM_AON 5
+#define CCM_LPCG_SIM_MEGA 6
+#define CCM_LPCG_ANADIG 7
+#define CCM_LPCG_SRC 8
+#define CCM_LPCG_CCM 9
+#define CCM_LPCG_GPC 10
+#define CCM_LPCG_ADC1 11
+#define CCM_LPCG_WDOG1 12
+#define CCM_LPCG_WDOG2 13
+#define CCM_LPCG_WDOG3 14
+#define CCM_LPCG_WDOG4 15
+#define CCM_LPCG_WDOG5 16
+#define CCM_LPCG_SEMA1 17
+#define CCM_LPCG_SEMA2 18
+#define CCM_LPCG_MU_A 19
+#define CCM_LPCG_MU_B 20
+#define CCM_LPCG_EDMA3 21
+#define CCM_LPCG_EDMA4 22
+#define CCM_LPCG_ROMCP_A55 23
+#define CCM_LPCG_ROMCP_M33 24
+#define CCM_LPCG_FLEXSPI1 25
+#define CCM_LPCG_AON_TRDC 26
+#define CCM_LPCG_WKUP_TRDC 27
+#define CCM_LPCG_OCOTP 28
+#define CCM_LPCG_BBSM_HP 29
+#define CCM_LPCG_BBSM 30
+#define CCM_LPCG_CSTRACE 31
+#define CCM_LPCG_CSSWO 32
+#define CCM_LPCG_IOMUXC 33
+#define CCM_LPCG_GPIO1 34
+#define CCM_LPCG_GPIO2 35
+#define CCM_LPCG_GPIO3 36
+#define CCM_LPCG_GPIO4 37
+#define CCM_LPCG_FLEXIO1 38
+#define CCM_LPCG_FLEXIO2 39
+#define CCM_LPCG_LPIT1 40
+#define CCM_LPCG_LPIT2 41
+#define CCM_LPCG_LPTMR1 42
+#define CCM_LPCG_LPTMR2 43
+#define CCM_LPCG_TPM1 44
+#define CCM_LPCG_TPM2 45
+#define CCM_LPCG_TPM3 46
+#define CCM_LPCG_TPM4 47
+#define CCM_LPCG_TPM5 48
+#define CCM_LPCG_TPM6 49
+#define CCM_LPCG_CAN1 50
+#define CCM_LPCG_CAN2 51
+#define CCM_LPCG_LPUART1 52
+#define CCM_LPCG_LPUART2 53
+#define CCM_LPCG_LPUART3 54
+#define CCM_LPCG_LPUART4 55
+#define CCM_LPCG_LPUART5 56
+#define CCM_LPCG_LPUART6 57
+#define CCM_LPCG_LPUART7 58
+#define CCM_LPCG_LPUART8 59
+#define CCM_LPCG_LPI2C1 60
+#define CCM_LPCG_LPI2C2 61
+#define CCM_LPCG_LPI2C3 62
+#define CCM_LPCG_LPI2C4 63
+#define CCM_LPCG_LPI2C5 64
+#define CCM_LPCG_LPI2C6 65
+#define CCM_LPCG_LPI2C7 66
+#define CCM_LPCG_LPI2C8 67
+#define CCM_LPCG_LPSPI1 68
+#define CCM_LPCG_LPSPI2 69
+#define CCM_LPCG_LPSPI3 70
+#define CCM_LPCG_LPSPI4 71
+#define CCM_LPCG_LPSPI5 72
+#define CCM_LPCG_LPSPI6 73
+#define CCM_LPCG_LPSPI7 74
+#define CCM_LPCG_LPSPI8 75
+#define CCM_LPCG_I3C1 76
+#define CCM_LPCG_I3C2 77
+#define CCM_LPCG_USDHC1 78
+#define CCM_LPCG_USDHC2 79
+#define CCM_LPCG_USDHC3 80
+#define CCM_LPCG_SAI1 81
+#define CCM_LPCG_SAI2 82
+#define CCM_LPCG_SAI3 83
+#define CCM_LPCG_SSI_W2AO 84
+#define CCM_LPCG_SSI_AO2W 85
+#define CCM_LPCG_MIPI_CSI 86
+#define CCM_LPCG_MIPI_DSI 87
+#define CCM_LPCG_LVDS 88
+#define CCM_LPCG_LCDIF 89
+#define CCM_LPCG_PXP 90
+#define CCM_LPCG_ISI 91
+#define CCM_LPCG_NIC_MEDIA 92
+#define CCM_LPCG_DDR_DFI 93
+#define CCM_LPCG_DDR_CTL 94
+#define CCM_LPCG_DDR_DFI_CTL 95
+#define CCM_LPCG_DDR_SSI 96
+#define CCM_LPCG_DDR_BYPASS 97
+#define CCM_LPCG_DDR_APB 98
+#define CCM_LPCG_DDR_DRAMPLL 99
+#define CCM_LPCG_DDR_CLK_CTL 100
+#define CCM_LPCG_NIC_CENTRAL 101
+#define CCM_LPCG_GIC600 102
+#define CCM_LPCG_NIC_APB 103
+#define CCM_LPCG_USB_CONTROLLER 104
+#define CCM_LPCG_USB_TEST_60M 105
+#define CCM_LPCG_HSIO_TROUT_24M 106
+#define CCM_LPCG_PDM 107
+#define CCM_LPCG_MQS1 108
+#define CCM_LPCG_MQS2 109
+#define CCM_LPCG_AUD_XCVR 110
+#define CCM_LPCG_NICMIX_MECC 111
+#define CCM_LPCG_SPDIF 112
+#define CCM_LPCG_SSI_ML2NIC 113
+#define CCM_LPCG_SSI_MED2NIC 114
+#define CCM_LPCG_SSI_HSIO2NIC 115
+#define CCM_LPCG_SSI_W2NIC 116
+#define CCM_LPCG_SSI_NIC2W 117
+#define CCM_LPCG_SSI_NIC2DDR 118
+#define CCM_LPCG_HSIO_32K 119
+#define CCM_LPCG_ENET1 120
+#define CCM_LPCG_ENET_QOS 121
+#define CCM_LPCG_SYS_CNT 122
+#define CCM_LPCG_TSTMR1 123
+#define CCM_LPCG_TSTMR2 124
+#define CCM_LPCG_TMC 125
+#define CCM_LPCG_PMRO 126
+
+/* Shared register indices */
+
+#define CCM_SHARED_EXT_CLK 0
+#define CCM_SHARED_A55_CLK 1
+#define CCM_SHARED_DRAM_CLK 2
+#define CCM_SHARED_GPR_COUNT 7
+
+/* Other parameters */
+
+#ifndef CONFIG_IMX9_CLK_OVER_SCMI
+
+#define ROOT_MUX_MAX 4 /* Count of root clock MUX options */
+#define CCM_CR_COUNT 94 /* Count of clock roots */
+#define CCM_LPCG_COUNT 126 /* Count of clock gates */
+#define CCM_OSCPLL_COUNT 18 /* Count of osc plls */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* NOTE: The PLL input (IN) clocks are not available in clock tree */
+
+enum ccm_clock_name_e
+{
+ OSC_24M = 0, /* 24MHZ OSCILLATOR. */
+ ARM_PLL = 1, /* ARM PLL */
+ ARM_PLLOUT = 2, /* ARM PLL OUT */
+ SYS_PLL1_IN = 3, /* SYSTEM PLL1 IN */
+ SYS_PLL1PFD0_IN = 4, /* SYSTEM PLL1 PFD0 IN */
+ SYS_PLL1PFD0 = 5, /* SYSTEM PLL1 PFD0 */
+ SYS_PLL1PFD0DIV2 = 6, /* SYSTEM PLL1 PFD0 DIV2 */
+ SYS_PLL1PFD1_IN = 7, /* SYSTEM PLL1 PFD1 IN */
+ SYS_PLL1PFD1 = 8, /* SYSTEM PLL1 PFD1 */
+ SYS_PLL1PFD1DIV2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */
+ SYS_PLL1PFD2_IN = 10, /* SYSTEM PLL1 PFD2 IN */
+ SYS_PLL1PFD2 = 11, /* SYSTEM PLL1 PFD2 */
+ SYS_PLL1PFD2DIV2 = 12, /* SYSTEM PLL1 PFD2 DIV2 */
+ AUDIO_PLL1 = 13, /* AUDIO PLL1 */
+ AUDIO_PLL1OUT = 14, /* AUDIO PLL1 OUT */
+ DRAM_PLL = 15, /* DRAM PLL */
+ DRAM_PLLOUT = 16, /* DRAM PLL OUT */
+ VIDEO_PLL1 = 17, /* VIDEO PLL1 */
+ VIDEO_PLL1OUT = 18, /* VIDEO PLL1 OUT */
+ EXT = 19, /* EXT */
+};
+
+/* This contains a simple LUT to find the corresponding MUX index per root */
+
+static const int g_ccm_root_mux[][ROOT_MUX_MAX] =
Review Comment:
should we move to source file
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "jasonbu (via GitHub)" <gi...@apache.org>.
jasonbu commented on code in PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#discussion_r2964480702
##########
arch/arm64/src/imx9/hardware/imx95/imx95_ccm.h:
##########
@@ -0,0 +1,753 @@
+/****************************************************************************
+ * arch/arm64/src/imx9/hardware/imx95/imx95_ccm.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX95_IMX95_CCM_H
+#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX95_IMX95_CCM_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define IMX9_CCM_CR_CTRL_OFFSET(n) (0x0000 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */
+#define IMX9_CCM_CR_CTRL_SET_OFFSET(n) (0x0004 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_SET, n=0..94) */
+#define IMX9_CCM_CR_CTRL_CLR_OFFSET(n) (0x0008 + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_CLR, n=0..94) */
+#define IMX9_CCM_CR_CTRL_TOG_OFFSET(n) (0x000c + ((n) << 7)) /* Clock root control (CLOCK_ROOTn_CONTROL_TOG, n=0..94) */
+#define IMX9_CCM_CR_STAT0_OFFSET(n) (0x0020 + ((n) << 7)) /* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */
+#define IMX9_CCM_CR_AUTH_OFFSET(n) (0x0030 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */
+#define IMX9_CCM_CR_AUTH_SET_OFFSET(n) (0x0034 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_SET, n=0..94) */
+#define IMX9_CCM_CR_AUTH_CLR_OFFSET(n) (0x0038 + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_CLR, n=0..94) */
+#define IMX9_CCM_CR_AUTH_TOG_OFFSET(n) (0x003c + ((n) << 7)) /* Clock root access control (CLOCK_ROOTn_AUTHEN_TOG, n=0..94) */
+
+#define IMX9_CCM_GPR_SH_OFFSET(n) (0x4800 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn, n=0..7) */
+#define IMX9_CCM_GPR_SH_SET_OFFSET(n) (0x4804 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_SET, n=0..7) */
+#define IMX9_CCM_GPR_SH_CLR_OFFSET(n) (0x4808 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_CLR, n=0..7) */
+#define IMX9_CCM_GPR_SH_TOG_OFFSET(n) (0x480c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_TOG, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_OFFSET(n) (0x4810 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n) (0x4814 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_SET, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n) (0x4818 + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_CLR, n=0..7) */
+#define IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n) (0x481c + ((n) << 5)) /* General Purpose Register (GPR_SHAREDn_AUTHEN_TOG, n=0..7) */
+
+#define IMX9_CCM_GPR_PR_OFFSET(n) (0x4c00 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn, n=1..7) */
+#define IMX9_CCM_GPR_PR_SET_OFFSET(n) (0x4c04 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_SET, n=1..7) */
+#define IMX9_CCM_GPR_PR_CLR_OFFSET(n) (0x4c08 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_CLR, n=1..7) */
+#define IMX9_CCM_GPR_PR_TOG_OFFSET(n) (0x4c0c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_TOG, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_OFFSET(n) (0x4c10 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n) (0x4c14 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_SET, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n) (0x4c18 + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_CLR, n=1..7) */
+#define IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n) (0x4c1c + (((n)-1) << 5)) /* General Purpose Register (GPR_PRIVATEn_AUTHEN_TOG, n=1..7) */
+
+#define IMX9_CCM_OSCPLL_DIR_OFFSET(n) (0x5000 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n) (0x5004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n) (0x5008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM0_OFFSET(n) (0x5010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM1_OFFSET(n) (0x5014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_LPM_CUR_OFFSET(n) (0x501C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+#define IMX9_CCM_OSCPLL_STAT0_OFFSET(n) (0x5020 + ((n) << 6)) /* Clock source working status (OSCPLLn_STATUS0, n=0..18) */
+#define IMX9_CCM_OSCPLL_STAT1_OFFSET(n) (0x5024 + ((n) << 6)) /* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */
+#define IMX9_CCM_OSCPLL_AUTH_OFFSET(n) (0x5030 + ((n) << 6)) /* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */
+
+#define IMX9_CCM_LPCG_DIR_OFFSET(n) (0x8000 + ((n) << 6)) /* LPCG direct control (LPCGn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n) (0x8004 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n) (0x8008 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM0_OFFSET(n) (0x8010 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM1_OFFSET(n) (0x8014 + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_LPM_CUR_OFFSET(n) (0x801C + ((n) << 6)) /* Clock source direct control (OSCPLLn_DIRECT, n=0..126) */
+#define IMX9_CCM_LPCG_STAT0_OFFSET(n) (0x8020 + ((n) << 6)) /* LPCG working status (LPCGn_STATUS0, n=0..126) */
+#define IMX9_CCM_LPCG_STAT1_OFFSET(n) (0x8024 + ((n) << 6)) /* LPCG low power status (LPCGn_STATUS1, n=0..126) */
+#define IMX9_CCM_LPCG_AUTH_OFFSET(n) (0x8030 + ((n) << 6)) /* LPCG access control (LPCGn_AUTHEN, n=0..126) */
+
+/* Register addresses *******************************************************/
+
+#define IMX9_CCM_CR_CTRL(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_OFFSET(n))
+#define IMX9_CCM_CR_CTRL_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_SET_OFFSET(n))
+#define IMX9_CCM_CR_CTRL_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_CLR_OFFSET(n))
+#define IMX9_CCM_CR_CTRL_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_CTRL_TOG_OFFSET(n))
+#define IMX9_CCM_CR_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_STAT0_OFFSET(n))
+#define IMX9_CCM_CR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_OFFSET(n))
+#define IMX9_CCM_CR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_SET_OFFSET(n))
+#define IMX9_CCM_CR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_CLR_OFFSET(n))
+#define IMX9_CCM_CR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_CR_AUTH_TOG_OFFSET(n))
+
+#define IMX9_CCM_GPR_SH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_OFFSET(n))
+#define IMX9_CCM_GPR_SH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_SET_OFFSET(n))
+#define IMX9_CCM_GPR_SH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_SH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_TOG_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_SET_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_SH_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_SH_AUTH_TOG_OFFSET(n))
+
+#define IMX9_CCM_GPR_PR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_OFFSET(n))
+#define IMX9_CCM_GPR_PR_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_SET_OFFSET(n))
+#define IMX9_CCM_GPR_PR_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_PR_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_TOG_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH_SET(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_SET_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH_CLR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_CLR_OFFSET(n))
+#define IMX9_CCM_GPR_PR_AUTH_TOG(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_GPR_PR_AUTH_TOG_OFFSET(n))
+
+#define IMX9_CCM_OSCPLL_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_DIR_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT0_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM_STAT1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM0_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_LPM1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT0_OFFSET(n))
+#define IMX9_CCM_OSCPLL_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_STAT1_OFFSET(n))
+#define IMX9_CCM_OSCPLL_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_OSCPLL_AUTH_OFFSET(n))
+
+#define IMX9_CCM_LPCG_DIR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_DIR_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT0_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM_STAT1_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM0_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n))
+#define IMX9_CCM_LPCG_LPM_CUR(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_LPM1_OFFSET(n))
+#define IMX9_CCM_LPCG_STAT0(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT0_OFFSET(n))
+#define IMX9_CCM_LPCG_STAT1(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_STAT1_OFFSET(n))
+#define IMX9_CCM_LPCG_AUTH(n) (IMX9_CCM_CTRL_BASE + IMX9_CCM_LPCG_AUTH_OFFSET(n))
+
+/* Register bit definitions *************************************************/
+
+/* Clock root control (CLOCK_ROOTn_CONTROL, n=0..94) */
+
+#define CCM_CR_CTRL_DIV_SHIFT (0) /* Bits 0-7: Divide selected clock by DIV+1 (DIV) */
+#define CCM_CR_CTRL_DIV_MASK (0xff << CCM_CR_CTRL_DIV_SHIFT)
+# define CCM_CR_CTRL_DIV(n) (((n)-1) << CCM_CR_CTRL_DIV_SHIFT) /* Divide selected clock by n */
+
+#define CCM_CR_CTRL_MUX_SHIFT (8) /* Bits 8-9: Select clock from 8 clock sources (MUX) */
+#define CCM_CR_CTRL_MUX_MASK (0x03 << CCM_CR_CTRL_MUX_SHIFT)
+# define CCM_CR_CTRL_MUX_SRCSEL(n) ((n) << CCM_CR_CTRL_MUX_SHIFT) /* Select clock source n */
+
+ /* Bits 11-23: Reserved */
+#define CCM_CR_CTRL_OFF (1 << 24) /* Bit 24: Shutdown clock root (OFF) */
+ /* Bits 25-31: Reserved */
+
+/* Clock root working status (CLOCK_ROOTn_STATUS0, n=0..94) */
+
+#define CCM_CR_STAT0_DIV_SHIFT (0) /* Bits 0-7: Current clock root DIV setting (DIV) */
+#define CCM_CR_STAT0_DIV_MASK (0xff << CCM_CR_STAT0_DIV_SHIFT)
+#define CCM_CR_STAT0_MUX_SHIFT (8) /* Bits 8-9: Current clock root MUX setting (MUX) */
+#define CCM_CR_STAT0_MUX_MASK (0x03 << CCM_CR_STAT0_MUX_SHIFT)
+ /* Bits 11-23: Reserved */
+#define CCM_CR_STAT0_OFF (1 << 24) /* Bit 24: Current clock root OFF setting (OFF) */
+ /* Bits 25-27: Reserved */
+#define CCM_CR_STAT0_SLICE_BUSY (1 << 28) /* Bit 28: Clock generation logic is applying the new setting (SLICE_BUSY) */
+#define CCM_CR_STAT0_CHANGING (1 << 31) /* Bit 31: Clock generation logic is updating currently (CHANGING) */
+
+/* Clock root access control (CLOCK_ROOTn_AUTHEN, n=0..94) */
+
+#define CCM_CR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */
+#define CCM_CR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_CR_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_CR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_CR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_CR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT)
+
+/* General Purpose Register (GPR_SHAREDn, n=0..7) */
+
+#define CCM_GPR_SH_GPR_SHIFT (0) /* Bits 0-31: General purpose register, shared for all CPU domains (GPR) */
+#define CCM_GPR_SH_GPR_MASK (0xffffffff << CCM_GPR_SH_GPR_SHIFT)
+#define CCM_GPR_A55_CLK_SEL_SHIFT (0)
+#define CCM_GPR_A55_CLK_SEL_MASK (0x01 << CCM_GPR_A55_CLK_SEL_SHIFT)
+#define CCM_GPR_A55_CLK_SEL_CCM (0 << 0)
+#define CCM_GPR_A55_CLK_SEL_PLL (1 << 0)
+
+/* General Purpose Register (GPR_SHAREDn_AUTHEN, n=0..7) */
+
+#define CCM_GPR_SH_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */
+#define CCM_GPR_SH_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_GPR_SH_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_GPR_SH_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_GPR_SH_AUTH_WHITE_LIST_MASK (0xffff << CCM_GPR_SH_AUTH_WHITE_LIST_SHIFT)
+
+/* General Purpose Register (GPR_PRIVATEn, n=1..7) */
+
+#define CCM_GPR_PR_GPR_SHIFT (0) /* Bits 0-31: General purpose register, with dedicated bits for each domain (GPR) */
+#define CCM_GPR_PR_GPR_MASK (0xffffffff << CCM_GPR_PR_GPR_SHIFT)
+
+/* General Purpose Register (GPR_PRIVATEn_AUTHEN, n=1..7) */
+
+#define CCM_GPR_PR_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock root can be changed in user mode (TZ_USER) */
+#define CCM_GPR_PR_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock root can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_GPR_PR_AUTH_LOCK_TZ (1 << 11) /* Bit 1: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_GPR_PR_AUTH_LOCK_LIST (1 << 12) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_GPR_PR_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_GPR_PR_AUTH_WHITE_LIST_MASK (0xffff << CCM_CR_AUTH_WHITE_LIST_SHIFT)
+
+/* Clock source direct control (OSCPLLn_DIRECT, n=0..18) */
+
+#define CCM_OSCPLL_DIR_ON (1 << 0) /* Bit 0: Turn on clock source (ON) */
+ /* Bits 1-31: Reserved */
+
+/* Clock source LPM status (OSCPLLn_LPM_STATUS0/1, n=0..18) */
+
+#define CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */
+#define CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_OSCPLL_LPM_STAT_CPU_MODE_SHIFT)
+#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */
+#define CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_OSCPLL_LPM_STAT_CPU_TRANS_REQ_SHIFT)
+# define CCM_OSCPLL_LPM_STAT_ON (0) /* CPU is in RUN mode */
+# define CCM_OSCPLL_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */
+# define CCM_OSCPLL_LPM_STAT_STOP (2) /* CPU is in STOP mode */
+# define CCM_OSCPLL_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */
+
+/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */
+
+#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT (4)
+#define CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_STAT_CPU_DOMAIN_SHIFT)
+#define CCM_OSCPLL_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_OSCPLL_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_STAT_CPU_MODE_MASK)
+
+/* Clock source LPM mode (OSCPLLn_LPM_0/1 and _CUR, n=0..18) */
+
+#define CCM_OSCPLL_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */
+#define CCM_OSCPLL_LPM_MODE_MASK (0x07 << CCM_OSCPLL_LPM_MODE_SHIFT)
+# define CCM_OSCPLL_LPM_MODE_OFF (0) /* Clock is off during all modes */
+# define CCM_OSCPLL_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */
+# define CCM_OSCPLL_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */
+# define CCM_OSCPLL_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */
+# define CCM_OSCPLL_LPM_MODE_ALL (4) /* Clock is on during all modes */
+
+/* CPU domain[n] from OSCPLLn_LPM_0/1 */
+
+#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT (4)
+#define CCM_OSCPLL_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_OSCPLL_LPM_MODE_CPU_DOMAIN_SHIFT)
+#define CCM_OSCPLL_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_OSCPLL_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n))
+#define CCM_OSCPLL_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_OSCPLL_LPM_MODE_MASK)
+
+/* Clock source working status (OSCPLLn_STATUS0, n=0..18) */
+
+#define CCM_OSCPLL_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */
+ /* Bits 1-3: Reserved */
+#define CCM_OSCPLL_STAT0_STATUS_EARLY (1 << 4) /* Bit 4: Clock source is active (STATUS_EARLY) */
+#define CCM_OSCPLL_STAT0_STATUS_LATE (1 << 5) /* Bit 5: Clock source is ready to use (STATUS_LATE) */
+ /* Bits 6-11: Reserved */
+#define CCM_OSCPLL_STAT0_IN_USE (1 << 12) /* Bit 28: Indicates whether the clock source is being used by active clock roots (IN_USE) */
+ /* Bits 16-31: Reserved */
+
+/* Clock source low power status (OSCPLLn_STATUS1, n=0..18) */
+
+#define CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT (0) /* Bits 0-15: Domain active */
+#define CCM_OSCPLL_STAT1_DOM_ACTIVE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ACTIVE_SHIFT)
+#define CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT (16) /* Bits 16-32: Domain enabled */
+#define CCM_OSCPLL_STAT1_DOM_ENABLE_MASK (0xffff << CCM_OSCPLL_STAT1_DOM_ENABLE_SHIFT)
+
+/* Clock source access control (OSCPLLn_AUTHEN, n=0..18) */
+
+#define CCM_OSCPLL_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */
+#define CCM_OSCPLL_AUTH_AUTO_CTRL (1 << 3) /* Bit 2: Auto mode (AUTO_CTRL) */
+#define CCM_OSCPLL_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */
+#define CCM_OSCPLL_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */
+#define CCM_OSCPLL_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_OSCPLL_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_OSCPLL_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_OSCPLL_AUTH_WHITE_LIST_MASK (0xffff << CCM_OSCPLL_AUTH_WHITE_LIST_SHIFT)
+
+/* LPCG direct control (LPCGn_DIRECT, n=0..126) */
+
+#define CCM_LPCG_DIR_ON (1 << 0) /* Bit 0: LPCG on (ON) */
+ /* Bit 1: Reserved */
+#define CCM_LPCG_ACK_TIMEOUT_EN (1 << 2) /* Bit 2: Ack timeout enable */
+ /* Bits 3-31: Reserved */
+
+/* Clock source LPM status (LPCGn_LPM_STATUS0/1, n=0..18) */
+
+#define CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT (0) /* Bits 0-1: Current mode of CPU */
+#define CCM_LPCG_LPM_STAT_CPU_MODE_MASK (0x03 << CCM_LPCG_LPM_STAT_CPU_MODE_SHIFT)
+#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT (2) /* Bit 2: Domain request pending */
+#define CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_MASK (0x01 << CCM_LPCG_LPM_STAT_CPU_TRANS_REQ_SHIFT)
+# define CCM_LPCG_LPM_STAT_ON (0) /* CPU is in RUN mode */
+# define CCM_LPCG_LPM_STAT_WAIT (1) /* CPU is in WAIT mode */
+# define CCM_LPCG_LPM_STAT_STOP (2) /* CPU is in STOP mode */
+# define CCM_LPCG_LPM_STAT_SUSPED (3) /* CPU is in SUSPEND mode */
+
+/* CPU domain[n] from OSCPLLn_LPM_STATUS0/1 */
+
+#define CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT (4)
+#define CCM_LPCG_LPM_STAT_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_STAT_CPU_DOMAIN_SHIFT)
+#define CCM_LPCG_LPM_STAT_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_STAT_CPU_DOMAIN(n)) & CCM_LPCG_LPM_STAT_CPU_MODE_MASK)
+
+/* Clock source LPM mode (LPCGn_LPM_0/1 and _CUR, n=0..18) */
+
+#define CCM_LPCG_LPM_MODE_SHIFT (0) /* Bits 0-2: Current mode of CPU */
+#define CCM_LPCG_LPM_MODE_MASK (0x07 << CCM_LPCG_LPM_MODE_SHIFT)
+# define CCM_LPCG_LPM_MODE_OFF (0) /* Clock is off during all modes */
+# define CCM_LPCG_LPM_MODE_RUN (1) /* Clock is on in run mode, but off in WAIT and STOP modes */
+# define CCM_LPCG_LPM_MODE_RUNWAIT (2) /* Clock is on in run and wait modes, but off in STOP modes */
+# define CCM_LPCG_LPM_MODE_RUNWAITSTOP (3) /* Clock is on during all modes, except SUSPEND mode */
+# define CCM_LPCG_LPM_MODE_ALL (4) /* Clock is on during all modes */
+
+/* CPU domain[n] from LPCGn_LPM_0/1 */
+
+#define CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT (4)
+#define CCM_LPCG_LPM_MODE_CPU_DOMAIN(n) ((n) * CCM_LPCG_LPM_MODE_CPU_DOMAIN_SHIFT)
+#define CCM_LPCG_LPM_MODE_CPU_MODE_SET(n, v) ((v) & CCM_LPCG_LPM_MODE_MASK << CCM_LPCG_LPM_MODE_CPU_DOMAIN(n))
+#define CCM_LPCG_LPM_MODE_CPU_MODE_GET(n, v) (((v) >> CCM_LPCG_LPM_MODE_CPU_DOMAIN(n)) & CCM_LPCG_LPM_MODE_MASK)
+
+/* LPCG working status (LPCGn_STATUS0, n=0..126) */
+
+#define CCM_LPCG_STAT0_ON (1 << 0) /* Bit 0: Clock source is turned on (ON) */
+ /* Bits 1-31 Reserved */
+
+/* LPCG low power status (LPCGn_STATUS1, n=0..126) */
+
+#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT (8) /* Bits 8-11: Domains that own this clock source according to whitelist (ACTIVE_DOMAIN) */
+#define CCM_LPCG_STAT0_ACTIVE_DOMAIN_MASK (0x0f << CCM_LPCG_STAT0_ACTIVE_DOMAIN_SHIFT)
+#define CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT (8) /* Bits 12-15: Enable status from each domain (DOMAIN_ENABLE) */
+#define CCM_LPCG_STAT0_DOMAIN_ENABLE_MASK (0x0f << CCM_LPCG_STAT0_DOMAIN_ENABLE_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* LPCG access control (LPCGn_AUTHEN, n=0..126) */
+
+#define CCM_LPCG_AUTH_CPULPM (1 << 2) /* Bit 2: CPU Low Power Mode (CPULPM) */
+#define CCM_LPCG_AUTH_LOCK_MODE (1 << 7) /* Bit 7: Lock low power and access mode (LOCK_MODE) */
+#define CCM_LPCG_AUTH_TZ_USER (1 << 8) /* Bit 8: Clock source can be changed in user mode (TZ_USER) */
+#define CCM_LPCG_AUTH_TZ_NS (1 << 9) /* Bit 9: Clock source can be changed in non-secure mode (TZ_NS) */
+ /* Bit 10: Reserved */
+#define CCM_LPCG_AUTH_LOCK_TZ (1 << 11) /* Bit 11: Lock TrustZone settings (LOCK_TZ) */
+ /* Bits 12-14: Reserved */
+#define CCM_LPCG_AUTH_LOCK_LIST (1 << 15) /* Bit 15: Lock whitelist settings (LOCK_LIST) */
+#define CCM_LPCG_AUTH_WHITE_LIST_SHIFT (16) /* Bits 16-31: Allow domains to change clock (WHITE_LIST) */
+#define CCM_LPCG_AUTH_WHITE_LIST_MASK (0xffff << CCM_LPCG_AUTH_WHITE_LIST_SHIFT)
+
+/* Auth access bits */
+
+#define CCM_AUTH_TZ_USER(n) ((n) << 8)
+#define CCM_AUTH_TZ_NS(n) ((n) << 9)
+#define CCM_AUTH_LOCK_TZ(n) ((n) << 11)
+
+/* Clock roots */
+
+#define CCM_CR_A55PERIPH 0 /* CLOCK Root Arm A55 Periph. */
+#define CCM_CR_A55MTRBUS 1 /* CLOCK Root Arm A55 MTR BUS. */
+#define CCM_CR_A55 2 /* CLOCK Root Arm A55. */
+#define CCM_CR_M33 3 /* CLOCK Root M33. */
+#define CCM_CR_SENTINEL 4 /* CLOCK Root Sentinel. */
+#define CCM_CR_BUSWAKEUP 5 /* CLOCK Root Bus Wakeup. */
+#define CCM_CR_BUSAON 6 /* CLOCK Root Bus Aon. */
+#define CCM_CR_WAKEUPAXI 7 /* CLOCK Root Wakeup Axi. */
+#define CCM_CR_SWOTRACE 8 /* CLOCK Root Swo Trace. */
+#define CCM_CR_M33SYSTICK 9 /* CLOCK Root M33 Systick. */
+#define CCM_CR_FLEXIO1 10 /* CLOCK Root Flexio1. */
+#define CCM_CR_FLEXIO2 11 /* CLOCK Root Flexio2. */
+#define CCM_CR_LPIT1 12 /* CLOCK Root Lpit1. */
+#define CCM_CR_LPIT2 13 /* CLOCK Root Lpit2. */
+#define CCM_CR_LPTMR1 14 /* CLOCK Root Lptmr1. */
+#define CCM_CR_LPTMR2 15 /* CLOCK Root Lptmr2. */
+#define CCM_CR_TPM1 16 /* CLOCK Root Tpm1. */
+#define CCM_CR_TPM2 17 /* CLOCK Root Tpm2. */
+#define CCM_CR_TPM3 18 /* CLOCK Root Tpm3. */
+#define CCM_CR_TPM4 19 /* CLOCK Root Tpm4. */
+#define CCM_CR_TPM5 20 /* CLOCK Root Tpm5. */
+#define CCM_CR_TPM6 21 /* CLOCK Root Tpm6. */
+#define CCM_CR_FLEXSPI1 22 /* CLOCK Root Flexspi1. */
+#define CCM_CR_CAN1 23 /* CLOCK Root Can1. */
+#define CCM_CR_CAN2 24 /* CLOCK Root Can2. */
+#define CCM_CR_LPUART1 25 /* CLOCK Root Lpuart1. */
+#define CCM_CR_LPUART2 26 /* CLOCK Root Lpuart2. */
+#define CCM_CR_LPUART3 27 /* CLOCK Root Lpuart3. */
+#define CCM_CR_LPUART4 28 /* CLOCK Root Lpuart4. */
+#define CCM_CR_LPUART5 29 /* CLOCK Root Lpuart5. */
+#define CCM_CR_LPUART6 30 /* CLOCK Root Lpuart6. */
+#define CCM_CR_LPUART7 31 /* CLOCK Root Lpuart7. */
+#define CCM_CR_LPUART8 32 /* CLOCK Root Lpuart8. */
+#define CCM_CR_LPI2C1 33 /* CLOCK Root Lpi2c1. */
+#define CCM_CR_LPI2C2 34 /* CLOCK Root Lpi2c2. */
+#define CCM_CR_LPI2C3 35 /* CLOCK Root Lpi2c3. */
+#define CCM_CR_LPI2C4 36 /* CLOCK Root Lpi2c4. */
+#define CCM_CR_LPI2C5 37 /* CLOCK Root Lpi2c5. */
+#define CCM_CR_LPI2C6 38 /* CLOCK Root Lpi2c6. */
+#define CCM_CR_LPI2C7 39 /* CLOCK Root Lpi2c7. */
+#define CCM_CR_LPI2C8 40 /* CLOCK Root Lpi2c8. */
+#define CCM_CR_LPSPI1 41 /* CLOCK Root Lpspi1. */
+#define CCM_CR_LPSPI2 42 /* CLOCK Root Lpspi2. */
+#define CCM_CR_LPSPI3 43 /* CLOCK Root Lpspi3. */
+#define CCM_CR_LPSPI4 44 /* CLOCK Root Lpspi4. */
+#define CCM_CR_LPSPI5 45 /* CLOCK Root Lpspi5. */
+#define CCM_CR_LPSPI6 46 /* CLOCK Root Lpspi6. */
+#define CCM_CR_LPSPI7 47 /* CLOCK Root Lpspi7. */
+#define CCM_CR_LPSPI8 48 /* CLOCK Root Lpspi8. */
+#define CCM_CR_I3C1 49 /* CLOCK Root I3c1. */
+#define CCM_CR_I3C2 50 /* CLOCK Root I3c2. */
+#define CCM_CR_USDHC1 51 /* CLOCK Root Usdhc1. */
+#define CCM_CR_USDHC2 52 /* CLOCK Root Usdhc2. */
+#define CCM_CR_USDHC3 53 /* CLOCK Root Usdhc3. */
+#define CCM_CR_SAI1 54 /* CLOCK Root Sai1. */
+#define CCM_CR_SAI2 55 /* CLOCK Root Sai2. */
+#define CCM_CR_SAI3 56 /* CLOCK Root Sai3. */
+#define CCM_CR_CCMCKO1 57 /* CLOCK Root Ccm Cko1. */
+#define CCM_CR_CCMCKO2 58 /* CLOCK Root Ccm Cko2. */
+#define CCM_CR_CCMCKO3 59 /* CLOCK Root Ccm Cko3. */
+#define CCM_CR_CCMCKO4 60 /* CLOCK Root Ccm Cko4. */
+#define CCM_CR_HSIO 61 /* CLOCK Root Hsio. */
+#define CCM_CR_HSIOUSBTEST60M 62 /* CLOCK Root Hsio Usb Test 60M. */
+#define CCM_CR_HSIOACSCAN80M 63 /* CLOCK Root Hsio Acscan 80M. */
+#define CCM_CR_HSIOACSCAN480M 64 /* CLOCK Root Hsio Acscan 480M. */
+#define CCM_CR_NIC 65 /* CLOCK Root Nic. */
+#define CCM_CR_NICAPB 66 /* CLOCK Root Nic Apb. */
+#define CCM_CR_MLAPB 67 /* CLOCK Root Ml Apb. */
+#define CCM_CR_ML 68 /* CLOCK Root Ml. */
+#define CCM_CR_MEDIAAXI 69 /* CLOCK Root Media Axi. */
+#define CCM_CR_MEDIAAPB 70 /* CLOCK Root Media Apb. */
+#define CCM_CR_MEDIALDB 71 /* CLOCK Root Media Ldb. */
+#define CCM_CR_MEDIADISPPIX 72 /* CLOCK Root Media Disp Pix. */
+#define CCM_CR_CAMPIX 73 /* CLOCK Root Cam Pix. */
+#define CCM_CR_MIPITESTBYTE 74 /* CLOCK Root Mipi Test Byte. */
+#define CCM_CR_MIPIPHYCFG 75 /* CLOCK Root Mipi Phy Cfg. */
+#define CCM_CR_DRAMALT 76 /* CLOCK Root Dram Alt. */
+#define CCM_CR_DRAMAPB 77 /* CLOCK Root Dram Apb. */
+#define CCM_CR_ADC 78 /* CLOCK Root Adc. */
+#define CCM_CR_PDM 79 /* CLOCK Root Pdm. */
+#define CCM_CR_TSTMR1 80 /* CLOCK Root Tstmr1. */
+#define CCM_CR_TSTMR2 81 /* CLOCK Root Tstmr2. */
+#define CCM_CR_MQS1 82 /* CLOCK Root MQS1. */
+#define CCM_CR_MQS2 83 /* CLOCK Root MQS2. */
+#define CCM_CR_AUDIOXCVR 84 /* CLOCK Root Audio XCVR. */
+#define CCM_CR_SPDIF 85 /* CLOCK Root Spdif. */
+#define CCM_CR_ENET 86 /* CLOCK Root Enet. */
+#define CCM_CR_ENETTIMER1 87 /* CLOCK Root Enet Timer1. */
+#define CCM_CR_ENETTIMER2 88 /* CLOCK Root Enet Timer2. */
+#define CCM_CR_ENETREF 89 /* CLOCK Root Enet Ref. */
+#define CCM_CR_ENETREFPHY 90 /* CLOCK Root Enet Ref Phy. */
+#define CCM_CR_I3C1SLOW 91 /* CLOCK Root I3c1Slow. */
+#define CCM_CR_I3C2SLOW 92 /* CLOCK Root I3c2Slow. */
+#define CCM_CR_USBPHYBURUNIN 93 /* CLOCK Root Usb Phy Burunin. */
+#define CCM_CR_PALCAMESCAN 94 /* CLOCK Root Pal Came Scan. */
+
+/* Clock gates */
+
+#define CCM_LPCG_A55 0
+#define CCM_LPCG_CM33 1
+#define CCM_LPCG_ARM_TROUT 2
+#define CCM_LPCG_SENTINEL 3
+#define CCM_LPCG_SIM_WAKEUP 4
+#define CCM_LPCG_SIM_AON 5
+#define CCM_LPCG_SIM_MEGA 6
+#define CCM_LPCG_ANADIG 7
+#define CCM_LPCG_SRC 8
+#define CCM_LPCG_CCM 9
+#define CCM_LPCG_GPC 10
+#define CCM_LPCG_ADC1 11
+#define CCM_LPCG_WDOG1 12
+#define CCM_LPCG_WDOG2 13
+#define CCM_LPCG_WDOG3 14
+#define CCM_LPCG_WDOG4 15
+#define CCM_LPCG_WDOG5 16
+#define CCM_LPCG_SEMA1 17
+#define CCM_LPCG_SEMA2 18
+#define CCM_LPCG_MU_A 19
+#define CCM_LPCG_MU_B 20
+#define CCM_LPCG_EDMA3 21
+#define CCM_LPCG_EDMA4 22
+#define CCM_LPCG_ROMCP_A55 23
+#define CCM_LPCG_ROMCP_M33 24
+#define CCM_LPCG_FLEXSPI1 25
+#define CCM_LPCG_AON_TRDC 26
+#define CCM_LPCG_WKUP_TRDC 27
+#define CCM_LPCG_OCOTP 28
+#define CCM_LPCG_BBSM_HP 29
+#define CCM_LPCG_BBSM 30
+#define CCM_LPCG_CSTRACE 31
+#define CCM_LPCG_CSSWO 32
+#define CCM_LPCG_IOMUXC 33
+#define CCM_LPCG_GPIO1 34
+#define CCM_LPCG_GPIO2 35
+#define CCM_LPCG_GPIO3 36
+#define CCM_LPCG_GPIO4 37
+#define CCM_LPCG_FLEXIO1 38
+#define CCM_LPCG_FLEXIO2 39
+#define CCM_LPCG_LPIT1 40
+#define CCM_LPCG_LPIT2 41
+#define CCM_LPCG_LPTMR1 42
+#define CCM_LPCG_LPTMR2 43
+#define CCM_LPCG_TPM1 44
+#define CCM_LPCG_TPM2 45
+#define CCM_LPCG_TPM3 46
+#define CCM_LPCG_TPM4 47
+#define CCM_LPCG_TPM5 48
+#define CCM_LPCG_TPM6 49
+#define CCM_LPCG_CAN1 50
+#define CCM_LPCG_CAN2 51
+#define CCM_LPCG_LPUART1 52
+#define CCM_LPCG_LPUART2 53
+#define CCM_LPCG_LPUART3 54
+#define CCM_LPCG_LPUART4 55
+#define CCM_LPCG_LPUART5 56
+#define CCM_LPCG_LPUART6 57
+#define CCM_LPCG_LPUART7 58
+#define CCM_LPCG_LPUART8 59
+#define CCM_LPCG_LPI2C1 60
+#define CCM_LPCG_LPI2C2 61
+#define CCM_LPCG_LPI2C3 62
+#define CCM_LPCG_LPI2C4 63
+#define CCM_LPCG_LPI2C5 64
+#define CCM_LPCG_LPI2C6 65
+#define CCM_LPCG_LPI2C7 66
+#define CCM_LPCG_LPI2C8 67
+#define CCM_LPCG_LPSPI1 68
+#define CCM_LPCG_LPSPI2 69
+#define CCM_LPCG_LPSPI3 70
+#define CCM_LPCG_LPSPI4 71
+#define CCM_LPCG_LPSPI5 72
+#define CCM_LPCG_LPSPI6 73
+#define CCM_LPCG_LPSPI7 74
+#define CCM_LPCG_LPSPI8 75
+#define CCM_LPCG_I3C1 76
+#define CCM_LPCG_I3C2 77
+#define CCM_LPCG_USDHC1 78
+#define CCM_LPCG_USDHC2 79
+#define CCM_LPCG_USDHC3 80
+#define CCM_LPCG_SAI1 81
+#define CCM_LPCG_SAI2 82
+#define CCM_LPCG_SAI3 83
+#define CCM_LPCG_SSI_W2AO 84
+#define CCM_LPCG_SSI_AO2W 85
+#define CCM_LPCG_MIPI_CSI 86
+#define CCM_LPCG_MIPI_DSI 87
+#define CCM_LPCG_LVDS 88
+#define CCM_LPCG_LCDIF 89
+#define CCM_LPCG_PXP 90
+#define CCM_LPCG_ISI 91
+#define CCM_LPCG_NIC_MEDIA 92
+#define CCM_LPCG_DDR_DFI 93
+#define CCM_LPCG_DDR_CTL 94
+#define CCM_LPCG_DDR_DFI_CTL 95
+#define CCM_LPCG_DDR_SSI 96
+#define CCM_LPCG_DDR_BYPASS 97
+#define CCM_LPCG_DDR_APB 98
+#define CCM_LPCG_DDR_DRAMPLL 99
+#define CCM_LPCG_DDR_CLK_CTL 100
+#define CCM_LPCG_NIC_CENTRAL 101
+#define CCM_LPCG_GIC600 102
+#define CCM_LPCG_NIC_APB 103
+#define CCM_LPCG_USB_CONTROLLER 104
+#define CCM_LPCG_USB_TEST_60M 105
+#define CCM_LPCG_HSIO_TROUT_24M 106
+#define CCM_LPCG_PDM 107
+#define CCM_LPCG_MQS1 108
+#define CCM_LPCG_MQS2 109
+#define CCM_LPCG_AUD_XCVR 110
+#define CCM_LPCG_NICMIX_MECC 111
+#define CCM_LPCG_SPDIF 112
+#define CCM_LPCG_SSI_ML2NIC 113
+#define CCM_LPCG_SSI_MED2NIC 114
+#define CCM_LPCG_SSI_HSIO2NIC 115
+#define CCM_LPCG_SSI_W2NIC 116
+#define CCM_LPCG_SSI_NIC2W 117
+#define CCM_LPCG_SSI_NIC2DDR 118
+#define CCM_LPCG_HSIO_32K 119
+#define CCM_LPCG_ENET1 120
+#define CCM_LPCG_ENET_QOS 121
+#define CCM_LPCG_SYS_CNT 122
+#define CCM_LPCG_TSTMR1 123
+#define CCM_LPCG_TSTMR2 124
+#define CCM_LPCG_TMC 125
+#define CCM_LPCG_PMRO 126
+
+/* Shared register indices */
+
+#define CCM_SHARED_EXT_CLK 0
+#define CCM_SHARED_A55_CLK 1
+#define CCM_SHARED_DRAM_CLK 2
+#define CCM_SHARED_GPR_COUNT 7
+
+/* Other parameters */
+
+#ifndef CONFIG_IMX9_CLK_OVER_SCMI
+
+#define ROOT_MUX_MAX 4 /* Count of root clock MUX options */
+#define CCM_CR_COUNT 94 /* Count of clock roots */
+#define CCM_LPCG_COUNT 126 /* Count of clock gates */
+#define CCM_OSCPLL_COUNT 18 /* Count of osc plls */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* NOTE: The PLL input (IN) clocks are not available in clock tree */
+
+enum ccm_clock_name_e
+{
+ OSC_24M = 0, /* 24MHZ OSCILLATOR. */
+ ARM_PLL = 1, /* ARM PLL */
+ ARM_PLLOUT = 2, /* ARM PLL OUT */
+ SYS_PLL1_IN = 3, /* SYSTEM PLL1 IN */
+ SYS_PLL1PFD0_IN = 4, /* SYSTEM PLL1 PFD0 IN */
+ SYS_PLL1PFD0 = 5, /* SYSTEM PLL1 PFD0 */
+ SYS_PLL1PFD0DIV2 = 6, /* SYSTEM PLL1 PFD0 DIV2 */
+ SYS_PLL1PFD1_IN = 7, /* SYSTEM PLL1 PFD1 IN */
+ SYS_PLL1PFD1 = 8, /* SYSTEM PLL1 PFD1 */
+ SYS_PLL1PFD1DIV2 = 9, /* SYSTEM PLL1 PFD1 DIV2 */
+ SYS_PLL1PFD2_IN = 10, /* SYSTEM PLL1 PFD2 IN */
+ SYS_PLL1PFD2 = 11, /* SYSTEM PLL1 PFD2 */
+ SYS_PLL1PFD2DIV2 = 12, /* SYSTEM PLL1 PFD2 DIV2 */
+ AUDIO_PLL1 = 13, /* AUDIO PLL1 */
+ AUDIO_PLL1OUT = 14, /* AUDIO PLL1 OUT */
+ DRAM_PLL = 15, /* DRAM PLL */
+ DRAM_PLLOUT = 16, /* DRAM PLL OUT */
+ VIDEO_PLL1 = 17, /* VIDEO PLL1 */
+ VIDEO_PLL1OUT = 18, /* VIDEO PLL1 OUT */
+ EXT = 19, /* EXT */
+};
+
+/* This contains a simple LUT to find the corresponding MUX index per root */
+
+static const int g_ccm_root_mux[][ROOT_MUX_MAX] =
Review Comment:
style follow nuttx/arch/arm64/src/imx9/hardware/imx93/imx93_ccm.h, referenced by multiple .c files. should move to source, but don't have to in this pr ?
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "lupyuen (via GitHub)" <gi...@apache.org>.
lupyuen commented on PR #18501:
URL: https://github.com/apache/nuttx/pull/18501#issuecomment-4107920641
Thanks @jasonbu! Yes you are correct, if our PR involves One Single Defconfig, it's definitely easier to run Docker to test the PR.
The method that I suggested (manual-nuttx-ci) is more suitable for PRs that affect Multiple Architectures, so manual-nuttx-ci is simpler than running Multiple Docker Builds. Or maybe we have devs who are not familiar with Docker, then they can use manual-nuttx-ci too.
We have just implemented a new feature to build One Single Defconfig, it might be helpful too. Thanks :-)
<img width="1906" height="1653" alt="Screenshot 2026-03-23 at 12 33 24 PM" src="https://github.com/user-attachments/assets/682061d0-c9fa-4371-8eb2-fe3891f2b9c8" />
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Re: [PR] arch/arm64/imx95-a55: add GPIO and eMMC (USDHC) support with partition table parsing [nuttx]
Posted by "xiaoxiang781216 (via GitHub)" <gi...@apache.org>.
xiaoxiang781216 merged PR #18501:
URL: https://github.com/apache/nuttx/pull/18501
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