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Posted to commits@nuttx.apache.org by "ken-hutchinson (via GitHub)" <gi...@apache.org> on 2025/11/11 21:55:18 UTC
[I] [HELP] watchdog with risk-v MPFS [nuttx]
ken-hutchinson opened a new issue, #17315:
URL: https://github.com/apache/nuttx/issues/17315
### Description
I'm looking to add watchdog timer support on MPFS (microchip polarfire). Seems to be built in wdt support for a bunch of platforms but not this one. Is that because it's particularly difficult/impossible? Has anyone looked into it before?
thanks
### Verification
- [x] I have verified before submitting the report.
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Re: [I] [HELP] watchdog with risk-v MPFS [nuttx]
Posted by "acassis (via GitHub)" <gi...@apache.org>.
acassis commented on issue #17315:
URL: https://github.com/apache/nuttx/issues/17315#issuecomment-3527695638
@jlaitine since you are one of the main developer of this arch, could you please take a look here?
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Re: [I] [HELP] watchdog with risk-v MPFS [nuttx]
Posted by "ken-hutchinson (via GitHub)" <gi...@apache.org>.
ken-hutchinson closed issue #17315: [HELP] watchdog with risk-v MPFS
URL: https://github.com/apache/nuttx/issues/17315
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Re: [I] [HELP] watchdog with risk-v MPFS [nuttx]
Posted by "jlaitine (via GitHub)" <gi...@apache.org>.
jlaitine commented on issue #17315:
URL: https://github.com/apache/nuttx/issues/17315#issuecomment-3528466529
Yes, I believe it is exactly like that. This is my current understanding of the watchdogs: The MPFS has got 5 watchdogs. The WDT0 can reset the whole MSS, so that is usable even if running NuttX standalone on any hart even without mss or any support implemented on E51. Other four, 1-4 can interrupt the E51 core only.
MPFS TRM is in here:
https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
It is not very detailed, but there you can find link to register maps (it is a downloadable zip containing HTML pages) and to some other resources.
I never wrote WDT support for MPFS, but it is great to get one !
Just add the WDT module base addresses into mpfs_memorymap.h, and another header for the wdog describing the register contents. Some AI can quickly generate the file from the register map htmls, just check it carefully afterwards). Or, just copy the relevant addresses/offsets from HSS:
```
include/mpfs_reg_map.h:
#define WDOG0_LO_BASE_ADDR (0x20001000u)
#define WDOG1_LO_BASE_ADDR (0x20101000u)
#define WDOG2_LO_BASE_ADDR (0x20103000u)
#define WDOG3_LO_BASE_ADDR (0x20105000u)
#define WDOG4_LO_BASE_ADDR (0x20107000u)
....
```
And then just start tinkering :)
-Jukka
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Re: [I] [HELP] watchdog with risk-v MPFS [nuttx]
Posted by "ken-hutchinson (via GitHub)" <gi...@apache.org>.
ken-hutchinson commented on issue #17315:
URL: https://github.com/apache/nuttx/issues/17315#issuecomment-3528042471
I got some info in the HSS forum. Looks like it may be easier than I thought. Just write directly to the memory to configure and tickle the WD. Not sure if that's the 'correct' way to do it.
https://github.com/polarfire-soc/hart-software-services/issues/92
Any other suggestions would be appreciated.
thanks
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Re: [I] [HELP] watchdog with risk-v MPFS [nuttx]
Posted by "ken-hutchinson (via GitHub)" <gi...@apache.org>.
ken-hutchinson commented on issue #17315:
URL: https://github.com/apache/nuttx/issues/17315#issuecomment-3552730167
Thanks for your help.
The only thing I couldn't get working is how to know what caused reset after restarting. MSS_WD_timeout_occured always returns zero. The low level operation of the interrupt handlers is very vague in the docs. I didn't use the NMI and just detected the E54 timeout in code on the E51
There is a bare metal example here
https://github.com/polarfire-soc/polarfire-soc-bare-metal-library/tree/master/examples/mss-watchdog/mpfs-watchdog-interrupt
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