You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/07/25 15:47:11 UTC
[incubator-nuttx] branch master updated (8eae3bb5ff -> 9e7e45df76)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from 8eae3bb5ff stm32f0l0g0/stm32_spi.c: fix receiving data for half duplex mode
new d3b1ee9866 Macronix MX25RXX driver: add support for MX25LXX as well
new 51a845ce54 SocketCAN: add non-blocking write
new dd1096695d Add initial support for NXP S32K3 MCU family
new 7816ba9a7b NXP S32K3XX: add initial support for NXP S32K344EVB board
new 7f3fc23dd6 NXP S32K3XX: add initial support for NXP MR-CANHUBK3 board
new b3590f00b3 NXStyle and preprocessor fixes Co-authored-by: Jari van Ewijk <ja...@nxp.com>
new eae3f77673 Fix wrong comment style
new ec118743ea NX style fixes
new 9e7e45df76 Evaluate n in preprocessor before masking
The 9 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/Kconfig | 12 +
arch/arm/include/s32k3xx/chip.h | 61 +
arch/arm/include/s32k3xx/irq.h | 82 +
arch/arm/include/s32k3xx/s32k3x4_irq.h | 292 ++
arch/arm/src/s32k3xx/Kconfig | 1586 ++++++++++
arch/arm/src/s32k3xx/Make.defs | 82 +
arch/arm/src/s32k3xx/chip.h | 71 +
arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h | 1642 ++++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h | 1407 +++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h | 117 +
arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h | 912 ++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h | 245 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h | 1397 +++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h | 254 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h | 3084 +++++++++++++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h | 320 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_firc.h | 61 +
arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h | 3130 ++++++++++++++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h | 773 +++++
arch/arm/src/s32k3xx/hardware/s32k3xx_fmu.h | 353 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h | 499 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h | 88 +
arch/arm/src/s32k3xx/hardware/s32k3xx_hse.h | 176 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_intm.h | 116 +
arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h | 556 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_lpspi.h | 468 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_lpuart.h | 541 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_cgm.h | 306 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_me.h | 561 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h | 183 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mcm.h | 148 +
arch/arm/src/s32k3xx/hardware/s32k3xx_memorymap.h | 255 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h | 271 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mu.h | 442 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_pflash.h | 350 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_pinmux.h | 60 +
arch/arm/src/s32k3xx/hardware/s32k3xx_pit.h | 186 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_pll.h | 134 +
arch/arm/src/s32k3xx/hardware/s32k3xx_pmc.h | 103 +
arch/arm/src/s32k3xx/hardware/s32k3xx_pramc.h | 55 +
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h | 504 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_rtc.h | 110 +
arch/arm/src/s32k3xx/hardware/s32k3xx_sema42.h | 118 +
arch/arm/src/s32k3xx/hardware/s32k3xx_sirc.h | 64 +
arch/arm/src/s32k3xx/hardware/s32k3xx_siul2.h | 315 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h | 117 +
arch/arm/src/s32k3xx/hardware/s32k3xx_swt.h | 132 +
arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h | 64 +
arch/arm/src/s32k3xx/hardware/s32k3xx_tspc.h | 68 +
.../arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h | 204 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h | 133 +
arch/arm/src/s32k3xx/hardware/s32k3xx_xbic.h | 129 +
arch/arm/src/s32k3xx/hardware/s32k3xx_xrdc.h | 354 +++
arch/arm/src/s32k3xx/s32k3xx_allocateheap.c | 287 ++
arch/arm/src/s32k3xx/s32k3xx_clockconfig.c | 1235 ++++++++
arch/arm/src/s32k3xx/s32k3xx_clockconfig.h | 424 +++
arch/arm/src/s32k3xx/s32k3xx_clocknames.h | 171 ++
arch/arm/src/s32k3xx/s32k3xx_clrpend.c | 82 +
arch/arm/src/s32k3xx/s32k3xx_config.h | 459 +++
arch/arm/src/s32k3xx/s32k3xx_edma.c | 1662 +++++++++++
arch/arm/src/s32k3xx/s32k3xx_edma.h | 465 +++
arch/arm/src/s32k3xx/s32k3xx_emac.c | 3084 +++++++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_emac.h | 110 +
arch/arm/src/s32k3xx/s32k3xx_flashboot.c | 66 +
arch/arm/src/s32k3xx/s32k3xx_flexcan.c | 2321 +++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_flexcan.h | 83 +
arch/arm/src/s32k3xx/s32k3xx_fs26.c | 511 ++++
arch/arm/src/s32k3xx/s32k3xx_fs26.h | 83 +
arch/arm/src/s32k3xx/s32k3xx_idle.c | 82 +
arch/arm/src/s32k3xx/s32k3xx_irq.c | 601 ++++
arch/arm/src/s32k3xx/s32k3xx_irq.h | 47 +
arch/arm/src/s32k3xx/s32k3xx_lowputc.c | 718 +++++
arch/arm/src/s32k3xx/s32k3xx_lowputc.h | 106 +
arch/arm/src/s32k3xx/s32k3xx_lpi2c.c | 1821 ++++++++++++
arch/arm/src/s32k3xx/s32k3xx_lpi2c.h | 71 +
arch/arm/src/s32k3xx/s32k3xx_lpspi.c | 2425 +++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_lpspi.h | 188 ++
arch/arm/src/s32k3xx/s32k3xx_periphclocks.c | 158 +
arch/arm/src/s32k3xx/s32k3xx_periphclocks.h | 239 ++
arch/arm/src/s32k3xx/s32k3xx_pin.c | 186 ++
arch/arm/src/s32k3xx/s32k3xx_pin.h | 596 ++++
arch/arm/src/s32k3xx/s32k3xx_pindma.c | 158 +
arch/arm/src/s32k3xx/s32k3xx_pingpio.c | 100 +
arch/arm/src/s32k3xx/s32k3xx_pinirq.c | 503 ++++
arch/arm/src/s32k3xx/s32k3xx_qspi.c | 1869 ++++++++++++
arch/arm/src/s32k3xx/s32k3xx_qspi.h | 131 +
arch/arm/src/s32k3xx/s32k3xx_serial.c | 2920 ++++++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_serial.h | 86 +
arch/arm/src/s32k3xx/s32k3xx_start.c | 307 ++
arch/arm/src/s32k3xx/s32k3xx_start.h | 70 +
arch/arm/src/s32k3xx/s32k3xx_swt.h | 104 +
arch/arm/src/s32k3xx/s32k3xx_timerisr.c | 133 +
arch/arm/src/s32k3xx/startup.S | 57 +
boards/Kconfig | 51 +-
boards/arm/s32k3xx/mr-canhubk3/Kconfig | 24 +
boards/arm/s32k3xx/mr-canhubk3/README.txt | 116 +
.../arm/s32k3xx/mr-canhubk3/configs/net/defconfig | 113 +
.../arm/s32k3xx/mr-canhubk3/configs/nsh/defconfig | 52 +
boards/arm/s32k3xx/mr-canhubk3/include/board.h | 324 ++
boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs | 49 +
boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld | 159 +
boards/arm/s32k3xx/mr-canhubk3/src/Makefile | 62 +
boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h | 147 +
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c | 74 +
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c | 150 +
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c | 82 +
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c | 320 ++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c | 154 +
.../s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c | 162 +
.../s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c | 105 +
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c | 105 +
.../s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c | 258 ++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c | 464 +++
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c | 376 +++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c | 334 +++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c | 104 +
boards/arm/s32k3xx/s32k344evb/Kconfig | 8 +
boards/arm/s32k3xx/s32k344evb/README.txt | 134 +
.../arm/s32k3xx/s32k344evb/configs/nsh/defconfig | 44 +
boards/arm/s32k3xx/s32k344evb/include/board.h | 168 ++
boards/arm/s32k3xx/s32k344evb/scripts/Make.defs | 49 +
boards/arm/s32k3xx/s32k344evb/scripts/flash.ld | 156 +
boards/arm/s32k3xx/s32k344evb/src/Makefile | 50 +
boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h | 133 +
.../arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c | 74 +
.../arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c | 166 ++
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c | 77 +
.../arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c | 122 +
.../arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c | 154 +
.../s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c | 157 +
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c | 104 +
.../s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c | 250 ++
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c | 366 +++
.../arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c | 125 +
drivers/mtd/Kconfig | 8 +
drivers/mtd/mx25rxx.c | 17 +-
drivers/serial/Kconfig | 35 +
drivers/serial/Kconfig-lpuart | 707 +++++
net/can/can.h | 26 +
net/can/can_input.c | 52 +-
net/can/can_sendmsg.c | 48 +-
net/can/can_sockif.c | 10 +-
142 files changed, 55384 insertions(+), 51 deletions(-)
create mode 100644 arch/arm/include/s32k3xx/chip.h
create mode 100644 arch/arm/include/s32k3xx/irq.h
create mode 100644 arch/arm/include/s32k3xx/s32k3x4_irq.h
create mode 100644 arch/arm/src/s32k3xx/Kconfig
create mode 100644 arch/arm/src/s32k3xx/Make.defs
create mode 100644 arch/arm/src/s32k3xx/chip.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_firc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_fmu.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_hse.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_intm.h
create mode 100755 arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_lpspi.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_lpuart.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_mc_cgm.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_mc_me.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_mcm.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_memorymap.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_mu.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_pflash.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_pinmux.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_pit.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_pll.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_pmc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_pramc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_rtc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_sema42.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_sirc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_siul2.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_swt.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_tspc.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h
create mode 100644 arch/arm/src/s32k3xx/hardware/s32k3xx_xbic.h
create mode 100755 arch/arm/src/s32k3xx/hardware/s32k3xx_xrdc.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_allocateheap.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_clockconfig.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_clockconfig.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_clocknames.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_clrpend.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_config.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_edma.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_edma.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_emac.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_emac.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_flashboot.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_flexcan.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_flexcan.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_fs26.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_fs26.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_idle.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_irq.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_irq.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_lowputc.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_lowputc.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_lpi2c.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_lpi2c.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_lpspi.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_lpspi.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_periphclocks.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_periphclocks.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_pin.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_pin.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_pindma.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_pingpio.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_pinirq.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_qspi.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_qspi.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_serial.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_serial.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_start.c
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_start.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_swt.h
create mode 100644 arch/arm/src/s32k3xx/s32k3xx_timerisr.c
create mode 100644 arch/arm/src/s32k3xx/startup.S
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/Kconfig
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/README.txt
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/configs/net/defconfig
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/configs/nsh/defconfig
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/include/board.h
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/Makefile
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c
create mode 100644 boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/Kconfig
create mode 100644 boards/arm/s32k3xx/s32k344evb/README.txt
create mode 100644 boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig
create mode 100644 boards/arm/s32k3xx/s32k344evb/include/board.h
create mode 100644 boards/arm/s32k3xx/s32k344evb/scripts/Make.defs
create mode 100644 boards/arm/s32k3xx/s32k344evb/scripts/flash.ld
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/Makefile
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c
create mode 100644 boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
[incubator-nuttx] 07/09: Fix wrong comment style
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit eae3f776736f784a39d8db02ba3a8edead93cfa9
Author: Peter van der Perk <pe...@nxp.com>
AuthorDate: Fri Jul 22 17:28:20 2022 +0200
Fix wrong comment style
---
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h | 262 ++++++++++++-------------
arch/arm/src/s32k3xx/s32k3xx_qspi.c | 28 +--
2 files changed, 145 insertions(+), 145 deletions(-)
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
index 5c4a52ae4f..8481579a1e 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
@@ -107,139 +107,139 @@
/** edma_mux0 **/
-#define DMA_REQ_DISABLED0 (0) ///< Channel disabled (default)
-#define DMA_REQ_SIUL_0 (1) ///< SIUL DMA request 0
-#define DMA_REQ_SIUL_1 (2) ///< SIUL DMA request 1
-#define DMA_REQ_SIUL_2 (3) ///< SIUL DMA request 2
-#define DMA_REQ_SIUL_3 (4) ///< SIUL DMA request 3
-#define DMA_REQ_SIUL_4 (5) ///< SIUL DMA request 4
-#define DMA_REQ_SIUL_5 (6) ///< SIUL DMA request 5
-#define DMA_REQ_SIUL_6 (7) ///< SIUL DMA request 6
-#define DMA_REQ_SIUL_7 (8) ///< SIUL DMA request 7
-#define DMA_REQ_BCTU_FIFO1 (10) ///< BCTU DMA FIFO1 request
-#define DMA_REQ_BCTU_0 (10) ///< BCTU DMA request 0
-#define DMA_REQ_BCTU_1 (11) ///< BCTU DMA request 1
-#define DMA_REQ_EMIOS0_0 (12) ///< eMIOS0 DMA request ch0
-#define DMA_REQ_EMIOS0_1 (13) ///< eMIOS0 DMA request ch1
-#define DMA_REQ_EMIOS0_9 (14) ///< eMIOS0 DMA request ch9
-#define DMA_REQ_EMIOS0_10 (15) ///< eMIOS0 DMA request ch10
-#define DMA_REQ_EMIOS1_0 (16) ///< eMIOS1 DMA request ch0
-#define DMA_REQ_EMIOS1_1 (17) ///< eMIOS1 DMA request ch1
-#define DMA_REQ_EMIOS1_9 (18) ///< eMIOS1 DMA request ch9
-#define DMA_REQ_EMIOS1_10 (19) ///< eMIOS1 DMA request ch10
-#define DMA_REQ_EMIOS2_0 (20) ///< eMIOS2 DMA request ch0
-#define DMA_REQ_EMIOS2_1 (21) ///< eMIOS2 DMA request ch1
-#define DMA_REQ_EMIOS2_9 (22) ///< eMIOS2 DMA request ch9
-#define DMA_REQ_EMIOS2_10 (23) ///< eMIOS2 DMA request ch10
-#define DMA_REQ_LCU0_0 (24) ///< LCU0 DMA request 0
-#define DMA_REQ_LCU1_0 (25) ///< LCU1 DMA request 0
-#define DMA_REQ_RESERVED1 (26) ///< RESERVED
-#define DMA_REQ_RESERVED2 (27) ///< RESERVED
-#define DMA_REQ_RESERVED3 (28) ///< RESERVED
-#define DMA_REQ_FLEXCAN0 (29) ///< FLEXCAN0 DMA request
-#define DMA_REQ_FLEXCAN1 (30) ///< FLEXCAN1 DMA request
-#define DMA_REQ_FLEXCAN2 (31) ///< FLEXCAN2 DMA request
-#define DMA_REQ_FLEXCAN3 (32) ///< FLEXCAN3 DMA request
-#define DMA_REQ_FLEXIO_0 (33) ///< FLEXIO DMA shifter0 | timer0 request
-#define DMA_REQ_FLEXIO_1 (34) ///< FLEXIO DMA shifter1 | timer1 request
-#define DMA_REQ_FLEXIO_2 (35) ///< FLEXIO DMA shifter2 | timer2 request
-#define DMA_REQ_FLEXIO_3 (36) ///< FLEXIO DMA shifter3 | timer3 request
-#define DMA_REQ_LPUART08_TX (37) ///< LPUART0 | LPUART8 DMA transmit request
-#define DMA_REQ_LPUART08_RX (38) ///< LPUART0 | LPUART8 DMA receive request
-#define DMA_REQ_LPUART19_TX (39) ///< LPUART1 | LPUART9 DMA transmit request
-#define DMA_REQ_LPUART19_RX (40) ///< LPUART1 | LPUART9 DMA receive request
-#define DMA_REQ_LPI2C0_RX (41) ///< LPI2C0 DMA receive | receive slave request
-#define DMA_REQ_LPI2C0_TX (42) ///< LPI2C0 DMA transmit | transmit slave request
-#define DMA_REQ_LPSPI0_TX (43) ///< LPSPI0 DMA transmit request
-#define DMA_REQ_LPSPI0_RX (44) ///< LPSPI0 DMA receive request
-#define DMA_REQ_LPSPI1_TX (45) ///< LPSPI1 DMA transmit request
-#define DMA_REQ_LPSPI1_RX (46) ///< LPSPI1 DMA receive request
-#define DMA_REQ_LPSPI2_TX (47) ///< LPSPI2 DMA transmit request
-#define DMA_REQ_LPSPI2_RX (48) ///< LPSPI2 DMA receive request
-#define DMA_REQ_LPSPI3_TX (49) ///< LPSPI3 DMA transmit request
-#define DMA_REQ_LPSPI3_RX (50) ///< LPSPI3 DMA receive request
-#define DMA_REQ_I3C0_RX (51) ///< I3C0 DMA receive request
-#define DMA_REQ_I3C0_TX (52) ///< I3C0 DMA transmit request
-#define DMA_REQ_QSPI_RX (53) ///< QSPI DMA receive buffer drain request
-#define DMA_REQ_QSPI_TX (54) ///< QSPI DMA transmit buffer fill request
-#define DMA_REQ_SAI0_RX (55) ///< SAI0 DMA receive request
-#define DMA_REQ_SAI0_TX (56) ///< SAI0 DMA transmit request
-#define DMA_REQ_RESERVED4 (57) ///< RESERVED
-#define DMA_REQ_ADC0 (58) ///< ADC0 DMA request
-#define DMA_REQ_ADC1 (59) ///< ADC1 DMA request
-#define DMA_REQ_ADC2 (60) ///< ADC2 DMA request
-#define DMA_REQ_LPCMP0 (61) ///< LPCMP0 DMA request
-#define DMA_REQ_ENABLED0 (62) ///< Always enabled
-#define DMA_REQ_ENABLED1 (63) ///< Always enabled */
+#define DMA_REQ_DISABLED0 (0) /* Channel disabled (default) */
+#define DMA_REQ_SIUL_0 (1) /* SIUL DMA request 0 */
+#define DMA_REQ_SIUL_1 (2) /* SIUL DMA request 1 */
+#define DMA_REQ_SIUL_2 (3) /* SIUL DMA request 2 */
+#define DMA_REQ_SIUL_3 (4) /* SIUL DMA request 3 */
+#define DMA_REQ_SIUL_4 (5) /* SIUL DMA request 4 */
+#define DMA_REQ_SIUL_5 (6) /* SIUL DMA request 5 */
+#define DMA_REQ_SIUL_6 (7) /* SIUL DMA request 6 */
+#define DMA_REQ_SIUL_7 (8) /* SIUL DMA request 7 */
+#define DMA_REQ_BCTU_FIFO1 (10) /* BCTU DMA FIFO1 request */
+#define DMA_REQ_BCTU_0 (10) /* BCTU DMA request 0 */
+#define DMA_REQ_BCTU_1 (11) /* BCTU DMA request 1 */
+#define DMA_REQ_EMIOS0_0 (12) /* eMIOS0 DMA request ch0 */
+#define DMA_REQ_EMIOS0_1 (13) /* eMIOS0 DMA request ch1 */
+#define DMA_REQ_EMIOS0_9 (14) /* eMIOS0 DMA request ch9 */
+#define DMA_REQ_EMIOS0_10 (15) /* eMIOS0 DMA request ch10 */
+#define DMA_REQ_EMIOS1_0 (16) /* eMIOS1 DMA request ch0 */
+#define DMA_REQ_EMIOS1_1 (17) /* eMIOS1 DMA request ch1 */
+#define DMA_REQ_EMIOS1_9 (18) /* eMIOS1 DMA request ch9 */
+#define DMA_REQ_EMIOS1_10 (19) /* eMIOS1 DMA request ch10 */
+#define DMA_REQ_EMIOS2_0 (20) /* eMIOS2 DMA request ch0 */
+#define DMA_REQ_EMIOS2_1 (21) /* eMIOS2 DMA request ch1 */
+#define DMA_REQ_EMIOS2_9 (22) /* eMIOS2 DMA request ch9 */
+#define DMA_REQ_EMIOS2_10 (23) /* eMIOS2 DMA request ch10 */
+#define DMA_REQ_LCU0_0 (24) /* LCU0 DMA request 0 */
+#define DMA_REQ_LCU1_0 (25) /* LCU1 DMA request 0 */
+#define DMA_REQ_RESERVED1 (26) /* RESERVED */
+#define DMA_REQ_RESERVED2 (27) /* RESERVED */
+#define DMA_REQ_RESERVED3 (28) /* RESERVED */
+#define DMA_REQ_FLEXCAN0 (29) /* FLEXCAN0 DMA request */
+#define DMA_REQ_FLEXCAN1 (30) /* FLEXCAN1 DMA request */
+#define DMA_REQ_FLEXCAN2 (31) /* FLEXCAN2 DMA request */
+#define DMA_REQ_FLEXCAN3 (32) /* FLEXCAN3 DMA request */
+#define DMA_REQ_FLEXIO_0 (33) /* FLEXIO DMA shifter0 | timer0 request */
+#define DMA_REQ_FLEXIO_1 (34) /* FLEXIO DMA shifter1 | timer1 request */
+#define DMA_REQ_FLEXIO_2 (35) /* FLEXIO DMA shifter2 | timer2 request */
+#define DMA_REQ_FLEXIO_3 (36) /* FLEXIO DMA shifter3 | timer3 request */
+#define DMA_REQ_LPUART08_TX (37) /* LPUART0 | LPUART8 DMA transmit request */
+#define DMA_REQ_LPUART08_RX (38) /* LPUART0 | LPUART8 DMA receive request */
+#define DMA_REQ_LPUART19_TX (39) /* LPUART1 | LPUART9 DMA transmit request */
+#define DMA_REQ_LPUART19_RX (40) /* LPUART1 | LPUART9 DMA receive request */
+#define DMA_REQ_LPI2C0_RX (41) /* LPI2C0 DMA receive | receive slave request */
+#define DMA_REQ_LPI2C0_TX (42) /* LPI2C0 DMA transmit | transmit slave request */
+#define DMA_REQ_LPSPI0_TX (43) /* LPSPI0 DMA transmit request */
+#define DMA_REQ_LPSPI0_RX (44) /* LPSPI0 DMA receive request */
+#define DMA_REQ_LPSPI1_TX (45) /* LPSPI1 DMA transmit request */
+#define DMA_REQ_LPSPI1_RX (46) /* LPSPI1 DMA receive request */
+#define DMA_REQ_LPSPI2_TX (47) /* LPSPI2 DMA transmit request */
+#define DMA_REQ_LPSPI2_RX (48) /* LPSPI2 DMA receive request */
+#define DMA_REQ_LPSPI3_TX (49) /* LPSPI3 DMA transmit request */
+#define DMA_REQ_LPSPI3_RX (50) /* LPSPI3 DMA receive request */
+#define DMA_REQ_I3C0_RX (51) /* I3C0 DMA receive request */
+#define DMA_REQ_I3C0_TX (52) /* I3C0 DMA transmit request */
+#define DMA_REQ_QSPI_RX (53) /* QSPI DMA receive buffer drain request */
+#define DMA_REQ_QSPI_TX (54) /* QSPI DMA transmit buffer fill request */
+#define DMA_REQ_SAI0_RX (55) /* SAI0 DMA receive request */
+#define DMA_REQ_SAI0_TX (56) /* SAI0 DMA transmit request */
+#define DMA_REQ_RESERVED4 (57) /* RESERVED */
+#define DMA_REQ_ADC0 (58) /* ADC0 DMA request */
+#define DMA_REQ_ADC1 (59) /* ADC1 DMA request */
+#define DMA_REQ_ADC2 (60) /* ADC2 DMA request */
+#define DMA_REQ_LPCMP0 (61) /* LPCMP0 DMA request */
+#define DMA_REQ_ENABLED0 (62) /* Always enabled */
+#define DMA_REQ_ENABLED1 (63) /* Always enabled */
/** edma_mux1 **/
-#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) ///< Channel disabled (default)
-#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) ///< SIUL DMA request 8
-#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) ///< SIUL DMA request 9
-#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) ///< SIUL DMA request 10
-#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) ///< SIUL DMA request 11
-#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) ///< SIUL DMA request 12
-#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) ///< SIUL DMA request 13
-#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) ///< SIUL DMA request 14
-#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) ///< SIUL DMA request 15
-#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) ///< BCTU DMA FIFO2 request
-#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) ///< BCTU DMA request 2
-#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) ///< eMIOS0 DMA request ch16
-#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) ///< eMIOS0 DMA request ch17
-#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) ///< eMIOS0 DMA request ch18
-#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) ///< eMIOS0 DMA request ch19
-#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) ///< eMIOS1 DMA request ch16
-#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) ///< eMIOS1 DMA request ch17
-#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) ///< eMIOS1 DMA request ch18
-#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) ///< eMIOS1 DMA request ch19
-#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) ///< eMIOS2 DMA request ch16
-#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) ///< eMIOS2 DMA request ch17
-#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) ///< eMIOS2 DMA request ch18
-#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) ///< eMIOS2 DMA request ch19
-#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) ///< LCU0 DMA request 1
-#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) ///< LCU1 DMA request 2
-#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) ///< LCU1 DMA request 1
-#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) ///< LCU1 DMA request 2
-#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[0] DMA request
-#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[1] DMA request
-#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[2] DMA request
-#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[3] DMA request
-#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) ///< RESERVED
-#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) ///< RESERVED
-#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) ///< FLEXCAN4 DMA request
-#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) ///< FLEXCAN5 DMA request
-#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) ///< RESERVED
-#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) ///< RESERVED
-#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) ///< FLEXIO DMA shifter4 | timer4 request
-#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) ///< FLEXIO DMA shifter5 | timer5 request
-#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) ///< FLEXIO DMA shifter6 | timer6 request
-#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) ///< FLEXIO DMA shifter7 | timer7 request
-#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) ///< LPUART2 | LPUART10 DMA transmit request
-#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) ///< LPUART2 | LPUART10 DMA receive request
-#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) ///< LPUART3 | LPUART11 DMA transmit request
-#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) ///< LPUART3 | LPUART11 DMA receive request
-#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) ///< LPUART4 | LPUART12 DMA transmit request
-#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) ///< LPUART4 | LPUART12 DMA receive request
-#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) ///< LPUART5 | LPUART13 DMA transmit request
-#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) ///< LPUART5 | LPUART13 DMA receive request
-#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) ///< LPUART6 | LPUART14 DMA transmit request
-#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) ///< LPUART6 | LPUART14 DMA receive request
-#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) ///< LPUART7 | LPUART15 DMA transmit request
-#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) ///< LPUART7 | LPUART15 DMA receive request
-#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) ///< LPI2C1 DMA receive | receive slave request
-#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) ///< LPI2C1 DMA transmit | transmit slave request
-#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) ///< LPSPI4 DMA transmit request
-#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) ///< LPSPI4 DMA receive request
-#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) ///< LPSPI5 DMA transmit request
-#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) ///< LPSPI5 DMA receive request
-#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) ///< SAI1 DMA RX request
-#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) ///< SAI1 DMA TX request
-#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) ///< RESERVED
-#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) ///< RESERVED
-#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) ///< LPCMP1 DMA request
-#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) ///< LPCMP2 DMA request
-#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) ///< Always enabled
-#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) ///< Always enabled
+#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) /* Channel disabled (default) */
+#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) /* SIUL DMA request 8 */
+#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) /* SIUL DMA request 9 */
+#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) /* SIUL DMA request 10 */
+#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) /* SIUL DMA request 11 */
+#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) /* SIUL DMA request 12 */
+#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) /* SIUL DMA request 13 */
+#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) /* SIUL DMA request 14 */
+#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) /* SIUL DMA request 15 */
+#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) /* BCTU DMA FIFO2 request */
+#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) /* BCTU DMA request 2 */
+#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) /* eMIOS0 DMA request ch16 */
+#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) /* eMIOS0 DMA request ch17 */
+#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) /* eMIOS0 DMA request ch18 */
+#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) /* eMIOS0 DMA request ch19 */
+#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) /* eMIOS1 DMA request ch16 */
+#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) /* eMIOS1 DMA request ch17 */
+#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) /* eMIOS1 DMA request ch18 */
+#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) /* eMIOS1 DMA request ch19 */
+#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) /* eMIOS2 DMA request ch16 */
+#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) /* eMIOS2 DMA request ch17 */
+#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) /* eMIOS2 DMA request ch18 */
+#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) /* eMIOS2 DMA request ch19 */
+#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) /* LCU0 DMA request 1 */
+#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) /* LCU1 DMA request 2 */
+#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) /* LCU1 DMA request 1 */
+#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) /* LCU1 DMA request 2 */
+#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[0] DMA request */
+#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[1] DMA request */
+#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[2] DMA request */
+#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) /* ENET IEEE 1588 PTP timer ch[3] DMA request */
+#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) /* RESERVED */
+#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) /* RESERVED */
+#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) /* FLEXCAN4 DMA request */
+#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) /* FLEXCAN5 DMA request */
+#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) /* RESERVED */
+#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) /* RESERVED */
+#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) /* FLEXIO DMA shifter4 | timer4 request */
+#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) /* FLEXIO DMA shifter5 | timer5 request */
+#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) /* FLEXIO DMA shifter6 | timer6 request */
+#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) /* FLEXIO DMA shifter7 | timer7 request */
+#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) /* LPUART2 | LPUART10 DMA transmit request */
+#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) /* LPUART2 | LPUART10 DMA receive request */
+#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) /* LPUART3 | LPUART11 DMA transmit request */
+#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) /* LPUART3 | LPUART11 DMA receive request */
+#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) /* LPUART4 | LPUART12 DMA transmit request */
+#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) /* LPUART4 | LPUART12 DMA receive request */
+#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) /* LPUART5 | LPUART13 DMA transmit request */
+#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) /* LPUART5 | LPUART13 DMA receive request */
+#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) /* LPUART6 | LPUART14 DMA transmit request */
+#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) /* LPUART6 | LPUART14 DMA receive request */
+#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) /* LPUART7 | LPUART15 DMA transmit request */
+#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) /* LPUART7 | LPUART15 DMA receive request */
+#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) /* LPI2C1 DMA receive | receive slave request */
+#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) /* LPI2C1 DMA transmit | transmit slave request */
+#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) /* LPSPI4 DMA transmit request */
+#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) /* LPSPI4 DMA receive request */
+#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) /* LPSPI5 DMA transmit request */
+#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) /* LPSPI5 DMA receive request */
+#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) /* SAI1 DMA RX request */
+#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) /* SAI1 DMA TX request */
+#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) /* RESERVED */
+#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) /* RESERVED */
+#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) /* LPCMP1 DMA request */
+#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) /* LPCMP2 DMA request */
+#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) /* Always enabled */
+#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) /* Always enabled */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */
diff --git a/arch/arm/src/s32k3xx/s32k3xx_qspi.c b/arch/arm/src/s32k3xx/s32k3xx_qspi.c
index 0ff75941fa..0456cd9781 100644
--- a/arch/arm/src/s32k3xx/s32k3xx_qspi.c
+++ b/arch/arm/src/s32k3xx/s32k3xx_qspi.c
@@ -83,20 +83,20 @@
#define QSPI_LUT_SHARE_TYPE1 2U /* Shared Lut */
#define QSPI_LUT_SHARE_TYPE2 3U /* Shared Lut */
-#define QSPI_LUT_CMD_STOP 0U ///< End of sequence
-#define QSPI_LUT_CMD_CMD 1U ///< Command
-#define QSPI_LUT_CMD_ADDR 2U ///< Address
-#define QSPI_LUT_CMD_DUMMY 3U ///< Dummy cycles
-#define QSPI_LUT_CMD_MODE 4U ///< 8-bit mode
-#define QSPI_LUT_CMD_MODE2 5U ///< 2-bit mode
-#define QSPI_LUT_CMD_MODE4 6U ///< 4-bit mode
-#define QSPI_LUT_CMD_READ 7U ///< Read data
-#define QSPI_LUT_CMD_WRITE 8U ///< Write data
-#define QSPI_LUT_CMD_JMP_ON_CS 9U ///< Jump on chip select deassert
-
-#define QSPI_TRANSFER_TYPE_SYNC 0U ///< Synchronous transfer using polling
-#define QSPI_TRANSFER_TYPE_ASYNC_INT 1U ///< Interrupt-based asynchronous transfer
-#define QSPI_TRANSFER_TYPE_ASYNC_DMA 2U ///< DMA-based asynchronous transfer
+#define QSPI_LUT_CMD_STOP 0U /* End of sequence */
+#define QSPI_LUT_CMD_CMD 1U /* Command */
+#define QSPI_LUT_CMD_ADDR 2U /* Address */
+#define QSPI_LUT_CMD_DUMMY 3U /* Dummy cycles */
+#define QSPI_LUT_CMD_MODE 4U /* 8-bit mode */
+#define QSPI_LUT_CMD_MODE2 5U /* 2-bit mode */
+#define QSPI_LUT_CMD_MODE4 6U /* 4-bit mode */
+#define QSPI_LUT_CMD_READ 7U /* Read data */
+#define QSPI_LUT_CMD_WRITE 8U /* Write data */
+#define QSPI_LUT_CMD_JMP_ON_CS 9U /* Jump on chip select deassert */
+
+#define QSPI_TRANSFER_TYPE_SYNC 0U /* Synchronous transfer using polling */
+#define QSPI_TRANSFER_TYPE_ASYNC_INT 1U /* Interrupt-based asynchronous transfer */
+#define QSPI_TRANSFER_TYPE_ASYNC_DMA 2U /* DMA-based asynchronous transfer */
#define QSPI_RX_BUF_SIZE 128U
[incubator-nuttx] 02/09: SocketCAN: add non-blocking write
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 51a845ce54e38ca6ecc13c2fd7029802cb07076f
Author: Jari van Ewijk <ja...@nxp.com>
AuthorDate: Fri Jul 22 10:23:20 2022 +0200
SocketCAN: add non-blocking write
Co-authored-by: Peter van der Perk <pe...@nxp.com>
---
net/can/can.h | 26 ++++++++++++++++++++++++++
net/can/can_input.c | 52 ++++++++++++++++++++++++---------------------------
net/can/can_sendmsg.c | 48 +++++++++++++++++++++++++++++++++++++++++++++--
net/can/can_sockif.c | 10 +++-------
4 files changed, 99 insertions(+), 37 deletions(-)
diff --git a/net/can/can.h b/net/can/can.h
index 48f9e1087d..d317fea6f7 100644
--- a/net/can/can.h
+++ b/net/can/can.h
@@ -267,6 +267,32 @@ ssize_t can_recvmsg(FAR struct socket *psock, FAR struct msghdr *msg,
void can_poll(FAR struct net_driver_s *dev, FAR struct can_conn_s *conn);
+/****************************************************************************
+ * Name: psock_can_cansend
+ *
+ * Description:
+ * psock_can_cansend() returns a value indicating if a write to the socket
+ * would block. It is still possible that the write may block if another
+ * write occurs first.
+ *
+ * Input Parameters:
+ * psock An instance of the internal socket structure.
+ *
+ * Returned Value:
+ * OK
+ * At least one byte of data could be successfully written.
+ * -EWOULDBLOCK
+ * There is no room in the output buffer.
+ * -EBADF
+ * An invalid descriptor was specified.
+ *
+ * Assumptions:
+ * None
+ *
+ ****************************************************************************/
+
+int psock_can_cansend(FAR struct socket *psock);
+
/****************************************************************************
* Name: can_sendmsg
*
diff --git a/net/can/can_input.c b/net/can/can_input.c
index 024bb9aad5..7a073d566d 100644
--- a/net/can/can_input.c
+++ b/net/can/can_input.c
@@ -155,48 +155,44 @@ int can_input(struct net_driver_s *dev)
{
FAR struct can_conn_s *conn = NULL;
int ret = OK;
+ uint16_t buflen = dev->d_len;
do
{
- /* FIXME Support for multiple sockets??? */
-
conn = can_nextconn(conn);
- }
- while (conn && conn->dev != 0 && dev != conn->dev);
-
- if (conn)
- {
- uint16_t flags;
- /* Setup for the application callback */
+ if (conn && (conn->dev == 0x0 || dev == conn->dev))
+ {
+ uint16_t flags;
- dev->d_appdata = dev->d_buf;
- dev->d_sndlen = 0;
+ /* Setup for the application callback */
- /* Perform the application callback */
+ dev->d_appdata = dev->d_buf;
+ dev->d_sndlen = 0;
+ dev->d_len = buflen;
- flags = can_callback(dev, conn, CAN_NEWDATA);
+ /* Perform the application callback */
- /* If the operation was successful, the CAN_NEWDATA flag is removed
- * and thus the packet can be deleted (OK will be returned).
- */
+ flags = can_callback(dev, conn, CAN_NEWDATA);
- if ((flags & CAN_NEWDATA) != 0)
- {
- /* No.. the packet was not processed now. Return -EAGAIN so
- * that the driver may retry again later. We still need to
- * set d_len to zero so that the driver is aware that there
- * is nothing to be sent.
+ /* If the operation was successful, the CAN_NEWDATA flag is removed
+ * and thus the packet can be deleted (OK will be returned).
*/
- nwarn("WARNING: Packet not processed\n");
- ret = -EAGAIN;
+ if ((flags & CAN_NEWDATA) != 0)
+ {
+ /* No.. the packet was not processed now. Return -EAGAIN so
+ * that the driver may retry again later. We still need to
+ * set d_len to zero so that the driver is aware that there
+ * is nothing to be sent.
+ */
+
+ nwarn("WARNING: Packet not processed\n");
+ ret = -EAGAIN;
+ }
}
}
- else
- {
- ninfo("No CAN listener\n");
- }
+ while (conn);
return ret;
}
diff --git a/net/can/can_sendmsg.c b/net/can/can_sendmsg.c
index a7912d99d1..3ccea61826 100644
--- a/net/can/can_sendmsg.c
+++ b/net/can/can_sendmsg.c
@@ -259,10 +259,17 @@ ssize_t can_sendmsg(FAR struct socket *psock, FAR struct msghdr *msg,
netdev_txnotify_dev(dev);
/* Wait for the send to complete or an error to occur.
- * net_lockedwait will also terminate if a signal is received.
+ * net_timedwait will also terminate if a signal is received.
*/
- ret = net_lockedwait(&state.snd_sem);
+ if (_SS_ISNONBLOCK(conn->sconn.s_flags) || (flags & MSG_DONTWAIT) != 0)
+ {
+ ret = net_timedwait(&state.snd_sem, 0);
+ }
+ else
+ {
+ ret = net_timedwait(&state.snd_sem, UINT_MAX);
+ }
/* Make sure that no further events are processed */
@@ -296,4 +303,41 @@ ssize_t can_sendmsg(FAR struct socket *psock, FAR struct msghdr *msg,
return state.snd_sent;
}
+/****************************************************************************
+ * Name: psock_can_cansend
+ *
+ * Description:
+ * psock_can_cansend() returns a value indicating if a write to the socket
+ * would block. No space in the buffer is actually reserved, so it is
+ * possible that the write may still block if the buffer is filled by
+ * another means.
+ *
+ * Input Parameters:
+ * psock An instance of the internal socket structure.
+ *
+ * Returned Value:
+ * OK
+ * At least one byte of data could be successfully written.
+ * -EWOULDBLOCK
+ * There is no room in the output buffer.
+ * -EBADF
+ * An invalid descriptor was specified.
+ *
+ ****************************************************************************/
+
+int psock_can_cansend(FAR struct socket *psock)
+{
+ /* Verify that we received a valid socket */
+
+ if (psock == NULL || psock->s_conn == NULL)
+ {
+ nerr("ERROR: Invalid socket\n");
+ return -EBADF;
+ }
+
+ /* TODO Query CAN driver mailboxes to see if there's mailbox available */
+
+ return OK;
+}
+
#endif /* CONFIG_NET && CONFIG_NET_CAN */
diff --git a/net/can/can_sockif.c b/net/can/can_sockif.c
index 780641f972..bddc3ef9b8 100644
--- a/net/can/can_sockif.c
+++ b/net/can/can_sockif.c
@@ -139,15 +139,13 @@ static uint16_t can_poll_eventhandler(FAR struct net_driver_s *dev,
eventset |= (POLLHUP | POLLERR);
}
-#if 0
/* A poll is a sign that we are free to send data. */
else if ((flags & CAN_POLL) != 0 &&
- psock_udp_cansend(info->psock) >= 0)
+ psock_can_cansend(info->psock) >= 0)
{
eventset |= (POLLOUT & info->fds->events);
}
-#endif
/* Awaken the caller of poll() is requested event occurred. */
@@ -608,14 +606,12 @@ static int can_poll_local(FAR struct socket *psock, FAR struct pollfd *fds,
fds->revents |= (POLLRDNORM & fds->events);
}
- #if 0
- if (psock_udp_cansend(psock) >= 0)
+ if (psock_can_cansend(psock) >= 0)
{
- /* Normal data may be sent without blocking (at least one byte). */
+ /* A CAN frame may be sent without blocking. */
fds->revents |= (POLLWRNORM & fds->events);
}
- #endif
/* Check if any requested events are already in effect */
[incubator-nuttx] 06/09: NXStyle and preprocessor fixes Co-authored-by: Jari van Ewijk
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b3590f00b346858c58733b50ce4279daf3ec3a79
Author: Peter van der Perk <pe...@nxp.com>
AuthorDate: Fri Jul 22 17:10:22 2022 +0200
NXStyle and preprocessor fixes
Co-authored-by: Jari van Ewijk <ja...@nxp.com>
---
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h | 262 ++++----
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h | 14 +-
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h | 722 ++++++++++-----------
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c | 8 -
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c | 29 +-
.../arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c | 8 -
.../arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c | 53 +-
drivers/mtd/mx25rxx.c | 8 +-
net/can/can_input.c | 2 +-
9 files changed, 546 insertions(+), 560 deletions(-)
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
index 97cd32ebbc..5c4a52ae4f 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
@@ -107,139 +107,139 @@
/** edma_mux0 **/
-#define DMA_REQ_DISABLED0 0 ///< Channel disabled (default)
-#define DMA_REQ_SIUL_0 1 ///< SIUL DMA request 0
-#define DMA_REQ_SIUL_1 2 ///< SIUL DMA request 1
-#define DMA_REQ_SIUL_2 3 ///< SIUL DMA request 2
-#define DMA_REQ_SIUL_3 4 ///< SIUL DMA request 3
-#define DMA_REQ_SIUL_4 5 ///< SIUL DMA request 4
-#define DMA_REQ_SIUL_5 6 ///< SIUL DMA request 5
-#define DMA_REQ_SIUL_6 7 ///< SIUL DMA request 6
-#define DMA_REQ_SIUL_7 8 ///< SIUL DMA request 7
-#define DMA_REQ_BCTU_FIFO1 10 ///< BCTU DMA FIFO1 request
-#define DMA_REQ_BCTU_0 10 ///< BCTU DMA request 0
-#define DMA_REQ_BCTU_1 11 ///< BCTU DMA request 1
-#define DMA_REQ_EMIOS0_0 12 ///< eMIOS0 DMA request ch0
-#define DMA_REQ_EMIOS0_1 13 ///< eMIOS0 DMA request ch1
-#define DMA_REQ_EMIOS0_9 14 ///< eMIOS0 DMA request ch9
-#define DMA_REQ_EMIOS0_10 15 ///< eMIOS0 DMA request ch10
-#define DMA_REQ_EMIOS1_0 16 ///< eMIOS1 DMA request ch0
-#define DMA_REQ_EMIOS1_1 17 ///< eMIOS1 DMA request ch1
-#define DMA_REQ_EMIOS1_9 18 ///< eMIOS1 DMA request ch9
-#define DMA_REQ_EMIOS1_10 19 ///< eMIOS1 DMA request ch10
-#define DMA_REQ_EMIOS2_0 20 ///< eMIOS2 DMA request ch0
-#define DMA_REQ_EMIOS2_1 21 ///< eMIOS2 DMA request ch1
-#define DMA_REQ_EMIOS2_9 22 ///< eMIOS2 DMA request ch9
-#define DMA_REQ_EMIOS2_10 23 ///< eMIOS2 DMA request ch10
-#define DMA_REQ_LCU0_0 24 ///< LCU0 DMA request 0
-#define DMA_REQ_LCU1_0 25 ///< LCU1 DMA request 0
-#define DMA_REQ_RESERVED1 26 ///< RESERVED
-#define DMA_REQ_RESERVED2 27 ///< RESERVED
-#define DMA_REQ_RESERVED3 28 ///< RESERVED
-#define DMA_REQ_FLEXCAN0 29 ///< FLEXCAN0 DMA request
-#define DMA_REQ_FLEXCAN1 30 ///< FLEXCAN1 DMA request
-#define DMA_REQ_FLEXCAN2 31 ///< FLEXCAN2 DMA request
-#define DMA_REQ_FLEXCAN3 32 ///< FLEXCAN3 DMA request
-#define DMA_REQ_FLEXIO_0 33 ///< FLEXIO DMA shifter0 | timer0 request
-#define DMA_REQ_FLEXIO_1 34 ///< FLEXIO DMA shifter1 | timer1 request
-#define DMA_REQ_FLEXIO_2 35 ///< FLEXIO DMA shifter2 | timer2 request
-#define DMA_REQ_FLEXIO_3 36 ///< FLEXIO DMA shifter3 | timer3 request
-#define DMA_REQ_LPUART08_TX 37 ///< LPUART0 | LPUART8 DMA transmit request
-#define DMA_REQ_LPUART08_RX 38 ///< LPUART0 | LPUART8 DMA receive request
-#define DMA_REQ_LPUART19_TX 39 ///< LPUART1 | LPUART9 DMA transmit request
-#define DMA_REQ_LPUART19_RX 40 ///< LPUART1 | LPUART9 DMA receive request
-#define DMA_REQ_LPI2C0_RX 41 ///< LPI2C0 DMA receive | receive slave request
-#define DMA_REQ_LPI2C0_TX 42 ///< LPI2C0 DMA transmit | transmit slave request
-#define DMA_REQ_LPSPI0_TX 43 ///< LPSPI0 DMA transmit request
-#define DMA_REQ_LPSPI0_RX 44 ///< LPSPI0 DMA receive request
-#define DMA_REQ_LPSPI1_TX 45 ///< LPSPI1 DMA transmit request
-#define DMA_REQ_LPSPI1_RX 46 ///< LPSPI1 DMA receive request
-#define DMA_REQ_LPSPI2_TX 47 ///< LPSPI2 DMA transmit request
-#define DMA_REQ_LPSPI2_RX 48 ///< LPSPI2 DMA receive request
-#define DMA_REQ_LPSPI3_TX 49 ///< LPSPI3 DMA transmit request
-#define DMA_REQ_LPSPI3_RX 50 ///< LPSPI3 DMA receive request
-#define DMA_REQ_I3C0_RX 51 ///< I3C0 DMA receive request
-#define DMA_REQ_I3C0_TX 52 ///< I3C0 DMA transmit request
-#define DMA_REQ_QSPI_RX 53 ///< QSPI DMA receive buffer drain request
-#define DMA_REQ_QSPI_TX 54 ///< QSPI DMA transmit buffer fill request
-#define DMA_REQ_SAI0_RX 55 ///< SAI0 DMA receive request
-#define DMA_REQ_SAI0_TX 56 ///< SAI0 DMA transmit request
-#define DMA_REQ_RESERVED4 57 ///< RESERVED
-#define DMA_REQ_ADC0 58 ///< ADC0 DMA request
-#define DMA_REQ_ADC1 59 ///< ADC1 DMA request
-#define DMA_REQ_ADC2 60 ///< ADC2 DMA request
-#define DMA_REQ_LPCMP0 61 ///< LPCMP0 DMA request
-#define DMA_REQ_ENABLED0 62 ///< Always enabled
-#define DMA_REQ_ENABLED1 63 ///< Always enabled */
+#define DMA_REQ_DISABLED0 (0) ///< Channel disabled (default)
+#define DMA_REQ_SIUL_0 (1) ///< SIUL DMA request 0
+#define DMA_REQ_SIUL_1 (2) ///< SIUL DMA request 1
+#define DMA_REQ_SIUL_2 (3) ///< SIUL DMA request 2
+#define DMA_REQ_SIUL_3 (4) ///< SIUL DMA request 3
+#define DMA_REQ_SIUL_4 (5) ///< SIUL DMA request 4
+#define DMA_REQ_SIUL_5 (6) ///< SIUL DMA request 5
+#define DMA_REQ_SIUL_6 (7) ///< SIUL DMA request 6
+#define DMA_REQ_SIUL_7 (8) ///< SIUL DMA request 7
+#define DMA_REQ_BCTU_FIFO1 (10) ///< BCTU DMA FIFO1 request
+#define DMA_REQ_BCTU_0 (10) ///< BCTU DMA request 0
+#define DMA_REQ_BCTU_1 (11) ///< BCTU DMA request 1
+#define DMA_REQ_EMIOS0_0 (12) ///< eMIOS0 DMA request ch0
+#define DMA_REQ_EMIOS0_1 (13) ///< eMIOS0 DMA request ch1
+#define DMA_REQ_EMIOS0_9 (14) ///< eMIOS0 DMA request ch9
+#define DMA_REQ_EMIOS0_10 (15) ///< eMIOS0 DMA request ch10
+#define DMA_REQ_EMIOS1_0 (16) ///< eMIOS1 DMA request ch0
+#define DMA_REQ_EMIOS1_1 (17) ///< eMIOS1 DMA request ch1
+#define DMA_REQ_EMIOS1_9 (18) ///< eMIOS1 DMA request ch9
+#define DMA_REQ_EMIOS1_10 (19) ///< eMIOS1 DMA request ch10
+#define DMA_REQ_EMIOS2_0 (20) ///< eMIOS2 DMA request ch0
+#define DMA_REQ_EMIOS2_1 (21) ///< eMIOS2 DMA request ch1
+#define DMA_REQ_EMIOS2_9 (22) ///< eMIOS2 DMA request ch9
+#define DMA_REQ_EMIOS2_10 (23) ///< eMIOS2 DMA request ch10
+#define DMA_REQ_LCU0_0 (24) ///< LCU0 DMA request 0
+#define DMA_REQ_LCU1_0 (25) ///< LCU1 DMA request 0
+#define DMA_REQ_RESERVED1 (26) ///< RESERVED
+#define DMA_REQ_RESERVED2 (27) ///< RESERVED
+#define DMA_REQ_RESERVED3 (28) ///< RESERVED
+#define DMA_REQ_FLEXCAN0 (29) ///< FLEXCAN0 DMA request
+#define DMA_REQ_FLEXCAN1 (30) ///< FLEXCAN1 DMA request
+#define DMA_REQ_FLEXCAN2 (31) ///< FLEXCAN2 DMA request
+#define DMA_REQ_FLEXCAN3 (32) ///< FLEXCAN3 DMA request
+#define DMA_REQ_FLEXIO_0 (33) ///< FLEXIO DMA shifter0 | timer0 request
+#define DMA_REQ_FLEXIO_1 (34) ///< FLEXIO DMA shifter1 | timer1 request
+#define DMA_REQ_FLEXIO_2 (35) ///< FLEXIO DMA shifter2 | timer2 request
+#define DMA_REQ_FLEXIO_3 (36) ///< FLEXIO DMA shifter3 | timer3 request
+#define DMA_REQ_LPUART08_TX (37) ///< LPUART0 | LPUART8 DMA transmit request
+#define DMA_REQ_LPUART08_RX (38) ///< LPUART0 | LPUART8 DMA receive request
+#define DMA_REQ_LPUART19_TX (39) ///< LPUART1 | LPUART9 DMA transmit request
+#define DMA_REQ_LPUART19_RX (40) ///< LPUART1 | LPUART9 DMA receive request
+#define DMA_REQ_LPI2C0_RX (41) ///< LPI2C0 DMA receive | receive slave request
+#define DMA_REQ_LPI2C0_TX (42) ///< LPI2C0 DMA transmit | transmit slave request
+#define DMA_REQ_LPSPI0_TX (43) ///< LPSPI0 DMA transmit request
+#define DMA_REQ_LPSPI0_RX (44) ///< LPSPI0 DMA receive request
+#define DMA_REQ_LPSPI1_TX (45) ///< LPSPI1 DMA transmit request
+#define DMA_REQ_LPSPI1_RX (46) ///< LPSPI1 DMA receive request
+#define DMA_REQ_LPSPI2_TX (47) ///< LPSPI2 DMA transmit request
+#define DMA_REQ_LPSPI2_RX (48) ///< LPSPI2 DMA receive request
+#define DMA_REQ_LPSPI3_TX (49) ///< LPSPI3 DMA transmit request
+#define DMA_REQ_LPSPI3_RX (50) ///< LPSPI3 DMA receive request
+#define DMA_REQ_I3C0_RX (51) ///< I3C0 DMA receive request
+#define DMA_REQ_I3C0_TX (52) ///< I3C0 DMA transmit request
+#define DMA_REQ_QSPI_RX (53) ///< QSPI DMA receive buffer drain request
+#define DMA_REQ_QSPI_TX (54) ///< QSPI DMA transmit buffer fill request
+#define DMA_REQ_SAI0_RX (55) ///< SAI0 DMA receive request
+#define DMA_REQ_SAI0_TX (56) ///< SAI0 DMA transmit request
+#define DMA_REQ_RESERVED4 (57) ///< RESERVED
+#define DMA_REQ_ADC0 (58) ///< ADC0 DMA request
+#define DMA_REQ_ADC1 (59) ///< ADC1 DMA request
+#define DMA_REQ_ADC2 (60) ///< ADC2 DMA request
+#define DMA_REQ_LPCMP0 (61) ///< LPCMP0 DMA request
+#define DMA_REQ_ENABLED0 (62) ///< Always enabled
+#define DMA_REQ_ENABLED1 (63) ///< Always enabled */
/** edma_mux1 **/
-#define DMA_REQ_DISABLED1 DMAMUX_CHCFG_DMAMUX1 | 0 ///< Channel disabled (default)
-#define DMA_REQ_SIUL_8 DMAMUX_CHCFG_DMAMUX1 | 1 ///< SIUL DMA request 8
-#define DMA_REQ_SIUL_9 DMAMUX_CHCFG_DMAMUX1 | 2 ///< SIUL DMA request 9
-#define DMA_REQ_SIUL_10 DMAMUX_CHCFG_DMAMUX1 | 3 ///< SIUL DMA request 10
-#define DMA_REQ_SIUL_11 DMAMUX_CHCFG_DMAMUX1 | 4 ///< SIUL DMA request 11
-#define DMA_REQ_SIUL_12 DMAMUX_CHCFG_DMAMUX1 | 5 ///< SIUL DMA request 12
-#define DMA_REQ_SIUL_13 DMAMUX_CHCFG_DMAMUX1 | 6 ///< SIUL DMA request 13
-#define DMA_REQ_SIUL_14 DMAMUX_CHCFG_DMAMUX1 | 7 ///< SIUL DMA request 14
-#define DMA_REQ_SIUL_15 DMAMUX_CHCFG_DMAMUX1 | 8 ///< SIUL DMA request 15
-#define DMA_REQ_BCTU_FIFO2 DMAMUX_CHCFG_DMAMUX1 | 9 ///< BCTU DMA FIFO2 request
-#define DMA_REQ_BCTU_2 DMAMUX_CHCFG_DMAMUX1 | 10 ///< BCTU DMA request 2
-#define DMA_REQ_EMIOS0_16 DMAMUX_CHCFG_DMAMUX1 | 11 ///< eMIOS0 DMA request ch16
-#define DMA_REQ_EMIOS0_17 DMAMUX_CHCFG_DMAMUX1 | 12 ///< eMIOS0 DMA request ch17
-#define DMA_REQ_EMIOS0_18 DMAMUX_CHCFG_DMAMUX1 | 13 ///< eMIOS0 DMA request ch18
-#define DMA_REQ_EMIOS0_19 DMAMUX_CHCFG_DMAMUX1 | 14 ///< eMIOS0 DMA request ch19
-#define DMA_REQ_EMIOS1_16 DMAMUX_CHCFG_DMAMUX1 | 15 ///< eMIOS1 DMA request ch16
-#define DMA_REQ_EMIOS1_17 DMAMUX_CHCFG_DMAMUX1 | 16 ///< eMIOS1 DMA request ch17
-#define DMA_REQ_EMIOS1_18 DMAMUX_CHCFG_DMAMUX1 | 17 ///< eMIOS1 DMA request ch18
-#define DMA_REQ_EMIOS1_19 DMAMUX_CHCFG_DMAMUX1 | 18 ///< eMIOS1 DMA request ch19
-#define DMA_REQ_EMIOS2_16 DMAMUX_CHCFG_DMAMUX1 | 19 ///< eMIOS2 DMA request ch16
-#define DMA_REQ_EMIOS2_17 DMAMUX_CHCFG_DMAMUX1 | 20 ///< eMIOS2 DMA request ch17
-#define DMA_REQ_EMIOS2_18 DMAMUX_CHCFG_DMAMUX1 | 21 ///< eMIOS2 DMA request ch18
-#define DMA_REQ_EMIOS2_19 DMAMUX_CHCFG_DMAMUX1 | 22 ///< eMIOS2 DMA request ch19
-#define DMA_REQ_LCU0_1 DMAMUX_CHCFG_DMAMUX1 | 23 ///< LCU0 DMA request 1
-#define DMA_REQ_LCU0_2 DMAMUX_CHCFG_DMAMUX1 | 24 ///< LCU1 DMA request 2
-#define DMA_REQ_LCU1_1 DMAMUX_CHCFG_DMAMUX1 | 25 ///< LCU1 DMA request 1
-#define DMA_REQ_LCU1_2 DMAMUX_CHCFG_DMAMUX1 | 26 ///< LCU1 DMA request 2
-#define DMA_REQ_ENET_0 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[0] DMA request
-#define DMA_REQ_ENET_1 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[1] DMA request
-#define DMA_REQ_ENET_2 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[2] DMA request
-#define DMA_REQ_ENET_3 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[3] DMA request
-#define DMA_REQ_RESERVED5 DMAMUX_CHCFG_DMAMUX1 | 28 ///< RESERVED
-#define DMA_REQ_RESERVED6 DMAMUX_CHCFG_DMAMUX1 | 29 ///< RESERVED
-#define DMA_REQ_FLECAN4 DMAMUX_CHCFG_DMAMUX1 | 30 ///< FLEXCAN4 DMA request
-#define DMA_REQ_FLECAN5 DMAMUX_CHCFG_DMAMUX1 | 31 ///< FLEXCAN5 DMA request
-#define DMA_REQ_RESERVED7 DMAMUX_CHCFG_DMAMUX1 | 32 ///< RESERVED
-#define DMA_REQ_RESERVED8 DMAMUX_CHCFG_DMAMUX1 | 33 ///< RESERVED
-#define DMA_REQ_FLEXIO_4 DMAMUX_CHCFG_DMAMUX1 | 34 ///< FLEXIO DMA shifter4 | timer4 request
-#define DMA_REQ_FLEXIO_5 DMAMUX_CHCFG_DMAMUX1 | 35 ///< FLEXIO DMA shifter5 | timer5 request
-#define DMA_REQ_FLEXIO_6 DMAMUX_CHCFG_DMAMUX1 | 36 ///< FLEXIO DMA shifter6 | timer6 request
-#define DMA_REQ_FLEXIO_7 DMAMUX_CHCFG_DMAMUX1 | 37 ///< FLEXIO DMA shifter7 | timer7 request
-#define DMA_REQ_LPUART210_TX DMAMUX_CHCFG_DMAMUX1 | 38 ///< LPUART2 | LPUART10 DMA transmit request
-#define DMA_REQ_LPUART210_RX DMAMUX_CHCFG_DMAMUX1 | 39 ///< LPUART2 | LPUART10 DMA receive request
-#define DMA_REQ_LPUART311_TX DMAMUX_CHCFG_DMAMUX1 | 40 ///< LPUART3 | LPUART11 DMA transmit request
-#define DMA_REQ_LPUART311_RX DMAMUX_CHCFG_DMAMUX1 | 41 ///< LPUART3 | LPUART11 DMA receive request
-#define DMA_REQ_LPUART412_TX DMAMUX_CHCFG_DMAMUX1 | 42 ///< LPUART4 | LPUART12 DMA transmit request
-#define DMA_REQ_LPUART412_RX DMAMUX_CHCFG_DMAMUX1 | 43 ///< LPUART4 | LPUART12 DMA receive request
-#define DMA_REQ_LPUART513_TX DMAMUX_CHCFG_DMAMUX1 | 44 ///< LPUART5 | LPUART13 DMA transmit request
-#define DMA_REQ_LPUART513_RX DMAMUX_CHCFG_DMAMUX1 | 45 ///< LPUART5 | LPUART13 DMA receive request
-#define DMA_REQ_LPUART614_TX DMAMUX_CHCFG_DMAMUX1 | 46 ///< LPUART6 | LPUART14 DMA transmit request
-#define DMA_REQ_LPUART614_RX DMAMUX_CHCFG_DMAMUX1 | 47 ///< LPUART6 | LPUART14 DMA receive request
-#define DMA_REQ_LPUART715_TX DMAMUX_CHCFG_DMAMUX1 | 48 ///< LPUART7 | LPUART15 DMA transmit request
-#define DMA_REQ_LPUART715_RX DMAMUX_CHCFG_DMAMUX1 | 49 ///< LPUART7 | LPUART15 DMA receive request
-#define DMA_REQ_LPI2C1_RX DMAMUX_CHCFG_DMAMUX1 | 50 ///< LPI2C1 DMA receive | receive slave request
-#define DMA_REQ_LPI2C1_TX DMAMUX_CHCFG_DMAMUX1 | 51 ///< LPI2C1 DMA transmit | transmit slave request
-#define DMA_REQ_LPSPI4_TX DMAMUX_CHCFG_DMAMUX1 | 52 ///< LPSPI4 DMA transmit request
-#define DMA_REQ_LPSPI4_RX DMAMUX_CHCFG_DMAMUX1 | 53 ///< LPSPI4 DMA receive request
-#define DMA_REQ_LPSPI5_TX DMAMUX_CHCFG_DMAMUX1 | 54 ///< LPSPI5 DMA transmit request
-#define DMA_REQ_LPSPI5_RX DMAMUX_CHCFG_DMAMUX1 | 55 ///< LPSPI5 DMA receive request
-#define DMA_REQ_SAI1_RX DMAMUX_CHCFG_DMAMUX1 | 56 ///< SAI1 DMA RX request
-#define DMA_REQ_SAI1_TX DMAMUX_CHCFG_DMAMUX1 | 57 ///< SAI1 DMA TX request
-#define DMA_REQ_RESERVED9 DMAMUX_CHCFG_DMAMUX1 | 58 ///< RESERVED
-#define DMA_REQ_RESERVED10 DMAMUX_CHCFG_DMAMUX1 | 59 ///< RESERVED
-#define DMA_REQ_LPCMP1 DMAMUX_CHCFG_DMAMUX1 | 60 ///< LPCMP1 DMA request
-#define DMA_REQ_LPCMP2 DMAMUX_CHCFG_DMAMUX1 | 61 ///< LPCMP2 DMA request
-#define DMA_REQ_ENABLED2 DMAMUX_CHCFG_DMAMUX1 | 62 ///< Always enabled
-#define DMA_REQ_ENABLED3 DMAMUX_CHCFG_DMAMUX1 | 63 ///< Always enabled
+#define DMA_REQ_DISABLED1 (DMAMUX_CHCFG_DMAMUX1 | 0) ///< Channel disabled (default)
+#define DMA_REQ_SIUL_8 (DMAMUX_CHCFG_DMAMUX1 | 1) ///< SIUL DMA request 8
+#define DMA_REQ_SIUL_9 (DMAMUX_CHCFG_DMAMUX1 | 2) ///< SIUL DMA request 9
+#define DMA_REQ_SIUL_10 (DMAMUX_CHCFG_DMAMUX1 | 3) ///< SIUL DMA request 10
+#define DMA_REQ_SIUL_11 (DMAMUX_CHCFG_DMAMUX1 | 4) ///< SIUL DMA request 11
+#define DMA_REQ_SIUL_12 (DMAMUX_CHCFG_DMAMUX1 | 5) ///< SIUL DMA request 12
+#define DMA_REQ_SIUL_13 (DMAMUX_CHCFG_DMAMUX1 | 6) ///< SIUL DMA request 13
+#define DMA_REQ_SIUL_14 (DMAMUX_CHCFG_DMAMUX1 | 7) ///< SIUL DMA request 14
+#define DMA_REQ_SIUL_15 (DMAMUX_CHCFG_DMAMUX1 | 8) ///< SIUL DMA request 15
+#define DMA_REQ_BCTU_FIFO2 (DMAMUX_CHCFG_DMAMUX1 | 9) ///< BCTU DMA FIFO2 request
+#define DMA_REQ_BCTU_2 (DMAMUX_CHCFG_DMAMUX1 | 10) ///< BCTU DMA request 2
+#define DMA_REQ_EMIOS0_16 (DMAMUX_CHCFG_DMAMUX1 | 11) ///< eMIOS0 DMA request ch16
+#define DMA_REQ_EMIOS0_17 (DMAMUX_CHCFG_DMAMUX1 | 12) ///< eMIOS0 DMA request ch17
+#define DMA_REQ_EMIOS0_18 (DMAMUX_CHCFG_DMAMUX1 | 13) ///< eMIOS0 DMA request ch18
+#define DMA_REQ_EMIOS0_19 (DMAMUX_CHCFG_DMAMUX1 | 14) ///< eMIOS0 DMA request ch19
+#define DMA_REQ_EMIOS1_16 (DMAMUX_CHCFG_DMAMUX1 | 15) ///< eMIOS1 DMA request ch16
+#define DMA_REQ_EMIOS1_17 (DMAMUX_CHCFG_DMAMUX1 | 16) ///< eMIOS1 DMA request ch17
+#define DMA_REQ_EMIOS1_18 (DMAMUX_CHCFG_DMAMUX1 | 17) ///< eMIOS1 DMA request ch18
+#define DMA_REQ_EMIOS1_19 (DMAMUX_CHCFG_DMAMUX1 | 18) ///< eMIOS1 DMA request ch19
+#define DMA_REQ_EMIOS2_16 (DMAMUX_CHCFG_DMAMUX1 | 19) ///< eMIOS2 DMA request ch16
+#define DMA_REQ_EMIOS2_17 (DMAMUX_CHCFG_DMAMUX1 | 20) ///< eMIOS2 DMA request ch17
+#define DMA_REQ_EMIOS2_18 (DMAMUX_CHCFG_DMAMUX1 | 21) ///< eMIOS2 DMA request ch18
+#define DMA_REQ_EMIOS2_19 (DMAMUX_CHCFG_DMAMUX1 | 22) ///< eMIOS2 DMA request ch19
+#define DMA_REQ_LCU0_1 (DMAMUX_CHCFG_DMAMUX1 | 23) ///< LCU0 DMA request 1
+#define DMA_REQ_LCU0_2 (DMAMUX_CHCFG_DMAMUX1 | 24) ///< LCU1 DMA request 2
+#define DMA_REQ_LCU1_1 (DMAMUX_CHCFG_DMAMUX1 | 25) ///< LCU1 DMA request 1
+#define DMA_REQ_LCU1_2 (DMAMUX_CHCFG_DMAMUX1 | 26) ///< LCU1 DMA request 2
+#define DMA_REQ_ENET_0 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[0] DMA request
+#define DMA_REQ_ENET_1 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[1] DMA request
+#define DMA_REQ_ENET_2 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[2] DMA request
+#define DMA_REQ_ENET_3 (DMAMUX_CHCFG_DMAMUX1 | 27) ///< ENET IEEE 1588 PTP timer ch[3] DMA request
+#define DMA_REQ_RESERVED5 (DMAMUX_CHCFG_DMAMUX1 | 28) ///< RESERVED
+#define DMA_REQ_RESERVED6 (DMAMUX_CHCFG_DMAMUX1 | 29) ///< RESERVED
+#define DMA_REQ_FLECAN4 (DMAMUX_CHCFG_DMAMUX1 | 30) ///< FLEXCAN4 DMA request
+#define DMA_REQ_FLECAN5 (DMAMUX_CHCFG_DMAMUX1 | 31) ///< FLEXCAN5 DMA request
+#define DMA_REQ_RESERVED7 (DMAMUX_CHCFG_DMAMUX1 | 32) ///< RESERVED
+#define DMA_REQ_RESERVED8 (DMAMUX_CHCFG_DMAMUX1 | 33) ///< RESERVED
+#define DMA_REQ_FLEXIO_4 (DMAMUX_CHCFG_DMAMUX1 | 34) ///< FLEXIO DMA shifter4 | timer4 request
+#define DMA_REQ_FLEXIO_5 (DMAMUX_CHCFG_DMAMUX1 | 35) ///< FLEXIO DMA shifter5 | timer5 request
+#define DMA_REQ_FLEXIO_6 (DMAMUX_CHCFG_DMAMUX1 | 36) ///< FLEXIO DMA shifter6 | timer6 request
+#define DMA_REQ_FLEXIO_7 (DMAMUX_CHCFG_DMAMUX1 | 37) ///< FLEXIO DMA shifter7 | timer7 request
+#define DMA_REQ_LPUART210_TX (DMAMUX_CHCFG_DMAMUX1 | 38) ///< LPUART2 | LPUART10 DMA transmit request
+#define DMA_REQ_LPUART210_RX (DMAMUX_CHCFG_DMAMUX1 | 39) ///< LPUART2 | LPUART10 DMA receive request
+#define DMA_REQ_LPUART311_TX (DMAMUX_CHCFG_DMAMUX1 | 40) ///< LPUART3 | LPUART11 DMA transmit request
+#define DMA_REQ_LPUART311_RX (DMAMUX_CHCFG_DMAMUX1 | 41) ///< LPUART3 | LPUART11 DMA receive request
+#define DMA_REQ_LPUART412_TX (DMAMUX_CHCFG_DMAMUX1 | 42) ///< LPUART4 | LPUART12 DMA transmit request
+#define DMA_REQ_LPUART412_RX (DMAMUX_CHCFG_DMAMUX1 | 43) ///< LPUART4 | LPUART12 DMA receive request
+#define DMA_REQ_LPUART513_TX (DMAMUX_CHCFG_DMAMUX1 | 44) ///< LPUART5 | LPUART13 DMA transmit request
+#define DMA_REQ_LPUART513_RX (DMAMUX_CHCFG_DMAMUX1 | 45) ///< LPUART5 | LPUART13 DMA receive request
+#define DMA_REQ_LPUART614_TX (DMAMUX_CHCFG_DMAMUX1 | 46) ///< LPUART6 | LPUART14 DMA transmit request
+#define DMA_REQ_LPUART614_RX (DMAMUX_CHCFG_DMAMUX1 | 47) ///< LPUART6 | LPUART14 DMA receive request
+#define DMA_REQ_LPUART715_TX (DMAMUX_CHCFG_DMAMUX1 | 48) ///< LPUART7 | LPUART15 DMA transmit request
+#define DMA_REQ_LPUART715_RX (DMAMUX_CHCFG_DMAMUX1 | 49) ///< LPUART7 | LPUART15 DMA receive request
+#define DMA_REQ_LPI2C1_RX (DMAMUX_CHCFG_DMAMUX1 | 50) ///< LPI2C1 DMA receive | receive slave request
+#define DMA_REQ_LPI2C1_TX (DMAMUX_CHCFG_DMAMUX1 | 51) ///< LPI2C1 DMA transmit | transmit slave request
+#define DMA_REQ_LPSPI4_TX (DMAMUX_CHCFG_DMAMUX1 | 52) ///< LPSPI4 DMA transmit request
+#define DMA_REQ_LPSPI4_RX (DMAMUX_CHCFG_DMAMUX1 | 53) ///< LPSPI4 DMA receive request
+#define DMA_REQ_LPSPI5_TX (DMAMUX_CHCFG_DMAMUX1 | 54) ///< LPSPI5 DMA transmit request
+#define DMA_REQ_LPSPI5_RX (DMAMUX_CHCFG_DMAMUX1 | 55) ///< LPSPI5 DMA receive request
+#define DMA_REQ_SAI1_RX (DMAMUX_CHCFG_DMAMUX1 | 56) ///< SAI1 DMA RX request
+#define DMA_REQ_SAI1_TX (DMAMUX_CHCFG_DMAMUX1 | 57) ///< SAI1 DMA TX request
+#define DMA_REQ_RESERVED9 (DMAMUX_CHCFG_DMAMUX1 | 58) ///< RESERVED
+#define DMA_REQ_RESERVED10 (DMAMUX_CHCFG_DMAMUX1 | 59) ///< RESERVED
+#define DMA_REQ_LPCMP1 (DMAMUX_CHCFG_DMAMUX1 | 60) ///< LPCMP1 DMA request
+#define DMA_REQ_LPCMP2 (DMAMUX_CHCFG_DMAMUX1 | 61) ///< LPCMP2 DMA request
+#define DMA_REQ_ENABLED2 (DMAMUX_CHCFG_DMAMUX1 | 62) ///< Always enabled
+#define DMA_REQ_ENABLED3 (DMAMUX_CHCFG_DMAMUX1 | 63) ///< Always enabled
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
index 5fcead5f76..cb39c54d5e 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
@@ -1311,13 +1311,13 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
-#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
-#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
-#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
@@ -1328,7 +1328,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
-#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
+#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
/* TCDn Transfer Size (TCDn_NBYTES) */
@@ -1364,7 +1364,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
-#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
@@ -1386,7 +1386,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
-#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
+#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
/* Bit 13: Reserved */
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
@@ -1402,7 +1402,7 @@ uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
-#define EDMA_TCD_BITER_LINKCH(n) ((n << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
+#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/****************************************************************************
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
index 3ebb256b27..b53f34ef87 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
@@ -594,11 +594,11 @@
#define EMAC_MAC_CONFIGURATION_TE (1 << 1) /* Bit 1: Transmitter Enable */
#define EMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2) /* Bits 2-4: Preamble Length for Transmit Packets */
#define EMAC_MAC_CONFIGURATION_PRELEN_MASK (0x3 << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT)
-#define EMAC_MAC_CONFIGURATION_PRELEN(n) ((n << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) & EMAC_MAC_CONFIGURATION_PRELEN_MASK)
+#define EMAC_MAC_CONFIGURATION_PRELEN(n) (((n) << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) & EMAC_MAC_CONFIGURATION_PRELEN_MASK)
#define EMAC_MAC_CONFIGURATION_DC (1 << 4) /* Bit 4: Deferral Check */
#define EMAC_MAC_CONFIGURATION_BL_SHIFT (5) /* Bits 5-7: Back-Off Limit */
#define EMAC_MAC_CONFIGURATION_BL_MASK (0x3 << EMAC_MAC_CONFIGURATION_BL_SHIFT)
-#define EMAC_MAC_CONFIGURATION_BL(n) ((n << EMAC_MAC_CONFIGURATION_BL_SHIFT) & EMAC_MAC_CONFIGURATION_BL_MASK)
+#define EMAC_MAC_CONFIGURATION_BL(n) (((n) << EMAC_MAC_CONFIGURATION_BL_SHIFT) & EMAC_MAC_CONFIGURATION_BL_MASK)
#define EMAC_MAC_CONFIGURATION_DR (1 << 8) /* Bit 8: Disable Retry */
#define EMAC_MAC_CONFIGURATION_DCRS (1 << 9) /* Bit 9: Disable Carrier Sense During Transmission */
#define EMAC_MAC_CONFIGURATION_DO (1 << 10) /* Bit 10: Disable Receive Own */
@@ -616,16 +616,16 @@
#define EMAC_MAC_CONFIGURATION_GPSLCE (1 << 23) /* Bit 23: Giant Packet Size Limit Control Enable */
#define EMAC_MAC_CONFIGURATION_IPG_SHIFT (24) /* Bits 24-27: Inter-Packet Gap */
#define EMAC_MAC_CONFIGURATION_IPG_MASK (0x7 << EMAC_MAC_CONFIGURATION_IPG_SHIFT)
-#define EMAC_MAC_CONFIGURATION_IPG(n) ((n << EMAC_MAC_CONFIGURATION_IPG_SHIFT) & EMAC_MAC_CONFIGURATION_IPG_MASK)
+#define EMAC_MAC_CONFIGURATION_IPG(n) (((n) << EMAC_MAC_CONFIGURATION_IPG_SHIFT) & EMAC_MAC_CONFIGURATION_IPG_MASK)
#define EMAC_MAC_CONFIGURATION_IPC (1 << 27) /* Bit 27: Checksum Offload */
#define EMAC_MAC_CONFIGURATION_SARC_SHIFT (28) /* Bits 28-31: Source Address Insertion Or Replacement Control */
#define EMAC_MAC_CONFIGURATION_SARC_MASK (0x7 << EMAC_MAC_CONFIGURATION_SARC_SHIFT)
-#define EMAC_MAC_CONFIGURATION_SARC(n) ((n << EMAC_MAC_CONFIGURATION_SARC_SHIFT) & EMAC_MAC_CONFIGURATION_SARC_MASK)
+#define EMAC_MAC_CONFIGURATION_SARC(n) (((n) << EMAC_MAC_CONFIGURATION_SARC_SHIFT) & EMAC_MAC_CONFIGURATION_SARC_MASK)
/* MAC Extended Configuration (MAC_EXT_CONFIGURATION) */
#define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0) /* Bits 0-14: Giant Packet Size Limit */
#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFF << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT)
-#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) ((n << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK)
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK)
#define EMAC_MAC_EXT_CONFIGURATION_DCRCC (1 << 16) /* Bit 16: Disable CRC Checking For Received Packets */
#define EMAC_MAC_EXT_CONFIGURATION_SPEN (1 << 17) /* Bit 17: Slow Protocol Detection Enable */
#define EMAC_MAC_EXT_CONFIGURATION_USP (1 << 18) /* Bit 18: Unicast Slow Protocol Packet Detect */
@@ -633,7 +633,7 @@
#define EMAC_MAC_EXT_CONFIGURATION_EIPGEN (1 << 24) /* Bit 24: Extended Inter-Packet Gap Enable */
#define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25) /* Bits 25-30: Extended Inter-Packet Gap */
#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1F << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT)
-#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) ((n << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK)
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK)
/* MAC Packet Filter (MAC_PACKET_FILTER) */
#define EMAC_MAC_PACKET_FILTER_PR (1 << 0) /* Bit 0: Promiscuous Mode */
@@ -644,7 +644,7 @@
#define EMAC_MAC_PACKET_FILTER_DBF (1 << 5) /* Bit 5: Disable Broadcast Packets */
#define EMAC_MAC_PACKET_FILTER_PCF_SHIFT (6) /* Bits 6-8: Pass Control Packets */
#define EMAC_MAC_PACKET_FILTER_PCF_MASK (0x3 << EMAC_MAC_PACKET_FILTER_PCF_SHIFT)
-#define EMAC_MAC_PACKET_FILTER_PCF(n) ((n << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) & EMAC_MAC_PACKET_FILTER_PCF_MASK)
+#define EMAC_MAC_PACKET_FILTER_PCF(n) (((n) << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) & EMAC_MAC_PACKET_FILTER_PCF_MASK)
#define EMAC_MAC_PACKET_FILTER_SAIF (1 << 8) /* Bit 8: SA Inverse Filtering */
#define EMAC_MAC_PACKET_FILTER_SAF (1 << 9) /* Bit 9: Source Address Filter Enable */
#define EMAC_MAC_PACKET_FILTER_HPF (1 << 10) /* Bit 10: Hash Or Perfect Filter */
@@ -656,23 +656,23 @@
/* MAC Watchdog Timeout (MAC_WATCHDOG_TIMEOUT) */
#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0) /* Bits 0-4: Watchdog Timeout */
#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xF << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)
-#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) ((n << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) (((n) << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
#define EMAC_MAC_WATCHDOG_TIMEOUT_PWE (1 << 8) /* Bit 8: Programmable Watchdog Enable */
/* MAC Hash Table First 32 Bits (MAC_HASH_TABLE_REG0) */
#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0) /* Bits 0-32: MAC Hash Table First 32 Bits */
#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)
-#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) ((n << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK)
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) (((n) << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK)
/* MAC Hash Table Second 32 Bits (MAC_HASH_TABLE_REG1) */
#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0) /* Bits 0-32: MAC Hash Table Second 32 Bits */
#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)
-#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) ((n << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK)
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) (((n) << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK)
/* MAC VLAN Tag (MAC_VLAN_TAG) */
#define EMAC_MAC_VLAN_TAG_VL_SHIFT (0) /* Bits 0-16: VLAN Tag Identifier for Receive Packets */
#define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_VL_SHIFT)
-#define EMAC_MAC_VLAN_TAG_VL(n) ((n << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK)
+#define EMAC_MAC_VLAN_TAG_VL(n) (((n) << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK)
#define EMAC_MAC_VLAN_TAG_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */
#define EMAC_MAC_VLAN_TAG_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */
#define EMAC_MAC_VLAN_TAG_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */
@@ -680,14 +680,14 @@
#define EMAC_MAC_VLAN_TAG_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */
#define EMAC_MAC_VLAN_TAG_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */
#define EMAC_MAC_VLAN_TAG_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EVLS_SHIFT)
-#define EMAC_MAC_VLAN_TAG_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_EVLS(n) (((n) << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK)
#define EMAC_MAC_VLAN_TAG_EVLRXS (1 << 24) /* Bit 24: Enable VLAN Tag In Receive Status */
#define EMAC_MAC_VLAN_TAG_VTHM (1 << 25) /* Bit 25: VLAN Tag Hash Table Match */
#define EMAC_MAC_VLAN_TAG_EDVLP (1 << 26) /* Bit 26: Enable Double VLAN Processing */
#define EMAC_MAC_VLAN_TAG_ERIVLT (1 << 27) /* Bit 27: Enable Inner VLAN Tag Comparison */
#define EMAC_MAC_VLAN_TAG_EIVLS_SHIFT (28) /* Bits 28-30: Enable Inner VLAN Tag Stripping */
#define EMAC_MAC_VLAN_TAG_EIVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT)
-#define EMAC_MAC_VLAN_TAG_EIVLS(n) ((n << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EIVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_EIVLS(n) (((n) << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EIVLS_MASK)
#define EMAC_MAC_VLAN_TAG_EIVLRXS (1 << 31) /* Bit 31: Enable Inner VLAN Tag In Receive Status */
/* MAC VLAN Tag Control (MAC_VLAN_TAG_CTRL) */
@@ -695,7 +695,7 @@
#define EMAC_MAC_VLAN_TAG_CTRL_CT (1 << 1) /* Bit 1: Command Type */
#define EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2) /* Bits 2-4: Offset */
#define EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT)
-#define EMAC_MAC_VLAN_TAG_CTRL_OFS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK)
+#define EMAC_MAC_VLAN_TAG_CTRL_OFS(n) (((n) << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK)
#define EMAC_MAC_VLAN_TAG_CTRL_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */
#define EMAC_MAC_VLAN_TAG_CTRL_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */
#define EMAC_MAC_VLAN_TAG_CTRL_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */
@@ -703,20 +703,20 @@
#define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */
#define EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */
#define EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)
-#define EMAC_MAC_VLAN_TAG_CTRL_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_CTRL_EVLS(n) (((n) << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK)
#define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS (1 << 24) /* Bit 24: Enable VLAN Tag In Receive Status */
#define EMAC_MAC_VLAN_TAG_CTRL_VTHM (1 << 25) /* Bit 25: VLAN Tag Hash Table Match */
#define EMAC_MAC_VLAN_TAG_CTRL_EDVLP (1 << 26) /* Bit 26: Enable Double VLAN Processing */
#define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT (1 << 27) /* Bit 27: Enable Inner VLAN Tag Comparison */
#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28) /* Bits 28-30: Enable Inner VLAN Tag Stripping */
#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)
-#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS(n) (((n) << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
#define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS (1 << 31) /* Bit 31: Enable Inner VLAN Tag In Receive Status */
/* MAC VLAN Tag Data (MAC_VLAN_TAG_DATA) */
#define EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
#define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT)
-#define EMAC_MAC_VLAN_TAG_DATA_VID(n) ((n << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_DATA_VID(n) (((n) << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK)
#define EMAC_MAC_VLAN_TAG_DATA_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_DATA_ETV (1 << 17) /* Bit 17: VLAN Comparison */
#define EMAC_MAC_VLAN_TAG_DATA_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
@@ -728,7 +728,7 @@
/* MAC VLAN Tag Filter 0 (MAC_VLAN_TAG_FILTER0) */
#define EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
#define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT)
-#define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER0_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER0_ETV (1 << 17) /* Bit 17: VLAN Comparison */
#define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
@@ -740,7 +740,7 @@
/* MAC VLAN Tag Filter 1 (MAC_VLAN_TAG_FILTER1) */
#define EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
#define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT)
-#define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER1_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER1_ETV (1 << 17) /* Bit 17: VLAN Comparison */
#define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
@@ -752,7 +752,7 @@
/* MAC VLAN Tag Filter 2 (MAC_VLAN_TAG_FILTER2) */
#define EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
#define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT)
-#define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER2_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER2_ETV (1 << 17) /* Bit 17: VLAN Comparison */
#define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
@@ -764,7 +764,7 @@
/* MAC VLAN Tag Filter 3 (MAC_VLAN_TAG_FILTER3) */
#define EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
#define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT)
-#define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER3_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER3_ETV (1 << 17) /* Bit 17: VLAN Comparison */
#define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
@@ -776,15 +776,15 @@
/* MAC VLAN Hash Table (MAC_VLAN_HASH_TABLE) */
#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0) /* Bits 0-16: VLAN Hash Table */
#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFF << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)
-#define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) ((n << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK)
+#define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) (((n) << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK)
/* MAC VLAN Inclusion Or Replacement (MAC_VLAN_INCL) */
#define EMAC_MAC_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */
#define EMAC_MAC_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_VLAN_INCL_VLT_SHIFT)
-#define EMAC_MAC_VLAN_INCL_VLT(n) ((n << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK)
+#define EMAC_MAC_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK)
#define EMAC_MAC_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control */
#define EMAC_MAC_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_VLAN_INCL_VLC_SHIFT)
-#define EMAC_MAC_VLAN_INCL_VLC(n) ((n << EMAC_MAC_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_VLAN_INCL_VLC_MASK)
+#define EMAC_MAC_VLAN_INCL_VLC(n) (((n) << EMAC_MAC_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_VLAN_INCL_VLC_MASK)
#define EMAC_MAC_VLAN_INCL_VLP (1 << 18) /* Bit 18: VLAN Priority Control */
#define EMAC_MAC_VLAN_INCL_CSVL (1 << 19) /* Bit 19: C-VLAN Or S-VLAN */
#define EMAC_MAC_VLAN_INCL_VLTI (1 << 20) /* Bit 20: VLAN Tag Input */
@@ -796,10 +796,10 @@
/* Inner VLAN Tag Inclusion Or Replacement (MAC_INNER_VLAN_INCL) */
#define EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */
#define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT)
-#define EMAC_MAC_INNER_VLAN_INCL_VLT(n) ((n << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK)
+#define EMAC_MAC_INNER_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK)
#define EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control in Transmit Packets */
#define EMAC_MAC_INNER_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT)
-#define EMAC_MAC_INNER_VLAN_INCL_VLC(n) ((n << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLC_MASK)
+#define EMAC_MAC_INNER_VLAN_INCL_VLC(n) (((n) << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLC_MASK)
#define EMAC_MAC_INNER_VLAN_INCL_VLP (1 << 18) /* Bit 18: VLAN Priority Control */
#define EMAC_MAC_INNER_VLAN_INCL_CSVL (1 << 19) /* Bit 19: C-VLAN Or S-VLAN */
#define EMAC_MAC_INNER_VLAN_INCL_VLTI (1 << 20) /* Bit 20: VLAN Tag Input */
@@ -809,11 +809,11 @@
#define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1 << 1) /* Bit 1: Transmit Flow Control Enable */
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4) /* Bits 4-7: Pause Low Threshold */
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x7 << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT)
-#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) ((n << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK)
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK)
#define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ (1 << 7) /* Bit 7: Disable Zero-Quanta Pause */
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16) /* Bits 16-32: Pause Time */
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT)
-#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) ((n << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK)
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK)
/* MAC Receive Flow Control (MAC_RX_FLOW_CTRL) */
#define EMAC_MAC_RX_FLOW_CTRL_RFE (1 << 0) /* Bit 0: Receive Flow Control Enable */
@@ -830,13 +830,13 @@
/* MAC RxQ Control 0 (MAC_RXQ_CTRL0) */
#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0) /* Bits 0-2: Receive Queue 0 Enable */
#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK (0x3 << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT)
-#define EMAC_MAC_RXQ_CTRL0_RXQ0EN(n) ((n << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK)
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN(n) (((n) << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK)
#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_DISABLE EMAC_MAC_RXQ_CTRL0_RXQ0EN(0)
#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_AVB EMAC_MAC_RXQ_CTRL0_RXQ0EN(0x1)
#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_DCB_GEN EMAC_MAC_RXQ_CTRL0_RXQ0EN(0x2)
#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-4: Receive Queue 1 Enable */
#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK (0x3 << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT)
-#define EMAC_MAC_RXQ_CTRL0_RXQ1EN(n) ((n << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK)
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN(n) (((n) << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK)
#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_DISABLE EMAC_MAC_RXQ_CTRL0_RXQ1EN(0)
#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_AVB EMAC_MAC_RXQ_CTRL0_RXQ1EN(0x1)
#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_DCB_GEN EMAC_MAC_RXQ_CTRL0_RXQ1EN(0x2)
@@ -844,32 +844,32 @@
/* Receive Queue Control 1 (MAC_RXQ_CTRL1) */
#define EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0) /* Bits 0-3: AV Untagged Control Packets Queue */
#define EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
-#define EMAC_MAC_RXQ_CTRL1_AVCPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_AVCPQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK)
#define EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT (4) /* Bits 4-7: PTP Packets Queue */
#define EMAC_MAC_RXQ_CTRL1_PTPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT)
-#define EMAC_MAC_RXQ_CTRL1_PTPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_PTPQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK)
#define EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT (12) /* Bits 12-15: Untagged Packet Queue */
#define EMAC_MAC_RXQ_CTRL1_UPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT)
-#define EMAC_MAC_RXQ_CTRL1_UPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_UPQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK)
#define EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16) /* Bits 16-19: Multicast And Broadcast Queue */
#define EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT)
-#define EMAC_MAC_RXQ_CTRL1_MCBCQ(n) ((n << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_MCBCQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK)
#define EMAC_MAC_RXQ_CTRL1_MCBCQEN (1 << 20) /* Bit 20: Multicast And Broadcast Queue Enable */
#define EMAC_MAC_RXQ_CTRL1_TACPQE (1 << 21) /* Bit 21: Tagged AV Control Packets Queuing Enable */
#define EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT (22) /* Bits 22-24: Tagged PTP Over Ethernet Packets Queuing Control */
#define EMAC_MAC_RXQ_CTRL1_TPQC_MASK (0x3 << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT)
-#define EMAC_MAC_RXQ_CTRL1_TPQC(n) ((n << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK)
+#define EMAC_MAC_RXQ_CTRL1_TPQC(n) (((n) << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK)
#define EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT (24) /* Bits 24-27: Frame Preemption Residue Queue */
#define EMAC_MAC_RXQ_CTRL1_FPRQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT)
-#define EMAC_MAC_RXQ_CTRL1_FPRQ(n) ((n << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_FPRQ(n) (((n) << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK)
/* MAC RxQ Control 2 (MAC_RXQ_CTRL2) */
#define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0) /* Bits 0-8: Priorities Selected In Receive Queue 0 */
#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT)
-#define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) ((n << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK)
#define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8) /* Bits 8-16: Priorities Selected In Receive Queue 1 */
#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT)
-#define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) ((n << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK)
/* MAC Interrupt Status (MAC_INTERRUPT_STATUS) */
#define EMAC_MAC_INTERRUPT_STATUS_PHYIS (1 << 3) /* Bit 3: PHY Interrupt */
@@ -904,20 +904,20 @@
/* MAC Version (MAC_VERSION) */
#define EMAC_MAC_VERSION_IPVER_SHIFT (0) /* Bits 0-8: IP Version */
#define EMAC_MAC_VERSION_IPVER_MASK (0xFF << EMAC_MAC_VERSION_IPVER_SHIFT)
-#define EMAC_MAC_VERSION_IPVER(n) ((n << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK)
+#define EMAC_MAC_VERSION_IPVER(n) (((n) << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK)
#define EMAC_MAC_VERSION_CFGVER_SHIFT (8) /* Bits 8-16: IP Configuration Version */
#define EMAC_MAC_VERSION_CFGVER_MASK (0xFF << EMAC_MAC_VERSION_CFGVER_SHIFT)
-#define EMAC_MAC_VERSION_CFGVER(n) ((n << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK)
+#define EMAC_MAC_VERSION_CFGVER(n) (((n) << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK)
/* MAC Debug (MAC_DEBUG) */
#define EMAC_MAC_DEBUG_RPESTS (1 << 0) /* Bit 0: Receive Protocol Engine Status */
#define EMAC_MAC_DEBUG_RFCFCSTS_SHIFT (1) /* Bits 1-3: MAC Receive Packet Controller FIFO Status */
#define EMAC_MAC_DEBUG_RFCFCSTS_MASK (0x3 << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT)
-#define EMAC_MAC_DEBUG_RFCFCSTS(n) ((n << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT) & EMAC_MAC_DEBUG_RFCFCSTS_MASK)
+#define EMAC_MAC_DEBUG_RFCFCSTS(n) (((n) << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT) & EMAC_MAC_DEBUG_RFCFCSTS_MASK)
#define EMAC_MAC_DEBUG_TPESTS (1 << 16) /* Bit 16: MAC GMII Or MII Transmit Protocol Engine Status */
#define EMAC_MAC_DEBUG_TFCSTS_SHIFT (17) /* Bits 17-19: MAC Transmit Packet Controller Status */
#define EMAC_MAC_DEBUG_TFCSTS_MASK (0x3 << EMAC_MAC_DEBUG_TFCSTS_SHIFT)
-#define EMAC_MAC_DEBUG_TFCSTS(n) ((n << EMAC_MAC_DEBUG_TFCSTS_SHIFT) & EMAC_MAC_DEBUG_TFCSTS_MASK)
+#define EMAC_MAC_DEBUG_TFCSTS(n) (((n) << EMAC_MAC_DEBUG_TFCSTS_SHIFT) & EMAC_MAC_DEBUG_TFCSTS_MASK)
/* MAC Hardware Feature 0 (MAC_HW_FEATURE0) */
#define EMAC_MAC_HW_FEATURE0_MIISEL (1 << 0) /* Bit 0: 10 or 100 Mbit/s Support Feature */
@@ -936,31 +936,31 @@
#define EMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) /* Bit 16: Receive Checksum Offload Feature */
#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18) /* Bits 18-23: MAC Addresses 1-31 */
#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1F << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT)
-#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) ((n << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK)
+#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK)
#define EMAC_MAC_HW_FEATURE0_MACADR32SEL (1 << 23) /* Bit 23: MAC Addresses 32-63 */
#define EMAC_MAC_HW_FEATURE0_MACADR64SEL (1 << 24) /* Bit 24: MAC Addresses 64-127 */
#define EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25) /* Bits 25-27: Timestamp System Time Source Feature */
#define EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x3 << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT)
-#define EMAC_MAC_HW_FEATURE0_TSSTSSEL(n) ((n << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK)
+#define EMAC_MAC_HW_FEATURE0_TSSTSSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK)
#define EMAC_MAC_HW_FEATURE0_SAVLANINS (1 << 27) /* Bit 27: SA or VLAN Insertion Feature */
#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28) /* Bits 28-31: Active PHY Feature */
#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0x7 << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT)
-#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(n) ((n << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK)
+#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK)
/* MAC Hardware Feature 1 (MAC_HW_FEATURE1) */
#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0) /* Bits 0-5: MTL Receive FIFO Size Feature */
#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT)
-#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) ((n << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK)
+#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK)
#define EMAC_MAC_HW_FEATURE1_SPRAM (1 << 5) /* Bit 5: Single Port RAM Feature */
#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6) /* Bits 6-11: MTL Transmit FIFO Size Feature */
#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT)
-#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) ((n << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK)
+#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK)
#define EMAC_MAC_HW_FEATURE1_OSTEN (1 << 11) /* Bit 11: One-Step Timestamping Enable Feature */
#define EMAC_MAC_HW_FEATURE1_PTOEN (1 << 12) /* Bit 12: PTP Offload Enable Feature */
#define EMAC_MAC_HW_FEATURE1_ADVTHWORD (1 << 13) /* Bit 13: IEEE 1588 High-Word Feature */
#define EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14) /* Bits 14-16: Address Width Feature */
#define EMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3 << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
-#define EMAC_MAC_HW_FEATURE1_ADDR64(n) ((n << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK)
+#define EMAC_MAC_HW_FEATURE1_ADDR64(n) (((n) << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK)
#define EMAC_MAC_HW_FEATURE1_DCBEN (1 << 16) /* Bit 16: DCB Enable Feature */
#define EMAC_MAC_HW_FEATURE1_SPHEN (1 << 17) /* Bit 17: Split Header Enable Feature */
#define EMAC_MAC_HW_FEATURE1_TSOEN (1 << 18) /* Bit 18: TCP Segmentation Offload Enable Feature */
@@ -970,57 +970,57 @@
#define EMAC_MAC_HW_FEATURE1_POUOST (1 << 23) /* Bit 23: One Step For PTP Over UDP/IP Feature */
#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24) /* Bits 24-26: Hash Table Size */
#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3 << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT)
-#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) ((n << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK)
+#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) (((n) << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK)
#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27) /* Bits 27-31: L3 Or L4 Filter Number */
#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xF << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT)
-#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) ((n << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK)
+#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) (((n) << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK)
/* MAC Hardware Feature 2 (MAC_HW_FEATURE2) */
#define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0) /* Bits 0-4: Number Of MTL Receive Queues */
#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT)
-#define EMAC_MAC_HW_FEATURE2_RXQCNT(n) ((n << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_RXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6) /* Bits 6-10: Number Of MTL Transmit Queues */
#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT)
-#define EMAC_MAC_HW_FEATURE2_TXQCNT(n) ((n << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_TXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12) /* Bits 12-16: Number Of DMA Receive Channels */
#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT)
-#define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) ((n << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18) /* Bits 18-22: Number Of DMA Transmit Channels */
#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT)
-#define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) ((n << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24) /* Bits 24-27: Number Of PPS Outputs */
#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT)
-#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(n) ((n << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK)
+#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(n) (((n) << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK)
#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28) /* Bits 28-31: Number Of Auxiliary Snapshot Inputs */
#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT)
-#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(n) ((n << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK)
+#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(n) (((n) << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK)
/* MAC Hardware Feature 3 (MAC_HW_FEATURE3) */
#define EMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0) /* Bits 0-3: Number Of Extended VLAN Tag Filters Indicates the number of selected extended VLAN tag filters. */
#define EMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7 << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT)
-#define EMAC_MAC_HW_FEATURE3_NRVF(n) ((n << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT) & EMAC_MAC_HW_FEATURE3_NRVF_MASK)
+#define EMAC_MAC_HW_FEATURE3_NRVF(n) (((n) << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT) & EMAC_MAC_HW_FEATURE3_NRVF_MASK)
#define EMAC_MAC_HW_FEATURE3_CBTISEL (1 << 4) /* Bit 4: Queue/Channel Based VLAN Tag Insertion On Transmit Feature */
#define EMAC_MAC_HW_FEATURE3_DVLAN (1 << 5) /* Bit 5: Double VLAN Tag Processing Feature */
#define EMAC_MAC_HW_FEATURE3_PDUPSEL (1 << 9) /* Bit 9: Broadcast/Multicast Packet Duplication Feature */
#define EMAC_MAC_HW_FEATURE3_FRPSEL (1 << 10) /* Bit 10: Flexible Receive Parser Feature */
#define EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11) /* Bits 11-13: Flexible Receive Parser Buffer Size */
#define EMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x3 << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT)
-#define EMAC_MAC_HW_FEATURE3_FRPBS(n) ((n << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK)
+#define EMAC_MAC_HW_FEATURE3_FRPBS(n) (((n) << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK)
#define EMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13) /* Bits 13-15: Flexible Receive Parser Table Entry Size */
#define EMAC_MAC_HW_FEATURE3_FRPES_MASK (0x3 << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT)
-#define EMAC_MAC_HW_FEATURE3_FRPES(n) ((n << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPES_MASK)
+#define EMAC_MAC_HW_FEATURE3_FRPES(n) (((n) << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPES_MASK)
#define EMAC_MAC_HW_FEATURE3_ESTSEL (1 << 16) /* Bit 16: Enhancements To Scheduling Traffic Feature */
#define EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17) /* Bits 17-20: Depth Of Gate Control List */
#define EMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0x7 << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT)
-#define EMAC_MAC_HW_FEATURE3_ESTDEP(n) ((n << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK)
+#define EMAC_MAC_HW_FEATURE3_ESTDEP(n) (((n) << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK)
#define EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20) /* Bits 20-22: Estimated Time Interval Width */
#define EMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x3 << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT)
-#define EMAC_MAC_HW_FEATURE3_ESTWID(n) ((n << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK)
+#define EMAC_MAC_HW_FEATURE3_ESTWID(n) (((n) << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK)
#define EMAC_MAC_HW_FEATURE3_FPESEL (1 << 26) /* Bit 26: Frame Preemption Feature */
#define EMAC_MAC_HW_FEATURE3_TBSSEL (1 << 27) /* Bit 27: Time-Based Scheduling Feature */
#define EMAC_MAC_HW_FEATURE3_ASP_SHIFT (28) /* Bits 28-30: Automotive Safety Package */
#define EMAC_MAC_HW_FEATURE3_ASP_MASK (0x3 << EMAC_MAC_HW_FEATURE3_ASP_SHIFT)
-#define EMAC_MAC_HW_FEATURE3_ASP(n) ((n << EMAC_MAC_HW_FEATURE3_ASP_SHIFT) & EMAC_MAC_HW_FEATURE3_ASP_MASK)
+#define EMAC_MAC_HW_FEATURE3_ASP(n) (((n) << EMAC_MAC_HW_FEATURE3_ASP_SHIFT) & EMAC_MAC_HW_FEATURE3_ASP_MASK)
/* MAC DPP FSM Interrupt Status (MAC_DPP_FSM_INTERRUPT_STATUS) */
#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES (1 << 2) /* Bit 2: Read Descriptor Parity Checker Error Status */
@@ -1053,18 +1053,18 @@
/* MAC FSM ACT Timer (MAC_FSM_ACT_TIMER) */
#define EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT (0) /* Bits 0-10: CSR Clocks For 1 us Tic */
#define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3FF << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT)
-#define EMAC_MAC_FSM_ACT_TIMER_TMR(n) ((n << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK)
+#define EMAC_MAC_FSM_ACT_TIMER_TMR(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK)
#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT (16) /* Bits 16-20: Normal Mode Timeout Value */
#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT)
-#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) ((n << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK)
+#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK)
#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT (20) /* Bits 20-24: Large Mode Timeout Value */
#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT)
-#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) ((n << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK)
+#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK)
/* SCS_REG 1 (SCS_REG1) */
#define EMAC_SCS_REG1_MAC_SCS1_SHIFT (0) /* Bits 0-32: MAC SCS 1 */
#define EMAC_SCS_REG1_MAC_SCS1_MASK (0xFFFFFFFF << EMAC_SCS_REG1_MAC_SCS1_SHIFT)
-#define EMAC_SCS_REG1_MAC_SCS1(n) ((n << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK)
+#define EMAC_SCS_REG1_MAC_SCS1(n) (((n) << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK)
/* MAC MDIO Address (MAC_MDIO_ADDRESS) */
#define EMAC_MAC_MDIO_ADDRESS_GB (1 << 0) /* Bit 0: GMII Busy */
@@ -1074,26 +1074,26 @@
#define EMAC_MAC_MDIO_ADDRESS_SKAP (1 << 4) /* Bit 4: Skip Address Packet */
#define EMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8) /* Bits 8-12: CSR Clock Range */
#define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xF << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
-#define EMAC_MAC_MDIO_ADDRESS_CR(n) ((n << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_CR(n) (((n) << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK)
#define EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12) /* Bits 12-15: Number Of Trailing Clocks */
#define EMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7 << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT)
-#define EMAC_MAC_MDIO_ADDRESS_NTC(n) ((n << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_NTC(n) (((n) << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK)
#define EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16) /* Bits 16-21: Register Or Device Address */
#define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT)
-#define EMAC_MAC_MDIO_ADDRESS_RDA(n) ((n << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_RDA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK)
#define EMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21) /* Bits 21-26: Physical Layer Address */
#define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT)
-#define EMAC_MAC_MDIO_ADDRESS_PA(n) ((n << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_PA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK)
#define EMAC_MAC_MDIO_ADDRESS_BTB (1 << 26) /* Bit 26: Back-To-Back Transactions */
#define EMAC_MAC_MDIO_ADDRESS_PSE (1 << 27) /* Bit 27: Preamble Suppression Enable */
/* MAC MDIO Data (MAC_MDIO_DATA) */
#define EMAC_MAC_MDIO_DATA_GD_SHIFT (0) /* Bits 0-16: GMII Data */
#define EMAC_MAC_MDIO_DATA_GD_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_GD_SHIFT)
-#define EMAC_MAC_MDIO_DATA_GD(n) ((n << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK)
+#define EMAC_MAC_MDIO_DATA_GD(n) (((n) << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK)
#define EMAC_MAC_MDIO_DATA_RA_SHIFT (16) /* Bits 16-32: Register Address */
#define EMAC_MAC_MDIO_DATA_RA_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_RA_SHIFT)
-#define EMAC_MAC_MDIO_DATA_RA(n) ((n << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK)
+#define EMAC_MAC_MDIO_DATA_RA(n) (((n) << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK)
/* MAC CSR Software Control (MAC_CSR_SW_CTRL) */
#define EMAC_MAC_CSR_SW_CTRL_RCWE (1 << 0) /* Bit 0: Enable Register Write 1 To Clear (W1C) */
@@ -1112,62 +1112,62 @@
/* MAC Presentation Time (MAC_PRESN_TIME_NS) */
#define EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time (In Nanoseconds) */
#define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT)
-#define EMAC_MAC_PRESN_TIME_NS_MPTN(n) ((n << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK)
+#define EMAC_MAC_PRESN_TIME_NS_MPTN(n) (((n) << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK)
/* MAC Presentation Time Update (MAC_PRESN_TIME_UPDT) */
#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time Update */
#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)
-#define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) ((n << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK)
+#define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) (((n) << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK)
/* MAC Address 0 High (MAC_ADDRESS0_HIGH) */
#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 0 [47:32] */
#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)
-#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK)
+#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK)
#define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
#define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT)
-#define EMAC_MAC_ADDRESS0_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK)
+#define EMAC_MAC_ADDRESS0_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK)
#define EMAC_MAC_ADDRESS0_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
/* MAC Address 0 Low (MAC_ADDRESS0_LOW) */
#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 0 [31:0] */
#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)
-#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK)
+#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK)
/* MAC Address 1 High (MAC_ADDRESS1_HIGH) */
#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */
#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT)
-#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK)
+#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK)
#define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
#define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT)
-#define EMAC_MAC_ADDRESS1_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK)
+#define EMAC_MAC_ADDRESS1_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK)
#define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */
#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT)
-#define EMAC_MAC_ADDRESS1_HIGH_MBC(n) ((n << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK)
+#define EMAC_MAC_ADDRESS1_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK)
#define EMAC_MAC_ADDRESS1_HIGH_SA (1 << 30) /* Bit 30: Source Address */
#define EMAC_MAC_ADDRESS1_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
/* MAC Address 1 Low (MAC_ADDRESS1_LOW) */
#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */
#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT)
-#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK)
+#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK)
/* MAC Address 2 High (MAC_ADDRESS2_HIGH) */
#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */
#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT)
-#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK)
+#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK)
#define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
#define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT)
-#define EMAC_MAC_ADDRESS2_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK)
+#define EMAC_MAC_ADDRESS2_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK)
#define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */
#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT)
-#define EMAC_MAC_ADDRESS2_HIGH_MBC(n) ((n << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK)
+#define EMAC_MAC_ADDRESS2_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK)
#define EMAC_MAC_ADDRESS2_HIGH_SA (1 << 30) /* Bit 30: Source Address */
#define EMAC_MAC_ADDRESS2_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
/* MAC Address 2 Low (MAC_ADDRESS2_LOW) */
#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */
#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT)
-#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK)
+#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK)
/* MMC Control (MMC_CONTROL) */
#define EMAC_MMC_CONTROL_CNTRST (1 << 0) /* Bit 0: Counters Reset */
@@ -1293,27 +1293,27 @@
/* Transmit Octet Count Good Bad (TX_OCTET_COUNT_GOOD_BAD) */
#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good Bad */
#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)
-#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) ((n << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
+#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
/* Transmit Packet Count Good Bad (TX_PACKET_COUNT_GOOD_BAD) */
#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good Bad */
#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)
-#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) ((n << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
+#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
/* Transmit Broadcast Packets Good (TX_BROADCAST_PACKETS_GOOD) */
#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good */
#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)
-#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) ((n << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
/* Transmit Multicast Packets Good (TX_MULTICAST_PACKETS_GOOD) */
#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good */
#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)
-#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) ((n << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
/* Transmit 64-Octet Packets Good Bad (TX_64OCTETS_PACKETS_GOOD_BAD) */
#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0) /* Bits 0-32: Transmit 64-Octet Packets Good Bad */
#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFF << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)
-#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) ((n << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
+#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) (((n) << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
/* Transmit 65 To 127 Octet Packets Good Bad
* (TX_65TO127OCTETS_PACKETS_GOOD_BAD)
@@ -1321,7 +1321,7 @@
#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0) /* Bits 0-32: Transmit 65 To 127 Octet Packets Good Bad */
#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)
-#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) ((n << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
+#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) (((n) << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
/* Transmit 128 To 255 Octet Packets Good Bad
* (TX_128TO255OCTETS_PACKETS_GOOD_BAD)
@@ -1329,7 +1329,7 @@
#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0) /* Bits 0-32: Transmit 128 To 255 Octet Packets Good Bad */
#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)
-#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) ((n << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
+#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) (((n) << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
/* Transmit 256 To 511 Octet Packets Good Bad
* (TX_256TO511OCTETS_PACKETS_GOOD_BAD)
@@ -1337,7 +1337,7 @@
#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0) /* Bits 0-32: Transmit 256 To 511 Octet Packets Good Bad */
#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)
-#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) ((n << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
+#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) (((n) << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
/* Transmit 512 To 1023 Octet Packets Good Bad
* (TX_512TO1023OCTETS_PACKETS_GOOD_BAD)
@@ -1345,7 +1345,7 @@
#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Transmit 512 To 1023 Octet Packets Good Bad */
#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)
-#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) ((n << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
+#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) (((n) << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
/* Transmit 1024 To Max Octet Packets Good Bad
* (TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)
@@ -1353,7 +1353,7 @@
#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Transmit 1024 To Max Octet Packets Good Bad */
#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)
-#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) ((n << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
+#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) (((n) << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
/* Transmit Unicast Packets Good Bad
* (TX_UNICAST_PACKETS_GOOD_BAD)
@@ -1361,22 +1361,22 @@
#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0) /* Bits 0-32: Transmit Unicast Packets Good Bad */
#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFF << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)
-#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) ((n << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
+#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) (((n) << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
/* Transmit Multicast Packets Good Bad (TX_MULTICAST_PACKETS_GOOD_BAD) */
#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good Bad */
#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)
-#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) ((n << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
/* Transmit Broadcast Packets Good Bad (TX_BROADCAST_PACKETS_GOOD_BAD) */
#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good Bad */
#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)
-#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) ((n << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
/* Transmit Underflow Error Packets (TX_UNDERFLOW_ERROR_PACKETS) */
#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0) /* Bits 0-32: Transmit Underflow Error Packets */
#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFF << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)
-#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) ((n << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
+#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) (((n) << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
/* Transmit Single Collision Good Packets
* (TX_SINGLE_COLLISION_GOOD_PACKETS)
@@ -1384,7 +1384,7 @@
#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0) /* Bits 0-32: Transmit Single Collision Good Packets */
#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFF << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)
-#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) ((n << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
+#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) (((n) << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
/* Transmit Multiple Collision Good Packets
* (TX_MULTIPLE_COLLISION_GOOD_PACKETS)
@@ -1392,117 +1392,117 @@
#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0) /* Bits 0-32: Transmit Multiple Collision Good Packets */
#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFF << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)
-#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) ((n << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
+#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) (((n) << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
/* Transmit Deferred Packets (TX_DEFERRED_PACKETS) */
#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0) /* Bits 0-32: Transmit Deferred Packets */
#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFF << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)
-#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) ((n << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
+#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) (((n) << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
/* Transmit Late Collision Packets (TX_LATE_COLLISION_PACKETS) */
#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0) /* Bits 0-32: Transmit Late Collision Packets */
#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFF << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)
-#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) ((n << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
+#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) (((n) << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
/* Transmit Excessive Collision Packets (TX_EXCESSIVE_COLLISION_PACKETS) */
#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0) /* Bits 0-32: Transmit Excessive Collision Packets */
#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)
-#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) ((n << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
+#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) (((n) << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
/* Transmit Carrier Error Packets (TX_CARRIER_ERROR_PACKETS) */
#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0) /* Bits 0-32: Transmit Carrier Error Packets */
#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFF << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)
-#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) ((n << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
+#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) (((n) << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
/* Transmit Octet Count Good (TX_OCTET_COUNT_GOOD) */
#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good */
#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)
-#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) ((n << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
+#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
/* Transmit Packet Count Good (TX_PACKET_COUNT_GOOD) */
#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good */
#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)
-#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) ((n << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
+#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
/* Transmit Excessive Deferral Error (TX_EXCESSIVE_DEFERRAL_ERROR) */
#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0) /* Bits 0-32: Transmit Excessive Deferral Error */
#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)
-#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) ((n << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
+#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) (((n) << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
/* Transmit Pause Packets (TX_PAUSE_PACKETS) */
#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0) /* Bits 0-32: Transmit Pause Packets */
#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFF << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)
-#define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) ((n << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
+#define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) (((n) << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
/* Transmit VLAN Packets Good (TX_VLAN_PACKETS_GOOD) */
#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0) /* Bits 0-32: Transmit VLAN Packets Good */
#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFF << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)
-#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) ((n << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
+#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) (((n) << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
/* Transmit O Size Packets Good (TX_OSIZE_PACKETS_GOOD) */
#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0) /* Bits 0-32: Transmit O Size Packets Good */
#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFF << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)
-#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) ((n << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
+#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) (((n) << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
/* Receive Packets Count Good Bad (RX_PACKETS_COUNT_GOOD_BAD) */
#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0) /* Bits 0-32: Receive Packets Count Good Bad */
#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFF << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)
-#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) ((n << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
+#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) (((n) << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
/* Receive Octet Count Good Bad (RX_OCTET_COUNT_GOOD_BAD) */
#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0) /* Bits 0-32: Receive Octet Count Good Bad */
#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)
-#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) ((n << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
+#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
/* Receive Octet Count Good (RX_OCTET_COUNT_GOOD) */
#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0) /* Bits 0-32: Receive Octet Count Good */
#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)
-#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) ((n << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
+#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
/* Receive Broadcast Packets Good (RX_BROADCAST_PACKETS_GOOD) */
#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0) /* Bits 0-32: Receive Broadcast Packets Good */
#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFF << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)
-#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) ((n << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
+#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) (((n) << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
/* Receive Multicast Packets Good (RX_MULTICAST_PACKETS_GOOD) */
#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0) /* Bits 0-32: Receive Multicast Packets Good */
#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFF << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)
-#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) ((n << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
+#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) (((n) << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
/* Receive CRC Error Packets (RX_CRC_ERROR_PACKETS) */
#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0) /* Bits 0-32: Receive CRC Error Packets */
#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFF << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)
-#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) ((n << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
+#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) (((n) << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
/* Receive Alignment Error Packets (RX_ALIGNMENT_ERROR_PACKETS) */
#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0) /* Bits 0-32: Receive Alignment Error Packets */
#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFF << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)
-#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) ((n << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
+#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) (((n) << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
/* Receive Runt Error Packets (RX_RUNT_ERROR_PACKETS) */
#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0) /* Bits 0-32: Receive Runt Error Packets */
#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFF << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)
-#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) ((n << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
+#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) (((n) << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
/* Receive Jabber Error Packets (RX_JABBER_ERROR_PACKETS) */
#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0) /* Bits 0-32: Receive Jabber Error Packets */
#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFF << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)
-#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) ((n << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
+#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) (((n) << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
/* Receive Undersize Packets Good (RX_UNDERSIZE_PACKETS_GOOD) */
#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0) /* Bits 0-32: Receive Undersize Packets Good */
#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFF << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)
-#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) ((n << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
+#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) (((n) << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
/* Receive Oversize Packets Good (RX_OVERSIZE_PACKETS_GOOD) */
#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0) /* Bits 0-32: Receive Oversize Packets Good */
#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFF << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)
-#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) ((n << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
+#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) (((n) << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
/* Receive 64 Octets Packets Good Bad (RX_64OCTETS_PACKETS_GOOD_BAD) */
#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0) /* Bits 0-32: Receive 64 Octets Packets Good Bad */
#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFF << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)
-#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) ((n << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
+#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) (((n) << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
/* Receive 65-127 Octets Packets Good Bad
* (RX_65TO127OCTETS_PACKETS_GOOD_BAD)
@@ -1510,7 +1510,7 @@
#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0) /* Bits 0-32: Receive 65-127 Octets Packets Good Bad */
#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)
-#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) ((n << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
+#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) (((n) << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
/* Receive 128-255 Octets Packets Good Bad
* (RX_128TO255OCTETS_PACKETS_GOOD_BAD)
@@ -1518,7 +1518,7 @@
#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0) /* Bits 0-32: Receive 128-255 Octets Packets Good Bad */
#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)
-#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) ((n << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
+#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) (((n) << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
/* Receive 256-511 Octets Packets Good Bad
* (RX_256TO511OCTETS_PACKETS_GOOD_BAD)
@@ -1526,7 +1526,7 @@
#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0) /* Bits 0-32: Receive 256-511 Octets Packets Good Bad */
#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)
-#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) ((n << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
+#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) (((n) << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
/* Receive 512-1023 Octets Packets Good Bad
* (RX_512TO1023OCTETS_PACKETS_GOOD_BAD)
@@ -1534,7 +1534,7 @@
#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Receive 512-1023 Octets Packets Good Bad */
#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)
-#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) ((n << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
+#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) (((n) << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
/* Receive 1024 To Max Octets Good Bad
* (RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)
@@ -1542,52 +1542,52 @@
#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Receive 1024-Max Octets Good Bad */
#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)
-#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) ((n << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
+#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) (((n) << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
/* Receive Unicast Packets Good (RX_UNICAST_PACKETS_GOOD) */
#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0) /* Bits 0-32: Receive Unicast Packets Good */
#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFF << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)
-#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) ((n << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
+#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) (((n) << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
/* Receive Length Error Packets (RX_LENGTH_ERROR_PACKETS) */
#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0) /* Bits 0-32: Receive Length Error Packets */
#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFF << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)
-#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) ((n << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
+#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) (((n) << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
/* Receive Out of Range Type Packet (RX_OUT_OF_RANGE_TYPE_PACKETS) */
#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0) /* Bits 0-32: Receive Out of Range Type Packet */
#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFF << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)
-#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) ((n << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
+#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) (((n) << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
/* Receive Pause Packets (RX_PAUSE_PACKETS) */
#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0) /* Bits 0-32: Receive Pause Packets */
#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFF << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)
-#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) ((n << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
+#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) (((n) << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
/* Receive FIFO Overflow Packets (RX_FIFO_OVERFLOW_PACKETS) */
#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0) /* Bits 0-32: Receive FIFO Overflow Packets */
#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFF << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)
-#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) ((n << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
+#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) (((n) << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
/* Receive VLAN Packets Good Bad (RX_VLAN_PACKETS_GOOD_BAD) */
#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0) /* Bits 0-32: Receive VLAN Packets Good Bad */
#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFF << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)
-#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) ((n << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
+#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) (((n) << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
/* Receive Watchdog Error Packets (RX_WATCHDOG_ERROR_PACKETS) */
#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0) /* Bits 0-32: Receive Watchdog Error Packets */
#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFF << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)
-#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) ((n << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
+#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) (((n) << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
/* Receive Receive Error Packets (RX_RECEIVE_ERROR_PACKETS) */
#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0) /* Bits 0-32: Receive Receive Error Packets */
#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFF << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)
-#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) ((n << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
+#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) (((n) << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
/* Receive Control Packets Good (RX_CONTROL_PACKETS_GOOD) */
#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0) /* Bits 0-32: Receive Control Packets Good */
#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFF << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)
-#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) ((n << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
+#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) (((n) << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
/* MMC Transmit FPE Fragment Counter Interrupt Status
* (MMC_FPE_TX_INTERRUPT)
@@ -1603,12 +1603,12 @@
/* Transmit FPE Fragment Counter (MMC_TX_FPE_FRAGMENT_CNTR) */
#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0) /* Bits 0-32: Transmit FPE Fragment Counter */
#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFF << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)
-#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(n) ((n << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
+#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(n) (((n) << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
/* Transmit Hold Request Counter (MMC_TX_HOLD_REQ_CNTR) */
#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0) /* Bits 0-32: Transmit Hold Request Counter */
#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFF << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)
-#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(n) ((n << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
+#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(n) (((n) << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
/* MMC Receive Packet Assembly Error Counter Interrupt Status
* (MMC_FPE_RX_INTERRUPT)
@@ -1631,22 +1631,22 @@
#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0) /* Bits 0-32: Packet Assembly Error Counter */
#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)
-#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(n) ((n << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
+#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
/* MMC Receive Packet SMD Error Counter (MMC_RX_PACKET_SMD_ERR_CNTR) */
#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0) /* Bits 0-32: Packet SMD Error Counter */
#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)
-#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(n) ((n << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
+#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(n) (((n) << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
/* MMC Receive Packet Assembly OK Counter (MMC_RX_PACKET_ASSEMBLY_OK_CNTR) */
#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0) /* Bits 0-32: Packet Assembly OK Counter */
#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)
-#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(n) ((n << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
+#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
/* MMC Receive FPE Fragment Counter (MMC_RX_FPE_FRAGMENT_CNTR) */
#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0) /* Bits 0-32: FPE Fragment Counter */
#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFF << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)
-#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(n) ((n << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
+#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(n) (((n) << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
/* MAC Layer 3 Layer 4 Control 0 (MAC_L3_L4_CONTROL0) */
#define EMAC_MAC_L3_L4_CONTROL0_L3PEN0 (1 << 0) /* Bit 0: Layer 3 Protocol Enable */
@@ -1656,10 +1656,10 @@
#define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable */
#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match */
#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(n) ((n << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
+#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match */
#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(n) ((n << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
+#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
#define EMAC_MAC_L3_L4_CONTROL0_L4PEN0 (1 << 16) /* Bit 16: Layer 4 Protocol Enable */
#define EMAC_MAC_L3_L4_CONTROL0_L4SPM0 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable */
#define EMAC_MAC_L3_L4_CONTROL0_L4SPIM0 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable */
@@ -1671,30 +1671,30 @@
/* MAC Layer 4 Address 0 (MAC_LAYER4_ADDRESS0) */
#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number */
#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(n) ((n << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number */
#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(n) ((n << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
/* MAC Layer 3 Address 0 Reg 0 (MAC_LAYER3_ADDR0_REG0) */
#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
+#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
/* MAC Layer 3 Address 1 Reg 0 (MAC_LAYER3_ADDR1_REG0) */
#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
+#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
/* MAC Layer 3 Address 2 Reg 0 (MAC_LAYER3_ADDR2_REG0) */
#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
+#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
/* MAC Layer 3 Address 3 Reg 0 (MAC_LAYER3_ADDR3_REG0) */
#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
+#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
/* MAC L3 L4 Control 1 (MAC_L3_L4_CONTROL1) */
#define EMAC_MAC_L3_L4_CONTROL1_L3PEN1 (1 << 0) /* Bit 0: Layer 3 Protocol Enable 1 */
@@ -1704,10 +1704,10 @@
#define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(n) ((n << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
+#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(n) ((n << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
+#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
#define EMAC_MAC_L3_L4_CONTROL1_L4PEN1 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L4SPM1 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L4SPIM1 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable 1 */
@@ -1719,30 +1719,30 @@
/* MAC Layer 4 Address 1 (MAC_LAYER4_ADDRESS1) */
#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 1 */
#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(n) ((n << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 1 */
#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(n) ((n << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
/* MAC Layer 3 Address 0 Reg 1 (MAC_LAYER3_ADDR0_REG1) */
#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
+#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
/* MAC Layer 3 Address 1 Reg 1 (MAC_LAYER3_ADDR1_REG1) */
#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
+#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
/* MAC Layer 3 Address 2 Reg 1 (MAC_LAYER3_ADDR2_REG1) */
#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
+#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
/* MAC Layer 3 Address 3 Reg 1 (MAC_LAYER3_ADDR3_REG1) */
#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
+#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
/* MAC L3 L4 Control 2 (MAC_L3_L4_CONTROL2) */
#define EMAC_MAC_L3_L4_CONTROL2_L3PEN2 (1 << 0) /* Bit 0: Layer 3 Protocol Enable 2 */
@@ -1752,10 +1752,10 @@
#define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(n) ((n << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
+#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(n) ((n << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
+#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
#define EMAC_MAC_L3_L4_CONTROL2_L4PEN2 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L4SPM2 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L4SPIM2 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable 2 */
@@ -1767,30 +1767,30 @@
/* MAC Layer 4 Address 2 (MAC_LAYER4_ADDRESS2) */
#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 2 */
#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(n) ((n << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 2 */
#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(n) ((n << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
/* MAC Layer 3 Address 0 Reg 2 (MAC_LAYER3_ADDR0_REG2) */
#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
+#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
/* MAC Layer 3 Address 1 Reg 2 (MAC_LAYER3_ADDR1_REG2) */
#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
+#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
/* MAC Layer 3 Address 2 Reg 2 (MAC_LAYER3_ADDR2_REG2) */
#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
+#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
/* MAC Layer 3 Address 3 Reg 2 (MAC_LAYER3_ADDR3_REG2) */
#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
+#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
/* MAC L3 L4 Control 3 (MAC_L3_L4_CONTROL3) */
#define EMAC_MAC_L3_L4_CONTROL3_L3PEN3 (1 << 0) /* Bit 0: Layer 3 Protocol Enable 3 */
@@ -1800,10 +1800,10 @@
#define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(n) ((n << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
+#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)
-#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(n) ((n << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
+#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
#define EMAC_MAC_L3_L4_CONTROL3_L4PEN3 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L4SPM3 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L4SPIM3 (1 << 19) /* Bit 19: Layer 4 Source Port Inverse Match Enable 3 */
@@ -1815,30 +1815,30 @@
/* MAC Layer 4 Address 3 (MAC_LAYER4_ADDRESS3) */
#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 3 */
#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(n) ((n << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 3 */
#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)
-#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(n) ((n << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
+#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
/* MAC Layer 3 Address 0 Reg 3 (MAC_LAYER3_ADDR0_REG3) */
#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(n) ((n << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
+#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
/* MAC Layer 3 Address 1 Reg 3 (MAC_LAYER3_ADDR1_REG3) */
#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(n) ((n << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
+#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
/* MAC Layer 3 Address 2 Reg 3 (MAC_LAYER3_ADDR2_REG3) */
#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(n) ((n << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
+#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
/* MAC Layer 3 Address 3 Reg 3 (MAC_LAYER3_ADDR3_REG3) */
#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)
-#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(n) ((n << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
+#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
/* MAC Timestamp Control (MAC_TIMESTAMP_CONTROL) */
#define EMAC_MAC_TIMESTAMP_CONTROL_TSENA (1 << 0) /* Bit 0: Timestamp Enable */
@@ -1857,7 +1857,7 @@
#define EMAC_MAC_TIMESTAMP_CONTROL_TSMSTRENA (1 << 15) /* Bit 15: Enable Snapshot For Messages Relevant To Master */
#define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16) /* Bits 16-18: Select PTP Packets For Taking Snapshots */
#define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x3 << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)
-#define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(n) ((n << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) & EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
+#define EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(n) (((n) << EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT) & EMAC_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
#define EMAC_MAC_TIMESTAMP_CONTROL_TSENMACADDR (1 << 18) /* Bit 18: Enable MAC Address For PTP Packet Filtering */
#define EMAC_MAC_TIMESTAMP_CONTROL_ESTI (1 << 20) /* Bit 20: External System Time Input */
#define EMAC_MAC_TIMESTAMP_CONTROL_TXTSSTSM (1 << 24) /* Bit 24: Transmit Timestamp Status Mode */
@@ -1866,36 +1866,36 @@
/* MAC Sub Second Increment (MAC_SUB_SECOND_INCREMENT) */
#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8) /* Bits 8-16: Sub-Nanosecond Increment Value */
#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)
-#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(n) ((n << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
+#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16) /* Bits 16-24: Sub-Second Increment Value */
#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)
-#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(n) ((n << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
+#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
/* MAC System Time In Seconds (MAC_SYSTEM_TIME_SECONDS) */
#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0) /* Bits 0-32: Timestamp Second */
#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)
-#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(n) ((n << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
+#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
/* MAC System Time In Nanoseconds (MAC_SYSTEM_TIME_NANOSECONDS) */
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Sub Seconds */
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)
-#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(n) ((n << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
+#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
/* MAC System Time Seconds Update (MAC_SYSTEM_TIME_SECONDS_UPDATE) */
#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0) /* Bits 0-32: Timestamp Seconds */
#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)
-#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(n) ((n << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
+#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
/* MAC System Time Nanoseconds Update (MAC_SYSTEM_TIME_NANOSECONDS_UPDATE) */
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Subseconds */
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)
-#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(n) ((n << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
+#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB (1 << 31) /* Bit 31: Add Or Subtract Time */
/* MAC Timestamp Addend (MAC_TIMESTAMP_ADDEND) */
#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0) /* Bits 0-32: Timestamp Addend Register */
#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)
-#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(n) ((n << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
+#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(n) (((n) << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
/* MAC System Time Higher Word In Seconds
* (MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS)
@@ -1903,7 +1903,7 @@
#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0) /* Bits 0-16: Timestamp Higher Word Register */
#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFF << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)
-#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(n) ((n << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
+#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(n) (((n) << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
/* MAC Timestamp Status (MAC_TIMESTAMP_STATUS) */
#define EMAC_MAC_TIMESTAMP_STATUS_TSSOVF (1 << 0) /* Bit 0: Timestamp Seconds Overflow */
@@ -1923,7 +1923,7 @@
#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0) /* Bits 0-31: Transmit Timestamp Status Low */
#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)
-#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(n) ((n << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
+#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS (1 << 31) /* Bit 31: Transmit Timestamp Status Missed */
/* MAC Transmit Timestamp Status In Seconds
@@ -1932,7 +1932,7 @@
#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0) /* Bits 0-32: Transmit Timestamp Status High */
#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)
-#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(n) ((n << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
+#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
/* MAC Timestamp Ingress Asymmetry Correction
* (MAC_TIMESTAMP_INGRESS_ASYM_CORR)
@@ -1940,7 +1940,7 @@
#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Ingress Asymmetry Correction */
#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)
-#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
+#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
/* MAC Timestamp Egress Asymmetry Correction
* (MAC_TIMESTAMP_EGRESS_ASYM_CORR)
@@ -1948,7 +1948,7 @@
#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Egress Asymmetry Correction */
#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)
-#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
+#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
/* MAC Timestamp Ingress Correction In Nanoseconds
* (MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND)
@@ -1956,7 +1956,7 @@
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0) /* Bits 0-32: Timestamp Ingress Correction */
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)
-#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
+#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
/* MAC Timestamp Egress Correction In Nanoseconds
* (MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND)
@@ -1964,7 +1964,7 @@
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0) /* Bits 0-32: Timestamp Egress Correction */
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)
-#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
+#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
/* MAC Timestamp Ingress Correction In Subnanoseconds
* (MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC)
@@ -1972,7 +1972,7 @@
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8) /* Bits 8-16: Timestamp Ingress Correction In Sub-Nanoseconds */
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)
-#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
+#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
/* MAC Timestamp Engress Correction In Subnanoseconds
* (MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC)
@@ -1980,145 +1980,145 @@
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8) /* Bits 8-16: Timestamp Egress Correction In Sub-Nanoseconds */
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)
-#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
+#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
/* MAC Timestamp Ingress Latency (MAC_TIMESTAMP_INGRESS_LATENCY) */
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8) /* Bits 8-16: Ingress Timestamp Latency In Nanoseconds */
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)
-#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
+#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16) /* Bits 16-28: Ingress Timestamp Latency In Sub-Nanoseconds */
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)
-#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(n) ((n << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
+#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
/* MAC Timestamp Egress Latecy (MAC_TIMESTAMP_EGRESS_LATENCY) */
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8) /* Bits 8-16: Egress Timestamp Latency In Sub-Nanoseconds */
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)
-#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
+#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16) /* Bits 16-28: Egress Timestamp Latency In Nanoseconds */
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)
-#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(n) ((n << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
+#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
/* MAC PPS Control (MAC_PPS_CONTROL) */
#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0) /* Bits 0-4: PPS Output Frequency Control */
#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
+#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
#define EMAC_MAC_PPS_CONTROL_PPSEN0 (1 << 4) /* Bit 4: Flexible PPS Output Mode Enable 0 */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5) /* Bits 5-7: Target Time Register Mode For PPS0 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
+#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN0 (1 << 7) /* Bit 7: MCGR Mode Enable For PPS0 Output */
#define EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8) /* Bits 8-12: Flexible PPS1 Output Control */
#define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_PPSCMD1(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK)
+#define EMAC_MAC_PPS_CONTROL_PPSCMD1(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13) /* Bits 13-15: Target Time Register Mode For PPS1 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
+#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN1 (1 << 15) /* Bit 15: MCGR Mode Enable For PPS1 Output */
#define EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16) /* Bits 16-20: Flexible PPS2 Output Control */
#define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_PPSCMD2(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK)
+#define EMAC_MAC_PPS_CONTROL_PPSCMD2(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21) /* Bits 21-23: Target Time Register Mode For PPS2 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
+#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN2 (1 << 23) /* Bit 23: MCGR Mode Enable For PPS2 Output */
#define EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24) /* Bits 24-28: Flexible PPS3 Output Control */
#define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_PPSCMD3(n) ((n << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK)
+#define EMAC_MAC_PPS_CONTROL_PPSCMD3(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29) /* Bits 29-31: Target Time Register Mode For PPS3 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)
-#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(n) ((n << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
+#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN3 (1 << 31) /* Bit 31: MCGR Mode Enable For PPS3 Output */
/* MAC PPS0 Target Time In Seconds (MAC_PPS0_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds Register */
#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)
-#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(n) ((n << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
+#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
/* MAC PPS0 Target Time In Nanoseconds (MAC_PPS0_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0) /* Bits 0-31: Target Time Low For PPS0 */
#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)
-#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(n) ((n << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
+#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0 (1 << 31) /* Bit 31: PPS Target Time Busy Status 0 */
/* MAC PPS0 Interval (MAC_PPS0_INTERVAL) */
#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 0 */
#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)
-#define EMAC_MAC_PPS0_INTERVAL_PPSINT0(n) ((n << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK)
+#define EMAC_MAC_PPS0_INTERVAL_PPSINT0(n) (((n) << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK)
/* MAC PPS0 Width (MAC_PPS0_WIDTH) */
#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 0 */
#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)
-#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(n) ((n << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
+#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(n) (((n) << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
/* MAC PPS1 Target Time In Seconds (MAC_PPS1_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 1 */
#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)
-#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(n) ((n << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
+#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
/* MAC PPS1 Target Time In Nanoseconds (MAC_PPS1_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0) /* Bits 0-31: Target Time Low For PPS1 */
#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)
-#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(n) ((n << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
+#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1 (1 << 31) /* Bit 31: PPS Target Time Busy Status 1 */
/* MAC PPS1 Interval (MAC_PPS1_INTERVAL) */
#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 1 */
#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)
-#define EMAC_MAC_PPS1_INTERVAL_PPSINT1(n) ((n << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK)
+#define EMAC_MAC_PPS1_INTERVAL_PPSINT1(n) (((n) << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK)
/* MAC PPS1 Width (MAC_PPS1_WIDTH) */
#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 1 */
#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)
-#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) ((n << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
+#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) (((n) << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
/* MAC PPS2 Taget Time In Seconds (MAC_PPS2_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 2 */
#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)
-#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) ((n << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
+#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
/* MAC PPS2 Target Time In Nanoseconds (MAC_PPS2_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0) /* Bits 0-31: Target Time Low For PPS2 */
#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)
-#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(n) ((n << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
+#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2 (1 << 31) /* Bit 31: PPS Target Time Busy Status 2 */
/* MAC PPS2 Interval (MAC_PPS2_INTERVAL) */
#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 2 */
#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)
-#define EMAC_MAC_PPS2_INTERVAL_PPSINT2(n) ((n << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK)
+#define EMAC_MAC_PPS2_INTERVAL_PPSINT2(n) (((n) << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK)
/* MAC PPS2 Width (MAC_PPS2_WIDTH) */
#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 2 */
#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)
-#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(n) ((n << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
+#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(n) (((n) << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
/* MAC PPS3 Target Time In Seconds (MAC_PPS3_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 3 */
#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)
-#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(n) ((n << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
+#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
/* MAC PPS3 Target Time In Nanoseconds (MAC_PPS3_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0) /* Bits 0-31: Target Time Low For PPS3 */
#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)
-#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(n) ((n << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
+#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3 (1 << 31) /* Bit 31: PPS Target Time Register Busy 3 */
/* MAC PPS3 Interval (MAC_PPS3_INTERVAL) */
#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval */
#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)
-#define EMAC_MAC_PPS3_INTERVAL_PPSINT3(n) ((n << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK)
+#define EMAC_MAC_PPS3_INTERVAL_PPSINT3(n) (((n) << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK)
/* MAC PPS3 Width (MAC_PPS3_WIDTH) */
#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 3 */
#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)
-#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(n) ((n << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
+#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(n) (((n) << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
/* MTL Operation Mode (MTL_OPERATION_MODE) */
#define EMAC_MTL_OPERATION_MODE_DTXSTS (1 << 1) /* Bit 1: Drop Transmit Status */
#define EMAC_MTL_OPERATION_MODE_RAA (1 << 2) /* Bit 2: Receive Arbitration Algorithm */
#define EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT (5) /* Bits 5-7: Transmit Scheduling Algorithm */
#define EMAC_MTL_OPERATION_MODE_SCHALG_MASK (0x3 << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT)
-#define EMAC_MTL_OPERATION_MODE_SCHALG(n) ((n << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT) & EMAC_MTL_OPERATION_MODE_SCHALG_MASK)
+#define EMAC_MTL_OPERATION_MODE_SCHALG(n) (((n) << EMAC_MTL_OPERATION_MODE_SCHALG_SHIFT) & EMAC_MTL_OPERATION_MODE_SCHALG_MASK)
#define EMAC_MTL_OPERATION_MODE_SCHALG_WRR EMAC_MTL_OPERATION_MODE_SCHALG(0x0)
#define EMAC_MTL_OPERATION_MODE_SCHALG_WFQ EMAC_MTL_OPERATION_MODE_SCHALG(0x1)
#define EMAC_MTL_OPERATION_MODE_SCHALG_DWRR EMAC_MTL_OPERATION_MODE_SCHALG(0x2)
@@ -2132,42 +2132,42 @@
#define EMAC_MTL_DBG_CTL_DBGMOD (1 << 1) /* Bit 1: Debug Mode Access to FIFO */
#define EMAC_MTL_DBG_CTL_BYTEEN_SHIFT (2) /* Bits 2-4: Byte Enables */
#define EMAC_MTL_DBG_CTL_BYTEEN_MASK (0x3 << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT)
-#define EMAC_MTL_DBG_CTL_BYTEEN(n) ((n << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT) & EMAC_MTL_DBG_CTL_BYTEEN_MASK)
+#define EMAC_MTL_DBG_CTL_BYTEEN(n) (((n) << EMAC_MTL_DBG_CTL_BYTEEN_SHIFT) & EMAC_MTL_DBG_CTL_BYTEEN_MASK)
#define EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT (5) /* Bits 5-7: Encoded Packet State */
#define EMAC_MTL_DBG_CTL_PKTSTATE_MASK (0x3 << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT)
-#define EMAC_MTL_DBG_CTL_PKTSTATE(n) ((n << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) & EMAC_MTL_DBG_CTL_PKTSTATE_MASK)
+#define EMAC_MTL_DBG_CTL_PKTSTATE(n) (((n) << EMAC_MTL_DBG_CTL_PKTSTATE_SHIFT) & EMAC_MTL_DBG_CTL_PKTSTATE_MASK)
#define EMAC_MTL_DBG_CTL_RSTALL (1 << 8) /* Bit 8: Reset All Pointers */
#define EMAC_MTL_DBG_CTL_RSTSEL (1 << 9) /* Bit 9: Reset Pointers Of Selected FIFO */
#define EMAC_MTL_DBG_CTL_FIFORDEN (1 << 10) /* Bit 10: FIFO Read Enable */
#define EMAC_MTL_DBG_CTL_FIFOWREN (1 << 11) /* Bit 11: FIFO Write Enable */
#define EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT (12) /* Bits 12-14: FIFO Selected for Access */
#define EMAC_MTL_DBG_CTL_FIFOSEL_MASK (0x3 << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT)
-#define EMAC_MTL_DBG_CTL_FIFOSEL(n) ((n << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) & EMAC_MTL_DBG_CTL_FIFOSEL_MASK)
+#define EMAC_MTL_DBG_CTL_FIFOSEL(n) (((n) << EMAC_MTL_DBG_CTL_FIFOSEL_SHIFT) & EMAC_MTL_DBG_CTL_FIFOSEL_MASK)
#define EMAC_MTL_DBG_CTL_PKTIE (1 << 14) /* Bit 14: Receive Packet Available Interrupt Status Enable */
#define EMAC_MTL_DBG_CTL_STSIE (1 << 15) /* Bit 15: Transmit Status Available Interrupt Status Enable */
#define EMAC_MTL_DBG_CTL_EIEE (1 << 16) /* Bit 16: ECC Inject Error Enable */
#define EMAC_MTL_DBG_CTL_EIEC_SHIFT (17) /* Bits 17-19: ECC Inject Error Control */
#define EMAC_MTL_DBG_CTL_EIEC_MASK (0x3 << EMAC_MTL_DBG_CTL_EIEC_SHIFT)
-#define EMAC_MTL_DBG_CTL_EIEC(n) ((n << EMAC_MTL_DBG_CTL_EIEC_SHIFT) & EMAC_MTL_DBG_CTL_EIEC_MASK)
+#define EMAC_MTL_DBG_CTL_EIEC(n) (((n) << EMAC_MTL_DBG_CTL_EIEC_SHIFT) & EMAC_MTL_DBG_CTL_EIEC_MASK)
/* MTL Debug Status (MTL_DBG_STS) */
#define EMAC_MTL_DBG_STS_FIFOBUSY (1 << 0) /* Bit 0: FIFO Busy */
#define EMAC_MTL_DBG_STS_PKTSTATE_SHIFT (1) /* Bits 1-3: Encoded Packet State */
#define EMAC_MTL_DBG_STS_PKTSTATE_MASK (0x3 << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT)
-#define EMAC_MTL_DBG_STS_PKTSTATE(n) ((n << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT) & EMAC_MTL_DBG_STS_PKTSTATE_MASK)
+#define EMAC_MTL_DBG_STS_PKTSTATE(n) (((n) << EMAC_MTL_DBG_STS_PKTSTATE_SHIFT) & EMAC_MTL_DBG_STS_PKTSTATE_MASK)
#define EMAC_MTL_DBG_STS_BYTEEN_SHIFT (3) /* Bits 3-5: Byte Enables */
#define EMAC_MTL_DBG_STS_BYTEEN_MASK (0x3 << EMAC_MTL_DBG_STS_BYTEEN_SHIFT)
-#define EMAC_MTL_DBG_STS_BYTEEN(n) ((n << EMAC_MTL_DBG_STS_BYTEEN_SHIFT) & EMAC_MTL_DBG_STS_BYTEEN_MASK)
+#define EMAC_MTL_DBG_STS_BYTEEN(n) (((n) << EMAC_MTL_DBG_STS_BYTEEN_SHIFT) & EMAC_MTL_DBG_STS_BYTEEN_MASK)
#define EMAC_MTL_DBG_STS_PKTI (1 << 8) /* Bit 8: Receive Packet Available Interrupt Status */
#define EMAC_MTL_DBG_STS_STSI (1 << 9) /* Bit 9: Transmit Status Available Interrupt Status */
#define EMAC_MTL_DBG_STS_LOCR_SHIFT (15) /* Bits 15-32: Remaining Locations In FIFO */
#define EMAC_MTL_DBG_STS_LOCR_MASK (0x1FFFF << EMAC_MTL_DBG_STS_LOCR_SHIFT)
-#define EMAC_MTL_DBG_STS_LOCR(n) ((n << EMAC_MTL_DBG_STS_LOCR_SHIFT) & EMAC_MTL_DBG_STS_LOCR_MASK)
+#define EMAC_MTL_DBG_STS_LOCR(n) (((n) << EMAC_MTL_DBG_STS_LOCR_SHIFT) & EMAC_MTL_DBG_STS_LOCR_MASK)
/* MTL FIFO Debug Data (MTL_FIFO_DEBUG_DATA) */
#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0) /* Bits 0-32: FIFO Debug Data */
#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFF << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)
-#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(n) ((n << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
+#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(n) (((n) << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
/* MTL Interrupt Status (MTL_INTERRUPT_STATUS) */
#define EMAC_MTL_INTERRUPT_STATUS_Q0IS (1 << 0) /* Bit 0: Queue 0 Interrupt Status */
@@ -2187,10 +2187,10 @@
#define EMAC_MTL_TBS_CTRL_LEOV (1 << 1) /* Bit 1: Launch Expiry Offset Valid */
#define EMAC_MTL_TBS_CTRL_LEGOS_SHIFT (4) /* Bits 4-7: Launch Expiry GSN Offset */
#define EMAC_MTL_TBS_CTRL_LEGOS_MASK (0x7 << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT)
-#define EMAC_MTL_TBS_CTRL_LEGOS(n) ((n << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEGOS_MASK)
+#define EMAC_MTL_TBS_CTRL_LEGOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEGOS_MASK)
#define EMAC_MTL_TBS_CTRL_LEOS_SHIFT (8) /* Bits 8-32: Launch Expiry Offset */
#define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF << EMAC_MTL_TBS_CTRL_LEOS_SHIFT)
-#define EMAC_MTL_TBS_CTRL_LEOS(n) ((n << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEOS_MASK)
+#define EMAC_MTL_TBS_CTRL_LEOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEOS_MASK)
/* MTL EST Control (MTL_EST_CONTROL) */
#define EMAC_MTL_EST_CONTROL_EEST (1 << 0) /* Bit 0: Enable EST */
@@ -2199,16 +2199,16 @@
#define EMAC_MTL_EST_CONTROL_DFBS (1 << 5) /* Bit 5: Drop Frames Causing Scheduling Error */
#define EMAC_MTL_EST_CONTROL_LCSE_SHIFT (6) /* Bits 6-8: Loop Count to Report Scheduling Error */
#define EMAC_MTL_EST_CONTROL_LCSE_MASK (0x3 << EMAC_MTL_EST_CONTROL_LCSE_SHIFT)
-#define EMAC_MTL_EST_CONTROL_LCSE(n) ((n << EMAC_MTL_EST_CONTROL_LCSE_SHIFT) & EMAC_MTL_EST_CONTROL_LCSE_MASK)
+#define EMAC_MTL_EST_CONTROL_LCSE(n) (((n) << EMAC_MTL_EST_CONTROL_LCSE_SHIFT) & EMAC_MTL_EST_CONTROL_LCSE_MASK)
#define EMAC_MTL_EST_CONTROL_TILS_SHIFT (8) /* Bits 8-11: Time Interval Left Shift Amount */
#define EMAC_MTL_EST_CONTROL_TILS_MASK (0x7 << EMAC_MTL_EST_CONTROL_TILS_SHIFT)
-#define EMAC_MTL_EST_CONTROL_TILS(n) ((n << EMAC_MTL_EST_CONTROL_TILS_SHIFT) & EMAC_MTL_EST_CONTROL_TILS_MASK)
+#define EMAC_MTL_EST_CONTROL_TILS(n) (((n) << EMAC_MTL_EST_CONTROL_TILS_SHIFT) & EMAC_MTL_EST_CONTROL_TILS_MASK)
#define EMAC_MTL_EST_CONTROL_CTOV_SHIFT (12) /* Bits 12-24: Current Time Offset Value */
#define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xFFF << EMAC_MTL_EST_CONTROL_CTOV_SHIFT)
-#define EMAC_MTL_EST_CONTROL_CTOV(n) ((n << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) & EMAC_MTL_EST_CONTROL_CTOV_MASK)
+#define EMAC_MTL_EST_CONTROL_CTOV(n) (((n) << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) & EMAC_MTL_EST_CONTROL_CTOV_MASK)
#define EMAC_MTL_EST_CONTROL_PTOV_SHIFT (24) /* Bits 24-32: PTP Time Offset Value */
#define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xFF << EMAC_MTL_EST_CONTROL_PTOV_SHIFT)
-#define EMAC_MTL_EST_CONTROL_PTOV(n) ((n << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) & EMAC_MTL_EST_CONTROL_PTOV_MASK)
+#define EMAC_MTL_EST_CONTROL_PTOV(n) (((n) << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) & EMAC_MTL_EST_CONTROL_PTOV_MASK)
/* MTL EST Status (MTL_EST_STATUS) */
#define EMAC_MTL_EST_STATUS_SWLC (1 << 0) /* Bit 0: Switch to Software Owned List Complete */
@@ -2217,27 +2217,27 @@
#define EMAC_MTL_EST_STATUS_HLBS (1 << 3) /* Bit 3: Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL */
#define EMAC_MTL_EST_STATUS_CGCE (1 << 4) /* Bit 4: Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting */
#define EMAC_MTL_EST_STATUS_SWOL (1 << 7) /* Bit 7: S/W owned list When '0' indicates Gate control list number "0" is owned by software and when "1" indicates the Gate Control list "1" is owned by the software */
-#define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8) /* Bits 8-12: BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true */
+#define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8) /* Bits 8-12: BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + ((n) * New Cycle Time) becomes true */
#define EMAC_MTL_EST_STATUS_BTRL_MASK (0xF << EMAC_MTL_EST_STATUS_BTRL_SHIFT)
-#define EMAC_MTL_EST_STATUS_BTRL(n) ((n << EMAC_MTL_EST_STATUS_BTRL_SHIFT) & EMAC_MTL_EST_STATUS_BTRL_MASK)
+#define EMAC_MTL_EST_STATUS_BTRL(n) (((n) << EMAC_MTL_EST_STATUS_BTRL_SHIFT) & EMAC_MTL_EST_STATUS_BTRL_MASK)
#define EMAC_MTL_EST_STATUS_CGSN_SHIFT (16) /* Bits 16-20: Current GCL Slot Number Indicates the slot number of the GCL list */
#define EMAC_MTL_EST_STATUS_CGSN_MASK (0xF << EMAC_MTL_EST_STATUS_CGSN_SHIFT)
-#define EMAC_MTL_EST_STATUS_CGSN(n) ((n << EMAC_MTL_EST_STATUS_CGSN_SHIFT) & EMAC_MTL_EST_STATUS_CGSN_MASK)
+#define EMAC_MTL_EST_STATUS_CGSN(n) (((n) << EMAC_MTL_EST_STATUS_CGSN_SHIFT) & EMAC_MTL_EST_STATUS_CGSN_MASK)
/* MTL EST Scheduling Error (MTL_EST_SCH_ERROR) */
#define EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT (0) /* Bits 0-2: Schedule Error Queue Number */
#define EMAC_MTL_EST_SCH_ERROR_SEQN_MASK (0x3 << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT)
-#define EMAC_MTL_EST_SCH_ERROR_SEQN(n) ((n << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT) & EMAC_MTL_EST_SCH_ERROR_SEQN_MASK)
+#define EMAC_MTL_EST_SCH_ERROR_SEQN(n) (((n) << EMAC_MTL_EST_SCH_ERROR_SEQN_SHIFT) & EMAC_MTL_EST_SCH_ERROR_SEQN_MASK)
/* MTL EST Frame Size Error (MTL_EST_FRM_SIZE_ERROR) */
#define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0) /* Bits 0-2: Frame Size Error Queue Number */
#define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x3 << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)
-#define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(n) ((n << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT) & EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
+#define EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN(n) (((n) << EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT) & EMAC_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
/* MTL EST Frame Size Capture (MTL_EST_FRM_SIZE_CAPTURE) */
#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0) /* Bits 0-15: Frame Size of HLBF */
#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFF << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)
-#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(n) ((n << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
+#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(n) (((n) << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ (1 << 16) /* Bit 16: Queue Number of HLBF */
/* MTL EST Interrupt Enable (MTL_EST_INTR_ENABLE) */
@@ -2255,43 +2255,43 @@
#define EMAC_MTL_EST_GCL_CONTROL_DBGB (1 << 5) /* Bit 5: Debug Mode Bank Select */
#define EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8) /* Bits 8-16: Gate Control List Address: (GCLA when GCRR is "0") */
#define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xFF << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT)
-#define EMAC_MTL_EST_GCL_CONTROL_ADDR(n) ((n << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK)
+#define EMAC_MTL_EST_GCL_CONTROL_ADDR(n) (((n) << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK)
#define EMAC_MTL_EST_GCL_CONTROL_ERR0 (1 << 20) /* Bit 20: If this field is 1, it indicates that when the software writes to GCL the last write operation was aborted and when MTL_EST_Control[SSWL] is 1, GCL registers are prohibited */
#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE (1 << 21) /* Bit 21: EST ECC Inject Error Enable */
#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22) /* Bits 22-24: ECC Inject Error Control for EST Memory */
#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0x3 << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)
-#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(n) ((n << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
+#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEC(n) (((n) << EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
/* MTL EST GCL Data (MTL_EST_GCL_DATA) */
#define EMAC_MTL_EST_GCL_DATA_GCD_SHIFT (0) /* Bits 0-32: Gate Control Data */
#define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFF << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT)
-#define EMAC_MTL_EST_GCL_DATA_GCD(n) ((n << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) & EMAC_MTL_EST_GCL_DATA_GCD_MASK)
+#define EMAC_MTL_EST_GCL_DATA_GCD(n) (((n) << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) & EMAC_MTL_EST_GCL_DATA_GCD_MASK)
/* MTL FPE Control Status (MTL_FPE_CTRL_STS) */
#define EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0) /* Bits 0-2: Additional Fragment Size */
#define EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3 << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT)
-#define EMAC_MTL_FPE_CTRL_STS_AFSZ(n) ((n << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT) & EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK)
+#define EMAC_MTL_FPE_CTRL_STS_AFSZ(n) (((n) << EMAC_MTL_FPE_CTRL_STS_AFSZ_SHIFT) & EMAC_MTL_FPE_CTRL_STS_AFSZ_MASK)
#define EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT (8) /* Bits 8-10: Preemption Classification */
#define EMAC_MTL_FPE_CTRL_STS_PEC_MASK (0x3 << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT)
-#define EMAC_MTL_FPE_CTRL_STS_PEC(n) ((n << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT) & EMAC_MTL_FPE_CTRL_STS_PEC_MASK)
+#define EMAC_MTL_FPE_CTRL_STS_PEC(n) (((n) << EMAC_MTL_FPE_CTRL_STS_PEC_SHIFT) & EMAC_MTL_FPE_CTRL_STS_PEC_MASK)
#define EMAC_MTL_FPE_CTRL_STS_HRS (1 << 28) /* Bit 28: Hold/Release Status */
/* MTL FPE Advance (MTL_FPE_ADVANCE) */
#define EMAC_MTL_FPE_ADVANCE_HADV_SHIFT (0) /* Bits 0-16: Hold Advance */
#define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT)
-#define EMAC_MTL_FPE_ADVANCE_HADV(n) ((n << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_HADV_MASK)
+#define EMAC_MTL_FPE_ADVANCE_HADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_HADV_MASK)
#define EMAC_MTL_FPE_ADVANCE_RADV_SHIFT (16) /* Bits 16-32: Release Advance */
#define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT)
-#define EMAC_MTL_FPE_ADVANCE_RADV(n) ((n << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_RADV_MASK)
+#define EMAC_MTL_FPE_ADVANCE_RADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_RADV_MASK)
/* MTL Rx Parser Control Status (MTL_RXP_CONTROL_STATUS) */
#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0) /* Bits 0-6: Number Of Valid Entry Address Or Index In The Instruction Table */
#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)
-#define EMAC_MTL_RXP_CONTROL_STATUS_NVE(n) ((n << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK)
+#define EMAC_MTL_RXP_CONTROL_STATUS_NVE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK)
#define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1 (1 << 15) /* Bit 15: MTL_SCS1 */
#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16) /* Bits 16-22: Number of parsable entries in the Instruction table */
#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)
-#define EMAC_MTL_RXP_CONTROL_STATUS_NPE(n) ((n << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK)
+#define EMAC_MTL_RXP_CONTROL_STATUS_NPE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK)
#define EMAC_MTL_RXP_CONTROL_STATUS_RXPI (1 << 31) /* Bit 31: RX Parser in Idle State */
/* MTL Rx Parser Interrupt Control Status
@@ -2310,13 +2310,13 @@
/* MTL Rx Parser Drop Count (MTL_RXP_DROP_CNT) */
#define EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0) /* Bits 0-31: Rx Parser Drop Count */
#define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT)
-#define EMAC_MTL_RXP_DROP_CNT_RXPDC(n) ((n << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK)
+#define EMAC_MTL_RXP_DROP_CNT_RXPDC(n) (((n) << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK)
#define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF (1 << 31) /* Bit 31: Rx Parser Drop Counter Overflow Bit */
/* MTL Rx Parser Error Count (MTL_RXP_ERROR_CNT) */
#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0) /* Bits 0-31: Rx Parser Error Count */
#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)
-#define EMAC_MTL_RXP_ERROR_CNT_RXPEC(n) ((n << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK)
+#define EMAC_MTL_RXP_ERROR_CNT_RXPEC(n) (((n) << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK)
#define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF (1 << 31) /* Bit 31: Rx Parser Error Counter Overflow Bit */
/* MTL Rx Parser Indirect Access Control Status
@@ -2325,18 +2325,18 @@
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0) /* Bits 0-8: FRP Instruction Table Offset Address */
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xFF << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)
-#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(n) ((n << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
+#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN (1 << 16) /* Bit 16: Read Write Control */
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE (1 << 20) /* Bit 20: ECC Inject Error Enable for Rx Parser Memory */
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT (21) /* Bits 21-23: ECC Inject Error Control for Rx Parser Memory */
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK (0x3 << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT)
-#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(n) ((n << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK)
+#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEC_MASK)
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY (1 << 31) /* Bit 31: FRP Instruction Table Access Busy */
/* MTL Rx Parser Indirect Access Data (MTL_RXP_INDIRECT_ACC_DATA) */
#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0) /* Bits 0-32: FRP Instruction Table Write/Read Data */
#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFF << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)
-#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(n) ((n << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
+#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
/* MTL ECC Control (MTL_ECC_CONTROL) */
#define EMAC_MTL_ECC_CONTROL_MTXEE (1 << 0) /* Bit 0: MTL Tx FIFO ECC Enable */
@@ -2373,25 +2373,25 @@
#define EMAC_MTL_ECC_ERR_STS_RCTL_EESRE (1 << 0) /* Bit 0: MTL ECC Error Status Read Enable */
#define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT (1) /* Bits 1-4: MTL ECC Memory Selection */
#define EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK (0x7 << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT)
-#define EMAC_MTL_ECC_ERR_STS_RCTL_EMS(n) ((n << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT) & EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK)
+#define EMAC_MTL_ECC_ERR_STS_RCTL_EMS(n) (((n) << EMAC_MTL_ECC_ERR_STS_RCTL_EMS_SHIFT) & EMAC_MTL_ECC_ERR_STS_RCTL_EMS_MASK)
#define EMAC_MTL_ECC_ERR_STS_RCTL_CCES (1 << 4) /* Bit 4: Clear Correctable Error Status */
#define EMAC_MTL_ECC_ERR_STS_RCTL_CUES (1 << 5) /* Bit 5: Clear Uncorrectable Error Status */
/* MTL ECC Error Adress Status (MTL_ECC_ERR_ADDR_STATUS) */
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT (0) /* Bits 0-16: MTL ECC Correctable Error Address Status */
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT)
-#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) ((n << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK)
+#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK)
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT (16) /* Bits 16-32: MTL ECC Uncorrectable Error Address Status */
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT)
-#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(n) ((n << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK)
+#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK)
/* MTL ECC Error Control Status (MTL_ECC_ERR_CNTR_STATUS) */
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT (0) /* Bits 0-8: MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's correctable error count value */
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xFF << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT)
-#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(n) ((n << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK)
+#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK)
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT (16) /* Bits 16-20: MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's uncorrectable error count value */
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xF << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT)
-#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(n) ((n << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK)
+#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK)
/* MTL DPP Control (MTL_DPP_CONTROL) */
#define EMAC_MTL_DPP_CONTROL_EDPP (1 << 0) /* Bit 0: Enable Data path Parity Protection */
@@ -2409,47 +2409,47 @@
#define EMAC_MTL_TXQ0_OPERATION_MODE_TSF (1 << 1) /* Bit 1: Transmit Store and Forward */
#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT (2) /* Bits 2-4: Transmit Queue Enable */
#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK (0x3 << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT)
-#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(n) ((n << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK)
+#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_DISABLE EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(0)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_AVB EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(0x1)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN_DCB_GEN EMAC_MTL_TXQ0_OPERATION_MODE_TXQEN(0x2)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT (4) /* Bits 4-7: Transmit Threshold Control */
#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT)
-#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(n) ((n << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK)
+#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */
#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT)
-#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(n) ((n << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK)
+#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK)
/* MTL Tx Queue 0 Underflow (MTL_TXQ0_UNDERFLOW) */
#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */
#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT)
-#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(n) ((n << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK)
+#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK)
#define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */
/* MTL Tx Queue 0 Debug (MTL_TXQ0_DEBUG) */
#define EMAC_MTL_TXQ0_DEBUG_TXQPAUSED (1 << 0) /* Bit 0: Transmit Queue in Pause */
#define EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT (1) /* Bits 1-3: MTL Tx Queue Read Controller Status */
#define EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK (0x3 << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT)
-#define EMAC_MTL_TXQ0_DEBUG_TRCSTS(n) ((n << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK)
+#define EMAC_MTL_TXQ0_DEBUG_TRCSTS(n) (((n) << EMAC_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ0_DEBUG_TRCSTS_MASK)
#define EMAC_MTL_TXQ0_DEBUG_TWCSTS (1 << 3) /* Bit 3: MTL Tx Queue Write Controller Status */
#define EMAC_MTL_TXQ0_DEBUG_TXQSTS (1 << 4) /* Bit 4: MTL Tx Queue Not Empty Status */
#define EMAC_MTL_TXQ0_DEBUG_TXSTSFSTS (1 << 5) /* Bit 5: MTL Tx Status FIFO Full Status */
#define EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT (16) /* Bits 16-19: Number of Packets in the Transmit Queue */
#define EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK (0x7 << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT)
-#define EMAC_MTL_TXQ0_DEBUG_PTXQ(n) ((n << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK)
+#define EMAC_MTL_TXQ0_DEBUG_PTXQ(n) (((n) << EMAC_MTL_TXQ0_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ0_DEBUG_PTXQ_MASK)
#define EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT (20) /* Bits 20-23: Number of Status Words in Tx Status FIFO of Queue */
#define EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK (0x7 << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT)
-#define EMAC_MTL_TXQ0_DEBUG_STXSTSF(n) ((n << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK)
+#define EMAC_MTL_TXQ0_DEBUG_STXSTSF(n) (((n) << EMAC_MTL_TXQ0_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ0_DEBUG_STXSTSF_MASK)
/* MTL Tx Queue 0 ETS Status (MTL_TXQ0_ETS_STATUS) */
#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */
#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT)
-#define EMAC_MTL_TXQ0_ETS_STATUS_ABS(n) ((n << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK)
+#define EMAC_MTL_TXQ0_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK)
/* MTL Tx Queue Quantum Weight (MTL_TXQ0_QUANTUM_WEIGHT) */
#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: Quantum or Weights */
#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT)
-#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(n) ((n << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK)
+#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK)
/* MTL Queue 0 Interrupt Control Status (MTL_Q0_INTERRUPT_CONTROL_STATUS) */
#define EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_TXUNFIS (1 << 0) /* Bit 0: Transmit Queue Underflow Interrupt Status */
@@ -2462,7 +2462,7 @@
/* MTL Rx Queue 0 Operation Mode (MTL_RXQ0_OPERATION_MODE) */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT (0) /* Bits 0-2: Receive Queue Threshold Control */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK (0x3 << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT)
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RTC(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RTC_MASK)
#define EMAC_MTL_RXQ0_OPERATION_MODE_FUP (1 << 3) /* Bit 3: Forward Undersized Good Packets */
#define EMAC_MTL_RXQ0_OPERATION_MODE_FEP (1 << 4) /* Bit 4: Forward Error Packets */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RSF (1 << 5) /* Bit 5: Receive Queue Store and Forward */
@@ -2470,13 +2470,13 @@
#define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex) */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT)
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT)
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(n) ((n << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK)
/* MTL Rx Queue Missed Packet Overflow Count
* (MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT)
@@ -2484,29 +2484,29 @@
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)
-#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) ((n << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK)
+#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK)
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)
-#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) ((n << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK)
+#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK)
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */
/* MTL Rx Queue 0 Debug (MTL_RXQ0_DEBUG) */
#define EMAC_MTL_RXQ0_DEBUG_RWCSTS (1 << 0) /* Bit 0: MTL Rx Queue Write Controller Active Status */
#define EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT (1) /* Bits 1-3: MTL Rx Queue Read Controller State */
#define EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK (0x3 << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT)
-#define EMAC_MTL_RXQ0_DEBUG_RRCSTS(n) ((n << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK)
+#define EMAC_MTL_RXQ0_DEBUG_RRCSTS(n) (((n) << EMAC_MTL_RXQ0_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RRCSTS_MASK)
#define EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT (4) /* Bits 4-6: MTL Rx Queue Fill-Level Status */
#define EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT)
-#define EMAC_MTL_RXQ0_DEBUG_RXQSTS(n) ((n << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK)
+#define EMAC_MTL_RXQ0_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK)
#define EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */
#define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT)
-#define EMAC_MTL_RXQ0_DEBUG_PRXQ(n) ((n << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK)
+#define EMAC_MTL_RXQ0_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK)
/* MTL Rx Queue 0 Control 0 (MTL_RXQ0_CONTROL) */
#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT (0) /* Bits 0-3: Receive Queue Weight */
#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK (0x7 << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT)
-#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(n) ((n << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK)
+#define EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT(n) (((n) << EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ0_CONTROL_RXQ_WEGT_MASK)
#define EMAC_MTL_RXQ0_CONTROL_RXQ_FRM_ARBIT (1 << 3) /* Bit 3: Receive Queue Packet Arbitration */
/* MTL Tx Queue 1 Operation Mode (MTL_TXQ1_OPERATION_MODE) */
@@ -2514,66 +2514,66 @@
#define EMAC_MTL_TXQ1_OPERATION_MODE_TSF (1 << 1) /* Bit 1: Transmit Store and Forward */
#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT (2) /* Bits 2-4: Transmit Queue Enable */
#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK (0x3 << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT)
-#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(n) ((n << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK)
+#define EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TXQEN_MASK)
#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT (4) /* Bits 4-7: Transmit Threshold Control */
#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT)
-#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(n) ((n << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK)
+#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK)
#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */
#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT)
-#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(n) ((n << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK)
+#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK)
/* MTL Tx Queue 1 Underflow (MTL_TXQ1_UNDERFLOW) */
#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */
#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT)
-#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(n) ((n << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK)
+#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK)
#define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */
/* MTL Tx Queue 1 Debug (MTL_TXQ1_DEBUG) */
#define EMAC_MTL_TXQ1_DEBUG_TXQPAUSED (1 << 0) /* Bit 0: Transmit Queue in Pause */
#define EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT (1) /* Bits 1-3: MTL Tx Queue Read Controller Status */
#define EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK (0x3 << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT)
-#define EMAC_MTL_TXQ1_DEBUG_TRCSTS(n) ((n << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK)
+#define EMAC_MTL_TXQ1_DEBUG_TRCSTS(n) (((n) << EMAC_MTL_TXQ1_DEBUG_TRCSTS_SHIFT) & EMAC_MTL_TXQ1_DEBUG_TRCSTS_MASK)
#define EMAC_MTL_TXQ1_DEBUG_TWCSTS (1 << 3) /* Bit 3: MTL Tx Queue Write Controller Status */
#define EMAC_MTL_TXQ1_DEBUG_TXQSTS (1 << 4) /* Bit 4: MTL Tx Queue Not Empty Status */
#define EMAC_MTL_TXQ1_DEBUG_TXSTSFSTS (1 << 5) /* Bit 5: MTL Tx Status FIFO Full Status */
#define EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT (16) /* Bits 16-19: Number of Packets in the Transmit Queue */
#define EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK (0x7 << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT)
-#define EMAC_MTL_TXQ1_DEBUG_PTXQ(n) ((n << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK)
+#define EMAC_MTL_TXQ1_DEBUG_PTXQ(n) (((n) << EMAC_MTL_TXQ1_DEBUG_PTXQ_SHIFT) & EMAC_MTL_TXQ1_DEBUG_PTXQ_MASK)
#define EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT (20) /* Bits 20-23: Number of Status Words in Tx Status FIFO of Queue */
#define EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK (0x7 << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT)
-#define EMAC_MTL_TXQ1_DEBUG_STXSTSF(n) ((n << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK)
+#define EMAC_MTL_TXQ1_DEBUG_STXSTSF(n) (((n) << EMAC_MTL_TXQ1_DEBUG_STXSTSF_SHIFT) & EMAC_MTL_TXQ1_DEBUG_STXSTSF_MASK)
/* MTL Tx Queue 1 ETS Control (MTL_TXQ1_ETS_CONTROL) */
#define EMAC_MTL_TXQ1_ETS_CONTROL_AVALG (1 << 2) /* Bit 2: AV Algorithm */
#define EMAC_MTL_TXQ1_ETS_CONTROL_CC (1 << 3) /* Bit 3: Credit Control */
#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT (4) /* Bits 4-7: Slot Count */
#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK (0x7 << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT)
-#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC(n) ((n << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT) & EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK)
+#define EMAC_MTL_TXQ1_ETS_CONTROL_SLC(n) (((n) << EMAC_MTL_TXQ1_ETS_CONTROL_SLC_SHIFT) & EMAC_MTL_TXQ1_ETS_CONTROL_SLC_MASK)
/* MTL Tx Queue 1 ETS Status (MTL_TXQ1_ETS_STATUS) */
#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */
#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT)
-#define EMAC_MTL_TXQ1_ETS_STATUS_ABS(n) ((n << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK)
+#define EMAC_MTL_TXQ1_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK)
/* MTL Tx Queue 1 Quantum Weight (MTL_TXQ1_QUANTUM_WEIGHT) */
#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: idleSlopeCredit, Quantum or Weights */
#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT)
-#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(n) ((n << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK)
+#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK)
/* MTL Tx Queue 1 Sendslope Credit (MTL_TXQ1_SENDSLOPECREDIT) */
#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT (0) /* Bits 0-14: sendSlopeCredit Value */
#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3FFF << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT)
-#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(n) ((n << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK)
+#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(n) (((n) << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK)
/* MTL Tx Queue 1 HiCredit (MTL_TXQ1_HICREDIT) */
#define EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT (0) /* Bits 0-29: hiCredit Value */
#define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT)
-#define EMAC_MTL_TXQ1_HICREDIT_HC(n) ((n << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK)
+#define EMAC_MTL_TXQ1_HICREDIT_HC(n) (((n) << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK)
/* MTL Tx Queue 1 LoCredit (MTL_TXQ1_LOCREDIT) */
#define EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT (0) /* Bits 0-29: loCredit Value */
#define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT)
-#define EMAC_MTL_TXQ1_LOCREDIT_LC(n) ((n << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK)
+#define EMAC_MTL_TXQ1_LOCREDIT_LC(n) (((n) << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK)
/* MTL Queue 1 Interrupt Control Status (MTL_Q1_INTERRUPT_CONTROL_STATUS) */
#define EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_TXUNFIS (1 << 0) /* Bit 0: Transmit Queue Underflow Interrupt Status */
@@ -2586,7 +2586,7 @@
/* MTL Rx Queue 1 Operation Mode (MTL_RXQ1_OPERATION_MODE) */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT (0) /* Bits 0-2: Receive Queue Threshold Control */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK (0x3 << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT)
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RTC(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RTC_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RTC_MASK)
#define EMAC_MTL_RXQ1_OPERATION_MODE_FUP (1 << 3) /* Bit 3: Forward Undersized Good Packets */
#define EMAC_MTL_RXQ1_OPERATION_MODE_FEP (1 << 4) /* Bit 4: Forward Error Packets */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RSF (1 << 5) /* Bit 5: Receive Queue Store and Forward */
@@ -2594,13 +2594,13 @@
#define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT)
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT)
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT)
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(n) ((n << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK)
/* MTL Rx Queue 1 Missed Packet Overflow Counter
* (MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT)
@@ -2608,29 +2608,29 @@
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)
-#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) ((n << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK)
+#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK)
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)
-#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) ((n << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK)
+#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK)
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */
/* MTL Rx Queue 1 Debug (MTL_RXQ1_DEBUG) */
#define EMAC_MTL_RXQ1_DEBUG_RWCSTS (1 << 0) /* Bit 0: MTL Rx Queue Write Controller Active Status */
#define EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT (1) /* Bits 1-3: MTL Rx Queue Read Controller State */
#define EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK (0x3 << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT)
-#define EMAC_MTL_RXQ1_DEBUG_RRCSTS(n) ((n << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK)
+#define EMAC_MTL_RXQ1_DEBUG_RRCSTS(n) (((n) << EMAC_MTL_RXQ1_DEBUG_RRCSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RRCSTS_MASK)
#define EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT (4) /* Bits 4-6: MTL Rx Queue Fill-Level Status */
#define EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT)
-#define EMAC_MTL_RXQ1_DEBUG_RXQSTS(n) ((n << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK)
+#define EMAC_MTL_RXQ1_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK)
#define EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */
#define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT)
-#define EMAC_MTL_RXQ1_DEBUG_PRXQ(n) ((n << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK)
+#define EMAC_MTL_RXQ1_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK)
/* MTL Rx Queue 1 Control (MTL_RXQ1_CONTROL) */
#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT (0) /* Bits 0-3: Receive Queue Weight */
#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK (0x7 << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT)
-#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(n) ((n << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK)
+#define EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT(n) (((n) << EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_SHIFT) & EMAC_MTL_RXQ1_CONTROL_RXQ_WEGT_MASK)
#define EMAC_MTL_RXQ1_CONTROL_RXQ_FRM_ARBIT (1 << 3) /* Bit 3: Receive Queue Packet Arbitration */
/* DMA Mode (DMA_MODE) */
@@ -2638,15 +2638,15 @@
#define EMAC_DMA_MODE_DA (1 << 1) /* Bit 1: DMA Tx or Rx Arbitration Scheme */
#define EMAC_DMA_MODE_TAA_SHIFT (2) /* Bits 2-5: Transmit Arbitration Algorithm */
#define EMAC_DMA_MODE_TAA_MASK (0x7 << EMAC_DMA_MODE_TAA_SHIFT)
-#define EMAC_DMA_MODE_TAA(n) ((n << EMAC_DMA_MODE_TAA_SHIFT) & EMAC_DMA_MODE_TAA_MASK)
+#define EMAC_DMA_MODE_TAA(n) (((n) << EMAC_DMA_MODE_TAA_SHIFT) & EMAC_DMA_MODE_TAA_MASK)
#define EMAC_DMA_MODE_ARBC (1 << 9) /* Bit 9: Is reserved for NXP internal use */
#define EMAC_DMA_MODE_TXPR (1 << 11) /* Bit 11: Transmit Priority */
#define EMAC_DMA_MODE_PR_SHIFT (12) /* Bits 12-15: Priority Ratio */
#define EMAC_DMA_MODE_PR_MASK (0x7 << EMAC_DMA_MODE_PR_SHIFT)
-#define EMAC_DMA_MODE_PR(n) ((n << EMAC_DMA_MODE_PR_SHIFT) & EMAC_DMA_MODE_PR_MASK)
+#define EMAC_DMA_MODE_PR(n) (((n) << EMAC_DMA_MODE_PR_SHIFT) & EMAC_DMA_MODE_PR_MASK)
#define EMAC_DMA_MODE_INTM_SHIFT (16) /* Bits 16-18: Interrupt Mode */
#define EMAC_DMA_MODE_INTM_MASK (0x3 << EMAC_DMA_MODE_INTM_SHIFT)
-#define EMAC_DMA_MODE_INTM(n) ((n << EMAC_DMA_MODE_INTM_SHIFT) & EMAC_DMA_MODE_INTM_MASK)
+#define EMAC_DMA_MODE_INTM(n) (((n) << EMAC_DMA_MODE_INTM_SHIFT) & EMAC_DMA_MODE_INTM_MASK)
/* DMA System Bus Mode (DMA_SYSBUS_MODE) */
#define EMAC_DMA_SYSBUS_MODE_FB (1 << 0) /* Bit 0: Fixed Burst Length */
@@ -2664,25 +2664,25 @@
#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS (1 << 0) /* Bit 0: AHB Master Status */
#define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8) /* Bits 8-12: DMA Channel 0 Receive Process State */
#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT)
-#define EMAC_DMA_DEBUG_STATUS0_RPS0(n) ((n << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK)
+#define EMAC_DMA_DEBUG_STATUS0_RPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK)
#define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12) /* Bits 12-16: DMA Channel 0 Transmit Process State */
#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT)
-#define EMAC_DMA_DEBUG_STATUS0_TPS0(n) ((n << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK)
+#define EMAC_DMA_DEBUG_STATUS0_TPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK)
#define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16) /* Bits 16-20: DMA Channel 1 Receive Process State */
#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT)
-#define EMAC_DMA_DEBUG_STATUS0_RPS1(n) ((n << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK)
+#define EMAC_DMA_DEBUG_STATUS0_RPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK)
#define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20) /* Bits 20-24: DMA Channel 1 Transmit Process State */
#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT)
-#define EMAC_DMA_DEBUG_STATUS0_TPS1(n) ((n << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK)
+#define EMAC_DMA_DEBUG_STATUS0_TPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK)
/* DMA TBS Control (DMA_TBS_CTRL) */
#define EMAC_DMA_TBS_CTRL_FTOV (1 << 0) /* Bit 0: Fetch Time Offset Valid */
#define EMAC_DMA_TBS_CTRL_FGOS_SHIFT (4) /* Bits 4-7: Fetch GSN Offset */
#define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x7 << EMAC_DMA_TBS_CTRL_FGOS_SHIFT)
-#define EMAC_DMA_TBS_CTRL_FGOS(n) ((n << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) & EMAC_DMA_TBS_CTRL_FGOS_MASK)
+#define EMAC_DMA_TBS_CTRL_FGOS(n) (((n) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) & EMAC_DMA_TBS_CTRL_FGOS_MASK)
#define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8) /* Bits 8-32: Fetch Time Offset */
#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF << EMAC_DMA_TBS_CTRL_FTOS_SHIFT)
-#define EMAC_DMA_TBS_CTRL_FTOS(n) ((n << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) & EMAC_DMA_TBS_CTRL_FTOS_MASK)
+#define EMAC_DMA_TBS_CTRL_FTOS(n) (((n) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) & EMAC_DMA_TBS_CTRL_FTOS_MASK)
/* DMA Safety Interrupt Status (DMA_SAFETY_INTERRUPT_STATUS) */
#define EMAC_DMA_SAFETY_INTERRUPT_STATUS_DECIS (1 << 0) /* Bit 0: DMA ECC Correctable Error Interrupt Status */
@@ -2695,17 +2695,17 @@
#define EMAC_DMA_CH0_CONTROL_PBLX8 (1 << 16) /* Bit 16: 8xPBL mode */
#define EMAC_DMA_CH0_CONTROL_DSL_SHIFT (18) /* Bits 18-21: Descriptor Skip Length */
#define EMAC_DMA_CH0_CONTROL_DSL_MASK (0x7 << EMAC_DMA_CH0_CONTROL_DSL_SHIFT)
-#define EMAC_DMA_CH0_CONTROL_DSL(n) ((n << EMAC_DMA_CH0_CONTROL_DSL_SHIFT) & EMAC_DMA_CH0_CONTROL_DSL_MASK)
+#define EMAC_DMA_CH0_CONTROL_DSL(n) (((n) << EMAC_DMA_CH0_CONTROL_DSL_SHIFT) & EMAC_DMA_CH0_CONTROL_DSL_MASK)
/* DMA Channel Tx Control (DMA_CH0_TX_CONTROL) */
#define EMAC_DMA_CH0_TX_CONTROL_ST (1 << 0) /* Bit 0: Start or Stop Transmission Command */
#define EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT (1) /* Bits 1-4: Transmit Channel Weight */
#define EMAC_DMA_CH0_TX_CONTROL_TCW_MASK (0x7 << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT)
-#define EMAC_DMA_CH0_TX_CONTROL_TCW(n) ((n << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK)
+#define EMAC_DMA_CH0_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK)
#define EMAC_DMA_CH0_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */
#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */
#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT)
-#define EMAC_DMA_CH0_TX_CONTROL_TXPBL(n) ((n << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK)
+#define EMAC_DMA_CH0_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK)
#define EMAC_DMA_CH0_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */
#define EMAC_DMA_CH0_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */
@@ -2713,45 +2713,45 @@
#define EMAC_DMA_CH0_RX_CONTROL_SR (1 << 0) /* Bit 0: Start or Stop Receive */
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT (1) /* Bits 1-3: Receive Buffer size Low */
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT)
-#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0(n) ((n << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK)
+#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK)
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT)
-#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y(n) ((n << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK)
+#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK)
#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */
#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT)
-#define EMAC_DMA_CH0_RX_CONTROL_RXPBL(n) ((n << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK)
+#define EMAC_DMA_CH0_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK)
#define EMAC_DMA_CH0_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */
#define EMAC_DMA_CH0_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */
/* DMA Channel 0 Tx Descriptor List Address (DMA_CH0_TXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */
#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)
-#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(n) ((n << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK)
+#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK)
/* DMA Channel 0 Rx Descriptor List Address (DMA_CH0_RXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */
#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)
-#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(n) ((n << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK)
+#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK)
/* DMA Channel 0 Tx Descriptor Tail Pointer (DMA_CH0_TXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */
#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT)
-#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(n) ((n << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK)
+#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK)
/* DMA Channeli 0 Rx Descriptor List Pointer (DMA_CH0_RXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */
#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT)
-#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(n) ((n << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK)
+#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK)
/* DMA Channel 0 Tx Descriptor Ring Length (DMA_CH0_TXDESC_RING_LENGTH) */
#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */
#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT)
-#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(n) ((n << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK)
+#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK)
/* DMA Channel 0 Rx Descriptor Ring Length (DMA_CH0_RXDESC_RING_LENGTH) */
#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */
#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT)
-#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(n) ((n << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK)
+#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK)
/* DMA Channel 0 Interrupt Enable (DMA_CH0_INTERRUPT_ENABLE) */
#define EMAC_DMA_CH0_INTERRUPT_ENABLE_TIE (1 << 0) /* Bit 0: Transmit Interrupt Enable */
@@ -2774,10 +2774,10 @@
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)
-#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) ((n << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)
+#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)
-#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) ((n << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK)
+#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) (((n) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK)
/* DMA Channel 0 Slot Function Control Status
* (DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS)
@@ -2787,10 +2787,10 @@
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)
-#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) ((n << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)
+#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)
-#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) ((n << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)
+#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)
/* DMA Channel 0 Current Application Transmit Descriptor
* (DMA_CH0_CURRENT_APP_TXDESC)
@@ -2798,7 +2798,7 @@
#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */
#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)
-#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK)
+#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK)
/* DMA Channel 0 Current Application Receive Descriptor
* (DMA_CH0_CURRENT_APP_RXDESC)
@@ -2806,7 +2806,7 @@
#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */
#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)
-#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK)
+#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK)
/* DMA Channel 0 Current Application Transmit Descriptor
* (DMA_CH0_CURRENT_APP_TXBUFFER)
@@ -2814,7 +2814,7 @@
#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */
#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)
-#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK)
+#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK)
/* DMA Channel 0 Current Application Receive Buffer
* (DMA_CH0_CURRENT_APP_RXBUFFER)
@@ -2822,7 +2822,7 @@
#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */
#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)
-#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) ((n << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK)
+#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK)
/* DMA Channel 0 Status (DMA_CH0_STATUS) */
#define EMAC_DMA_CH0_STATUS_TI (1 << 0) /* Bit 0: Transmit Interrupt */
@@ -2840,43 +2840,43 @@
#define EMAC_DMA_CH0_STATUS_NIS (1 << 15) /* Bit 15: Normal Interrupt Summary */
#define EMAC_DMA_CH0_STATUS_TEB_SHIFT (16) /* Bits 16-19: Tx DMA Error Bits */
#define EMAC_DMA_CH0_STATUS_TEB_MASK (0x7 << EMAC_DMA_CH0_STATUS_TEB_SHIFT)
-#define EMAC_DMA_CH0_STATUS_TEB(n) ((n << EMAC_DMA_CH0_STATUS_TEB_SHIFT) & EMAC_DMA_CH0_STATUS_TEB_MASK)
+#define EMAC_DMA_CH0_STATUS_TEB(n) (((n) << EMAC_DMA_CH0_STATUS_TEB_SHIFT) & EMAC_DMA_CH0_STATUS_TEB_MASK)
#define EMAC_DMA_CH0_STATUS_REB_SHIFT (19) /* Bits 19-22: Rx DMA Error Bits */
#define EMAC_DMA_CH0_STATUS_REB_MASK (0x7 << EMAC_DMA_CH0_STATUS_REB_SHIFT)
-#define EMAC_DMA_CH0_STATUS_REB(n) ((n << EMAC_DMA_CH0_STATUS_REB_SHIFT) & EMAC_DMA_CH0_STATUS_REB_MASK)
+#define EMAC_DMA_CH0_STATUS_REB(n) (((n) << EMAC_DMA_CH0_STATUS_REB_SHIFT) & EMAC_DMA_CH0_STATUS_REB_MASK)
/* DMA Channel 0 Miss Frame Counter (DMA_CH0_MISS_FRAME_CNT) */
#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters Indicates the number of packet counters that DMA drops either because of bus error or because of programing RPF field in DMA_CH${i}_Rx_Control register */
#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT)
-#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) ((n << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK)
+#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK)
#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */
/* DMA Channel 0 Rx Parser Accept Count (DMA_CH0_RXP_ACCEPT_CNT) */
#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */
#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT)
-#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(n) ((n << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK)
+#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK)
#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */
/* DMA Channel 0 Rx ERI Count (DMA_CH0_RX_ERI_CNT) */
#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */
#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT)
-#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(n) ((n << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK)
+#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK)
/* DMA Channel 1 Control (DMA_CH1_CONTROL) */
#define EMAC_DMA_CH1_CONTROL_PBLX8 (1 << 16) /* Bit 16: 8xPBL mode */
#define EMAC_DMA_CH1_CONTROL_DSL_SHIFT (18) /* Bits 18-21: Descriptor Skip Length */
#define EMAC_DMA_CH1_CONTROL_DSL_MASK (0x7 << EMAC_DMA_CH1_CONTROL_DSL_SHIFT)
-#define EMAC_DMA_CH1_CONTROL_DSL(n) ((n << EMAC_DMA_CH1_CONTROL_DSL_SHIFT) & EMAC_DMA_CH1_CONTROL_DSL_MASK)
+#define EMAC_DMA_CH1_CONTROL_DSL(n) (((n) << EMAC_DMA_CH1_CONTROL_DSL_SHIFT) & EMAC_DMA_CH1_CONTROL_DSL_MASK)
/* DMA Channel 1 Tx Control (DMA_CH1_TX_CONTROL) */
#define EMAC_DMA_CH1_TX_CONTROL_ST (1 << 0) /* Bit 0: Start or Stop Transmission Command */
#define EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT (1) /* Bits 1-4: Transmit Channel Weight */
#define EMAC_DMA_CH1_TX_CONTROL_TCW_MASK (0x7 << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT)
-#define EMAC_DMA_CH1_TX_CONTROL_TCW(n) ((n << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK)
+#define EMAC_DMA_CH1_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK)
#define EMAC_DMA_CH1_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */
#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */
#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT)
-#define EMAC_DMA_CH1_TX_CONTROL_TXPBL(n) ((n << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK)
+#define EMAC_DMA_CH1_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK)
#define EMAC_DMA_CH1_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */
#define EMAC_DMA_CH1_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */
@@ -2884,45 +2884,45 @@
#define EMAC_DMA_CH1_RX_CONTROL_SR (1 << 0) /* Bit 0: Start or Stop Receive */
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT (1) /* Bits 1-3: Receive Buffer size Low */
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT)
-#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0(n) ((n << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK)
+#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK)
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT)
-#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y(n) ((n << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK)
+#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK)
#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */
#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT)
-#define EMAC_DMA_CH1_RX_CONTROL_RXPBL(n) ((n << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK)
+#define EMAC_DMA_CH1_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK)
#define EMAC_DMA_CH1_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */
#define EMAC_DMA_CH1_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */
/* DMA Channel 1 Tx Descriptor List Address (DMA_CH1_TXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */
#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)
-#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(n) ((n << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK)
+#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK)
/* DMA Channel 1 Rx Descriptor List Address (DMA_CH1_RXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */
#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)
-#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(n) ((n << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK)
+#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK)
/* DMA Channel 1 Tx Descriptor Tail Pointer (DMA_CH1_TXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */
#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT)
-#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(n) ((n << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK)
+#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK)
/* DMA Channel 1 Rx Descriptor Tail Pointer (DMA_CH1_RXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */
#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT)
-#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(n) ((n << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK)
+#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK)
/* DMA Channel 1 Tx Descriptor Ring Length (DMA_CH1_TXDESC_RING_LENGTH) */
#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */
#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT)
-#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(n) ((n << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK)
+#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK)
/* DMA Channel 1 Rx Descriptor Ring Length (DMA_CH1_RXDESC_RING_LENGTH) */
#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */
#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT)
-#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(n) ((n << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK)
+#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK)
/* DMA Channel 1 Interrupt Enable (DMA_CH1_INTERRUPT_ENABLE) */
#define EMAC_DMA_CH1_INTERRUPT_ENABLE_TIE (1 << 0) /* Bit 0: Transmit Interrupt Enable */
@@ -2945,10 +2945,10 @@
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)
-#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) ((n << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)
+#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)
-#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) ((n << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK)
+#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU(n) (((n) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK)
/* DMA Channel 1 Slot Function Control Status
* (DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS)
@@ -2958,10 +2958,10 @@
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)
-#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) ((n << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)
+#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)
-#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) ((n << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)
+#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)
/* DMA Channel 1 Current Application Transmit Descriptor
* (DMA_CH1_CURRENT_APP_TXDESC)
@@ -2969,7 +2969,7 @@
#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */
#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)
-#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK)
+#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK)
/* DMA Channel 1 Current Application Receive Descriptor
* (DMA_CH1_CURRENT_APP_RXDESC)
@@ -2977,7 +2977,7 @@
#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */
#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)
-#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK)
+#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK)
/* DMA Channel 1 Current Application Transmit Buffer
* (DMA_CH1_CURRENT_APP_TXBUFFER)
@@ -2985,7 +2985,7 @@
#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */
#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)
-#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK)
+#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK)
/* DMA Channel 1 Current Application Receive Buffer
* (DMA_CH1_CURRENT_APP_RXBUFFER)
@@ -2993,7 +2993,7 @@
#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */
#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)
-#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) ((n << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK)
+#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK)
/* DMA Channel 1 Status (DMA_CH1_STATUS) */
#define EMAC_DMA_CH1_STATUS_TI (1 << 0) /* Bit 0: Transmit Interrupt */
@@ -3011,27 +3011,27 @@
#define EMAC_DMA_CH1_STATUS_NIS (1 << 15) /* Bit 15: Normal Interrupt Summary */
#define EMAC_DMA_CH1_STATUS_TEB_SHIFT (16) /* Bits 16-19: Tx DMA Error Bits */
#define EMAC_DMA_CH1_STATUS_TEB_MASK (0x7 << EMAC_DMA_CH1_STATUS_TEB_SHIFT)
-#define EMAC_DMA_CH1_STATUS_TEB(n) ((n << EMAC_DMA_CH1_STATUS_TEB_SHIFT) & EMAC_DMA_CH1_STATUS_TEB_MASK)
+#define EMAC_DMA_CH1_STATUS_TEB(n) (((n) << EMAC_DMA_CH1_STATUS_TEB_SHIFT) & EMAC_DMA_CH1_STATUS_TEB_MASK)
#define EMAC_DMA_CH1_STATUS_REB_SHIFT (19) /* Bits 19-22: Rx DMA Error Bits */
#define EMAC_DMA_CH1_STATUS_REB_MASK (0x7 << EMAC_DMA_CH1_STATUS_REB_SHIFT)
-#define EMAC_DMA_CH1_STATUS_REB(n) ((n << EMAC_DMA_CH1_STATUS_REB_SHIFT) & EMAC_DMA_CH1_STATUS_REB_MASK)
+#define EMAC_DMA_CH1_STATUS_REB(n) (((n) << EMAC_DMA_CH1_STATUS_REB_SHIFT) & EMAC_DMA_CH1_STATUS_REB_MASK)
/* DMA Channel 1 Miss Frame Counter (DMA_CH1_MISS_FRAME_CNT) */
#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters */
#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT)
-#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(n) ((n << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK)
+#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK)
#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */
/* DMA Channel 1 Rx Parser Accept Count (DMA_CH1_RXP_ACCEPT_CNT) */
#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */
#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT)
-#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(n) ((n << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK)
+#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK)
#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */
/* DMA Channel 1 Rx ERI Count (DMA_CH1_RX_ERI_CNT) */
#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */
#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT)
-#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(n) ((n << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK)
+#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK)
#define EMAC_TDES3_CPC(x) (((uint32_t)(((uint32_t)(x)) << 26U)) & 0x0C000000U)
#define EMAC_TDES3_CIC(x) (((uint32_t)(((uint32_t)(x)) << 16U)) & 0x00030000U)
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
index 4ac3536c4f..8f675dbcf2 100644
--- a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
@@ -31,14 +31,6 @@
#include "mr-canhubk3.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifndef OK
-# define OK 0
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
index e3dffda672..e4b3fe1123 100644
--- a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
@@ -65,21 +65,22 @@ void board_userled(int led, bool ledon)
{
uint32_t ledcfg;
- if (led == BOARD_LED_R)
+ switch (ledcfg)
{
- ledcfg = GPIO_LED_R;
- }
- else if (led == BOARD_LED_G)
- {
- ledcfg = GPIO_LED_G;
- }
- else if (led == BOARD_LED_B)
- {
- ledcfg = GPIO_LED_B;
- }
- else
- {
- return;
+ case BOARD_LED_R:
+ ledcfg = GPIO_LED_R;
+ break;
+
+ case BOARD_LED_G:
+ ledcfg = GPIO_LED_G;
+ break;
+
+ case BOARD_LED_B:
+ ledcfg = GPIO_LED_B;
+ break;
+
+ default:
+ return;
}
/* Invert output, an output of '0' illuminates the LED */
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
index efbe5b9aa4..e927f834b3 100644
--- a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
@@ -31,14 +31,6 @@
#include "s32k344evb.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#ifndef OK
-# define OK 0
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
index daceb4fb28..5919e96ffe 100644
--- a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
@@ -70,33 +70,34 @@ void board_userled(int led, bool ledon)
{
uint32_t ledcfg;
- if (led == BOARD_LED0_R)
+ switch (ledcfg)
{
- ledcfg = GPIO_LED0_R;
- }
- else if (led == BOARD_LED0_G)
- {
- ledcfg = GPIO_LED0_G;
- }
- else if (led == BOARD_LED0_B)
- {
- ledcfg = GPIO_LED0_B;
- }
- else if (led == BOARD_LED1_R)
- {
- ledcfg = GPIO_LED1_R;
- }
- else if (led == BOARD_LED1_G)
- {
- ledcfg = GPIO_LED1_G;
- }
- else if (led == BOARD_LED1_B)
- {
- ledcfg = GPIO_LED1_B;
- }
- else
- {
- return;
+ case BOARD_LED0_R:
+ ledcfg = GPIO_LED0_R;
+ break;
+
+ case BOARD_LED0_G:
+ ledcfg = GPIO_LED0_G;
+ break;
+
+ case BOARD_LED0_B:
+ ledcfg = GPIO_LED0_B;
+ break;
+
+ case BOARD_LED1_R:
+ ledcfg = GPIO_LED1_R;
+ break;
+
+ case BOARD_LED1_G:
+ ledcfg = GPIO_LED1_G;
+ break;
+
+ case BOARD_LED1_B:
+ ledcfg = GPIO_LED1_B;
+ break;
+
+ default:
+ return;
}
/* An output of '1' illuminates the LED */
diff --git a/drivers/mtd/mx25rxx.c b/drivers/mtd/mx25rxx.c
index ef1b36c649..e9d0928cbb 100644
--- a/drivers/mtd/mx25rxx.c
+++ b/drivers/mtd/mx25rxx.c
@@ -101,9 +101,9 @@
#define MX25R_JEDEC_MANUFACTURER 0xc2 /* Macronix manufacturer ID */
#ifdef CONFIG_MX25RXX_LXX
-#define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
+# define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
#else
-#define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
+# define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
#endif
#define MX25R_JEDEC_MX25R6435F_CAPACITY 0x17 /* MX25R6435F memory capacity */
#define MX25R_JEDEC_MX25R8035F_CAPACITY 0x14 /* MX25R8035F memory capacity */
@@ -118,9 +118,9 @@
#define MX25R6435F_PAGE_SIZE (256)
#ifdef CONFIG_MX25RXX_PAGE128
-#define MX25R6435F_PAGE_SHIFT (7)
+# define MX25R6435F_PAGE_SHIFT (7)
#else
-#define MX25R6435F_PAGE_SHIFT (8)
+# define MX25R6435F_PAGE_SHIFT (8)
#endif
/* Status register bit definitions */
diff --git a/net/can/can_input.c b/net/can/can_input.c
index 7a073d566d..d01a2d199f 100644
--- a/net/can/can_input.c
+++ b/net/can/can_input.c
@@ -161,7 +161,7 @@ int can_input(struct net_driver_s *dev)
{
conn = can_nextconn(conn);
- if (conn && (conn->dev == 0x0 || dev == conn->dev))
+ if (conn && (conn->dev == NULL || dev == conn->dev))
{
uint16_t flags;
[incubator-nuttx] 01/09: Macronix MX25RXX driver: add support for MX25LXX as well
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d3b1ee98663f1fecbe3408380597d261f1278e8e
Author: Jari van Ewijk <ja...@nxp.com>
AuthorDate: Fri Jul 22 10:20:39 2022 +0200
Macronix MX25RXX driver: add support for MX25LXX as well
Co-authored-by: Peter van der Perk <pe...@nxp.com>
---
drivers/mtd/Kconfig | 8 ++++++++
drivers/mtd/mx25rxx.c | 13 +++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 006215bc1d..08486d9446 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -716,6 +716,14 @@ config MX25RXX_SECTOR512
bool "Simulate 512 byte Erase Blocks"
default n
+config MX25RXX_PAGE128
+ bool "128 byte size pages"
+ default n
+
+config MX25RXX_LXX
+ bool "Run MX25RXX driver in MX25LXX mode"
+ default n
+
endif # MTD_MX25RXX
config MTD_SMART
diff --git a/drivers/mtd/mx25rxx.c b/drivers/mtd/mx25rxx.c
index 23b04a00bb..ef1b36c649 100644
--- a/drivers/mtd/mx25rxx.c
+++ b/drivers/mtd/mx25rxx.c
@@ -100,7 +100,11 @@
/* JEDEC Read ID register values */
#define MX25R_JEDEC_MANUFACTURER 0xc2 /* Macronix manufacturer ID */
+#ifdef CONFIG_MX25RXX_LXX
+#define MX25R_JEDEC_MEMORY_TYPE 0x20 /* MX25Lx memory type */
+#else
#define MX25R_JEDEC_MEMORY_TYPE 0x28 /* MX25Rx memory type */
+#endif
#define MX25R_JEDEC_MX25R6435F_CAPACITY 0x17 /* MX25R6435F memory capacity */
#define MX25R_JEDEC_MX25R8035F_CAPACITY 0x14 /* MX25R8035F memory capacity */
@@ -112,7 +116,12 @@
#define MX25R6435F_SECTOR_SHIFT (12)
#define MX25R6435F_SECTOR_COUNT (2048)
#define MX25R6435F_PAGE_SIZE (256)
+
+#ifdef CONFIG_MX25RXX_PAGE128
+#define MX25R6435F_PAGE_SHIFT (7)
+#else
#define MX25R6435F_PAGE_SHIFT (8)
+#endif
/* Status register bit definitions */
@@ -539,7 +548,11 @@ void mx25rxx_write_status_config(FAR struct mx25rxx_dev_s *dev,
dev->cmdbuf[1] = config & 0xff;
dev->cmdbuf[2] = config >> 8;
+#ifdef CONFIG_MX25RXX_LXX
+ mx25rxx_command_write(dev->qspi, MX25R_WRSR, dev->cmdbuf, 2);
+#else
mx25rxx_command_write(dev->qspi, MX25R_WRSR, dev->cmdbuf, 3);
+#endif
mx25rxx_write_enable(dev, false);
}
[incubator-nuttx] 03/09: Add initial support for NXP S32K3 MCU family
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit dd1096695d04ae33932979b08d4303c221c6309a
Author: Jari van Ewijk <ja...@nxp.com>
AuthorDate: Fri Jul 22 10:25:50 2022 +0200
Add initial support for NXP S32K3 MCU family
Co-authored-by: Peter van der Perk <pe...@nxp.com>
---
arch/arm/Kconfig | 12 +
arch/arm/include/s32k3xx/chip.h | 61 +
arch/arm/include/s32k3xx/irq.h | 82 +
arch/arm/include/s32k3xx/s32k3x4_irq.h | 292 ++
arch/arm/src/s32k3xx/Kconfig | 1586 ++++++++++
arch/arm/src/s32k3xx/Make.defs | 82 +
arch/arm/src/s32k3xx/chip.h | 71 +
arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h | 1642 ++++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h | 1407 +++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h | 117 +
arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h | 912 ++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h | 245 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h | 1433 +++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h | 254 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h | 3084 +++++++++++++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h | 320 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_firc.h | 61 +
arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h | 3130 ++++++++++++++++++++
arch/arm/src/s32k3xx/hardware/s32k3xx_flexio.h | 773 +++++
arch/arm/src/s32k3xx/hardware/s32k3xx_fmu.h | 353 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h | 499 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h | 88 +
arch/arm/src/s32k3xx/hardware/s32k3xx_hse.h | 176 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_intm.h | 116 +
arch/arm/src/s32k3xx/hardware/s32k3xx_lpi2c.h | 556 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_lpspi.h | 468 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_lpuart.h | 541 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_cgm.h | 306 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_me.h | 561 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_mc_rgm.h | 183 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mcm.h | 148 +
arch/arm/src/s32k3xx/hardware/s32k3xx_memorymap.h | 255 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mscm.h | 271 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_mu.h | 442 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_pflash.h | 350 +++
arch/arm/src/s32k3xx/hardware/s32k3xx_pinmux.h | 60 +
arch/arm/src/s32k3xx/hardware/s32k3xx_pit.h | 186 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_pll.h | 134 +
arch/arm/src/s32k3xx/hardware/s32k3xx_pmc.h | 103 +
arch/arm/src/s32k3xx/hardware/s32k3xx_pramc.h | 55 +
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h | 505 ++++
arch/arm/src/s32k3xx/hardware/s32k3xx_rtc.h | 110 +
arch/arm/src/s32k3xx/hardware/s32k3xx_sema42.h | 118 +
arch/arm/src/s32k3xx/hardware/s32k3xx_sirc.h | 64 +
arch/arm/src/s32k3xx/hardware/s32k3xx_siul2.h | 315 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h | 117 +
arch/arm/src/s32k3xx/hardware/s32k3xx_swt.h | 132 +
arch/arm/src/s32k3xx/hardware/s32k3xx_sxosc.h | 64 +
arch/arm/src/s32k3xx/hardware/s32k3xx_tspc.h | 68 +
.../arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h | 204 ++
arch/arm/src/s32k3xx/hardware/s32k3xx_wkpu.h | 133 +
arch/arm/src/s32k3xx/hardware/s32k3xx_xbic.h | 129 +
arch/arm/src/s32k3xx/hardware/s32k3xx_xrdc.h | 354 +++
arch/arm/src/s32k3xx/s32k3xx_allocateheap.c | 287 ++
arch/arm/src/s32k3xx/s32k3xx_clockconfig.c | 1235 ++++++++
arch/arm/src/s32k3xx/s32k3xx_clockconfig.h | 424 +++
arch/arm/src/s32k3xx/s32k3xx_clocknames.h | 171 ++
arch/arm/src/s32k3xx/s32k3xx_clrpend.c | 82 +
arch/arm/src/s32k3xx/s32k3xx_config.h | 459 +++
arch/arm/src/s32k3xx/s32k3xx_edma.c | 1626 ++++++++++
arch/arm/src/s32k3xx/s32k3xx_edma.h | 465 +++
arch/arm/src/s32k3xx/s32k3xx_emac.c | 3084 +++++++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_emac.h | 110 +
arch/arm/src/s32k3xx/s32k3xx_flashboot.c | 66 +
arch/arm/src/s32k3xx/s32k3xx_flexcan.c | 2321 +++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_flexcan.h | 83 +
arch/arm/src/s32k3xx/s32k3xx_fs26.c | 511 ++++
arch/arm/src/s32k3xx/s32k3xx_fs26.h | 83 +
arch/arm/src/s32k3xx/s32k3xx_idle.c | 82 +
arch/arm/src/s32k3xx/s32k3xx_irq.c | 601 ++++
arch/arm/src/s32k3xx/s32k3xx_irq.h | 47 +
arch/arm/src/s32k3xx/s32k3xx_lowputc.c | 718 +++++
arch/arm/src/s32k3xx/s32k3xx_lowputc.h | 106 +
arch/arm/src/s32k3xx/s32k3xx_lpi2c.c | 1821 ++++++++++++
arch/arm/src/s32k3xx/s32k3xx_lpi2c.h | 71 +
arch/arm/src/s32k3xx/s32k3xx_lpspi.c | 2425 +++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_lpspi.h | 188 ++
arch/arm/src/s32k3xx/s32k3xx_periphclocks.c | 158 +
arch/arm/src/s32k3xx/s32k3xx_periphclocks.h | 239 ++
arch/arm/src/s32k3xx/s32k3xx_pin.c | 186 ++
arch/arm/src/s32k3xx/s32k3xx_pin.h | 596 ++++
arch/arm/src/s32k3xx/s32k3xx_pindma.c | 158 +
arch/arm/src/s32k3xx/s32k3xx_pingpio.c | 100 +
arch/arm/src/s32k3xx/s32k3xx_pinirq.c | 503 ++++
arch/arm/src/s32k3xx/s32k3xx_qspi.c | 1869 ++++++++++++
arch/arm/src/s32k3xx/s32k3xx_qspi.h | 131 +
arch/arm/src/s32k3xx/s32k3xx_serial.c | 2920 ++++++++++++++++++
arch/arm/src/s32k3xx/s32k3xx_serial.h | 86 +
arch/arm/src/s32k3xx/s32k3xx_start.c | 307 ++
arch/arm/src/s32k3xx/s32k3xx_start.h | 70 +
arch/arm/src/s32k3xx/s32k3xx_swt.h | 104 +
arch/arm/src/s32k3xx/s32k3xx_timerisr.c | 133 +
arch/arm/src/s32k3xx/startup.S | 57 +
drivers/serial/Kconfig | 35 +
drivers/serial/Kconfig-lpuart | 707 +++++
95 files changed, 49153 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index c26c70c490..59d00ae5e7 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -248,6 +248,14 @@ config ARCH_CHIP_S32K1XX
---help---
NPX S32K1XX architectures (ARM Cortex-M0+ and Cortex-M4F).
+config ARCH_CHIP_S32K3XX
+ bool "NXP S32K3XX"
+ select ARCH_HAVE_MPU
+ select ARCH_HAVE_RAMFUNCS
+ select ARM_HAVE_MPU_UNIFIED
+ ---help---
+ NPX S32K3XX architectures (ARM Cortex-M7).
+
config ARCH_CHIP_SAMA5
bool "Atmel SAMA5"
select ARCH_CORTEXA5
@@ -873,6 +881,7 @@ config ARCH_CHIP
default "nuc1xx" if ARCH_CHIP_NUC1XX
default "rp2040" if ARCH_CHIP_RP2040
default "s32k1xx" if ARCH_CHIP_S32K1XX
+ default "s32k3xx" if ARCH_CHIP_S32K3XX
default "sama5" if ARCH_CHIP_SAMA5
default "samd2l2" if ARCH_CHIP_SAMD2X || ARCH_CHIP_SAML2X
default "samd5e5" if ARCH_CHIP_SAMD5X || ARCH_CHIP_SAME5X
@@ -1220,6 +1229,9 @@ endif
if ARCH_CHIP_S32K1XX
source "arch/arm/src/s32k1xx/Kconfig"
endif
+if ARCH_CHIP_S32K3XX
+source arch/arm/src/s32k3xx/Kconfig
+endif
if ARCH_CHIP_MAX326XX
source "arch/arm/src/max326xx/Kconfig"
endif
diff --git a/arch/arm/include/s32k3xx/chip.h b/arch/arm/include/s32k3xx/chip.h
new file mode 100644
index 0000000000..d1ebeb563a
--- /dev/null
+++ b/arch/arm/include/s32k3xx/chip.h
@@ -0,0 +1,61 @@
+/****************************************************************************
+ * arch/arm/include/s32k3xx/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_INCLUDE_S32K3XX_CHIP_H
+#define __ARCH_ARM_INCLUDE_S32K3XX_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Prototypes
+ ****************************************************************************/
+
+/* NVIC priority levels *****************************************************/
+
+/* Each priority field holds a priority value. The lower the value, the
+ * greater the priority of the corresponding interrupt.
+ */
+
+/* Supports 16 programmable interrupt levels */
+
+#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set is minimum priority */
+#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
+#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
+#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_INCLUDE_S32K3XX_CHIP_H */
diff --git a/arch/arm/include/s32k3xx/irq.h b/arch/arm/include/s32k3xx/irq.h
new file mode 100644
index 0000000000..17a6f6ca15
--- /dev/null
+++ b/arch/arm/include/s32k3xx/irq.h
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * arch/arm/include/s32k3xx/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_S32K3XX_IRQ_H
+#define __ARCH_ARM_INCLUDE_S32K3XX_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds to the vector number and hence maps directly to
+ * bits in the NVIC. This does, however, waste several words of memory in
+ * the IRQ to handle mapping tables.
+ */
+
+/* Processor Exceptions (vectors 0-15) */
+
+#define S32K3XX_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
+ /* Vector 0: Initial Stack Pointer */
+ /* Vector 1: Initial Program Counter (not handled as an IRQ) */
+#define S32K3XX_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt */
+#define S32K3XX_IRQ_HARDFAULT (3) /* Vector 3: Hard Fault */
+#define S32K3XX_IRQ_MEMFAULT (4) /* Vector 4: Memory Management Fault */
+#define S32K3XX_IRQ_BUSFAULT (5) /* Vector 5: Bus Fault */
+#define S32K3XX_IRQ_USAGEFAULT (6) /* Vector 6: Usage Fault */
+ /* Vector 7: Reserved */
+ /* Vector 8: Reserved */
+ /* Vector 9: Reserved */
+ /* Vector 10: Reserved */
+#define S32K3XX_IRQ_SVCALL (11) /* Vector 11: Supervisor Call */
+#define S32K3XX_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
+ /* Vector 13: Reserved */
+#define S32K3XX_IRQ_PENDSV (14) /* Vector 14: Pendable System Service Request */
+#define S32K3XX_IRQ_SYSTICK (15) /* Vector 15: System Tick */
+
+/* External interrupts (vectors >= 16).
+ * These definitions are chip-specific.
+ */
+
+#define S32K3XX_IRQ_EXTINT (16) /* Vector 16: Vector number of the first external interrupt */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#if defined(CONFIG_ARCH_CHIP_S32K344)
+# include <arch/chip/s32k3x4_irq.h>
+#else
+# error Unrecognized S32K3XX part
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_S32K3XX_IRQ_H */
diff --git a/arch/arm/include/s32k3xx/s32k3x4_irq.h b/arch/arm/include/s32k3xx/s32k3x4_irq.h
new file mode 100644
index 0000000000..159192a33f
--- /dev/null
+++ b/arch/arm/include/s32k3xx/s32k3x4_irq.h
@@ -0,0 +1,292 @@
+/****************************************************************************
+ * arch/arm/include/s32k3xx/s32k3x4_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_S32K3XX_S32K3X4_IRQ_H
+#define __ARCH_ARM_INCLUDE_S32K3XX_S32K3X4_IRQ_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers.
+ * The IRQ number corresponds to the vector number and hence maps directly to
+ * bits in the NVIC. This does, however, waste several words of memory in
+ * the IRQ to handle mapping tables.
+ */
+
+/* External interrupts (vectors >= 16).
+ * These definitions are chip-specific.
+ */
+
+/* CPU to CPU and Directed Interrupts */
+
+#define S32K3XX_IRQ_CPU_TO_CPU1 (S32K3XX_IRQ_EXTINT + 0) /* 0: CPU to CPU interupt 0 (Core 0 --> Core 1) */
+#define S32K3XX_IRQ_CPU_TO_CPU2 (S32K3XX_IRQ_EXTINT + 1) /* 1: CPU to CPU interupt 1 (Core 0 --> Core 1) */
+#define S32K3XX_IRQ_CPU_TO_CPU3 (S32K3XX_IRQ_EXTINT + 2) /* 2: CPU to CPU interupt 2 (Core 0 <-- Core 1) */
+#define S32K3XX_IRQ_CPU_TO_CPU4 (S32K3XX_IRQ_EXTINT + 3) /* 3: CPU to CPU interupt 3 (Core 0 <-- Core 1) */
+
+/* Shared Peripheral Interrupts - On-Platform Vectors */
+
+#define S32K3XX_IRQ_DMA_CH0 (S32K3XX_IRQ_EXTINT + 4) /* 4: DMA transfer complete and error CH0 */
+#define S32K3XX_IRQ_DMA_CH1 (S32K3XX_IRQ_EXTINT + 5) /* 5: DMA transfer complete and error CH1 */
+#define S32K3XX_IRQ_DMA_CH2 (S32K3XX_IRQ_EXTINT + 6) /* 6: DMA transfer complete and error CH2 */
+#define S32K3XX_IRQ_DMA_CH3 (S32K3XX_IRQ_EXTINT + 7) /* 7: DMA transfer complete and error CH3 */
+#define S32K3XX_IRQ_DMA_CH4 (S32K3XX_IRQ_EXTINT + 8) /* 8: DMA transfer complete and error CH4 */
+#define S32K3XX_IRQ_DMA_CH5 (S32K3XX_IRQ_EXTINT + 9) /* 9: DMA transfer complete and error CH5 */
+#define S32K3XX_IRQ_DMA_CH6 (S32K3XX_IRQ_EXTINT + 10) /* 10: DMA transfer complete and error CH6 */
+#define S32K3XX_IRQ_DMA_CH7 (S32K3XX_IRQ_EXTINT + 11) /* 11: DMA transfer complete and error CH7 */
+#define S32K3XX_IRQ_DMA_CH8 (S32K3XX_IRQ_EXTINT + 12) /* 12: DMA transfer complete and error CH8 */
+#define S32K3XX_IRQ_DMA_CH9 (S32K3XX_IRQ_EXTINT + 13) /* 13: DMA transfer complete and error CH9 */
+#define S32K3XX_IRQ_DMA_CH10 (S32K3XX_IRQ_EXTINT + 14) /* 14: DMA transfer complete and error CH10 */
+#define S32K3XX_IRQ_DMA_CH11 (S32K3XX_IRQ_EXTINT + 15) /* 15: DMA transfer complete and error CH11 */
+#define S32K3XX_IRQ_DMA_CH12 (S32K3XX_IRQ_EXTINT + 16) /* 16: DMA transfer complete and error CH12 */
+#define S32K3XX_IRQ_DMA_CH13 (S32K3XX_IRQ_EXTINT + 17) /* 17: DMA transfer complete and error CH13 */
+#define S32K3XX_IRQ_DMA_CH14 (S32K3XX_IRQ_EXTINT + 18) /* 18: DMA transfer complete and error CH14 */
+#define S32K3XX_IRQ_DMA_CH15 (S32K3XX_IRQ_EXTINT + 19) /* 19: DMA transfer complete and error CH15 */
+#define S32K3XX_IRQ_DMA_CH16 (S32K3XX_IRQ_EXTINT + 20) /* 20: DMA transfer complete and error CH16 */
+#define S32K3XX_IRQ_DMA_CH17 (S32K3XX_IRQ_EXTINT + 21) /* 21: DMA transfer complete and error CH17 */
+#define S32K3XX_IRQ_DMA_CH18 (S32K3XX_IRQ_EXTINT + 22) /* 22: DMA transfer complete and error CH18 */
+#define S32K3XX_IRQ_DMA_CH19 (S32K3XX_IRQ_EXTINT + 23) /* 23: DMA transfer complete and error CH19 */
+#define S32K3XX_IRQ_DMA_CH20 (S32K3XX_IRQ_EXTINT + 24) /* 24: DMA transfer complete and error CH20 */
+#define S32K3XX_IRQ_DMA_CH21 (S32K3XX_IRQ_EXTINT + 25) /* 25: DMA transfer complete and error CH21 */
+#define S32K3XX_IRQ_DMA_CH22 (S32K3XX_IRQ_EXTINT + 26) /* 26: DMA transfer complete and error CH22 */
+#define S32K3XX_IRQ_DMA_CH23 (S32K3XX_IRQ_EXTINT + 27) /* 27: DMA transfer complete and error CH23 */
+#define S32K3XX_IRQ_DMA_CH24 (S32K3XX_IRQ_EXTINT + 28) /* 28: DMA transfer complete and error CH24 */
+#define S32K3XX_IRQ_DMA_CH25 (S32K3XX_IRQ_EXTINT + 29) /* 29: DMA transfer complete and error CH25 */
+#define S32K3XX_IRQ_DMA_CH26 (S32K3XX_IRQ_EXTINT + 30) /* 30: DMA transfer complete and error CH26 */
+#define S32K3XX_IRQ_DMA_CH27 (S32K3XX_IRQ_EXTINT + 31) /* 31: DMA transfer complete and error CH27 */
+#define S32K3XX_IRQ_DMA_CH28 (S32K3XX_IRQ_EXTINT + 32) /* 32: DMA transfer complete and error CH28 */
+#define S32K3XX_IRQ_DMA_CH29 (S32K3XX_IRQ_EXTINT + 33) /* 33: DMA transfer complete and error CH29 */
+#define S32K3XX_IRQ_DMA_CH30 (S32K3XX_IRQ_EXTINT + 34) /* 34: DMA transfer complete and error CH30 */
+#define S32K3XX_IRQ_DMA_CH31 (S32K3XX_IRQ_EXTINT + 35) /* 35: DMA transfer complete and error CH31 */
+#define S32K3XX_IRQ_ERM_SBE (S32K3XX_IRQ_EXTINT + 36) /* 36: Error Reporting Module single bit ECC error interrupt */
+#define S32K3XX_IRQ_ERM_MBE (S32K3XX_IRQ_EXTINT + 37) /* 37: Error Reporting Module multi bit ECC error interrupt */
+#define S32K3XX_IRQ_MCM_FPU (S32K3XX_IRQ_EXTINT + 38) /* 38: Miscellaneous Control Module FPU interrupts */
+#define S32K3XX_IRQ_STM0 (S32K3XX_IRQ_EXTINT + 39) /* 39: System Timer Module 0 interrupt */
+#define S32K3XX_IRQ_STM1 (S32K3XX_IRQ_EXTINT + 40) /* 40: System Timer Module 1 interrupt */
+#define S32K3XX_IRQ_RESERVED41 (S32K3XX_IRQ_EXTINT + 41) /* 41: Reserved */
+#define S32K3XX_IRQ_SWT0 (S32K3XX_IRQ_EXTINT + 42) /* 42: System Watchdog Timer 0 initial time-out interrupt */
+#define S32K3XX_IRQ_SWT1 (S32K3XX_IRQ_EXTINT + 43) /* 43: System Watchdog Timer 1 initial time-out interrupt */
+#define S32K3XX_IRQ_RESERVED44 (S32K3XX_IRQ_EXTINT + 44) /* 44: Reserved */
+#define S32K3XX_IRQ_CTI0 (S32K3XX_IRQ_EXTINT + 45) /* 45: Cross Trigger Interface interrupt 0 */
+#define S32K3XX_IRQ_CTI1 (S32K3XX_IRQ_EXTINT + 46) /* 46: Cross Trigger Interface interrupt 1 */
+#define S32K3XX_IRQ_RESERVED47 (S32K3XX_IRQ_EXTINT + 47) /* 47: Reserved */
+
+/* Shared Peripheral Interrupts - Off-Platform Vectors */
+
+#define S32K3XX_IRQ_PFLASH_OP (S32K3XX_IRQ_EXTINT + 48) /* 48: Platform Flash Memory Controller program or erase operation completed */
+#define S32K3XX_IRQ_PFLASH_WDOG (S32K3XX_IRQ_EXTINT + 49) /* 49: Platform Flash Memory Controller main/express watchdog time-out interrupt */
+#define S32K3XX_IRQ_PFLASH_WDOGALT (S32K3XX_IRQ_EXTINT + 50) /* 50: Platform Flash Memory Controller alternate watchdog time-out interrupt */
+#define S32K3XX_IRQ_MC_RGM (S32K3XX_IRQ_EXTINT + 51) /* 51: Reset Generation Module interrupt */
+#define S32K3XX_IRQ_PMC (S32K3XX_IRQ_EXTINT + 52) /* 52: Power Management Controller interrupts */
+#define S32K3XX_IRQ_SIUL2_VEC0 (S32K3XX_IRQ_EXTINT + 53) /* 53: System Integration Unit Lite 2 external interrupt vector 0 */
+#define S32K3XX_IRQ_SIUL2_VEC1 (S32K3XX_IRQ_EXTINT + 54) /* 54: System Integration Unit Lite 2 external interrupt vector 1 */
+#define S32K3XX_IRQ_SIUL2_VEC2 (S32K3XX_IRQ_EXTINT + 55) /* 55: System Integration Unit Lite 2 external interrupt vector 2 */
+#define S32K3XX_IRQ_SIUL2_VEC3 (S32K3XX_IRQ_EXTINT + 56) /* 56: System Integration Unit Lite 2 external interrupt vector 3 */
+#define S32K3XX_IRQ_RESERVED57 (S32K3XX_IRQ_EXTINT + 57) /* 57: Reserved */
+#define S32K3XX_IRQ_RESERVED58 (S32K3XX_IRQ_EXTINT + 58) /* 58: Reserved */
+#define S32K3XX_IRQ_RESERVED59 (S32K3XX_IRQ_EXTINT + 59) /* 59: Reserved */
+#define S32K3XX_IRQ_RESERVED60 (S32K3XX_IRQ_EXTINT + 60) /* 60: Reserved */
+#define S32K3XX_IRQ_EMIOS0_20_23 (S32K3XX_IRQ_EXTINT + 61) /* 61: eMIOS0 interrupt requests 20-23 */
+#define S32K3XX_IRQ_EMIOS0_16_19 (S32K3XX_IRQ_EXTINT + 62) /* 62: eMIOS0 interrupt requests 16-19 */
+#define S32K3XX_IRQ_EMIOS0_12_15 (S32K3XX_IRQ_EXTINT + 63) /* 63: eMIOS0 interrupt requests 12-15 */
+#define S32K3XX_IRQ_EMIOS0_8_11 (S32K3XX_IRQ_EXTINT + 64) /* 64: eMIOS0 interrupt requests 8-11 */
+#define S32K3XX_IRQ_EMIOS0_4_7 (S32K3XX_IRQ_EXTINT + 65) /* 65: eMIOS0 interrupt requests 4-7 */
+#define S32K3XX_IRQ_EMIOS0_0_3 (S32K3XX_IRQ_EXTINT + 66) /* 66: eMIOS0 interrupt requests 0-3 */
+#define S32K3XX_IRQ_RESERVED67 (S32K3XX_IRQ_EXTINT + 67) /* 67: Reserved */
+#define S32K3XX_IRQ_RESERVED68 (S32K3XX_IRQ_EXTINT + 68) /* 68: Reserved */
+#define S32K3XX_IRQ_EMIOS1_20_23 (S32K3XX_IRQ_EXTINT + 69) /* 69: eMIOS1 interrupt requests 20-23 */
+#define S32K3XX_IRQ_EMIOS1_16_19 (S32K3XX_IRQ_EXTINT + 70) /* 70: eMIOS1 interrupt requests 16-19 */
+#define S32K3XX_IRQ_EMIOS1_12_15 (S32K3XX_IRQ_EXTINT + 71) /* 71: eMIOS1 interrupt requests 12-15 */
+#define S32K3XX_IRQ_EMIOS1_8_11 (S32K3XX_IRQ_EXTINT + 72) /* 72: eMIOS1 interrupt requests 8-11 */
+#define S32K3XX_IRQ_EMIOS1_4_7 (S32K3XX_IRQ_EXTINT + 73) /* 73: eMIOS1 interrupt requests 4-7 */
+#define S32K3XX_IRQ_EMIOS1_0_3 (S32K3XX_IRQ_EXTINT + 74) /* 74: eMIOS1 interrupt requests 0-3 */
+#define S32K3XX_IRQ_RESERVED75 (S32K3XX_IRQ_EXTINT + 75) /* 75: Reserved */
+#define S32K3XX_IRQ_RESERVED76 (S32K3XX_IRQ_EXTINT + 76) /* 76: Reserved */
+#define S32K3XX_IRQ_EMIOS2_20_23 (S32K3XX_IRQ_EXTINT + 77) /* 77: eMIOS2 interrupt requests 20-23 */
+#define S32K3XX_IRQ_EMIOS2_16_19 (S32K3XX_IRQ_EXTINT + 78) /* 78: eMIOS2 interrupt requests 16-19 */
+#define S32K3XX_IRQ_EMIOS2_12_15 (S32K3XX_IRQ_EXTINT + 79) /* 79: eMIOS2 interrupt requests 12-15 */
+#define S32K3XX_IRQ_EMIOS2_8_11 (S32K3XX_IRQ_EXTINT + 80) /* 80: eMIOS2 interrupt requests 8-11 */
+#define S32K3XX_IRQ_EMIOS2_4_7 (S32K3XX_IRQ_EXTINT + 81) /* 81: eMIOS2 interrupt requests 4-7 */
+#define S32K3XX_IRQ_EMIOS2_0_3 (S32K3XX_IRQ_EXTINT + 82) /* 82: eMIOS2 interrupt requests 0-3 */
+#define S32K3XX_IRQ_WKPU (S32K3XX_IRQ_EXTINT + 83) /* 83: Wakeup Unit interrupts */
+#define S32K3XX_IRQ_CMU0 (S32K3XX_IRQ_EXTINT + 84) /* 84: Clock Monitoring Unit 0 interrupt */
+#define S32K3XX_IRQ_CMU1 (S32K3XX_IRQ_EXTINT + 85) /* 85: Clock Monitoring Unit 1 interrupt */
+#define S32K3XX_IRQ_CMU2 (S32K3XX_IRQ_EXTINT + 86) /* 86: Clock Monitoring Unit 2 interrupt */
+#define S32K3XX_IRQ_BCTU (S32K3XX_IRQ_EXTINT + 87) /* 87: Body Cross Triggering Unit interrupts */
+#define S32K3XX_IRQ_RESERVED88 (S32K3XX_IRQ_EXTINT + 88) /* 88: Reserved */
+#define S32K3XX_IRQ_RESERVED89 (S32K3XX_IRQ_EXTINT + 89) /* 89: Reserved */
+#define S32K3XX_IRQ_RESERVED90 (S32K3XX_IRQ_EXTINT + 90) /* 90: Reserved */
+#define S32K3XX_IRQ_RESERVED91 (S32K3XX_IRQ_EXTINT + 91) /* 91: Reserved */
+#define S32k3XX_IRQ_LCU0 (S32K3XX_IRQ_EXTINT + 92) /* 92: Logic Control Unit 0 interrupts */
+#define S32k3XX_IRQ_LCU1 (S32K3XX_IRQ_EXTINT + 93) /* 93: Logic Control Unit 1 interrupts */
+#define S32K3XX_IRQ_RESERVED94 (S32K3XX_IRQ_EXTINT + 94) /* 94: Reserved */
+#define S32K3XX_IRQ_RESERVED95 (S32K3XX_IRQ_EXTINT + 95) /* 95: Reserved */
+#define S32k3XX_IRQ_PIT0 (S32K3XX_IRQ_EXTINT + 96) /* 96: Periodic Interrupt Timer 0 interrupts */
+#define S32k3XX_IRQ_PIT1 (S32K3XX_IRQ_EXTINT + 97) /* 97: Periodic Interrupt Timer 1 interrupts */
+#define S32k3XX_IRQ_PIT2 (S32K3XX_IRQ_EXTINT + 98) /* 98: Periodic Interrupt Timer 2 interrupts */
+#define S32K3XX_IRQ_RESERVED99 (S32K3XX_IRQ_EXTINT + 99) /* 99: Reserved */
+#define S32K3XX_IRQ_RESERVED100 (S32K3XX_IRQ_EXTINT + 100) /* 100: Reserved */
+#define S32K3XX_IRQ_RESERVED101 (S32K3XX_IRQ_EXTINT + 101) /* 101: Reserved */
+#define S32K3XX_IRQ_RTC (S32K3XX_IRQ_EXTINT + 102) /* 102: Real Time Clock interrupts */
+#define S32K3XX_IRQ_RESERVED103 (S32K3XX_IRQ_EXTINT + 103) /* 103: Reserved */
+#define S32K3XX_IRQ_RESERVED104 (S32K3XX_IRQ_EXTINT + 104) /* 104: Reserved */
+#define S32K3XX_IRQ_EMAC_COMMON (S32K3XX_IRQ_EXTINT + 105) /* 105: Ethernet MAC common interrupts */
+#define S32K3XX_IRQ_EMAC_TX (S32K3XX_IRQ_EXTINT + 106) /* 106: Ethernet MAC TX interrupts */
+#define S32K3XX_IRQ_EMAC_RX (S32K3XX_IRQ_EXTINT + 107) /* 107: Ethernet MAC RX interrupts */
+#define S32K3XX_IRQ_EMAC_SAFETY (S32K3XX_IRQ_EXTINT + 108) /* 108: Ethernet MAC safety interrupts */
+#define S32K3XX_IRQ_FLEXCAN0_0 (S32K3XX_IRQ_EXTINT + 109) /* 109: FlexCAN 0 interrupts 0 */
+#define S32K3XX_IRQ_FLEXCAN0_1 (S32K3XX_IRQ_EXTINT + 110) /* 110: FlexCAN 0 interrupts 1 */
+#define S32K3XX_IRQ_FLEXCAN0_2 (S32K3XX_IRQ_EXTINT + 111) /* 111: FlexCAN 0 interrupts 2 */
+#define S32K3XX_IRQ_FLEXCAN0_3 (S32K3XX_IRQ_EXTINT + 112) /* 112: FlexCAN 0 interrupts 3 */
+#define S32K3XX_IRQ_FLEXCAN1_0 (S32K3XX_IRQ_EXTINT + 113) /* 113: FlexCAN 1 interrupts 0 */
+#define S32K3XX_IRQ_FLEXCAN1_1 (S32K3XX_IRQ_EXTINT + 114) /* 114: FlexCAN 1 interrupts 1 */
+#define S32K3XX_IRQ_FLEXCAN1_2 (S32K3XX_IRQ_EXTINT + 115) /* 115: FlexCAN 1 interrupts 2 */
+#define S32K3XX_IRQ_FLEXCAN2_0 (S32K3XX_IRQ_EXTINT + 116) /* 116: FlexCAN 2 interrupts 0 */
+#define S32K3XX_IRQ_FLEXCAN2_1 (S32K3XX_IRQ_EXTINT + 117) /* 117: FlexCAN 2 interrupts 1 */
+#define S32K3XX_IRQ_FLEXCAN2_2 (S32K3XX_IRQ_EXTINT + 118) /* 118: FlexCAN 2 interrupts 2 */
+#define S32K3XX_IRQ_FLEXCAN3_0 (S32K3XX_IRQ_EXTINT + 119) /* 119: FlexCAN 3 interrupts 0 */
+#define S32K3XX_IRQ_FLEXCAN3_1 (S32K3XX_IRQ_EXTINT + 120) /* 120: FlexCAN 3 interrupts 1 */
+#define S32K3XX_IRQ_FLEXCAN4_0 (S32K3XX_IRQ_EXTINT + 121) /* 121: FlexCAN 4 interrupts 0 */
+#define S32K3XX_IRQ_FLEXCAN4_1 (S32K3XX_IRQ_EXTINT + 122) /* 122: FlexCAN 4 interrupts 1 */
+#define S32K3XX_IRQ_FLEXCAN5_0 (S32K3XX_IRQ_EXTINT + 123) /* 123: FlexCAN 5 interrupts 0 */
+#define S32K3XX_IRQ_FLEXCAN5_1 (S32K3XX_IRQ_EXTINT + 124) /* 124: FlexCAN 5 interrupts 1 */
+#define S32K3XX_IRQ_RESERVED125 (S32K3XX_IRQ_EXTINT + 125) /* 125: Reserved */
+#define S32K3XX_IRQ_RESERVED126 (S32K3XX_IRQ_EXTINT + 126) /* 126: Reserved */
+#define S32K3XX_IRQ_RESERVED127 (S32K3XX_IRQ_EXTINT + 127) /* 127: Reserved */
+#define S32K3XX_IRQ_RESERVED128 (S32K3XX_IRQ_EXTINT + 128) /* 128: Reserved */
+#define S32K3XX_IRQ_RESERVED129 (S32K3XX_IRQ_EXTINT + 129) /* 129: Reserved */
+#define S32K3XX_IRQ_RESERVED130 (S32K3XX_IRQ_EXTINT + 130) /* 130: Reserved */
+#define S32K3XX_IRQ_RESERVED131 (S32K3XX_IRQ_EXTINT + 131) /* 131: Reserved */
+#define S32K3XX_IRQ_RESERVED132 (S32K3XX_IRQ_EXTINT + 132) /* 132: Reserved */
+#define S32K3XX_IRQ_RESERVED133 (S32K3XX_IRQ_EXTINT + 133) /* 133: Reserved */
+#define S32K3XX_IRQ_RESERVED134 (S32K3XX_IRQ_EXTINT + 134) /* 134: Reserved */
+#define S32K3XX_IRQ_RESERVED135 (S32K3XX_IRQ_EXTINT + 135) /* 135: Reserved */
+#define S32K3XX_IRQ_RESERVED136 (S32K3XX_IRQ_EXTINT + 136) /* 136: Reserved */
+#define S32K3XX_IRQ_RESERVED137 (S32K3XX_IRQ_EXTINT + 137) /* 137: Reserved */
+#define S32K3XX_IRQ_RESERVED138 (S32K3XX_IRQ_EXTINT + 138) /* 138: Reserved */
+#define S32K3XX_IRQ_FLEXIO (S32K3XX_IRQ_EXTINT + 139) /* 139: FlexIO interrupt */
+#define S32K3XX_IRQ_RESERVED140 (S32K3XX_IRQ_EXTINT + 140) /* 140: Reserved */
+#define S32K3XX_IRQ_LPUART0 (S32K3XX_IRQ_EXTINT + 141) /* 141: LPUART0 interrupts */
+#define S32K3XX_IRQ_LPUART1 (S32K3XX_IRQ_EXTINT + 142) /* 142: LPUART1 interrupts */
+#define S32K3XX_IRQ_LPUART2 (S32K3XX_IRQ_EXTINT + 143) /* 143: LPUART2 interrupts */
+#define S32K3XX_IRQ_LPUART3 (S32K3XX_IRQ_EXTINT + 144) /* 144: LPUART3 interrupts */
+#define S32K3XX_IRQ_LPUART4 (S32K3XX_IRQ_EXTINT + 145) /* 145: LPUART4 interrupts */
+#define S32K3XX_IRQ_LPUART5 (S32K3XX_IRQ_EXTINT + 146) /* 146: LPUART5 interrupts */
+#define S32K3XX_IRQ_LPUART6 (S32K3XX_IRQ_EXTINT + 147) /* 147: LPUART6 interrupts */
+#define S32K3XX_IRQ_LPUART7 (S32K3XX_IRQ_EXTINT + 148) /* 148: LPUART7 interrupts */
+#define S32K3XX_IRQ_LPUART8 (S32K3XX_IRQ_EXTINT + 149) /* 149: LPUART8 interrupts */
+#define S32K3XX_IRQ_LPUART9 (S32K3XX_IRQ_EXTINT + 150) /* 150: LPUART9 interrupts */
+#define S32K3XX_IRQ_LPUART10 (S32K3XX_IRQ_EXTINT + 151) /* 151: LPUART10 interrupts */
+#define S32K3XX_IRQ_LPUART11 (S32K3XX_IRQ_EXTINT + 152) /* 152: LPUART11 interrupts */
+#define S32K3XX_IRQ_LPUART12 (S32K3XX_IRQ_EXTINT + 153) /* 153: LPUART12 interrupts */
+#define S32K3XX_IRQ_LPUART13 (S32K3XX_IRQ_EXTINT + 154) /* 154: LPUART13 interrupts */
+#define S32K3XX_IRQ_LPUART14 (S32K3XX_IRQ_EXTINT + 155) /* 155: LPUART14 interrupts */
+#define S32K3XX_IRQ_LPUART15 (S32K3XX_IRQ_EXTINT + 156) /* 156: LPUART15 interrupts */
+#define S32K3XX_IRQ_RESERVED157 (S32K3XX_IRQ_EXTINT + 157) /* 157: Reserved */
+#define S32K3XX_IRQ_RESERVED158 (S32K3XX_IRQ_EXTINT + 158) /* 158: Reserved */
+#define S32K3XX_IRQ_RESERVED159 (S32K3XX_IRQ_EXTINT + 159) /* 159: Reserved */
+#define S32K3XX_IRQ_RESERVED160 (S32K3XX_IRQ_EXTINT + 160) /* 160: Reserved */
+#define S32K3XX_IRQ_LPI2C0 (S32K3XX_IRQ_EXTINT + 161) /* 161: LPI2C0 interrupts */
+#define S32K3XX_IRQ_LPI2C1 (S32K3XX_IRQ_EXTINT + 162) /* 162: LPI2C1 interrupts */
+#define S32K3XX_IRQ_RESERVED163 (S32K3XX_IRQ_EXTINT + 163) /* 163: Reserved */
+#define S32K3XX_IRQ_RESERVED164 (S32K3XX_IRQ_EXTINT + 164) /* 164: Reserved */
+#define S32K3XX_IRQ_LPSPI0 (S32K3XX_IRQ_EXTINT + 165) /* 165: LPSPI0 interrupt */
+#define S32K3XX_IRQ_LPSPI1 (S32K3XX_IRQ_EXTINT + 166) /* 166: LPSPI1 interrupt */
+#define S32K3XX_IRQ_LPSPI2 (S32K3XX_IRQ_EXTINT + 167) /* 167: LPSPI2 interrupt */
+#define S32K3XX_IRQ_LPSPI3 (S32K3XX_IRQ_EXTINT + 168) /* 168: LPSPI3 interrupt */
+#define S32K3XX_IRQ_LPSPI4 (S32K3XX_IRQ_EXTINT + 169) /* 169: LPSPI4 interrupt */
+#define S32K3XX_IRQ_LPSPI5 (S32K3XX_IRQ_EXTINT + 170) /* 170: LPSPI5 interrupt */
+#define S32K3XX_IRQ_RESERVED171 (S32K3XX_IRQ_EXTINT + 171) /* 171: Reserved */
+#define S32K3XX_IRQ_RESERVED172 (S32K3XX_IRQ_EXTINT + 172) /* 172: Reserved */
+#define S32K3XX_IRQ_QSPI (S32K3XX_IRQ_EXTINT + 173) /* 173: Quad SPI interrupts */
+#define S32K3XX_IRQ_SAI0 (S32K3XX_IRQ_EXTINT + 174) /* 174: SAI0 interrupts */
+#define S32K3XX_IRQ_SAI1 (S32K3XX_IRQ_EXTINT + 175) /* 175: SAI1 interrupts */
+#define S32K3XX_IRQ_RESERVED176 (S32K3XX_IRQ_EXTINT + 176) /* 176: Reserved */
+#define S32K3XX_IRQ_RESERVED177 (S32K3XX_IRQ_EXTINT + 177) /* 177: Reserved */
+#define S32K3XX_IRQ_JDC (S32K3XX_IRQ_EXTINT + 178) /* 178: JTAG Data Communication interrupt */
+#define S32K3XX_IRQ_RESERVED177 (S32K3XX_IRQ_EXTINT + 179) /* 179: Reserved */
+#define S32K3XX_IRQ_ADC0 (S32K3XX_IRQ_EXTINT + 180) /* 180: ADC0 interrupts */
+#define S32K3XX_IRQ_ADC1 (S32K3XX_IRQ_EXTINT + 181) /* 181: ADC1 interrupts */
+#define S32K3XX_IRQ_ADC2 (S32K3XX_IRQ_EXTINT + 182) /* 182: ADC2 interrupts */
+#define S32K3XX_IRQ_LPCMP0 (S32K3XX_IRQ_EXTINT + 183) /* 183: LPCMP0 interrupt */
+#define S32K3XX_IRQ_LPCMP1 (S32K3XX_IRQ_EXTINT + 184) /* 184: LPCMP1 interrupt */
+#define S32K3XX_IRQ_LPCMP2 (S32K3XX_IRQ_EXTINT + 185) /* 185: LPCMP2 interrupt */
+#define S32K3XX_IRQ_RESERVED186 (S32K3XX_IRQ_EXTINT + 186) /* 186: Reserved */
+#define S32K3XX_IRQ_RESERVED187 (S32K3XX_IRQ_EXTINT + 187) /* 187: Reserved */
+#define S32K3XX_IRQ_RESERVED188 (S32K3XX_IRQ_EXTINT + 188) /* 188: Reserved */
+#define S32K3XX_IRQ_FCCU0 (S32K3XX_IRQ_EXTINT + 189) /* 189: Fault Collection Control Unit interrupt 0 */
+#define S32K3XX_IRQ_FCCU1 (S32K3XX_IRQ_EXTINT + 190) /* 190: Fault Collection Control Unit interrupt 1 */
+#define S32K3XX_IRQ_STCU (S32K3XX_IRQ_EXTINT + 191) /* 191: Self-Test Control Unit interrupts */
+#define S32K3XX_IRQ_MU0_MUB_EX0 (S32K3XX_IRQ_EXTINT + 192) /* 192: Messaging Unit 0, Interface B, exception 0 */
+#define S32K3XX_IRQ_MU0_MUB_EX1 (S32K3XX_IRQ_EXTINT + 193) /* 193: Messaging Unit 0, Interface B, exception 1 */
+#define S32K3XX_IRQ_MU0_MUB_EX2 (S32K3XX_IRQ_EXTINT + 194) /* 194: Messaging Unit 0, Interface B, exception 2 */
+#define S32K3XX_IRQ_MU1_MUB_EX0 (S32K3XX_IRQ_EXTINT + 195) /* 195: Messaging Unit 1, Interface B, exception 0 */
+#define S32K3XX_IRQ_MU1_MUB_EX1 (S32K3XX_IRQ_EXTINT + 196) /* 196: Messaging Unit 1, Interface B, exception 1 */
+#define S32K3XX_IRQ_MU1_MUB_EX2 (S32K3XX_IRQ_EXTINT + 197) /* 197: Messaging Unit 1, Interface B, exception 2 */
+#define S32K3XX_IRQ_RESERVED198 (S32K3XX_IRQ_EXTINT + 198) /* 198: Reserved */
+#define S32K3XX_IRQ_RESERVED199 (S32K3XX_IRQ_EXTINT + 199) /* 199: Reserved */
+#define S32K3XX_IRQ_RESERVED200 (S32K3XX_IRQ_EXTINT + 200) /* 200: Reserved */
+#define S32K3XX_IRQ_RESERVED201 (S32K3XX_IRQ_EXTINT + 201) /* 201: Reserved */
+#define S32K3XX_IRQ_MU2_MUA_EX0 (S32K3XX_IRQ_EXTINT + 202) /* 202: Messaging Unit 2, Interface A, exception 0 */
+#define S32K3XX_IRQ_MU2_MUA_EX1 (S32K3XX_IRQ_EXTINT + 203) /* 203: Messaging Unit 2, Interface A, exception 1 */
+#define S32K3XX_IRQ_MU2_MUA_EX2 (S32K3XX_IRQ_EXTINT + 204) /* 204: Messaging Unit 2, Interface A, exception 2 */
+#define S32K3XX_IRQ_MU2_MUB_EX0 (S32K3XX_IRQ_EXTINT + 205) /* 205: Messaging Unit 2, Interface B, exception 0 */
+#define S32K3XX_IRQ_MU2_MUB_EX1 (S32K3XX_IRQ_EXTINT + 206) /* 206: Messaging Unit 2, Interface B, exception 1 */
+#define S32K3XX_IRQ_MU2_MUB_EX2 (S32K3XX_IRQ_EXTINT + 207) /* 207: Messaging Unit 2, Interface B, exception 2 */
+#define S32K3XX_IRQ_RST_FCCU (S32K3XX_IRQ_EXTINT + 208) /* 208: FCCU failure to react interrupt */
+#define S32K3XX_IRQ_RST_STCU (S32K3XX_IRQ_EXTINT + 209) /* 209: STCU critical failure interrupt */
+#define S32K3XX_IRQ_RST_RGM (S32K3XX_IRQ_EXTINT + 210) /* 210: RGM functional reset escalation interrupt */
+#define S32K3XX_IRQ_RST_CMU0 (S32K3XX_IRQ_EXTINT + 211) /* 211: CMU0 reset reaction interrupt */
+#define S32K3XX_IRQ_RST_PLL_LOL (S32K3XX_IRQ_EXTINT + 212) /* 212: PLL Loss of Lock (LOL) interrupt */
+#define S32K3XX_IRQ_RST_CORECLK (S32K3XX_IRQ_EXTINT + 213) /* 213: CORE_CLK_FAIL CMU reset reaction interrupt */
+#define S32K3XX_IRQ_RESERVED214 (S32K3XX_IRQ_EXTINT + 214) /* 214: Reserved */
+#define S32K3XX_IRQ_RST_AIPSPCLK (S32K3XX_IRQ_EXTINT + 215) /* 215: AIPS_PLAT_CLK_FAIL CMU reset reaction interrupt */
+#define S32K3XX_IRQ_RESERVED216 (S32K3XX_IRQ_EXTINT + 216) /* 216: Reserved */
+#define S32K3XX_IRQ_RST_HSECLK (S32K3XX_IRQ_EXTINT + 217) /* 217: HSE_CLK_FAIL CMU reset reaction interrupt */
+#define S32K3XX_IRQ_RST_CGMCLK (S32K3XX_IRQ_EXTINT + 218) /* 218: Clock Generation Module clkdiv failed */
+#define S32K3XX_IRQ_RESERVED219 (S32K3XX_IRQ_EXTINT + 219) /* 219: Reserved */
+#define S32K3XX_IRQ_RST_HSE (S32K3XX_IRQ_EXTINT + 220) /* 220: HSE Tamper interrupt */
+#define S32K3XX_IRQ_RST_HSESNVS (S32K3XX_IRQ_EXTINT + 221) /* 221: HSE SNVS Tamper interrupt */
+#define S32K3XX_IRQ_RST_MDMDAP (S32K3XX_IRQ_EXTINT + 222) /* 222: MDM DAP destructive reset interrupt */
+#define S32K3XX_IRQ_RST_PIN (S32K3XX_IRQ_EXTINT + 223) /* 223: Pin reset interrupt */
+#define S32K3XX_IRQ_RESERVED224 (S32K3XX_IRQ_EXTINT + 224) /* 224: Reserved */
+#define S32K3XX_IRQ_RESERVED225 (S32K3XX_IRQ_EXTINT + 225) /* 225: Reserved */
+#define S32K3XX_IRQ_RESERVED226 (S32K3XX_IRQ_EXTINT + 226) /* 226: Reserved */
+#define S32K3XX_IRQ_RESERVED227 (S32K3XX_IRQ_EXTINT + 227) /* 227: Reserved */
+#define S32K3XX_IRQ_RESERVED228 (S32K3XX_IRQ_EXTINT + 228) /* 228: Reserved */
+#define S32K3XX_IRQ_RESERVED229 (S32K3XX_IRQ_EXTINT + 229) /* 229: Reserved */
+#define S32K3XX_IRQ_RESERVED230 (S32K3XX_IRQ_EXTINT + 230) /* 230: Reserved */
+#define S32K3XX_IRQ_RESERVED231 (S32K3XX_IRQ_EXTINT + 231) /* 231: Reserved */
+
+#define S32K3XX_IRQ_NEXTINT (232)
+#define S32K3XX_IRQ_NIRQS (S32K3XX_IRQ_EXTINT + S32K3XX_IRQ_NEXTINT)
+
+/* Total number of IRQs */
+
+#define NR_IRQS (S32K3XX_IRQ_NIRQS)
+
+#endif /* __ARCH_ARM_INCLUDE_S32K3XX_S32K3X4_IRQ_H */
diff --git a/arch/arm/src/s32k3xx/Kconfig b/arch/arm/src/s32k3xx/Kconfig
new file mode 100644
index 0000000000..65589fcd84
--- /dev/null
+++ b/arch/arm/src/s32k3xx/Kconfig
@@ -0,0 +1,1586 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_S32K3XX
+
+# Chip Selection
+
+choice
+ prompt "S32K3XX Chip Selection"
+ default ARCH_CHIP_S32K344
+
+#config ARCH_CHIP_S32K311
+# bool "S32K311"
+# select ARCH_FAMILY_S32K3XX_BASE
+# select S32K3XX_HAVE_I3C0
+# ---help---
+# Single Cortex-M7 @ 120 MHz, 1 MB Flash, 128 KB SRAM
+
+#config ARCH_CHIP_S32K312
+# bool "S32K312"
+# select ARCH_FAMILY_S32K3X2
+# select S32K3XX_HAVE_FLEXCAN4
+# select S32K3XX_HAVE_FLEXCAN5
+# select S32K3XX_HAVE_LPUART4
+# select S32K3XX_HAVE_LPUART5
+# select S32K3XX_HAVE_LPUART6
+# select S32K3XX_HAVE_LPUART7
+# ---help---
+# Single Cortex-M7 @ 120 MHz, 2 MB Flash, 192 KB SRAM
+
+config ARCH_CHIP_S32K314
+ bool "S32K314"
+ select ARCH_FAMILY_S32K3X4
+ ---help---
+ Single Cortex-M7 @ 160 MHz, 4 MB Flash, 512 KB SRAM
+
+#config ARCH_CHIP_S32K322
+# bool "S32K322"
+# select ARCH_FAMILY_S32K3X2
+# select S32K3XX_HAVE_ENET
+# select S32K3XX_HAVE_QSPI
+# select S32K3XX_HAVE_SAI0
+# select S32K3XX_HAVE_SAI1
+# ---help---
+# Single Cortex-M7 @ 160 MHz, 2 MB Flash, 256 KB SRAM
+
+config ARCH_CHIP_S32K324
+ bool "S32K324"
+ select ARCH_FAMILY_S32K3X4
+ ---help---
+ Dual Cortex-M7 @ 160 MHz, 4 MB Flash, 512 KB SRAM
+
+#config ARCH_CHIP_S32K341
+# bool "S32K341"
+# select ARCH_FAMILY_S32K3XX_BASE
+# select S32K3XX_HAVE_ENET
+# select S32K3XX_HAVE_FLEXCAN3
+# select S32K3XX_HAVE_I3C0
+# select S32K3XX_HAVE_QSPI
+# select S32K3XX_HAVE_SAI0
+# select S32K3XX_HAVE_SAI1
+# ---help---
+# Lock-Step Cortex-M7 @ 160 MHz, 1 MB Flash, 256 KB SRAM
+
+#config ARCH_CHIP_S32K342
+# bool "S32K342"
+# select ARCH_FAMILY_S32K3X2
+# select S32K3XX_HAVE_ENET
+# select S32k3XX_HAVE_QSPI
+# select S32K3XX_HAVE_SAI0
+# select S32K3XX_HAVE_SAI1
+# ---help---
+# Lock-Step Cortex-M7 @ 160 MHz, 2 MB Flash, 256 KB SRAM
+
+config ARCH_CHIP_S32K344
+ bool "S32K344"
+ select ARCH_FAMILY_S32K3X4
+ ---help---
+ Lock-Step Cortex-M7 @ 160 MHz, 4 MB Flash, 512 KB SRAM
+
+#config ARCH_CHIP_S32K328
+# bool "S32K328"
+# select ARCH_FAMILY_S32K3X8
+# ---help---
+# Dual Cortex-M7 @ 160 MHz, 8 MB Flash, 1152 KB SRAM
+
+#config ARCH_CHIP_S32K338
+# bool "S32K338"
+# select ARCH_FAMILY_S32K3X8
+# ---help---
+# Triple Cortex-M7 @ 240 MHz, 8 MB Flash, 1152 KB SRAM
+
+#config ARCH_CHIP_S32K348
+# bool "S32K348"
+# select ARCH_FAMILY_S32K3X8
+# ---help---
+# Lock-Step Cortex-M7 @ 160 MHz, 8 MB Flash, 1152 KB SRAM
+
+#config ARCH_CHIP_S32K358
+# bool "S32K358"
+# select ARCH_FAMILY_S32K3X8
+# ---help---
+# Lock-Step Cortex-M7 + Single Cortex-M7 @ 240 MHz, 8 MB Flash, 1152 KB SRAM
+
+endchoice # S32K3XX Chip Selection
+
+# Chip Family
+
+config ARCH_FAMILY_S32K3X2
+ bool
+ select ARCH_FAMILY_S32K3XX_BASE
+ select S32K3XX_HAVE_FLEXCAN3
+ select S32K3XX_HAVE_I3C0
+
+config ARCH_FAMILY_S32K3X4
+ bool
+ select ARCH_FAMILY_S32K3XX_BASE
+ select S32K3XX_HAVE_EMIOS2
+ select S32K3XX_HAVE_ENET
+ select S32K3XX_HAVE_FLEXCAN3
+ select S32K3XX_HAVE_FLEXCAN4
+ select S32K3XX_HAVE_FLEXCAN5
+ select S32K3XX_HAVE_LPSPI4
+ select S32K3XX_HAVE_LPSPI5
+ select S32K3XX_HAVE_LPUART4
+ select S32K3XX_HAVE_LPUART5
+ select S32K3XX_HAVE_LPUART6
+ select S32K3XX_HAVE_LPUART7
+ select S32K3XX_HAVE_LPUART8
+ select S32K3XX_HAVE_LPUART9
+ select S32K3XX_HAVE_LPUART10
+ select S32K3XX_HAVE_LPUART11
+ select S32K3XX_HAVE_LPUART12
+ select S32K3XX_HAVE_LPUART13
+ select S32K3XX_HAVE_LPUART14
+ select S32K3XX_HAVE_LPUART15
+ select S32K3XX_HAVE_QSPI
+ select S32K3XX_HAVE_SAI0
+ select S32K3XX_HAVE_SAI1
+
+config ARCH_FAMILY_S32K3X8
+ bool
+ select ARCH_FAMILY_S32K3XX_BASE
+ select S32K3XX_HAVE_EMIOS2
+ select S32K3XX_HAVE_ENET
+ select S32K3XX_HAVE_FLEXCAN3
+ select S32K3XX_HAVE_FLEXCAN4
+ select S32K3XX_HAVE_FLEXCAN5
+ select S32K3XX_HAVE_FLEXCAN6
+ select S32K3XX_HAVE_FLEXCAN7
+ select S32K3XX_HAVE_I3C0
+ select S32K3XX_HAVE_LPSPI4
+ select S32K3XX_HAVE_LPSPI5
+ select S32K3XX_HAVE_LPUART4
+ select S32K3XX_HAVE_LPUART5
+ select S32K3XX_HAVE_LPUART6
+ select S32K3XX_HAVE_LPUART7
+ select S32K3XX_HAVE_LPUART8
+ select S32K3XX_HAVE_LPUART9
+ select S32K3XX_HAVE_LPUART10
+ select S32K3XX_HAVE_LPUART11
+ select S32K3XX_HAVE_LPUART12
+ select S32K3XX_HAVE_LPUART13
+ select S32K3XX_HAVE_LPUART14
+ select S32K3XX_HAVE_LPUART15
+ select S32K3XX_HAVE_QSPI
+ select S32K3XX_HAVE_SAI0
+ select S32K3XX_HAVE_SAI1
+ select S32k3XX_HAVE_SDHC
+
+config ARCH_FAMILY_S32K3XX_BASE
+ bool
+ select ARCH_CORTEXM7
+ select ARCH_HAVE_FPU
+ select ARCH_HAVE_FETCHADD
+ select ARMV7M_HAVE_ICACHE
+ select ARMV7M_HAVE_DCACHE
+ select ARMV7M_HAVE_ITCM
+ select ARMV7M_HAVE_DTCM
+
+# Chip Capabilities
+
+config S32K3XX_HAVE_EMIOS2
+ bool
+ default n
+
+config S32K3XX_HAVE_ENET
+ bool
+ default n
+ select ARCH_HAVE_PHY
+ select ARCH_PHY_INTERRUPT
+ select ARCH_HAVE_NETDEV_STATISTICS
+
+config S32K3XX_HAVE_FLEXCAN3
+ bool
+ default n
+
+config S32K3XX_HAVE_FLEXCAN4
+ bool
+ default n
+
+config S32K3XX_HAVE_FLEXCAN5
+ bool
+ default n
+
+config S32K3XX_HAVE_FLEXCAN6
+ bool
+ default n
+
+config S32K3XX_HAVE_FLEXCAN7
+ bool
+ default n
+
+config S32K3XX_HAVE_I3C0
+ bool
+ default n
+
+config S32K3XX_HAVE_LPSPI4
+ bool
+ default n
+
+config S32K3XX_HAVE_LPSPI5
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART4
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART5
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART6
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART7
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART8
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART9
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART10
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART11
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART12
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART13
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART14
+ bool
+ default n
+
+config S32K3XX_HAVE_LPUART15
+ bool
+ default n
+
+config S32K3XX_HAVE_QSPI
+ bool
+ default n
+
+config S32K3XX_HAVE_SAI0
+ bool
+ default n
+
+config S32K3XX_HAVE_SAI1
+ bool
+ default n
+
+config S32K3XX_HAVE_SDHC
+ bool
+ default n
+ select ARCH_HAVE_SDIO
+
+
+menu "S32K3XX Heap Configuration"
+
+config S32K3XX_DTCM_HEAP
+ bool "Add DTCM to heap"
+ ---help---
+ Select to add the entire DTCM to the heap
+
+endmenu # S32K3XX Heap Configuration
+
+# Peripheral Group Selections
+
+config S32K3XX_EMIOS
+ bool
+ default n
+
+config S32K3XX_FLEXCAN
+ bool
+ default n
+ select NET_CAN_HAVE_CANFD
+ select NET_CAN_HAVE_TX_DEADLINE
+
+config S32K3XX_LPI2C
+ bool
+ default n
+
+config S32K3XX_LPSPI
+ bool
+ default n
+ select SPI
+
+config S32K3XX_LPUART
+ bool
+ default n
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+# Peripheral Selection
+
+menu "S32K3XX Peripheral Selection"
+
+config S32K3XX_EDMA
+ bool "eDMA"
+ select ARCH_DMA
+ default n
+ ---help---
+ Support DMA
+
+menu "eMIOS"
+
+config S32K3XX_EMIOS0
+ bool "eMIOS0"
+ default n
+ select S32K3XX_EMIOS
+
+config S32K3XX_EMIOS1
+ bool "eMIOS1"
+ default n
+ select S32K3XX_EMIOS
+
+config S32K3XX_EMIOS2
+ bool "eMIOS2"
+ default n
+ select S32K3XX_EMIOS
+ depends on S32K3XX_HAVE_EMIOS2
+
+endmenu # eMIOS
+
+config S32K3XX_ENET
+ bool "Ethernet"
+ default n
+ depends on S32K3XX_HAVE_ENET
+
+
+config S32K3XX_QSPI
+ bool "QSPI Flash"
+ default n
+ depends on S32K3XX_HAVE_QSPI
+
+menu "FlexCAN"
+
+config S32K3XX_FLEXCAN0
+ bool "FlexCAN0"
+ default n
+ select S32K3XX_FLEXCAN
+
+config S32K3XX_FLEXCAN1
+ bool "FlexCAN1"
+ default n
+ select S32K3XX_FLEXCAN
+
+config S32K3XX_FLEXCAN2
+ bool "FlexCAN2"
+ default n
+ select S32K3XX_FLEXCAN
+
+config S32K3XX_FLEXCAN3
+ bool "FlexCAN3"
+ default n
+ select S32K3XX_FLEXCAN
+ depends on S32K3XX_HAVE_FLEXCAN3
+
+config S32K3XX_FLEXCAN4
+ bool "FlexCAN4"
+ default n
+ select S32K3XX_FLEXCAN
+ depends on S32K3XX_HAVE_FLEXCAN4
+
+config S32K3XX_FLEXCAN5
+ bool "FlexCAN5"
+ default n
+ select S32K3XX_FLEXCAN
+ depends on S32K3XX_HAVE_FLEXCAN5
+
+config S32K3XX_FLEXCAN6
+ bool "FlexCAN6"
+ default n
+ select S32K3XX_FLEXCAN
+ depends on S32K3XX_HAVE_FLEXCAN6
+
+config S32K3XX_FLEXCAN7
+ bool "FlexCAN7"
+ default n
+ select S32K3XX_FLEXCAN
+ depends on S32K3XX_HAVE_FLEXCAN7
+
+endmenu # FlexCAN
+
+menu "LPI2C"
+
+config S32K3XX_LPI2C0
+ bool "LPI2C0"
+ default n
+ select S32K3XX_LPI2C
+
+config S32K3XX_LPI2C1
+ bool "LPI2C1"
+ default n
+ select S32K3XX_LPI2C
+
+endmenu # LPI2C
+
+menu "LPSPI"
+
+config S32K3XX_LPSPI0
+ bool "LPSPI0"
+ default n
+ select S32K3XX_LPSPI
+
+config S32K3XX_LPSPI1
+ bool "LPSPI1"
+ default n
+ select S32K3XX_LPSPI
+
+config S32K3XX_LPSPI2
+ bool "LPSPI2"
+ default n
+ select S32K3XX_LPSPI
+
+config S32K3XX_LPSPI3
+ bool "LPSPI3"
+ default n
+ select S32K3XX_LPSPI
+
+config S32K3XX_LPSPI4
+ bool "LPSPI4"
+ default n
+ select S32K3XX_LPSPI
+ depends on S32K3XX_HAVE_LPSPI4
+
+config S32K3XX_LPSPI5
+ bool "LPSPI5"
+ default n
+ select S32K3XX_LPSPI
+ depends on S32K3XX_HAVE_LPSPI5
+
+endmenu # LPSPI
+
+menu "LPUART"
+
+config S32K3XX_LPUART0
+ bool "LPUART0"
+ default n
+ select S32K3XX_LPUART
+ select LPUART0_SERIALDRIVER
+
+config S32K3XX_LPUART1
+ bool "LPUART1"
+ default n
+ select S32K3XX_LPUART
+ select LPUART1_SERIALDRIVER
+
+config S32K3XX_LPUART2
+ bool "LPUART2"
+ default n
+ select S32K3XX_LPUART
+ select LPUART2_SERIALDRIVER
+
+config S32K3XX_LPUART3
+ bool "LPUART3"
+ default n
+ select S32K3XX_LPUART
+ select LPUART3_SERIALDRIVER
+
+config S32K3XX_LPUART4
+ bool "LPUART4"
+ default n
+ select S32K3XX_LPUART
+ select LPUART4_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART4
+
+config S32K3XX_LPUART5
+ bool "LPUART5"
+ default n
+ select S32K3XX_LPUART
+ select LPUART5_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART5
+
+config S32K3XX_LPUART6
+ bool "LPUART6"
+ default n
+ select S32K3XX_LPUART
+ select LPUART6_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART6
+
+config S32K3XX_LPUART7
+ bool "LPUART7"
+ default n
+ select S32K3XX_LPUART
+ select LPUART7_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART7
+
+config S32K3XX_LPUART8
+ bool "LPUART8"
+ default n
+ select S32K3XX_LPUART
+ select LPUART8_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART8
+
+config S32K3XX_LPUART9
+ bool "LPUART9"
+ default n
+ select S32K3XX_LPUART
+ select LPUART9_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART9
+
+config S32K3XX_LPUART10
+ bool "LPUART10"
+ default n
+ select S32K3XX_LPUART
+ select LPUART10_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART10
+
+config S32K3XX_LPUART11
+ bool "LPUART11"
+ default n
+ select S32K3XX_LPUART
+ select LPUART11_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART11
+
+config S32K3XX_LPUART12
+ bool "LPUART12"
+ default n
+ select S32K3XX_LPUART
+ select LPUART12_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART12
+
+config S32K3XX_LPUART13
+ bool "LPUART13"
+ default n
+ select S32K3XX_LPUART
+ select LPUART13_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART13
+
+config S32K3XX_LPUART14
+ bool "LPUART14"
+ default n
+ select S32K3XX_LPUART
+ select LPUART14_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART14
+
+config S32K3XX_LPUART15
+ bool "LPUART15"
+ default n
+ select S32K3XX_LPUART
+ select LPUART15_SERIALDRIVER
+ depends on S32K3XX_HAVE_LPUART15
+
+endmenu # LPUART
+
+config S32K3XX_RTC
+ bool "RTC"
+ default n
+
+config S32K3XX_FS26
+ bool "FS26 SBC Disable watchdog"
+ default n
+ ---help---
+ Disables the FS26 watchdog so that the S32K3XX MCU does not get resetted.
+ Engineering development purpose only, not for use in production.
+ Please refer to the FS26 Datasheet.
+
+endmenu # S32K3XX Peripheral Selection
+
+menu "S32K3XX eMIOS PWM Configuration"
+ depends on S32K3XX_FTM
+
+config S32K3XX_EMIOS0_CH0_PWM
+ bool "eMIOS0 Channel 0 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH1_PWM
+ bool "eMIOS0 Channel 1 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH2_PWM
+ bool "eMIOS0 Channel 2 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH3_PWM
+ bool "eMIOS0 Channel 3 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH4_PWM
+ bool "eMIOS0 Channel 4 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH5_PWM
+ bool "eMIOS0 Channel 5 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH6_PWM
+ bool "eMIOS0 Channel 6 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH7_PWM
+ bool "eMIOS0 Channel 7 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH8_PWM
+ bool "eMIOS0 Channel 8 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH9_PWM
+ bool "eMIOS0 Channel 9 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH10_PWM
+ bool "eMIOS0 Channel 10 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH11_PWM
+ bool "eMIOS0 Channel 11 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH12_PWM
+ bool "eMIOS0 Channel 12 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH13_PWM
+ bool "eMIOS0 Channel 13 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH14_PWM
+ bool "eMIOS0 Channel 14 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH15_PWM
+ bool "eMIOS0 Channel 15 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH16_PWM
+ bool "eMIOS0 Channel 16 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH17_PWM
+ bool "eMIOS0 Channel 17 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH18_PWM
+ bool "eMIOS0 Channel 18 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH19_PWM
+ bool "eMIOS0 Channel 19 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH20_PWM
+ bool "eMIOS0 Channel 20 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH21_PWM
+ bool "eMIOS0 Channel 21 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH22_PWM
+ bool "eMIOS0 Channel 22 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS0_CH23_PWM
+ bool "eMIOS0 Channel 23 PWM"
+ default n
+ depends on S32K3XX_EMIOS0
+
+config S32K3XX_EMIOS1_CH0_PWM
+ bool "eMIOS1 Channel 0 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH1_PWM
+ bool "eMIOS1 Channel 1 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH2_PWM
+ bool "eMIOS1 Channel 2 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH3_PWM
+ bool "eMIOS1 Channel 3 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH4_PWM
+ bool "eMIOS1 Channel 4 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH5_PWM
+ bool "eMIOS1 Channel 5 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH6_PWM
+ bool "eMIOS1 Channel 6 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH7_PWM
+ bool "eMIOS1 Channel 7 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH8_PWM
+ bool "eMIOS1 Channel 8 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH9_PWM
+ bool "eMIOS1 Channel 9 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH10_PWM
+ bool "eMIOS1 Channel 10 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH11_PWM
+ bool "eMIOS1 Channel 11 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH12_PWM
+ bool "eMIOS1 Channel 12 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH13_PWM
+ bool "eMIOS1 Channel 13 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH14_PWM
+ bool "eMIOS1 Channel 14 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH15_PWM
+ bool "eMIOS1 Channel 15 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH16_PWM
+ bool "eMIOS1 Channel 16 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH17_PWM
+ bool "eMIOS1 Channel 17 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH18_PWM
+ bool "eMIOS1 Channel 18 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH19_PWM
+ bool "eMIOS1 Channel 19 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH20_PWM
+ bool "eMIOS1 Channel 20 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH21_PWM
+ bool "eMIOS1 Channel 21 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH22_PWM
+ bool "eMIOS1 Channel 22 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS1_CH23_PWM
+ bool "eMIOS1 Channel 23 PWM"
+ default n
+ depends on S32K3XX_EMIOS1
+
+config S32K3XX_EMIOS2_CH0_PWM
+ bool "eMIOS2 Channel 0 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH1_PWM
+ bool "eMIOS2 Channel 1 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH2_PWM
+ bool "eMIOS2 Channel 2 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH3_PWM
+ bool "eMIOS2 Channel 3 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH4_PWM
+ bool "eMIOS2 Channel 4 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH5_PWM
+ bool "eMIOS2 Channel 5 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH6_PWM
+ bool "eMIOS2 Channel 6 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH7_PWM
+ bool "eMIOS2 Channel 7 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH8_PWM
+ bool "eMIOS2 Channel 8 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH9_PWM
+ bool "eMIOS2 Channel 9 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH10_PWM
+ bool "eMIOS2 Channel 10 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH11_PWM
+ bool "eMIOS2 Channel 11 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH12_PWM
+ bool "eMIOS2 Channel 12 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH13_PWM
+ bool "eMIOS2 Channel 13 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH14_PWM
+ bool "eMIOS2 Channel 14 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH15_PWM
+ bool "eMIOS2 Channel 15 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH16_PWM
+ bool "eMIOS2 Channel 16 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH17_PWM
+ bool "eMIOS2 Channel 17 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH18_PWM
+ bool "eMIOS2 Channel 18 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH19_PWM
+ bool "eMIOS2 Channel 19 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH20_PWM
+ bool "eMIOS2 Channel 20 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH21_PWM
+ bool "eMIOS2 Channel 21 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH22_PWM
+ bool "eMIOS2 Channel 22 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+config S32K3XX_EMIOS2_CH23_PWM
+ bool "eMIOS2 Channel 23 PWM"
+ default n
+ depends on S32K3XX_EMIOS2
+
+endmenu # S32K3XX eMIOS PWM Configuration
+
+config S32K3XX_SWT_DISABLE
+ bool "Disable software watchdog timer on reset"
+ default y
+
+menu "S32K3XX GPIO Interrupt Configuration"
+
+config S32K3XX_GPIOIRQ
+ bool "GPIO pin interrupts"
+ ---help---
+ Enable support for interrupting GPIO pins
+
+if S32K3XX_GPIOIRQ
+
+config S32K3XX_EIRQINTS
+ bool "EIRQ interrupts"
+ ---help---
+ Enable support for EIRQ interrupts
+
+config S32K3XX_WKPUINTS
+ bool "WKPU interrupts"
+ ---help---
+ Enable support for WKPU interrupts
+
+endif # S32K3XX_GPIOIRQ
+
+endmenu # S32K3XX GPIO Interrupt Configuration
+
+menu "eDMA Configuration"
+ depends on S32K3XX_EDMA
+
+config S32K3XX_EDMA_NTCD
+ int "Number of transfer descriptors"
+ default 32
+ ---help---
+ Number of pre-allocated transfer descriptors. Needed for scatter-
+ gather DMA. Make to be set to zero to disable in-memory TCDs in
+ which case only the TCD channel registers will be used and scatter-
+ will not be supported.
+
+config S32K3XX_EDMA_ELINK
+ bool "Channeling Linking"
+ default y
+ ---help---
+ This option enables optional minor or major loop channel linking:
+
+ Minor loop channel linking: As the channel completes the minor
+ loop, this flag enables linking to another channel. The link target
+ channel initiates a channel service request via an internal
+ mechanism that sets the TCDn_CSR[START] bit of the specified
+ channel.
+
+ If minor loop channel linking is disabled, this link mechanism is
+ suppressed in favor of the major loop channel linking.
+
+ Major loop channel linking: As the channel completes the minor
+ loop, this option enables the linking to another channel. The link
+ target channel initiates a channel service request via an internal
+ mechanism that sets the TCDn_CSR[START] bit of the linked channel.
+
+config S32K3XX_EDMA_ERCA
+ bool "Round Robin Channel Arbitration"
+ default y
+ ---help---
+ Normally, a fixed priority arbitration is used for channel
+ selection. If this option is selected, round robin arbitration is
+ used for channel selection.
+
+config S32K3XX_EDMA_HOE
+ bool "Halt On Error"
+ default y
+ ---help---
+ Any error causes the HALT bit to set. Subsequently, all service
+ requests are ignored until the HALT bit is cleared.
+
+config S32K3XX_EDMA_CLM
+ bool "Continuous Link Mode"
+ default n
+ ---help---
+ By default, A minor loop channel link made to itself goes through
+ channel arbitration before being activated again. If this option is
+ selected, a minor loop channel link made to itself does not go
+ through channel arbitration before being activated again. Upon minor
+ loop completion, the channel activates again if that channel has a
+ minor loop channel link enabled and the link channel is itself. This
+ effectively applies the minor loop offsets and restarts the next
+ minor loop.
+
+config S32K3XX_EDMA_EMLIM
+ bool "Minor Loop Mapping"
+ default n
+ ---help---
+ Normally TCD word 2 is a 32-bit NBYTES field. When this option is
+ enabled, TCD word 2 is redefined to include individual enable fields,
+ an offset field, and the NBYTES field. The individual enable fields
+ allow the minor loop offset to be applied to the source address, the
+ destination address, or both. The NBYTES field is reduced when either
+ offset is enabled.
+
+config S32K3XX_EDMA_EDBG
+ bool "Enable Debug"
+ default n
+ ---help---
+ When in debug mode, the DMA stalls the start of a new channel. Executing
+ channels are allowed to complete. Channel execution resumes when the
+ system exits debug mode or the EDBG bit is cleared
+
+endmenu # eDMA Global Configuration
+
+menu "LPSPI Configuration"
+ depends on S32K3XX_LPSPI
+
+config S32K3XX_LPSPI_DWORD
+ bool "DWORD up to 64 bit transfer support"
+ default n
+
+config S32K3XX_LPSPI_DMA
+ bool "SPI DMA"
+ depends on S32K3XX_EDMA
+ default n
+ ---help---
+ Use DMA to improve SPI transfer performance.
+
+config S32K3XX_LPSPI0_DMA
+ bool "LPSPI0 DMA"
+ default n
+ depends on S32K3XX_LPSPI0 && S32K3XX_LPSPI_DMA
+ ---help---
+ Use DMA to improve LPSPI0 transfer performance.
+
+config S32K3XX_LPSPI1_DMA
+ bool "LPSPI1 DMA"
+ default n
+ depends on S32K3XX_LPSPI1 && S32K3XX_LPSPI_DMA
+ ---help---
+ Use DMA to improve LPSPI1 transfer performance.
+
+config S32K3XX_LPSPI2_DMA
+ bool "LPSPI2 DMA"
+ default n
+ depends on S32K3XX_LPSPI2 && S32K3XX_LPSPI_DMA
+ ---help---
+ Use DMA to improve LPSPI2 transfer performance.
+
+config S32K3XX_LPSPI3_DMA
+ bool "LPSPI3 DMA"
+ default n
+ depends on S32K3XX_LPSPI3 && S32K3XX_LPSPI_DMA
+ ---help---
+ Use DMA to improve LPSPI3 transfer performance.
+
+config S32K3XX_LPSPI4_DMA
+ bool "LPSPI4 DMA"
+ default n
+ depends on S32K3XX_LPSPI4 && S32K3XX_LPSPI_DMA
+ ---help---
+ Use DMA to improve LPSPI4 transfer performance.
+
+
+config S32K3XX_LPSPI5_DMA
+ bool "LPSPI5 DMA"
+ default n
+ depends on S32K3XX_LPSPI5 && S32K3XX_LPSPI_DMA
+ ---help---
+ Use DMA to improve LPSPI5 transfer performance.
+
+
+config S32K3XX_LPSPI_DMATHRESHOLD
+ int "SPI DMA threshold"
+ default 4
+ depends on KINETIS_SPI_DMA
+ ---help---
+ When SPI DMA is enabled, small DMA transfers will still be performed
+ by polling logic. But we need a threshold value to determine what
+ is small.
+
+config S32K3XX_LPSPI0_PINCFG
+ int "LPSPI0 input & data pin config"
+ depends on S32K3XX_LPSPI0
+ default 0
+ ---help---
+ Configures which pins are used for input and output data during serial transfers.
+ 0 - SIN is used for input data and SOUT is used for output data
+ 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
+ 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ 3 - SOUT is used for input data and SIN is used for output data
+
+config S32K3XX_LPSPI1_PINCFG
+ int "LPSPI1 input & data pin config"
+ depends on S32K3XX_LPSPI1
+ default 0
+ ---help---
+ Configures which pins are used for input and output data during serial transfers.
+ 0 - SIN is used for input data and SOUT is used for output data
+ 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
+ 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ 3 - SOUT is used for input data and SIN is used for output data
+
+config S32K3XX_LPSPI2_PINCFG
+ int "LPSPI2 input & data pin config"
+ depends on S32K3XX_LPSPI2
+ default 0
+ ---help---
+ Configures which pins are used for input and output data during serial transfers.
+ 0 - SIN is used for input data and SOUT is used for output data
+ 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
+ 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ 3 - SOUT is used for input data and SIN is used for output data
+
+config S32K3XX_LPSPI3_PINCFG
+ int "LPSPI3 input & data pin config"
+ depends on S32K3XX_LPSPI3
+ default 0
+ ---help---
+ Configures which pins are used for input and output data during serial transfers.
+ 0 - SIN is used for input data and SOUT is used for output data
+ 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
+ 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ 3 - SOUT is used for input data and SIN is used for output data
+
+config S32K3XX_LPSPI4_PINCFG
+ int "LPSPI4 input & data pin config"
+ depends on S32K3XX_LPSPI4
+ default 0
+ ---help---
+ Configures which pins are used for input and output data during serial transfers.
+ 0 - SIN is used for input data and SOUT is used for output data
+ 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
+ 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ 3 - SOUT is used for input data and SIN is used for output data
+
+config S32K3XX_LPSPI5_PINCFG
+ int "LPSPI5 input & data pin config"
+ depends on S32K3XX_LPSPI5
+ default 0
+ ---help---
+ Configures which pins are used for input and output data during serial transfers.
+ 0 - SIN is used for input data and SOUT is used for output data
+ 1 - SIN is used for both input and output data, only half-duplex serial transfers are supported
+ 2 - SOUT is used for both input and output data, only half-duplex serial transfers are supported
+ 3 - SOUT is used for input data and SIN is used for output data
+
+endmenu # LPSPI Configuration
+
+menu "LPI2C0 Configuration"
+ depends on S32K3XX_LPI2C0
+
+config LPI2C0_BUSYIDLE
+ int "Bus idle timeout period in clock cycles"
+ default 0
+
+config LPI2C0_FILTSCL
+ int "I2C master digital glitch filters for SCL input in clock cycles"
+ default 0
+
+config LPI2C0_FILTSDA
+ int "I2C master digital glitch filters for SDA input in clock cycles"
+ default 0
+
+endmenu # LPI2C0 Configuration
+
+menu "LPI2C1 Configuration"
+ depends on S32K3XX_LPI2C1
+
+config LPI2C1_BUSYIDLE
+ int "Bus idle timeout period in clock cycles"
+ default 0
+
+config LPI2C1_FILTSCL
+ int "I2C master digital glitch filters for SCL input in clock cycles"
+ default 0
+
+config LPI2C1_FILTSDA
+ int "I2C master digital glitch filters for SDA input in clock cycles"
+ default 0
+
+endmenu # LPI2C1 Configuration
+
+
+menu "LPUART Configuration"
+ depends on S32K3XX_LPUART
+
+config S32K3XX_LPUART_INVERT
+ bool "Signal Invert Support"
+ default n
+
+config S32K3XX_LPUART_SINGLEWIRE
+ bool "Signal Wire Support"
+ default n
+
+endmenu
+
+menu "Ethernet Configuration"
+ depends on S32K3XX_ENET
+
+config S32K3XX_ENET_NRXBUFFERS
+ int "Number Rx buffers"
+ default 6
+
+config S32K3XX_ENET_NTXBUFFERS
+ int "Number Tx buffers"
+ default 2
+
+config S32K3XX_ENET_ENHANCEDBD
+ bool # not optional
+ default n
+
+config S32K3XX_ENET_NETHIFS
+ int # Not optional
+ default 1
+
+config S32K3XX_ENET_PHYINIT
+ bool "Board-specific PHY Initialization"
+ default n
+ ---help---
+ Some boards require specialized initialization of the PHY before it
+ can be used. This may include such things as configuring GPIOs,
+ resetting the PHY, etc. If CONFIG_S32K3XX_ENET_PHYINIT is defined in
+ the configuration then the board specific logic must provide
+ imxrt_phy_boardinitialize(); The i.MXRT ENET driver will call this
+ function one time before it first uses the PHY.
+
+endmenu # S32K3XX_ENET
+
+menu "FlexCAN0 Configuration"
+ depends on S32K3XX_FLEXCAN0
+
+config FLEXCAN0_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN0_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN0_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN0_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN0_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN0_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN0 Configuration
+
+menu "FlexCAN1 Configuration"
+ depends on S32K3XX_FLEXCAN1
+
+config FLEXCAN1_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN1_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN1_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN1_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN1_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN1_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN1 Configuration
+
+menu "FlexCAN2 Configuration"
+ depends on S32K3XX_FLEXCAN2
+
+config FLEXCAN2_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN2_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN2_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN2_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN2_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN2_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN2 Configuration
+
+menu "FlexCAN3 Configuration"
+ depends on S32K3XX_FLEXCAN3
+
+config FLEXCAN3_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN3_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN3_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN3_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN3_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN3_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN3 Configuration
+
+menu "FlexCAN4 Configuration"
+ depends on S32K3XX_FLEXCAN4
+
+config FLEXCAN4_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN4_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN4_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN4_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN4_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN4_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN4 Configuration
+
+menu "FlexCAN5 Configuration"
+ depends on S32K3XX_FLEXCAN5
+
+config FLEXCAN5_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN5_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN5_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN5_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN5_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN5_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN5 Configuration
+
+menu "FlexCAN6 Configuration"
+ depends on S32K3XX_FLEXCAN6
+
+config FLEXCAN6_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN6_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN6_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN6_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN6_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN6_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN6 Configuration
+
+menu "FlexCAN7 Configuration"
+ depends on S32K3XX_FLEXCAN7
+
+config FLEXCAN7_BITRATE
+ int "CAN bitrate"
+ depends on !NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN7_SAMPLEP
+ int "CAN sample point"
+ depends on !NET_CAN_CANFD
+ default 80
+
+config FLEXCAN7_ARBI_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 1000000
+
+config FLEXCAN7_ARBI_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 80
+
+config FLEXCAN7_DATA_BITRATE
+ int "CAN FD Arbitration phase bitrate"
+ depends on NET_CAN_CANFD
+ default 4000000
+
+config FLEXCAN7_DATA_SAMPLEP
+ int "CAN FD Arbitration phase sample point"
+ depends on NET_CAN_CANFD
+ default 90
+
+endmenu # FlexCAN7 Configuration
+
+menu "QSPI Configuration"
+ depends on S32K3XX_QSPI
+
+config S32K3XX_QSPI_INTERRUPTS
+ bool "QSPI interrupt"
+ default n
+
+config S32K3XX_QSPI_DMA
+ bool "QSPI DMA"
+ default n
+
+endmenu # FlexCAN0 Configuration
+
+menu "FS26 Configuration"
+ depends on S32K3XX_FS26
+
+config FS26_SPI_FREQUENCY
+ int "FS26 Spi frequency"
+ default 100000
+
+endmenu
+
+endif # ARCH_CHIP_S32K3XX
diff --git a/arch/arm/src/s32k3xx/Make.defs b/arch/arm/src/s32k3xx/Make.defs
new file mode 100644
index 0000000000..1f3f2a55fd
--- /dev/null
+++ b/arch/arm/src/s32k3xx/Make.defs
@@ -0,0 +1,82 @@
+############################################################################
+# arch/arm/src/s32k3xx/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Copyright 2022 NXP
+
+# Common ARM and Cortex-M7 files
+
+include armv7-m/Make.defs
+
+# Required S32K3 files
+
+CHIP_ASRCS += startup.S
+
+CHIP_CSRCS = s32k3xx_irq.c s32k3xx_clrpend.c s32k3xx_flashboot.c
+CHIP_CSRCS += s32k3xx_start.c s32k3xx_lowputc.c s32k3xx_clockconfig.c
+CHIP_CSRCS += s32k3xx_periphclocks.c s32k3xx_pin.c s32k3xx_pingpio.c
+CHIP_CSRCS += s32k3xx_idle.c s32k3xx_allocateheap.c
+
+# Configuration-dependent S32K3 files
+
+ifneq ($(CONFIG_SCHED_TICKLESS),y)
+CHIP_CSRCS += s32k3xx_timerisr.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPUART),y)
+CHIP_CSRCS += s32k3xx_serial.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_GPIOIRQ),y)
+CHIP_CSRCS += s32k3xx_pinirq.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_EDMA),y)
+CHIP_CSRCS += s32k3xx_pindma.c
+CHIP_CSRCS += s32k3xx_edma.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPI2C),y)
+CHIP_CSRCS += s32k3xx_lpi2c.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPSPI),y)
+CHIP_CSRCS += s32k3xx_lpspi.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_ENET),y)
+CHIP_CSRCS += s32k3xx_emac.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_FLEXCAN),y)
+CHIP_CSRCS += s32k3xx_flexcan.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_FS26),y)
+CHIP_CSRCS += s32k3xx_fs26.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_QSPI),y)
+CHIP_CSRCS += s32k3xx_qspi.c
+endif
+
+# Make sure that the S32K3 common directory in included in the VPATH
+
+VPATH += chip/common
+VPATH += chip/s32k3xx
diff --git a/arch/arm/src/s32k3xx/chip.h b/arch/arm/src/s32k3xx/chip.h
new file mode 100644
index 0000000000..bff5474a75
--- /dev/null
+++ b/arch/arm/src/s32k3xx/chip.h
@@ -0,0 +1,71 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_CHIP_H
+#define __ARCH_ARM_SRC_S32K3XX_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/* Include the memory map and the chip definitions file.
+ * Other chip hardware files should then include this file for the proper
+ * setup.
+ */
+
+#include <arch/irq.h>
+#include "hardware/s32k3xx_memorymap.h"
+
+/* The common ARMv6/7-M vector handling logic expects the following
+ * definitions in this file.
+ * ARMV6/7M_PERIPHERAL_INTERRUPTS provides the number of supported
+ * external interrupts which, for this architecture, is provided in the
+ * arch/s32k3xx/irq.h header file.
+ */
+
+#define ARMV6M_PERIPHERAL_INTERRUPTS S32K3XX_IRQ_NEXTINT
+#define ARMV7M_PERIPHERAL_INTERRUPTS S32K3XX_IRQ_NEXTINT
+
+/* Cache line sizes (in bytes)for the S32K3XX */
+
+#define ARMV7M_DCACHE_LINESIZE 32 /* 4 bytes */
+#define ARMV7M_ICACHE_LINESIZE 64 /* 8 bytes */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_CHIP_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h b/arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h
new file mode 100644
index 0000000000..8b1c5b30fd
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h
@@ -0,0 +1,1642 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k344_pinmux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K344_PINMUX_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K344_PINMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <s32k3xx_pin.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* In most cases, there are alternative configurations for various pins.
+ * Those alternative pins are labeled with a suffix like _1, _2, etc. in
+ * order to distinguish them. Logic in the board.h file must select the
+ * correct pin configuration for the board by defining a pin
+ * configuration (with no suffix) that maps to the correct alternative.
+ *
+ * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!!
+ * Additional effort is required to select specific GPIO options such as
+ * frequency, and pull-up/down! Just the basics are defined for most pins
+ * in the initial version of this file.
+ */
+
+/* Analog-to-Digital Converter (ADC)
+ *
+ * These are only outputs for external analog multiplexing. Analog inputs
+ * cannot be controlled by the pin multiplexing in the SIUL2 module. Those
+ * analog functions are available in parallel to the multiplexed digital
+ * functionality. See the S32K3xx reference manual for more information.
+ */
+
+#define PIN_ADC0_MA0_1 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT4)
+#define PIN_ADC0_MA0_2 (PIN_PORTE | PIN2 | PIN_OUTPUT_ALT7)
+#define PIN_ADC0_MA0_3 (PIN_PORTF | PIN9 | PIN_OUTPUT_ALT3)
+#define PIN_ADC0_MA0_4 (PIN_PORTF | PIN12 | PIN_OUTPUT_ALT3)
+#define PIN_ADC0_MA1_1 (PIN_PORTC | PIN14 | PIN_OUTPUT_ALT4)
+#define PIN_ADC0_MA1_2 (PIN_PORTE | PIN6 | PIN_OUTPUT_ALT7)
+#define PIN_ADC0_MA1_3 (PIN_PORTF | PIN10 | PIN_OUTPUT_ALT3)
+#define PIN_ADC0_MA1_4 (PIN_PORTF | PIN13 | PIN_OUTPUT_ALT3)
+#define PIN_ADC0_MA2_1 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT7)
+#define PIN_ADC0_MA2_2 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT4)
+#define PIN_ADC0_MA2_3 (PIN_PORTF | PIN11 | PIN_OUTPUT_ALT3)
+#define PIN_ADC0_MA2_4 (PIN_PORTF | PIN19 | PIN_OUTPUT_ALT4)
+
+#define PIN_ADC1_MA0_1 (PIN_PORTB | PIN2 | PIN_OUTPUT_ALT1)
+#define PIN_ADC1_MA0_2 (PIN_PORTB | PIN23 | PIN_OUTPUT_ALT1)
+#define PIN_ADC1_MA0_3 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT5)
+#define PIN_ADC1_MA0_4 (PIN_PORTF | PIN16 | PIN_OUTPUT_ALT4)
+#define PIN_ADC1_MA0_5 (PIN_PORTF | PIN29 | PIN_OUTPUT_ALT4)
+#define PIN_ADC1_MA1_1 (PIN_PORTB | PIN24 | PIN_OUTPUT_ALT1)
+#define PIN_ADC1_MA1_2 (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT4)
+#define PIN_ADC1_MA1_3 (PIN_PORTC | PIN21 | PIN_OUTPUT_ALT5)
+#define PIN_ADC1_MA1_4 (PIN_PORTF | PIN17 | PIN_OUTPUT_ALT4)
+#define PIN_ADC1_MA1_5 (PIN_PORTF | PIN30 | PIN_OUTPUT_ALT4)
+#define PIN_ADC1_MA2_1 (PIN_PORTB | PIN28 | PIN_OUTPUT_ALT1)
+#define PIN_ADC1_MA2_2 (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT1)
+#define PIN_ADC1_MA2_3 (PIN_PORTC | PIN20 | PIN_OUTPUT_ALT5)
+#define PIN_ADC1_MA2_4 (PIN_PORTF | PIN18 | PIN_OUTPUT_ALT4)
+#define PIN_ADC1_MA2_5 (PIN_PORTF | PIN31 | PIN_OUTPUT_ALT1)
+
+/* FlexCAN */
+
+#define PIN_CAN0_RX_1 (PIN_PORTA | PIN6 | PIN_INPUT_ALT2 | IMCR(512))
+#define PIN_CAN0_RX_2 (PIN_PORTA | PIN28 | PIN_INPUT_ALT4 | IMCR(512))
+#define PIN_CAN0_RX_3 (PIN_PORTB | PIN0 | PIN_INPUT_ALT3 | IMCR(512))
+#define PIN_CAN0_RX_4 (PIN_PORTC | PIN2 | PIN_INPUT_ALT1 | IMCR(512))
+#define PIN_CAN0_RX_5 (PIN_PORTF | PIN21 | PIN_INPUT_ALT5 | IMCR(512))
+#define PIN_CAN0_TX_1 (PIN_PORTA | PIN7 | PIN_OUTPUT_ALT4)
+#define PIN_CAN0_TX_2 (PIN_PORTA | PIN27 | PIN_OUTPUT_ALT5)
+#define PIN_CAN0_TX_3 (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT5)
+#define PIN_CAN0_TX_4 (PIN_PORTC | PIN3 | PIN_OUTPUT_ALT3)
+#define PIN_CAN0_TX_5 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT6)
+
+#define PIN_CAN1_RX_1 (PIN_PORTA | PIN12 | PIN_INPUT_ALT2 | IMCR(513))
+#define PIN_CAN1_RX_2 (PIN_PORTA | PIN22 | PIN_INPUT_ALT3 | IMCR(513))
+#define PIN_CAN1_RX_3 (PIN_PORTB | PIN23 | PIN_INPUT_ALT4 | IMCR(513))
+#define PIN_CAN1_RX_4 (PIN_PORTC | PIN9 | PIN_INPUT_ALT1 | IMCR(513))
+#define PIN_CAN1_RX_5 (PIN_PORTF | PIN15 | PIN_INPUT_ALT5 | IMCR(513))
+#define PIN_CAN1_TX_1 (PIN_PORTA | PIN11 | PIN_OUTPUT_ALT1)
+#define PIN_CAN1_TX_2 (PIN_PORTA | PIN23 | PIN_OUTPUT_ALT1)
+#define PIN_CAN1_TX_3 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT1)
+#define PIN_CAN1_TX_4 (PIN_PORTC | PIN8 | PIN_OUTPUT_ALT3)
+#define PIN_CAN1_TX_5 (PIN_PORTF | PIN14 | PIN_OUTPUT_ALT1)
+
+#define PIN_CAN2_RX_1 (PIN_PORTC | PIN6 | PIN_INPUT_ALT6 | IMCR(514))
+#define PIN_CAN2_RX_2 (PIN_PORTC | PIN14 | PIN_INPUT_ALT2 | IMCR(514))
+#define PIN_CAN2_RX_3 (PIN_PORTC | PIN16 | PIN_INPUT_ALT1 | IMCR(514))
+#define PIN_CAN2_RX_4 (PIN_PORTD | PIN19 | PIN_INPUT_ALT4 | IMCR(514))
+#define PIN_CAN2_RX_5 (PIN_PORTE | PIN25 | PIN_INPUT_ALT3 | IMCR(514))
+#define PIN_CAN2_RX_6 (PIN_PORTF | PIN26 | PIN_INPUT_ALT5 | IMCR(514))
+#define PIN_CAN2_TX_1 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT7)
+#define PIN_CAN2_TX_2 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT1)
+#define PIN_CAN2_TX_3 (PIN_PORTC | PIN17 | PIN_OUTPUT_ALT3)
+#define PIN_CAN2_TX_4 (PIN_PORTD | PIN18 | PIN_OUTPUT_ALT1)
+#define PIN_CAN2_TX_5 (PIN_PORTE | PIN24 | PIN_OUTPUT_ALT3)
+#define PIN_CAN2_TX_6 (PIN_PORTF | PIN25 | PIN_OUTPUT_ALT1)
+
+#define PIN_CAN3_RX_1 (PIN_PORTC | PIN1 | PIN_INPUT_ALT2 | IMCR(515))
+#define PIN_CAN3_RX_2 (PIN_PORTC | PIN29 | PIN_INPUT_ALT3 | IMCR(515))
+#define PIN_CAN3_RX_3 (PIN_PORTD | PIN15 | PIN_INPUT_ALT1 | IMCR(515))
+#define PIN_CAN3_RX_4 (PIN_PORTE | PIN29 | PIN_INPUT_ALT4 | IMCR(515))
+#define PIN_CAN3_RX_5 (PIN_PORTF | PIN30 | PIN_INPUT_ALT5 | IMCR(515))
+#define PIN_CAN3_TX_1 (PIN_PORTC | PIN0 | PIN_OUTPUT_ALT1)
+#define PIN_CAN3_TX_2 (PIN_PORTC | PIN28 | PIN_OUTPUT_ALT1)
+#define PIN_CAN3_TX_3 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT4)
+#define PIN_CAN3_TX_4 (PIN_PORTE | PIN28 | PIN_OUTPUT_ALT1)
+#define PIN_CAN3_TX_5 (PIN_PORTF | PIN29 | PIN_OUTPUT_ALT1)
+
+#define PIN_CAN4_RX_1 (PIN_PORTB | PIN2 | PIN_INPUT_ALT2 | IMCR(516))
+#define PIN_CAN4_RX_2 (PIN_PORTC | PIN31 | PIN_INPUT_ALT3 | IMCR(516))
+#define PIN_CAN4_RX_3 (PIN_PORTE | PIN14 | PIN_INPUT_ALT1 | IMCR(516))
+#define PIN_CAN4_RX_4 (PIN_PORTE | PIN31 | PIN_INPUT_ALT4 | IMCR(516))
+#define PIN_CAN4_RX_5 (PIN_PORTG | PIN9 | PIN_INPUT_ALT5 | IMCR(516))
+#define PIN_CAN4_TX_1 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT5)
+#define PIN_CAN4_TX_2 (PIN_PORTC | PIN30 | PIN_OUTPUT_ALT1)
+#define PIN_CAN4_TX_3 (PIN_PORTE | PIN3 | PIN_OUTPUT_ALT1)
+#define PIN_CAN4_TX_4 (PIN_PORTE | PIN30 | PIN_OUTPUT_ALT1)
+#define PIN_CAN4_TX_5 (PIN_PORTG | PIN8 | PIN_OUTPUT_ALT1)
+
+#define PIN_CAN5_RX_1 (PIN_PORTC | PIN11 | PIN_INPUT_ALT2 | IMCR(517))
+#define PIN_CAN5_RX_2 (PIN_PORTC | PIN26 | PIN_INPUT_ALT5 | IMCR(517))
+#define PIN_CAN5_RX_3 (PIN_PORTD | PIN17 | PIN_INPUT_ALT1 | IMCR(517))
+#define PIN_CAN5_RX_4 (PIN_PORTF | PIN5 | PIN_INPUT_ALT3 | IMCR(517))
+#define PIN_CAN5_RX_5 (PIN_PORTG | PIN14 | PIN_INPUT_ALT4 | IMCR(517))
+#define PIN_CAN5_TX_1 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT3)
+#define PIN_CAN5_TX_2 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT1)
+#define PIN_CAN5_TX_3 (PIN_PORTE | PIN12 | PIN_OUTPUT_ALT2)
+#define PIN_CAN5_TX_4 (PIN_PORTF | PIN4 | PIN_OUTPUT_ALT1)
+#define PIN_CAN5_TX_5 (PIN_PORTG | PIN13 | PIN_OUTPUT_ALT1)
+
+/* Clock Output (CLKOUT) */
+
+#define PIN_CLKOUT_RUN_1 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT5)
+#define PIN_CLKOUT_RUN_2 (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT6)
+#define PIN_CLKOUT_RUN_3 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT7)
+#define PIN_CLKOUT_STANDBY_1 (PIN_PORTA | PIN12 | PIN_OUTPUT_ALT3)
+#define PIN_CLKOUT_STANDBY_2 (PIN_PORTE | PIN10 | PIN_OUTPUT_ALT5)
+
+/* Comparator (CMP)
+ *
+ * These are only digital comparator outputs. The analog comparator inputs
+ * cannot be controlled by the pin multiplexing in the SIUL2 module. Those
+ * analog functions are available in parallel to the multiplexed digital
+ * functionality. See the S32K3xx reference manual for more information.
+ */
+
+#define PIN_CMP0_OUT_1 (PIN_PORTA | PIN4 | PIN_OUTPUT_ALT4)
+#define PIN_CMP0_OUT_2 (PIN_PORTE | PIN3 | PIN_OUTPUT_ALT7)
+#define PIN_CMP0_OUT_3 (PIN_PORTF | PIN14 | PIN_OUTPUT_ALT3)
+#define PIN_CMP0_RRT_1 (PIN_PORTA | PIN11 | PIN_OUTPUT_ALT5)
+#define PIN_CMP0_RRT_2 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT6)
+#define PIN_CMP0_RRT_3 (PIN_PORTF | PIN15 | PIN_OUTPUT_ALT3)
+
+#define PIN_CMP1_OUT_1 (PIN_PORTA | PIN12 | PIN_OUTPUT_ALT7)
+#define PIN_CMP1_OUT_2 (PIN_PORTE | PIN30 | PIN_OUTPUT_ALT2)
+#define PIN_CMP1_RRT_1 (PIN_PORTE | PIN15 | PIN_OUTPUT_ALT5)
+#define PIN_CMP1_RRT_2 (PIN_PORTE | PIN31 | PIN_OUTPUT_ALT2)
+
+#define PIN_CMP2_OUT_1 (PIN_PORTA | PIN9 | PIN_OUTPUT_ALT7)
+#define PIN_CMP2_OUT_2 (PIN_PORTG | PIN4 | PIN_OUTPUT_ALT4)
+#define PIN_CMP2_RRT_1 (PIN_PORTC | PIN5 | PIN_OUTPUT_ALT5)
+#define PIN_CMP2_RRT_2 (PIN_PORTG | PIN5 | PIN_OUTPUT_ALT4)
+
+/* External Interrupt (EIRQ) */
+
+#define PIN_EIRQ0_1 (PIN_PORTA | PIN0 | PIN_INPUT_ALT1 | IMCR(528))
+#define PIN_EIRQ0_2 (PIN_PORTA | PIN18 | PIN_INPUT_ALT2 | IMCR(528))
+#define PIN_EIRQ0_3 (PIN_PORTC | PIN0 | PIN_INPUT_ALT3 | IMCR(528))
+#define PIN_EIRQ0_4 (PIN_PORTE | PIN0 | PIN_INPUT_ALT4 | IMCR(528))
+#define PIN_EIRQ0_5 (PIN_PORTF | PIN0 | PIN_INPUT_ALT5 | IMCR(528))
+#define PIN_EIRQ1_1 (PIN_PORTA | PIN1 | PIN_INPUT_ALT1 | IMCR(529))
+#define PIN_EIRQ1_2 (PIN_PORTA | PIN19 | PIN_INPUT_ALT2 | IMCR(529))
+#define PIN_EIRQ1_3 (PIN_PORTC | PIN1 | PIN_INPUT_ALT3 | IMCR(529))
+#define PIN_EIRQ1_4 (PIN_PORTE | PIN1 | PIN_INPUT_ALT4 | IMCR(529))
+#define PIN_EIRQ1_5 (PIN_PORTF | PIN1 | PIN_INPUT_ALT5 | IMCR(529))
+#define PIN_EIRQ2_1 (PIN_PORTA | PIN2 | PIN_INPUT_ALT1 | IMCR(530))
+#define PIN_EIRQ2_2 (PIN_PORTA | PIN20 | PIN_INPUT_ALT2 | IMCR(530))
+#define PIN_EIRQ2_3 (PIN_PORTC | PIN2 | PIN_INPUT_ALT3 | IMCR(530))
+#define PIN_EIRQ2_4 (PIN_PORTE | PIN2 | PIN_INPUT_ALT4 | IMCR(530))
+#define PIN_EIRQ2_5 (PIN_PORTF | PIN2 | PIN_INPUT_ALT5 | IMCR(530))
+#define PIN_EIRQ3_1 (PIN_PORTA | PIN3 | PIN_INPUT_ALT1 | IMCR(531))
+#define PIN_EIRQ3_2 (PIN_PORTA | PIN21 | PIN_INPUT_ALT2 | IMCR(531))
+#define PIN_EIRQ3_3 (PIN_PORTC | PIN3 | PIN_INPUT_ALT3 | IMCR(531))
+#define PIN_EIRQ3_4 (PIN_PORTE | PIN3 | PIN_INPUT_ALT4 | IMCR(531))
+#define PIN_EIRQ3_5 (PIN_PORTF | PIN3 | PIN_INPUT_ALT5 | IMCR(531))
+#define PIN_EIRQ4_1 (PIN_PORTA | PIN4 | PIN_INPUT_ALT1 | IMCR(532))
+#define PIN_EIRQ4_2 (PIN_PORTA | PIN16 | PIN_INPUT_ALT2 | IMCR(532))
+#define PIN_EIRQ4_3 (PIN_PORTC | PIN4 | PIN_INPUT_ALT3 | IMCR(532))
+#define PIN_EIRQ4_4 (PIN_PORTE | PIN4 | PIN_INPUT_ALT4 | IMCR(532))
+#define PIN_EIRQ4_5 (PIN_PORTF | PIN4 | PIN_INPUT_ALT5 | IMCR(532))
+#define PIN_EIRQ5_1 (PIN_PORTA | PIN5 | PIN_INPUT_ALT1 | IMCR(533))
+#define PIN_EIRQ5_2 (PIN_PORTA | PIN25 | PIN_INPUT_ALT2 | IMCR(533))
+#define PIN_EIRQ5_3 (PIN_PORTC | PIN5 | PIN_INPUT_ALT3 | IMCR(533))
+#define PIN_EIRQ5_4 (PIN_PORTE | PIN5 | PIN_INPUT_ALT4 | IMCR(533))
+#define PIN_EIRQ5_5 (PIN_PORTF | PIN5 | PIN_INPUT_ALT5 | IMCR(533))
+#define PIN_EIRQ6_1 (PIN_PORTA | PIN6 | PIN_INPUT_ALT1 | IMCR(534))
+#define PIN_EIRQ6_2 (PIN_PORTA | PIN28 | PIN_INPUT_ALT2 | IMCR(534))
+#define PIN_EIRQ6_3 (PIN_PORTC | PIN6 | PIN_INPUT_ALT3 | IMCR(534))
+#define PIN_EIRQ6_4 (PIN_PORTE | PIN6 | PIN_INPUT_ALT4 | IMCR(534))
+#define PIN_EIRQ6_5 (PIN_PORTF | PIN6 | PIN_INPUT_ALT5 | IMCR(534))
+#define PIN_EIRQ7_1 (PIN_PORTA | PIN7 | PIN_INPUT_ALT1 | IMCR(535))
+#define PIN_EIRQ7_2 (PIN_PORTA | PIN30 | PIN_INPUT_ALT2 | IMCR(535))
+#define PIN_EIRQ7_3 (PIN_PORTC | PIN7 | PIN_INPUT_ALT3 | IMCR(535))
+#define PIN_EIRQ7_4 (PIN_PORTE | PIN8 | PIN_INPUT_ALT4 | IMCR(535))
+#define PIN_EIRQ7_5 (PIN_PORTF | PIN7 | PIN_INPUT_ALT5 | IMCR(535))
+#define PIN_EIRQ8_1 (PIN_PORTB | PIN0 | PIN_INPUT_ALT1 | IMCR(536))
+#define PIN_EIRQ8_2 (PIN_PORTB | PIN21 | PIN_INPUT_ALT2 | IMCR(536))
+#define PIN_EIRQ8_3 (PIN_PORTD | PIN0 | PIN_INPUT_ALT3 | IMCR(536))
+#define PIN_EIRQ8_4 (PIN_PORTE | PIN9 | PIN_INPUT_ALT4 | IMCR(536))
+#define PIN_EIRQ8_5 (PIN_PORTG | PIN0 | PIN_INPUT_ALT5 | IMCR(536))
+#define PIN_EIRQ9_1 (PIN_PORTB | PIN1 | PIN_INPUT_ALT1 | IMCR(537))
+#define PIN_EIRQ9_2 (PIN_PORTB | PIN22 | PIN_INPUT_ALT2 | IMCR(537))
+#define PIN_EIRQ9_3 (PIN_PORTD | PIN1 | PIN_INPUT_ALT3 | IMCR(537))
+#define PIN_EIRQ9_4 (PIN_PORTE | PIN10 | PIN_INPUT_ALT4 | IMCR(537))
+#define PIN_EIRQ9_5 (PIN_PORTG | PIN1 | PIN_INPUT_ALT5 | IMCR(537))
+#define PIN_EIRQ10_1 (PIN_PORTB | PIN2 | PIN_INPUT_ALT1 | IMCR(538))
+#define PIN_EIRQ10_2 (PIN_PORTB | PIN23 | PIN_INPUT_ALT2 | IMCR(538))
+#define PIN_EIRQ10_3 (PIN_PORTD | PIN2 | PIN_INPUT_ALT3 | IMCR(538))
+#define PIN_EIRQ10_4 (PIN_PORTE | PIN11 | PIN_INPUT_ALT4 | IMCR(538))
+#define PIN_EIRQ10_5 (PIN_PORTG | PIN2 | PIN_INPUT_ALT5 | IMCR(538))
+#define PIN_EIRQ11_1 (PIN_PORTB | PIN3 | PIN_INPUT_ALT1 | IMCR(539))
+#define PIN_EIRQ11_2 (PIN_PORTB | PIN24 | PIN_INPUT_ALT2 | IMCR(539))
+#define PIN_EIRQ11_3 (PIN_PORTD | PIN3 | PIN_INPUT_ALT3 | IMCR(539))
+#define PIN_EIRQ11_4 (PIN_PORTE | PIN12 | PIN_INPUT_ALT4 | IMCR(539))
+#define PIN_EIRQ11_5 (PIN_PORTG | PIN3 | PIN_INPUT_ALT5 | IMCR(539))
+#define PIN_EIRQ12_1 (PIN_PORTB | PIN4 | PIN_INPUT_ALT1 | IMCR(540))
+#define PIN_EIRQ12_2 (PIN_PORTB | PIN25 | PIN_INPUT_ALT2 | IMCR(540))
+#define PIN_EIRQ12_3 (PIN_PORTD | PIN4 | PIN_INPUT_ALT3 | IMCR(540))
+#define PIN_EIRQ12_4 (PIN_PORTE | PIN13 | PIN_INPUT_ALT4 | IMCR(540))
+#define PIN_EIRQ12_5 (PIN_PORTG | PIN4 | PIN_INPUT_ALT5 | IMCR(540))
+#define PIN_EIRQ13_1 (PIN_PORTB | PIN5 | PIN_INPUT_ALT1 | IMCR(541))
+#define PIN_EIRQ13_2 (PIN_PORTB | PIN26 | PIN_INPUT_ALT2 | IMCR(541))
+#define PIN_EIRQ13_3 (PIN_PORTD | PIN5 | PIN_INPUT_ALT3 | IMCR(541))
+#define PIN_EIRQ13_4 (PIN_PORTE | PIN14 | PIN_INPUT_ALT4 | IMCR(541))
+#define PIN_EIRQ13_5 (PIN_PORTG | PIN5 | PIN_INPUT_ALT5 | IMCR(541))
+#define PIN_EIRQ14_1 (PIN_PORTB | PIN8 | PIN_INPUT_ALT1 | IMCR(542))
+#define PIN_EIRQ14_2 (PIN_PORTB | PIN28 | PIN_INPUT_ALT2 | IMCR(542))
+#define PIN_EIRQ14_3 (PIN_PORTD | PIN6 | PIN_INPUT_ALT3 | IMCR(542))
+#define PIN_EIRQ14_4 (PIN_PORTE | PIN15 | PIN_INPUT_ALT4 | IMCR(542))
+#define PIN_EIRQ14_5 (PIN_PORTG | PIN6 | PIN_INPUT_ALT5 | IMCR(542))
+#define PIN_EIRQ15_1 (PIN_PORTB | PIN9 | PIN_INPUT_ALT1 | IMCR(543))
+#define PIN_EIRQ15_2 (PIN_PORTB | PIN31 | PIN_INPUT_ALT2 | IMCR(543))
+#define PIN_EIRQ15_3 (PIN_PORTD | PIN7 | PIN_INPUT_ALT3 | IMCR(543))
+#define PIN_EIRQ15_4 (PIN_PORTE | PIN16 | PIN_INPUT_ALT4 | IMCR(543))
+#define PIN_EIRQ15_5 (PIN_PORTG | PIN7 | PIN_INPUT_ALT5 | IMCR(543))
+#define PIN_EIRQ16_1 (PIN_PORTA | PIN8 | PIN_INPUT_ALT1 | IMCR(544))
+#define PIN_EIRQ16_2 (PIN_PORTC | PIN8 | PIN_INPUT_ALT2 | IMCR(544))
+#define PIN_EIRQ16_3 (PIN_PORTC | PIN20 | PIN_INPUT_ALT3 | IMCR(544))
+#define PIN_EIRQ16_4 (PIN_PORTF | PIN8 | PIN_INPUT_ALT4 | IMCR(544))
+#define PIN_EIRQ17_1 (PIN_PORTA | PIN9 | PIN_INPUT_ALT1 | IMCR(545))
+#define PIN_EIRQ17_2 (PIN_PORTC | PIN9 | PIN_INPUT_ALT2 | IMCR(545))
+#define PIN_EIRQ17_3 (PIN_PORTC | PIN21 | PIN_INPUT_ALT3 | IMCR(545))
+#define PIN_EIRQ17_4 (PIN_PORTF | PIN9 | PIN_INPUT_ALT4 | IMCR(545))
+#define PIN_EIRQ18_1 (PIN_PORTA | PIN10 | PIN_INPUT_ALT1 | IMCR(546))
+#define PIN_EIRQ18_2 (PIN_PORTC | PIN10 | PIN_INPUT_ALT2 | IMCR(546))
+#define PIN_EIRQ18_3 (PIN_PORTC | PIN23 | PIN_INPUT_ALT3 | IMCR(546))
+#define PIN_EIRQ18_4 (PIN_PORTF | PIN10 | PIN_INPUT_ALT4 | IMCR(546))
+#define PIN_EIRQ19_1 (PIN_PORTA | PIN11 | PIN_INPUT_ALT1 | IMCR(547))
+#define PIN_EIRQ19_2 (PIN_PORTC | PIN11 | PIN_INPUT_ALT2 | IMCR(547))
+#define PIN_EIRQ19_3 (PIN_PORTC | PIN24 | PIN_INPUT_ALT3 | IMCR(547))
+#define PIN_EIRQ19_4 (PIN_PORTF | PIN11 | PIN_INPUT_ALT4 | IMCR(547))
+#define PIN_EIRQ20_1 (PIN_PORTA | PIN12 | PIN_INPUT_ALT1 | IMCR(548))
+#define PIN_EIRQ20_2 (PIN_PORTC | PIN12 | PIN_INPUT_ALT2 | IMCR(548))
+#define PIN_EIRQ20_3 (PIN_PORTC | PIN25 | PIN_INPUT_ALT3 | IMCR(548))
+#define PIN_EIRQ20_4 (PIN_PORTF | PIN12 | PIN_INPUT_ALT4 | IMCR(548))
+#define PIN_EIRQ21_1 (PIN_PORTA | PIN13 | PIN_INPUT_ALT1 | IMCR(549))
+#define PIN_EIRQ21_2 (PIN_PORTC | PIN13 | PIN_INPUT_ALT2 | IMCR(549))
+#define PIN_EIRQ21_3 (PIN_PORTC | PIN26 | PIN_INPUT_ALT3 | IMCR(549))
+#define PIN_EIRQ21_4 (PIN_PORTF | PIN13 | PIN_INPUT_ALT4 | IMCR(549))
+#define PIN_EIRQ22_1 (PIN_PORTA | PIN14 | PIN_INPUT_ALT1 | IMCR(550))
+#define PIN_EIRQ22_2 (PIN_PORTC | PIN14 | PIN_INPUT_ALT2 | IMCR(550))
+#define PIN_EIRQ22_3 (PIN_PORTC | PIN27 | PIN_INPUT_ALT3 | IMCR(550))
+#define PIN_EIRQ22_4 (PIN_PORTF | PIN14 | PIN_INPUT_ALT4 | IMCR(550))
+#define PIN_EIRQ23_1 (PIN_PORTA | PIN15 | PIN_INPUT_ALT1 | IMCR(551))
+#define PIN_EIRQ23_2 (PIN_PORTC | PIN15 | PIN_INPUT_ALT2 | IMCR(551))
+#define PIN_EIRQ23_3 (PIN_PORTC | PIN29 | PIN_INPUT_ALT3 | IMCR(551))
+#define PIN_EIRQ23_4 (PIN_PORTF | PIN15 | PIN_INPUT_ALT4 | IMCR(551))
+#define PIN_EIRQ24_1 (PIN_PORTB | PIN10 | PIN_INPUT_ALT1 | IMCR(552))
+#define PIN_EIRQ24_2 (PIN_PORTD | PIN8 | PIN_INPUT_ALT2 | IMCR(552))
+#define PIN_EIRQ24_3 (PIN_PORTD | PIN17 | PIN_INPUT_ALT3 | IMCR(552))
+#define PIN_EIRQ24_4 (PIN_PORTG | PIN8 | PIN_INPUT_ALT4 | IMCR(552))
+#define PIN_EIRQ25_1 (PIN_PORTB | PIN11 | PIN_INPUT_ALT1 | IMCR(553))
+#define PIN_EIRQ25_2 (PIN_PORTD | PIN9 | PIN_INPUT_ALT2 | IMCR(553))
+#define PIN_EIRQ25_3 (PIN_PORTD | PIN20 | PIN_INPUT_ALT3 | IMCR(553))
+#define PIN_EIRQ25_4 (PIN_PORTG | PIN9 | PIN_INPUT_ALT4 | IMCR(553))
+#define PIN_EIRQ26_1 (PIN_PORTB | PIN12 | PIN_INPUT_ALT1 | IMCR(554))
+#define PIN_EIRQ26_2 (PIN_PORTD | PIN10 | PIN_INPUT_ALT2 | IMCR(554))
+#define PIN_EIRQ26_3 (PIN_PORTD | PIN21 | PIN_INPUT_ALT3 | IMCR(554))
+#define PIN_EIRQ26_4 (PIN_PORTG | PIN10 | PIN_INPUT_ALT4 | IMCR(554))
+#define PIN_EIRQ27_1 (PIN_PORTB | PIN13 | PIN_INPUT_ALT1 | IMCR(555))
+#define PIN_EIRQ27_2 (PIN_PORTD | PIN11 | PIN_INPUT_ALT2 | IMCR(555))
+#define PIN_EIRQ27_3 (PIN_PORTD | PIN22 | PIN_INPUT_ALT3 | IMCR(555))
+#define PIN_EIRQ27_4 (PIN_PORTG | PIN11 | PIN_INPUT_ALT4 | IMCR(555))
+#define PIN_EIRQ28_1 (PIN_PORTB | PIN14 | PIN_INPUT_ALT1 | IMCR(556))
+#define PIN_EIRQ28_2 (PIN_PORTD | PIN12 | PIN_INPUT_ALT2 | IMCR(556))
+#define PIN_EIRQ28_3 (PIN_PORTD | PIN23 | PIN_INPUT_ALT3 | IMCR(556))
+#define PIN_EIRQ28_4 (PIN_PORTG | PIN12 | PIN_INPUT_ALT4 | IMCR(556))
+#define PIN_EIRQ29_1 (PIN_PORTB | PIN15 | PIN_INPUT_ALT1 | IMCR(557))
+#define PIN_EIRQ29_2 (PIN_PORTD | PIN13 | PIN_INPUT_ALT2 | IMCR(557))
+#define PIN_EIRQ29_3 (PIN_PORTD | PIN24 | PIN_INPUT_ALT3 | IMCR(557))
+#define PIN_EIRQ29_4 (PIN_PORTG | PIN13 | PIN_INPUT_ALT4 | IMCR(557))
+#define PIN_EIRQ30_1 (PIN_PORTB | PIN16 | PIN_INPUT_ALT1 | IMCR(558))
+#define PIN_EIRQ30_2 (PIN_PORTD | PIN14 | PIN_INPUT_ALT3 | IMCR(558))
+#define PIN_EIRQ30_3 (PIN_PORTD | PIN27 | PIN_INPUT_ALT2 | IMCR(558))
+#define PIN_EIRQ30_4 (PIN_PORTG | PIN14 | PIN_INPUT_ALT4 | IMCR(558))
+#define PIN_EIRQ31_1 (PIN_PORTB | PIN17 | PIN_INPUT_ALT1 | IMCR(559))
+#define PIN_EIRQ31_2 (PIN_PORTD | PIN15 | PIN_INPUT_ALT2 | IMCR(559))
+#define PIN_EIRQ31_3 (PIN_PORTD | PIN28 | PIN_INPUT_ALT3 | IMCR(559))
+#define PIN_EIRQ31_4 (PIN_PORTG | PIN15 | PIN_INPUT_ALT4 | IMCR(559))
+
+/* Ethernet MAC (EMAC) */
+
+#define PIN_EMAC_MII_COL_1 (PIN_PORTB | PIN23 | PIN_INPUT_ALT1 | IMCR(801))
+#define PIN_EMAC_MII_COL_2 (PIN_PORTC | PIN14 | PIN_INPUT_ALT2 | IMCR(801))
+#define PIN_EMAC_MII_CRS_1 (PIN_PORTB | PIN22 | PIN_INPUT_ALT1 | IMCR(802))
+#define PIN_EMAC_MII_CRS_2 (PIN_PORTC | PIN15 | PIN_INPUT_ALT2 | IMCR(802))
+#define PIN_EMAC_MII_RMII_MDC_1 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT7)
+#define PIN_EMAC_MII_RMII_MDC_2 (PIN_PORTD | PIN17 | PIN_OUTPUT_ALT3)
+#define PIN_EMAC_MII_RMII_MDC_3 (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT5)
+#define PIN_EMAC_MII_RMII_MDIO_1 (PIN_PORTB | PIN4 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(803))
+#define PIN_EMAC_MII_RMII_MDIO_2 (PIN_PORTD | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(803))
+#define PIN_EMAC_MII_RMII_RX_DV_1 (PIN_PORTC | PIN15 | PIN_INPUT_ALT2 | IMCR(804))
+#define PIN_EMAC_MII_RMII_RX_DV_2 (PIN_PORTC | PIN17 | PIN_INPUT_ALT1 | IMCR(804))
+#define PIN_EMAC_MII_RMII_RX_ER_1 (PIN_PORTC | PIN14 | PIN_INPUT_ALT2 | IMCR(805))
+#define PIN_EMAC_MII_RMII_RX_ER_2 (PIN_PORTC | PIN16 | PIN_INPUT_ALT1 | IMCR(805))
+#define PIN_EMAC_MII_RMII_RXD0_1 (PIN_PORTC | PIN0 | PIN_INPUT_ALT2 | IMCR(806))
+#define PIN_EMAC_MII_RMII_RXD0_2 (PIN_PORTC | PIN1 | PIN_INPUT_ALT1 | IMCR(806))
+#define PIN_EMAC_MII_RMII_RXD0_3 (PIN_PORTD | PIN9 | PIN_INPUT_ALT3 | IMCR(806))
+#define PIN_EMAC_MII_RMII_RXD1_1 (PIN_PORTC | PIN0 | PIN_INPUT_ALT1 | IMCR(807))
+#define PIN_EMAC_MII_RMII_RXD1_2 (PIN_PORTC | PIN1 | PIN_INPUT_ALT2 | IMCR(807))
+#define PIN_EMAC_MII_RMII_RXD1_3 (PIN_PORTD | PIN8 | PIN_INPUT_ALT3 | IMCR(807))
+#define PIN_EMAC_MII_RMII_TX_CLK_1 (PIN_PORTC | PIN0 | PIN_INPUT_ALT4 | IMCR(808))
+#define PIN_EMAC_MII_RMII_TX_CLK_2 (PIN_PORTD | PIN6 | PIN_INPUT_ALT2 | IMCR(808))
+#define PIN_EMAC_MII_RMII_TX_CLK_3 (PIN_PORTD | PIN11 | PIN_INPUT_ALT1 | IMCR(808))
+#define PIN_EMAC_MII_RMII_TX_CLK_4 (PIN_PORTD | PIN12 | PIN_INPUT_ALT3 | IMCR(808))
+#define PIN_EMAC_MII_RMII_TX_EN_1 (PIN_PORTD | PIN11 | PIN_OUTPUT_ALT3)
+#define PIN_EMAC_MII_RMII_TX_EN_2 (PIN_PORTD | PIN12 | PIN_OUTPUT_ALT5)
+#define PIN_EMAC_MII_RMII_TX_EN_3 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT6)
+#define PIN_EMAC_MII_RMII_TXD0_1 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_RMII_TXD0_2 (PIN_PORTC | PIN2 | PIN_OUTPUT_ALT5)
+#define PIN_EMAC_MII_RMII_TXD0_3 (PIN_PORTD | PIN7 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_RMII_TXD1_1 (PIN_PORTB | PIN4 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_RMII_TXD1_2 (PIN_PORTC | PIN2 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_RMII_TXD1_3 (PIN_PORTD | PIN7 | PIN_OUTPUT_ALT5)
+#define PIN_EMAC_MII_RX_CLK_1 (PIN_PORTC | PIN1 | PIN_INPUT_ALT3 | IMCR(812))
+#define PIN_EMAC_MII_RX_CLK_2 (PIN_PORTD | PIN5 | PIN_INPUT_ALT2 | IMCR(812))
+#define PIN_EMAC_MII_RX_CLK_3 (PIN_PORTD | PIN10 | PIN_INPUT_ALT1 | IMCR(812))
+#define PIN_EMAC_MII_RXD2_1 (PIN_PORTC | PIN15 | PIN_INPUT_ALT2 | IMCR(813))
+#define PIN_EMAC_MII_RXD2_2 (PIN_PORTD | PIN9 | PIN_INPUT_ALT1 | IMCR(813))
+#define PIN_EMAC_MII_RXD3_1 (PIN_PORTC | PIN14 | PIN_INPUT_ALT2 | IMCR(814))
+#define PIN_EMAC_MII_RXD3_2 (PIN_PORTD | PIN8 | PIN_INPUT_ALT1 | IMCR(814))
+#define PIN_EMAC_MII_TXD2_1 (PIN_PORTD | PIN5 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_TXD2_2 (PIN_PORTD | PIN6 | PIN_OUTPUT_ALT5)
+#define PIN_EMAC_MII_TXD2_3 (PIN_PORTD | PIN11 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_TXD3_1 (PIN_PORTD | PIN5 | PIN_OUTPUT_ALT5)
+#define PIN_EMAC_MII_TXD3_2 (PIN_PORTD | PIN6 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_MII_TXD3_3 (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT1)
+#define PIN_EMAC_PPS0_1 (PIN_PORTA | PIN26 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT3 | IMCR(656))
+#define PIN_EMAC_PPS0_2 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(656))
+#define PIN_EMAC_PPS0_3 (PIN_PORTE | PIN3 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(656))
+#define PIN_EMAC_PPS1_1 (PIN_PORTA | PIN27 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(657))
+#define PIN_EMAC_PPS1_2 (PIN_PORTD | PIN13 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(657))
+#define PIN_EMAC_PPS1_3 (PIN_PORTE | PIN14 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(657))
+#define PIN_EMAC_PPS2_1 (PIN_PORTA | PIN29 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(658))
+#define PIN_EMAC_PPS2_2 (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(658))
+#define PIN_EMAC_PPS2_3 (PIN_PORTD | PIN17 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(658))
+#define PIN_EMAC_PPS3_1 (PIN_PORTB | PIN28 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(659))
+#define PIN_EMAC_PPS3_2 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(659))
+#define PIN_EMAC_PPS3_3 (PIN_PORTE | PIN12 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(659))
+
+/* Enhanced Modular I/O Subsystem (eMIOS) */
+
+#define PIN_EMIOS0_CH0_1 (PIN_PORTB | PIN12 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(560))
+#define PIN_EMIOS0_CH0_2 (PIN_PORTC | PIN0 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(560))
+#define PIN_EMIOS0_CH0_3 (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(560))
+#define PIN_EMIOS0_CH1_1 (PIN_PORTB | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(561))
+#define PIN_EMIOS0_CH1_2 (PIN_PORTC | PIN1 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(561))
+#define PIN_EMIOS0_CH1_3 (PIN_PORTD | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(561))
+#define PIN_EMIOS0_CH1_4 (PIN_PORTE | PIN11 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(561))
+#define PIN_EMIOS0_CH2_1 (PIN_PORTB | PIN14 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(562))
+#define PIN_EMIOS0_CH2_2 (PIN_PORTC | PIN2 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(562))
+#define PIN_EMIOS0_CH2_3 (PIN_PORTD | PIN0 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(562))
+#define PIN_EMIOS0_CH2_4 (PIN_PORTD | PIN5 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(562))
+#define PIN_EMIOS0_CH3_1 (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(563))
+#define PIN_EMIOS0_CH3_2 (PIN_PORTB | PIN15 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(563))
+#define PIN_EMIOS0_CH3_3 (PIN_PORTC | PIN3 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(563))
+#define PIN_EMIOS0_CH3_4 (PIN_PORTD | PIN1 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(563))
+#define PIN_EMIOS0_CH3_5 (PIN_PORTE | PIN2 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(563))
+#define PIN_EMIOS0_CH4_1 (PIN_PORTB | PIN4 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(564))
+#define PIN_EMIOS0_CH4_2 (PIN_PORTB | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(564))
+#define PIN_EMIOS0_CH5_1 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(565))
+#define PIN_EMIOS0_CH5_2 (PIN_PORTB | PIN17 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(565))
+#define PIN_EMIOS0_CH6_1 (PIN_PORTA | PIN17 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(566))
+#define PIN_EMIOS0_CH6_2 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT4 | IMCR(566))
+#define PIN_EMIOS0_CH6_3 (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(566))
+#define PIN_EMIOS0_CH7_1 (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(567))
+#define PIN_EMIOS0_CH7_2 (PIN_PORTE | PIN7 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(567))
+#define PIN_EMIOS0_CH7_3 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(567))
+#define PIN_EMIOS0_CH8_1 (PIN_PORTB | PIN2 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(568))
+#define PIN_EMIOS0_CH8_2 (PIN_PORTC | PIN4 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(568))
+#define PIN_EMIOS0_CH8_3 (PIN_PORTC | PIN22 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(568))
+#define PIN_EMIOS0_CH9_1 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(569))
+#define PIN_EMIOS0_CH9_2 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(569))
+#define PIN_EMIOS0_CH10_1 (PIN_PORTA | PIN15 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(570))
+#define PIN_EMIOS0_CH10_2 (PIN_PORTC | PIN14 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(570))
+#define PIN_EMIOS0_CH11_1 (PIN_PORTA | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(571))
+#define PIN_EMIOS0_CH11_2 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(571))
+#define PIN_EMIOS0_CH12_1 (PIN_PORTA | PIN10 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(572))
+#define PIN_EMIOS0_CH12_2 (PIN_PORTD | PIN8 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(572))
+#define PIN_EMIOS0_CH13_1 (PIN_PORTA | PIN11 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(573))
+#define PIN_EMIOS0_CH13_2 (PIN_PORTD | PIN9 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(573))
+#define PIN_EMIOS0_CH14_1 (PIN_PORTA | PIN12 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(574))
+#define PIN_EMIOS0_CH14_2 (PIN_PORTC | PIN0 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(574))
+#define PIN_EMIOS0_CH15_1 (PIN_PORTA | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(575))
+#define PIN_EMIOS0_CH15_2 (PIN_PORTC | PIN1 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(575))
+#define PIN_EMIOS0_CH16_1 (PIN_PORTC | PIN5 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(576))
+#define PIN_EMIOS0_CH16_2 (PIN_PORTD | PIN0 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(576))
+#define PIN_EMIOS0_CH16_3 (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(576))
+#define PIN_EMIOS0_CH17_1 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(577))
+#define PIN_EMIOS0_CH17_2 (PIN_PORTD | PIN1 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(577))
+#define PIN_EMIOS0_CH17_3 (PIN_PORTD | PIN11 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(577))
+#define PIN_EMIOS0_CH18_1 (PIN_PORTD | PIN12 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(578))
+#define PIN_EMIOS0_CH18_2 (PIN_PORTD | PIN17 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(578))
+#define PIN_EMIOS0_CH18_3 (PIN_PORTE | PIN4 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(578))
+#define PIN_EMIOS0_CH19_1 (PIN_PORTD | PIN5 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(579))
+#define PIN_EMIOS0_CH19_2 (PIN_PORTE | PIN3 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(579))
+#define PIN_EMIOS0_CH19_3 (PIN_PORTE | PIN5 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(579))
+#define PIN_EMIOS0_CH19_4 (PIN_PORTE | PIN14 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(579))
+#define PIN_EMIOS0_CH20_1 (PIN_PORTD | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(580))
+#define PIN_EMIOS0_CH20_2 (PIN_PORTE | PIN10 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(580))
+#define PIN_EMIOS0_CH21_1 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(581))
+#define PIN_EMIOS0_CH21_2 (PIN_PORTE | PIN11 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(581))
+#define PIN_EMIOS0_CH22_1 (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(582))
+#define PIN_EMIOS0_CH22_2 (PIN_PORTE | PIN15 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(582))
+#define PIN_EMIOS0_CH22_3 (PIN_PORTE | PIN19 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(582))
+#define PIN_EMIOS0_CH23_1 (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(583))
+#define PIN_EMIOS0_CH23_2 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(583))
+
+#define PIN_EMIOS1_CH0_1 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(592))
+#define PIN_EMIOS1_CH0_2 (PIN_PORTA | PIN18 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(592))
+#define PIN_EMIOS1_CH0_3 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT6 | IMCR(592))
+#define PIN_EMIOS1_CH0_4 (PIN_PORTC | PIN24 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(592))
+#define PIN_EMIOS1_CH0_5 (PIN_PORTE | PIN20 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(592))
+#define PIN_EMIOS1_CH0_6 (PIN_PORTF | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(592))
+#define PIN_EMIOS1_CH1_1 (PIN_PORTA | PIN11 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(593))
+#define PIN_EMIOS1_CH1_2 (PIN_PORTA | PIN19 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(593))
+#define PIN_EMIOS1_CH1_3 (PIN_PORTC | PIN11 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT7 | IMCR(593))
+#define PIN_EMIOS1_CH1_4 (PIN_PORTC | PIN25 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(593))
+#define PIN_EMIOS1_CH1_5 (PIN_PORTE | PIN21 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(593))
+#define PIN_EMIOS1_CH1_6 (PIN_PORTF | PIN17 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(593))
+#define PIN_EMIOS1_CH2_1 (PIN_PORTA | PIN12 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(594))
+#define PIN_EMIOS1_CH2_2 (PIN_PORTA | PIN20 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(594))
+#define PIN_EMIOS1_CH2_3 (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(594))
+#define PIN_EMIOS1_CH2_4 (PIN_PORTE | PIN22 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(594))
+#define PIN_EMIOS1_CH2_5 (PIN_PORTF | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(594))
+#define PIN_EMIOS1_CH3_1 (PIN_PORTA | PIN13 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(595))
+#define PIN_EMIOS1_CH3_2 (PIN_PORTA | PIN21 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(595))
+#define PIN_EMIOS1_CH3_3 (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT7 | IMCR(595))
+#define PIN_EMIOS1_CH3_4 (PIN_PORTC | PIN26 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(595))
+#define PIN_EMIOS1_CH3_5 (PIN_PORTE | PIN23 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(595))
+#define PIN_EMIOS1_CH3_6 (PIN_PORTF | PIN19 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(595))
+#define PIN_EMIOS1_CH4_1 (PIN_PORTA | PIN14 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT7 | IMCR(596))
+#define PIN_EMIOS1_CH4_2 (PIN_PORTA | PIN22 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(596))
+#define PIN_EMIOS1_CH4_3 (PIN_PORTC | PIN14 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT8 | IMCR(596))
+#define PIN_EMIOS1_CH4_4 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(596))
+#define PIN_EMIOS1_CH4_5 (PIN_PORTE | PIN4 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(596))
+#define PIN_EMIOS1_CH4_6 (PIN_PORTE | PIN24 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(596))
+#define PIN_EMIOS1_CH4_7 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(596))
+#define PIN_EMIOS1_CH5_1 (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(597))
+#define PIN_EMIOS1_CH5_2 (PIN_PORTE | PIN5 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(597))
+#define PIN_EMIOS1_CH5_3 (PIN_PORTE | PIN12 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT5 | IMCR(597))
+#define PIN_EMIOS1_CH5_4 (PIN_PORTE | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(597))
+#define PIN_EMIOS1_CH5_5 (PIN_PORTE | PIN25 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(597))
+#define PIN_EMIOS1_CH5_6 (PIN_PORTF | PIN21 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(597))
+#define PIN_EMIOS1_CH6_1 (PIN_PORTA | PIN23 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(598))
+#define PIN_EMIOS1_CH6_2 (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(598))
+#define PIN_EMIOS1_CH6_3 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(598))
+#define PIN_EMIOS1_CH6_4 (PIN_PORTE | PIN26 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(598))
+#define PIN_EMIOS1_CH6_5 (PIN_PORTF | PIN22 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(598))
+#define PIN_EMIOS1_CH7_1 (PIN_PORTA | PIN24 | PIN_INPUT_ALT2 | IMCR(599))
+#define PIN_EMIOS1_CH7_2 (PIN_PORTB | PIN17 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT7 | IMCR(599))
+#define PIN_EMIOS1_CH7_3 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(599))
+#define PIN_EMIOS1_CH7_4 (PIN_PORTC | PIN28 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(599))
+#define PIN_EMIOS1_CH7_5 (PIN_PORTE | PIN27 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(599))
+#define PIN_EMIOS1_CH7_6 (PIN_PORTF | PIN23 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(599))
+#define PIN_EMIOS1_CH8_1 (PIN_PORTA | PIN25 | PIN_INPUT_ALT2 | IMCR(600))
+#define PIN_EMIOS1_CH8_2 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(600))
+#define PIN_EMIOS1_CH8_3 (PIN_PORTE | PIN2 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(600))
+#define PIN_EMIOS1_CH8_4 (PIN_PORTF | PIN24 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(600))
+#define PIN_EMIOS1_CH9_1 (PIN_PORTA | PIN26 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(601))
+#define PIN_EMIOS1_CH9_2 (PIN_PORTC | PIN8 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(601))
+#define PIN_EMIOS1_CH9_3 (PIN_PORTC | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(601))
+#define PIN_EMIOS1_CH9_4 (PIN_PORTF | PIN25 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(601))
+#define PIN_EMIOS1_CH10_1 (PIN_PORTA | PIN27 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(602))
+#define PIN_EMIOS1_CH10_2 (PIN_PORTB | PIN4 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT6 | IMCR(602))
+#define PIN_EMIOS1_CH10_3 (PIN_PORTC | PIN29 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(602))
+#define PIN_EMIOS1_CH10_4 (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(602))
+#define PIN_EMIOS1_CH10_5 (PIN_PORTF | PIN26 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(602))
+#define PIN_EMIOS1_CH11_1 (PIN_PORTA | PIN7 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(603))
+#define PIN_EMIOS1_CH11_2 (PIN_PORTA | PIN28 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(603))
+#define PIN_EMIOS1_CH11_3 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(603))
+#define PIN_EMIOS1_CH11_4 (PIN_PORTF | PIN27 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(603))
+#define PIN_EMIOS1_CH12_1 (PIN_PORTA | PIN8 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(604))
+#define PIN_EMIOS1_CH12_2 (PIN_PORTA | PIN29 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(604))
+#define PIN_EMIOS1_CH12_3 (PIN_PORTC | PIN30 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(604))
+#define PIN_EMIOS1_CH12_4 (PIN_PORTD | PIN6 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(604))
+#define PIN_EMIOS1_CH12_5 (PIN_PORTF | PIN28 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(604))
+#define PIN_EMIOS1_CH13_1 (PIN_PORTA | PIN6 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(605))
+#define PIN_EMIOS1_CH13_2 (PIN_PORTA | PIN30 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(605))
+#define PIN_EMIOS1_CH13_3 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(605))
+#define PIN_EMIOS1_CH13_4 (PIN_PORTF | PIN29 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(605))
+#define PIN_EMIOS1_CH14_1 (PIN_PORTA | PIN31 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(606))
+#define PIN_EMIOS1_CH14_2 (PIN_PORTC | PIN31 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(606))
+#define PIN_EMIOS1_CH14_3 (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(606))
+#define PIN_EMIOS1_CH14_4 (PIN_PORTE | PIN6 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT5 | IMCR(606))
+#define PIN_EMIOS1_CH14_5 (PIN_PORTF | PIN30 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(606))
+#define PIN_EMIOS1_CH15_1 (PIN_PORTB | PIN8 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT6 | IMCR(607))
+#define PIN_EMIOS1_CH15_2 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(607))
+#define PIN_EMIOS1_CH15_3 (PIN_PORTB | PIN19 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(607))
+#define PIN_EMIOS1_CH15_4 (PIN_PORTD | PIN16 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT7 | IMCR(607))
+#define PIN_EMIOS1_CH15_5 (PIN_PORTD | PIN18 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(607))
+#define PIN_EMIOS1_CH15_6 (PIN_PORTF | PIN31 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(607))
+#define PIN_EMIOS1_CH16_1 (PIN_PORTA | PIN18 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(608))
+#define PIN_EMIOS1_CH16_2 (PIN_PORTB | PIN9 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(608))
+#define PIN_EMIOS1_CH16_3 (PIN_PORTB | PIN20 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(608))
+#define PIN_EMIOS1_CH16_4 (PIN_PORTD | PIN19 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(608))
+#define PIN_EMIOS1_CH16_5 (PIN_PORTG | PIN0 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(608))
+#define PIN_EMIOS1_CH17_1 (PIN_PORTB | PIN10 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(609))
+#define PIN_EMIOS1_CH17_2 (PIN_PORTB | PIN21 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(609))
+#define PIN_EMIOS1_CH17_3 (PIN_PORTD | PIN20 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(609))
+#define PIN_EMIOS1_CH17_4 (PIN_PORTG | PIN1 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(609))
+#define PIN_EMIOS1_CH18_1 (PIN_PORTB | PIN11 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(610))
+#define PIN_EMIOS1_CH18_2 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(610))
+#define PIN_EMIOS1_CH18_3 (PIN_PORTD | PIN21 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(610))
+#define PIN_EMIOS1_CH18_4 (PIN_PORTG | PIN2 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(610))
+#define PIN_EMIOS1_CH19_1 (PIN_PORTA | PIN2 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(611))
+#define PIN_EMIOS1_CH19_2 (PIN_PORTB | PIN23 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(611))
+#define PIN_EMIOS1_CH19_3 (PIN_PORTD | PIN22 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(611))
+#define PIN_EMIOS1_CH19_4 (PIN_PORTG | PIN3 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(611))
+#define PIN_EMIOS1_CH20_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(612))
+#define PIN_EMIOS1_CH20_2 (PIN_PORTB | PIN24 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(612))
+#define PIN_EMIOS1_CH20_3 (PIN_PORTD | PIN23 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(612))
+#define PIN_EMIOS1_CH20_4 (PIN_PORTG | PIN4 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(612))
+#define PIN_EMIOS1_CH21_1 (PIN_PORTB | PIN25 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(613))
+#define PIN_EMIOS1_CH21_2 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(613))
+#define PIN_EMIOS1_CH21_3 (PIN_PORTD | PIN24 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(613))
+#define PIN_EMIOS1_CH21_4 (PIN_PORTG | PIN5 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(613))
+#define PIN_EMIOS1_CH22_1 (PIN_PORTB | PIN26 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(614))
+#define PIN_EMIOS1_CH22_2 (PIN_PORTD | PIN3 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(614))
+#define PIN_EMIOS1_CH22_3 (PIN_PORTD | PIN25 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(614))
+#define PIN_EMIOS1_CH22_4 (PIN_PORTG | PIN6 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(614))
+#define PIN_EMIOS1_CH23_1 (PIN_PORTB | PIN27 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(615))
+#define PIN_EMIOS1_CH23_2 (PIN_PORTD | PIN4 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(615))
+#define PIN_EMIOS1_CH23_3 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(615))
+#define PIN_EMIOS1_CH23_4 (PIN_PORTG | PIN7 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(615))
+
+#define PIN_EMIOS2_CH0_1 (PIN_PORTA | PIN18 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(624))
+#define PIN_EMIOS2_CH0_2 (PIN_PORTC | PIN24 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT5 | IMCR(624))
+#define PIN_EMIOS2_CH0_3 (PIN_PORTD | PIN20 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(624))
+#define PIN_EMIOS2_CH0_4 (PIN_PORTD | PIN28 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(624))
+#define PIN_EMIOS2_CH0_5 (PIN_PORTF | PIN0 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(624))
+#define PIN_EMIOS2_CH1_1 (PIN_PORTA | PIN19 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(625))
+#define PIN_EMIOS2_CH1_2 (PIN_PORTC | PIN25 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(625))
+#define PIN_EMIOS2_CH1_3 (PIN_PORTF | PIN1 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(625))
+#define PIN_EMIOS2_CH2_1 (PIN_PORTA | PIN20 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(626))
+#define PIN_EMIOS2_CH2_2 (PIN_PORTC | PIN26 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(626))
+#define PIN_EMIOS2_CH2_3 (PIN_PORTF | PIN2 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(626))
+#define PIN_EMIOS2_CH3_1 (PIN_PORTA | PIN21 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(627))
+#define PIN_EMIOS2_CH3_2 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(627))
+#define PIN_EMIOS2_CH3_3 (PIN_PORTF | PIN3 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(627))
+#define PIN_EMIOS2_CH4_1 (PIN_PORTC | PIN29 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(628))
+#define PIN_EMIOS2_CH4_2 (PIN_PORTE | PIN24 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(628))
+#define PIN_EMIOS2_CH4_3 (PIN_PORTF | PIN4 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(628))
+#define PIN_EMIOS2_CH5_1 (PIN_PORTC | PIN30 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(629))
+#define PIN_EMIOS2_CH5_2 (PIN_PORTE | PIN25 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(629))
+#define PIN_EMIOS2_CH5_3 (PIN_PORTF | PIN5 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(629))
+#define PIN_EMIOS2_CH6_1 (PIN_PORTC | PIN31 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(630))
+#define PIN_EMIOS2_CH6_2 (PIN_PORTE | PIN26 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(630))
+#define PIN_EMIOS2_CH6_3 (PIN_PORTF | PIN6 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(630))
+#define PIN_EMIOS2_CH7_1 (PIN_PORTA | PIN8 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(631))
+#define PIN_EMIOS2_CH7_2 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(631))
+#define PIN_EMIOS2_CH7_3 (PIN_PORTF | PIN7 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(631))
+#define PIN_EMIOS2_CH8_1 (PIN_PORTA | PIN25 | PIN_INPUT_ALT2 | IMCR(632))
+#define PIN_EMIOS2_CH8_2 (PIN_PORTD | PIN21 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(632))
+#define PIN_EMIOS2_CH8_3 (PIN_PORTD | PIN29 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(632))
+#define PIN_EMIOS2_CH8_4 (PIN_PORTF | PIN8 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(632))
+#define PIN_EMIOS2_CH9_1 (PIN_PORTA | PIN26 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(633))
+#define PIN_EMIOS2_CH9_2 (PIN_PORTC | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(633))
+#define PIN_EMIOS2_CH9_3 (PIN_PORTD | PIN27 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(633))
+#define PIN_EMIOS2_CH9_4 (PIN_PORTF | PIN9 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(633))
+#define PIN_EMIOS2_CH10_1 (PIN_PORTA | PIN27 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(634))
+#define PIN_EMIOS2_CH10_2 (PIN_PORTB | PIN28 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(634))
+#define PIN_EMIOS2_CH10_3 (PIN_PORTF | PIN10 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(634))
+#define PIN_EMIOS2_CH11_1 (PIN_PORTA | PIN28 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(635))
+#define PIN_EMIOS2_CH11_2 (PIN_PORTB | PIN29 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(635))
+#define PIN_EMIOS2_CH11_3 (PIN_PORTF | PIN11 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(635))
+#define PIN_EMIOS2_CH12_1 (PIN_PORTA | PIN29 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(636))
+#define PIN_EMIOS2_CH12_2 (PIN_PORTC | PIN18 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(636))
+#define PIN_EMIOS2_CH12_3 (PIN_PORTF | PIN12 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(636))
+#define PIN_EMIOS2_CH13_1 (PIN_PORTA | PIN30 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(637))
+#define PIN_EMIOS2_CH13_2 (PIN_PORTC | PIN19 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(637))
+#define PIN_EMIOS2_CH13_3 (PIN_PORTF | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(637))
+#define PIN_EMIOS2_CH14_1 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(638))
+#define PIN_EMIOS2_CH14_2 (PIN_PORTC | PIN20 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(638))
+#define PIN_EMIOS2_CH14_3 (PIN_PORTF | PIN14 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(638))
+#define PIN_EMIOS2_CH15_1 (PIN_PORTB | PIN19 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(639))
+#define PIN_EMIOS2_CH15_2 (PIN_PORTC | PIN21 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT5 | IMCR(639))
+#define PIN_EMIOS2_CH15_3 (PIN_PORTF | PIN15 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(639))
+#define PIN_EMIOS2_CH15_4 (PIN_PORTG | PIN15 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(639))
+#define PIN_EMIOS2_CH16_1 (PIN_PORTB | PIN20 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(640))
+#define PIN_EMIOS2_CH16_2 (PIN_PORTD | PIN30 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(640))
+#define PIN_EMIOS2_CH16_3 (PIN_PORTF | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT4 | IMCR(640))
+#define PIN_EMIOS2_CH16_4 (PIN_PORTG | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(640))
+#define PIN_EMIOS2_CH17_1 (PIN_PORTB | PIN21 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(641))
+#define PIN_EMIOS2_CH17_2 (PIN_PORTE | PIN18 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(641))
+#define PIN_EMIOS2_CH17_3 (PIN_PORTF | PIN17 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(641))
+#define PIN_EMIOS2_CH17_4 (PIN_PORTG | PIN17 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(641))
+#define PIN_EMIOS2_CH18_1 (PIN_PORTA | PIN14 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(642))
+#define PIN_EMIOS2_CH18_2 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(642))
+#define PIN_EMIOS2_CH18_3 (PIN_PORTF | PIN18 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(642))
+#define PIN_EMIOS2_CH18_4 (PIN_PORTG | PIN18 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(642))
+#define PIN_EMIOS2_CH19_1 (PIN_PORTB | PIN23 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(643))
+#define PIN_EMIOS2_CH19_2 (PIN_PORTE | PIN21 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(643))
+#define PIN_EMIOS2_CH19_3 (PIN_PORTF | PIN19 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(643))
+#define PIN_EMIOS2_CH19_4 (PIN_PORTG | PIN19 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(643))
+#define PIN_EMIOS2_CH20_1 (PIN_PORTB | PIN24 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(644))
+#define PIN_EMIOS2_CH20_2 (PIN_PORTE | PIN22 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(644))
+#define PIN_EMIOS2_CH20_3 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(644))
+#define PIN_EMIOS2_CH20_4 (PIN_PORTG | PIN20 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(644))
+#define PIN_EMIOS2_CH21_1 (PIN_PORTB | PIN25 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(645))
+#define PIN_EMIOS2_CH21_2 (PIN_PORTE | PIN23 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(645))
+#define PIN_EMIOS2_CH21_3 (PIN_PORTF | PIN21 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(645))
+#define PIN_EMIOS2_CH21_4 (PIN_PORTG | PIN21 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(645))
+#define PIN_EMIOS2_CH22_1 (PIN_PORTB | PIN26 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(646))
+#define PIN_EMIOS2_CH22_2 (PIN_PORTD | PIN22 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(646))
+#define PIN_EMIOS2_CH22_3 (PIN_PORTD | PIN31 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(646))
+#define PIN_EMIOS2_CH22_4 (PIN_PORTF | PIN22 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(646))
+#define PIN_EMIOS2_CH22_5 (PIN_PORTG | PIN22 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(646))
+#define PIN_EMIOS2_CH23_1 (PIN_PORTB | PIN27 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(647))
+#define PIN_EMIOS2_CH23_2 (PIN_PORTD | PIN23 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(647))
+#define PIN_EMIOS2_CH23_3 (PIN_PORTE | PIN17 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(647))
+#define PIN_EMIOS2_CH23_4 (PIN_PORTF | PIN23 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(647))
+#define PIN_EMIOS2_CH23_5 (PIN_PORTG | PIN23 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(647))
+
+/* Fault Collection and Control Unit (FCCU) */
+
+#define PIN_FCCU_ERR_IN0_1 (PIN_PORTA | PIN2 | PIN_INPUT_ALT1 | IMCR(660))
+#define PIN_FCCU_ERR_IN0_2 (PIN_PORTE | PIN15 | PIN_INPUT_ALT2 | IMCR(660))
+#define PIN_FCCU_ERR_IN0_3 (PIN_PORTF | PIN14 | PIN_INPUT_ALT3 | IMCR(660))
+#define PIN_FCCU_ERR_IN1_1 (PIN_PORTA | PIN3 | PIN_INPUT_ALT1 | IMCR(661))
+#define PIN_FCCU_ERR_IN1_2 (PIN_PORTE | PIN16 | PIN_INPUT_ALT2 | IMCR(661))
+#define PIN_FCCU_ERR_IN1_3 (PIN_PORTF | PIN15 | PIN_INPUT_ALT3 | IMCR(661))
+#define PIN_FCCU_ERR_OUT0_1 (PIN_PORTA | PIN2 | PIN_OUTPUT_ALT1)
+#define PIN_FCCU_ERR_OUT0_2 (PIN_PORTE | PIN15 | PIN_OUTPUT_ALT1)
+#define PIN_FCCU_ERR_OUT0_3 (PIN_PORTF | PIN14 | PIN_OUTPUT_ALT4)
+#define PIN_FCCU_ERR_OUT1_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT1)
+#define PIN_FCCU_ERR_OUT1_2 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT1)
+#define PIN_FCCU_ERR_OUT1_3 (PIN_PORTF | PIN15 | PIN_OUTPUT_ALT5)
+
+/* FlexIO */
+
+#define PIN_FXIO_D0_1 (PIN_PORTA | PIN10 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(664))
+#define PIN_FXIO_D0_2 (PIN_PORTA | PIN21 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(664))
+#define PIN_FXIO_D0_3 (PIN_PORTA | PIN31 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(664))
+#define PIN_FXIO_D0_4 (PIN_PORTC | PIN30 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(664))
+#define PIN_FXIO_D0_5 (PIN_PORTD | PIN0 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(664))
+#define PIN_FXIO_D0_6 (PIN_PORTD | PIN9 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(664))
+#define PIN_FXIO_D0_7 (PIN_PORTF | PIN4 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT7 | IMCR(664))
+#define PIN_FXIO_D1_1 (PIN_PORTA | PIN11 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(665))
+#define PIN_FXIO_D1_2 (PIN_PORTA | PIN22 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(665))
+#define PIN_FXIO_D1_3 (PIN_PORTA | PIN26 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT7 | IMCR(665))
+#define PIN_FXIO_D1_4 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(665))
+#define PIN_FXIO_D1_5 (PIN_PORTC | PIN31 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(665))
+#define PIN_FXIO_D1_6 (PIN_PORTD | PIN1 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(665))
+#define PIN_FXIO_D1_7 (PIN_PORTD | PIN8 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT5 | IMCR(665))
+#define PIN_FXIO_D1_8 (PIN_PORTF | PIN7 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT8 | IMCR(665))
+#define PIN_FXIO_D2_1 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(666))
+#define PIN_FXIO_D2_2 (PIN_PORTA | PIN23 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(666))
+#define PIN_FXIO_D2_3 (PIN_PORTA | PIN25 | PIN_INPUT_ALT6 | IMCR(666))
+#define PIN_FXIO_D2_4 (PIN_PORTB | PIN19 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(666))
+#define PIN_FXIO_D2_5 (PIN_PORTC | PIN28 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT7 | IMCR(666))
+#define PIN_FXIO_D2_6 (PIN_PORTD | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(666))
+#define PIN_FXIO_D2_7 (PIN_PORTE | PIN1 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT8 | IMCR(666))
+#define PIN_FXIO_D2_8 (PIN_PORTE | PIN15 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(666))
+#define PIN_FXIO_D2_9 (PIN_PORTF | PIN8 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT9 | IMCR(666))
+#define PIN_FXIO_D3_1 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(667))
+#define PIN_FXIO_D3_2 (PIN_PORTA | PIN24 | PIN_INPUT_ALT3 | IMCR(667))
+#define PIN_FXIO_D3_3 (PIN_PORTB | PIN20 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(667))
+#define PIN_FXIO_D3_4 (PIN_PORTC | PIN29 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT6 | IMCR(667))
+#define PIN_FXIO_D3_5 (PIN_PORTD | PIN19 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(667))
+#define PIN_FXIO_D3_6 (PIN_PORTE | PIN0 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT7 | IMCR(667))
+#define PIN_FXIO_D3_7 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(667))
+#define PIN_FXIO_D3_8 (PIN_PORTF | PIN14 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT8 | IMCR(667))
+#define PIN_FXIO_D4_1 (PIN_PORTA | PIN2 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(668))
+#define PIN_FXIO_D4_2 (PIN_PORTB | PIN21 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(668))
+#define PIN_FXIO_D4_3 (PIN_PORTB | PIN23 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(668))
+#define PIN_FXIO_D4_4 (PIN_PORTC | PIN5 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT7 | IMCR(668))
+#define PIN_FXIO_D4_5 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(668))
+#define PIN_FXIO_D4_6 (PIN_PORTE | PIN10 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(668))
+#define PIN_FXIO_D4_7 (PIN_PORTE | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(668))
+#define PIN_FXIO_D4_8 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT8 | IMCR(668))
+#define PIN_FXIO_D5_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(669))
+#define PIN_FXIO_D5_2 (PIN_PORTA | PIN27 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT9 | IMCR(669))
+#define PIN_FXIO_D5_3 (PIN_PORTB | PIN24 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(669))
+#define PIN_FXIO_D5_4 (PIN_PORTC | PIN1 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT7 | IMCR(669))
+#define PIN_FXIO_D5_5 (PIN_PORTC | PIN4 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT8 | IMCR(669))
+#define PIN_FXIO_D5_6 (PIN_PORTD | PIN3 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(669))
+#define PIN_FXIO_D5_7 (PIN_PORTE | PIN11 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(669))
+#define PIN_FXIO_D5_8 (PIN_PORTE | PIN13 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(669))
+#define PIN_FXIO_D5_9 (PIN_PORTE | PIN17 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(669))
+#define PIN_FXIO_D5_10 (PIN_PORTE | PIN24 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT10 | IMCR(669))
+#define PIN_FXIO_D5_11 (PIN_PORTF | PIN21 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT11 | IMCR(669))
+#define PIN_FXIO_D6_1 (PIN_PORTA | PIN4 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT8 | IMCR(670))
+#define PIN_FXIO_D6_2 (PIN_PORTA | PIN8 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(670))
+#define PIN_FXIO_D6_3 (PIN_PORTB | PIN25 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(670))
+#define PIN_FXIO_D6_4 (PIN_PORTC | PIN18 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT9 | IMCR(670))
+#define PIN_FXIO_D6_5 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(670))
+#define PIN_FXIO_D6_6 (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT7 | IMCR(670))
+#define PIN_FXIO_D6_7 (PIN_PORTD | PIN31 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(670))
+#define PIN_FXIO_D6_8 (PIN_PORTE | PIN3 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT6 | IMCR(670))
+#define PIN_FXIO_D6_9 (PIN_PORTE | PIN4 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(670))
+#define PIN_FXIO_D6_10 (PIN_PORTF | PIN25 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT10 | IMCR(670))
+#define PIN_FXIO_D7_1 (PIN_PORTA | PIN9 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(671))
+#define PIN_FXIO_D7_2 (PIN_PORTB | PIN26 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(671))
+#define PIN_FXIO_D7_3 (PIN_PORTD | PIN3 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(671))
+#define PIN_FXIO_D7_4 (PIN_PORTD | PIN13 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT7 | IMCR(671))
+#define PIN_FXIO_D7_5 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(671))
+#define PIN_FXIO_D7_6 (PIN_PORTE | PIN5 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(671))
+#define PIN_FXIO_D7_7 (PIN_PORTE | PIN14 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(671))
+#define PIN_FXIO_D7_8 (PIN_PORTF | PIN28 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT8 | IMCR(671))
+#define PIN_FXIO_D8_1 (PIN_PORTA | PIN13 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(672))
+#define PIN_FXIO_D8_2 (PIN_PORTB | PIN13 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(672))
+#define PIN_FXIO_D8_3 (PIN_PORTB | PIN27 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(672))
+#define PIN_FXIO_D8_4 (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT5 | IMCR(672))
+#define PIN_FXIO_D8_5 (PIN_PORTE | PIN12 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(672))
+#define PIN_FXIO_D8_6 (PIN_PORTF | PIN29 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT6 | IMCR(672))
+#define PIN_FXIO_D9_1 (PIN_PORTA | PIN7 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(673))
+#define PIN_FXIO_D9_2 (PIN_PORTA | PIN12 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(673))
+#define PIN_FXIO_D9_3 (PIN_PORTB | PIN28 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(673))
+#define PIN_FXIO_D9_4 (PIN_PORTD | PIN17 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(673))
+#define PIN_FXIO_D9_5 (PIN_PORTF | PIN31 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(673))
+#define PIN_FXIO_D10_1 (PIN_PORTB | PIN29 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(674))
+#define PIN_FXIO_D10_2 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(674))
+#define PIN_FXIO_D10_3 (PIN_PORTD | PIN9 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT4 | IMCR(674))
+#define PIN_FXIO_D10_4 (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(674))
+#define PIN_FXIO_D10_5 (PIN_PORTG | PIN6 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(674))
+#define PIN_FXIO_D11_1 (PIN_PORTB | PIN30 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(675))
+#define PIN_FXIO_D11_2 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(675))
+#define PIN_FXIO_D11_3 (PIN_PORTD | PIN8 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT5 | IMCR(675))
+#define PIN_FXIO_D11_4 (PIN_PORTE | PIN7 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT4 | IMCR(675))
+#define PIN_FXIO_D11_5 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(675))
+#define PIN_FXIO_D11_6 (PIN_PORTE | PIN24 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT6 | IMCR(675))
+#define PIN_FXIO_D11_7 (PIN_PORTG | PIN7 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT7 | IMCR(675))
+#define PIN_FXIO_D12_1 (PIN_PORTC | PIN8 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT3 | IMCR(676))
+#define PIN_FXIO_D12_2 (PIN_PORTC | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(676))
+#define PIN_FXIO_D12_3 (PIN_PORTE | PIN6 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(676))
+#define PIN_FXIO_D12_4 (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(676))
+#define PIN_FXIO_D12_5 (PIN_PORTG | PIN8 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(676))
+#define PIN_FXIO_D13_1 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT3 | IMCR(677))
+#define PIN_FXIO_D13_2 (PIN_PORTC | PIN19 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(677))
+#define PIN_FXIO_D13_3 (PIN_PORTD | PIN6 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(677))
+#define PIN_FXIO_D13_4 (PIN_PORTE | PIN2 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(677))
+#define PIN_FXIO_D13_5 (PIN_PORTG | PIN13 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(677))
+#define PIN_FXIO_D14_1 (PIN_PORTA | PIN14 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(678))
+#define PIN_FXIO_D14_2 (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(678))
+#define PIN_FXIO_D14_3 (PIN_PORTC | PIN17 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(678))
+#define PIN_FXIO_D14_4 (PIN_PORTC | PIN20 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(678))
+#define PIN_FXIO_D14_5 (PIN_PORTG | PIN15 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(678))
+#define PIN_FXIO_D15_1 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(679))
+#define PIN_FXIO_D15_2 (PIN_PORTC | PIN11 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(679))
+#define PIN_FXIO_D15_3 (PIN_PORTC | PIN16 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(679))
+#define PIN_FXIO_D15_4 (PIN_PORTC | PIN21 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(679))
+#define PIN_FXIO_D15_5 (PIN_PORTD | PIN5 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(679))
+#define PIN_FXIO_D15_6 (PIN_PORTG | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(679))
+#define PIN_FXIO_D16_1 (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(680))
+#define PIN_FXIO_D16_2 (PIN_PORTC | PIN14 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(680))
+#define PIN_FXIO_D16_3 (PIN_PORTC | PIN23 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(680))
+#define PIN_FXIO_D16_4 (PIN_PORTG | PIN17 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(680))
+#define PIN_FXIO_D17_1 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(681))
+#define PIN_FXIO_D17_2 (PIN_PORTC | PIN24 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(681))
+#define PIN_FXIO_D17_3 (PIN_PORTG | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(681))
+#define PIN_FXIO_D18_1 (PIN_PORTB | PIN2 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(682))
+#define PIN_FXIO_D18_2 (PIN_PORTC | PIN25 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(682))
+#define PIN_FXIO_D18_3 (PIN_PORTG | PIN19 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(682))
+#define PIN_FXIO_D19_1 (PIN_PORTA | PIN6 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(683))
+#define PIN_FXIO_D19_2 (PIN_PORTA | PIN17 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(683))
+#define PIN_FXIO_D19_3 (PIN_PORTC | PIN11 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(683))
+#define PIN_FXIO_D19_4 (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT5 | IMCR(683))
+#define PIN_FXIO_D19_5 (PIN_PORTC | PIN26 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(683))
+#define PIN_FXIO_D19_6 (PIN_PORTG | PIN20 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(683))
+#define PIN_FXIO_D20_1 (PIN_PORTB | PIN17 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(684))
+#define PIN_FXIO_D20_2 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(684))
+#define PIN_FXIO_D20_3 (PIN_PORTG | PIN21 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(684))
+#define PIN_FXIO_D21_1 (PIN_PORTB | PIN16 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(685))
+#define PIN_FXIO_D21_2 (PIN_PORTC | PIN28 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(685))
+#define PIN_FXIO_D21_3 (PIN_PORTG | PIN22 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(685))
+#define PIN_FXIO_D22_1 (PIN_PORTB | PIN15 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(686))
+#define PIN_FXIO_D22_2 (PIN_PORTC | PIN29 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(686))
+#define PIN_FXIO_D22_3 (PIN_PORTG | PIN23 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(686))
+#define PIN_FXIO_D23_1 (PIN_PORTB | PIN14 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(687))
+#define PIN_FXIO_D23_2 (PIN_PORTC | PIN30 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(687))
+#define PIN_FXIO_D23_3 (PIN_PORTG | PIN24 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(687))
+#define PIN_FXIO_D24_1 (PIN_PORTB | PIN13 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(688))
+#define PIN_FXIO_D24_2 (PIN_PORTC | PIN31 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(688))
+#define PIN_FXIO_D24_3 (PIN_PORTG | PIN25 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(688))
+#define PIN_FXIO_D25_1 (PIN_PORTB | PIN12 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(689))
+#define PIN_FXIO_D25_2 (PIN_PORTD | PIN20 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(689))
+#define PIN_FXIO_D25_3 (PIN_PORTG | PIN26 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(689))
+#define PIN_FXIO_D26_1 (PIN_PORTB | PIN11 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(690))
+#define PIN_FXIO_D26_2 (PIN_PORTD | PIN21 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(690))
+#define PIN_FXIO_D26_3 (PIN_PORTG | PIN27 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(690))
+#define PIN_FXIO_D27_1 (PIN_PORTB | PIN10 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(691))
+#define PIN_FXIO_D27_2 (PIN_PORTD | PIN22 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(691))
+#define PIN_FXIO_D28_1 (PIN_PORTB | PIN9 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(692))
+#define PIN_FXIO_D28_2 (PIN_PORTD | PIN23 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(692))
+#define PIN_FXIO_D29_1 (PIN_PORTB | PIN8 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(693))
+#define PIN_FXIO_D29_2 (PIN_PORTD | PIN24 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(693))
+#define PIN_FXIO_D30_1 (PIN_PORTA | PIN16 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(694))
+#define PIN_FXIO_D30_2 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(694))
+#define PIN_FXIO_D31_1 (PIN_PORTA | PIN15 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(695))
+#define PIN_FXIO_D31_2 (PIN_PORTD | PIN27 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(695))
+
+/* Hardware Security Engine (HSE) */
+
+#define PIN_HSE_TAMPER_EXTIN0_1 (PIN_PORTB | PIN1 | PIN_INPUT_ALT1 | IMCR(855))
+#define PIN_HSE_TAMPER_EXTIN0_2 (PIN_PORTB | PIN31 | PIN_INPUT_ALT3 | IMCR(855))
+#define PIN_HSE_TAMPER_EXTIN0_3 (PIN_PORTD | PIN24 | PIN_INPUT_ALT2 | IMCR(855))
+#define PIN_HSE_TAMPER_EXTIN0_4 (PIN_PORTF | PIN11 | PIN_INPUT_ALT4 | IMCR(855))
+#define PIN_HSE_TAMPER_LOOP_OUT0_1 (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT7)
+#define PIN_HSE_TAMPER_LOOP_OUT0_2 (PIN_PORTB | PIN30 | PIN_OUTPUT_ALT5)
+#define PIN_HSE_TAMPER_LOOP_OUT0_3 (PIN_PORTD | PIN23 | PIN_OUTPUT_ALT5)
+#define PIN_HSE_TAMPER_LOOP_OUT0_4 (PIN_PORTF | PIN19 | PIN_OUTPUT_ALT6)
+
+/* JTAG Debug */
+
+#define PIN_JTAG_TCK (PIN_PORTC | PIN4 | PIN_INPUT_ALT0 | IMCR(696))
+#define PIN_JTAG_TDI (PIN_PORTC | PIN5 | PIN_INPUT_ALT0 | IMCR(697))
+#define PIN_JTAG_TDO (PIN_PORTA | PIN10 | PIN_OUTPUT_ALT7)
+#define PIN_JTAG_TMS (PIN_PORTA | PIN4 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT0 | IMCR(698))
+
+/* Logic Control Unit (LCU) */
+
+#define PIN_LCU0_OUT0_1 (PIN_PORTD | PIN3 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT0_2 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT7)
+#define PIN_LCU0_OUT1_1 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT1)
+#define PIN_LCU0_OUT1_2 (PIN_PORTD | PIN27 | PIN_OUTPUT_ALT7)
+#define PIN_LCU0_OUT2_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT4)
+#define PIN_LCU0_OUT2_2 (PIN_PORTB | PIN12 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT2_3 (PIN_PORTD | PIN28 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT3_1 (PIN_PORTA | PIN2 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT3_2 (PIN_PORTB | PIN13 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT3_3 (PIN_PORTD | PIN29 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT4_1 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT3)
+#define PIN_LCU0_OUT4_2 (PIN_PORTD | PIN21 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT5_1 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT5_2 (PIN_PORTD | PIN22 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT6_1 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT4)
+#define PIN_LCU0_OUT6_2 (PIN_PORTD | PIN4 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT7_1 (PIN_PORTB | PIN14 | PIN_OUTPUT_ALT4)
+#define PIN_LCU0_OUT7_2 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT4)
+#define PIN_LCU0_OUT8_1 (PIN_PORTB | PIN11 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT8_2 (PIN_PORTD | PIN30 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT9_1 (PIN_PORTB | PIN10 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT9_2 (PIN_PORTD | PIN31 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT10_1 (PIN_PORTB | PIN9 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT10_2 (PIN_PORTD | PIN23 | PIN_OUTPUT_ALT6)
+#define PIN_LCU0_OUT11_1 (PIN_PORTB | PIN8 | PIN_OUTPUT_ALT5)
+#define PIN_LCU0_OUT11_2 (PIN_PORTD | PIN24 | PIN_OUTPUT_ALT6)
+
+#define PIN_LCU1_OUT0_1 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT0_2 (PIN_PORTC | PIN23 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT1_1 (PIN_PORTC | PIN14 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT1_2 (PIN_PORTC | PIN24 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT2_1 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT2_2 (PIN_PORTC | PIN25 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT3_1 (PIN_PORTB | PIN2 | PIN_OUTPUT_ALT5)
+#define PIN_LCU1_OUT3_2 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT4_1 (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT7)
+#define PIN_LCU1_OUT4_2 (PIN_PORTC | PIN21 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT5_1 (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT5)
+#define PIN_LCU1_OUT5_2 (PIN_PORTC | PIN20 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT6_1 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT5)
+#define PIN_LCU1_OUT6_2 (PIN_PORTC | PIN19 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT7_1 (PIN_PORTC | PIN8 | PIN_OUTPUT_ALT5)
+#define PIN_LCU1_OUT7_2 (PIN_PORTC | PIN18 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT8_1 (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT8_2 (PIN_PORTC | PIN28 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT9_1 (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT9_2 (PIN_PORTC | PIN26 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT10_1 (PIN_PORTB | PIN29 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT10_2 (PIN_PORTC | PIN11 | PIN_OUTPUT_ALT7)
+#define PIN_LCU1_OUT11_1 (PIN_PORTB | PIN28 | PIN_OUTPUT_ALT6)
+#define PIN_LCU1_OUT11_2 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT6)
+
+/* LPI2C */
+
+#define PIN_LPI2C0_HREQ_1 (PIN_PORTB | PIN11 | PIN_INPUT_ALT1 | IMCR(723))
+#define PIN_LPI2C0_HREQ_2 (PIN_PORTC | PIN7 | PIN_INPUT_ALT2 | IMCR(723))
+#define PIN_LPI2C0_SCL_1 (PIN_PORTC | PIN8 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(724))
+#define PIN_LPI2C0_SCL_2 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(724))
+#define PIN_LPI2C0_SCL_3 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(724))
+#define PIN_LPI2C0_SCLS (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(725))
+#define PIN_LPI2C0_SDA_1 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(726))
+#define PIN_LPI2C0_SDA_2 (PIN_PORTD | PIN13 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(726))
+#define PIN_LPI2C0_SDA_3 (PIN_PORTF | PIN21 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(726))
+#define PIN_LPI2C0_SDAS (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(727))
+
+#define PIN_LPI2C1_HREQ_1 (PIN_PORTC | PIN5 | PIN_INPUT_ALT2 | IMCR(728))
+#define PIN_LPI2C1_HREQ_2 (PIN_PORTD | PIN12 | PIN_INPUT_ALT1 | IMCR(728))
+#define PIN_LPI2C1_SCL_1 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(729))
+#define PIN_LPI2C1_SCL_2 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT6 | IMCR(729))
+#define PIN_LPI2C1_SCL_3 (PIN_PORTC | PIN28 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(729))
+#define PIN_LPI2C1_SCL_4 (PIN_PORTD | PIN9 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(729))
+#define PIN_LPI2C1_SCL_5 (PIN_PORTF | PIN7 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(729))
+#define PIN_LPI2C1_SCLS (PIN_PORTC | PIN17 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(730))
+#define PIN_LPI2C1_SDA_1 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(731))
+#define PIN_LPI2C1_SDA_2 (PIN_PORTC | PIN16 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT5 | IMCR(731))
+#define PIN_LPI2C1_SDA_3 (PIN_PORTC | PIN29 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(731))
+#define PIN_LPI2C1_SDA_4 (PIN_PORTD | PIN8 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(731))
+#define PIN_LPI2C1_SDA_5 (PIN_PORTF | PIN8 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(731))
+#define PIN_LPI2C1_SDAS (PIN_PORTC | PIN16 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(732))
+
+/* LPSPI */
+
+#define PIN_LPSPI0_PCS0_1 (PIN_PORTA | PIN26 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(733))
+#define PIN_LPSPI0_PCS0_2 (PIN_PORTB | PIN0 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(733))
+#define PIN_LPSPI0_PCS0_3 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(733))
+#define PIN_LPSPI0_PCS0_4 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT6 | IMCR(733))
+#define PIN_LPSPI0_PCS0_5 (PIN_PORTD | PIN6 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT7 | IMCR(733))
+#define PIN_LPSPI0_PCS0_6 (PIN_PORTE | PIN4 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT5 | IMCR(733))
+#define PIN_LPSPI0_PCS0_7 (PIN_PORTF | PIN28 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(733))
+#define PIN_LPSPI0_PCS1_1 (PIN_PORTA | PIN7 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(734))
+#define PIN_LPSPI0_PCS1_2 (PIN_PORTA | PIN31 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(734))
+#define PIN_LPSPI0_PCS1_3 (PIN_PORTB | PIN5 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(734))
+#define PIN_LPSPI0_PCS1_4 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(734))
+#define PIN_LPSPI0_PCS1_5 (PIN_PORTD | PIN5 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT5 | IMCR(734))
+#define PIN_LPSPI0_PCS2_1 (PIN_PORTC | PIN2 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(735))
+#define PIN_LPSPI0_PCS2_2 (PIN_PORTE | PIN6 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(735))
+#define PIN_LPSPI0_PCS3_1 (PIN_PORTA | PIN15 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(736))
+#define PIN_LPSPI0_PCS3_2 (PIN_PORTD | PIN7 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(736))
+#define PIN_LPSPI0_PCS4 (PIN_PORTA | PIN16 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(737))
+#define PIN_LPSPI0_PCS5 (PIN_PORTB | PIN8 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(738))
+#define PIN_LPSPI0_PCS6 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(739))
+#define PIN_LPSPI0_PCS7 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(740))
+#define PIN_LPSPI0_SCK_1 (PIN_PORTC | PIN8 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(741))
+#define PIN_LPSPI0_SCK_2 (PIN_PORTD | PIN11 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(741))
+#define PIN_LPSPI0_SCK_3 (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(741))
+#define PIN_LPSPI0_SCK_4 (PIN_PORTE | PIN1 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(741))
+#define PIN_LPSPI0_SIN_1 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(742))
+#define PIN_LPSPI0_SIN_2 (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(742))
+#define PIN_LPSPI0_SIN_3 (PIN_PORTD | PIN16 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(742))
+#define PIN_LPSPI0_SIN_4 (PIN_PORTE | PIN0 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(742))
+#define PIN_LPSPI0_SOUT_1 (PIN_PORTA | PIN30 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(743))
+#define PIN_LPSPI0_SOUT_2 (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(743))
+#define PIN_LPSPI0_SOUT_3 (PIN_PORTB | PIN4 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(743))
+#define PIN_LPSPI0_SOUT_4 (PIN_PORTD | PIN12 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(743))
+#define PIN_LPSPI0_SOUT_5 (PIN_PORTE | PIN2 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(743))
+
+#define PIN_LPSPI1_PCS0_1 (PIN_PORTA | PIN11 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(744))
+#define PIN_LPSPI1_PCS0_2 (PIN_PORTA | PIN21 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(744))
+#define PIN_LPSPI1_PCS0_3 (PIN_PORTA | PIN26 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(744))
+#define PIN_LPSPI1_PCS0_4 (PIN_PORTD | PIN3 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(744))
+#define PIN_LPSPI1_PCS0_5 (PIN_PORTF | PIN21 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(744))
+#define PIN_LPSPI1_PCS1_1 (PIN_PORTA | PIN6 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(745))
+#define PIN_LPSPI1_PCS1_2 (PIN_PORTA | PIN22 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(745))
+#define PIN_LPSPI1_PCS1_3 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(745))
+#define PIN_LPSPI1_PCS1_4 (PIN_PORTC | PIN6 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(745))
+#define PIN_LPSPI1_PCS1_5 (PIN_PORTD | PIN4 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(745))
+#define PIN_LPSPI1_PCS1_6 (PIN_PORTE | PIN4 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT5 | IMCR(745))
+#define PIN_LPSPI1_PCS2_1 (PIN_PORTA | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(746))
+#define PIN_LPSPI1_PCS2_2 (PIN_PORTD | PIN20 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(746))
+#define PIN_LPSPI1_PCS3_1 (PIN_PORTA | PIN14 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(747))
+#define PIN_LPSPI1_PCS3_2 (PIN_PORTB | PIN17 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(747))
+#define PIN_LPSPI1_PCS4 (PIN_PORTA | PIN13 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(748))
+#define PIN_LPSPI1_PCS5 (PIN_PORTA | PIN12 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(749))
+#define PIN_LPSPI1_SCK_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(750))
+#define PIN_LPSPI1_SCK_2 (PIN_PORTA | PIN19 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(750))
+#define PIN_LPSPI1_SCK_3 (PIN_PORTA | PIN28 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(750))
+#define PIN_LPSPI1_SCK_4 (PIN_PORTB | PIN14 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(750))
+#define PIN_LPSPI1_SIN_1 (PIN_PORTA | PIN2 | PIN_INPUT_ALT2 | IMCR(751))
+#define PIN_LPSPI1_SIN_2 (PIN_PORTA | PIN20 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(751))
+#define PIN_LPSPI1_SIN_3 (PIN_PORTA | PIN29 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(751))
+#define PIN_LPSPI1_SIN_4 (PIN_PORTB | PIN15 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(751))
+#define PIN_LPSPI1_SOUT_1 (PIN_PORTA | PIN18 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(752))
+#define PIN_LPSPI1_SOUT_2 (PIN_PORTA | PIN30 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(752))
+#define PIN_LPSPI1_SOUT_3 (PIN_PORTB | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(752))
+#define PIN_LPSPI1_SOUT_4 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(752))
+
+#define PIN_LPSPI2_PCS0_1 (PIN_PORTA | PIN9 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(753))
+#define PIN_LPSPI2_PCS0_2 (PIN_PORTB | PIN25 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(753))
+#define PIN_LPSPI2_PCS0_3 (PIN_PORTC | PIN14 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(753))
+#define PIN_LPSPI2_PCS0_4 (PIN_PORTE | PIN11 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(753))
+#define PIN_LPSPI2_PCS0_5 (PIN_PORTE | PIN13 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT5 | IMCR(753))
+#define PIN_LPSPI2_PCS0_6 (PIN_PORTF | PIN3 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT6 | IMCR(753))
+#define PIN_LPSPI2_PCS1_1 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(754))
+#define PIN_LPSPI2_PCS1_2 (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(754))
+#define PIN_LPSPI2_PCS1_3 (PIN_PORTC | PIN19 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(754))
+#define PIN_LPSPI2_PCS1_4 (PIN_PORTE | PIN10 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(754))
+#define PIN_LPSPI2_PCS2_1 (PIN_PORTA | PIN21 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(755))
+#define PIN_LPSPI2_PCS2_2 (PIN_PORTE | PIN13 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(755))
+#define PIN_LPSPI2_PCS2_3 (PIN_PORTF | PIN25 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(755))
+#define PIN_LPSPI2_PCS3_1 (PIN_PORTA | PIN15 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(756))
+#define PIN_LPSPI2_PCS3_2 (PIN_PORTF | PIN26 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(756))
+#define PIN_LPSPI2_SCK_1 (PIN_PORTB | PIN29 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(757))
+#define PIN_LPSPI2_SCK_2 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(757))
+#define PIN_LPSPI2_SCK_3 (PIN_PORTE | PIN15 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(757))
+#define PIN_LPSPI2_SCK_4 (PIN_PORTF | PIN0 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(757))
+#define PIN_LPSPI2_SIN_1 (PIN_PORTB | PIN2 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(758))
+#define PIN_LPSPI2_SIN_2 (PIN_PORTB | PIN28 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(758))
+#define PIN_LPSPI2_SIN_3 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(758))
+#define PIN_LPSPI2_SIN_4 (PIN_PORTF | PIN1 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(758))
+#define PIN_LPSPI2_SOUT_1 (PIN_PORTA | PIN8 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(759))
+#define PIN_LPSPI2_SOUT_2 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT2 | IMCR(759))
+#define PIN_LPSPI2_SOUT_3 (PIN_PORTB | PIN27 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(759))
+#define PIN_LPSPI2_SOUT_4 (PIN_PORTF | PIN2 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(759))
+
+#define PIN_LPSPI3_PCS0_1 (PIN_PORTA | PIN9 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(760))
+#define PIN_LPSPI3_PCS0_2 (PIN_PORTB | PIN17 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(760))
+#define PIN_LPSPI3_PCS0_3 (PIN_PORTD | PIN17 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(760))
+#define PIN_LPSPI3_PCS0_4 (PIN_PORTF | PIN16 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(760))
+#define PIN_LPSPI3_PCS1_1 (PIN_PORTA | PIN6 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT5 | IMCR(761))
+#define PIN_LPSPI3_PCS1_2 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(761))
+#define PIN_LPSPI3_PCS1_3 (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(761))
+#define PIN_LPSPI3_PCS1_4 (PIN_PORTF | PIN18 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(761))
+#define PIN_LPSPI3_PCS1_5 (PIN_PORTF | PIN29 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(761))
+#define PIN_LPSPI3_PCS2_1 (PIN_PORTB | PIN13 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(762))
+#define PIN_LPSPI3_PCS2_2 (PIN_PORTC | PIN2 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(762))
+#define PIN_LPSPI3_PCS2_3 (PIN_PORTF | PIN19 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(762))
+#define PIN_LPSPI3_PCS3_1 (PIN_PORTB | PIN12 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(763))
+#define PIN_LPSPI3_PCS3_2 (PIN_PORTD | PIN7 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT5 | IMCR(763))
+#define PIN_LPSPI3_PCS3_3 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(763))
+#define PIN_LPSPI3_PCS3_4 (PIN_PORTF | PIN23 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT3 | IMCR(763))
+#define PIN_LPSPI3_SCK_1 (PIN_PORTC | PIN17 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(764))
+#define PIN_LPSPI3_SCK_2 (PIN_PORTD | PIN1 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(764))
+#define PIN_LPSPI3_SCK_3 (PIN_PORTE | PIN7 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(764))
+#define PIN_LPSPI3_SCK_4 (PIN_PORTF | PIN13 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(764))
+#define PIN_LPSPI3_SIN_1 (PIN_PORTC | PIN16 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(765))
+#define PIN_LPSPI3_SIN_2 (PIN_PORTD | PIN20 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(765))
+#define PIN_LPSPI3_SIN_3 (PIN_PORTE | PIN10 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(765))
+#define PIN_LPSPI3_SIN_4 (PIN_PORTF | PIN12 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(765))
+#define PIN_LPSPI3_SOUT_1 (PIN_PORTA | PIN17 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(766))
+#define PIN_LPSPI3_SOUT_2 (PIN_PORTD | PIN0 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(766))
+#define PIN_LPSPI3_SOUT_3 (PIN_PORTD | PIN8 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(766))
+#define PIN_LPSPI3_SOUT_4 (PIN_PORTF | PIN15 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(766))
+
+#define PIN_LPSPI4_PCS0_1 (PIN_PORTB | PIN8 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(767))
+#define PIN_LPSPI4_PCS0_2 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(767))
+#define PIN_LPSPI4_PCS0_3 (PIN_PORTE | PIN23 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT4 | IMCR(767))
+#define PIN_LPSPI4_PCS0_4 (PIN_PORTF | PIN25 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(767))
+#define PIN_LPSPI4_PCS1_1 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(768))
+#define PIN_LPSPI4_PCS1_2 (PIN_PORTC | PIN25 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT4 | IMCR(768))
+#define PIN_LPSPI4_PCS1_3 (PIN_PORTE | PIN24 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(768))
+#define PIN_LPSPI4_PCS1_4 (PIN_PORTF | PIN26 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(768))
+#define PIN_LPSPI4_PCS2_1 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(769))
+#define PIN_LPSPI4_PCS2_2 (PIN_PORTF | PIN22 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(769))
+#define PIN_LPSPI4_PCS2_3 (PIN_PORTF | PIN27 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(769))
+#define PIN_LPSPI4_PCS3_1 (PIN_PORTA | PIN16 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(770))
+#define PIN_LPSPI4_PCS3_2 (PIN_PORTF | PIN28 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(770))
+#define PIN_LPSPI4_PCS3_3 (PIN_PORTG | PIN12 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(770))
+#define PIN_LPSPI4_SCK_1 (PIN_PORTB | PIN10 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(771))
+#define PIN_LPSPI4_SCK_2 (PIN_PORTC | PIN27 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(771))
+#define PIN_LPSPI4_SCK_3 (PIN_PORTE | PIN22 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(771))
+#define PIN_LPSPI4_SIN_1 (PIN_PORTB | PIN11 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(772))
+#define PIN_LPSPI4_SIN_2 (PIN_PORTC | PIN26 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(772))
+#define PIN_LPSPI4_SIN_3 (PIN_PORTE | PIN21 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(772))
+#define PIN_LPSPI4_SOUT_1 (PIN_PORTB | PIN9 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(773))
+#define PIN_LPSPI4_SOUT_2 (PIN_PORTC | PIN11 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(773))
+#define PIN_LPSPI4_SOUT_3 (PIN_PORTE | PIN25 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(773))
+
+#define PIN_LPSPI5_PCS0_1 (PIN_PORTA | PIN15 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(774))
+#define PIN_LPSPI5_PCS0_2 (PIN_PORTD | PIN4 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(774))
+#define PIN_LPSPI5_PCS0_3 (PIN_PORTD | PIN17 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(774))
+#define PIN_LPSPI5_PCS1_1 (PIN_PORTA | PIN14 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(775))
+#define PIN_LPSPI5_PCS1_2 (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT1 | IMCR(775))
+#define PIN_LPSPI5_PCS2 (PIN_PORTD | PIN29 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(776))
+#define PIN_LPSPI5_PCS3 (PIN_PORTD | PIN30 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(777))
+#define PIN_LPSPI5_SCK_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(778))
+#define PIN_LPSPI5_SCK_2 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(778))
+#define PIN_LPSPI5_SCK_3 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(778))
+#define PIN_LPSPI5_SIN_1 (PIN_PORTA | PIN2 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(779))
+#define PIN_LPSPI5_SIN_2 (PIN_PORTD | PIN13 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(779))
+#define PIN_LPSPI5_SIN_3 (PIN_PORTD | PIN28 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(779))
+#define PIN_LPSPI5_SOUT_1 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(780))
+#define PIN_LPSPI5_SOUT_2 (PIN_PORTD | PIN27 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(780))
+#define PIN_LPSPI5_SOUT_3 (PIN_PORTE | PIN9 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(780))
+
+/* LPUART */
+
+#define PIN_LPUART0_CTS_1 (PIN_PORTA | PIN0 | PIN_INPUT_ALT1 | IMCR(872))
+#define PIN_LPUART0_CTS_2 (PIN_PORTC | PIN8 | PIN_INPUT_ALT2 | IMCR(872))
+#define PIN_LPUART0_RTS_1 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT3)
+#define PIN_LPUART0_RTS_2 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT3)
+#define PIN_LPUART0_RX_1 (PIN_PORTA | PIN2 | PIN_INPUT_ALT1 | IMCR(699))
+#define PIN_LPUART0_RX_2 (PIN_PORTA | PIN28 | PIN_INPUT_ALT4 | IMCR(699))
+#define PIN_LPUART0_RX_3 (PIN_PORTB | PIN0 | PIN_INPUT_ALT2 | IMCR(699))
+#define PIN_LPUART0_RX_4 (PIN_PORTC | PIN2 | PIN_INPUT_ALT3 | IMCR(699))
+#define PIN_LPUART0_TX_1 (PIN_PORTA | PIN3 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(875))
+#define PIN_LPUART0_TX_2 (PIN_PORTA | PIN27 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT4 | IMCR(875))
+#define PIN_LPUART0_TX_3 (PIN_PORTB | PIN1 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(875))
+#define PIN_LPUART0_TX_4 (PIN_PORTC | PIN3 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT3 | IMCR(875))
+
+#define PIN_LPUART1_CTS_1 (PIN_PORTA | PIN6 | PIN_INPUT_ALT2 | IMCR(873))
+#define PIN_LPUART1_CTS_2 (PIN_PORTE | PIN2 | PIN_INPUT_ALT1 | IMCR(873))
+#define PIN_LPUART1_CTS_3 (PIN_PORTE | PIN15 | PIN_INPUT_ALT3 | IMCR(873))
+#define PIN_LPUART1_RTS_1 (PIN_PORTA | PIN7 | PIN_OUTPUT_ALT5)
+#define PIN_LPUART1_RTS_2 (PIN_PORTE | PIN6 | PIN_OUTPUT_ALT3)
+#define PIN_LPUART1_RTS_3 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT5)
+#define PIN_LPUART1_RX_1 (PIN_PORTA | PIN19 | PIN_INPUT_ALT5 | IMCR(700))
+#define PIN_LPUART1_RX_2 (PIN_PORTB | PIN23 | PIN_INPUT_ALT4 | IMCR(700))
+#define PIN_LPUART1_RX_3 (PIN_PORTC | PIN6 | PIN_INPUT_ALT1 | IMCR(700))
+#define PIN_LPUART1_RX_4 (PIN_PORTC | PIN8 | PIN_INPUT_ALT2 | IMCR(700))
+#define PIN_LPUART1_RX_5 (PIN_PORTD | PIN13 | PIN_INPUT_ALT3 | IMCR(700))
+#define PIN_LPUART1_TX_1 (PIN_PORTA | PIN18 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(876))
+#define PIN_LPUART1_TX_2 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT5 | IMCR(876))
+#define PIN_LPUART1_TX_3 (PIN_PORTC | PIN7 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(876))
+#define PIN_LPUART1_TX_4 (PIN_PORTC | PIN9 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(876))
+#define PIN_LPUART1_TX_5 (PIN_PORTD | PIN14 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT3 | IMCR(876))
+
+#define PIN_LPUART2_CTS_1 (PIN_PORTD | PIN11 | PIN_INPUT_ALT1 | IMCR(874))
+#define PIN_LPUART2_CTS_2 (PIN_PORTD | PIN15 | PIN_INPUT_ALT2 | IMCR(874))
+#define PIN_LPUART2_CTS_3 (PIN_PORTE | PIN9 | PIN_INPUT_ALT3 | IMCR(874))
+#define PIN_LPUART2_RTS_1 (PIN_PORTD | PIN12 | PIN_OUTPUT_ALT3)
+#define PIN_LPUART2_RTS_2 (PIN_PORTD | PIN16 | PIN_OUTPUT_ALT6)
+#define PIN_LPUART2_RTS_3 (PIN_PORTE | PIN3 | PIN_OUTPUT_ALT5)
+#define PIN_LPUART2_RX_1 (PIN_PORTA | PIN8 | PIN_INPUT_ALT3 | IMCR(701))
+#define PIN_LPUART2_RX_2 (PIN_PORTA | PIN30 | PIN_INPUT_ALT4 | IMCR(701))
+#define PIN_LPUART2_RX_3 (PIN_PORTC | PIN16 | PIN_INPUT_ALT5 | IMCR(701))
+#define PIN_LPUART2_RX_4 (PIN_PORTD | PIN6 | PIN_INPUT_ALT1 | IMCR(701))
+#define PIN_LPUART2_RX_5 (PIN_PORTD | PIN17 | PIN_INPUT_ALT2 | IMCR(701))
+#define PIN_LPUART2_TX_1 (PIN_PORTA | PIN9 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT1 | IMCR(877))
+#define PIN_LPUART2_TX_2 (PIN_PORTA | PIN29 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT5 | IMCR(877))
+#define PIN_LPUART2_TX_3 (PIN_PORTC | PIN15 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(877))
+#define PIN_LPUART2_TX_4 (PIN_PORTD | PIN7 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(877))
+#define PIN_LPUART2_TX_5 (PIN_PORTE | PIN12 | PIN_OUTPUT_ALT3 | PIN_INPUT_ALT4 | IMCR(877))
+
+#define PIN_LPUART3_RX_1 (PIN_PORTA | PIN6 | PIN_INPUT_ALT2 | IMCR(702))
+#define PIN_LPUART3_RX_2 (PIN_PORTD | PIN3 | PIN_INPUT_ALT3 | IMCR(702))
+#define PIN_LPUART3_RX_3 (PIN_PORTE | PIN15 | PIN_INPUT_ALT1 | IMCR(702))
+#define PIN_LPUART3_TX_1 (PIN_PORTA | PIN7 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(878))
+#define PIN_LPUART3_TX_2 (PIN_PORTD | PIN2 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT2 | IMCR(878))
+#define PIN_LPUART3_TX_3 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT3 | IMCR(878))
+
+#define PIN_LPUART4_RX_1 (PIN_PORTB | PIN17 | PIN_INPUT_ALT3 | IMCR(703))
+#define PIN_LPUART4_RX_2 (PIN_PORTE | PIN7 | PIN_INPUT_ALT4 | IMCR(703))
+#define PIN_LPUART4_RX_3 (PIN_PORTE | PIN10 | PIN_INPUT_ALT2 | IMCR(703))
+#define PIN_LPUART4_TX_1 (PIN_PORTA | PIN17 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT1 | IMCR(879))
+#define PIN_LPUART4_TX_2 (PIN_PORTB | PIN16 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(879))
+#define PIN_LPUART4_TX_3 (PIN_PORTE | PIN11 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(879))
+
+#define PIN_LPUART5_RX_1 (PIN_PORTB | PIN28 | PIN_INPUT_ALT4 | IMCR(704))
+#define PIN_LPUART5_RX_2 (PIN_PORTD | PIN0 | PIN_INPUT_ALT2 | IMCR(704))
+#define PIN_LPUART5_RX_3 (PIN_PORTE | PIN3 | PIN_INPUT_ALT1 | IMCR(704))
+#define PIN_LPUART5_RX_4 (PIN_PORTF | PIN1 | PIN_INPUT_ALT3 | IMCR(704))
+#define PIN_LPUART5_TX_1 (PIN_PORTB | PIN27 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(880))
+#define PIN_LPUART5_TX_2 (PIN_PORTD | PIN1 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(880))
+#define PIN_LPUART5_TX_3 (PIN_PORTE | PIN14 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(880))
+#define PIN_LPUART5_TX_4 (PIN_PORTF | PIN0 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT4 | IMCR(880))
+
+#define PIN_LPUART6_RX_1 (PIN_PORTA | PIN15 | PIN_INPUT_ALT2 | IMCR(705))
+#define PIN_LPUART6_RX_2 (PIN_PORTC | PIN18 | PIN_INPUT_ALT4 | IMCR(705))
+#define PIN_LPUART6_RX_3 (PIN_PORTD | PIN8 | PIN_INPUT_ALT1 | IMCR(705))
+#define PIN_LPUART6_RX_4 (PIN_PORTF | PIN3 | PIN_INPUT_ALT3 | IMCR(705))
+#define PIN_LPUART6_TX_1 (PIN_PORTA | PIN16 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT1 | IMCR(881))
+#define PIN_LPUART6_TX_2 (PIN_PORTB | PIN29 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(881))
+#define PIN_LPUART6_TX_3 (PIN_PORTD | PIN9 | PIN_OUTPUT_ALT4 | PIN_INPUT_ALT2 | IMCR(881))
+#define PIN_LPUART6_TX_4 (PIN_PORTF | PIN2 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT4 | IMCR(881))
+
+#define PIN_LPUART7_RX_1 (PIN_PORTB | PIN14 | PIN_INPUT_ALT1 | IMCR(706))
+#define PIN_LPUART7_RX_2 (PIN_PORTC | PIN20 | PIN_INPUT_ALT4 | IMCR(706))
+#define PIN_LPUART7_RX_3 (PIN_PORTE | PIN0 | PIN_INPUT_ALT2 | IMCR(706))
+#define PIN_LPUART7_RX_4 (PIN_PORTF | PIN19 | PIN_INPUT_ALT3 | IMCR(706))
+#define PIN_LPUART7_TX_1 (PIN_PORTB | PIN15 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(882))
+#define PIN_LPUART7_TX_2 (PIN_PORTC | PIN19 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(882))
+#define PIN_LPUART7_TX_3 (PIN_PORTE | PIN1 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT3 | IMCR(882))
+#define PIN_LPUART7_TX_4 (PIN_PORTF | PIN18 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT4 | IMCR(882))
+
+#define PIN_LPUART8_RX_1 (PIN_PORTB | PIN12 | PIN_INPUT_ALT1 | IMCR(707))
+#define PIN_LPUART8_RX_2 (PIN_PORTD | PIN15 | PIN_INPUT_ALT2 | IMCR(707))
+#define PIN_LPUART8_RX_3 (PIN_PORTF | PIN21 | PIN_INPUT_ALT3 | IMCR(707))
+#define PIN_LPUART8_TX_1 (PIN_PORTB | PIN13 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(883))
+#define PIN_LPUART8_TX_2 (PIN_PORTD | PIN16 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT2 | IMCR(883))
+#define PIN_LPUART8_TX_3 (PIN_PORTF | PIN20 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(883))
+
+#define PIN_LPUART9_RX_1 (PIN_PORTB | PIN2 | PIN_INPUT_ALT2 | IMCR(708))
+#define PIN_LPUART9_RX_2 (PIN_PORTB | PIN9 | PIN_INPUT_ALT1 | IMCR(708))
+#define PIN_LPUART9_RX_3 (PIN_PORTF | PIN24 | PIN_INPUT_ALT3 | IMCR(708))
+#define PIN_LPUART9_TX_1 (PIN_PORTB | PIN3 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(884))
+#define PIN_LPUART9_TX_2 (PIN_PORTB | PIN10 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(884))
+#define PIN_LPUART9_TX_3 (PIN_PORTF | PIN23 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(884))
+
+#define PIN_LPUART10_RX_1 (PIN_PORTC | PIN12 | PIN_INPUT_ALT2 | IMCR(709))
+#define PIN_LPUART10_RX_2 (PIN_PORTE | PIN2 | PIN_INPUT_ALT1 | IMCR(709))
+#define PIN_LPUART10_RX_3 (PIN_PORTF | PIN13 | PIN_INPUT_ALT3 | IMCR(709))
+#define PIN_LPUART10_TX_1 (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(885))
+#define PIN_LPUART10_TX_2 (PIN_PORTE | PIN6 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(885))
+#define PIN_LPUART10_TX_3 (PIN_PORTF | PIN12 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(885))
+
+#define PIN_LPUART11_RX_1 (PIN_PORTA | PIN12 | PIN_INPUT_ALT2 | IMCR(710))
+#define PIN_LPUART11_RX_2 (PIN_PORTC | PIN11 | PIN_INPUT_ALT1 | IMCR(710))
+#define PIN_LPUART11_RX_3 (PIN_PORTF | PIN28 | PIN_INPUT_ALT3 | IMCR(710))
+#define PIN_LPUART11_TX_1 (PIN_PORTA | PIN13 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(886))
+#define PIN_LPUART11_TX_2 (PIN_PORTC | PIN10 | PIN_OUTPUT_ALT2 | PIN_INPUT_ALT2 | IMCR(886))
+#define PIN_LPUART11_TX_3 (PIN_PORTF | PIN27 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(886))
+
+#define PIN_LPUART12_RX_1 (PIN_PORTC | PIN25 | PIN_INPUT_ALT2 | IMCR(711))
+#define PIN_LPUART12_RX_2 (PIN_PORTE | PIN5 | PIN_INPUT_ALT1 | IMCR(711))
+#define PIN_LPUART12_RX_3 (PIN_PORTF | PIN17 | PIN_INPUT_ALT3 | IMCR(711))
+#define PIN_LPUART12_TX_1 (PIN_PORTC | PIN24 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(887))
+#define PIN_LPUART12_TX_2 (PIN_PORTE | PIN4 | PIN_OUTPUT_ALT5 | PIN_INPUT_ALT2 | IMCR(887))
+#define PIN_LPUART12_TX_3 (PIN_PORTF | PIN16 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(887))
+
+#define PIN_LPUART13_RX_1 (PIN_PORTB | PIN19 | PIN_INPUT_ALT1 | IMCR(712))
+#define PIN_LPUART13_RX_2 (PIN_PORTC | PIN27 | PIN_INPUT_ALT2 | IMCR(712))
+#define PIN_LPUART13_RX_3 (PIN_PORTG | PIN1 | PIN_INPUT_ALT3 | IMCR(712))
+#define PIN_LPUART13_TX_1 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(888))
+#define PIN_LPUART13_TX_2 (PIN_PORTC | PIN26 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(888))
+#define PIN_LPUART13_TX_3 (PIN_PORTG | PIN0 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(888))
+
+#define PIN_LPUART14_RX_1 (PIN_PORTB | PIN21 | PIN_INPUT_ALT1 | IMCR(713))
+#define PIN_LPUART14_RX_2 (PIN_PORTD | PIN27 | PIN_INPUT_ALT2 | IMCR(713))
+#define PIN_LPUART14_RX_3 (PIN_PORTG | PIN3 | PIN_INPUT_ALT3 | IMCR(713))
+#define PIN_LPUART14_TX_1 (PIN_PORTB | PIN20 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(889))
+#define PIN_LPUART14_TX_2 (PIN_PORTD | PIN26 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(889))
+#define PIN_LPUART14_TX_3 (PIN_PORTG | PIN2 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(889))
+
+#define PIN_LPUART15_RX_1 (PIN_PORTB | PIN26 | PIN_INPUT_ALT1 | IMCR(714))
+#define PIN_LPUART15_RX_2 (PIN_PORTD | PIN29 | PIN_INPUT_ALT2 | IMCR(714))
+#define PIN_LPUART15_RX_3 (PIN_PORTG | PIN5 | PIN_INPUT_ALT3 | IMCR(714))
+#define PIN_LPUART15_TX_1 (PIN_PORTB | PIN25 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT1 | IMCR(890))
+#define PIN_LPUART15_TX_2 (PIN_PORTD | PIN28 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT2 | IMCR(890))
+#define PIN_LPUART15_TX_3 (PIN_PORTG | PIN4 | PIN_OUTPUT_ALT1 | PIN_INPUT_ALT3 | IMCR(890))
+
+/* GPIO */
+
+#define PIN_PTA0 (PIN_PORTA | PIN0)
+#define PIN_PTA1 (PIN_PORTA | PIN1)
+#define PIN_PTA2 (PIN_PORTA | PIN2)
+#define PIN_PTA3 (PIN_PORTA | PIN3)
+#define PIN_PTA4 (PIN_PORTA | PIN4)
+#define PIN_PTA5 (PIN_PORTA | PIN5)
+#define PIN_PTA6 (PIN_PORTA | PIN6)
+#define PIN_PTA7 (PIN_PORTA | PIN7)
+#define PIN_PTA8 (PIN_PORTA | PIN8)
+#define PIN_PTA9 (PIN_PORTA | PIN9)
+#define PIN_PTA10 (PIN_PORTA | PIN10)
+#define PIN_PTA11 (PIN_PORTA | PIN11)
+#define PIN_PTA12 (PIN_PORTA | PIN12)
+#define PIN_PTA13 (PIN_PORTA | PIN13)
+#define PIN_PTA14 (PIN_PORTA | PIN14)
+#define PIN_PTA15 (PIN_PORTA | PIN15)
+#define PIN_PTA16 (PIN_PORTA | PIN16)
+#define PIN_PTA17 (PIN_PORTA | PIN17)
+#define PIN_PTA18 (PIN_PORTA | PIN18)
+#define PIN_PTA19 (PIN_PORTA | PIN19)
+#define PIN_PTA20 (PIN_PORTA | PIN20)
+#define PIN_PTA21 (PIN_PORTA | PIN21)
+#define PIN_PTA22 (PIN_PORTA | PIN22)
+#define PIN_PTA23 (PIN_PORTA | PIN23)
+#define PIN_PTA24 (PIN_PORTA | PIN24)
+#define PIN_PTA25 (PIN_PORTA | PIN25)
+#define PIN_PTA26 (PIN_PORTA | PIN26)
+#define PIN_PTA27 (PIN_PORTA | PIN27)
+#define PIN_PTA28 (PIN_PORTA | PIN28)
+#define PIN_PTA29 (PIN_PORTA | PIN29)
+#define PIN_PTA30 (PIN_PORTA | PIN30)
+#define PIN_PTA31 (PIN_PORTA | PIN31)
+
+#define PIN_PTB0 (PIN_PORTB | PIN0)
+#define PIN_PTB1 (PIN_PORTB | PIN1)
+#define PIN_PTB2 (PIN_PORTB | PIN2)
+#define PIN_PTB3 (PIN_PORTB | PIN3)
+#define PIN_PTB4 (PIN_PORTB | PIN4)
+#define PIN_PTB5 (PIN_PORTB | PIN5)
+#define PIN_PTB8 (PIN_PORTB | PIN8)
+#define PIN_PTB9 (PIN_PORTB | PIN9)
+#define PIN_PTB10 (PIN_PORTB | PIN10)
+#define PIN_PTB11 (PIN_PORTB | PIN11)
+#define PIN_PTB12 (PIN_PORTB | PIN12)
+#define PIN_PTB13 (PIN_PORTB | PIN13)
+#define PIN_PTB14 (PIN_PORTB | PIN14)
+#define PIN_PTB15 (PIN_PORTB | PIN15)
+#define PIN_PTB16 (PIN_PORTB | PIN16)
+#define PIN_PTB17 (PIN_PORTB | PIN17)
+#define PIN_PTB18 (PIN_PORTB | PIN18)
+#define PIN_PTB19 (PIN_PORTB | PIN19)
+#define PIN_PTB20 (PIN_PORTB | PIN20)
+#define PIN_PTB21 (PIN_PORTB | PIN21)
+#define PIN_PTB22 (PIN_PORTB | PIN22)
+#define PIN_PTB23 (PIN_PORTB | PIN23)
+#define PIN_PTB24 (PIN_PORTB | PIN24)
+#define PIN_PTB25 (PIN_PORTB | PIN25)
+#define PIN_PTB26 (PIN_PORTB | PIN26)
+#define PIN_PTB27 (PIN_PORTB | PIN27)
+#define PIN_PTB28 (PIN_PORTB | PIN28)
+#define PIN_PTB29 (PIN_PORTB | PIN29)
+#define PIN_PTB30 (PIN_PORTB | PIN30)
+#define PIN_PTB31 (PIN_PORTB | PIN31)
+
+#define PIN_PTC0 (PIN_PORTC | PIN0)
+#define PIN_PTC1 (PIN_PORTC | PIN1)
+#define PIN_PTC2 (PIN_PORTC | PIN2)
+#define PIN_PTC3 (PIN_PORTC | PIN3)
+#define PIN_PTC4 (PIN_PORTC | PIN4)
+#define PIN_PTC5 (PIN_PORTC | PIN5)
+#define PIN_PTC6 (PIN_PORTC | PIN6)
+#define PIN_PTC7 (PIN_PORTC | PIN7)
+#define PIN_PTC8 (PIN_PORTC | PIN8)
+#define PIN_PTC9 (PIN_PORTC | PIN9)
+#define PIN_PTC10 (PIN_PORTC | PIN10)
+#define PIN_PTC11 (PIN_PORTC | PIN11)
+#define PIN_PTC12 (PIN_PORTC | PIN12)
+#define PIN_PTC13 (PIN_PORTC | PIN13)
+#define PIN_PTC14 (PIN_PORTC | PIN14)
+#define PIN_PTC15 (PIN_PORTC | PIN15)
+#define PIN_PTC16 (PIN_PORTC | PIN16)
+#define PIN_PTC17 (PIN_PORTC | PIN17)
+#define PIN_PTC18 (PIN_PORTC | PIN18)
+#define PIN_PTC19 (PIN_PORTC | PIN19)
+#define PIN_PTC20 (PIN_PORTC | PIN20)
+#define PIN_PTC21 (PIN_PORTC | PIN21)
+#define PIN_PTC22 (PIN_PORTC | PIN22)
+#define PIN_PTC23 (PIN_PORTC | PIN23)
+#define PIN_PTC24 (PIN_PORTC | PIN24)
+#define PIN_PTC25 (PIN_PORTC | PIN25)
+#define PIN_PTC26 (PIN_PORTC | PIN26)
+#define PIN_PTC27 (PIN_PORTC | PIN27)
+#define PIN_PTC28 (PIN_PORTC | PIN28)
+#define PIN_PTC29 (PIN_PORTC | PIN29)
+#define PIN_PTC30 (PIN_PORTC | PIN30)
+#define PIN_PTC31 (PIN_PORTC | PIN31)
+
+#define PIN_PTD0 (PIN_PORTD | PIN0)
+#define PIN_PTD1 (PIN_PORTD | PIN1)
+#define PIN_PTD2 (PIN_PORTD | PIN2)
+#define PIN_PTD3 (PIN_PORTD | PIN3)
+#define PIN_PTD4 (PIN_PORTD | PIN4)
+#define PIN_PTD5 (PIN_PORTD | PIN5)
+#define PIN_PTD6 (PIN_PORTD | PIN6)
+#define PIN_PTD7 (PIN_PORTD | PIN7)
+#define PIN_PTD8 (PIN_PORTD | PIN8)
+#define PIN_PTD9 (PIN_PORTD | PIN9)
+#define PIN_PTD10 (PIN_PORTD | PIN10)
+#define PIN_PTD11 (PIN_PORTD | PIN11)
+#define PIN_PTD12 (PIN_PORTD | PIN12)
+#define PIN_PTD13 (PIN_PORTD | PIN13)
+#define PIN_PTD14 (PIN_PORTD | PIN14)
+#define PIN_PTD15 (PIN_PORTD | PIN15)
+#define PIN_PTD16 (PIN_PORTD | PIN16)
+#define PIN_PTD17 (PIN_PORTD | PIN17)
+#define PIN_PTD18 (PIN_PORTD | PIN18)
+#define PIN_PTD19 (PIN_PORTD | PIN19)
+#define PIN_PTD20 (PIN_PORTD | PIN20)
+#define PIN_PTD21 (PIN_PORTD | PIN21)
+#define PIN_PTD22 (PIN_PORTD | PIN22)
+#define PIN_PTD23 (PIN_PORTD | PIN23)
+#define PIN_PTD24 (PIN_PORTD | PIN24)
+#define PIN_PTD25 (PIN_PORTD | PIN25)
+#define PIN_PTD26 (PIN_PORTD | PIN26)
+#define PIN_PTD27 (PIN_PORTD | PIN27)
+#define PIN_PTD28 (PIN_PORTD | PIN28)
+#define PIN_PTD29 (PIN_PORTD | PIN29)
+#define PIN_PTD30 (PIN_PORTD | PIN30)
+#define PIN_PTD31 (PIN_PORTD | PIN31)
+
+#define PIN_PTE0 (PIN_PORTE | PIN0)
+#define PIN_PTE1 (PIN_PORTE | PIN1)
+#define PIN_PTE2 (PIN_PORTE | PIN2)
+#define PIN_PTE3 (PIN_PORTE | PIN3)
+#define PIN_PTE4 (PIN_PORTE | PIN4)
+#define PIN_PTE5 (PIN_PORTE | PIN5)
+#define PIN_PTE6 (PIN_PORTE | PIN6)
+#define PIN_PTE7 (PIN_PORTE | PIN7)
+#define PIN_PTE8 (PIN_PORTE | PIN8)
+#define PIN_PTE9 (PIN_PORTE | PIN9)
+#define PIN_PTE10 (PIN_PORTE | PIN10)
+#define PIN_PTE11 (PIN_PORTE | PIN11)
+#define PIN_PTE12 (PIN_PORTE | PIN12)
+#define PIN_PTE13 (PIN_PORTE | PIN13)
+#define PIN_PTE14 (PIN_PORTE | PIN14)
+#define PIN_PTE15 (PIN_PORTE | PIN15)
+#define PIN_PTE16 (PIN_PORTE | PIN16)
+#define PIN_PTE17 (PIN_PORTE | PIN17)
+#define PIN_PTE18 (PIN_PORTE | PIN18)
+#define PIN_PTE19 (PIN_PORTE | PIN19)
+#define PIN_PTE20 (PIN_PORTE | PIN20)
+#define PIN_PTE21 (PIN_PORTE | PIN21)
+#define PIN_PTE22 (PIN_PORTE | PIN22)
+#define PIN_PTE23 (PIN_PORTE | PIN23)
+#define PIN_PTE24 (PIN_PORTE | PIN24)
+#define PIN_PTE25 (PIN_PORTE | PIN25)
+#define PIN_PTE26 (PIN_PORTE | PIN26)
+#define PIN_PTE27 (PIN_PORTE | PIN27)
+#define PIN_PTE28 (PIN_PORTE | PIN28)
+#define PIN_PTE29 (PIN_PORTE | PIN29)
+#define PIN_PTE30 (PIN_PORTE | PIN30)
+#define PIN_PTE31 (PIN_PORTE | PIN31)
+
+#define PIN_PTF0 (PIN_PORTF | PIN0)
+#define PIN_PTF1 (PIN_PORTF | PIN1)
+#define PIN_PTF2 (PIN_PORTF | PIN2)
+#define PIN_PTF3 (PIN_PORTF | PIN3)
+#define PIN_PTF4 (PIN_PORTF | PIN4)
+#define PIN_PTF5 (PIN_PORTF | PIN5)
+#define PIN_PTF6 (PIN_PORTF | PIN6)
+#define PIN_PTF7 (PIN_PORTF | PIN7)
+#define PIN_PTF8 (PIN_PORTF | PIN8)
+#define PIN_PTF9 (PIN_PORTF | PIN9)
+#define PIN_PTF10 (PIN_PORTF | PIN10)
+#define PIN_PTF11 (PIN_PORTF | PIN11)
+#define PIN_PTF12 (PIN_PORTF | PIN12)
+#define PIN_PTF13 (PIN_PORTF | PIN13)
+#define PIN_PTF14 (PIN_PORTF | PIN14)
+#define PIN_PTF15 (PIN_PORTF | PIN15)
+#define PIN_PTF16 (PIN_PORTF | PIN16)
+#define PIN_PTF17 (PIN_PORTF | PIN17)
+#define PIN_PTF18 (PIN_PORTF | PIN18)
+#define PIN_PTF19 (PIN_PORTF | PIN19)
+#define PIN_PTF20 (PIN_PORTF | PIN20)
+#define PIN_PTF21 (PIN_PORTF | PIN21)
+#define PIN_PTF22 (PIN_PORTF | PIN22)
+#define PIN_PTF23 (PIN_PORTF | PIN23)
+#define PIN_PTF24 (PIN_PORTF | PIN24)
+#define PIN_PTF25 (PIN_PORTF | PIN25)
+#define PIN_PTF26 (PIN_PORTF | PIN26)
+#define PIN_PTF27 (PIN_PORTF | PIN27)
+#define PIN_PTF28 (PIN_PORTF | PIN28)
+#define PIN_PTF29 (PIN_PORTF | PIN29)
+#define PIN_PTF30 (PIN_PORTF | PIN30)
+#define PIN_PTF31 (PIN_PORTF | PIN31)
+
+#define PIN_PTG0 (PIN_PORTG | PIN0)
+#define PIN_PTG1 (PIN_PORTG | PIN1)
+#define PIN_PTG2 (PIN_PORTG | PIN2)
+#define PIN_PTG3 (PIN_PORTG | PIN3)
+#define PIN_PTG4 (PIN_PORTG | PIN4)
+#define PIN_PTG5 (PIN_PORTG | PIN5)
+#define PIN_PTG6 (PIN_PORTG | PIN6)
+#define PIN_PTG7 (PIN_PORTG | PIN7)
+#define PIN_PTG8 (PIN_PORTG | PIN8)
+#define PIN_PTG9 (PIN_PORTG | PIN9)
+#define PIN_PTG10 (PIN_PORTG | PIN10)
+#define PIN_PTG11 (PIN_PORTG | PIN11)
+#define PIN_PTG12 (PIN_PORTG | PIN12)
+#define PIN_PTG13 (PIN_PORTG | PIN13)
+#define PIN_PTG14 (PIN_PORTG | PIN14)
+#define PIN_PTG15 (PIN_PORTG | PIN15)
+#define PIN_PTG16 (PIN_PORTG | PIN16)
+#define PIN_PTG17 (PIN_PORTG | PIN17)
+#define PIN_PTG18 (PIN_PORTG | PIN18)
+#define PIN_PTG19 (PIN_PORTG | PIN19)
+#define PIN_PTG20 (PIN_PORTG | PIN20)
+#define PIN_PTG21 (PIN_PORTG | PIN21)
+#define PIN_PTG22 (PIN_PORTG | PIN22)
+#define PIN_PTG23 (PIN_PORTG | PIN23)
+#define PIN_PTG24 (PIN_PORTG | PIN24)
+#define PIN_PTG25 (PIN_PORTG | PIN25)
+#define PIN_PTG26 (PIN_PORTG | PIN26)
+#define PIN_PTG27 (PIN_PORTG | PIN27)
+
+/* QuadSPI */
+
+#define PIN_QSPI_IOFA0 (PIN_PORTD | PIN11 | PIN_OUTPUT_MODE_ALT7 | PIN_INPUT_ALT1 | IMCR(817))
+#define PIN_QSPI_IOFA1 (PIN_PORTD | PIN7 | PIN_OUTPUT_MODE_ALT7 | PIN_INPUT_ALT1 | IMCR(818))
+#define PIN_QSPI_IOFA2 (PIN_PORTD | PIN12 | PIN_OUTPUT_MODE_ALT7 | PIN_INPUT_ALT1 | IMCR(819))
+#define PIN_QSPI_IOFA3 (PIN_PORTC | PIN2 | PIN_OUTPUT_MODE_ALT7 | PIN_INPUT_ALT1 | IMCR(820))
+#define PIN_QSPI_PCSFA (PIN_PORTC | PIN3 | PIN_OUTPUT_MODE_ALT6)
+#define PIN_QSPI_SCKFA (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(821))
+
+/* Reset */
+
+#define PIN_RESET (PIN_PORTA | PIN5 | PIN_OUTPUT_ALT7)
+
+/* Synchronous Audio Interface (SAI) */
+
+#define PIN_SAI0_BCLK (PIN_PORTC | PIN12 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(827))
+#define PIN_SAI0_D0 (PIN_PORTB | PIN2 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(828))
+#define PIN_SAI0_D1 (PIN_PORTB | PIN29 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(829))
+#define PIN_SAI0_D2 (PIN_PORTC | PIN18 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(830))
+#define PIN_SAI0_D3 (PIN_PORTC | PIN19 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(831))
+#define PIN_SAI0_MCLK (PIN_PORTB | PIN3 | PIN_INPUT_ALT1 | IMCR(832))
+#define PIN_SAI0_SYNC (PIN_PORTC | PIN13 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT1 | IMCR(833))
+
+#define PIN_SAI1_BCLK (PIN_PORTE | PIN8 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(834))
+#define PIN_SAI1_D0 (PIN_PORTD | PIN13 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(835))
+#define PIN_SAI1_MCLK (PIN_PORTD | PIN14 | PIN_INPUT_ALT1 | IMCR(836))
+#define PIN_SAI1_SYNC (PIN_PORTD | PIN15 | PIN_OUTPUT_ALT6 | PIN_INPUT_ALT1 | IMCR(837))
+
+/* SWD Debug */
+
+#define PIN_SWD_CLK (PIN_PORTC | PIN4 | PIN_INPUT_ALT0 | IMCR(696))
+#define PIN_SWD_DIO (PIN_PORTA | PIN4 | PIN_OUTPUT_ALT7 | PIN_INPUT_ALT0 | IMCR(698))
+#define PIN_TRACE_SWO (PIN_PORTA | PIN10 | PIN_OUTPUT_ALT7)
+
+/* ETM Trace Debug */
+
+#define PIN_TRACE_ETM_CLKOUT_0 (PIN_PORTC | PIN2 | PIN_OUTPUT_ALT6)
+#define PIN_TRACE_ETM_CLKOUT_1 (PIN_PORTG | PIN6 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D0_0 (PIN_PORTD | PIN7 | PIN_OUTPUT_ALT6)
+#define PIN_TRACE_ETM_D0_1 (PIN_PORTG | PIN7 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D1_0 (PIN_PORTD | PIN12 | PIN_OUTPUT_ALT4)
+#define PIN_TRACE_ETM_D1_1 (PIN_PORTG | PIN15 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D2_0 (PIN_PORTD | PIN11 | PIN_OUTPUT_ALT4)
+#define PIN_TRACE_ETM_D2_1 (PIN_PORTG | PIN16 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D3_0 (PIN_PORTD | PIN10 | PIN_OUTPUT_ALT4)
+#define PIN_TRACE_ETM_D3_1 (PIN_PORTF | PIN31 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D4 (PIN_PORTG | PIN17 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D5 (PIN_PORTF | PIN28 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D6 (PIN_PORTG | PIN18 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D7 (PIN_PORTG | PIN19 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D8 (PIN_PORTG | PIN20 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D9 (PIN_PORTG | PIN21 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D10 (PIN_PORTG | PIN22 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D11 (PIN_PORTG | PIN23 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D12 (PIN_PORTG | PIN24 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D13 (PIN_PORTG | PIN25 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D14 (PIN_PORTG | PIN26 | PIN_OUTPUT_ALT7)
+#define PIN_TRACE_ETM_D15 (PIN_PORTG | PIN27 | PIN_OUTPUT_ALT7)
+
+/* Trigger MUX (TRGMUX) */
+
+#define PIN_TRGMUX_IN0 (PIN_PORTB | PIN5 | PIN_INPUT_ALT1 | IMCR(856))
+#define PIN_TRGMUX_IN1 (PIN_PORTB | PIN4 | PIN_INPUT_ALT1 | IMCR(857))
+#define PIN_TRGMUX_IN2 (PIN_PORTB | PIN3 | PIN_INPUT_ALT1 | IMCR(858))
+#define PIN_TRGMUX_IN3 (PIN_PORTB | PIN2 | PIN_INPUT_ALT1 | IMCR(859))
+#define PIN_TRGMUX_IN4 (PIN_PORTD | PIN3 | PIN_INPUT_ALT1 | IMCR(860))
+#define PIN_TRGMUX_IN5 (PIN_PORTD | PIN2 | PIN_INPUT_ALT1 | IMCR(861))
+#define PIN_TRGMUX_IN6 (PIN_PORTE | PIN3 | PIN_INPUT_ALT1 | IMCR(862))
+#define PIN_TRGMUX_IN7 (PIN_PORTD | PIN5 | PIN_INPUT_ALT1 | IMCR(863))
+#define PIN_TRGMUX_IN8 (PIN_PORTC | PIN15 | PIN_INPUT_ALT1 | IMCR(864))
+#define PIN_TRGMUX_IN9 (PIN_PORTC | PIN14 | PIN_INPUT_ALT1 | IMCR(865))
+#define PIN_TRGMUX_IN10 (PIN_PORTC | PIN11 | PIN_INPUT_ALT1 | IMCR(866))
+#define PIN_TRGMUX_IN11 (PIN_PORTC | PIN10 | PIN_INPUT_ALT1 | IMCR(867))
+#define PIN_TRGMUX_IN12 (PIN_PORTA | PIN18 | PIN_INPUT_ALT1 | IMCR(868))
+#define PIN_TRGMUX_IN13 (PIN_PORTA | PIN19 | PIN_INPUT_ALT1 | IMCR(869))
+#define PIN_TRGMUX_IN14 (PIN_PORTA | PIN20 | PIN_INPUT_ALT1 | IMCR(870))
+#define PIN_TRGMUX_IN15 (PIN_PORTA | PIN21 | PIN_INPUT_ALT1 | IMCR(871))
+#define PIN_TRGMUX_OUT0 (PIN_PORTA | PIN1 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT1 (PIN_PORTD | PIN0 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT2 (PIN_PORTD | PIN1 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT3 (PIN_PORTA | PIN0 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT4 (PIN_PORTE | PIN10 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT5 (PIN_PORTE | PIN11 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT6 (PIN_PORTE | PIN15 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT7 (PIN_PORTE | PIN16 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT8 (PIN_PORTA | PIN31 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT9 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT9 (PIN_PORTB | PIN18 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT10 (PIN_PORTB | PIN19 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT11 (PIN_PORTB | PIN20 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT12 (PIN_PORTB | PIN21 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT13 (PIN_PORTB | PIN22 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT14 (PIN_PORTB | PIN23 | PIN_OUTPUT_ALT7)
+#define PIN_TRGMUX_OUT15 (PIN_PORTC | PIN24 | PIN_OUTPUT_ALT7)
+
+/* Wakeup Unit (WKPU) */
+
+#define PIN_WKPU0 (PIN_PORTA | PIN2 | PIN_INPUT_WKPU | WPKU(0))
+#define PIN_WKPU1 (PIN_PORTD | PIN3 | PIN_INPUT_WKPU | WPKU(1))
+#define PIN_WKPU2 (PIN_PORTC | PIN7 | PIN_INPUT_WKPU | WPKU(2))
+#define PIN_WKPU3 (PIN_PORTC | PIN6 | PIN_INPUT_WKPU | WPKU(3))
+#define PIN_WKPU4 (PIN_PORTA | PIN13 | PIN_INPUT_WKPU | WPKU(4))
+#define PIN_WKPU5 (PIN_PORTA | PIN1 | PIN_INPUT_WKPU | WPKU(5))
+#define PIN_WKPU6 (PIN_PORTD | PIN0 | PIN_INPUT_WKPU | WPKU(6))
+#define PIN_WKPU7 (PIN_PORTB | PIN0 | PIN_INPUT_WKPU | WPKU(7))
+#define PIN_WKPU8 (PIN_PORTB | PIN2 | PIN_INPUT_WKPU | WPKU(8))
+#define PIN_WKPU9 (PIN_PORTD | PIN2 | PIN_INPUT_WKPU | WPKU(9))
+#define PIN_WKPU10 (PIN_PORTC | PIN9 | PIN_INPUT_WKPU | WPKU(10))
+#define PIN_WKPU11 (PIN_PORTB | PIN13 | PIN_INPUT_WKPU | WPKU(11))
+#define PIN_WKPU12 (PIN_PORTB | PIN12 | PIN_INPUT_WKPU | WPKU(12))
+#define PIN_WKPU13 (PIN_PORTB | PIN16 | PIN_INPUT_WKPU | WPKU(13))
+#define PIN_WKPU14 (PIN_PORTB | PIN17 | PIN_INPUT_WKPU | WPKU(14))
+#define PIN_WKPU15 (PIN_PORTA | PIN6 | PIN_INPUT_WKPU | WPKU(15))
+#define PIN_WKPU16 (PIN_PORTB | PIN11 | PIN_INPUT_WKPU | WPKU(16))
+#define PIN_WKPU17 (PIN_PORTB | PIN9 | PIN_INPUT_WKPU | WPKU(17))
+#define PIN_WKPU18 (PIN_PORTC | PIN11 | PIN_INPUT_WKPU | WPKU(18))
+#define PIN_WKPU19 (PIN_PORTE | PIN16 | PIN_INPUT_WKPU | WPKU(19))
+#define PIN_WKPU20 (PIN_PORTA | PIN15 | PIN_INPUT_WKPU | WPKU(20))
+#define PIN_WKPU21 (PIN_PORTA | PIN9 | PIN_INPUT_WKPU | WPKU(21))
+#define PIN_WKPU22 (PIN_PORTD | PIN4 | PIN_INPUT_WKPU | WPKU(22))
+#define PIN_WKPU23 (PIN_PORTA | PIN8 | PIN_INPUT_WKPU | WPKU(23))
+#define PIN_WKPU24 (PIN_PORTD | PIN13 | PIN_INPUT_WKPU | WPKU(24))
+#define PIN_WKPU25 (PIN_PORTB | PIN8 | PIN_INPUT_WKPU | WPKU(25))
+#define PIN_WKPU26 (PIN_PORTE | PIN0 | PIN_INPUT_WKPU | WPKU(26))
+#define PIN_WKPU27 (PIN_PORTE | PIN2 | PIN_INPUT_WKPU | WPKU(27))
+#define PIN_WKPU28 (PIN_PORTE | PIN11 | PIN_INPUT_WKPU | WPKU(28))
+#define PIN_WKPU29 (PIN_PORTE | PIN6 | PIN_INPUT_WKPU | WPKU(29))
+#define PIN_WKPU30 (PIN_PORTE | PIN14 | PIN_INPUT_WKPU | WPKU(30))
+#define PIN_WKPU31 (PIN_PORTA | PIN16 | PIN_INPUT_WKPU | WPKU(31))
+#define PIN_WKPU32 (PIN_PORTE | PIN5 | PIN_INPUT_WKPU | WPKU(32))
+#define PIN_WKPU33 (PIN_PORTB | PIN15 | PIN_INPUT_WKPU | WPKU(33))
+#define PIN_WKPU34 (PIN_PORTA | PIN25 | PIN_INPUT_WKPU | WPKU(34))
+#define PIN_WKPU35 (PIN_PORTA | PIN26 | PIN_INPUT_WKPU | WPKU(35))
+#define PIN_WKPU36 (PIN_PORTC | PIN18 | PIN_INPUT_WKPU | WPKU(36))
+#define PIN_WKPU37 (PIN_PORTA | PIN30 | PIN_INPUT_WKPU | WPKU(37))
+#define PIN_WKPU38 (PIN_PORTB | PIN19 | PIN_INPUT_WKPU | WPKU(38))
+#define PIN_WKPU39 (PIN_PORTB | PIN21 | PIN_INPUT_WKPU | WPKU(39))
+#define PIN_WKPU40 (PIN_PORTB | PIN23 | PIN_INPUT_WKPU | WPKU(40))
+#define PIN_WKPU41 (PIN_PORTB | PIN26 | PIN_INPUT_WKPU | WPKU(41))
+#define PIN_WKPU42 (PIN_PORTB | PIN28 | PIN_INPUT_WKPU | WPKU(42))
+#define PIN_WKPU43 (PIN_PORTC | PIN20 | PIN_INPUT_WKPU | WPKU(43))
+#define PIN_WKPU44 (PIN_PORTC | PIN23 | PIN_INPUT_WKPU | WPKU(44))
+#define PIN_WKPU45 (PIN_PORTC | PIN25 | PIN_INPUT_WKPU | WPKU(45))
+#define PIN_WKPU46 (PIN_PORTC | PIN24 | PIN_INPUT_WKPU | WPKU(46))
+#define PIN_WKPU47 (PIN_PORTC | PIN29 | PIN_INPUT_WKPU | WPKU(47))
+#define PIN_WKPU48 (PIN_PORTC | PIN26 | PIN_INPUT_WKPU | WPKU(48))
+#define PIN_WKPU49 (PIN_PORTC | PIN31 | PIN_INPUT_WKPU | WPKU(49))
+#define PIN_WKPU50 (PIN_PORTD | PIN23 | PIN_INPUT_WKPU | WPKU(50))
+#define PIN_WKPU51 (PIN_PORTD | PIN27 | PIN_INPUT_WKPU | WPKU(51))
+#define PIN_WKPU52 (PIN_PORTD | PIN29 | PIN_INPUT_WKPU | WPKU(52))
+#define PIN_WKPU53 (PIN_PORTD | PIN31 | PIN_INPUT_WKPU | WPKU(53))
+#define PIN_WKPU54 (PIN_PORTD | PIN20 | PIN_INPUT_WKPU | WPKU(54))
+#define PIN_WKPU55 (PIN_PORTE | PIN18 | PIN_INPUT_WKPU | WPKU(55))
+#define PIN_WKPU56 (PIN_PORTE | PIN21 | PIN_INPUT_WKPU | WPKU(56))
+#define PIN_WKPU57 (PIN_PORTE | PIN23 | PIN_INPUT_WKPU | WPKU(57))
+#define PIN_WKPU58 (PIN_PORTE | PIN25 | PIN_INPUT_WKPU | WPKU(58))
+#define PIN_WKPU59 (PIN_PORTA | PIN20 | PIN_INPUT_WKPU | WPKU(59))
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K344_PINMUX_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h
new file mode 100644
index 0000000000..7d9eeec933
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h
@@ -0,0 +1,1407 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_adc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_ADC_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_ADC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* ADC Register Offsets *****************************************************/
+
+#define S32K3XX_ADC_MCR_OFFSET (0x0000) /* Main Configuration Register (MCR) */
+#define S32K3XX_ADC_MSR_OFFSET (0x0004) /* Main Status Register (MSR) */
+#define S32K3XX_ADC_ISR_OFFSET (0x0010) /* Interrupt Status Register (ISR) */
+#define S32K3XX_ADC_CEOCFR0_OFFSET (0x0014) /* Channel End Of Conversation Flag Register for Precision Inputs (CEOCFR0) */
+#define S32K3XX_ADC_CEOCFR1_OFFSET (0x0018) /* Channel End Of Conversation Flag Register for Standard Inputs (CEOCFR1) */
+#define S32K3XX_ADC_CEOCFR2_OFFSET (0x001c) /* Channel End Of Conversation Flag Register for External Inputs (CEOCFR2) */
+#define S32K3XX_ADC_IMR_OFFSET (0x0020) /* Interrupt Mask Register (IMR) */
+#define S32K3XX_ADC_CIMR0_OFFSET (0x0024) /* EOC Interrupt Enable Register for Precision Inputs (CIMR0) */
+#define S32K3XX_ADC_CIMR1_OFFSET (0x0028) /* EOC Interrupt Enable Register for Standard Inputs (CIMR1) */
+#define S32K3XX_ADC_CIMR2_OFFSET (0x002c) /* EOC Interrupt Enable Register for External Inputs (CIMR2) */
+#define S32K3XX_ADC_WTISR_OFFSET (0x0030) /* Analog Watchdog Threshold Interrupt Status Register (WTISR) */
+#define S32K3XX_ADC_WTIMR_OFFSET (0x0034) /* Analog Watchdog Threshold Interrupt Enable Register (WTIMR) */
+#define S32K3XX_ADC_DMAE_OFFSET (0x0040) /* Direct Memory Access Configuration Register (DMAE) */
+#define S32K3XX_ADC_DMAR0_OFFSET (0x0044) /* DMA Request Enable Register for Precision Inputs (DMAR0) */
+#define S32K3XX_ADC_DMAR1_OFFSET (0x0048) /* DMA Request Enable Register for Standard Inputs (DMAR1) */
+#define S32K3XX_ADC_DMAR2_OFFSET (0x004c) /* DMA Request Enable Register for External Inputs (DMAR2) */
+#define S32K3XX_ADC_THRHLR0_OFFSET (0x0060) /* Analog Watchdog Threshold Values Register 0 (THRHLR0) */
+#define S32K3XX_ADC_THRHLR1_OFFSET (0x0064) /* Analog Watchdog Threshold Values Register 1 (THRHLR1) */
+#define S32K3XX_ADC_THRHLR2_OFFSET (0x0068) /* Analog Watchdog Threshold Values Register 2 (THRHLR2) */
+#define S32K3XX_ADC_THRHLR3_OFFSET (0x006c) /* Analog Watchdog Threshold Values Register 3 (THRHLR3) */
+#define S32K3XX_ADC_PSCR_OFFSET (0x0080) /* Presampling Control Register (PSCR) */
+#define S32K3XX_ADC_PSR0_OFFSET (0x0084) /* Presampling Enable Register for Precision Inputs (PSR0) */
+#define S32K3XX_ADC_PSR1_OFFSET (0x0088) /* Presampling Enable Register for Standard Inputs (PSR1) */
+#define S32K3XX_ADC_PSR2_OFFSET (0x008c) /* Presampling Enable Register for External Inputs (PSR2) */
+#define S32K3XX_ADC_CTR0_OFFSET (0x0094) /* Conversion Timing Register for Precision Inputs (CTR0) */
+#define S32K3XX_ADC_CTR1_OFFSET (0x0098) /* Conversion Timing Register for Standard Inputs (CTR1) */
+#define S32K3XX_ADC_CTR2_OFFSET (0x009c) /* Conversion Timing Register for External Inputs (CTR2) */
+#define S32K3XX_ADC_NCMR0_OFFSET (0x00a4) /* Normal Conversion Enable Register for Precision Inputs (NCMR0) */
+#define S32K3XX_ADC_NCMR1_OFFSET (0x00a8) /* Normal Conversion Enable Register for Standard Inputs (NCMR1) */
+#define S32K3XX_ADC_NCMR2_OFFSET (0x00ac) /* Normal Conversion Enable Register for External Inputs (NCMR2) */
+#define S32K3XX_ADC_JCMR0_OFFSET (0x00b4) /* Injected Conversion Enable Register for Precision Inputs (JCMR0) */
+#define S32K3XX_ADC_JCMR1_OFFSET (0x00b8) /* Injected Conversion Enable Register for Standard Inputs (JCMR1) */
+#define S32K3XX_ADC_JCMR2_OFFSET (0x00bc) /* Injected Conversion Enable Register for External Inputs (JCMR2) */
+#define S32K3XX_ADC_DSDR_OFFSET (0x00c4) /* Delay Start of Data Conversion Register (DSDR) */
+#define S32K3XX_ADC_PDEDR_OFFSET (0x00c8) /* Power Down Exit Delay Register (PDEDR) */
+
+#define S32K3XX_ADC_PCDR_OFFSET(n) (0x0100 + ((n) << 2))
+#define S32K3XX_ADC_PCDR0_OFFSET (0x0100) /* Precision Input 0 Conversion Data Register (PCDR0) */
+#define S32K3XX_ADC_PCDR1_OFFSET (0x0104) /* Precision Input 1 Conversion Data Register (PCDR1) */
+#define S32K3XX_ADC_PCDR2_OFFSET (0x0108) /* Precision Input 2 Conversion Data Register (PCDR2) */
+#define S32K3XX_ADC_PCDR3_OFFSET (0x010c) /* Precision Input 3 Conversion Data Register (PCDR3) */
+#define S32K3XX_ADC_PCDR4_OFFSET (0x0110) /* Precision Input 4 Conversion Data Register (PCDR4) */
+#define S32K3XX_ADC_PCDR5_OFFSET (0x0114) /* Precision Input 5 Conversion Data Register (PCDR5) */
+#define S32K3XX_ADC_PCDR6_OFFSET (0x0118) /* Precision Input 6 Conversion Data Register (PCDR6) */
+#define S32K3XX_ADC_PCDR7_OFFSET (0x011c) /* Precision Input 7 Conversion Data Register (PCDR7) */
+
+#define S32K3XX_ADC_ICDR_OFFSET(n) (0x0180 + ((n) << 2))
+#define S32K3XX_ADC_ICDR0_OFFSET (0x0180) /* Standard Input 0 Conversion Data Register (ICDR0) */
+#define S32K3XX_ADC_ICDR1_OFFSET (0x0184) /* Standard Input 1 Conversion Data Register (ICDR1) */
+#define S32K3XX_ADC_ICDR2_OFFSET (0x0188) /* Standard Input 2 Conversion Data Register (ICDR2) */
+#define S32K3XX_ADC_ICDR3_OFFSET (0x018c) /* Standard Input 3 Conversion Data Register (ICDR3) */
+#define S32K3XX_ADC_ICDR4_OFFSET (0x0190) /* Standard Input 4 Conversion Data Register (ICDR4) */
+#define S32K3XX_ADC_ICDR5_OFFSET (0x0194) /* Standard Input 5 Conversion Data Register (ICDR5) */
+#define S32K3XX_ADC_ICDR6_OFFSET (0x0198) /* Standard Input 6 Conversion Data Register (ICDR6) */
+#define S32K3XX_ADC_ICDR7_OFFSET (0x019c) /* Standard Input 7 Conversion Data Register (ICDR7) */
+#define S32K3XX_ADC_ICDR8_OFFSET (0x01a0) /* Standard Input 8 Conversion Data Register (ICDR8) */
+#define S32K3XX_ADC_ICDR9_OFFSET (0x01a4) /* Standard Input 9 Conversion Data Register (ICDR9) */
+#define S32K3XX_ADC_ICDR10_OFFSET (0x01a8) /* Standard Input 10 Conversion Data Register (ICDR10) */
+#define S32K3XX_ADC_ICDR11_OFFSET (0x01ac) /* Standard Input 11 Conversion Data Register (ICDR11) */
+#define S32K3XX_ADC_ICDR12_OFFSET (0x01b0) /* Standard Input 12 Conversion Data Register (ICDR12) */
+#define S32K3XX_ADC_ICDR13_OFFSET (0x01b4) /* Standard Input 13 Conversion Data Register (ICDR13) */
+#define S32K3XX_ADC_ICDR14_OFFSET (0x01b8) /* Standard Input 14 Conversion Data Register (ICDR14) */
+#define S32K3XX_ADC_ICDR15_OFFSET (0x01bc) /* Standard Input 15 Conversion Data Register (ICDR15) */
+#define S32K3XX_ADC_ICDR16_OFFSET (0x01c0) /* Standard Input 16 Conversion Data Register (ICDR16) */
+#define S32K3XX_ADC_ICDR17_OFFSET (0x01c4) /* Standard Input 17 Conversion Data Register (ICDR17) */
+#define S32K3XX_ADC_ICDR18_OFFSET (0x01c8) /* Standard Input 18 Conversion Data Register (ICDR18) */
+#define S32K3XX_ADC_ICDR19_OFFSET (0x01cc) /* Standard Input 19 Conversion Data Register (ICDR19) */
+#define S32K3XX_ADC_ICDR20_OFFSET (0x01d0) /* Standard Input 20 Conversion Data Register (ICDR20) */
+#define S32K3XX_ADC_ICDR21_OFFSET (0x01d4) /* Standard Input 21 Conversion Data Register (ICDR21) */
+#define S32K3XX_ADC_ICDR22_OFFSET (0x01d8) /* Standard Input 22 Conversion Data Register (ICDR22) */
+#define S32K3XX_ADC_ICDR23_OFFSET (0x01dc) /* Standard Input 23 Conversion Data Register (ICDR23) */
+
+#define S32K3XX_ADC_ECDR_OFFSET(n) (0x0200 + ((n) << 2))
+#define S32K3XX_ADC_ECDR0_OFFSET (0x0200) /* External Input 0 Conversion Data Register (ECDR0) */
+#define S32K3XX_ADC_ECDR1_OFFSET (0x0204) /* External Input 1 Conversion Data Register (ECDR1) */
+#define S32K3XX_ADC_ECDR2_OFFSET (0x0208) /* External Input 2 Conversion Data Register (ECDR2) */
+#define S32K3XX_ADC_ECDR3_OFFSET (0x020c) /* External Input 3 Conversion Data Register (ECDR3) */
+#define S32K3XX_ADC_ECDR4_OFFSET (0x0210) /* External Input 4 Conversion Data Register (ECDR4) */
+#define S32K3XX_ADC_ECDR5_OFFSET (0x0214) /* External Input 5 Conversion Data Register (ECDR5) */
+#define S32K3XX_ADC_ECDR6_OFFSET (0x0218) /* External Input 6 Conversion Data Register (ECDR6) */
+#define S32K3XX_ADC_ECDR7_OFFSET (0x021c) /* External Input 7 Conversion Data Register (ECDR7) */
+#define S32K3XX_ADC_ECDR8_OFFSET (0x0220) /* External Input 8 Conversion Data Register (ECDR8) */
+#define S32K3XX_ADC_ECDR9_OFFSET (0x0224) /* External Input 9 Conversion Data Register (ECDR9) */
+#define S32K3XX_ADC_ECDR10_OFFSET (0x0228) /* External Input 10 Conversion Data Register (ECDR10) */
+#define S32K3XX_ADC_ECDR11_OFFSET (0x022c) /* External Input 11 Conversion Data Register (ECDR11) */
+#define S32K3XX_ADC_ECDR12_OFFSET (0x0230) /* External Input 12 Conversion Data Register (ECDR12) */
+#define S32K3XX_ADC_ECDR13_OFFSET (0x0234) /* External Input 13 Conversion Data Register (ECDR13) */
+#define S32K3XX_ADC_ECDR14_OFFSET (0x0238) /* External Input 14 Conversion Data Register (ECDR14) */
+#define S32K3XX_ADC_ECDR15_OFFSET (0x023c) /* External Input 15 Conversion Data Register (ECDR15) */
+#define S32K3XX_ADC_ECDR16_OFFSET (0x0240) /* External Input 16 Conversion Data Register (ECDR16) */
+#define S32K3XX_ADC_ECDR17_OFFSET (0x0244) /* External Input 17 Conversion Data Register (ECDR17) */
+#define S32K3XX_ADC_ECDR18_OFFSET (0x0248) /* External Input 18 Conversion Data Register (ECDR18) */
+#define S32K3XX_ADC_ECDR19_OFFSET (0x024c) /* External Input 19 Conversion Data Register (ECDR19) */
+#define S32K3XX_ADC_ECDR20_OFFSET (0x0250) /* External Input 20 Conversion Data Register (ECDR20) */
+#define S32K3XX_ADC_ECDR21_OFFSET (0x0254) /* External Input 21 Conversion Data Register (ECDR21) */
+#define S32K3XX_ADC_ECDR22_OFFSET (0x0258) /* External Input 22 Conversion Data Register (ECDR22) */
+#define S32K3XX_ADC_ECDR23_OFFSET (0x025c) /* External Input 23 Conversion Data Register (ECDR23) */
+#define S32K3XX_ADC_ECDR24_OFFSET (0x0260) /* External Input 24 Conversion Data Register (ECDR24) */
+#define S32K3XX_ADC_ECDR25_OFFSET (0x0264) /* External Input 25 Conversion Data Register (ECDR25) */
+#define S32K3XX_ADC_ECDR26_OFFSET (0x0268) /* External Input 26 Conversion Data Register (ECDR26) */
+#define S32K3XX_ADC_ECDR27_OFFSET (0x026c) /* External Input 27 Conversion Data Register (ECDR27) */
+#define S32K3XX_ADC_ECDR28_OFFSET (0x0270) /* External Input 28 Conversion Data Register (ECDR28) */
+#define S32K3XX_ADC_ECDR29_OFFSET (0x0274) /* External Input 29 Conversion Data Register (ECDR29) */
+#define S32K3XX_ADC_ECDR30_OFFSET (0x0278) /* External Input 30 Conversion Data Register (ECDR30) */
+#define S32K3XX_ADC_ECDR31_OFFSET (0x027c) /* External Input 31 Conversion Data Register (ECDR31) */
+
+#define S32K3XX_ADC_CWSELRPI0_OFFSET (0x02b0) /* Channel Analog Watchdog Select Register for Precision Inputs 0 (CWSELRPI0) */
+#define S32K3XX_ADC_CWSELRPI1_OFFSET (0x02b4) /* Channel Analog Watchdog Select Register for Precision Inputs 1 (CWSELRPI1) */
+#define S32K3XX_ADC_CWSELRSI0_OFFSET (0x02c0) /* Channel Analog Watchdog Select Register for Standard Inputs 0 (CWSELRSI0) */
+#define S32K3XX_ADC_CWSELRSI1_OFFSET (0x02c4) /* Channel Analog Watchdog Select Register for Standard Inputs 1 (CWSELRSI1) */
+#define S32K3XX_ADC_CWSELRSI2_OFFSET (0x02c8) /* Channel Analog Watchdog Select Register for Standard Inputs 2 (CWSELRSI2) */
+#define S32K3XX_ADC_CWSELREI0_OFFSET (0x02d0) /* Channel Analog Watchdog Select Register for External Inputs 0 (CWSELREI0) */
+#define S32K3XX_ADC_CWSELREI1_OFFSET (0x02d4) /* Channel Analog Watchdog Select Register for External Inputs 1 (CWSELREI1) */
+#define S32K3XX_ADC_CWSELREI2_OFFSET (0x02d8) /* Channel Analog Watchdog Select Register for External Inputs 2 (CWSELREI2) */
+#define S32K3XX_ADC_CWSELREI3_OFFSET (0x02dc) /* Channel Analog Watchdog Select Register for External Inputs 3 (CWSELREI3) */
+#define S32K3XX_ADC_CWENR0_OFFSET (0x02e0) /* Channel Watchdog Enable Register for Precision Inputs (CWENR0) */
+#define S32K3XX_ADC_CWENR1_OFFSET (0x02e4) /* Channel Watchdog Enable Register for Standard Inputs (CWENR1) */
+#define S32K3XX_ADC_CWENR2_OFFSET (0x02e8) /* Channel Watchdog Enable Register for External Inputs (CWENR2) */
+#define S32K3XX_ADC_AWORR0_OFFSET (0x02f0) /* Analog Watchdog Out of Range Register for Precision Inputs (AWORR0) */
+#define S32K3XX_ADC_AWORR1_OFFSET (0x02f4) /* Analog Watchdog Out of Range Register for Standard Inputs (AWORR1) */
+#define S32K3XX_ADC_AWORR2_OFFSET (0x02f8) /* Analog Watchdog Out of Range Register for External Inputs (AWORR2) */
+#define S32K3XX_ADC_STCR1_OFFSET (0x0340) /* Self-Test Configuration Register 1 (STCR1) */
+#define S32K3XX_ADC_STCR2_OFFSET (0x0344) /* Self-Test Configuration Register 2 (STCR2) */
+#define S32K3XX_ADC_STCR3_OFFSET (0x0348) /* Self-Test Configuration Register 3 (STCR3) */
+#define S32K3XX_ADC_STBRR_OFFSET (0x034c) /* Self-Test Baud Rate Register (STBRR) */
+#define S32K3XX_ADC_STSR1_OFFSET (0x0350) /* Self-Test Status Register 1 (STSR1) */
+#define S32K3XX_ADC_STSR2_OFFSET (0x0354) /* Self-Test Status Register 2 (STSR2) */
+#define S32K3XX_ADC_STSR3_OFFSET (0x0358) /* Self-Test Status Register 3 (STSR3) */
+#define S32K3XX_ADC_STSR4_OFFSET (0x035c) /* Self-Test Status Register 4 (STSR4) */
+#define S32K3XX_ADC_STDR1_OFFSET (0x0370) /* Self-Test Conversion Data Register 1 (STDR1) */
+#define S32K3XX_ADC_STAW0R_OFFSET (0x0380) /* Self-Test Analog Watchdog S0 Register (STAW0R) */
+#define S32K3XX_ADC_STAW1R_OFFSET (0x0388) /* Self-Test Analog Watchdog S1 Register (STAW1R) */
+#define S32K3XX_ADC_STAW2R_OFFSET (0x038c) /* Self-Test Analog Watchdog S2 Register (STAW2R) */
+#define S32K3XX_ADC_STAW4R_OFFSET (0x0394) /* Self-Test Analog Watchdog C0 Register (STAW4R) */
+#define S32K3XX_ADC_STAW5R_OFFSET (0x0398) /* Self-Test Analog Watchdog C Register (STAW5R) */
+#define S32K3XX_ADC_AMSIO_OFFSET (0x039c) /* Analog Miscellaneous In/Out Register (AMSIO) */
+#define S32K3XX_ADC_CALBISTREG_OFFSET (0x03a0) /* Control and Calibration Status Register (CALBISTREG) */
+#define S32K3XX_ADC_OFSGNUSR_OFFSET (0x03a8) /* Offset and Gain User Register (OFSGNUSR) */
+#define S32K3XX_ADC_CAL2_OFFSET (0x03b4) /* Calibration Value 2 (CAL2) */
+
+/* ADC Register Addresses ***************************************************/
+
+/* ADC0 */
+
+#define S32K3XX_ADC0_MCR (S32K3XX_ADC0_BASE + S32K3XX_ADC_MCR_OFFSET)
+#define S32K3XX_ADC0_MSR (S32K3XX_ADC0_BASE + S32K3XX_ADC_MSR_OFFSET)
+#define S32K3XX_ADC0_ISR (S32K3XX_ADC0_BASE + S32K3XX_ADC_ISR_OFFSET)
+#define S32K3XX_ADC0_CEOCFR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CEOCFR0_OFFSET)
+#define S32K3XX_ADC0_CEOCFR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CEOCFR1_OFFSET)
+#define S32K3XX_ADC0_CEOCFR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CEOCFR2_OFFSET)
+#define S32K3XX_ADC0_IMR (S32K3XX_ADC0_BASE + S32K3XX_ADC_IMR_OFFSET)
+#define S32K3XX_ADC0_CIMR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CIMR0_OFFSET)
+#define S32K3XX_ADC0_CIMR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CIMR1_OFFSET)
+#define S32K3XX_ADC0_CIMR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CIMR2_OFFSET)
+#define S32K3XX_ADC0_WTISR (S32K3XX_ADC0_BASE + S32K3XX_ADC_WTISR_OFFSET)
+#define S32K3XX_ADC0_WTIMR (S32K3XX_ADC0_BASE + S32K3XX_ADC_WTIMR_OFFSET)
+#define S32K3XX_ADC0_DMAE (S32K3XX_ADC0_BASE + S32K3XX_ADC_DMAE_OFFSET)
+#define S32K3XX_ADC0_DMAR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_DMAR0_OFFSET)
+#define S32K3XX_ADC0_DMAR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_DMAR1_OFFSET)
+#define S32K3XX_ADC0_DMAR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_DMAR2_OFFSET)
+#define S32K3XX_ADC0_THRHLR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_THRHLR0_OFFSET)
+#define S32K3XX_ADC0_THRHLR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_THRHLR1_OFFSET)
+#define S32K3XX_ADC0_THRHLR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_THRHLR2_OFFSET)
+#define S32K3XX_ADC0_THRHLR3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_THRHLR3_OFFSET)
+#define S32K3XX_ADC0_PSCR (S32K3XX_ADC0_BASE + S32K3XX_ADC_PSCR_OFFSET)
+#define S32K3XX_ADC0_PSR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PSR0_OFFSET)
+#define S32K3XX_ADC0_PSR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PSR1_OFFSET)
+#define S32K3XX_ADC0_PSR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PSR2_OFFSET)
+#define S32K3XX_ADC0_CTR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CTR0_OFFSET)
+#define S32K3XX_ADC0_CTR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CTR1_OFFSET)
+#define S32K3XX_ADC0_CTR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CTR2_OFFSET)
+#define S32K3XX_ADC0_NCMR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_NCMR0_OFFSET)
+#define S32K3XX_ADC0_NCMR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_NCMR1_OFFSET)
+#define S32K3XX_ADC0_NCMR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_NCMR2_OFFSET)
+#define S32K3XX_ADC0_JCMR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_JCMR0_OFFSET)
+#define S32K3XX_ADC0_JCMR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_JCMR1_OFFSET)
+#define S32K3XX_ADC0_JCMR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_JCMR2_OFFSET)
+#define S32K3XX_ADC0_DSDR (S32K3XX_ADC0_BASE + S32K3XX_ADC_DSDR_OFFSET)
+#define S32K3XX_ADC0_PDEDR (S32K3XX_ADC0_BASE + S32K3XX_ADC_PDEDR_OFFSET)
+
+#define S32K3XX_ADC0_PCDR(n) (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR_OFFSET(n))
+#define S32K3XX_ADC0_PCDR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR0_OFFSET)
+#define S32K3XX_ADC0_PCDR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR1_OFFSET)
+#define S32K3XX_ADC0_PCDR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR2_OFFSET)
+#define S32K3XX_ADC0_PCDR3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR3_OFFSET)
+#define S32K3XX_ADC0_PCDR4 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR4_OFFSET)
+#define S32K3XX_ADC0_PCDR5 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR5_OFFSET)
+#define S32K3XX_ADC0_PCDR6 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR6_OFFSET)
+#define S32K3XX_ADC0_PCDR7 (S32K3XX_ADC0_BASE + S32K3XX_ADC_PCDR7_OFFSET)
+
+#define S32K3XX_ADC0_ICDR(n) (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR_OFFSET(n))
+#define S32K3XX_ADC0_ICDR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR0_OFFSET)
+#define S32K3XX_ADC0_ICDR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR1_OFFSET)
+#define S32K3XX_ADC0_ICDR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR2_OFFSET)
+#define S32K3XX_ADC0_ICDR3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR3_OFFSET)
+#define S32K3XX_ADC0_ICDR4 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR4_OFFSET)
+#define S32K3XX_ADC0_ICDR5 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR5_OFFSET)
+#define S32K3XX_ADC0_ICDR6 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR6_OFFSET)
+#define S32K3XX_ADC0_ICDR7 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR7_OFFSET)
+#define S32K3XX_ADC0_ICDR8 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR8_OFFSET)
+#define S32K3XX_ADC0_ICDR9 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR9_OFFSET)
+#define S32K3XX_ADC0_ICDR10 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR10_OFFSET)
+#define S32K3XX_ADC0_ICDR11 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR11_OFFSET)
+#define S32K3XX_ADC0_ICDR12 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR12_OFFSET)
+#define S32K3XX_ADC0_ICDR13 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR13_OFFSET)
+#define S32K3XX_ADC0_ICDR14 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR14_OFFSET)
+#define S32K3XX_ADC0_ICDR15 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR15_OFFSET)
+#define S32K3XX_ADC0_ICDR16 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR16_OFFSET)
+#define S32K3XX_ADC0_ICDR17 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR17_OFFSET)
+#define S32K3XX_ADC0_ICDR18 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR18_OFFSET)
+#define S32K3XX_ADC0_ICDR19 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR19_OFFSET)
+#define S32K3XX_ADC0_ICDR20 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR20_OFFSET)
+#define S32K3XX_ADC0_ICDR21 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR21_OFFSET)
+#define S32K3XX_ADC0_ICDR22 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR22_OFFSET)
+#define S32K3XX_ADC0_ICDR23 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ICDR23_OFFSET)
+
+#define S32K3XX_ADC0_ECDR(n) (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR_OFFSET(n))
+#define S32K3XX_ADC0_ECDR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR0_OFFSET)
+#define S32K3XX_ADC0_ECDR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR1_OFFSET)
+#define S32K3XX_ADC0_ECDR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR2_OFFSET)
+#define S32K3XX_ADC0_ECDR3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR3_OFFSET)
+#define S32K3XX_ADC0_ECDR4 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR4_OFFSET)
+#define S32K3XX_ADC0_ECDR5 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR5_OFFSET)
+#define S32K3XX_ADC0_ECDR6 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR6_OFFSET)
+#define S32K3XX_ADC0_ECDR7 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR7_OFFSET)
+#define S32K3XX_ADC0_ECDR8 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR8_OFFSET)
+#define S32K3XX_ADC0_ECDR9 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR9_OFFSET)
+#define S32K3XX_ADC0_ECDR10 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR10_OFFSET)
+#define S32K3XX_ADC0_ECDR11 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR11_OFFSET)
+#define S32K3XX_ADC0_ECDR12 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR12_OFFSET)
+#define S32K3XX_ADC0_ECDR13 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR13_OFFSET)
+#define S32K3XX_ADC0_ECDR14 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR14_OFFSET)
+#define S32K3XX_ADC0_ECDR15 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR15_OFFSET)
+#define S32K3XX_ADC0_ECDR16 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR16_OFFSET)
+#define S32K3XX_ADC0_ECDR17 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR17_OFFSET)
+#define S32K3XX_ADC0_ECDR18 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR18_OFFSET)
+#define S32K3XX_ADC0_ECDR19 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR19_OFFSET)
+#define S32K3XX_ADC0_ECDR20 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR20_OFFSET)
+#define S32K3XX_ADC0_ECDR21 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR21_OFFSET)
+#define S32K3XX_ADC0_ECDR22 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR22_OFFSET)
+#define S32K3XX_ADC0_ECDR23 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR23_OFFSET)
+#define S32K3XX_ADC0_ECDR24 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR24_OFFSET)
+#define S32K3XX_ADC0_ECDR25 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR25_OFFSET)
+#define S32K3XX_ADC0_ECDR26 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR26_OFFSET)
+#define S32K3XX_ADC0_ECDR27 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR27_OFFSET)
+#define S32K3XX_ADC0_ECDR28 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR28_OFFSET)
+#define S32K3XX_ADC0_ECDR29 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR29_OFFSET)
+#define S32K3XX_ADC0_ECDR30 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR30_OFFSET)
+#define S32K3XX_ADC0_ECDR31 (S32K3XX_ADC0_BASE + S32K3XX_ADC_ECDR31_OFFSET)
+
+#define S32K3XX_ADC0_CWSELRPI0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELRPI0_OFFSET)
+#define S32K3XX_ADC0_CWSELRPI1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELRPI1_OFFSET)
+#define S32K3XX_ADC0_CWSELRSI0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELRSI0_OFFSET)
+#define S32K3XX_ADC0_CWSELRSI1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELRSI1_OFFSET)
+#define S32K3XX_ADC0_CWSELRSI2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELRSI2_OFFSET)
+#define S32K3XX_ADC0_CWSELREI0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELREI0_OFFSET)
+#define S32K3XX_ADC0_CWSELREI1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELREI1_OFFSET)
+#define S32K3XX_ADC0_CWSELREI2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELREI2_OFFSET)
+#define S32K3XX_ADC0_CWSELREI3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWSELREI3_OFFSET)
+#define S32K3XX_ADC0_CWENR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWENR0_OFFSET)
+#define S32K3XX_ADC0_CWENR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWENR1_OFFSET)
+#define S32K3XX_ADC0_CWENR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CWENR2_OFFSET)
+#define S32K3XX_ADC0_AWORR0 (S32K3XX_ADC0_BASE + S32K3XX_ADC_AWORR0_OFFSET)
+#define S32K3XX_ADC0_AWORR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_AWORR1_OFFSET)
+#define S32K3XX_ADC0_AWORR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_AWORR2_OFFSET)
+#define S32K3XX_ADC0_STCR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STCR1_OFFSET)
+#define S32K3XX_ADC0_STCR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STCR2_OFFSET)
+#define S32K3XX_ADC0_STCR3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STCR3_OFFSET)
+#define S32K3XX_ADC0_STBRR (S32K3XX_ADC0_BASE + S32K3XX_ADC_STBRR_OFFSET)
+#define S32K3XX_ADC0_STSR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STSR1_OFFSET)
+#define S32K3XX_ADC0_STSR2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STSR2_OFFSET)
+#define S32K3XX_ADC0_STSR3 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STSR3_OFFSET)
+#define S32K3XX_ADC0_STSR4 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STSR4_OFFSET)
+#define S32K3XX_ADC0_STDR1 (S32K3XX_ADC0_BASE + S32K3XX_ADC_STDR1_OFFSET)
+#define S32K3XX_ADC0_STAW0R (S32K3XX_ADC0_BASE + S32K3XX_ADC_STAW0R_OFFSET)
+#define S32K3XX_ADC0_STAW1R (S32K3XX_ADC0_BASE + S32K3XX_ADC_STAW1R_OFFSET)
+#define S32K3XX_ADC0_STAW2R (S32K3XX_ADC0_BASE + S32K3XX_ADC_STAW2R_OFFSET)
+#define S32K3XX_ADC0_STAW4R (S32K3XX_ADC0_BASE + S32K3XX_ADC_STAW4R_OFFSET)
+#define S32K3XX_ADC0_STAW5R (S32K3XX_ADC0_BASE + S32K3XX_ADC_STAW5R_OFFSET)
+#define S32K3XX_ADC0_AMSIO (S32K3XX_ADC0_BASE + S32K3XX_ADC_AMSIO_OFFSET )
+#define S32K3XX_ADC0_CALBISTREG (S32K3XX_ADC0_BASE + S32K3XX_ADC_CALBISTREG_OFFSET)
+#define S32K3XX_ADC0_OFSGNUSR (S32K3XX_ADC0_BASE + S32K3XX_ADC_OFSGNUSR_OFFSET)
+#define S32K3XX_ADC0_CAL2 (S32K3XX_ADC0_BASE + S32K3XX_ADC_CAL2_OFFSET)
+
+/* ADC1 */
+
+#define S32K3XX_ADC1_MCR (S32K3XX_ADC1_BASE + S32K3XX_ADC_MCR_OFFSET)
+#define S32K3XX_ADC1_MSR (S32K3XX_ADC1_BASE + S32K3XX_ADC_MSR_OFFSET)
+#define S32K3XX_ADC1_ISR (S32K3XX_ADC1_BASE + S32K3XX_ADC_ISR_OFFSET)
+#define S32K3XX_ADC1_CEOCFR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CEOCFR0_OFFSET)
+#define S32K3XX_ADC1_CEOCFR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CEOCFR1_OFFSET)
+#define S32K3XX_ADC1_CEOCFR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CEOCFR2_OFFSET)
+#define S32K3XX_ADC1_IMR (S32K3XX_ADC1_BASE + S32K3XX_ADC_IMR_OFFSET)
+#define S32K3XX_ADC1_CIMR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CIMR0_OFFSET)
+#define S32K3XX_ADC1_CIMR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CIMR1_OFFSET)
+#define S32K3XX_ADC1_CIMR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CIMR2_OFFSET)
+#define S32K3XX_ADC1_WTISR (S32K3XX_ADC1_BASE + S32K3XX_ADC_WTISR_OFFSET)
+#define S32K3XX_ADC1_WTIMR (S32K3XX_ADC1_BASE + S32K3XX_ADC_WTIMR_OFFSET)
+#define S32K3XX_ADC1_DMAE (S32K3XX_ADC1_BASE + S32K3XX_ADC_DMAE_OFFSET)
+#define S32K3XX_ADC1_DMAR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_DMAR0_OFFSET)
+#define S32K3XX_ADC1_DMAR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_DMAR1_OFFSET)
+#define S32K3XX_ADC1_DMAR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_DMAR2_OFFSET)
+#define S32K3XX_ADC1_THRHLR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_THRHLR0_OFFSET)
+#define S32K3XX_ADC1_THRHLR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_THRHLR1_OFFSET)
+#define S32K3XX_ADC1_THRHLR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_THRHLR2_OFFSET)
+#define S32K3XX_ADC1_THRHLR3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_THRHLR3_OFFSET)
+#define S32K3XX_ADC1_PSCR (S32K3XX_ADC1_BASE + S32K3XX_ADC_PSCR_OFFSET)
+#define S32K3XX_ADC1_PSR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PSR0_OFFSET)
+#define S32K3XX_ADC1_PSR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PSR1_OFFSET)
+#define S32K3XX_ADC1_PSR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PSR2_OFFSET)
+#define S32K3XX_ADC1_CTR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CTR0_OFFSET)
+#define S32K3XX_ADC1_CTR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CTR1_OFFSET)
+#define S32K3XX_ADC1_CTR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CTR2_OFFSET)
+#define S32K3XX_ADC1_NCMR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_NCMR0_OFFSET)
+#define S32K3XX_ADC1_NCMR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_NCMR1_OFFSET)
+#define S32K3XX_ADC1_NCMR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_NCMR2_OFFSET)
+#define S32K3XX_ADC1_JCMR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_JCMR0_OFFSET)
+#define S32K3XX_ADC1_JCMR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_JCMR1_OFFSET)
+#define S32K3XX_ADC1_JCMR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_JCMR2_OFFSET)
+#define S32K3XX_ADC1_DSDR (S32K3XX_ADC1_BASE + S32K3XX_ADC_DSDR_OFFSET)
+#define S32K3XX_ADC1_PDEDR (S32K3XX_ADC1_BASE + S32K3XX_ADC_PDEDR_OFFSET)
+
+#define S32K3XX_ADC1_PCDR(n) (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR_OFFSET(n))
+#define S32K3XX_ADC1_PCDR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR0_OFFSET)
+#define S32K3XX_ADC1_PCDR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR1_OFFSET)
+#define S32K3XX_ADC1_PCDR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR2_OFFSET)
+#define S32K3XX_ADC1_PCDR3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR3_OFFSET)
+#define S32K3XX_ADC1_PCDR4 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR4_OFFSET)
+#define S32K3XX_ADC1_PCDR5 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR5_OFFSET)
+#define S32K3XX_ADC1_PCDR6 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR6_OFFSET)
+#define S32K3XX_ADC1_PCDR7 (S32K3XX_ADC1_BASE + S32K3XX_ADC_PCDR7_OFFSET)
+
+#define S32K3XX_ADC1_ICDR(n) (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR_OFFSET(n))
+#define S32K3XX_ADC1_ICDR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR0_OFFSET)
+#define S32K3XX_ADC1_ICDR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR1_OFFSET)
+#define S32K3XX_ADC1_ICDR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR2_OFFSET)
+#define S32K3XX_ADC1_ICDR3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR3_OFFSET)
+#define S32K3XX_ADC1_ICDR4 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR4_OFFSET)
+#define S32K3XX_ADC1_ICDR5 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR5_OFFSET)
+#define S32K3XX_ADC1_ICDR6 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR6_OFFSET)
+#define S32K3XX_ADC1_ICDR7 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR7_OFFSET)
+#define S32K3XX_ADC1_ICDR8 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR8_OFFSET)
+#define S32K3XX_ADC1_ICDR9 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR9_OFFSET)
+#define S32K3XX_ADC1_ICDR10 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR10_OFFSET)
+#define S32K3XX_ADC1_ICDR11 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR11_OFFSET)
+#define S32K3XX_ADC1_ICDR12 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR12_OFFSET)
+#define S32K3XX_ADC1_ICDR13 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR13_OFFSET)
+#define S32K3XX_ADC1_ICDR14 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR14_OFFSET)
+#define S32K3XX_ADC1_ICDR15 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR15_OFFSET)
+#define S32K3XX_ADC1_ICDR16 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR16_OFFSET)
+#define S32K3XX_ADC1_ICDR17 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR17_OFFSET)
+#define S32K3XX_ADC1_ICDR18 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR18_OFFSET)
+#define S32K3XX_ADC1_ICDR19 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR19_OFFSET)
+#define S32K3XX_ADC1_ICDR20 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR20_OFFSET)
+#define S32K3XX_ADC1_ICDR21 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR21_OFFSET)
+#define S32K3XX_ADC1_ICDR22 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR22_OFFSET)
+#define S32K3XX_ADC1_ICDR23 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ICDR23_OFFSET)
+
+#define S32K3XX_ADC1_ECDR(n) (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR_OFFSET(n))
+#define S32K3XX_ADC1_ECDR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR0_OFFSET)
+#define S32K3XX_ADC1_ECDR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR1_OFFSET)
+#define S32K3XX_ADC1_ECDR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR2_OFFSET)
+#define S32K3XX_ADC1_ECDR3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR3_OFFSET)
+#define S32K3XX_ADC1_ECDR4 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR4_OFFSET)
+#define S32K3XX_ADC1_ECDR5 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR5_OFFSET)
+#define S32K3XX_ADC1_ECDR6 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR6_OFFSET)
+#define S32K3XX_ADC1_ECDR7 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR7_OFFSET)
+#define S32K3XX_ADC1_ECDR8 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR8_OFFSET)
+#define S32K3XX_ADC1_ECDR9 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR9_OFFSET)
+#define S32K3XX_ADC1_ECDR10 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR10_OFFSET)
+#define S32K3XX_ADC1_ECDR11 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR11_OFFSET)
+#define S32K3XX_ADC1_ECDR12 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR12_OFFSET)
+#define S32K3XX_ADC1_ECDR13 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR13_OFFSET)
+#define S32K3XX_ADC1_ECDR14 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR14_OFFSET)
+#define S32K3XX_ADC1_ECDR15 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR15_OFFSET)
+#define S32K3XX_ADC1_ECDR16 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR16_OFFSET)
+#define S32K3XX_ADC1_ECDR17 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR17_OFFSET)
+#define S32K3XX_ADC1_ECDR18 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR18_OFFSET)
+#define S32K3XX_ADC1_ECDR19 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR19_OFFSET)
+#define S32K3XX_ADC1_ECDR20 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR20_OFFSET)
+#define S32K3XX_ADC1_ECDR21 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR21_OFFSET)
+#define S32K3XX_ADC1_ECDR22 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR22_OFFSET)
+#define S32K3XX_ADC1_ECDR23 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR23_OFFSET)
+#define S32K3XX_ADC1_ECDR24 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR24_OFFSET)
+#define S32K3XX_ADC1_ECDR25 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR25_OFFSET)
+#define S32K3XX_ADC1_ECDR26 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR26_OFFSET)
+#define S32K3XX_ADC1_ECDR27 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR27_OFFSET)
+#define S32K3XX_ADC1_ECDR28 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR28_OFFSET)
+#define S32K3XX_ADC1_ECDR29 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR29_OFFSET)
+#define S32K3XX_ADC1_ECDR30 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR30_OFFSET)
+#define S32K3XX_ADC1_ECDR31 (S32K3XX_ADC1_BASE + S32K3XX_ADC_ECDR31_OFFSET)
+
+#define S32K3XX_ADC1_CWSELRPI0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELRPI0_OFFSET)
+#define S32K3XX_ADC1_CWSELRPI1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELRPI1_OFFSET)
+#define S32K3XX_ADC1_CWSELRSI0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELRSI0_OFFSET)
+#define S32K3XX_ADC1_CWSELRSI1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELRSI1_OFFSET)
+#define S32K3XX_ADC1_CWSELRSI2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELRSI2_OFFSET)
+#define S32K3XX_ADC1_CWSELREI0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELREI0_OFFSET)
+#define S32K3XX_ADC1_CWSELREI1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELREI1_OFFSET)
+#define S32K3XX_ADC1_CWSELREI2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELREI2_OFFSET)
+#define S32K3XX_ADC1_CWSELREI3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWSELREI3_OFFSET)
+#define S32K3XX_ADC1_CWENR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWENR0_OFFSET)
+#define S32K3XX_ADC1_CWENR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWENR1_OFFSET)
+#define S32K3XX_ADC1_CWENR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CWENR2_OFFSET)
+#define S32K3XX_ADC1_AWORR0 (S32K3XX_ADC1_BASE + S32K3XX_ADC_AWORR0_OFFSET)
+#define S32K3XX_ADC1_AWORR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_AWORR1_OFFSET)
+#define S32K3XX_ADC1_AWORR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_AWORR2_OFFSET)
+#define S32K3XX_ADC1_STCR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STCR1_OFFSET)
+#define S32K3XX_ADC1_STCR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STCR2_OFFSET)
+#define S32K3XX_ADC1_STCR3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STCR3_OFFSET)
+#define S32K3XX_ADC1_STBRR (S32K3XX_ADC1_BASE + S32K3XX_ADC_STBRR_OFFSET)
+#define S32K3XX_ADC1_STSR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STSR1_OFFSET)
+#define S32K3XX_ADC1_STSR2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STSR2_OFFSET)
+#define S32K3XX_ADC1_STSR3 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STSR3_OFFSET)
+#define S32K3XX_ADC1_STSR4 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STSR4_OFFSET)
+#define S32K3XX_ADC1_STDR1 (S32K3XX_ADC1_BASE + S32K3XX_ADC_STDR1_OFFSET)
+#define S32K3XX_ADC1_STAW0R (S32K3XX_ADC1_BASE + S32K3XX_ADC_STAW0R_OFFSET)
+#define S32K3XX_ADC1_STAW1R (S32K3XX_ADC1_BASE + S32K3XX_ADC_STAW1R_OFFSET)
+#define S32K3XX_ADC1_STAW2R (S32K3XX_ADC1_BASE + S32K3XX_ADC_STAW2R_OFFSET)
+#define S32K3XX_ADC1_STAW4R (S32K3XX_ADC1_BASE + S32K3XX_ADC_STAW4R_OFFSET)
+#define S32K3XX_ADC1_STAW5R (S32K3XX_ADC1_BASE + S32K3XX_ADC_STAW5R_OFFSET)
+#define S32K3XX_ADC1_AMSIO (S32K3XX_ADC1_BASE + S32K3XX_ADC_AMSIO_OFFSET )
+#define S32K3XX_ADC1_CALBISTREG (S32K3XX_ADC1_BASE + S32K3XX_ADC_CALBISTREG_OFFSET)
+#define S32K3XX_ADC1_OFSGNUSR (S32K3XX_ADC1_BASE + S32K3XX_ADC_OFSGNUSR_OFFSET)
+#define S32K3XX_ADC1_CAL2 (S32K3XX_ADC1_BASE + S32K3XX_ADC_CAL2_OFFSET)
+
+/* ADC2 */
+
+#define S32K3XX_ADC2_MCR (S32K3XX_ADC2_BASE + S32K3XX_ADC_MCR_OFFSET)
+#define S32K3XX_ADC2_MSR (S32K3XX_ADC2_BASE + S32K3XX_ADC_MSR_OFFSET)
+#define S32K3XX_ADC2_ISR (S32K3XX_ADC2_BASE + S32K3XX_ADC_ISR_OFFSET)
+#define S32K3XX_ADC2_CEOCFR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CEOCFR0_OFFSET)
+#define S32K3XX_ADC2_CEOCFR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CEOCFR1_OFFSET)
+#define S32K3XX_ADC2_CEOCFR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CEOCFR2_OFFSET)
+#define S32K3XX_ADC2_IMR (S32K3XX_ADC2_BASE + S32K3XX_ADC_IMR_OFFSET)
+#define S32K3XX_ADC2_CIMR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CIMR0_OFFSET)
+#define S32K3XX_ADC2_CIMR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CIMR1_OFFSET)
+#define S32K3XX_ADC2_CIMR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CIMR2_OFFSET)
+#define S32K3XX_ADC2_WTISR (S32K3XX_ADC2_BASE + S32K3XX_ADC_WTISR_OFFSET)
+#define S32K3XX_ADC2_WTIMR (S32K3XX_ADC2_BASE + S32K3XX_ADC_WTIMR_OFFSET)
+#define S32K3XX_ADC2_DMAE (S32K3XX_ADC2_BASE + S32K3XX_ADC_DMAE_OFFSET)
+#define S32K3XX_ADC2_DMAR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_DMAR0_OFFSET)
+#define S32K3XX_ADC2_DMAR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_DMAR1_OFFSET)
+#define S32K3XX_ADC2_DMAR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_DMAR2_OFFSET)
+#define S32K3XX_ADC2_THRHLR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_THRHLR0_OFFSET)
+#define S32K3XX_ADC2_THRHLR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_THRHLR1_OFFSET)
+#define S32K3XX_ADC2_THRHLR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_THRHLR2_OFFSET)
+#define S32K3XX_ADC2_THRHLR3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_THRHLR3_OFFSET)
+#define S32K3XX_ADC2_PSCR (S32K3XX_ADC2_BASE + S32K3XX_ADC_PSCR_OFFSET)
+#define S32K3XX_ADC2_PSR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PSR0_OFFSET)
+#define S32K3XX_ADC2_PSR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PSR1_OFFSET)
+#define S32K3XX_ADC2_PSR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PSR2_OFFSET)
+#define S32K3XX_ADC2_CTR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CTR0_OFFSET)
+#define S32K3XX_ADC2_CTR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CTR1_OFFSET)
+#define S32K3XX_ADC2_CTR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CTR2_OFFSET)
+#define S32K3XX_ADC2_NCMR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_NCMR0_OFFSET)
+#define S32K3XX_ADC2_NCMR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_NCMR1_OFFSET)
+#define S32K3XX_ADC2_NCMR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_NCMR2_OFFSET)
+#define S32K3XX_ADC2_JCMR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_JCMR0_OFFSET)
+#define S32K3XX_ADC2_JCMR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_JCMR1_OFFSET)
+#define S32K3XX_ADC2_JCMR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_JCMR2_OFFSET)
+#define S32K3XX_ADC2_DSDR (S32K3XX_ADC2_BASE + S32K3XX_ADC_DSDR_OFFSET)
+#define S32K3XX_ADC2_PDEDR (S32K3XX_ADC2_BASE + S32K3XX_ADC_PDEDR_OFFSET)
+
+#define S32K3XX_ADC2_PCDR(n) (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR_OFFSET(n))
+#define S32K3XX_ADC2_PCDR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR0_OFFSET)
+#define S32K3XX_ADC2_PCDR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR1_OFFSET)
+#define S32K3XX_ADC2_PCDR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR2_OFFSET)
+#define S32K3XX_ADC2_PCDR3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR3_OFFSET)
+#define S32K3XX_ADC2_PCDR4 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR4_OFFSET)
+#define S32K3XX_ADC2_PCDR5 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR5_OFFSET)
+#define S32K3XX_ADC2_PCDR6 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR6_OFFSET)
+#define S32K3XX_ADC2_PCDR7 (S32K3XX_ADC2_BASE + S32K3XX_ADC_PCDR7_OFFSET)
+
+#define S32K3XX_ADC2_ICDR(n) (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR_OFFSET(n))
+#define S32K3XX_ADC2_ICDR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR0_OFFSET)
+#define S32K3XX_ADC2_ICDR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR1_OFFSET)
+#define S32K3XX_ADC2_ICDR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR2_OFFSET)
+#define S32K3XX_ADC2_ICDR3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR3_OFFSET)
+#define S32K3XX_ADC2_ICDR4 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR4_OFFSET)
+#define S32K3XX_ADC2_ICDR5 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR5_OFFSET)
+#define S32K3XX_ADC2_ICDR6 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR6_OFFSET)
+#define S32K3XX_ADC2_ICDR7 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR7_OFFSET)
+#define S32K3XX_ADC2_ICDR8 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR8_OFFSET)
+#define S32K3XX_ADC2_ICDR9 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR9_OFFSET)
+#define S32K3XX_ADC2_ICDR10 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR10_OFFSET)
+#define S32K3XX_ADC2_ICDR11 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR11_OFFSET)
+#define S32K3XX_ADC2_ICDR12 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR12_OFFSET)
+#define S32K3XX_ADC2_ICDR13 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR13_OFFSET)
+#define S32K3XX_ADC2_ICDR14 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR14_OFFSET)
+#define S32K3XX_ADC2_ICDR15 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR15_OFFSET)
+#define S32K3XX_ADC2_ICDR16 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR16_OFFSET)
+#define S32K3XX_ADC2_ICDR17 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR17_OFFSET)
+#define S32K3XX_ADC2_ICDR18 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR18_OFFSET)
+#define S32K3XX_ADC2_ICDR19 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR19_OFFSET)
+#define S32K3XX_ADC2_ICDR20 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR20_OFFSET)
+#define S32K3XX_ADC2_ICDR21 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR21_OFFSET)
+#define S32K3XX_ADC2_ICDR22 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR22_OFFSET)
+#define S32K3XX_ADC2_ICDR23 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ICDR23_OFFSET)
+
+#define S32K3XX_ADC2_ECDR(n) (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR_OFFSET(n))
+#define S32K3XX_ADC2_ECDR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR0_OFFSET)
+#define S32K3XX_ADC2_ECDR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR1_OFFSET)
+#define S32K3XX_ADC2_ECDR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR2_OFFSET)
+#define S32K3XX_ADC2_ECDR3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR3_OFFSET)
+#define S32K3XX_ADC2_ECDR4 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR4_OFFSET)
+#define S32K3XX_ADC2_ECDR5 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR5_OFFSET)
+#define S32K3XX_ADC2_ECDR6 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR6_OFFSET)
+#define S32K3XX_ADC2_ECDR7 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR7_OFFSET)
+#define S32K3XX_ADC2_ECDR8 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR8_OFFSET)
+#define S32K3XX_ADC2_ECDR9 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR9_OFFSET)
+#define S32K3XX_ADC2_ECDR10 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR10_OFFSET)
+#define S32K3XX_ADC2_ECDR11 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR11_OFFSET)
+#define S32K3XX_ADC2_ECDR12 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR12_OFFSET)
+#define S32K3XX_ADC2_ECDR13 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR13_OFFSET)
+#define S32K3XX_ADC2_ECDR14 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR14_OFFSET)
+#define S32K3XX_ADC2_ECDR15 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR15_OFFSET)
+#define S32K3XX_ADC2_ECDR16 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR16_OFFSET)
+#define S32K3XX_ADC2_ECDR17 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR17_OFFSET)
+#define S32K3XX_ADC2_ECDR18 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR18_OFFSET)
+#define S32K3XX_ADC2_ECDR19 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR19_OFFSET)
+#define S32K3XX_ADC2_ECDR20 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR20_OFFSET)
+#define S32K3XX_ADC2_ECDR21 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR21_OFFSET)
+#define S32K3XX_ADC2_ECDR22 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR22_OFFSET)
+#define S32K3XX_ADC2_ECDR23 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR23_OFFSET)
+#define S32K3XX_ADC2_ECDR24 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR24_OFFSET)
+#define S32K3XX_ADC2_ECDR25 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR25_OFFSET)
+#define S32K3XX_ADC2_ECDR26 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR26_OFFSET)
+#define S32K3XX_ADC2_ECDR27 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR27_OFFSET)
+#define S32K3XX_ADC2_ECDR28 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR28_OFFSET)
+#define S32K3XX_ADC2_ECDR29 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR29_OFFSET)
+#define S32K3XX_ADC2_ECDR30 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR30_OFFSET)
+#define S32K3XX_ADC2_ECDR31 (S32K3XX_ADC2_BASE + S32K3XX_ADC_ECDR31_OFFSET)
+
+#define S32K3XX_ADC2_CWSELRPI0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELRPI0_OFFSET)
+#define S32K3XX_ADC2_CWSELRPI1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELRPI1_OFFSET)
+#define S32K3XX_ADC2_CWSELRSI0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELRSI0_OFFSET)
+#define S32K3XX_ADC2_CWSELRSI1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELRSI1_OFFSET)
+#define S32K3XX_ADC2_CWSELRSI2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELRSI2_OFFSET)
+#define S32K3XX_ADC2_CWSELREI0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELREI0_OFFSET)
+#define S32K3XX_ADC2_CWSELREI1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELREI1_OFFSET)
+#define S32K3XX_ADC2_CWSELREI2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELREI2_OFFSET)
+#define S32K3XX_ADC2_CWSELREI3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWSELREI3_OFFSET)
+#define S32K3XX_ADC2_CWENR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWENR0_OFFSET)
+#define S32K3XX_ADC2_CWENR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWENR1_OFFSET)
+#define S32K3XX_ADC2_CWENR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CWENR2_OFFSET)
+#define S32K3XX_ADC2_AWORR0 (S32K3XX_ADC2_BASE + S32K3XX_ADC_AWORR0_OFFSET)
+#define S32K3XX_ADC2_AWORR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_AWORR1_OFFSET)
+#define S32K3XX_ADC2_AWORR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_AWORR2_OFFSET)
+#define S32K3XX_ADC2_STCR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STCR1_OFFSET)
+#define S32K3XX_ADC2_STCR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STCR2_OFFSET)
+#define S32K3XX_ADC2_STCR3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STCR3_OFFSET)
+#define S32K3XX_ADC2_STBRR (S32K3XX_ADC2_BASE + S32K3XX_ADC_STBRR_OFFSET)
+#define S32K3XX_ADC2_STSR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STSR1_OFFSET)
+#define S32K3XX_ADC2_STSR2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STSR2_OFFSET)
+#define S32K3XX_ADC2_STSR3 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STSR3_OFFSET)
+#define S32K3XX_ADC2_STSR4 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STSR4_OFFSET)
+#define S32K3XX_ADC2_STDR1 (S32K3XX_ADC2_BASE + S32K3XX_ADC_STDR1_OFFSET)
+#define S32K3XX_ADC2_STAW0R (S32K3XX_ADC2_BASE + S32K3XX_ADC_STAW0R_OFFSET)
+#define S32K3XX_ADC2_STAW1R (S32K3XX_ADC2_BASE + S32K3XX_ADC_STAW1R_OFFSET)
+#define S32K3XX_ADC2_STAW2R (S32K3XX_ADC2_BASE + S32K3XX_ADC_STAW2R_OFFSET)
+#define S32K3XX_ADC2_STAW4R (S32K3XX_ADC2_BASE + S32K3XX_ADC_STAW4R_OFFSET)
+#define S32K3XX_ADC2_STAW5R (S32K3XX_ADC2_BASE + S32K3XX_ADC_STAW5R_OFFSET)
+#define S32K3XX_ADC2_AMSIO (S32K3XX_ADC2_BASE + S32K3XX_ADC_AMSIO_OFFSET )
+#define S32K3XX_ADC2_CALBISTREG (S32K3XX_ADC2_BASE + S32K3XX_ADC_CALBISTREG_OFFSET)
+#define S32K3XX_ADC2_OFSGNUSR (S32K3XX_ADC2_BASE + S32K3XX_ADC_OFSGNUSR_OFFSET)
+#define S32K3XX_ADC2_CAL2 (S32K3XX_ADC2_BASE + S32K3XX_ADC_CAL2_OFFSET)
+
+/* ADC Register Bitfield Definitions ****************************************/
+
+/* Main Configuration Register (MCR) */
+
+#define ADC_MCR_PWDN (1 << 0) /* Bit 0: Power Down (PWDN) */
+#define ADC_MCR_ADCLKSEL_SHIFT (1) /* Bits 1-2: Conversion Clock (ADC_clk) Frequency Selection (ADCLKSEL) */
+#define ADC_MCR_ADCLKSEL_MASK (0x03 << ADC_MCR_ADCLKSEL_SHIFT)
+# define ADC_MCR_ADCLKSEL_DIV1 (0x00 << ADC_MCR_ADCLKSEL_SHIFT) /* (Module Clock Frequency)/1 */
+# define ADC_MCR_ADCLKSEL_DIV2 (0x01 << ADC_MCR_ADCLKSEL_SHIFT) /* (Module Clock Frequency)/2 */
+# define ADC_MCR_ADCLKSEL_DIV4 (0x02 << ADC_MCR_ADCLKSEL_SHIFT) /* (Module Clock Frequency)/4 */
+# define ADC_MCR_ADCLKSEL_DIV8 (0x03 << ADC_MCR_ADCLKSEL_SHIFT) /* (Module Clock Frequency)/8 */
+
+ /* Bits 3-4: Reserved */
+#define ADC_MCR_ACKO (1 << 5) /* Bit 5: Auto Clock Off (ACKO) */
+#define ADC_MCR_ABORT (1 << 6) /* Bit 6: Abort Conversion (ABORT) */
+#define ADC_MCR_ABORTCHAIN (1 << 7) /* Bit 7: Abort Chain (ABORTCHAIN) */
+ /* Bit 8: Reserved */
+#define ADC_MCR_AVGS_SHIFT (9) /* Bits 9-10: Averaging Select (AVGS) */
+#define ADC_MCR_AVGS_MASK (0x03 << ADC_MCR_AVGS_SHIFT)
+# define ADC_MCR_AVGS_4CONV (0x00 << ADC_MCR_AVGS_SHIFT) /* 4 Conversions */
+# define ADC_MCR_AVGS_8CONV (0x01 << ADC_MCR_AVGS_SHIFT) /* 8 Conversions */
+# define ADC_MCR_AVGS_16CONV (0x02 << ADC_MCR_AVGS_SHIFT) /* 16 Conversions */
+# define ADC_MCR_AVGS_32CONV (0x03 << ADC_MCR_AVGS_SHIFT) /* 32 Conversions */
+
+#define ADC_MCR_AVGEN (1 << 11) /* Bit 11: Averaging Enable (AVGEN) */
+ /* Bits 12-14: Reserved */
+#define ADC_MCR_STCL (1 << 15) /* Bit 15: Self-Test Configuration Lock (STCL) */
+#define ADC_MCR_BCTU_MODE (1 << 16) /* Bit 16: Body Cross Trigger Unit Mode Select (BCTU_MODE) */
+#define ADC_MCR_BCTUEN (1 << 17) /* Bit 17: Body Cross Trigger Unit Enable (BCTUEN) */
+ /* Bit 18-19: Reserved */
+#define ADC_MCR_JSTART (1 << 20) /* Bit 20: Injected Start (JSTART) */
+#define ADC_MCR_JEDGE (1 << 21) /* Bit 21: Injected Trigger Edge Selection (JEDGE) */
+#define ADC_MCR_JTRGEN (1 << 22) /* Bit 22: Injection Trigger Enable (JTRGEN) */
+ /* Bit 23: Reserved */
+#define ADC_MCR_NSTART (1 << 24) /* Bit 24: Start Normal Conversion (NSTART) */
+#define ADC_MCR_XSTRTEN (1 << 25) /* Bit 25: Auxiliary External Start Enable (XSTRTEN) */
+#define ADC_MCR_EDGE (1 << 26) /* Bit 26: External Trigger Edge Selection (EDGE) */
+#define ADC_MCR_TRGEN (1 << 27) /* Bit 27: External Trigger Enable (TRGEN) */
+ /* Bit 28: Reserved */
+#define ADC_MCR_MODE (1 << 29) /* Bit 29: Normal Conversion Mode (MODE) */
+#define ADC_MCR_WLSIDE (1 << 30) /* Bit 30: Write Left-Aligned (WLSIDE) */
+#define ADC_MCR_OWREN (1 << 31) /* Bit 31: Overwrite Enable (OWREN) */
+
+/* Main Status Register (MSR) */
+
+#define ADC_MSR_ADCSTATUS_SHIFT (0) /* Bits 0-2: ADC State (ADCSTATUS) */
+#define ADC_MSR_ADCSTATUS_MASK (0x07 << ADC_MSR_ADCSTATUS_SHIFT)
+# define ADC_MSR_ADCSTATUS_IDLE (0x00 << ADC_MSR_ADCSTATUS_SHIFT) /* Idle */
+# define ADC_MSR_ADCSTATUS_PWRDOWN (0x01 << ADC_MSR_ADCSTATUS_SHIFT) /* Power Down */
+# define ADC_MSR_ADCSTATUS_WAIT (0x02 << ADC_MSR_ADCSTATUS_SHIFT) /* Wait */
+# define ADC_MSR_ADCSTATUS_CALIB (0x03 << ADC_MSR_ADCSTATUS_SHIFT) /* Calibrate */
+# define ADC_MSR_ADCSTATUS_CONV (0x04 << ADC_MSR_ADCSTATUS_SHIFT) /* Convert */
+# define ADC_MSR_ADCSTATUS_DONE (0x06 << ADC_MSR_ADCSTATUS_SHIFT) /* Done */
+
+ /* Bits 3-4: Reserved */
+#define ADC_MSR_ADCO (1 << 5) /* Bit 5: Auto Clock-Off On (ACKO) */
+ /* Bits 6-8: Reserved */
+#define ADC_MSR_CHADDR_SHIFT (9) /* Bits 9-15: Input Under Measure (CHADDR) */
+#define ADC_MSR_CHADDR_MASK (0x7f << ADC_MSR_CHADDR_SHIFT)
+#define ADC_MSR_BCTUSTART (1 << 16) /* Bit 16: BCTU Conversion Started (BCTUSTART) */
+ /* Bit 17: Reserved */
+#define ADC_MSR_SELF_TEST_S (1 << 18) /* Bit 18: Indicates whether an ongoing conversion is for self-test (SELF_TEST_S) */
+ /* Bit 19: Reserved */
+#define ADC_MSR_JSTART (1 << 20) /* Bit 20: Injected Conversion Started (JSTART) */
+ /* Bits 21-22: Reserved */
+#define ADC_MSR_JABORT (1 << 23) /* Bit 23: Injected Conversion Aborted (JABORT) */
+#define ADC_MSR_NSTART (1 << 24) /* Bit 24: Normal Conversion Started (NSTART) */
+ /* Bits 25-30: Reserved */
+#define ADC_MSR_CALIBRTD (1 << 31) /* Bit 31: Calibration Status (CALIBRTD) */
+
+/* Interrupt Status Register (ISR) */
+
+#define ADC_ISR_ECH (1 << 0) /* Bit 0: End of Chain Conversion (ECH) */
+#define ADC_ISR_EOC (1 << 1) /* Bit 1: End of Conversion (EOC) */
+#define ADC_ISR_JECH (1 << 2) /* Bit 2: End of Injected Chain Conversion (JECH) */
+#define ADC_ISR_JEOC (1 << 3) /* Bit 3: End of Injected Conversion (JEOC) */
+#define ADC_ISR_EOBCTU (1 << 4) /* Bit 4: End of BCTU Conversion (EOBCTU) */
+ /* Bits 5-31: Reserved */
+
+/* Channel End Of Conversation Flag Register for Precision Inputs (CEOCFR0) */
+
+#define ADC_CEOCFR0_PIEOCF(n) (1 << (n)) /* Bits 0-7: Precision Input End of Conversion Flag n (PIEOCFn) */
+ /* Bits 8-31: Reserved */
+
+/* Channel End Of Conversation Flag Register for Standard Inputs (CEOCFR1) */
+
+#define ADC_CEOCFR1_SIEOCF(n) (1 << (n)) /* Bits 0-23: Standard Input End of Conversion Flag n (SIEOCFn) */
+ /* Bits 24-31: Reserved */
+
+/* Channel End Of Conversation Flag Register for External Inputs (CEOCFR2) */
+
+#define ADC_CEOCFR2_EIEOCF(n) (1 << (n)) /* Bits 0-31: External Input End of Conversion Flag n (EIEOCFn) */
+
+/* Interrupt Mask Register (IMR) */
+
+#define ADC_IMR_MSKECH (1 << 0) /* Bit 0: ECH Interrupt Flag Enable (MSKECH) */
+#define ADC_IMR_MSKEOC (1 << 1) /* Bit 1: EOC Interrupt Flag Enable (MSKEOC) */
+#define ADC_IMR_MSKJECH (1 << 2) /* Bit 2: JECH Interrupt Flag Enable (MSKJECH) */
+#define ADC_IMR_MSKJEOC (1 << 3) /* Bit 3: JEOC Interrupt Flag Enable (MSKJEOC) */
+#define ADC_IMR_MSKEOBCTU (1 << 4) /* Bit 4: EOBCTU Interrupt Flag Enable (MSKEOBCTU) */
+ /* Bits 5-31: Reserved */
+
+/* EOC Interrupt Enable Register for Precision Inputs (CIMR0) */
+
+#define ADC_CIMR0_PIEOCIEN(n) (1 << (n)) /* Bits 0-7: Precision Input EOC Interrupt Enable n (PIEOCIEN) */
+ /* Bits 8-31: Reserved */
+
+/* EOC Interrupt Enable Register for Standard Inputs (CIMR1) */
+
+#define ADC_CIMR1_SIEOCIEN(n) (1 << (n)) /* Bits 0-23: Standard Input EOC Interrupt Enable n (SIEOCIEN) */
+ /* Bits 24-31: Reserved */
+
+/* EOC Interrupt Enable Register for External Inputs (CIMR2) */
+
+#define ADC_CIMR2_EIEOCIEN(n) (1 << (n)) /* Bits 0-31: External Input EOC Interrupt Enable n (EIEOCIEN) */
+
+/* Analog Watchdog Threshold Interrupt Status Register (WTISR) */
+
+#define ADC_WTISR_LAWIF1 (1 << 0) /* Bit 0: Low Analog Watchdog Interrupt Flag Enable 1 (LAWIF1) */
+#define ADC_WTISR_HAWIF1 (1 << 1) /* Bit 1: High Analog Watchdog Interrupt Flag Enable 1 (HAWIF1) */
+#define ADC_WTISR_LAWIF2 (1 << 2) /* Bit 2: Low Analog Watchdog Interrupt Flag Enable 2 (LAWIF2) */
+#define ADC_WTISR_HAWIF2 (1 << 3) /* Bit 3: High Analog Watchdog Interrupt Flag Enable 2 (HAWIF2) */
+#define ADC_WTISR_LAWIF3 (1 << 4) /* Bit 4: Low Analog Watchdog Interrupt Flag Enable 3 (LAWIF3) */
+#define ADC_WTISR_HAWIF3 (1 << 5) /* Bit 5: High Analog Watchdog Interrupt Flag Enable 3 (HAWIF3) */
+#define ADC_WTISR_LAWIF4 (1 << 6) /* Bit 6: Low Analog Watchdog Interrupt Flag Enable 4 (LAWIF4) */
+#define ADC_WTISR_HAWIF4 (1 << 7) /* Bit 7: High Analog Watchdog Interrupt Flag Enable 4 (HAWIF4) */
+#define ADC_WTISR_LAWIF5 (1 << 8) /* Bit 8: Low Analog Watchdog Interrupt Flag Enable 5 (LAWIF5) */
+#define ADC_WTISR_HAWIF5 (1 << 9) /* Bit 9: High Analog Watchdog Interrupt Flag Enable 5 (HAWIF5) */
+#define ADC_WTISR_LAWIF6 (1 << 10) /* Bit 10: Low Analog Watchdog Interrupt Flag Enable 6 (LAWIF6) */
+#define ADC_WTISR_HAWIF6 (1 << 11) /* Bit 11: High Analog Watchdog Interrupt Flag Enable 6 (HAWIF6) */
+#define ADC_WTISR_LAWIF7 (1 << 12) /* Bit 12: Low Analog Watchdog Interrupt Flag Enable 7 (LAWIF7) */
+#define ADC_WTISR_HAWIF7 (1 << 13) /* Bit 13: High Analog Watchdog Interrupt Flag Enable 7 (HAWIF7) */
+#define ADC_WTISR_LAWIF8 (1 << 14) /* Bit 14: Low Analog Watchdog Interrupt Flag Enable 8 (LAWIF8) */
+#define ADC_WTISR_HAWIF8 (1 << 15) /* Bit 15: High Analog Watchdog Interrupt Flag Enable 8 (HAWIF8) */
+#define ADC_WTISR_LAWIF9 (1 << 16) /* Bit 16: Low Analog Watchdog Interrupt Flag Enable 9 (LAWIF9) */
+#define ADC_WTISR_HAWIF9 (1 << 17) /* Bit 17: High Analog Watchdog Interrupt Flag Enable 9 (HAWIF9) */
+#define ADC_WTISR_LAWIF10 (1 << 18) /* Bit 18: Low Analog Watchdog Interrupt Flag Enable 10 (LAWIF10) */
+#define ADC_WTISR_HAWIF10 (1 << 19) /* Bit 19: High Analog Watchdog Interrupt Flag Enable 10 (HAWIF10) */
+#define ADC_WTISR_LAWIF11 (1 << 20) /* Bit 20: Low Analog Watchdog Interrupt Flag Enable 11 (LAWIF11) */
+#define ADC_WTISR_HAWIF11 (1 << 21) /* Bit 21: High Analog Watchdog Interrupt Flag Enable 11 (HAWIF11) */
+#define ADC_WTISR_LAWIF12 (1 << 22) /* Bit 22: Low Analog Watchdog Interrupt Flag Enable 12 (LAWIF12) */
+#define ADC_WTISR_HAWIF12 (1 << 23) /* Bit 23: High Analog Watchdog Interrupt Flag Enable 12 (HAWIF12) */
+#define ADC_WTISR_LAWIF13 (1 << 24) /* Bit 24: Low Analog Watchdog Interrupt Flag Enable 13 (LAWIF13) */
+#define ADC_WTISR_HAWIF13 (1 << 25) /* Bit 25: High Analog Watchdog Interrupt Flag Enable 13 (HAWIF13) */
+#define ADC_WTISR_LAWIF14 (1 << 26) /* Bit 26: Low Analog Watchdog Interrupt Flag Enable 14 (LAWIF14) */
+#define ADC_WTISR_HAWIF14 (1 << 27) /* Bit 27: High Analog Watchdog Interrupt Flag Enable 14 (HAWIF14) */
+#define ADC_WTISR_LAWIF15 (1 << 28) /* Bit 28: Low Analog Watchdog Interrupt Flag Enable 15 (LAWIF15) */
+#define ADC_WTISR_HAWIF15 (1 << 29) /* Bit 29: High Analog Watchdog Interrupt Flag Enable 15 (HAWIF15) */
+#define ADC_WTISR_LAWIF16 (1 << 30) /* Bit 30: Low Analog Watchdog Interrupt Flag Enable 16 (LAWIF16) */
+#define ADC_WTISR_HAWIF16 (1 << 31) /* Bit 31: High Analog Watchdog Interrupt Flag Enable 16 (HAWIF16) */
+
+/* Analog Watchdog Threshold Interrupt Enable Register (WTIMR) */
+
+#define ADC_WTIMR_LAWIFEN1 (1 << 0) /* Bit 0: Low Analog Watchdog Interrupt Flag Enable 1 (LAWIFEN1) */
+#define ADC_WTIMR_HDWIFEN1 (1 << 1) /* Bit 1: High Data Watchdog Interrupt Flag Enable 1 (HDWIFEN1) */
+#define ADC_WTIMR_LAWIFEN2 (1 << 2) /* Bit 2: Low Analog Watchdog Interrupt Flag Enable 2 (LAWIFEN2) */
+#define ADC_WTIMR_HDWIFEN2 (1 << 3) /* Bit 3: High Data Watchdog Interrupt Flag Enable 2 (HDWIFEN2) */
+#define ADC_WTIMR_LAWIFEN3 (1 << 4) /* Bit 4: Low Analog Watchdog Interrupt Flag Enable 3 (LAWIFEN3) */
+#define ADC_WTIMR_HDWIFEN3 (1 << 5) /* Bit 5: High Data Watchdog Interrupt Flag Enable 3 (HDWIFEN3) */
+#define ADC_WTIMR_LAWIFEN4 (1 << 6) /* Bit 6: Low Analog Watchdog Interrupt Flag Enable 4 (LAWIFEN4) */
+#define ADC_WTIMR_HDWIFEN4 (1 << 7) /* Bit 7: High Data Watchdog Interrupt Flag Enable 4 (HDWIFEN4) */
+ /* Bits 8-31: Reserved */
+
+/* Direct Memory Access Configuration Register (DMAE) */
+
+#define ADC_DMAE_DMAEN (1 << 0) /* Bit 0: DMA Enable (DMAEN) */
+#define ADC_DMAE_DCLR (1 << 1) /* Bit 1: DMA Clear Request (DCLR) */
+ /* Bits 2-31: Reserved */
+
+/* DMA Request Enable Register for Precision Inputs (DMAR0) */
+
+#define ADC_DMAR0_PIDMAREN(n) (1 << (n)) /* Bits 0-7: Precision Input DMA Request Enable n (PIDMARENn) */
+ /* Bits 8-31: Reserved */
+
+/* DMA Request Enable Register for Standard Inputs (DMAR1) */
+
+#define ADC_DMAR1_SIDMAREN(n) (1 << (n)) /* Bits 0-23: Standard Input DMA Request Enable n (SIDMARENn) */
+ /* Bits 24-31: Reserved */
+
+/* DMA Request Enable Register for External Inputs (DMAR2) */
+
+#define ADC_DMAR2_EIDMAREN(n) (1 << (n)) /* Bits 0-31: External Input DMA Request Enable n (EIDMARENn) */
+
+/* Analog Watchdog Threshold Values Register n (THRHLRn) */
+
+#define ADC_THRHLR_THRL_SHIFT (0) /* Bits 0-14: Low Threshold Value (THRL) */
+#define ADC_THRHLR_THRL_MASK (0x7fff << ADC_THRHLR_THRL_SHIFT)
+ /* Bit 15: Reserved */
+#define ADC_THRHLR_THRH_SHIFT (16) /* Bits 16-30: High Threshold Value (THRH) */
+#define ADC_THRHLR_THRH_MASK (0x7fff << ADC_THRHLR_THRH_SHIFT)
+ /* Bit 31: Reserved */
+
+/* Presampling Control Register (PSCR) */
+
+#define ADC_PSCR_PRECONV (1 << 0) /* Bit 0: Convert Presampled Value (PRECONV) */
+#define ADC_PSCR_PREVAL0 (1 << 1) /* Bit 1: Presampling Voltage Select for Precision Inputs (PREVAL0) */
+ /* Bit 2: Reserved */
+#define ADC_PSCR_PREVAL1 (1 << 3) /* Bit 3: Presampling Voltage Select for Standard Inputs (PREVAL1) */
+ /* Bit 4: Reserved */
+#define ADC_PSCR_PREVAL2 (1 << 5) /* Bit 5: Presampling Voltage Select for External Inputs (PREVAL2) */
+ /* Bits 6-31: Reserved */
+
+/* Presampling Enable Register for Precision Inputs (PSR0) */
+
+#define ADC_PSR0_PRES(n) (1 << (n)) /* Bits 0-7: Presampling Enable n (PRESn) */
+ /* Bits 8-31: Reserved */
+
+/* Presampling Enable Register for Standard Inputs (PSR1) */
+
+#define ADC_PSR1_PRES(n) (1 << (n)) /* Bits 0-23: Presampling Enable n (PRESn) */
+ /* Bits 24-31: Reserved */
+
+/* Presampling Enable Register for External Inputs (PSR2) */
+
+#define ADC_PSR2_PRES(n) (1 << (n)) /* Bits 0-31: Presampling Enable n (PRESn) */
+
+/* Conversion Timing Register for Precision Inputs (CTR0) */
+
+#define ADC_CTR0_INPSAMP_SHIFT (0) /* Bits 0-7: Input Sample Cycles (INPSAMP) */
+#define ADC_CTR0_INPSAMP_MASK (0xff << ADC_CTR0_INPSAMP_SHIFT)
+ /* Bits 8-31: Reserved */
+
+/* Conversion Timing Register for Standard Inputs (CTR1) */
+
+#define ADC_CTR1_INPSAMP_SHIFT (0) /* Bits 0-7: Input Sample Cycles (INPSAMP) */
+#define ADC_CTR1_INPSAMP_MASK (0xff << ADC_CTR1_INPSAMP_SHIFT)
+ /* Bits 8-31: Reserved */
+
+/* Conversion Timing Register for External Inputs (CTR2) */
+
+#define ADC_CTR2_INPSAMP_SHIFT (0) /* Bits 0-7: Input Sample Cycles (INPSAMP) */
+#define ADC_CTR2_INPSAMP_MASK (0xff << ADC_CTR2_INPSAMP_SHIFT)
+ /* Bits 8-31: Reserved */
+
+/* Normal Conversion Enable Register for Precision Inputs (NCMR0) */
+
+#define ADC_NMCR0_CH(n) (1 << (n)) /* Bits 0-7: Precision Input n to be Converted (CHn) */
+ /* Bits 8-31: Reserved */
+
+/* Normal Conversion Enable Register for Standard Inputs (NCMR1) */
+
+#define ADC_NMCR1_CH(n) (1 << (n)) /* Bits 0-23: Standard Input n to be Converted (CHn) */
+ /* Bits 24-31: Reserved */
+
+/* Normal Conversion Enable Register for External Inputs (NCMR2) */
+
+#define ADC_NMCR2_CH(n) (1 << (n)) /* Bits 0-31: External Input n to be Converted (CHn) */
+
+/* Injected Conversion Enable Register for Precision Inputs (JCMR0) */
+
+#define ADC_JMCR0_CH(n) (1 << (n)) /* Bits 0-7: Precision Input to be Converted (CHn) */
+ /* Bits 8-31: Reserved */
+
+/* Injected Conversion Enable Register for Standard Inputs (JCMR1) */
+
+#define ADC_JMCR1_CH(n) (1 << (n)) /* Bits 0-23: Standard Input to be Converted (CHn) */
+ /* Bits 24-31: Reserved */
+
+/* Injected Conversion Enable Register for External Inputs (JCMR2) */
+
+#define ADC_JMCR2_CH(n) (1 << (n)) /* Bits 0-31: External Input to be Converted (CHn) */
+
+/* Delay Start of Data Conversion Register (DSDR) */
+
+#define ADC_DSDR_DSD_SHIFT (0) /* Bits 0-15: Delay (DSD) */
+#define ASD_DSDR_DSD_MASK (0xff << ADC_DSDR_DSD_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* Power Down Exit Delay Register (PDEDR) */
+
+#define ADC_PDEDR_PDED_SHIFT (0) /* Bits 0-7: Delay (PDED) */
+#define ASD_PDEDR_PDED_MASK (0x0f << ADC_PDEDR_PDED_SHIFT)
+ /* Bits 8-31: Reserved */
+
+/* Precision Input n Conversion Data Register (PCDRn) */
+
+#define ADC_PCDR_CDATA_SHIFT (0) /* Bits 0-15: Conversion Data (CDATA) */
+#define ADC_PCDR_CDATA_MASK (0xff << ADC_PCDR_CDATA_SHIFT)
+#define ADC_PCDR_RESULT_SHIFT (16) /* Bits 16-17: Conversion Data Type (RESULT) */
+#define ADC_PCDR_RESULT_MASK (0x03 << ADC_PCDR_RESULT_SHIFT)
+# define ADC_PCDR_RESULT_NORM (0x00 << ADC_PCDR_RESULT_MASK) /* Normal Trigger */
+# define ADC_PCDR_RESULT_INJ (0x01 << ADC_PCDR_RESULT_MASK) /* Injected Trigger */
+# define ADC_PCDR_RESULT_BCTU (0x02 << ADC_PCDR_RESULT_MASK) /* BCTU Trigger */
+
+#define ADC_PCDR_OVERW (1 << 18) /* Bit 18: Overwrite Status Flag (OVERW) */
+#define ADC_PCDR_VALID (1 << 19) /* Bit 19: Conversion Data Available (VALID) */
+ /* Bits 20-31: Reserved */
+
+/* Standard Input n Conversion Data Register (ICDRn) */
+
+#define ADC_ICDR_CDATA_SHIFT (0) /* Bits 0-15: Conversion Data (CDATA) */
+#define ADC_ICDR_CDATA_MASK (0xff << ADC_ICDR_CDATA_SHIFT)
+#define ADC_ICDR_RESULT_SHIFT (16) /* Bits 16-17: Conversion Data Type (RESULT) */
+#define ADC_ICDR_RESULT_MASK (0x03 << ADC_ICDR_RESULT_SHIFT)
+# define ADC_ICDR_RESULT_NORM (0x00 << ADC_ICDR_RESULT_MASK) /* Normal Trigger */
+# define ADC_ICDR_RESULT_INJ (0x01 << ADC_ICDR_RESULT_MASK) /* Injected Trigger */
+# define ADC_ICDR_RESULT_BCTU (0x02 << ADC_ICDR_RESULT_MASK) /* BCTU Trigger */
+
+#define ADC_ICDR_OVERW (1 << 18) /* Bit 18: Overwrite Status Flag (OVERW) */
+#define ADC_ICDR_VALID (1 << 19) /* Bit 19: Conversion Data Available (VALID) */
+ /* Bits 20-31: Reserved */
+
+/* External Input n Conversion Data Register (ECDRn) */
+
+#define ADC_ECDR_CDATA_SHIFT (0) /* Bits 0-15: Conversion Data (CDATA) */
+#define ADC_ECDR_CDATA_MASK (0xff << ADC_ECDR_CDATA_SHIFT)
+#define ADC_ECDR_RESULT_SHIFT (16) /* Bits 16-17: Conversion Data Type (RESULT) */
+#define ADC_ECDR_RESULT_MASK (0x03 << ADC_ECDR_RESULT_SHIFT)
+# define ADC_ECDR_RESULT_NORM (0x00 << ADC_ECDR_RESULT_SHIFT) /* Normal Trigger */
+# define ADC_ECDR_RESULT_INJ (0x01 << ADC_ECDR_RESULT_SHIFT) /* Injected Trigger */
+# define ADC_ECDR_RESULT_BCTU (0x02 << ADC_ECDR_RESULT_SHIFT) /* BCTU Trigger */
+
+#define ADC_ECDR_OVERW (1 << 18) /* Bit 18: Overwrite Status Flag (OVERW) */
+#define ADC_ECDR_VALID (1 << 19) /* Bit 19: Conversion Data Available (VALID) */
+ /* Bits 20-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for Precision Inputs 0
+ * (CWSELRPI0)
+ */
+
+#define ADC_CWSELRPI0_WSEL_SI0_0_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI0_0) */
+#define ADC_CWSELRPI0_WSEL_SI0_0_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_0_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_1_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI0_1) */
+#define ADC_CWSELRPI0_WSEL_SI0_1_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_1_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_2_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI0_2) */
+#define ADC_CWSELRPI0_WSEL_SI0_2_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_2_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_3_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI0_3) */
+#define ADC_CWSELRPI0_WSEL_SI0_3_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_3_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_4_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI0_4) */
+#define ADC_CWSELRPI0_WSEL_SI0_4_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_4_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_5_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI0_5) */
+#define ADC_CWSELRPI0_WSEL_SI0_5_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_5_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_6_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI0_6) */
+#define ADC_CWSELRPI0_WSEL_SI0_6_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_6_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELRPI0_WSEL_SI0_7_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI0_7) */
+#define ADC_CWSELRPI0_WSEL_SI0_7_MASK (0x03 << ADC_CWSELRPI0_WSEL_SI0_7_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for Precision Inputs 1
+ * (CWSELRPI1)
+ */
+
+ /* Bits 0-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for Standard Inputs 0
+ * (CWSELRSI0)
+ */
+
+#define ADC_CWSELRSI0_WSEL_SI0_0_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI0_0) */
+#define ADC_CWSELRSI0_WSEL_SI0_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI0_0_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI1_0_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI1_0) */
+#define ADC_CWSELRSI0_WSEL_SI1_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI1_0_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI2_0_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI2_0) */
+#define ADC_CWSELRSI0_WSEL_SI2_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI2_0_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI3_0_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI3_0) */
+#define ADC_CWSELRSI0_WSEL_SI3_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI3_0_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI4_0_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI4_0) */
+#define ADC_CWSELRSI0_WSEL_SI4_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI4_0_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI5_0_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI5_0) */
+#define ADC_CWSELRSI0_WSEL_SI5_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI5_0_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI6_0_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI6_0) */
+#define ADC_CWSELRSI0_WSEL_SI6_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI6_0_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELRSI0_WSEL_SI7_0_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI7_0) */
+#define ADC_CWSELRSI0_WSEL_SI7_0_MASK (0x03 << ADC_CWSELRSI0_WSEL_SI7_0_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for Standard Inputs 1
+ * (CWSELRSI1)
+ */
+
+#define ADC_CWSELRSI1_WSEL_SI0_1_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI0_1) */
+#define ADC_CWSELRSI1_WSEL_SI0_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI0_1_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI1_1_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI1_1) */
+#define ADC_CWSELRSI1_WSEL_SI1_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI1_1_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI2_1_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI2_1) */
+#define ADC_CWSELRSI1_WSEL_SI2_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI2_1_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI3_1_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI3_1) */
+#define ADC_CWSELRSI1_WSEL_SI3_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI3_1_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI4_1_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI4_1) */
+#define ADC_CWSELRSI1_WSEL_SI4_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI4_1_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI5_1_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI5_1) */
+#define ADC_CWSELRSI1_WSEL_SI5_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI5_1_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI6_1_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI6_1) */
+#define ADC_CWSELRSI1_WSEL_SI6_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI6_1_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELRSI1_WSEL_SI7_1_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI7_1) */
+#define ADC_CWSELRSI1_WSEL_SI7_1_MASK (0x03 << ADC_CWSELRSI1_WSEL_SI7_1_SHIFT)
+
+/* Channel Analog Watchdog Select Register for Standard Inputs 2
+ * (CWSELRSI2)
+ */
+
+#define ADC_CWSELRSI2_WSEL_SI0_2_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI0_2) */
+#define ADC_CWSELRSI2_WSEL_SI0_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI0_2_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI1_2_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI1_2) */
+#define ADC_CWSELRSI2_WSEL_SI1_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI1_2_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI2_2_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI2_2) */
+#define ADC_CWSELRSI2_WSEL_SI2_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI2_2_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI3_2_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI3_2) */
+#define ADC_CWSELRSI2_WSEL_SI3_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI3_2_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI4_2_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI4_2) */
+#define ADC_CWSELRSI2_WSEL_SI4_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI4_2_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI5_2_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI5_2) */
+#define ADC_CWSELRSI2_WSEL_SI5_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI5_2_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI6_2_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI6_2) */
+#define ADC_CWSELRSI2_WSEL_SI6_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI6_2_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELRSI2_WSEL_SI7_2_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI7_2) */
+#define ADC_CWSELRSI2_WSEL_SI7_2_MASK (0x03 << ADC_CWSELRSI2_WSEL_SI7_2_SHIFT)
+
+/* Channel Analog Watchdog Select Register for External Inputs 0
+ * (CWSELREI0)
+ */
+
+#define ADC_CWSELREI0_WSEL_SI0_0_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI0_0) */
+#define ADC_CWSELREI0_WSEL_SI0_0_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_0_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_1_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI0_1) */
+#define ADC_CWSELREI0_WSEL_SI0_1_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_1_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_2_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI0_2) */
+#define ADC_CWSELREI0_WSEL_SI0_2_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_2_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_3_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI0_3) */
+#define ADC_CWSELREI0_WSEL_SI0_3_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_3_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_4_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI0_4) */
+#define ADC_CWSELREI0_WSEL_SI0_4_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_4_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_5_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI0_5) */
+#define ADC_CWSELREI0_WSEL_SI0_5_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_5_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_6_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI0_6) */
+#define ADC_CWSELREI0_WSEL_SI0_6_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_6_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELREI0_WSEL_SI0_7_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI0_7) */
+#define ADC_CWSELREI0_WSEL_SI0_7_MASK (0x03 << ADC_CWSELREI0_WSEL_SI0_7_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for External Inputs 1
+ * (CWSELREI1)
+ */
+
+#define ADC_CWSELREI1_WSEL_SI1_8_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI1_8) */
+#define ADC_CWSELREI1_WSEL_SI1_8_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_8_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_9_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI1_9) */
+#define ADC_CWSELREI1_WSEL_SI1_9_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_9_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_10_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI1_10) */
+#define ADC_CWSELREI1_WSEL_SI1_10_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_10_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_11_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI1_11) */
+#define ADC_CWSELREI1_WSEL_SI1_11_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_11_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_12_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI1_12) */
+#define ADC_CWSELREI1_WSEL_SI1_12_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_12_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_13_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI1_13) */
+#define ADC_CWSELREI1_WSEL_SI1_13_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_13_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_14_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI1_14) */
+#define ADC_CWSELREI1_WSEL_SI1_14_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_14_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELREI1_WSEL_SI1_15_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI1_15) */
+#define ADC_CWSELREI1_WSEL_SI1_15_MASK (0x03 << ADC_CWSELREI1_WSEL_SI1_15_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for External Inputs 2
+ * (CWSELREI2)
+ */
+
+#define ADC_CWSELREI2_WSEL_SI2_16_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI2_16) */
+#define ADC_CWSELREI2_WSEL_SI2_16_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_16_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_17_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI2_17) */
+#define ADC_CWSELREI2_WSEL_SI2_17_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_17_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_18_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI2_18) */
+#define ADC_CWSELREI2_WSEL_SI2_18_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_18_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_19_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI2_19) */
+#define ADC_CWSELREI2_WSEL_SI2_19_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_19_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_20_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI2_20) */
+#define ADC_CWSELREI2_WSEL_SI2_20_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_20_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_21_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI2_21) */
+#define ADC_CWSELREI2_WSEL_SI2_21_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_21_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_22_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI2_22) */
+#define ADC_CWSELREI2_WSEL_SI2_22_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_22_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELREI2_WSEL_SI2_23_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI2_23) */
+#define ADC_CWSELREI2_WSEL_SI2_23_MASK (0x03 << ADC_CWSELREI2_WSEL_SI2_23_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Channel Analog Watchdog Select Register for External Inputs 3
+ * (CWSELREI3)
+ */
+
+#define ADC_CWSELREI3_WSEL_SI3_24_SHIFT (0) /* Bits 0-1: Analog Watchdog Selection (WSEL_SI3_24) */
+#define ADC_CWSELREI3_WSEL_SI3_24_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_24_SHIFT)
+ /* Bits 2-3: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_25_SHIFT (4) /* Bits 4-5: Analog Watchdog Selection (WSEL_SI3_25) */
+#define ADC_CWSELREI3_WSEL_SI3_25_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_25_SHIFT)
+ /* Bits 6-7: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_26_SHIFT (8) /* Bits 8-9: Analog Watchdog Selection (WSEL_SI3_26) */
+#define ADC_CWSELREI3_WSEL_SI3_26_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_26_SHIFT)
+ /* Bits 10-11: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_27_SHIFT (12) /* Bits 12-13: Analog Watchdog Selection (WSEL_SI3_27) */
+#define ADC_CWSELREI3_WSEL_SI3_27_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_27_SHIFT)
+ /* Bits 14-15: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_28_SHIFT (16) /* Bits 16-17: Analog Watchdog Selection (WSEL_SI3_28) */
+#define ADC_CWSELREI3_WSEL_SI3_28_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_28_SHIFT)
+ /* Bits 18-19: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_29_SHIFT (20) /* Bits 20-21: Analog Watchdog Selection (WSEL_SI3_29) */
+#define ADC_CWSELREI3_WSEL_SI3_29_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_29_SHIFT)
+ /* Bits 22-23: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_30_SHIFT (24) /* Bits 24-25: Analog Watchdog Selection (WSEL_SI3_30) */
+#define ADC_CWSELREI3_WSEL_SI3_30_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_30_SHIFT)
+ /* Bits 26-27: Reserved */
+#define ADC_CWSELREI3_WSEL_SI3_31_SHIFT (28) /* Bits 28-29: Analog Watchdog Selection (WSEL_SI3_31) */
+#define ADC_CWSELREI3_WSEL_SI3_31_MASK (0x03 << ADC_CWSELREI3_WSEL_SI3_31_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Channel Watchdog Enable Register for Precision Inputs (CWENR0) */
+
+#define ADC_CWENR0_CWEN(n) (1 << (n)) /* Bits 0-7: Channel Analog Watchdog Enable for Precision Inputs (CWENn) */
+ /* Bits 8-31: Reserved */
+
+/* Channel Watchdog Enable Register for Standard Inputs (CWENR1) */
+
+#define ADC_CWENR1_CWEN(n) (1 << (n)) /* Bits 0-23: Channel Analog Watchdog Enable for Standard Inputs (CWENn) */
+ /* Bits 24-31: Reserved */
+
+/* Channel Watchdog Enable Register for External Inputs (CWENR2) */
+
+#define ADC_CWENR2_CWEN(n) (1 << (n)) /* Bits 0-31: Channel Analog Watchdog Enable for External Inputs (CWENn) */
+
+/* Analog Watchdog Out of Range Register for Precision Inputs (AWORR0) */
+
+#define ADC_AWORR0_CWEN(n) (1 << (n)) /* Bits 0-7: Analog Watchdog Out of Range for Precision Inputs (AWOR_CHn) */
+ /* Bits 8-31: Reserved */
+
+/* Analog Watchdog Out of Range Register for Standard Inputs (AWORR1) */
+
+#define ADC_AWORR1_CWEN(n) (1 << (n)) /* Bits 0-23: Analog Watchdog Out of Range for Standard Inputs (AWOR_CHn) */
+ /* Bits 24-31: Reserved */
+
+/* Analog Watchdog Out of Range Register for External Inputs (AWORR2) */
+
+#define ADC_AWORR2_CWEN(n) (1 << (n)) /* Bits 0-31: Analog Watchdog Out of Range for External Inputs (AWOR_CHn) */
+
+/* Self-Test Configuration Register 1 (STCR1) */
+
+ /* Bits 0-7: Reserved */
+#define ADC_STCR1_INPSAMP_S_SHIFT (8) /* Bits 8-15: Input Sampling Time Algorithm S (INPSAMP_S) */
+#define ADC_STCR1_INPSAMP_S_MASK (0xff << ADC_STCR1_INPSAMP_S_SHIFT)
+ /* Bits 16-23: Reserved */
+#define ADC_STCR1_INPSAMP_C_SHIFT (24) /* Bits 24-31: Input Sampling Time Algorithm C (INPSAMP_C) */
+#define ADC_STCR1_INPSAMP_C_MASK (0xff << ADC_STCR1_INPSAMP_C_SHIFT)
+
+/* Self-Test Configuration Register 2 (STCR2) */
+
+#define ADC_STCR2_FMA_S (1 << 0) /* Bit 0: Fault Mapping Algorithm S (FMA_S) */
+ /* Bit 1: Reserved */
+#define ADC_STCR2_FMA_C (1 << 2) /* Bit 2: Fault Mapping Algorithm C (FMA_C) */
+#define ADC_STCR2_FMA_WDTERR (1 << 3) /* Bit 3: Fault Mapping Self-Test Watchdog Timer Error (FMA_WDTERR) */
+#define ADC_STCR2_FMA_WDSERR (1 << 4) /* Bit 4: Fault Mapping Self-Test Watchdog Sequence Error (FMA_WDSERR) */
+ /* Bits 5-6: Reserved */
+#define ADC_STCR2_EN (1 << 7) /* Bit 7: Self-Test Enable (EN) */
+ /* Bits 8-10: Reserved */
+#define ADC_STCR2_MSKERR_S0 (1 << 11) /* Bit 11: Mask Error Interrupt Algorithm S0 (MSKERR_S0) */
+#define ADC_STCR2_MSKERR_S1 (1 << 12) /* Bit 12: Mask Error Interrupt Algorithm S1 (MSKERR_S1) */
+#define ADC_STCR2_MSKERR_S2 (1 << 13) /* Bit 13: Mask Error Interrupt Algorithm S2 (MSKERR_S2) */
+ /* Bit 14: Reserved */
+#define ADC_STCR2_MSKERR_C (1 << 15) /* Bit 15: Mask Error Interrupt Algorithm C (MSKERR_C) */
+#define ADC_STCR2_MSKWDG_EOA_S (1 << 16) /* Bit 16: Mask Error Interrupt End Of Algorithm S (MSKWDG_EOA_S) */
+ /* Bit 17: Reserved */
+#define ADC_STCR2_MSKWDG_EOA_C (1 << 18) /* Bit 18: Mask Error Interrupt End Of Algorithm C (MSKWDG_EOA_C) */
+ /* Bits 19-22: Reserved */
+#define ADC_STCR2_MSKST_EOC (1 << 23) /* Bit 23: Mask Interrupt Self-Test End Of Conversion (MSKST_EOC) */
+ /* Bit 24: Reserved */
+#define ADC_STCR2_MSKWDTERR (1 << 25) /* Bit 25: Mask Interrupt Self-Test Watchdog Timer Error (MSKWDTERR) */
+#define ADC_STCR2_SERR (1 << 26) /* Bit 26: Self-Test Error Injection (SERR) */
+#define ADC_STCR2_MSKWDSERR (1 << 27) /* Bit 27: Mask Interrupt Self-Test Watchdog Sequence Error (MSKWDSERR) */
+ /* Bits 28-31: Reserved */
+
+/* Self-Test Configuration Register 3 (STCR3) */
+
+#define ADC_STCR3_MSTEP_SHIFT (0) /* Bits 0-4: Algorithm Step (MSTEP) */
+#define ADC_STCR3_MSTEP_MASK (0x1f << ADC_STCR3_MSTEP_SHIFT)
+ /* Bits 5-7: Reserved */
+#define ADC_STCR3_ALG_SHIFT (8) /* Bits 8-9: Algorithm Selection (ALG) */
+#define ADC_STCR3_ALG_MASK (0x03 << ADC_STCR3_ALG_SHIFT)
+# define ADC_STCR3_ALG_OSOM_ALGS_SS (0x00 << ADC_STCR3_ALG_SHIFT) /* One-Shot Operation Mode: Algorithm S (Single Step = MSTEP) */
+# define ADC_STCR3_ALG_OSOM_ALGC_SS (0x02 << ADC_STCR3_ALG_SHIFT) /* One-Shot Operation Mode: Algorithm C (Single Step = MSTEP) */
+# define ADC_STCR3_ALG_OSOM_ALGS (0x03 << ADC_STCR3_ALG_SHIFT) /* One-Shot Operation Mode: Algorithm S (Default) */
+# define ADC_STCR3_ALG_CCM_ALGS (0x00 << ADC_STCR3_ALG_SHIFT) /* Continuous Conversion Mode: Algorithm S */
+# define ADC_STCR3_ALG_CCM_ALGC (0x02 << ADC_STCR3_ALG_SHIFT) /* Continuous Conversion Mode: Algorithm C */
+# define ADC_STCR3_ALG_CCM_ALGSS (0x03 << ADC_STCR3_ALG_SHIFT) /* Continuous Conversion Mode: Algorithm S + Algorithm C (Default) */
+
+ /* Bits 10-31: Reserved */
+
+/* Self-Test Baud Rate Register (STBRR) */
+
+#define ADC_STBRR_BR_SHIFT (0) /* Bits 0-7: Baud Rate (BR) */
+#define ADC_STBRR_BR_MASK (0xff << ADC_STBRR_BR_SHIFT)
+ /* Bits 8-15: Reserved */
+#define ADC_STBRR_WDT_SHIFT (16) /* Bits 16-18: Self-Test Watchdog Timer (WDT) */
+#define ADC_STBRR_WDT_MASK (0x07 << ADC_STBRR_WDT_SHIFT)
+# define ADC_STBRR_WDT_8KCYC (0x00 << ADC_STBRR_WDT_SHIFT) /* 8,192 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_39KCYC (0x01 << ADC_STBRR_WDT_SHIFT) /* 39,936 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_78KCYC (0x02 << ADC_STBRR_WDT_SHIFT) /* 79,872 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_156KCYC (0x03 << ADC_STBRR_WDT_SHIFT) /* 159,744 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_391KCYC (0x04 << ADC_STBRR_WDT_SHIFT) /* 400,384 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_781KCYC (0x05 << ADC_STBRR_WDT_SHIFT) /* 799,744 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_1562KCYC (0x06 << ADC_STBRR_WDT_SHIFT) /* 1,599,488 Conversion Clock Cycles */
+# define ADC_STBRR_WDT_3906KCYC (0x07 << ADC_STBRR_WDT_SHIFT) /* 3,999,744 Conversion Clock Cycles */
+
+ /* Bits 19-31: Reserved */
+
+/* Self-Test Status Register 1 (STSR1) */
+
+ /* Bits 0-4: Reserved */
+#define ADC_STSR1_STEP_C_SHIFT (5) /* Bits 5-9: Step Of Algorithm C (STEP_C) */
+#define ADC_STSR1_STEP_C_MASK (0x1f << ADC_STSR1_STEP_C_SHIFT)
+ /* Bit 10: Reserved */
+#define ADC_STSR1_ERR_S0 (1 << 11) /* Bit 11: Error Algorithm S Step 0 (ERR_S0) */
+#define ADC_STSR1_ERR_S1 (1 << 12) /* Bit 12: Error Algorithm S Step 1 (ERR_S1) */
+#define ADC_STSR1_ERR_S2 (1 << 13) /* Bit 13: Error Algorithm S Step 2 (ERR_S2) */
+ /* Bit 14: Reserved */
+#define ADC_STSR1_ERR_C (1 << 15) /* Bit 15: Error Algorithm C (ERR_C) */
+#define ADC_STSR1_WDG_EOA_S (1 << 16) /* Bit 16: Self-Test Watchdog End Of Algorithm S (WDG_EOA_S) */
+ /* Bit 17: Reserved */
+#define ADC_STSR1_WDG_EOA_C (1 << 18) /* Bit 18: Self-Test Watchdog End Of Algorithm C (WDG_EOA_C) */
+ /* Bit 19-22: Reserved */
+#define ADC_STSR1_ST_EOC (1 << 23) /* Bit 23: Self-Test End Of Conversion (ST_EOC) */
+#define ADC_STSR1_OVERWR (1 << 24) /* Bit 24: Self-Test Error Status Overwrite (OVERWR) */
+#define ADC_STSR1_WDTERR (1 << 25) /* Bit 25: Self-Test Watchdog Timer Error (WDTERR) */
+ /* Bit 26: Reserved */
+#define ADC_STSR1_WDSERR (1 << 27) /* Bit 27: Self-Test Watchdog Sequence Error (WDSERR) */
+ /* Bit 28-31: Reserved */
+
+/* Self-Test Status Register 2 (STSR2) */
+
+#define ADC_STSR2_DATA0_SHIFT (0) /* Bits 0-14: Conversion Data ERR_S1 (DATA0) */
+#define ADC_STSR2_DATA0_MASK (0x7fff << ADC_STSR2_DATA0_SHIFT)
+ /* Bits 15-31: Reserved */
+
+/* Self-Test Status Register 3 (STSR3) */
+
+#define ADC_STSR3_DATA0_SHIFT (0) /* Bits 0-14: Conversion Data ERR_S0 (DATA0) */
+#define ADC_STSR3_DATA0_MASK (0x7fff << ADC_STSR3_DATA0_SHIFT)
+ /* Bit 15: Reserved */
+#define ADC_STSR3_DATA1_SHIFT (16) /* Bits 16-30: Conversion Data ERR_S2 (DATA1) */
+#define ADC_STSR3_DATA1_MASK (0x7fff << ADC_STSR3_DATA1_SHIFT)
+ /* Bit 31: Reserved */
+
+/* Self-Test Status Register 4 (STSR4) */
+
+ /* Bits 0-15: Reserved */
+#define ADC_STSR4_DATA1_SHIFT (16) /* Bits 16-30: Conversion Data ERR_C (DATA1) */
+#define ADC_STSR4_DATA1_MASK (0x7fff << ADC_STSR4_DATA1_SHIFT)
+ /* Bit 31: Reserved */
+
+/* Self-Test Conversion Data Register 1 (STDR1) */
+
+#define ADC_STDR1_TCDATA_SHIFT (0) /* Bits 0-14: Test Channel Conversion Data (TCDATA) */
+#define ADC_STDR1_TCDATA_MASK (0x7fff << ADC_STDR1_TCDATA_SHIFT)
+ /* Bits 15-17: Reserved */
+#define ADC_STDR1_OVERWR (1 << 18) /* Bit 18: Conversion Data Overwrite Status (OVERWR) */
+#define ADC_STDR1_VALID (1 << 19) /* Bit 19: Valid Conversion Data (VALID) */
+ /* Bits 20-31: Reserved */
+
+/* Self-Test Analog Watchdog S0 Register (STAW0R) */
+
+#define ADC_STAW0R_THRL_SHIFT (0) /* Bits 0-14: Lower Threshold Value (THRL) */
+#define ADC_STAW0R_THRL_MASK (0x7fff << ADC_STAW0R_THRL_SHIFT)
+ /* Bit 15: Reserved */
+#define ADC_STAW0R_THRH_SHIFT (16) /* Bits 16-29: Higher Threshold Value (THRH) */
+#define ADC_STAW0R_THRH_MASK (0x3fff << ADC_STAW0R_THRH_SHIFT)
+#define ADC_STAW0R_WDTE (1 << 30) /* Bit 30: Self-Test Watchdog Timer Enable (WDTE) */
+#define ADC_STAW0R_AWDE (1 << 31) /* Bit 31: Self-Test Watchdog Enable (AWDE) */
+
+/* Self-Test Analog Watchdog S1 Register (STAW1R) */
+
+#define ADC_STAW1R_THRL_SHIFT (0) /* Bits 0-14: Lower Threshold Value (THRL) */
+#define ADC_STAW1R_THRL_MASK (0x7fff << ADC_STAW1R_THRL_SHIFT)
+ /* Bits 15-30: Reserved */
+#define ADC_STAW1R_AWDE (1 << 31) /* Bit 31: Self-Test Watchdog Enable (AWDE) */
+
+/* Self-Test Analog Watchdog S2 Register (STAW2R) */
+
+#define ADC_STAW2R_THRL_SHIFT (0) /* Bits 0-14: Lower Threshold Value (THRL) */
+#define ADC_STAW2R_THRL_MASK (0x7fff << ADC_STAW2R_THRL_SHIFT)
+ /* Bits 15-30: Reserved */
+#define ADC_STAW2R_AWDE (1 << 31) /* Bit 31: Self-Test Watchdog Enable (AWDE) */
+
+/* Self-Test Analog Watchdog C0 Register (STAW4R) */
+
+#define ADC_STAW4R_THRL_SHIFT (0) /* Bits 0-14: Lower Threshold Value (THRL) */
+#define ADC_STAW4R_THRL_MASK (0x7fff << ADC_STAW4R_THRL_SHIFT)
+ /* Bit 15: Reserved */
+#define ADC_STAW4R_THRH_SHIFT (16) /* Bits 16-29: Higher Threshold Value (THRH) */
+#define ADC_STAW4R_THRH_MASK (0x3fff << ADC_STAW4R_THRH_SHIFT)
+#define ADC_STAW4R_WDTE (1 << 30) /* Bit 30: Self-Test Watchdog Timer Enable (WDTE) */
+#define ADC_STAW4R_AWDE (1 << 31) /* Bit 31: Self-Test Watchdog Enable (AWDE) */
+
+/* Self-Test Analog Watchdog C Register (STAW5R) */
+
+#define ADC_STAW5R_THRL_SHIFT (0) /* Bits 0-14: Lower Threshold Value (THRL) */
+#define ADC_STAW5R_THRL_MASK (0x7fff << ADC_STAW5R_THRL_SHIFT)
+ /* Bit 15: Reserved */
+#define ADC_STAW5R_THRH_SHIFT (16) /* Bits 16-30: Higher Threshold Value (THRH) */
+#define ADC_STAW5R_THRH_MASK (0x7fff << ADC_STAW5R_THRH_SHIFT)
+ /* Bit 31: Reserved */
+
+/* Analog Miscellaneous In/Out Register (AMSIO) */
+
+ /* Bits 0-16: Reserved */
+#define ADC_AMSIO_HSEN_SHIFT (17) /* Bits 17-18: High-Speed Enable (HSEN) */
+#define ADC_AMSIO_HSEN_MASK (0x03 << ADC_AMSIO_HSEN_SHIFT)
+# define ADC_AMSIO_HSEN_NS (0x00 << ADC_AMSIO_HSEN_SHIFT) /* Normal Conversion Speed */
+# define ADC_AMSIO_HSEN_HS (0x03 << ADC_AMSIO_HSEN_SHIFT) /* High-Speed Conversion */
+
+ /* Bits 19-31: Reserved */
+
+/* Control and Calibration Status Register (CALBISTREG) */
+
+#define ADC_CALBISTREG_TEST_EN (1 << 0) /* Bit 0: Calibration Enable (TEST_EN) */
+ /* Bits 1-2: Reserved */
+#define ADC_CALBISTREG_TEST_FAIL (1 << 3) /* Bit 3: Calibration Status (TEST_FAIL) */
+#define ADC_CALBISTREG_AVG_EN (1 << 4) /* Bit 4: Calibration Averaging Enable (AVG_EN) */
+#define ADC_CALBISTREG_NR_SMPL_SHIFT (5) /* Bits 5-6: Calibration Averaging Number (NR_SMPL) */
+#define ADC_CALBISTREG_NR_SMPL_MASK (0x03 << ADC_CALBISTREG_NR_SMPL_SHIFT)
+# define ADC_CALBISTREG_NR_SMPL_4SMPL (0x00 << ADC_CALBISTREG_NR_SMPL_SHIFT) /* 4 Samples */
+# define ADC_CALBISTREG_NR_SMPL_8SMPL (0x01 << ADC_CALBISTREG_NR_SMPL_SHIFT) /* 8 Samples */
+# define ADC_CALBISTREG_NR_SMPL_16SMPL (0x02 << ADC_CALBISTREG_NR_SMPL_SHIFT) /* 16 Samples */
+# define ADC_CALBISTREG_NR_SMPL_32SMPL (0x03 << ADC_CALBISTREG_NR_SMPL_SHIFT) /* 32 Samples */
+
+ /* Bits 7-13: Reserved */
+#define ADC_CALBISTREG_CALSTFUL (1 << 14) /* Bit 14: Calibration and Self-Test Full Range Comparison (CALSTFUL) */
+#define ADC_CALBISTREG_C_T_BUSY (1 << 15) /* Bit 15: Calibration Busy (C_T_BUSY) */
+ /* Bits 16-26: Reserved */
+#define ADC_CALBISTREG_TSAMP_SHIFT (27) /* Bits 27-28: Sample Period in Calibration (TSAMP) */
+#define ADC_CALBISTREG_TSAMP_MASK (0x03 << ADC_CALBISTREG_TSAMP_SHIFT)
+# define ADC_CALBISTREG_TSAMP_22CYC (0x00 << ADC_CALBISTREG_TSAMP_SHIFT) /* 22 Conversion Clock Cycles */
+# define ADC_CALBISTREG_TSAMP_8CYC (0x01 << ADC_CALBISTREG_TSAMP_SHIFT) /* 8 Conversion Clock Cycles */
+# define ADC_CALBISTREG_TSAMP_16CYC (0x02 << ADC_CALBISTREG_TSAMP_SHIFT) /* 16 Conversion Clock Cycles */
+# define ADC_CALBISTREG_TSAMP_32CYC (0x03 << ADC_CALBISTREG_TSAMP_SHIFT) /* 32 Conversion Clock Cycles */
+
+#define ADC_CALBISTREG_RESN_SHIFT (29) /* Bits 29-31: Conversion Resolution (RESN) */
+#define ADC_CALBISTREG_RESN_MASK (0x07 << ADC_CALBISTREG_RESN_SHIFT)
+# define ADC_CALBISTREG_RESN_14BIT (0x00 << ADC_CALBISTREG_RESN_SHIFT) /* 14-Bit Resolution */
+# define ADC_CALBISTREG_RESN_12BIT (0x01 << ADC_CALBISTREG_RESN_SHIFT) /* 12-Bit Resolution */
+# define ADC_CALBISTREG_RESN_10BIT (0x02 << ADC_CALBISTREG_RESN_SHIFT) /* 10-Bit Resolution */
+# define ADC_CALBISTREG_RESN_8BIT (0x03 << ADC_CALBISTREG_RESN_SHIFT) /* 8-Bit Resolution */
+
+/* Offset and Gain User Register (OFSGNUSR) */
+
+#define ADC_OFSGNUSR_OFFSET_USER_SHIFT (0) /* Bits 0-7: Offset User (OFFSET_USER) */
+#define ADC_OFSGNUSR_OFFSET_USER_MASK (0xff << ADC_OFSGNUSR_OFFSET_USER_SHIFT)
+ /* Bits 8-15: Reserved */
+#define ADC_OFSGNUSR_GAIN_USER_SHIFT (0) /* Bits 16-25: Gain User (GAIN_USER) */
+#define ADC_OFSGNUSR_GAIN_USER_MASK (0x03ff << ADC_OFSGNUSR_GAIN_USER_SHIFT)
+ /* Bits 26-31: Reserved */
+
+/* Calibration Value 2 (CAL2) */
+
+ /* Bits 0-14: Reserved */
+#define ADC_CAL2_ENX (1 << 15) /* Bit 15: Enable X (ENX) */
+ /* Bits 16-31: Reserved */
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_ADC_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h
new file mode 100644
index 0000000000..9d93c00d06
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h
@@ -0,0 +1,117 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_axbs.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_AXBS_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_AXBS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* AXBS Register Offsets ****************************************************/
+
+#define S32K3XX_AXBS_PRS0_OFFSET (0x0000) /* Priority Slave Register 0 (PRS0) */
+#define S32K3XX_AXBS_CRS0_OFFSET (0x0010) /* Control Register 0 (CRS0) */
+#define S32K3XX_AXBS_PRS1_OFFSET (0x0100) /* Priority Slave Register 1 (PRS1) */
+#define S32K3XX_AXBS_CRS1_OFFSET (0x0110) /* Control Register 1 (CRS1) */
+#define S32K3XX_AXBS_PRS2_OFFSET (0x0200) /* Priority Slave Register 2 (PRS2) */
+#define S32K3XX_AXBS_CRS2_OFFSET (0x0210) /* Control Register 2 (CRS2) */
+#define S32K3XX_AXBS_PRS3_OFFSET (0x0300) /* Priority Slave Register 3 (PRS3) */
+#define S32K3XX_AXBS_CRS3_OFFSET (0x0310) /* Control Register 3 (CRS3) */
+#define S32K3XX_AXBS_PRS4_OFFSET (0x0400) /* Priority Slave Register 4 (PRS4) */
+#define S32K3XX_AXBS_CRS4_OFFSET (0x0410) /* Control Register 4 (CRS4) */
+#define S32K3XX_AXBS_PRS5_OFFSET (0x0500) /* Priority Slave Register 5 (PRS5) */
+#define S32K3XX_AXBS_CRS5_OFFSET (0x0510) /* Control Register 5 (CRS5) */
+#define S32K3XX_AXBS_PRS6_OFFSET (0x0600) /* Priority Slave Register 6 (PRS6) */
+#define S32K3XX_AXBS_CRS6_OFFSET (0x0610) /* Control Register 6 (CRS6) */
+
+/* AXBS Register Addresses **************************************************/
+
+#define S32K3XX_AXBS_PRS0 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS0_OFFSET)
+#define S32K3XX_AXBS_CRS0 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS0_OFFSET)
+#define S32K3XX_AXBS_PRS1 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS1_OFFSET)
+#define S32K3XX_AXBS_CRS1 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS1_OFFSET)
+#define S32K3XX_AXBS_PRS2 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS2_OFFSET)
+#define S32K3XX_AXBS_CRS2 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS2_OFFSET)
+#define S32K3XX_AXBS_PRS3 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS3_OFFSET)
+#define S32K3XX_AXBS_CRS3 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS3_OFFSET)
+#define S32K3XX_AXBS_PRS4 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS4_OFFSET)
+#define S32K3XX_AXBS_CRS4 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS4_OFFSET)
+#define S32K3XX_AXBS_PRS5 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS5_OFFSET)
+#define S32K3XX_AXBS_CRS5 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS5_OFFSET)
+#define S32K3XX_AXBS_PRS6 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_PRS6_OFFSET)
+#define S32K3XX_AXBS_CRS6 (S32K3XX_AXBS_BASE + S32K3XX_AXBS_CRS6_OFFSET)
+
+/* AXBS Register Bitfield Definitions ***************************************/
+
+/* Priority Slave Register n (PRSn) */
+
+#define AXBS_PRS_M0_SHIFT (0) /* Bit 0-2: Master 0 Priority (M0) */
+#define AXBS_PRS_M0_MASK (0x07 << AXBS_PRS_M0_SHIFT)
+ /* Bit 3: Reserved */
+#define AXBS_PRS_M1_SHIFT (4) /* Bit 4-6: Master 1 Priority (M1) */
+#define AXBS_PRS_M1_MASK (0x07 << AXBS_PRS_M1_SHIFT)
+ /* Bit 7: Reserved */
+#define AXBS_PRS_M2_SHIFT (8) /* Bit 8-10: Master 2 Priority (M2) */
+#define AXBS_PRS_M2_MASK (0x07 << AXBS_PRS_M2_SHIFT)
+ /* Bit 11: Reserved */
+#define AXBS_PRS_M3_SHIFT (12) /* Bit 12-14: Master 3 Priority (M3) */
+#define AXBS_PRS_M3_MASK (0x07 << AXBS_PRS_M3_SHIFT)
+ /* Bit 15: Reserved */
+#define AXBS_PRS_M4_SHIFT (16) /* Bit 16-18: Master 4 Priority (M4) */
+#define AXBS_PRS_M4_MASK (0x07 << AXBS_PRS_M4_SHIFT)
+ /* Bits 19-31: Reserved */
+
+/* Control Register n (CRSn) */
+
+#define AXBS_CRS_PARK_SHIFT (0) /* Bits 0-2: Determines which master port the slave parks on when (PARK) */
+#define AXBS_CRS_PARK_MASK (0x07 << AXBS_CRS_PARK_SHIFT)
+ /* Bit 3: Reserved */
+#define AXBS_CRS_PCTL_SHIFT (4) /* Bits 4-5: Parking Control (PCTL) */
+#define AXBS_CRS_PCTL_MASK (0x03 << AXBS_CRS_PCTL_SHIFT)
+# define AXBS_CRS_PCTL_PARK (0x00 << AXBS_CRS_PCTL_SHIFT) /* Slave port parks on the master port defined by the PARK bit field */
+# define AXBS_CRS_PCTL_LAST (0x01 << AXBS_CRS_PCTL_SHIFT) /* Slave port parks on the last master port in control */
+# define AXBS_CRS_PCTL_LPOW (0x02 << AXBS_CRS_PCTL_SHIFT) /* Low-power park */
+
+ /* Bits 7-6: Reserved */
+#define AXBS_CRS_ARB_SHIFT (8) /* Bits 8-9: Arbitration Mode (ARB) */
+#define AXBS_CRS_ARB_MASK (0x03 << AXBS_CRS_ARB_SHIFT)
+# define AXBS_CRS_ARB_FIX (0x00 << AXBS_CRS_ARB_SHIFT) /* Fixed priority */
+# define AXBS_CRS_ARB_RR (0x01 << AXBS_CRS_ARB_SHIFT) /* Round-robin (rotating) priority */
+
+ /* Bits 10-15: Reserved */
+#define AXBS_CRS_HPE0 (1 << 16) /* Bit 16: High Priority Elevation 0 (HPE0) */
+#define AXBS_CRS_HPE1 (1 << 17) /* Bit 17: High Priority Elevation 1 (HPE1) */
+#define AXBS_CRS_HPE2 (1 << 18) /* Bit 18: High Priority Elevation 2 (HPE2) */
+#define AXBS_CRS_HPE3 (1 << 19) /* Bit 19: High Priority Elevation 3 (HPE3) */
+#define AXBS_CRS_HPE4 (1 << 20) /* Bit 20: High Priority Elevation 4 (HPE4) */
+ /* Bits 21-29: Reserved */
+#define AXBS_CRS_HLP (1 << 30) /* Bit 30: Halt Low Priority (HLP) */
+#define AXBS_CRS_RO (1 << 31) /* Bit 31: Read Only (RO) */
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_AXBS_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h
new file mode 100644
index 0000000000..b4ee821a4c
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h
@@ -0,0 +1,912 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_dcm.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DCM_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DCM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* DCM Register Offsets *****************************************************/
+
+#define S32K3XX_DCM_DCMSTAT_OFFSET (0x0000) /* DCM Status (DCMSTAT) */
+#define S32K3XX_DCM_DCMLCC_OFFSET (0x0004) /* LC and LC Control (DCMLCC) */
+#define S32K3XX_DCM_DCMLCS_OFFSET (0x0008) /* LC Scan Status (DCMLCS) */
+#define S32K3XX_DCM_DCMMISC_OFFSET (0x001c) /* DCM Miscellaneous (DCMMISC) */
+#define S32K3XX_DCM_DCMDEB_OFFSET (0x0020) /* Debug Status and Configuration (DCMDEB) */
+#define S32K3XX_DCM_DCMEC_OFFSET (0x002c) /* DCF Error Count (DCMEC) */
+#define S32K3XX_DCM_DCMSRR1_OFFSET (0x0030) /* DCF Scan Report 1 (DCMSRR1) */
+#define S32K3XX_DCM_DCMSRR2_OFFSET (0x0034) /* DCF Scan Report 2 (DCMSRR2) */
+#define S32K3XX_DCM_DCMSRR3_OFFSET (0x0038) /* DCF Scan Report 3 (DCMSRR3) */
+#define S32K3XX_DCM_DCMSRR4_OFFSET (0x003c) /* DCF Scan Report 4 (DCMSRR4) */
+#define S32K3XX_DCM_DCMSRR5_OFFSET (0x0040) /* DCF Scan Report 5 (DCMSRR5) */
+#define S32K3XX_DCM_DCMSRR6_OFFSET (0x0044) /* DCF Scan Report 6 (DCMSRR6) */
+#define S32K3XX_DCM_DCMSRR7_OFFSET (0x0048) /* DCF Scan Report 7 (DCMSRR7) */
+#define S32K3XX_DCM_DCMSRR8_OFFSET (0x004c) /* DCF Scan Report 8 (DCMSRR8) */
+#define S32K3XX_DCM_DCMSRR9_OFFSET (0x0050) /* DCF Scan Report 9 (DCMSRR9) */
+#define S32K3XX_DCM_DCMSRR10_OFFSET (0x0054) /* DCF Scan Report 10 (DCMSRR10) */
+#define S32K3XX_DCM_DCMSRR11_OFFSET (0x0058) /* DCF Scan Report 11 (DCMSRR11) */
+#define S32K3XX_DCM_DCMSRR12_OFFSET (0x005c) /* DCF Scan Report 12 (DCMSRR12) */
+#define S32K3XX_DCM_DCMSRR13_OFFSET (0x0060) /* DCF Scan Report 13 (DCMSRR13) */
+#define S32K3XX_DCM_DCMSRR14_OFFSET (0x0064) /* DCF Scan Report 14 (DCMSRR14) */
+#define S32K3XX_DCM_DCMSRR15_OFFSET (0x0068) /* DCF Scan Report 15 (DCMSRR15) */
+#define S32K3XX_DCM_DCMSRR16_OFFSET (0x006c) /* DCF Scan Report 16 (DCMSRR16) */
+#define S32K3XX_DCM_DCMLCS2_OFFSET (0x0080) /* LC Scan Status 2 (DCMLCS2) */
+#define S32K3XX_DCM_GPR_DCMROD1_OFFSET (0x0200) /* Read Only GPR On Destructive Reset Register 1 (DCMROD1) */
+#define S32K3XX_DCM_GPR_DCMROD3_OFFSET (0x0208) /* Read Only GPR On Destructive Reset Register 3 (DCMROD3) */
+#define S32K3XX_DCM_GPR_DCMROD4_OFFSET (0x020c) /* Read Only GPR On Destructive Reset Register 4 (DCMROD4) */
+#define S32K3XX_DCM_GPR_DCMROD5_OFFSET (0x0210) /* Read Only GPR On Destructive Reset Register 5 (DCMROD5) */
+#define S32K3XX_DCM_GPR_DCMROF1_OFFSET (0x0300) /* Read Only GPR On Functional Reset Register 1 (DCMROF1) */
+#define S32K3XX_DCM_GPR_DCMROF2_OFFSET (0x0304) /* Read Only GPR On Functional Reset Register 2 (DCMROF2) */
+#define S32K3XX_DCM_GPR_DCMROF3_OFFSET (0x0308) /* Read Only GPR On Functional Reset Register 3 (DCMROF3) */
+#define S32K3XX_DCM_GPR_DCMROF4_OFFSET (0x030c) /* Read Only GPR On Functional Reset Register 4 (DCMROF4) */
+#define S32K3XX_DCM_GPR_DCMROF5_OFFSET (0x0310) /* Read Only GPR On Functional Reset Register 5 (DCMROF5) */
+#define S32K3XX_DCM_GPR_DCMROF6_OFFSET (0x0314) /* Read Only GPR On Functional Reset Register 6 (DCMROF6) */
+#define S32K3XX_DCM_GPR_DCMROF7_OFFSET (0x0318) /* Read Only GPR On Functional Reset Register 7 (DCMROF7) */
+#define S32K3XX_DCM_GPR_DCMROF8_OFFSET (0x031c) /* Read Only GPR On Functional Reset Register 8 (DCMROF8) */
+#define S32K3XX_DCM_GPR_DCMROF9_OFFSET (0x0320) /* Read Only GPR On Functional Reset Register 9 (DCMROF9) */
+#define S32K3XX_DCM_GPR_DCMROF10_OFFSET (0x0324) /* Read Only GPR On Functional Reset Register 10 (DCMROF10) */
+#define S32K3XX_DCM_GPR_DCMROF11_OFFSET (0x0328) /* Read Only GPR On Functional Reset Register 11 (DCMROF11) */
+#define S32K3XX_DCM_GPR_DCMROF12_OFFSET (0x032c) /* Read Only GPR On Functional Reset Register 12 (DCMROF12) */
+#define S32K3XX_DCM_GPR_DCMROF13_OFFSET (0x0330) /* Read Only GPR On Functional Reset Register 13 (DCMROF13) */
+#define S32K3XX_DCM_GPR_DCMROF14_OFFSET (0x0334) /* Read Only GPR On Functional Reset Register 14 (DCMROF14) */
+#define S32K3XX_DCM_GPR_DCMROF15_OFFSET (0x0338) /* Read Only GPR On Functional Reset Register 15 (DCMROF15) */
+#define S32K3XX_DCM_GPR_DCMROF16_OFFSET (0x033c) /* Read Only GPR On Functional Reset Register 16 (DCMROF16) */
+#define S32K3XX_DCM_GPR_DCMROF17_OFFSET (0x0340) /* Read Only GPR On Functional Reset Register 17 (DCMROF17) */
+#define S32K3XX_DCM_GPR_DCMROF19_OFFSET (0x0348) /* Read Only GPR On Functional Reset Register 19 (DCMROF19) */
+#define S32K3XX_DCM_GPR_DCMROF20_OFFSET (0x034c) /* Read Only GPR On Functional Reset Register 20 (DCMROF20) */
+#define S32K3XX_DCM_GPR_DCMROF21_OFFSET (0x0350) /* Read Only GPR On Functional Reset Register 21 (DCMROF21) */
+#define S32K3XX_DCM_GPR_DCMRWP1_OFFSET (0x0400) /* Read Write GPR On Power On Reset Register 1 (DCMRWP1) */
+#define S32K3XX_DCM_GPR_DCMRWP3_OFFSET (0x0408) /* Read Write GPR On Power On Reset Register 3 (DCMRWP3) */
+#define S32K3XX_DCM_GPR_DCMRWD2_OFFSET (0x0504) /* Read Write GPR On Destructive Reset Register 2 (DCMRWD2) */
+#define S32K3XX_DCM_GPR_DCMRWD3_OFFSET (0x0508) /* Read Write GPR On Destructive Reset Register 3 (DCMRWD3) */
+#define S32K3XX_DCM_GPR_DCMRWD4_OFFSET (0x050c) /* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */
+#define S32K3XX_DCM_GPR_DCMRWD5_OFFSET (0x0510) /* Read Write GPR On Destructive Reset Register 5 (DCMRWD5) */
+#define S32K3XX_DCM_GPR_DCMRWD6_OFFSET (0x0514) /* Read Write GPR On Destructive Reset Register 6 (DCMRWD6) */
+#define S32K3XX_DCM_GPR_DCMRWD7_OFFSET (0x0518) /* Read Write GPR On Destructive Reset Register 7 (DCMRWD7) */
+#define S32K3XX_DCM_GPR_DCMRWD8_OFFSET (0x051c) /* Read Write GPR On Destructive Reset Register 8 (DCMRWD8) */
+#define S32K3XX_DCM_GPR_DCMRWD9_OFFSET (0x0520) /* Read Write GPR On Destructive Reset Register 9 (DCMRWD9) */
+#define S32K3XX_DCM_GPR_DCMRWF1_OFFSET (0x0600) /* Read Write GPR On Functional Reset Register 1 (DCMRWF1) */
+#define S32K3XX_DCM_GPR_DCMRWF2_OFFSET (0x0604) /* Read Write GPR On Functional Reset Register 2 (DCMRWF2) */
+#define S32K3XX_DCM_GPR_DCMRWF4_OFFSET (0x060c) /* Read Write GPR On Functional Reset Register 4 (DCMRWF4) */
+#define S32K3XX_DCM_GPR_DCMRWF5_OFFSET (0x0610) /* Read Write GPR On Functional Reset Register 5 (DCMRWF5) */
+#define S32K3XX_DCM_GPR_DCMROPP1_OFFSET (0x0700) /* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */
+#define S32K3XX_DCM_GPR_DCMROPP2_OFFSET (0x0704) /* Read Only GPR On PMCPOR Reset Register 2 (DCMROPP2) */
+#define S32K3XX_DCM_GPR_DCMROPP3_OFFSET (0x0708) /* Read Only GPR On PMCPOR Reset Register 3 (DCMROPP3) */
+#define S32K3XX_DCM_GPR_DCMROPP4_OFFSET (0x070c) /* Read Only GPR On PMCPOR Reset Register 4 (DCMROPP4) */
+
+/* DCM Register Addresses ***************************************************/
+
+#define S32K3XX_DCM_DCMSTAT (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSTAT_OFFSET)
+#define S32K3XX_DCM_DCMLCC (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMLCC_OFFSET)
+#define S32K3XX_DCM_DCMLCS (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMLCS_OFFSET)
+#define S32K3XX_DCM_DCMMISC (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMMISC_OFFSET)
+#define S32K3XX_DCM_DCMDEB (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMDEB_OFFSET)
+#define S32K3XX_DCM_DCMEC (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMEC_OFFSET)
+#define S32K3XX_DCM_DCMSRR1 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR1_OFFSET)
+#define S32K3XX_DCM_DCMSRR2 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR2_OFFSET)
+#define S32K3XX_DCM_DCMSRR3 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR3_OFFSET)
+#define S32K3XX_DCM_DCMSRR4 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR4_OFFSET)
+#define S32K3XX_DCM_DCMSRR5 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR5_OFFSET)
+#define S32K3XX_DCM_DCMSRR6 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR6_OFFSET)
+#define S32K3XX_DCM_DCMSRR7 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR7_OFFSET)
+#define S32K3XX_DCM_DCMSRR8 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR8_OFFSET)
+#define S32K3XX_DCM_DCMSRR9 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR9_OFFSET)
+#define S32K3XX_DCM_DCMSRR10 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR10_OFFSET)
+#define S32K3XX_DCM_DCMSRR11 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR11_OFFSET)
+#define S32K3XX_DCM_DCMSRR12 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR12_OFFSET)
+#define S32K3XX_DCM_DCMSRR13 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR13_OFFSET)
+#define S32K3XX_DCM_DCMSRR14 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR14_OFFSET)
+#define S32K3XX_DCM_DCMSRR15 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR15_OFFSET)
+#define S32K3XX_DCM_DCMSRR16 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMSRR16_OFFSET)
+#define S32K3XX_DCM_DCMLCS2 (S32K3XX_DCM_BASE + S32K3XX_DCM_DCMLCS2_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROD1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD1_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROD3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD3_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROD4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD4_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROD5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROD5_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF1_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF2_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF3_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF4_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF5_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF6 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF6_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF7 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF7_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF8 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF8_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF9 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF9_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF10 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF10_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF11 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF11_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF12 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF12_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF13 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF13_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF14 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF14_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF15 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF15_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF16 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF16_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF17 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF17_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF19 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF19_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF20 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF20_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROF21 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROF21_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWP1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWP1_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWP3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWP3_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD2_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD3_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD4_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD5_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD6 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD6_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD7 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD7_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD8 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD8_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWD9 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWD9_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWF1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF1_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWF2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF2_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWF4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF4_OFFSET)
+#define S32K3XX_DCM_GPR_DCMRWF5 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMRWF5_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROPP1 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP1_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROPP2 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP2_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROPP3 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP3_OFFSET)
+#define S32K3XX_DCM_GPR_DCMROPP4 (S32K3XX_DCM_BASE + S32K3XX_DCM_GPR_DCMROPP4_OFFSET)
+
+/* DCM Register Bitfield Definitions ****************************************/
+
+/* DCM Status (DCMSTAT) */
+
+#define DCM_DCMSTAT_DCMDONE (1 << 0) /* Bit 0: DCM Scanning Status (DCMDONE) */
+#define DCM_DCMSTAT_DCMERR (1 << 1) /* Bit 1: DCM completion with error status (DCMERR) */
+ /* Bits 2-3: Reserved */
+#define DCM_DCMSTAT_DCMLCST (1 << 4) /* Bit 4: LC Scanning Status (DCMLCST) */
+ /* Bits 5-7: Reserved */
+#define DCM_DCMSTAT_DCMUTS (1 << 8) /* Bit 8: DCM UTEST DCF Scanning Status (DCMUTS) */
+#define DCM_DCMSTAT_DCMOTAS (1 << 9) /* Bit 9: DCM OTA Scanning Status (DCMOTAS) */
+#define DCM_DCMSTAT_DCMDBGPS (1 << 10) /* Bit 10: Debug Password Scanning Status (DCMDBGPS) */
+ /* Bits 11-31: Reserved */
+
+/* LC and LC Control (DCMLCC) */
+
+#define DCM_DCMLCC_DCMCLC_SHIFT (0) /* Bits 0-2: Current LC (DCMCLC) */
+#define DCM_DCMLCC_DCMCLC_MASK (0x07 << DCM_DCMLCC_DCMCLC_SHIFT)
+#define DCM_DCMLCC_DCMLCFN (1 << 3) /* Bit 3: Force LC (DCMLCFN) */
+#define DCM_DCMLCC_DCMRLC_SHIFT (0) /* Bits 4-6: Real LC (DCMRLC) */
+#define DCM_DCMLCC_DCMRLC_MASK (0x07 << DCM_DCMLCC_DCMRLC_SHIFT)
+ /* Bit 7: Reserved */
+#define DCM_DCMLCC_DCMFLC_SHIFT (8) /* Bits 8-9: Force Next LC (DCMFLC) */
+#define DCM_DCMLCC_DCMFLC_MASK (0x03 << DCM_DCMLCC_DCMFLC_SHIFT)
+ /* Bits 10-31: Reserved */
+
+/* LC Scan Status (DCMLCS) */
+
+#define DCM_DCMLCS_DCMLCSS1 (1 << 0) /* Bit 0: MCU_PROD Scan Status (DCMLCSS1) */
+#define DCM_DCMLCS_DCMLCC1_SHIFT (1) /* Bits 1-3: MCU_PROD Marking (DCMLCC1) */
+#define DCM_DCMLCS_DCMLCC1_MASK (0x07 << DCM_DCMLCS_DCMLCC1_SHIFT)
+# define DCM_DCMLCS_DCMLCC1_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Not scanned yet */
+# define DCM_DCMLCS_DCMLCC1_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Marked as active */
+# define DCM_DCMLCS_DCMLCC1_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Marked as inactive */
+# define DCM_DCMLCS_DCMLCC1_ERASED (0x03 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Region is erased/virgin */
+# define DCM_DCMLCS_DCMLCC1_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Marked as inactive by an unknown pattern */
+# define DCM_DCMLCS_DCMLCC1_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC1_SHIFT) /* Scanning timed out */
+
+#define DCM_DCMLCS_DCMLCE1 (1 << 4) /* Bit 4: MCU_PROD ECC Errors (DCMLCE1) */
+#define DCM_DCMLCS_DCMLCFE1 (1 << 5) /* Bit 5: MCU_PROD Flash Memory Error Check (DCMLCFE1) */
+#define DCM_DCMLCS_DCMLCSS2 (1 << 6) /* Bit 6: CUST_DEL Scan Status (DCMLCSS2) */
+#define DCM_DCMLCS_DCMLCC2_SHIFT (7) /* Bits 7-9: CUST_DEL Marking (DCMLCC2) */
+#define DCM_DCMLCS_DCMLCC2_MASK (0x07 << DCM_DCMLCS_DCMLCC2_SHIFT)
+# define DCM_DCMLCS_DCMLCC2_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Not scanned yet */
+# define DCM_DCMLCS_DCMLCC2_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Marked as active */
+# define DCM_DCMLCS_DCMLCC2_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Marked as inactive */
+# define DCM_DCMLCS_DCMLCC2_ERASED (0x03 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Region is erased/virgin */
+# define DCM_DCMLCS_DCMLCC2_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Marked as inactive by an unknown pattern */
+# define DCM_DCMLCS_DCMLCC2_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC2_SHIFT) /* Scanning timed out */
+
+#define DCM_DCMLCS_DCMLCE2 (1 << 10) /* Bit 10: CUST_DEL ECC Errors (DCMLCE2) */
+#define DCM_DCMLCS_DCMLCFE2 (1 << 11) /* Bit 11: CUST_DEL Flash Memory Error Check (DCMLCFE2) */
+#define DCM_DCMLCS_DCMLCSS3 (1 << 12) /* Bit 12: OEM_PROD Scan Status (DCMLCSS3) */
+#define DCM_DCMLCS_DCMLCC3_SHIFT (13) /* Bits 13-15: OEM_PROD Marking (DCMLCC3) */
+#define DCM_DCMLCS_DCMLCC3_MASK (0x07 << DCM_DCMLCS_DCMLCC3_SHIFT)
+# define DCM_DCMLCS_DCMLCC3_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Not scanned yet */
+# define DCM_DCMLCS_DCMLCC3_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Marked as active */
+# define DCM_DCMLCS_DCMLCC3_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Marked as inactive */
+# define DCM_DCMLCS_DCMLCC3_ERASED (0x03 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Region is erased/virgin */
+# define DCM_DCMLCS_DCMLCC3_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Marked as inactive by an unknown pattern */
+# define DCM_DCMLCS_DCMLCC3_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC3_SHIFT) /* Scanning timed out */
+
+#define DCM_DCMLCS_DCMLCE3 (1 << 16) /* Bit 16: OEM_PROD ECC Errors (DCMLCE3) */
+#define DCM_DCMLCS_DCMLCFE3 (1 << 17) /* Bit 17: OEM_PROD Flash Memory Error Check (DCMLCFE3) */
+#define DCM_DCMLCS_DCMLCSS4 (1 << 18) /* Bit 18: IN_FIELD Scan Status (DCMLCSS4) */
+#define DCM_DCMLCS_DCMLCC4_SHIFT (19) /* Bits 19-21: IN_FIELD Marking (DCMLCC4) */
+#define DCM_DCMLCS_DCMLCC4_MASK (0x07 << DCM_DCMLCS_DCMLCC4_SHIFT)
+# define DCM_DCMLCS_DCMLCC4_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Not scanned yet */
+# define DCM_DCMLCS_DCMLCC4_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Marked as active */
+# define DCM_DCMLCS_DCMLCC4_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Marked as inactive */
+# define DCM_DCMLCS_DCMLCC4_ERASED (0x03 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Region is erased/virgin */
+# define DCM_DCMLCS_DCMLCC4_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Marked as inactive by an unknown pattern */
+# define DCM_DCMLCS_DCMLCC4_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC4_SHIFT) /* Scanning timed out */
+
+#define DCM_DCMLCS_DCMLCE4 (1 << 22) /* Bit 22: IN_FIELD ECC Errors (DCMLCE4) */
+#define DCM_DCMLCS_DCMLCFE4 (1 << 23) /* Bit 23: IN_FIELD Flash Memory Error Check (DCMLCFE4) */
+#define DCM_DCMLCS_DCMLCSS5 (1 << 24) /* Bit 24: Pre-FA Scan Status (DCMLCSS5) */
+#define DCM_DCMLCS_DCMLCC5_SHIFT (25) /* Bits 25-27: Pre-FA Marking (DCMLCC5) */
+#define DCM_DCMLCS_DCMLCC5_MASK (0x07 << DCM_DCMLCS_DCMLCC5_SHIFT)
+# define DCM_DCMLCS_DCMLCC5_NOSCAN (0x00 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Not scanned yet */
+# define DCM_DCMLCS_DCMLCC5_ACTIVE (0x01 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Marked as active */
+# define DCM_DCMLCS_DCMLCC5_INACTIVE (0x02 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Marked as inactive */
+# define DCM_DCMLCS_DCMLCC5_ERASED (0x03 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Region is erased/virgin */
+# define DCM_DCMLCS_DCMLCC5_UNKNOWN (0x05 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Marked as inactive by an unknown pattern */
+# define DCM_DCMLCS_DCMLCC5_TIMEOUT (0x06 << DCM_DCMLCS_DCMLCC5_SHIFT) /* Scanning timed out */
+
+#define DCM_DCMLCS_DCMLCE5 (1 << 28) /* Bit 28: Pre-FA ECC Errors (DCMLCE5) */
+#define DCM_DCMLCS_DCMLCFE5 (1 << 29) /* Bit 29: Pre-FA Flash Memory Error Check (DCMLCFE5) */
+ /* Bits 30-31: Reserved */
+
+/* DCM Miscellaneous (DCMMISC) */
+
+ /* Bits 0-9: Reserved */
+#define DCM_DCMMISC_DCMDBGT (1 << 10) /* Bit 10: DBG Section Error (DCMDBGT) */
+#define DCM_DCMMISC_DCMDBGE (1 << 11) /* Bit 11: DCM ECC error on DBG sections (DCMDBGE) */
+ /* Bits 12-27: Reserved */
+#define DCM_DCMMISC_DCMCERS (1 << 28) /* Bits 28: DCF Client Errors (DCMCERS) */
+ /* Bit 29: Reserved */
+#define DCM_DCMMISC_MRKLSTRCHK (1 << 30) /* Bit 30: MRK Local Storage Check (MRKLSTRCHK) */
+ /* Bit 31: Reserved */
+
+/* Debug Status and Configuration (DCMDEB) */
+
+ /* Bit 0: Reserved */
+#define DCM_DCMDEB_DCM_APPDBG_STAT (1 << 1) /* Bit 1: DCM Authentication Engine Status (DCM_APPDBG_STAT) */
+ /* Bits 2-15: Reserved */
+#define DCM_DCMDEB_APPDBG_STAT_SOC (1 << 16) /* Bit 16: Application Debug Status (APPDBG_STAT_SOC) */
+ /* Bits 17-31: Reserved */
+
+/* DCF Error Count (DCMEC) */
+
+#define DCM_DCMEC_DCMECT_SHIFT (0) /* Bits 0-15: Error Count (DCMECT) */
+#define DCM_DCMEC_DCMECT_MASK (0xffff << DCM_DCMEC_DCMECT_SHIFT)
+ /* Bits 16-31: Reserved */
+
+/* DCF Scan Report (DCMSRRn) */
+
+#define DCM_DCMSSR_DCMDCFE_SHIFT (0) /* Bits 0-20: Flash Memory Address (DCMDCFE1) */
+#define DCM_DCMSSR_DCMDCFE_MASK (0x1fffff << DCM_DCMSSR1_DCMDCFE1_SHIFT)
+ /* Bits 21-23: Reserved */
+#define DCM_DCMSSR_DCMDCFF_SHIFT (24) /* Bits 24-26: DCF Record Location (DCMDCFF1) */
+#define DCM_DCMSSR_DCMDCFF_MASK (0x1fffff << DCM_DCMSSR1_DCMDCFE1_SHIFT)
+#define DCM_DCMSSR_DCMESF (1 << 27) /* Bit 27: Flash Memory Error (DCMESF1) */
+#define DCM_DCMSSR_DCMESD (1 << 28) /* Bit 28: Chip Side Error (DCMESD1) */
+#define DCM_DCMSSR_DCMDCFT (1 << 29) /* Bit 29: Scanning Timeout On Flash Memory (DCMDCFT1) */
+ /* Bit 30-31: Reserved */
+
+/* LC Scan Status 2 (DCMLCS2) */
+
+#define DCM_DCMLCS2_DCMLCSS6 (1 << 0) /* Bit 0: FA Scan Status (DCMLCSS6) */
+#define DCM_DCMLCS2_DCMLCC6_SHIFT (1) /* Bits 1-3: FA Marking (DCMLCC6) */
+#define DCM_DCMLCS2_DCMLCC6_MASK (0x07 << DCM_DCMLCS2_DCMLCC6_SHIFT)
+# define DCM_DCMLCS2_DCMLCC6_NOSCAN (0x00 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Not scanned yet */
+# define DCM_DCMLCS2_DCMLCC6_ACTIVE (0x01 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Marked as active */
+# define DCM_DCMLCS2_DCMLCC6_INACTIVE (0x02 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Marked as inactive */
+# define DCM_DCMLCS2_DCMLCC6_ERASED (0x03 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Region is erased/virgin */
+# define DCM_DCMLCS2_DCMLCC6_UNKNOWN (0x05 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Marked as inactive by an unknown pattern */
+# define DCM_DCMLCS2_DCMLCC6_TIMEOUT (0x06 << DCM_DCMLCS2_DCMLCC6_SHIFT) /* Scanning timed out */
+
+#define DCM_DCMLCS2_DCMLCE6 (1 << 4) /* Bit 4: FA ECC Errors (DCMLCE6) */
+#define DCM_DCMLCS2_DCMLCFE6 (1 << 5) /* Bit 5: Flash Memory Error Check (DCMLCFE6) */
+ /* Bits 6-31: Reserved */
+
+/* Read Only GPR On Destructive Reset Register 1 (DCMROD1) */
+
+#define DCM_GPR_DCMROD1_PCU_ISO_STATUS (1 << 0) /* Bit 0: PCU Input Isolation status on previous standb entry (PCU_ISO_STATUS) */
+#define DCM_GPR_DCMROD1_HSE_DCF_VIO (1 << 1) /* Bit 1: DCF violation from HSE (HSE_DCF_VIO) */
+#define DCM_GPR_DCMROD1_KEY_RESP_READY (1 << 2) /* Bit 2: Key Response Ready (KEY_RESP_READY) */
+ /* Bits 3-31: Reserved */
+
+/* Read Only GPR On Destructive Reset Register 3 (DCMROD3) */
+
+#define DCM_GPR_DCMROD3_CM7_0_LOCKUP (1 << 0) /* Bit 0: CM7_0 Core Lockup Status (CM7_0_LOCKUP) */
+#define DCM_GPR_DCMROD3_CM7_1_LOCKUP (1 << 1) /* Bit 0: CM7_1 Core Lockup Status (CM7_1_LOCKUP) */
+#define DCM_GPR_DCMROD3_HSE_LOCKUP (1 << 2) /* Bit 2: HSE Core Lockup Status (HSE_LOCKUP) */
+#define DCM_GPR_DCMROD3_CM7_RCCU1_ALARM (1 << 3) /* Bit 3: Cortex M7 Cores Lockstep Error Status (CM7_RCCU1_ALARM) */
+#define DCM_GPR_DCMROD3_CM7_RCCU2_ALARM (1 << 4) /* Bit 4: Cortex M7 Cores Redundant Lockstep Error Status (CM7_RCCU2_ALARM) */
+#define DCM_GPR_DCMROD3_TCM_GSKT_ALARM (1 << 5) /* Bit 5: TCM IAHB Gasket Monitor Alarm Status (TCM_GSKT_ALARM) */
+
+#define DCM_GPR_DCMROD3_DMA_SYS_GSKT_ALARM (1 << 6) /* Bit 6: Status of IAHB gasket safety alarm from DMA system AXBS IAHB gasket (DMA_SYS_GSKT_ALARM) */
+#define DCM_GPR_DCMROD3_DMA_PERIPH_GSKT_ALARM (1 << 7) /* Bit 7: Status of IAHB gasket safety alarm from DMA periph AXBS IAHB gasket (DMA_PERIPH_GSKT_ALARM) */
+
+#define DCM_GPR_DCMROD3_SYS_AXBS_ALARM (1 << 8) /* Bit 8: System AXBS Safety Alarm Status (SYS_AXBS_ALARM) */
+#define DCM_GPR_DCMROD3_DMA_AXBS_ALARM (1 << 9) /* Bit 9: DMA AXBS_Lite Safety Alarm Status (DMA_AXBS_ALARM) */
+ /* Bit 10: Reserved */
+#define DCM_GPR_DCMROD3_HSE_GSKT_ALARM (1 << 11) /* Bit 11: HSE IAHB Gasket Alarm Status (HSE_GSKT_ALARM) */
+#define DCM_GPR_DCMROD3_QSPI_GSKT_ALARM (1 << 12) /* Bit 12: QSPI IAHB Gasket Alarm Status (QSPI_GSKT_ALARM) */
+#define DCM_GPR_DCMROD3_AIPS1_GSKT_ALARM (1 << 13) /* Bit 13: AIPS1 IAHB Gasket Alarm Status (AIPS1_GSKT_ALARM) */
+#define DCM_GPR_DCMROD3_AIPS2_GSKT_ALARM (1 << 14) /* Bit 14: AIPS2 IAHB Gasket Alarm Status (AIPS2_GSKT_ALARM) */
+#define DCM_GPR_DCMROD3_ADDR_EDC_ERR (1 << 15) /* Bit 15: Status of integrity error on addresses for safety (ADDR_EDC_ERR) */
+#define DCM_GPR_DCMROD3_DATA_EDC_ERR (1 << 16) /* Bit 16: Status of integrity error on data for safety (DATA_EDC_ERR) */
+#define DCM_GPR_DCMROD3_TCM_AXBS_ALARM (1 << 17) /* Bit 17: TCM AHB Splitter Safety Alarm Status (TCM_AXBS_ALARM) */
+#define DCM_GPR_DCMROD3_EMAC_GSKT_ALARM (1 << 18) /* Bit 18: EMAC IAHB Gasket Alarm Status (EMAC_GSKT_ALARM) */
+#define DCM_GPR_DCMROD3_PERIPH_AXBS_ALARM (1 << 19) /* Bit 19: PERIPH AXBS_Lite Safety Alarm Status (PERIPH_AXBS_ALARM) */
+ /* Bits 20-21: Reserved */
+#define DCM_GPR_DCMROD3_LC_ERR (1 << 22) /* Bit 22: Error in Lifecycle Scanning (LC_ERR) */
+ /* Bit 23: Reserved */
+#define DCM_GPR_DCMROD3_PRAM1_ECC_ERR (1 << 24) /* Bit 24: Multi bit ECC error from SRAM1 (PRAM1_ECC_ERR) */
+#define DCM_GPR_DCMROD3_PRAM0_ECC_ERR (1 << 25) /* Bit 25: Multi bit ECC error from SRAM0 (PRAM0_ECC_ERR) */
+
+#define DCM_GPR_DCMROD3_CM7_0_DCDATA_ECC_ERR (1 << 26) /* Bit 26: Multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR) */
+#define DCM_GPR_DCMROD3_CM7_1_DCDATA_ECC_ERR (1 << 27) /* Bit 27: Multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR) */
+#define DCM_GPR_DCMROD3_CM7_0_DCTAG_ECC_ERR (1 << 28) /* Bit 28: Multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR) */
+#define DCM_GPR_DCMROD3_CM7_1_DCTAG_ECC_ERR (1 << 29) /* Bit 29: Multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR) */
+#define DCM_GPR_DCMROD3_CM7_0_ICDATA_ECC_ERR (1 << 30) /* Bit 30: Multi bit ECC error from CM7_0 ICache data memory (CM7_0_ICDATA_ECC_ERR) */
+#define DCM_GPR_DCMROD3_CM7_1_ICDATA_ECC_ERR (1 << 31) /* Bit 31: Multi bit ECC error from CM7_1 ICache data memory (CM7_1_ICDATA_ECC_ERR) */
+
+/* Read Only GPR On Destructive Reset Register 4 (DCMROD4) */
+
+#define DCM_GPR_DCMROD4_CM7_0_ICTAG_ECC_ERR (1 << 0) /* Bit 0: Multi bit ECC error from CM7_0 ICache tag memory (CM7_0_ICTAG_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_1_ICTAG_ECC_ERR (1 << 1) /* Bit 1: Multi bit ECC error from CM7_1 ICache tag memory (CM7_1_ICTAG_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_0_ITCM_ECC_ERR (1 << 2) /* Bit 2: Uncorrectable ECC error reported from CM7_0 Instruction TCM memory (CM7_0_ITCM_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_0_DTCM0_ECC_ERR (1 << 3) /* Bit 3: Uncorrectable ECC error reported from CM7_0 Data TCM memory block 0 (CM7_0_DTCM0_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_0_DTCM1_ECC_ERR (1 << 4) /* Bit 4: Uncorrectable ECC error reported from CM7_1 Data TCM memory block 1 (CM7_0_DTCM1_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_1_ITCM_ECC_ERR (1 << 5) /* Bit 5: Uncorrectable ECC error reported from CM7_1 Instruction TCM memory (CM7_1_ITCM_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_1_DTCM0_ECC_ERR (1 << 6) /* Bit 6: Uncorrectable ECC error reported from CM7_1 Data TCM memory block 0 (CM7_1_DTCM0_ECC_ERR) */
+#define DCM_GPR_DCMROD4_CM7_1_DTCM1_ECC_ERR (1 << 7) /* Bit 7: Uncorrectable ECC error reported from CM7_1 Data TCM memory block 1 (CM7_1_DTCM1_ECC_ERR) */
+#define DCM_GPR_DCMROD4_DMA_TCD_RAM_ECC_ERR (1 << 8) /* Bit 8: Uncorrectable ECC error reported from DMA_TCD memory (DMA_TCD_RAM_ECC_ERR) */
+
+#define DCM_GPR_DCMROD4_PRAM0_FCCU_ALARM (1 << 9) /* Bit 9: Status of PRAM0 safety alarm (PRAM0_FCCU_ALARM) */
+#define DCM_GPR_DCMROD4_PRAM1_FCCU_ALARM (1 << 10) /* Bit 10: Status of PRAM1 safety alarm (PRAM1_FCCU_ALARM) */
+#define DCM_GPR_DCMROD4_HSE_RAM_ECC_ERR (1 << 11) /* Bit 11: HSE RAM Uncorrectable ECC status (HSE_RAM_ECC_ERR) */
+#define DCM_GPR_DCMROD4_PF0_CODE_ECC_ERR (1 << 12) /* Bit 12: Flash0 Code ECC Uncorrectable Error (PF0_CODE_ECC_ERR) */
+#define DCM_GPR_DCMROD4_PF0_DATA_ECC_ERR (1 << 13) /* Bit 13: Flash0 Data ECC Uncorrectable Error (PF0_DATA_ECC_ERR) */
+#define DCM_GPR_DCMROD4_PF1_CODE_ECC_ERR (1 << 14) /* Bit 14: Flash1 Code ECC Uncorrectable Error (PF1_CODE_ECC_ERR) */
+#define DCM_GPR_DCMROD4_PF1_DATA_ECC_ERR (1 << 15) /* Bit 15: Flash1 Data ECC Uncorrectable Error (PF1_DATA_ECC_ERR) */
+#define DCM_GPR_DCMROD4_PF2_CODE_ECC_ERR (1 << 16) /* Bit 16: Flash2 Code ECC Uncorrectable Error (PF2_CODE_ECC_ERR) */
+#define DCM_GPR_DCMROD4_PF2_DATA_ECC_ERR (1 << 17) /* Bit 17: Flash2 Data ECC Uncorrectable Error (PF2_DATA_ECC_ERR) */
+#define DCM_GPR_DCMROD4_FLASH_EDC_ERR (1 << 18) /* Bit 18: Status of flash ECC correction error through EDC reported by FMU (FLASH_EDC_ERR) */
+
+#define DCM_GPR_DCMROD4_FLASH_ADDR_ENC_ERR (1 << 19) /* Bit 19: Flash Address Encode Error (FLASH_ADDR_ENC_ERR) */
+
+#define DCM_GPR_DCMROD4_FLASH_REF_ERR (1 << 20) /* Bit 20: Flash reference current loss or read voltage error while previous read(s) (FLASH_REF_ERR) */
+#define DCM_GPR_DCMROD4_FLASH_RST_ERR (1 << 21) /* Bit 21: Flash Reset Error Status (FLASH_RST_ERR) */
+#define DCM_GPR_DCMROD4_FLASH_SCAN_ERR (1 << 22) /* Bit 22: Error while DCM flash scanning process due to invalid data (FLASH_SCAN_ERR) */
+ /* Bit 23: Reserved */
+#define DCM_GPR_DCMROD4_FLASH_ECC_ERR (1 << 24) /* Bit 24: ECC Error from Flash Controller (FLASH_ECC_ERR) */
+#define DCM_GPR_DCMROD4_FLASH_ACCESS_ERR (1 << 25) /* Bit 25: Transaction Monitor Mismatch Error from Flash Controller (FLASH_ACCESS_ERR) */
+#define DCM_GPR_DCMROD4_VDD1P1_GNG_ERR (1 << 26) /* Bit 26: Go/no-go indicator for VDD1PD1 (double bond) supply going to PLL (VDD1P1_GNG_ERR) */
+#define DCM_GPR_DCMROD4_VDD2P5_GNG_ERR (1 << 27) /* Bit 27: Go/no-go indicator for VDD_HV_FLA (double bond) supply going to FXOSC and PLL (VDD2P5_GNG_ERR) */
+ /* Bit 28: Reserved */
+
+#define DCM_GPR_DCMROD4_TEST_ACTIVATION_0_ERR (1 << 29) /* Bit 29: Accidental Partial Test Activation (TEST_ACTIVATION_0_ERR) */
+#define DCM_GPR_DCMROD4_TEST_ACTIVATION_1_ERR (1 << 30) /* Bit 30: Accidental Partial Test Activation (TEST_ACTIVATION_1_ERR) */
+
+ /* Bit 31: Reserved */
+
+/* Read Only GPR On Destructive Reset Register 5 (DCMROD5) */
+
+ /* Bit 0: Reserved */
+#define DCM_GPR_DCMROD5_INTM_0_ERR (1 << 1) /* Bit 1: Interrupt monitor0 error reported by INTM (INTM_0_ERR) */
+#define DCM_GPR_DCMROD5_INTM_1_ERR (1 << 2) /* Bit 2: Interrupt monitor1 error reported by INTM (INTM_0_ERR) */
+#define DCM_GPR_DCMROD5_INTM_2_ERR (1 << 3) /* Bit 3: Interrupt monitor2 error reported by INTM (INTM_0_ERR) */
+#define DCM_GPR_DCMROD5_INTM_3_ERR (1 << 4) /* Bit 4: Interrupt monitor3 error reported by INTM (INTM_0_ERR) */
+#define DCM_GPR_DCMROD5_SW_NCF_0 (1 << 5) /* Bit 5: Status of DCMRWF1[FCCU_SW_NCF0] (SW_NCF_0) */
+#define DCM_GPR_DCMROD5_SW_NCF_1 (1 << 6) /* Bit 6: Status of DCMRWF1[FCCU_SW_NCF1] (SW_NCF_1) */
+#define DCM_GPR_DCMROD5_SW_NCF_2 (1 << 7) /* Bit 7: Status of DCMRWF1[FCCU_SW_NCF2] (SW_NCF_2) */
+#define DCM_GPR_DCMROD5_SW_NCF_3 (1 << 8) /* Bit 8: Status of DCMRWF1[FCCU_SW_NCF3] (SW_NCF_3) */
+#define DCM_GPR_DCMROD5_STCU_NCF (1 << 9) /* Bit 9: STCU non-critical fault / BIST result error (STCU_NCF) */
+
+#define DCM_GPR_DCMROD5_MBIST_ACTIVATION_ERR (1 << 10) /* Bit 10: Indicates an accidental backdoor access on memories (MBIST_ACTIVATION_ERR) */
+
+#define DCM_GPR_DCMROD5_STCU_BIST_USER_CF (1 << 11) /* Bit 11: L/M BIST enabled accidentally (STCU_BIST_USER_CF) */
+#define DCM_GPR_DCMROD5_MTR_BUS_ERR (1 << 12) /* Bit 12: Fault reported due to illegal access on MTR (MTR_BUS_ERR) */
+
+#define DCM_GPR_DCMROD5_DEBUG_ACTIVATION_ERR (1 << 13) /* Bit 13: Monitoring of unintended debug activation (DEBUG_ACTIVATION_ERR) */
+
+#define DCM_GPR_DCMROD5_TCM_RDATA_EDC_ERR (1 << 14) /* Bit 14: Integrity (EDC) error on TCM read data for safety (TCM_RDATA_EDC_ERR) */
+
+#define DCM_GPR_DCMROD5_EMAC_RDATA_EDC_ERR (1 << 15) /* Bit 15: Integrity (EDC) error on EMAC read data for safety (EMAC_RDATA_EDC_ERR) */
+
+ /* Bit 16: Reserved */
+#define DCM_GPR_DCMROD5_DMA_RDATA_EDC_ERR (1 << 17) /* Bit 17: Integrity (EDC) error on eDMA read data for safety (DMA_RDATA_EDC_ERR) */
+
+#define DCM_GPR_DCMROD5_CM7_1_AHBP_RDATA_EDC_ERR (1 << 18) /* Bit 18: Integrity error on CM7_1 peripheral read data for safety (CM7_1_AHBP_RDATA_EDC_ERR) */
+#define DCM_GPR_DCMROD5_CM7_1_AHBM_RDATA_EDC_ERR (1 << 19) /* Bit 19: Integrity error on CM7_1 main read data for safety (CM7_1_AHBM_RDATA_EDC_ERR) */
+#define DCM_GPR_DCMROD5_CM7_0_AHBP_RDATA_EDC_ERR (1 << 20) /* Bit 18: Integrity error on CM7_0 peripheral read data for safety (CM7_0_AHBP_RDATA_EDC_ERR) */
+#define DCM_GPR_DCMROD5_CM7_0_AHBM_RDATA_EDC_ERR (1 << 21) /* Bit 19: Integrity error on CM7_0 main read data for safety (CM7_0_AHBM_RDATA_EDC_ERR) */
+
+#define DCM_GPR_DCMROD5_HSE_RDATA_EDC_ERR (1 << 22) /* Bit 22: Integrity (EDC) error on HSE read data for safety (HSE_RDATA_EDC_ERR) */
+ /* Bits 23-31: Reserved */
+
+/* Read Only GPR On Functional Reset Register 1 (DCMROF1) */
+
+#define DCM_GPR_DCMROF1_EMAC_MDC_CHID_0 (1 << 0) /* Bit 0: EMAC DMA Channel ID0 Status (EMAC_MDC_CHID_0) */
+#define DCM_GPR_DCMROF1_EMAC_MDC_CHID_1 (1 << 1) /* Bit 1: EMAC DMA Channel ID0 Status (EMAC_MDC_CHID_0) */
+ /* Bits 2-31: Reserved */
+
+/* Read Only GPR On Functional Reset Register n (DCMROFn, n=2..17) */
+
+#define DCM_GPR_DCMROF2_17_DCF_SDID_SHIFT (0) /* Bits 0-31: Configuration bits of DCF client SDID x (DCF_SDIDx) */
+#define DCM_GPR_DCMROF2_17_DCF_SDID_MASK (0xffffffff << DCM_GPR_DCMROF2_17_DCF_SDID_SHIFT)
+
+/* Read Only GPR On Functional Reset Register 19 (DCMROF19) */
+
+ /* Bits 0-28: Reserved */
+#define DCM_GPR_DCMROF19_LOCKSTEP_EN (1 << 29) /* Bit 29: Lockstep Enable (LOCKSTEP_EN) */
+#define DCM_GPR_DCMROF19_DCM_DONE (1 << 30) /* Bit 30: DCM Done (DCM_DONE) */
+
+#define DCM_GPR_DCMROF19_FCCU_EOUT_DEDICATED (1 << 31) /* Bit 31: FCCU EOUT Dedicated (FCCU_EOUT_DEDICATED) */
+
+/* Read Only GPR On Functional Reset Register 20 (DCMROF20) */
+
+#define DCM_GPR_DCMROF20_POR_WDG_EN (1 << 0) /* Bit 0: Indicates the status of POR_WDG as configured in DCF record (POR_WDG_EN) */
+#define DCM_GPR_DCMROF20_LMAUTO_DIS (1 << 1) /* Bit 1: PMC last mile automatic crossover from boot regulation feature support (LMAUTO_DIS) */
+#define DCM_GPR_DCMROF20_CM7_TCM_WS_EN (1 << 2) /* Bit 2: Status of CM7 DTCM and ITCM waitstates as configured in DCF record (CM7_TCM_WS_EN) */
+
+#define DCM_GPR_DCMROF20_DMA_AXBS_IAHB_BYP (1 << 3) /* Bit 3: Status of DMA AXBS IAHB gasket as configured in DCF record (DMA_AXBS_IAHB_BYP) */
+ /* Bit 4: Reserved */
+#define DCM_GPR_DCMROF20_QSPI_IAHB_BYP (1 << 5) /* Bit 5: Status of QSPI IAHB gasket as configured in DCF record (QSPI_IAHB_BYP) */
+#define DCM_GPR_DCMROF20_AIPS_IAHB_BYP (1 << 6) /* Bit 6: Status of AIPS1/2 IAHB gasket as configured in DCF record (AIPS_IAHB_BYP) */
+ /* Bits 7-17: Reserved */
+
+#define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT (18) /* Bits 18-31: Destructive Reset Escalation (DCF_DEST_RST_ESC) */
+#define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_MASK (0x3fff << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT)
+# define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_DIS (0x0000 << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT) /* Destructive Reset Escalation disabled */
+# define DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_EN (0x0001 << DCM_GPR_DCMROF20_DCF_DEST_RST_ESC_SHIFT) /* Destructive Rest Escalation enabled */
+
+/* Read Only GPR On Functional Reset Register 21 (DCMROF21) */
+
+#define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT (0) /* Bits 0-17: Destructive Reset Escalation (DCF_DEST_RST_ESC) */
+#define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_MASK (0x03ffff << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT)
+# define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_DIS (0x000000 << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT) /* Destructive Reset Escalation disabled */
+# define DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_EN (0x000001 << DCM_GPR_DCMROF21_DCF_DEST_RST_ESC_SHIFT) /* Destructive Rest Escalation enabled */
+
+ /* Bit 18: Reserved */
+
+#define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT (19) /* Bits 19-20: HSE Clock Mode Option (HSE_CLK_MODE_OPTION) */
+#define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_MASK (0x03 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT)
+# define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_A (0x00 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT) /* Applicable for clocking option A */
+# define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_CDEF (0x01 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT) /* Applicable for clocking options C, D, E, E2 and F */
+# define DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_B (0x02 << DCM_GPR_DCMROF21_HSE_CLK_MODE_OPTION_SHIFT) /* Applicable for clocking option B */
+
+/* Read Write GPR On Power On Reset Register 1 (DCMRWP1) */
+
+ /* Bits 0-2: Reserved */
+#define DCM_GPR_DCMRWP1_CLKOUT_STANDBY (1 << 3) /* Bit 3: Clockout standby expose over functional and destructive reset (CLKOUT_STANDBY) */
+ /* Bits 4-7: Reserved */
+#define DCM_GPR_DCMRWP1_STANDBY_PWDOG_DIS (1 << 8) /* Bit 8: Disables the standby entry and exit monitoring window of the POR WDOG (STANDBY_PWDOG_DIS) */
+
+#define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT (9) /* Bits 9-10: Trims for POR WDG timeout value (POR_WDOG_TRIM) */
+#define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_MASK (0x03 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT)
+# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_6_25MS (0x00 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 06.25ms */
+# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_12_5MS (0x01 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 12.50ms */
+# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_25MS (0x02 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 25.00ms */
+# define DCM_GPR_DCMRWP1_POR_WDOG_TRIM_50MS (0x03 << DCM_GPR_DCMRWP1_POR_WDOG_TRIM_SHIFT) /* POR WDOG Timeout = 50.00ms */
+
+ /* Bits 11-31: Reserved */
+
+/* Read Write GPR On Power On Reset Register 3 (DCMRWP3) */
+
+ /* Bits 0-8: Reserved */
+#define DCM_GPR_DCMRWP3_DEST_RST9_AS_IPI (1 << 9) /* Bit 9: Configures a destructive reset to interrupt (DEST_RST9_AS_IPI) */
+ /* Bits 10-31: Reserved */
+
+/* Read Write GPR On Destructive Reset Register 2 (DCMRWD2) */
+
+ /* Bits 0-6: Reserved */
+
+#define DCM_GPR_DCMRWD2_EOUT_STAT_DUR_STEST (1 << 7) /* Bit 7: Controls the EOUT state during selftest (EOUT_STAT_DUR_STEST) */
+
+ /* Bits 8-31: Reserved */
+
+/* Read Write GPR On Destructive Reset Register 3 (DCMRWD3) */
+
+#define DCM_GPR_DCMRWD3_CM7_0_LOCKUP_EN (1 << 0) /* Bit 0: Enable fault monitoring at FCCU NCF 0 for CM7_0 core lockup (CM7_0_LOCKUP_EN) */
+#define DCM_GPR_DCMRWD3_CM7_1_LOCKUP_EN (1 << 1) /* Bit 1: Enable fault monitoring at FCCU NCF 0 for CM7_1 core lockup (CM7_1_LOCKUP_EN) */
+ /* Bit 2: Reserved */
+#define DCM_GPR_DCMRWD3_CM7_RCCU1_ALARM_EN (1 << 3) /* Bit 3: Enable fault monitoring at FCCU NCF 0 for Cortex M7 cores lockstep error (CM7_RCCU1_ALARM_EN) */
+#define DCM_GPR_DCMRWD3_CM7_RCCU2_ALARM_EN (1 << 4) /* Bit 4: Enable fault monitoring at FCCU NCF 0 for Cortex M7 cores redundant lockstep error (CM7_RCCU2_ALARM_EN) */
+
+#define DCM_GPR_DCMRWD3_TCM_GSKT_ALARM_EN (1 << 5) /* Bit 5: Enable fault monitoring at FCCU NCF 1 for TCM IAHB Gasket monitor alarm (TCM_GSKT_ALRM_EN) */
+
+#define DCM_GPR_DCMRWD3_DMA_SYS_GSKT_ALARM_EN (1 << 6) /* Bit 6: Enable fault monitoring at FCCU NCF 1 for IAHB gasket safety alarm from DMA system AXBS IAHB gasket (DMA_SYS_GSKT_ALARM_EN) */
+#define DCM_GPR_DCMRWD3_DMA_PERIPH_GSKT_ALARM_EN (1 << 7) /* Bit 7: Enable fault monitoring at FCCU NCF 1 for IAHB gasket safety alarm from DMA periph AXBS IAHB gasket (DMA_PERIPH_GSKT_ALARM_EN) */
+
+#define DCM_GPR_DCMRWD3_SYS_AXBS_ALARM_EN (1 << 8) /* Bit 8: Enable fault monitoring at FCCU NCF 1 for system AXBS safety alarm (SYS_AXBS_ALARM_EN) */
+#define DCM_GPR_DCMRWD3_DMA_AXBS_ALARM_EN (1 << 9) /* Bit 9: Enable fault monitoring at FCCU NCF 1 for DMA AXBS_Lite safety alarm (DMA_AXBS_ALARM_EN) */
+ /* Bit 10: Reserved */
+#define DCM_GPR_DCMRWD3_HSE_GSKT_ALARM_EN (1 << 11) /* Bit 11: Enable fault monitoring at FCCU NCF 1 for HSE IAHB gasket alarm (HSE_GSKT_ALARM_EN) */
+
+#define DCM_GPR_DCMRWD3_QSPI_GSKT_ALARM_EN (1 << 12) /* Bit 12: Enable fault monitoring at FCCU NCF 1 for QSPI IAHB gasket alarm (QSPI_GSKT_ALARM_EN) */
+#define DCM_GPR_DCMRWD3_AIPS1_GSKT_ALARM_EN (1 << 13) /* Bit 13: Enable fault monitoring at FCCU NCF 1 for AIPS1 IAHB gasket alarm (AIPS1_GSKT_ALARM_EN) */
+#define DCM_GPR_DCMRWD3_AIPS2_GSKT_ALARM_EN (1 << 14) /* Bit 14: Enable fault monitoring at FCCU NCF 1 for AIPS2 IAHB gasket alarm (AIPS2_GSKT_ALARM_EN) */
+
+#define DCM_GPR_DCMRWD3_ADDR_EDC_ERR_EN (1 << 15) /* Bit 15: Enable fault monitoring at FCCU NCF 1 for integrity error on address for safety (ADDR_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_DATA_EDC_ERR_EN (1 << 16) /* Bit 16: Enable fault monitoring at FCCU NCF 1 for integrity error on data for safety (DATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_TCM_AXBS_ALARM_EN (1 << 17) /* Bit 17: Enable fault monitoring at FCCU NCF 1 for TCM AHB splitter safety alarm (TCM_AXBS_ALARM_EN) */
+
+#define DCM_GPR_DCMRWD3_EMAC_GSKT_ALARM_EN (1 << 18) /* Bit 18: Enable fault monitoring at FCCU NCF 1 for EMAC IAHB gasket alarm (EMAC_GSKT_ALARM_EN) */
+#define DCM_GPR_DCMRWD3_PERIPH_AXBS_ALARM_EN (1 << 19) /* Bit 19: Enable fault monitoring at FCCU NCF 1 for PERIPH AXBS_Lite safety alarm (PERIPH_AXBS_ALARM_EN) */
+
+ /* Bits 20-21: Reserved */
+#define DCM_GPR_DCMRWD3_LC_ERR_EN (1 << 22) /* Bit 22: Enable fault monitoring at FCCU NCF 3 for error in lifecycle scanning (LC_ERR_EN) */
+ /* Bits 23: Reserved */
+
+#define DCM_GPR_DCMRWD3_PRAM1_ECC_ERR_EN (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM1 (PRAM1_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_PRAM0_ECC_ERR_EN (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from SRAM0 (PRAM0_ECC_ERR_EN) */
+
+#define DCM_GPR_DCMRWD3_CM7_0_DCDATA_ECC_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_CM7_1_DCDATA_ECC_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_CM7_0_DCTAG_ECC_ERR_EN (1 << 28) /* Bit 28: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 DCache tag memory (CM7_0_DCTAG_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_CM7_1_DCTAG_ECC_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 DCache tag memory (CM7_1_DCTAG_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_CM7_0_ICDATA_ECC_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache data memory (CM7_0_DCDATA_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD3_CM7_1_ICDATA_ECC_ERR_EN (1 << 31) /* Bit 31: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache data memory (CM7_1_DCDATA_ECC_ERR_EN) */
+
+/* Read Write GPR On Destructive Reset Register 4 (DCMRWD4) */
+
+#define DCM_GPR_DCMRWD4_CM7_0_ICTAG_ECC_ERR_EN (1 << 0) /* Bit 0: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_0 ICache tag memory (CM7_0_ICTAG_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_1_ICTAG_ECC_ERR_EN (1 << 1) /* Bit 1: Enable fault monitoring at FCCU NCF 2 for multi bit ECC error from CM7_1 ICache tag memory (CM7_1_ICTAG_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_0_ITCM_ECC_ERR_EN (1 << 2) /* Bit 2: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_0 Instruction TCM memory (CM7_0_ITCM_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_0_DTCM0_ECC_ERR_EN (1 << 3) /* Bit 3: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_0 Data TCM memory block 0 (CM7_0_DTCM0_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_0_DTCM1_ECC_ERR_EN (1 << 4) /* Bit 4: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_0 Data TCM memory block 1 (CM7_0_DTCM1_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_1_ITCM_ECC_ERR_EN (1 << 5) /* Bit 5: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_1 Instruction TCM memory (CM7_1_ITCM_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_1_DTCM0_ECC_ERR_EN (1 << 6) /* Bit 6: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_1 Data TCM memory block 0 (CM7_1_DTCM0_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_CM7_1_DTCM1_ECC_ERR_EN (1 << 7) /* Bit 7: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error from CM7_1 Data TCM memory block 1 (CM7_1_DTCM1_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_DMA_TCD_RAM_ECC_ERR_EN (1 << 8) /* Bit 8: Enable fault monitoring at FCCU NCF 2 for uncorrectable ECC error reported from DMA_TCD memory (DMA_TCD_RAM_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PRAM0_FCCU_ALARM_EN (1 << 9) /* Bit 9: Enable fault monitoring at FCCU NCF 2 for PRAM0 safety alarm (PRAM0_FCCU_ALARM_EN) */
+#define DCM_GPR_DCMRWD4_PRAM1_FCCU_ALARM_EN (1 << 10) /* Bit 10: Enable fault monitoring at FCCU NCF 2 for PRAM1 safety alarm (PRAM1_FCCU_ALARM_EN) */
+#define DCM_GPR_DCMRWD4_HSE_RAM_ECC_ERR_EN (1 << 11) /* Bit 11: Enable fault monitoring at FCCU NCF 2 for HSE RAM Uncorrectable ECC (HSE_RAM_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PF0_CODE_ECC_ERR_EN (1 << 12) /* Bit 12: Enable fault monitoring at FCCU NCF 3 for Flash0 code ECC uncorrectable error (PF0_CODE_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PF0_DATA_ECC_ERR_EN (1 << 13) /* Bit 13: Enable fault monitoring at FCCU NCF 3 for Flash0 data ECC uncorrectable error (PF0_DATA_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PF1_CODE_ECC_ERR_EN (1 << 14) /* Bit 14: Enable fault monitoring at FCCU NCF 3 for Flash1 code ECC uncorrectable error (PF1_CODE_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PF1_DATA_ECC_ERR_EN (1 << 15) /* Bit 15: Enable fault monitoring at FCCU NCF 3 for Flash1 data ECC uncorrectable error (PF1_DATA_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PF2_CODE_ECC_ERR_EN (1 << 16) /* Bit 16: Enable fault monitoring at FCCU NCF 3 for Flash2 code ECC uncorrectable error (PF2_CODE_ECC_ERR_EN) */
+#define DCM_GPR_DCMRWD4_PF2_DATA_ECC_ERR_EN (1 << 17) /* Bit 17: Enable fault monitoring at FCCU NCF 3 for Flash2 data ECC uncorrectable error (PF2_DATA_ECC_ERR_EN) */
+
+#define DCM_GPR_DCMRWD4_FLASH_EDC_ERR_EN (1 << 18) /* Bit 18: Enable fault monitoring at FCCU NCF 3 for Flash ECC correction error through EDC reported by FMU (FLASH_EDC_ERR_EN) */
+
+#define DCM_GPR_DCMRWD4_FLASH_ADDR_ENC_ERR_EN (1 << 19) /* Bit 19: Enable fault monitoring at FCCU NCF 3 for flash address encode error (FLASH_ADDR_ENC_ERR_EN) */
+
+#define DCM_GPR_DCMRWD4_FLASH_REF_ERR_EN (1 << 20) /* Bit 20: Enable fault monitoring at FCCU NCF 3 for flash reference current loss or read voltage error while previous read(s) (FLASH_REF_ERR_EN) */
+#define DCM_GPR_DCMRWD4_FLASH_RST_ERR_EN (1 << 21) /* Bit 21: Enable fault monitoring at FCCU NCF 3 for flash reset error (FLASH_RST_ERR_EN) */
+#define DCM_GPR_DCMRWD4_FLASH_SCAN_ERR_EN (1 << 22) /* Bit 22: Enable fault monitoring at FCCU NCF 3 for error while DCM flash scanning process due to invalid data (FLASH_SCAN_ERR_EN) */
+ /* Bit 23: Reserved */
+#define DCM_GPR_DCMRWD4_FLASH_ECC_ERR_EN (1 << 24) /* Bit 24: Enable fault monitoring at FCCU NCF 3 for ECC error from Flash Controller (FLASH_ECC_ERR_EN) */
+
+#define DCM_GPR_DCMRWD4_FLASH_ACCESS_ERR_EN (1 << 25) /* Bit 25: Enable fault monitoring at FCCU NCF 3 for transaction monitor mismatch (FLASH_ACCESS_ERR_EN) */
+
+#define DCM_GPR_DCMRWD4_VDD1P1_GNG_ERR_EN (1 << 26) /* Bit 26: Enable fault monitoring at FCCU NCF 4 for Go/No-go indicator for VDD1PD1 (double bond) supply going to PLL (VDD1P1_GNG_ERR_EN) */
+#define DCM_GPR_DCMRWD4_VDD2P5_GNG_ERR_EN (1 << 27) /* Bit 27: Enable fault monitoring at FCCU NCF 4 for Go/No-go indicator for VDD_HV_FLA (double bond) supply going to FXOSC and PLL (VDD2P5_GNG_ERR_EN) */
+ /* Bit 28: Reserved */
+
+#define DCM_GPR_DCMRWD4_TEST_ACTIVATION_0_ERR_EN (1 << 29) /* Bit 29: Enable fault monitoring at FCCU NCF 5 for accidental partial test activation (TEST_ACTIVATION_0_ERR_EN) */
+#define DCM_GPR_DCMRWD4_TEST_ACTIVATION_1_ERR_EN (1 << 30) /* Bit 30: Enable fault monitoring at FCCU NCF 5 for accidental partial test activation (TEST_ACTIVATION_1_ERR_EN) */
+
+ /* Bit 31: Reserved */
+
+/* Read Write GPR On Destructive Reset Register 5 (DCMRWD5) */
+
+ /* Bit 0: Reserved */
+#define DCM_GPR_DCMRWD5_INTM_0_ERR_EN (1 << 1) /* Bit 1: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 0 error reported by INTM (INTM_0_ERR_EN) */
+#define DCM_GPR_DCMRWD5_INTM_1_ERR_EN (1 << 2) /* Bit 2: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 1 error reported by INTM (INTM_1_ERR_EN) */
+#define DCM_GPR_DCMRWD5_INTM_2_ERR_EN (1 << 3) /* Bit 3: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 2 error reported by INTM (INTM_2_ERR_EN) */
+#define DCM_GPR_DCMRWD5_INTM_3_ERR_EN (1 << 4) /* Bit 4: Enable fault monitoring at FCCU NCF 6 for interrupt monitor 3 error reported by INTM (INTM_3_ERR_EN) */
+#define DCM_GPR_DCMRWD5_SW_NCF_0_EN (1 << 5) /* Bit 5: Enable fault monitoring at FCCU NCF 7 for Software NFC0 (SW_NCF_0_EN) */
+#define DCM_GPR_DCMRWD5_SW_NCF_1_EN (1 << 6) /* Bit 6: Enable fault monitoring at FCCU NCF 7 for Software NFC1 (SW_NCF_1_EN) */
+#define DCM_GPR_DCMRWD5_SW_NCF_2_EN (1 << 7) /* Bit 7: Enable fault monitoring at FCCU NCF 7 for Software NFC2 (SW_NCF_2_EN) */
+#define DCM_GPR_DCMRWD5_SW_NCF_3_EN (1 << 8) /* Bit 8: Enable fault monitoring at FCCU NCF 7 for Software NFC3 (SW_NCF_3_EN) */
+#define DCM_GPR_DCMRWD5_STCU_NCF_EN (1 << 9) /* Bit 9: Enable fault monitoring at FCCU NCF 5 for STCU non-critical fault / BIST result error (STCU_NCF_EN) */
+
+#define DCM_GPR_DCMRWD5_MBIST_ACTIVATION_ERR_EN (1 << 10) /* Bit 10: Enable fault monitoring at FCCU NCF 5 for accidental backdoor access on memories (MBIST_ACTIVATION_ERR_EN) */
+#define DCM_GPR_DCMRWD5_STCU_BIST_USER_CF_EN (1 << 11) /* Bit 11: Enable fault monitoring at FCCU NCF 5 for L/M BIST enabled accidentally (STCU_BIST_USER_CF_EN) */
+
+#define DCM_GPR_DCMRWD5_MTR_BUS_ERR_EN (1 << 12) /* Bit 12: Enable fault monitoring at FCCU NFC 5 for fault reported due to illegal access on MTR (MTR_BUS_ERR_EN) */
+
+#define DCM_GPR_DCMRWD5_DEBUG_ACTIVATION_ERR_EN (1 << 13) /* Bit 13: Enable fault monitoring at FCCU NCF 5 for monitoring of unintended debug activation (DEBUG_ACTIVATION_ERR_EN) */
+#define DCM_GPR_DCMRWD5_TCM_RDATA_EDC_ERR_EN (1 << 14) /* Bit 14: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on TCM read data for safety (TCM_RDATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD5_EMAC_RDATA_EDC_ERR_EN (1 << 15) /* Bit 15: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on EMAC read data for safety (EMAC_RDATA_EDC_ERR_EN) */
+
+ /* Bit 16: Reserved */
+
+#define DCM_GPR_DCMRWD5_DMA_RDATA_EDC_ERR_EN (1 << 17) /* Bit 17: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on eDMA read data for safety (DMA_RDATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD5_CM7_1_AHBP_RDATA_EDC_ERR_EN (1 << 18) /* Bit 18: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_1 peripheral read data for safety (CM7_1_AHBP_RDATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD5_CM7_1_AHBM_RDATA_EDC_ERR_EN (1 << 19) /* Bit 19: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_1 main read data for safety (CM7_1_AHBM_RDATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD5_CM7_0_AHBP_RDATA_EDC_ERR_EN (1 << 20) /* Bit 20: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_0 peripheral read data for safety (CM7_0_AHBP_RDATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD5_CM7_0_AHBM_RDATA_EDC_ERR_EN (1 << 21) /* Bit 21: Enable fault monitoring at FCCU NCF 1 for integrity error on CM7_0 main read data for safety (CM7_0_AHBM_RDATA_EDC_ERR_EN) */
+#define DCM_GPR_DCMRWD5_HSE_RDATA_EDC_ERR_EN (1 << 22) /* Bit 22: Enable fault monitoring at FCCU NCF 1 for integrity (EDC) error on HSE read data for safety (HSE_RDATA_EDC_ERR_EN) */
+
+ /* Bits 23-31: Reserved */
+
+/* Read Write GPR On Destructive Reset Register 6 (DCMRWD6) */
+
+#define DCM_GPR_DCMRWD6_EDMA_DBG_DIS_CM7_0 (1 << 0) /* Bit 0: EDMA debug disable bit for CM7_0 (EDMA_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FCCU_DBG_DIS_CM7_0 (1 << 1) /* Bit 1: FCCU debug disable bit for CM7_0 (FCCU_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LCU0_DBG_DIS_CM7_0 (1 << 2) /* Bit 2: LCU0 debug disable bit for CM7_0 (LCU0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LCU1_DBG_DIS_CM7_0 (1 << 3) /* Bit 3: LCU1 debug disable bit for CM7_0 (LCU1_DBG_DIS_CM7_0) */
+
+#define DCM_GPR_DCMRWD6_EMIOS0_DBG_DIS_CM7_0 (1 << 4) /* Bit 4: EMIOS0 debug disable bit for CM7_0 (EMIOS0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_EMIOS1_DBG_DIS_CM7_0 (1 << 5) /* Bit 5: EMIOS1 debug disable bit for CM7_0 (EMIOS1_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_EMIOS2_DBG_DIS_CM7_0 (1 << 6) /* Bit 6: EMIOS2 debug disable bit for CM7_0 (EMIOS2_DBG_DIS_CM7_0) */
+
+#define DCM_GPR_DCMRWD6_RTC_DBG_DIS_CM7_0 (1 << 7) /* Bit 7: RTC debug disable bit for CM7_0 (RTC_DBG_DIS_CM7_0) */
+
+#define DCM_GPR_DCMRWD6_SWT0_DBG_DIS_CM7_0 (1 << 8) /* Bit 8: SWT0 debug disable bit for CM7_0 (SWT0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_SWT1_DBG_DIS_CM7_0 (1 << 9) /* Bit 9: SWT1 debug disable bit for CM7_0 (SWT1_DBG_DIS_CM7_0) */
+
+#define DCM_GPR_DCMRWD6_STM0_DBG_DIS_CM7_0 (1 << 10) /* Bit 10: STM0 debug disable bit for CM7_0 (STM0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_STM1_DBG_DIS_CM7_0 (1 << 11) /* Bit 11: STM1 debug disable bit for CM7_0 (STM1_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_PIT0_DBG_DIS_CM7_0 (1 << 12) /* Bit 12: PIT0 debug disable bit for CM7_0 (PIT0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_PIT1_DBG_DIS_CM7_0 (1 << 13) /* Bit 13: PIT1 debug disable bit for CM7_0 (PIT1_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_PIT2_DBG_DIS_CM7_0 (1 << 14) /* Bit 14: PIT2 debug disable bit for CM7_0 (PIT2_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPSPI0_DBG_DIS_CM7_0 (1 << 15) /* Bit 15: LPSPI0 debug disable bit for CM7_0 (LPSPI0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPSPI1_DBG_DIS_CM7_0 (1 << 16) /* Bit 16: LPSPI1 debug disable bit for CM7_0 (LPSPI1_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPSPI2_DBG_DIS_CM7_0 (1 << 17) /* Bit 17: LPSPI2 debug disable bit for CM7_0 (LPSPI2_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPSPI3_DBG_DIS_CM7_0 (1 << 18) /* Bit 18: LPSPI3 debug disable bit for CM7_0 (LPSPI3_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPSPI4_DBG_DIS_CM7_0 (1 << 19) /* Bit 19: LPSPI4 debug disable bit for CM7_0 (LPSPI4_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPSPI5_DBG_DIS_CM7_0 (1 << 20) /* Bit 20: LPSPI5 debug disable bit for CM7_0 (LPSPI5_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPI2C0_DBG_DIS_CM7_0 (1 << 21) /* Bit 21: LPI2C0 debug disable bit for CM7_0 (LPI2C0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_LPI2C1_DBG_DIS_CM7_0 (1 << 22) /* Bit 22: LPI2C1 debug disable bit for CM7_0 (LPI2C1_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXIO_DBG_DIS_CM7_0 (1 << 23) /* Bit 23: FLEXIO debug disable bit for CM7_0 (FLEXIO_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXCAN0_DBG_DIS_CM7_0 (1 << 24) /* Bit 24: FLEXCAN0 debug disable bit for CM7_0 (FLEXCAN0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXCAN1_DBG_DIS_CM7_0 (1 << 25) /* Bit 25: FLEXCAN1 debug disable bit for CM7_0 (FLEXCAN1_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXCAN2_DBG_DIS_CM7_0 (1 << 26) /* Bit 26: FLEXCAN2 debug disable bit for CM7_0 (FLEXCAN2_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXCAN3_DBG_DIS_CM7_0 (1 << 27) /* Bit 27: FLEXCAN3 debug disable bit for CM7_0 (FLEXCAN3_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXCAN4_DBG_DIS_CM7_0 (1 << 28) /* Bit 28: FLEXCAN4 debug disable bit for CM7_0 (FLEXCAN4_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_FLEXCAN5_DBG_DIS_CM7_0 (1 << 29) /* Bit 29: FLEXCAN5 debug disable bit for CM7_0 (FLEXCAN5_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_SAI0_DBG_DIS_CM7_0 (1 << 30) /* Bit 30: SAI0 debug disable bit for CM7_0 (SAI0_DBG_DIS_CM7_0) */
+#define DCM_GPR_DCMRWD6_SAI1_DBG_DIS_CM7_0 (1 << 31) /* Bit 31: SAI1 debug disable bit for CM7_0 (SAI1_DBG_DIS_CM7_0) */
+
+/* Read Write GPR On Destructive Reset Register 7 (DCMRWD7) */
+
+#define DCM_GPR_DCMRWD7_I3C_DBG_DIS_CM7_0 (1 << 0) /* Bit 0: I3C debug disable bit for CM7_0 (I3C_DBG_DIS_CM7_0) */
+ /* Bits 1-31: Reserved */
+
+/* Read Write GPR On Destructive Reset Register 8 (DCMRWD8) */
+
+#define DCM_GPR_DCMRWD8_EDMA_DBG_DIS_CM7_1 (1 << 0) /* Bit 0: EDMA debug disable bit for CM7_1 (EDMA_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FCCU_DBG_DIS_CM7_1 (1 << 1) /* Bit 1: FCCU debug disable bit for CM7_1 (FCCU_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LCU0_DBG_DIS_CM7_1 (1 << 2) /* Bit 2: LCU0 debug disable bit for CM7_1 (LCU0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LCU1_DBG_DIS_CM7_1 (1 << 3) /* Bit 3: LCU1 debug disable bit for CM7_1 (LCU1_DBG_DIS_CM7_1) */
+
+#define DCM_GPR_DCMRWD8_EMIOS0_DBG_DIS_CM7_1 (1 << 4) /* Bit 4: EMIOS0 debug disable bit for CM7_1 (EMIOS0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_EMIOS1_DBG_DIS_CM7_1 (1 << 5) /* Bit 5: EMIOS1 debug disable bit for CM7_1 (EMIOS1_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_EMIOS2_DBG_DIS_CM7_1 (1 << 6) /* Bit 6: EMIOS2 debug disable bit for CM7_1 (EMIOS2_DBG_DIS_CM7_1) */
+
+#define DCM_GPR_DCMRWD8_RTC_DBG_DIS_CM7_1 (1 << 7) /* Bit 7: RTC debug disable bit for CM7_1 (RTC_DBG_DIS_CM7_1) */
+
+#define DCM_GPR_DCMRWD8_SWT0_DBG_DIS_CM7_1 (1 << 8) /* Bit 8: SWT0 debug disable bit for CM7_1 (SWT0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_SWT1_DBG_DIS_CM7_1 (1 << 9) /* Bit 9: SWT1 debug disable bit for CM7_1 (SWT1_DBG_DIS_CM7_1) */
+
+#define DCM_GPR_DCMRWD8_STM0_DBG_DIS_CM7_1 (1 << 10) /* Bit 10: STM0 debug disable bit for CM7_1 (STM0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_STM1_DBG_DIS_CM7_1 (1 << 11) /* Bit 11: STM1 debug disable bit for CM7_1 (STM1_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_PIT0_DBG_DIS_CM7_1 (1 << 12) /* Bit 12: PIT0 debug disable bit for CM7_1 (PIT0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_PIT1_DBG_DIS_CM7_1 (1 << 13) /* Bit 13: PIT1 debug disable bit for CM7_1 (PIT1_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_PIT2_DBG_DIS_CM7_1 (1 << 14) /* Bit 14: PIT2 debug disable bit for CM7_1 (PIT2_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPSPI0_DBG_DIS_CM7_1 (1 << 15) /* Bit 15: LPSPI0 debug disable bit for CM7_1 (LPSPI0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPSPI1_DBG_DIS_CM7_1 (1 << 16) /* Bit 16: LPSPI1 debug disable bit for CM7_1 (LPSPI1_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPSPI2_DBG_DIS_CM7_1 (1 << 17) /* Bit 17: LPSPI2 debug disable bit for CM7_1 (LPSPI2_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPSPI3_DBG_DIS_CM7_1 (1 << 18) /* Bit 18: LPSPI3 debug disable bit for CM7_1 (LPSPI3_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPSPI4_DBG_DIS_CM7_1 (1 << 19) /* Bit 19: LPSPI4 debug disable bit for CM7_1 (LPSPI4_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPSPI5_DBG_DIS_CM7_1 (1 << 20) /* Bit 20: LPSPI5 debug disable bit for CM7_1 (LPSPI5_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPI2C0_DBG_DIS_CM7_1 (1 << 21) /* Bit 21: LPI2C0 debug disable bit for CM7_1 (LPI2C0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_LPI2C1_DBG_DIS_CM7_1 (1 << 22) /* Bit 22: LPI2C1 debug disable bit for CM7_1 (LPI2C1_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXIO_DBG_DIS_CM7_1 (1 << 23) /* Bit 23: FLEXIO debug disable bit for CM7_1 (FLEXIO_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXCAN0_DBG_DIS_CM7_1 (1 << 24) /* Bit 24: FLEXCAN0 debug disable bit for CM7_1 (FLEXCAN0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXCAN1_DBG_DIS_CM7_1 (1 << 25) /* Bit 25: FLEXCAN1 debug disable bit for CM7_1 (FLEXCAN1_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXCAN2_DBG_DIS_CM7_1 (1 << 26) /* Bit 26: FLEXCAN2 debug disable bit for CM7_1 (FLEXCAN2_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXCAN3_DBG_DIS_CM7_1 (1 << 27) /* Bit 27: FLEXCAN3 debug disable bit for CM7_1 (FLEXCAN3_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXCAN4_DBG_DIS_CM7_1 (1 << 28) /* Bit 28: FLEXCAN4 debug disable bit for CM7_1 (FLEXCAN4_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_FLEXCAN5_DBG_DIS_CM7_1 (1 << 29) /* Bit 29: FLEXCAN5 debug disable bit for CM7_1 (FLEXCAN5_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_SAI0_DBG_DIS_CM7_1 (1 << 30) /* Bit 30: SAI0 debug disable bit for CM7_1 (SAI0_DBG_DIS_CM7_1) */
+#define DCM_GPR_DCMRWD8_SAI1_DBG_DIS_CM7_1 (1 << 31) /* Bit 31: SAI1 debug disable bit for CM7_1 (SAI1_DBG_DIS_CM7_1) */
+
+/* Read Write GPR On Destructive Reset Register 9 (DCMRWD9) */
+
+#define DCM_GPR_DCMRWD9_I3C_DBG_DIS_CM7_1 (1 << 0) /* Bit 0: I3C debug disable bit for CM7_1 (I3C_DBG_DIS_CM7_1) */
+ /* Bits 1-31: Reserved */
+
+/* Read Write GPR On Functional Reset Register 1 (DCMRWF1) */
+
+#define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL (1 << 0) /* Bit 0: Select between EMAC and STM for CAN timestamping (CAN_TIMESTAMP_SEL) */
+# define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_EMAC (1 << 0) /* EMAC selected for CAN timestamping */
+# define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_SEL_STM0 (1 << 1) /* STM0 selected for CAN timestamping */
+
+#define DCM_GPR_DCMRWF1_CAN_TIMESTAMP_EN (1 << 1) /* Bit 1: Enables CAN timestamping feature for all FlexCANs (CAN_TIMESTAMP_EN) */
+#define DCM_GPR_DCMRWF1_FCCU_SW_NCF0 (1 << 2) /* Bit 2: Control to initiate Software NFC to FCCU (FCCU_SW_NFC0) */
+#define DCM_GPR_DCMRWF1_FCCU_SW_NCF1 (1 << 3) /* Bit 3: Control to initiate Software NFC to FCCU (FCCU_SW_NFC1) */
+#define DCM_GPR_DCMRWF1_FCCU_SW_NCF2 (1 << 4) /* Bit 4: Control to initiate Software NFC to FCCU (FCCU_SW_NFC2) */
+#define DCM_GPR_DCMRWF1_FCCU_SW_NCF3 (1 << 5) /* Bit 5: Control to initiate Software NFC to FCCU (FCCU_SW_NFC3) */
+ /* Bit 6: Reserved */
+
+#define DCM_GPR_DCMRWF1_RMII_MII_SEL (1 << 7) /* Bit 7: Selects between MII and RMII mode of ethernet (RMII_MII_SEL) */
+# define DCM_GPR_DCMRWF1_RMII_MII_SEL_MII (0 << 7) /* MII mode */
+# define DCM_GPR_DCMRWF1_RMII_MII_SEL_RMII (1 << 7) /* RMII mode */
+
+ /* Bits 8-14: Reserved */
+
+#define DCM_GPR_DCMRWF1_VDD_HV_B_IO_CTRL_LATCH (1 << 15) /* Bit 15: Controls the IO controls latching in low frequency RUN mode to reduce power consumption on VDD_HV_B domain pins (VDD_HV_B_IO_CTRL_LATCH) */
+
+#define DCM_GPR_DCMRWF1_STANDBY_IO_CONFIG (1 << 16) /* Bit 16: Controls the IO state in standby mode (STANDBY_IO_CONFIG) */
+ /* Bits 17-19: Reserved */
+#define DCM_GPR_DCMRWF1_SUPPLY_MON_EN (1 << 20) /* Bit 20: Enable the supply voltage monitoring by ADC (SUPPLY_MON_SEL) */
+
+#define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT (21) /* Bits 21-23: Selects the source of voltage used by ADC for supply monitoring (SUPPLY_MON_SEL) */
+#define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_MASK (0x07 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT)
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_HV_A (0x00 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_HV_A_DIV */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_HV_B (0x01 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_HV_B_DIV */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_1_5 (0x02 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_1.5_DIV */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_2_5 (0x03 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD_2.5_OSC */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_HOT (0x04 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PD1_HOT_POINT */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_COLD (0x05 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PD1_COLD_POINT */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_PLL (0x06 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PLL */
+# define DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_PD0 (0x07 << DCM_GPR_DCMRWF1_SUPPLY_MON_SEL_SHIFT) /* VDD1.1_PD0 */
+
+#define DCM_GPR_DCMRWF1_VSS_LV_ANMUX_EN (1 << 24) /* Bit 24: Enable VSS_LV monitoring (VSS_LV_ANMUX_EN) */
+
+#define DCM_GPR_DCMRWF1_VDD_HV_A_VLT_DVDR_EN (1 << 25) /* Bit 25: Enable 2:1 divider for VDD_HV_A for supply voltage monitoring by ADC (VDD_HV_A_VLT_DVDR_EN) */
+#define DCM_GPR_DCMRWF1_VDD_HV_B_VLT_DVDR_EN (1 << 26) /* Bit 26: Enable 2:1 divider for VDD_HV_B for supply voltage monitoring by ADC (VDD_HV_B_VLT_DVDR_EN) */
+#define DCM_GPR_DCMRWF1_VDD_1_5_VLT_DVDR_EN (1 << 27) /* Bit 27: Enable 2:1 divider for VDD1P5 for supply voltage monitoring by ADC (VDD_1_5_VLT_DVDR_EN) */
+
+ /* Bits 28-31: Reserved */
+
+/* Read Write GPR On Functional Reset Register 2 (DCMRWF2) */
+
+ /* Bits 0-2: Reserved */
+
+#define DCM_GPR_DCMRWF2_DCM_SCAN_BYP_STDBY_EXT (1 << 3) /* Bit 3: Bypass the DCM scanning on standby exit (DCM_SCAN_BYP_STDBY_EXT) */
+#define DCM_GPR_DCMRWF2_FIRC_TRIM_BYP_STDBY_EXT (1 << 4) /* Bit 4: Bypass the FIRC trimming on standby exit (FIRC_TRIM_BYP_STDBY_EXT) */
+#define DCM_GPR_DCMRWF2_PMC_TRIM_RGM_DCF_BYP_STDBY_EXT (1 << 5) /* Bit 5: Bypass the PMC trimming and RGM DCF loading on standby exit (PMC_TRIM_RGM_DCF_BYP_STDBY_EXT) */
+#define DCM_GPR_DCMRWF2_SIRC_TRIM_BYP_STDBY_EXT (1 << 6) /* Bit 6: Bypass the SIRC trimming on standby exit (SIRC_TRIM_BYP_STDBY_EXT) */
+
+ /* Bits 7-15: Reserved */
+#define DCM_GPR_DCMRWF2_HSE_GSKT_BYPASS (1 << 16) /* Enable the HSE IAHB gasket bypass out of standby mode (HSE_GSKT_BYPASS) */
+ /* Bits 17-31: Reserved */
+
+/* Read Write GPR On Functional Reset Register 4 (DCMRWF4) */
+
+ /* Bit 0: Reserved */
+
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S8 (1 << 1) /* Bit 1: Selects GPIO45 to drive ADC0_S8 (MUX_MODE_EN_ADC0_S8) */
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC0_S9 (1 << 2) /* Bit 2: Selects GPIO46 to drive ADC0_S9 (MUX_MODE_EN_ADC0_S9) */
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S14 (1 << 3) /* Bit 3: Selects GPIO32 to drive ADC1_S14 (MUX_MODE_EN_ADC1_S14) */
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S15 (1 << 4) /* Bit 4: Selects GPIO33 to drive ADC1_S15 (MUX_MODE_EN_ADC1_S15) */
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S22 (1 << 5) /* Bit 5: Selects GPIO114 to drive ADC1_S22 (MUX_MODE_EN_ADC1_S22) */
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC1_S23 (1 << 6) /* Bit 6: Selects GPIO115 to drive ADC1_S23 (MUX_MODE_EN_ADC1_S23) */
+
+ /* Bits 7-8: Reserved */
+
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S8 (1 << 9) /* Bit 9: Selects GPIO45 to drive ADC2_S8 (MUX_MODE_EN_ADC2_S8) */
+#define DCM_GPR_DCMRWF4_MUX_MODE_EN_ADC2_S9 (1 << 10) /* Bit 10: Selects GPIO46 to drive ADC2_S9 (MUX_MODE_EN_ADC2_S9) */
+
+ /* Bits 11-12: Reserved */
+
+#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN0_BYP (1 << 13) /* Bit 13: Bypass glitch filter on TRGMUX input63 (GLITCH_FIL_TRG_IN0_BYP) */
+#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN1_BYP (1 << 14) /* Bit 14: Bypass glitch filter on TRGMUX input62 (GLITCH_FIL_TRG_IN1_BYP) */
+#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN2_BYP (1 << 15) /* Bit 15: Bypass glitch filter on TRGMUX input61 (GLITCH_FIL_TRG_IN2_BYP) */
+#define DCM_GPR_DCMRWF4_GLITCH_FIL_TRG_IN3_BYP (1 << 16) /* Bit 16: Bypass glitch filter on TRGMUX input60 (GLITCH_FIL_TRG_IN3_BYP) */
+
+#define DCM_GPR_DCMRWF4_CM7_0_CPUWAIT (1 << 17) /* Bit 17: Put CM7_0 core into wait mode (CM7_0_CPUWAIT) */
+#define DCM_GPR_DCMRWF4_CM7_1_CPUWAIT (1 << 18) /* Bit 18: Put CM7_1 core into wait mode (CM7_1_CPUWAIT) */
+ /* Bits 19-31: Reserved */
+
+/* Read Write GPR On Functional Reset Register 5 (DCMRWF5) */
+
+#define DCM_GPR_DCMRWF5_BOOT_MODE (1 << 0) /* Bit 0: Selects the boot mode after exiting standby mode (BOOT_MODE) */
+# define DCM_GPR_DCMRWF5_BOOT_MODE_NORMAL (0 << 0) /* Normal */
+# define DCM_GPR_DCMRWF5_BOOT_MODE_FAST (1 << 0) /* Fast Standby */
+
+#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT (1) /* Bits 1-31: Cortex-M7_0 base address of vector table to be used after exiting (fast) standby mode (BOOT_ADDRESS) */
+#define DCM_GPR_DCMRWF5_BOOT_ADDRESS_MASK (0x7fffffff << DCM_GPR_DCMRWF5_BOOT_ADDRESS_SHIFT)
+
+/* Read Only GPR On PMCPOR Reset Register 1 (DCMROPP1) */
+
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT0 (1 << 0) /* Bit 0: Status of functional reset sequence process FUNC0 when POR_WDG overflows (POR_WDG_STAT0) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT1 (1 << 1) /* Bit 1: Status of functional reset sequence process FUNC1 when POR_WDG overflows (POR_WDG_STAT1) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT2 (1 << 2) /* Bit 2: Status of functional reset sequence process FUNC2 when POR_WDG overflows (POR_WDG_STAT2) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT3 (1 << 3) /* Bit 3: Status of functional reset sequence process FUNC3 when POR_WDG overflows (POR_WDG_STAT3) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT4 (1 << 4) /* Bit 4: Status of functional reset sequence process FUNC4 when POR_WDG overflows (POR_WDG_STAT4) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT5 (1 << 5) /* Bit 5: Status of functional reset sequence process FUNC5 when POR_WDG overflows (POR_WDG_STAT5) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT6 (1 << 6) /* Bit 6: Status of functional reset sequence process FUNC6 when POR_WDG overflows (POR_WDG_STAT6) */
+ /* Bits 7-9: Reserved */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT10 (1 << 10) /* Bit 10: Status of functional reset sequence process FUNC7 when POR_WDG overflows (POR_WDG_STAT10) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT11 (1 << 11) /* Bit 11: Status of functional reset sequence process FUNC8 when POR_WDG overflows (POR_WDG_STAT11) */
+ /* Bits 12-13: Reserved */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT14 (1 << 14) /* Bit 14: Status of functional reset sequence process FUNC9 when POR_WDG overflows (POR_WDG_STAT14) */
+ /* Bits 15-16: Reserved */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT17 (1 << 17) /* Bit 17: Status of functional reset sequence process FUNC10 when POR_WDG overflows (POR_WDG_STAT17) */
+ /* Bits 18-19: Reserved */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT20 (1 << 20) /* Bit 20: Status of functional reset sequence process DEST0 when POR_WDG overflows (POR_WDG_STAT20) */
+ /* Bits 21-28: Reserved */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT29 (1 << 29) /* Bit 29: Status of standby entry request initiated by MC_ME when POR_WDG overflows (POR_WDG_STAT29) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT30 (1 << 30) /* Bit 30: Status of standby exit acknowledgement by MC_PCU when POR_WDG overflows (POR_WDG_STAT30) */
+#define DCM_GPR_DCMROPP1_POR_WDG_STAT31 (1 << 31) /* Bit 31: MC_RGM reset event (if occurred) while the device is in STANDBY mode (POR_WDG_STAT31) */
+
+/* Read Only GPR On PMCPOR Reset Register 2 (DCMROPP2) */
+
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT32 (1 << 0) /* Bit 0: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT32) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT33 (1 << 1) /* Bit 1: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT33) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT34 (1 << 2) /* Bit 2: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT34) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT35 (1 << 3) /* Bit 3: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT35) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT36 (1 << 4) /* Bit 4: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT36) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT37 (1 << 5) /* Bit 5: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT37) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT38 (1 << 6) /* Bit 6: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT38) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT39 (1 << 7) /* Bit 7: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT39) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT40 (1 << 8) /* Bit 8: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT40) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT41 (1 << 9) /* Bit 9: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT41) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT42 (1 << 10) /* Bit 10: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT42) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT43 (1 << 11) /* Bit 11: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT43) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT44 (1 << 12) /* Bit 12: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT44) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT45 (1 << 13) /* Bit 13: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT45) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT46 (1 << 14) /* Bit 14: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT46) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT47 (1 << 15) /* Bit 15: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT47) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT48 (1 << 16) /* Bit 16: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT48) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT49 (1 << 17) /* Bit 17: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT49) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT50 (1 << 18) /* Bit 18: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT50) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT51 (1 << 19) /* Bit 19: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT51) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT52 (1 << 20) /* Bit 20: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT52) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT53 (1 << 21) /* Bit 21: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT53) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT54 (1 << 22) /* Bit 22: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT54) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT55 (1 << 23) /* Bit 23: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT55) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT56 (1 << 24) /* Bit 24: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT56) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT57 (1 << 25) /* Bit 25: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT57) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT58 (1 << 26) /* Bit 26: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT58) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT59 (1 << 27) /* Bit 27: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT59) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT60 (1 << 28) /* Bit 28: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT60) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT61 (1 << 29) /* Bit 29: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT61) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT62 (1 << 30) /* Bit 30: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT62) */
+#define DCM_GPR_DCMROPP2_POR_WDG_STAT63 (1 << 31) /* Bit 31: MC_RGM functional/external event status register when POR_WDG overflows (POR_WDG_STAT63) */
+
+/* Read Only GPR On PMCPOR Reset Register 3 (DCMROPP3) */
+
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT64 (1 << 0) /* Bit 0: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT64) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT65 (1 << 1) /* Bit 1: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT65) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT66 (1 << 2) /* Bit 2: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT66) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT67 (1 << 3) /* Bit 3: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT67) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT68 (1 << 4) /* Bit 4: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT68) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT69 (1 << 5) /* Bit 5: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT69) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT70 (1 << 6) /* Bit 6: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT70) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT71 (1 << 7) /* Bit 7: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT71) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT72 (1 << 8) /* Bit 8: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT72) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT73 (1 << 9) /* Bit 9: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT73) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT74 (1 << 10) /* Bit 10: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT74) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT75 (1 << 11) /* Bit 11: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT75) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT76 (1 << 12) /* Bit 12: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT76) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT77 (1 << 13) /* Bit 13: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT77) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT78 (1 << 14) /* Bit 14: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT78) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT79 (1 << 15) /* Bit 15: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT79) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT80 (1 << 16) /* Bit 16: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT80) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT81 (1 << 17) /* Bit 17: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT81) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT82 (1 << 18) /* Bit 18: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT82) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT83 (1 << 19) /* Bit 19: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT83) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT84 (1 << 20) /* Bit 20: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT84) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT85 (1 << 21) /* Bit 21: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT85) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT86 (1 << 22) /* Bit 22: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT86) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT87 (1 << 23) /* Bit 23: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT87) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT88 (1 << 24) /* Bit 24: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT88) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT89 (1 << 25) /* Bit 25: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT89) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT90 (1 << 26) /* Bit 26: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT90) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT91 (1 << 27) /* Bit 27: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT91) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT92 (1 << 28) /* Bit 28: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT92) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT93 (1 << 29) /* Bit 29: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT93) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT94 (1 << 30) /* Bit 30: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT94) */
+#define DCM_GPR_DCMROPP3_POR_WDG_STAT95 (1 << 31) /* Bit 31: MC_RGM destructive event status register when POR_WDG overflows (POR_WDG_STAT95) */
+
+/* Read Only GPR On PMCPOR Reset Register 4 (DCMROPP4) */
+
+#define DCM_GPR_DCMROPP4_POR_WDG_STAT96 (1 << 0) /* Bit 0: POR_WDG reset event if POR_WDG initiates a POR sequence (POR_WDG_STAT96) */
+ /* Bits 1-31: Reserved */
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DCM_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
new file mode 100644
index 0000000000..97cd32ebbc
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_dmamux.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* DMAMUX Register Offsets **************************************************/
+
+#define S32K3XX_DMAMUX_CHCFG3_OFFSET (0x00) /* Channel Configuration Register 3 (CHCFG3) */
+#define S32K3XX_DMAMUX_CHCFG2_OFFSET (0x01) /* Channel Configuration Register 2 (CHCFG2) */
+#define S32K3XX_DMAMUX_CHCFG1_OFFSET (0x02) /* Channel Configuration Register 1 (CHCFG1) */
+#define S32K3XX_DMAMUX_CHCFG0_OFFSET (0x03) /* Channel Configuration Register 0 (CHCFG0) */
+#define S32K3XX_DMAMUX_CHCFG7_OFFSET (0x04) /* Channel Configuration Register 7 (CHCFG7) */
+#define S32K3XX_DMAMUX_CHCFG6_OFFSET (0x05) /* Channel Configuration Register 6 (CHCFG6) */
+#define S32K3XX_DMAMUX_CHCFG5_OFFSET (0x06) /* Channel Configuration Register 5 (CHCFG5) */
+#define S32K3XX_DMAMUX_CHCFG4_OFFSET (0x07) /* Channel Configuration Register 4 (CHCFG4) */
+#define S32K3XX_DMAMUX_CHCFG11_OFFSET (0x08) /* Channel Configuration Register 11 (CHCFG11) */
+#define S32K3XX_DMAMUX_CHCFG10_OFFSET (0x09) /* Channel Configuration Register 10 (CHCFG10) */
+#define S32K3XX_DMAMUX_CHCFG9_OFFSET (0x0a) /* Channel Configuration Register 9 (CHCFG9) */
+#define S32K3XX_DMAMUX_CHCFG8_OFFSET (0x0b) /* Channel Configuration Register 8 (CHCFG8) */
+#define S32K3XX_DMAMUX_CHCFG15_OFFSET (0x0c) /* Channel Configuration Register 15 (CHCFG15) */
+#define S32K3XX_DMAMUX_CHCFG14_OFFSET (0x0d) /* Channel Configuration Register 14 (CHCFG14) */
+#define S32K3XX_DMAMUX_CHCFG13_OFFSET (0x0e) /* Channel Configuration Register 13 (CHCFG13) */
+#define S32K3XX_DMAMUX_CHCFG12_OFFSET (0x0f) /* Channel Configuration Register 12 (CHCFG12) */
+
+#define S32K3XX_DMAMUX_CHCFG_OFFSET(n) ((n) + 3 - 2 * ((n) % 4))
+
+#define S32K3XX_DMAMUX0_CHCFG(n) (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG_OFFSET(n))
+#define S32K3XX_DMAMUX1_CHCFG(n) (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG_OFFSET(n))
+
+/* DMAMUX Register Addresses ************************************************/
+
+#define S32K3XX_DMAMUX0_CHCFG3 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG3_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG2 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG2_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG1 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG1_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG0 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG0_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG7 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG7_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG6 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG6_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG5 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG5_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG4 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG4_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG11 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG11_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG10 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG10_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG9 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG9_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG8 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG8_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG15 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG15_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG14 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG14_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG13 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG13_OFFSET)
+#define S32K3XX_DMAMUX0_CHCFG12 (S32K3XX_DMAMUX0_BASE + S32K3XX_DMAMUX_CHCFG12_OFFSET)
+
+#define S32K3XX_DMAMUX1_CHCFG3 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG3_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG2 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG2_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG1 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG1_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG0 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG0_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG7 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG7_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG6 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG6_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG5 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG5_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG4 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG4_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG11 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG11_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG10 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG10_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG9 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG9_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG8 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG8_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG15 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG15_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG14 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG14_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG13 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG13_OFFSET)
+#define S32K3XX_DMAMUX1_CHCFG12 (S32K3XX_DMAMUX1_BASE + S32K3XX_DMAMUX_CHCFG12_OFFSET)
+
+/* DMAMUX Register Bitfield Definitions *************************************/
+
+#define DMAMUX_CHCFG_SOURCE_SHIFT (0) /* Bits 0-5: DMA Channel Source (SOURCE) */
+#define DMAMUX_CHCFG_SOURCE_MASK (0x3f << DMAMUX_CHCFG_SOURCE_SHIFT)
+#define DMAMUX_CHCFG_TRIG (1 << 6) /* Bit 6: DMA Channel Trigger Enable (TRIG) */
+#define DMAMUX_CHCFG_ENBL (1 << 7) /* Bit 7: DMA Channel Enable (ENBL) */
+#define DMAMUX_CHCFG_MASK (0xff) /* Bits 0-7 */
+
+#define DMAMUX_CHCFG_DMAMUX1 (1 << 15) /* Bit 15: DMAMUX1 Selection */
+
+/* DMA Request sources */
+
+/** edma_mux0 **/
+
+#define DMA_REQ_DISABLED0 0 ///< Channel disabled (default)
+#define DMA_REQ_SIUL_0 1 ///< SIUL DMA request 0
+#define DMA_REQ_SIUL_1 2 ///< SIUL DMA request 1
+#define DMA_REQ_SIUL_2 3 ///< SIUL DMA request 2
+#define DMA_REQ_SIUL_3 4 ///< SIUL DMA request 3
+#define DMA_REQ_SIUL_4 5 ///< SIUL DMA request 4
+#define DMA_REQ_SIUL_5 6 ///< SIUL DMA request 5
+#define DMA_REQ_SIUL_6 7 ///< SIUL DMA request 6
+#define DMA_REQ_SIUL_7 8 ///< SIUL DMA request 7
+#define DMA_REQ_BCTU_FIFO1 10 ///< BCTU DMA FIFO1 request
+#define DMA_REQ_BCTU_0 10 ///< BCTU DMA request 0
+#define DMA_REQ_BCTU_1 11 ///< BCTU DMA request 1
+#define DMA_REQ_EMIOS0_0 12 ///< eMIOS0 DMA request ch0
+#define DMA_REQ_EMIOS0_1 13 ///< eMIOS0 DMA request ch1
+#define DMA_REQ_EMIOS0_9 14 ///< eMIOS0 DMA request ch9
+#define DMA_REQ_EMIOS0_10 15 ///< eMIOS0 DMA request ch10
+#define DMA_REQ_EMIOS1_0 16 ///< eMIOS1 DMA request ch0
+#define DMA_REQ_EMIOS1_1 17 ///< eMIOS1 DMA request ch1
+#define DMA_REQ_EMIOS1_9 18 ///< eMIOS1 DMA request ch9
+#define DMA_REQ_EMIOS1_10 19 ///< eMIOS1 DMA request ch10
+#define DMA_REQ_EMIOS2_0 20 ///< eMIOS2 DMA request ch0
+#define DMA_REQ_EMIOS2_1 21 ///< eMIOS2 DMA request ch1
+#define DMA_REQ_EMIOS2_9 22 ///< eMIOS2 DMA request ch9
+#define DMA_REQ_EMIOS2_10 23 ///< eMIOS2 DMA request ch10
+#define DMA_REQ_LCU0_0 24 ///< LCU0 DMA request 0
+#define DMA_REQ_LCU1_0 25 ///< LCU1 DMA request 0
+#define DMA_REQ_RESERVED1 26 ///< RESERVED
+#define DMA_REQ_RESERVED2 27 ///< RESERVED
+#define DMA_REQ_RESERVED3 28 ///< RESERVED
+#define DMA_REQ_FLEXCAN0 29 ///< FLEXCAN0 DMA request
+#define DMA_REQ_FLEXCAN1 30 ///< FLEXCAN1 DMA request
+#define DMA_REQ_FLEXCAN2 31 ///< FLEXCAN2 DMA request
+#define DMA_REQ_FLEXCAN3 32 ///< FLEXCAN3 DMA request
+#define DMA_REQ_FLEXIO_0 33 ///< FLEXIO DMA shifter0 | timer0 request
+#define DMA_REQ_FLEXIO_1 34 ///< FLEXIO DMA shifter1 | timer1 request
+#define DMA_REQ_FLEXIO_2 35 ///< FLEXIO DMA shifter2 | timer2 request
+#define DMA_REQ_FLEXIO_3 36 ///< FLEXIO DMA shifter3 | timer3 request
+#define DMA_REQ_LPUART08_TX 37 ///< LPUART0 | LPUART8 DMA transmit request
+#define DMA_REQ_LPUART08_RX 38 ///< LPUART0 | LPUART8 DMA receive request
+#define DMA_REQ_LPUART19_TX 39 ///< LPUART1 | LPUART9 DMA transmit request
+#define DMA_REQ_LPUART19_RX 40 ///< LPUART1 | LPUART9 DMA receive request
+#define DMA_REQ_LPI2C0_RX 41 ///< LPI2C0 DMA receive | receive slave request
+#define DMA_REQ_LPI2C0_TX 42 ///< LPI2C0 DMA transmit | transmit slave request
+#define DMA_REQ_LPSPI0_TX 43 ///< LPSPI0 DMA transmit request
+#define DMA_REQ_LPSPI0_RX 44 ///< LPSPI0 DMA receive request
+#define DMA_REQ_LPSPI1_TX 45 ///< LPSPI1 DMA transmit request
+#define DMA_REQ_LPSPI1_RX 46 ///< LPSPI1 DMA receive request
+#define DMA_REQ_LPSPI2_TX 47 ///< LPSPI2 DMA transmit request
+#define DMA_REQ_LPSPI2_RX 48 ///< LPSPI2 DMA receive request
+#define DMA_REQ_LPSPI3_TX 49 ///< LPSPI3 DMA transmit request
+#define DMA_REQ_LPSPI3_RX 50 ///< LPSPI3 DMA receive request
+#define DMA_REQ_I3C0_RX 51 ///< I3C0 DMA receive request
+#define DMA_REQ_I3C0_TX 52 ///< I3C0 DMA transmit request
+#define DMA_REQ_QSPI_RX 53 ///< QSPI DMA receive buffer drain request
+#define DMA_REQ_QSPI_TX 54 ///< QSPI DMA transmit buffer fill request
+#define DMA_REQ_SAI0_RX 55 ///< SAI0 DMA receive request
+#define DMA_REQ_SAI0_TX 56 ///< SAI0 DMA transmit request
+#define DMA_REQ_RESERVED4 57 ///< RESERVED
+#define DMA_REQ_ADC0 58 ///< ADC0 DMA request
+#define DMA_REQ_ADC1 59 ///< ADC1 DMA request
+#define DMA_REQ_ADC2 60 ///< ADC2 DMA request
+#define DMA_REQ_LPCMP0 61 ///< LPCMP0 DMA request
+#define DMA_REQ_ENABLED0 62 ///< Always enabled
+#define DMA_REQ_ENABLED1 63 ///< Always enabled */
+
+/** edma_mux1 **/
+
+#define DMA_REQ_DISABLED1 DMAMUX_CHCFG_DMAMUX1 | 0 ///< Channel disabled (default)
+#define DMA_REQ_SIUL_8 DMAMUX_CHCFG_DMAMUX1 | 1 ///< SIUL DMA request 8
+#define DMA_REQ_SIUL_9 DMAMUX_CHCFG_DMAMUX1 | 2 ///< SIUL DMA request 9
+#define DMA_REQ_SIUL_10 DMAMUX_CHCFG_DMAMUX1 | 3 ///< SIUL DMA request 10
+#define DMA_REQ_SIUL_11 DMAMUX_CHCFG_DMAMUX1 | 4 ///< SIUL DMA request 11
+#define DMA_REQ_SIUL_12 DMAMUX_CHCFG_DMAMUX1 | 5 ///< SIUL DMA request 12
+#define DMA_REQ_SIUL_13 DMAMUX_CHCFG_DMAMUX1 | 6 ///< SIUL DMA request 13
+#define DMA_REQ_SIUL_14 DMAMUX_CHCFG_DMAMUX1 | 7 ///< SIUL DMA request 14
+#define DMA_REQ_SIUL_15 DMAMUX_CHCFG_DMAMUX1 | 8 ///< SIUL DMA request 15
+#define DMA_REQ_BCTU_FIFO2 DMAMUX_CHCFG_DMAMUX1 | 9 ///< BCTU DMA FIFO2 request
+#define DMA_REQ_BCTU_2 DMAMUX_CHCFG_DMAMUX1 | 10 ///< BCTU DMA request 2
+#define DMA_REQ_EMIOS0_16 DMAMUX_CHCFG_DMAMUX1 | 11 ///< eMIOS0 DMA request ch16
+#define DMA_REQ_EMIOS0_17 DMAMUX_CHCFG_DMAMUX1 | 12 ///< eMIOS0 DMA request ch17
+#define DMA_REQ_EMIOS0_18 DMAMUX_CHCFG_DMAMUX1 | 13 ///< eMIOS0 DMA request ch18
+#define DMA_REQ_EMIOS0_19 DMAMUX_CHCFG_DMAMUX1 | 14 ///< eMIOS0 DMA request ch19
+#define DMA_REQ_EMIOS1_16 DMAMUX_CHCFG_DMAMUX1 | 15 ///< eMIOS1 DMA request ch16
+#define DMA_REQ_EMIOS1_17 DMAMUX_CHCFG_DMAMUX1 | 16 ///< eMIOS1 DMA request ch17
+#define DMA_REQ_EMIOS1_18 DMAMUX_CHCFG_DMAMUX1 | 17 ///< eMIOS1 DMA request ch18
+#define DMA_REQ_EMIOS1_19 DMAMUX_CHCFG_DMAMUX1 | 18 ///< eMIOS1 DMA request ch19
+#define DMA_REQ_EMIOS2_16 DMAMUX_CHCFG_DMAMUX1 | 19 ///< eMIOS2 DMA request ch16
+#define DMA_REQ_EMIOS2_17 DMAMUX_CHCFG_DMAMUX1 | 20 ///< eMIOS2 DMA request ch17
+#define DMA_REQ_EMIOS2_18 DMAMUX_CHCFG_DMAMUX1 | 21 ///< eMIOS2 DMA request ch18
+#define DMA_REQ_EMIOS2_19 DMAMUX_CHCFG_DMAMUX1 | 22 ///< eMIOS2 DMA request ch19
+#define DMA_REQ_LCU0_1 DMAMUX_CHCFG_DMAMUX1 | 23 ///< LCU0 DMA request 1
+#define DMA_REQ_LCU0_2 DMAMUX_CHCFG_DMAMUX1 | 24 ///< LCU1 DMA request 2
+#define DMA_REQ_LCU1_1 DMAMUX_CHCFG_DMAMUX1 | 25 ///< LCU1 DMA request 1
+#define DMA_REQ_LCU1_2 DMAMUX_CHCFG_DMAMUX1 | 26 ///< LCU1 DMA request 2
+#define DMA_REQ_ENET_0 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[0] DMA request
+#define DMA_REQ_ENET_1 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[1] DMA request
+#define DMA_REQ_ENET_2 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[2] DMA request
+#define DMA_REQ_ENET_3 DMAMUX_CHCFG_DMAMUX1 | 27 ///< ENET IEEE 1588 PTP timer ch[3] DMA request
+#define DMA_REQ_RESERVED5 DMAMUX_CHCFG_DMAMUX1 | 28 ///< RESERVED
+#define DMA_REQ_RESERVED6 DMAMUX_CHCFG_DMAMUX1 | 29 ///< RESERVED
+#define DMA_REQ_FLECAN4 DMAMUX_CHCFG_DMAMUX1 | 30 ///< FLEXCAN4 DMA request
+#define DMA_REQ_FLECAN5 DMAMUX_CHCFG_DMAMUX1 | 31 ///< FLEXCAN5 DMA request
+#define DMA_REQ_RESERVED7 DMAMUX_CHCFG_DMAMUX1 | 32 ///< RESERVED
+#define DMA_REQ_RESERVED8 DMAMUX_CHCFG_DMAMUX1 | 33 ///< RESERVED
+#define DMA_REQ_FLEXIO_4 DMAMUX_CHCFG_DMAMUX1 | 34 ///< FLEXIO DMA shifter4 | timer4 request
+#define DMA_REQ_FLEXIO_5 DMAMUX_CHCFG_DMAMUX1 | 35 ///< FLEXIO DMA shifter5 | timer5 request
+#define DMA_REQ_FLEXIO_6 DMAMUX_CHCFG_DMAMUX1 | 36 ///< FLEXIO DMA shifter6 | timer6 request
+#define DMA_REQ_FLEXIO_7 DMAMUX_CHCFG_DMAMUX1 | 37 ///< FLEXIO DMA shifter7 | timer7 request
+#define DMA_REQ_LPUART210_TX DMAMUX_CHCFG_DMAMUX1 | 38 ///< LPUART2 | LPUART10 DMA transmit request
+#define DMA_REQ_LPUART210_RX DMAMUX_CHCFG_DMAMUX1 | 39 ///< LPUART2 | LPUART10 DMA receive request
+#define DMA_REQ_LPUART311_TX DMAMUX_CHCFG_DMAMUX1 | 40 ///< LPUART3 | LPUART11 DMA transmit request
+#define DMA_REQ_LPUART311_RX DMAMUX_CHCFG_DMAMUX1 | 41 ///< LPUART3 | LPUART11 DMA receive request
+#define DMA_REQ_LPUART412_TX DMAMUX_CHCFG_DMAMUX1 | 42 ///< LPUART4 | LPUART12 DMA transmit request
+#define DMA_REQ_LPUART412_RX DMAMUX_CHCFG_DMAMUX1 | 43 ///< LPUART4 | LPUART12 DMA receive request
+#define DMA_REQ_LPUART513_TX DMAMUX_CHCFG_DMAMUX1 | 44 ///< LPUART5 | LPUART13 DMA transmit request
+#define DMA_REQ_LPUART513_RX DMAMUX_CHCFG_DMAMUX1 | 45 ///< LPUART5 | LPUART13 DMA receive request
+#define DMA_REQ_LPUART614_TX DMAMUX_CHCFG_DMAMUX1 | 46 ///< LPUART6 | LPUART14 DMA transmit request
+#define DMA_REQ_LPUART614_RX DMAMUX_CHCFG_DMAMUX1 | 47 ///< LPUART6 | LPUART14 DMA receive request
+#define DMA_REQ_LPUART715_TX DMAMUX_CHCFG_DMAMUX1 | 48 ///< LPUART7 | LPUART15 DMA transmit request
+#define DMA_REQ_LPUART715_RX DMAMUX_CHCFG_DMAMUX1 | 49 ///< LPUART7 | LPUART15 DMA receive request
+#define DMA_REQ_LPI2C1_RX DMAMUX_CHCFG_DMAMUX1 | 50 ///< LPI2C1 DMA receive | receive slave request
+#define DMA_REQ_LPI2C1_TX DMAMUX_CHCFG_DMAMUX1 | 51 ///< LPI2C1 DMA transmit | transmit slave request
+#define DMA_REQ_LPSPI4_TX DMAMUX_CHCFG_DMAMUX1 | 52 ///< LPSPI4 DMA transmit request
+#define DMA_REQ_LPSPI4_RX DMAMUX_CHCFG_DMAMUX1 | 53 ///< LPSPI4 DMA receive request
+#define DMA_REQ_LPSPI5_TX DMAMUX_CHCFG_DMAMUX1 | 54 ///< LPSPI5 DMA transmit request
+#define DMA_REQ_LPSPI5_RX DMAMUX_CHCFG_DMAMUX1 | 55 ///< LPSPI5 DMA receive request
+#define DMA_REQ_SAI1_RX DMAMUX_CHCFG_DMAMUX1 | 56 ///< SAI1 DMA RX request
+#define DMA_REQ_SAI1_TX DMAMUX_CHCFG_DMAMUX1 | 57 ///< SAI1 DMA TX request
+#define DMA_REQ_RESERVED9 DMAMUX_CHCFG_DMAMUX1 | 58 ///< RESERVED
+#define DMA_REQ_RESERVED10 DMAMUX_CHCFG_DMAMUX1 | 59 ///< RESERVED
+#define DMA_REQ_LPCMP1 DMAMUX_CHCFG_DMAMUX1 | 60 ///< LPCMP1 DMA request
+#define DMA_REQ_LPCMP2 DMAMUX_CHCFG_DMAMUX1 | 61 ///< LPCMP2 DMA request
+#define DMA_REQ_ENABLED2 DMAMUX_CHCFG_DMAMUX1 | 62 ///< Always enabled
+#define DMA_REQ_ENABLED3 DMAMUX_CHCFG_DMAMUX1 | 63 ///< Always enabled
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_DMAMUX_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
new file mode 100644
index 0000000000..5fcead5f76
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
@@ -0,0 +1,1433 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define S32K3XX_EDMA_NCHANNELS 32
+
+/* eDMA Register Offsets ****************************************************/
+
+#define S32K3XX_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
+#define S32K3XX_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
+#define S32K3XX_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
+#define S32K3XX_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
+
+#define S32K3XX_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+/* eDMA Register Addresses **************************************************/
+
+#define S32K3XX_EDMA_CSR (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CSR_OFFSET)
+#define S32K3XX_EDMA_ES (S32K3XX_EDMA_BASE + S32K3XX_EDMA_ES_OFFSET)
+#define S32K3XX_EDMA_INT (S32K3XX_EDMA_BASE + S32K3XX_EDMA_INT_OFFSET)
+#define S32K3XX_EDMA_HRS (S32K3XX_EDMA_BASE + S32K3XX_EDMA_HRS_OFFSET)
+#define S32K3XX_EDMA_CH_GRPRI(n) (S32K3XX_EDMA_BASE + S32K3XX_EDMA_CH_GRPRI_OFFSET(n))
+
+/* eDMA Transfer Control Descriptor (TCD) Register Offsets ******************/
+
+#define S32K3XX_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH0_CSR_OFFSET (0x000000) /* Channel 0 Control and Status Register (CH0_CSR) */
+#define S32K3XX_EDMA_CH0_ES_OFFSET (0x000004) /* Channel 0 Error Status Register (CH0_ES) */
+#define S32K3XX_EDMA_CH0_INT_OFFSET (0x000008) /* Channel 0 Interrupt Status Register (CH0_INT) */
+#define S32K3XX_EDMA_CH0_SBR_OFFSET (0x00000c) /* Channel 0 System Bus Register (CH0_SBR) */
+#define S32K3XX_EDMA_CH0_PRI_OFFSET (0x000010) /* Channel 0 Priority Register (CH0_PRI) */
+#define S32K3XX_EDMA_TCD0_SADDR_OFFSET (0x000020) /* TCD0 Source Address Register (TCD0_SADDR) */
+#define S32K3XX_EDMA_TCD0_SOFF_OFFSET (0x000024) /* TCD0 Signed Source Address Offset Register (TCD0_SOFF) */
+#define S32K3XX_EDMA_TCD0_ATTR_OFFSET (0x000026) /* TCD0 Transfer Attributes (TCD0_ATTR) */
+#define S32K3XX_EDMA_TCD0_NBYTES_OFFSET (0x000028) /* TCD0 Transfer Size (TCD0_NBYTES) */
+#define S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET (0x00002c) /* TCD0 Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD0_DADDR_OFFSET (0x000030) /* TCD0 Destination Address Register (TCD0_DADDR) */
+#define S32K3XX_EDMA_TCD0_DOFF_OFFSET (0x000034) /* TCD0 Signed Destination Address Offset Register (TCD0_DOFF) */
+#define S32K3XX_EDMA_TCD0_CITER_OFFSET (0x000036) /* TCD0 Current Major Loop Count Register (TCD0_CITER) */
+#define S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET (0x000038) /* TCD0 Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD0_CSR_OFFSET (0x00003c) /* TCD0 Control and Status Register (TCD0_CSR) */
+#define S32K3XX_EDMA_TCD0_BITER_OFFSET (0x00003e) /* TCD0 Beginning Major Loop Count Register (TCD0_BITER) */
+
+#define S32K3XX_EDMA_CH1_CSR_OFFSET (0x004000) /* Channel 1 Control and Status Register (CH1_CSR) */
+#define S32K3XX_EDMA_CH1_ES_OFFSET (0x004004) /* Channel 1 Error Status Register (CH1_ES) */
+#define S32K3XX_EDMA_CH1_INT_OFFSET (0x004008) /* Channel 1 Interrupt Status Register (CH1_INT) */
+#define S32K3XX_EDMA_CH1_SBR_OFFSET (0x00400c) /* Channel 1 System Bus Register (CH1_SBR) */
+#define S32K3XX_EDMA_CH1_PRI_OFFSET (0x004010) /* Channel 1 Priority Register (CH1_PRI) */
+#define S32K3XX_EDMA_TCD1_SADDR_OFFSET (0x004020) /* TCD1 Source Address Register (TCD1_SADDR) */
+#define S32K3XX_EDMA_TCD1_SOFF_OFFSET (0x004024) /* TCD1 Signed Source Address Offset Register (TCD1_SOFF) */
+#define S32K3XX_EDMA_TCD1_ATTR_OFFSET (0x004026) /* TCD1 Transfer Attributes (TCD1_ATTR) */
+#define S32K3XX_EDMA_TCD1_NBYTES_OFFSET (0x004028) /* TCD1 Transfer Size (TCD1_NBYTES) */
+#define S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET (0x00402c) /* TCD1 Last Source Address Adjustment / Store DADDR Address Register (TCD1_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD1_DADDR_OFFSET (0x004030) /* TCD1 Destination Address Register (TCD1_DADDR) */
+#define S32K3XX_EDMA_TCD1_DOFF_OFFSET (0x004034) /* TCD1 Signed Destination Address Offset Register (TCD1_DOFF) */
+#define S32K3XX_EDMA_TCD1_CITER_OFFSET (0x004036) /* TCD1 Current Major Loop Count Register (TCD1_CITER) */
+#define S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET (0x004038) /* TCD1 Last Destination Address Adjustment / Scatter Gather Address Register (TCD1_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD1_CSR_OFFSET (0x00403c) /* TCD1 Control and Status Register (TCD1_CSR) */
+#define S32K3XX_EDMA_TCD1_BITER_OFFSET (0x00403e) /* TCD1 Beginning Major Loop Count Register (TCD1_BITER) */
+
+#define S32K3XX_EDMA_CH2_CSR_OFFSET (0x008000) /* Channel 2 Control and Status Register (CH2_CSR) */
+#define S32K3XX_EDMA_CH2_ES_OFFSET (0x008004) /* Channel 2 Error Status Register (CH2_ES) */
+#define S32K3XX_EDMA_CH2_INT_OFFSET (0x008008) /* Channel 2 Interrupt Status Register (CH2_INT) */
+#define S32K3XX_EDMA_CH2_SBR_OFFSET (0x00800c) /* Channel 2 System Bus Register (CH2_SBR) */
+#define S32K3XX_EDMA_CH2_PRI_OFFSET (0x008010) /* Channel 2 Priority Register (CH2_PRI) */
+#define S32K3XX_EDMA_TCD2_SADDR_OFFSET (0x008020) /* TCD2 Source Address Register (TCD2_SADDR) */
+#define S32K3XX_EDMA_TCD2_SOFF_OFFSET (0x008024) /* TCD2 Signed Source Address Offset Register (TCD2_SOFF) */
+#define S32K3XX_EDMA_TCD2_ATTR_OFFSET (0x008026) /* TCD2 Transfer Attributes (TCD2_ATTR) */
+#define S32K3XX_EDMA_TCD2_NBYTES_OFFSET (0x008028) /* TCD2 Transfer Size (TCD2_NBYTES) */
+#define S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET (0x00802c) /* TCD2 Last Source Address Adjustment / Store DADDR Address Register (TCD2_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD2_DADDR_OFFSET (0x008030) /* TCD2 Destination Address Register (TCD2_DADDR) */
+#define S32K3XX_EDMA_TCD2_DOFF_OFFSET (0x008034) /* TCD2 Signed Destination Address Offset Register (TCD2_DOFF) */
+#define S32K3XX_EDMA_TCD2_CITER_OFFSET (0x008036) /* TCD2 Current Major Loop Count Register (TCD2_CITER) */
+#define S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET (0x008038) /* TCD2 Last Destination Address Adjustment / Scatter Gather Address Register (TCD2_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD2_CSR_OFFSET (0x00803c) /* TCD2 Control and Status Register (TCD2_CSR) */
+#define S32K3XX_EDMA_TCD2_BITER_OFFSET (0x00803e) /* TCD2 Beginning Major Loop Count Register (TCD2_BITER) */
+
+#define S32K3XX_EDMA_CH3_CSR_OFFSET (0x00c000) /* Channel 3 Control and Status Register (CH3_CSR) */
+#define S32K3XX_EDMA_CH3_ES_OFFSET (0x00c004) /* Channel 3 Error Status Register (CH3_ES) */
+#define S32K3XX_EDMA_CH3_INT_OFFSET (0x00c008) /* Channel 3 Interrupt Status Register (CH3_INT) */
+#define S32K3XX_EDMA_CH3_SBR_OFFSET (0x00c00c) /* Channel 3 System Bus Register (CH3_SBR) */
+#define S32K3XX_EDMA_CH3_PRI_OFFSET (0x00c010) /* Channel 3 Priority Register (CH3_PRI) */
+#define S32K3XX_EDMA_TCD3_SADDR_OFFSET (0x00c020) /* TCD3 Source Address Register (TCD3_SADDR) */
+#define S32K3XX_EDMA_TCD3_SOFF_OFFSET (0x00c024) /* TCD3 Signed Source Address Offset Register (TCD3_SOFF) */
+#define S32K3XX_EDMA_TCD3_ATTR_OFFSET (0x00c026) /* TCD3 Transfer Attributes (TCD3_ATTR) */
+#define S32K3XX_EDMA_TCD3_NBYTES_OFFSET (0x00c028) /* TCD3 Transfer Size (TCD3_NBYTES) */
+#define S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET (0x00c02c) /* TCD3 Last Source Address Adjustment / Store DADDR Address Register (TCD3_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD3_DADDR_OFFSET (0x00c030) /* TCD3 Destination Address Register (TCD3_DADDR) */
+#define S32K3XX_EDMA_TCD3_DOFF_OFFSET (0x00c034) /* TCD3 Signed Destination Address Offset Register (TCD3_DOFF) */
+#define S32K3XX_EDMA_TCD3_CITER_OFFSET (0x00c036) /* TCD3 Current Major Loop Count Register (TCD3_CITER) */
+#define S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET (0x00c038) /* TCD3 Last Destination Address Adjustment / Scatter Gather Address Register (TCD3_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD3_CSR_OFFSET (0x00c03c) /* TCD3 Control and Status Register (TCD3_CSR) */
+#define S32K3XX_EDMA_TCD3_BITER_OFFSET (0x00c03e) /* TCD3 Beginning Major Loop Count Register (TCD3_BITER) */
+
+#define S32K3XX_EDMA_CH4_CSR_OFFSET (0x010000) /* Channel 4 Control and Status Register (CH4_CSR) */
+#define S32K3XX_EDMA_CH4_ES_OFFSET (0x010004) /* Channel 4 Error Status Register (CH4_ES) */
+#define S32K3XX_EDMA_CH4_INT_OFFSET (0x010008) /* Channel 4 Interrupt Status Register (CH4_INT) */
+#define S32K3XX_EDMA_CH4_SBR_OFFSET (0x01000c) /* Channel 4 System Bus Register (CH4_SBR) */
+#define S32K3XX_EDMA_CH4_PRI_OFFSET (0x010010) /* Channel 4 Priority Register (CH4_PRI) */
+#define S32K3XX_EDMA_TCD4_SADDR_OFFSET (0x010020) /* TCD4 Source Address Register (TCD4_SADDR) */
+#define S32K3XX_EDMA_TCD4_SOFF_OFFSET (0x010024) /* TCD4 Signed Source Address Offset Register (TCD4_SOFF) */
+#define S32K3XX_EDMA_TCD4_ATTR_OFFSET (0x010026) /* TCD4 Transfer Attributes (TCD4_ATTR) */
+#define S32K3XX_EDMA_TCD4_NBYTES_OFFSET (0x010028) /* TCD4 Transfer Size (TCD4_NBYTES) */
+#define S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET (0x01002c) /* TCD4 Last Source Address Adjustment / Store DADDR Address Register (TCD4_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD4_DADDR_OFFSET (0x010030) /* TCD4 Destination Address Register (TCD4_DADDR) */
+#define S32K3XX_EDMA_TCD4_DOFF_OFFSET (0x010034) /* TCD4 Signed Destination Address Offset Register (TCD4_DOFF) */
+#define S32K3XX_EDMA_TCD4_CITER_OFFSET (0x010036) /* TCD4 Current Major Loop Count Register (TCD4_CITER) */
+#define S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET (0x010038) /* TCD4 Last Destination Address Adjustment / Scatter Gather Address Register (TCD4_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD4_CSR_OFFSET (0x01003c) /* TCD4 Control and Status Register (TCD4_CSR) */
+#define S32K3XX_EDMA_TCD4_BITER_OFFSET (0x01003e) /* TCD4 Beginning Major Loop Count Register (TCD4_BITER) */
+
+#define S32K3XX_EDMA_CH5_CSR_OFFSET (0x014000) /* Channel 5 Control and Status Register (CH5_CSR) */
+#define S32K3XX_EDMA_CH5_ES_OFFSET (0x014004) /* Channel 5 Error Status Register (CH5_ES) */
+#define S32K3XX_EDMA_CH5_INT_OFFSET (0x014008) /* Channel 5 Interrupt Status Register (CH5_INT) */
+#define S32K3XX_EDMA_CH5_SBR_OFFSET (0x01400c) /* Channel 5 System Bus Register (CH5_SBR) */
+#define S32K3XX_EDMA_CH5_PRI_OFFSET (0x014010) /* Channel 5 Priority Register (CH5_PRI) */
+#define S32K3XX_EDMA_TCD5_SADDR_OFFSET (0x014020) /* TCD5 Source Address Register (TCD5_SADDR) */
+#define S32K3XX_EDMA_TCD5_SOFF_OFFSET (0x014024) /* TCD5 Signed Source Address Offset Register (TCD5_SOFF) */
+#define S32K3XX_EDMA_TCD5_ATTR_OFFSET (0x014026) /* TCD5 Transfer Attributes (TCD5_ATTR) */
+#define S32K3XX_EDMA_TCD5_NBYTES_OFFSET (0x014028) /* TCD5 Transfer Size (TCD5_NBYTES) */
+#define S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET (0x01402c) /* TCD5 Last Source Address Adjustment / Store DADDR Address Register (TCD5_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD5_DADDR_OFFSET (0x014030) /* TCD5 Destination Address Register (TCD5_DADDR) */
+#define S32K3XX_EDMA_TCD5_DOFF_OFFSET (0x014034) /* TCD5 Signed Destination Address Offset Register (TCD5_DOFF) */
+#define S32K3XX_EDMA_TCD5_CITER_OFFSET (0x014036) /* TCD5 Current Major Loop Count Register (TCD5_CITER) */
+#define S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET (0x014038) /* TCD5 Last Destination Address Adjustment / Scatter Gather Address Register (TCD5_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD5_CSR_OFFSET (0x01403c) /* TCD5 Control and Status Register (TCD5_CSR) */
+#define S32K3XX_EDMA_TCD5_BITER_OFFSET (0x01403e) /* TCD5 Beginning Major Loop Count Register (TCD5_BITER) */
+
+#define S32K3XX_EDMA_CH6_CSR_OFFSET (0x018000) /* Channel 6 Control and Status Register (CH6_CSR) */
+#define S32K3XX_EDMA_CH6_ES_OFFSET (0x018004) /* Channel 6 Error Status Register (CH6_ES) */
+#define S32K3XX_EDMA_CH6_INT_OFFSET (0x018008) /* Channel 6 Interrupt Status Register (CH6_INT) */
+#define S32K3XX_EDMA_CH6_SBR_OFFSET (0x01800c) /* Channel 6 System Bus Register (CH6_SBR) */
+#define S32K3XX_EDMA_CH6_PRI_OFFSET (0x018010) /* Channel 6 Priority Register (CH6_PRI) */
+#define S32K3XX_EDMA_TCD6_SADDR_OFFSET (0x018020) /* TCD6 Source Address Register (TCD6_SADDR) */
+#define S32K3XX_EDMA_TCD6_SOFF_OFFSET (0x018024) /* TCD6 Signed Source Address Offset Register (TCD6_SOFF) */
+#define S32K3XX_EDMA_TCD6_ATTR_OFFSET (0x018026) /* TCD6 Transfer Attributes (TCD6_ATTR) */
+#define S32K3XX_EDMA_TCD6_NBYTES_OFFSET (0x018028) /* TCD6 Transfer Size (TCD6_NBYTES) */
+#define S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET (0x01802c) /* TCD6 Last Source Address Adjustment / Store DADDR Address Register (TCD6_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD6_DADDR_OFFSET (0x018030) /* TCD6 Destination Address Register (TCD6_DADDR) */
+#define S32K3XX_EDMA_TCD6_DOFF_OFFSET (0x018034) /* TCD6 Signed Destination Address Offset Register (TCD6_DOFF) */
+#define S32K3XX_EDMA_TCD6_CITER_OFFSET (0x018036) /* TCD6 Current Major Loop Count Register (TCD6_CITER) */
+#define S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET (0x018038) /* TCD6 Last Destination Address Adjustment / Scatter Gather Address Register (TCD6_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD6_CSR_OFFSET (0x01803c) /* TCD6 Control and Status Register (TCD6_CSR) */
+#define S32K3XX_EDMA_TCD6_BITER_OFFSET (0x01803e) /* TCD6 Beginning Major Loop Count Register (TCD6_BITER) */
+
+#define S32K3XX_EDMA_CH7_CSR_OFFSET (0x01c000) /* Channel 7 Control and Status Register (CH7_CSR) */
+#define S32K3XX_EDMA_CH7_ES_OFFSET (0x01c004) /* Channel 7 Error Status Register (CH7_ES) */
+#define S32K3XX_EDMA_CH7_INT_OFFSET (0x01c008) /* Channel 7 Interrupt Status Register (CH7_INT) */
+#define S32K3XX_EDMA_CH7_SBR_OFFSET (0x01c00c) /* Channel 7 System Bus Register (CH7_SBR) */
+#define S32K3XX_EDMA_CH7_PRI_OFFSET (0x01c010) /* Channel 7 Priority Register (CH7_PRI) */
+#define S32K3XX_EDMA_TCD7_SADDR_OFFSET (0x01c020) /* TCD7 Source Address Register (TCD7_SADDR) */
+#define S32K3XX_EDMA_TCD7_SOFF_OFFSET (0x01c024) /* TCD7 Signed Source Address Offset Register (TCD7_SOFF) */
+#define S32K3XX_EDMA_TCD7_ATTR_OFFSET (0x01c026) /* TCD7 Transfer Attributes (TCD7_ATTR) */
+#define S32K3XX_EDMA_TCD7_NBYTES_OFFSET (0x01c028) /* TCD7 Transfer Size (TCD7_NBYTES) */
+#define S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET (0x01c02c) /* TCD7 Last Source Address Adjustment / Store DADDR Address Register (TCD7_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD7_DADDR_OFFSET (0x01c030) /* TCD7 Destination Address Register (TCD7_DADDR) */
+#define S32K3XX_EDMA_TCD7_DOFF_OFFSET (0x01c034) /* TCD7 Signed Destination Address Offset Register (TCD7_DOFF) */
+#define S32K3XX_EDMA_TCD7_CITER_OFFSET (0x01c036) /* TCD7 Current Major Loop Count Register (TCD7_CITER) */
+#define S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET (0x01c038) /* TCD7 Last Destination Address Adjustment / Scatter Gather Address Register (TCD7_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD7_CSR_OFFSET (0x01c03c) /* TCD7 Control and Status Register (TCD7_CSR) */
+#define S32K3XX_EDMA_TCD7_BITER_OFFSET (0x01c03e) /* TCD7 Beginning Major Loop Count Register (TCD7_BITER) */
+
+#define S32K3XX_EDMA_CH8_CSR_OFFSET (0x020000) /* Channel 8 Control and Status Register (CH8_CSR) */
+#define S32K3XX_EDMA_CH8_ES_OFFSET (0x020004) /* Channel 8 Error Status Register (CH8_ES) */
+#define S32K3XX_EDMA_CH8_INT_OFFSET (0x020008) /* Channel 8 Interrupt Status Register (CH8_INT) */
+#define S32K3XX_EDMA_CH8_SBR_OFFSET (0x02000c) /* Channel 8 System Bus Register (CH8_SBR) */
+#define S32K3XX_EDMA_CH8_PRI_OFFSET (0x020010) /* Channel 8 Priority Register (CH8_PRI) */
+#define S32K3XX_EDMA_TCD8_SADDR_OFFSET (0x020020) /* TCD8 Source Address Register (TCD8_SADDR) */
+#define S32K3XX_EDMA_TCD8_SOFF_OFFSET (0x020024) /* TCD8 Signed Source Address Offset Register (TCD8_SOFF) */
+#define S32K3XX_EDMA_TCD8_ATTR_OFFSET (0x020026) /* TCD8 Transfer Attributes (TCD8_ATTR) */
+#define S32K3XX_EDMA_TCD8_NBYTES_OFFSET (0x020028) /* TCD8 Transfer Size (TCD8_NBYTES) */
+#define S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET (0x02002c) /* TCD8 Last Source Address Adjustment / Store DADDR Address Register (TCD8_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD8_DADDR_OFFSET (0x020030) /* TCD8 Destination Address Register (TCD8_DADDR) */
+#define S32K3XX_EDMA_TCD8_DOFF_OFFSET (0x020034) /* TCD8 Signed Destination Address Offset Register (TCD8_DOFF) */
+#define S32K3XX_EDMA_TCD8_CITER_OFFSET (0x020036) /* TCD8 Current Major Loop Count Register (TCD8_CITER) */
+#define S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET (0x020038) /* TCD8 Last Destination Address Adjustment / Scatter Gather Address Register (TCD8_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD8_CSR_OFFSET (0x02003c) /* TCD8 Control and Status Register (TCD8_CSR) */
+#define S32K3XX_EDMA_TCD8_BITER_OFFSET (0x02003e) /* TCD8 Beginning Major Loop Count Register (TCD8_BITER) */
+
+#define S32K3XX_EDMA_CH9_CSR_OFFSET (0x024000) /* Channel 9 Control and Status Register (CH9_CSR) */
+#define S32K3XX_EDMA_CH9_ES_OFFSET (0x024004) /* Channel 9 Error Status Register (CH9_ES) */
+#define S32K3XX_EDMA_CH9_INT_OFFSET (0x024008) /* Channel 9 Interrupt Status Register (CH9_INT) */
+#define S32K3XX_EDMA_CH9_SBR_OFFSET (0x02400c) /* Channel 9 System Bus Register (CH9_SBR) */
+#define S32K3XX_EDMA_CH9_PRI_OFFSET (0x024010) /* Channel 9 Priority Register (CH9_PRI) */
+#define S32K3XX_EDMA_TCD9_SADDR_OFFSET (0x024020) /* TCD9 Source Address Register (TCD9_SADDR) */
+#define S32K3XX_EDMA_TCD9_SOFF_OFFSET (0x024024) /* TCD9 Signed Source Address Offset Register (TCD9_SOFF) */
+#define S32K3XX_EDMA_TCD9_ATTR_OFFSET (0x024026) /* TCD9 Transfer Attributes (TCD9_ATTR) */
+#define S32K3XX_EDMA_TCD9_NBYTES_OFFSET (0x024028) /* TCD9 Transfer Size (TCD9_NBYTES) */
+#define S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET (0x02402c) /* TCD9 Last Source Address Adjustment / Store DADDR Address Register (TCD9_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD9_DADDR_OFFSET (0x024030) /* TCD9 Destination Address Register (TCD9_DADDR) */
+#define S32K3XX_EDMA_TCD9_DOFF_OFFSET (0x024034) /* TCD9 Signed Destination Address Offset Register (TCD9_DOFF) */
+#define S32K3XX_EDMA_TCD9_CITER_OFFSET (0x024036) /* TCD9 Current Major Loop Count Register (TCD9_CITER) */
+#define S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET (0x024038) /* TCD9 Last Destination Address Adjustment / Scatter Gather Address Register (TCD9_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD9_CSR_OFFSET (0x02403c) /* TCD9 Control and Status Register (TCD9_CSR) */
+#define S32K3XX_EDMA_TCD9_BITER_OFFSET (0x02403e) /* TCD9 Beginning Major Loop Count Register (TCD9_BITER) */
+
+#define S32K3XX_EDMA_CH10_CSR_OFFSET (0x028000) /* Channel 10 Control and Status Register (CH10_CSR) */
+#define S32K3XX_EDMA_CH10_ES_OFFSET (0x028004) /* Channel 10 Error Status Register (CH10_ES) */
+#define S32K3XX_EDMA_CH10_INT_OFFSET (0x028008) /* Channel 10 Interrupt Status Register (CH10_INT) */
+#define S32K3XX_EDMA_CH10_SBR_OFFSET (0x02800c) /* Channel 10 System Bus Register (CH10_SBR) */
+#define S32K3XX_EDMA_CH10_PRI_OFFSET (0x028010) /* Channel 10 Priority Register (CH10_PRI) */
+#define S32K3XX_EDMA_TCD10_SADDR_OFFSET (0x028020) /* TCD10 Source Address Register (TCD10_SADDR) */
+#define S32K3XX_EDMA_TCD10_SOFF_OFFSET (0x028024) /* TCD10 Signed Source Address Offset Register (TCD10_SOFF) */
+#define S32K3XX_EDMA_TCD10_ATTR_OFFSET (0x028026) /* TCD10 Transfer Attributes (TCD10_ATTR) */
+#define S32K3XX_EDMA_TCD10_NBYTES_OFFSET (0x028028) /* TCD10 Transfer Size (TCD10_NBYTES) */
+#define S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET (0x02802c) /* TCD10 Last Source Address Adjustment / Store DADDR Address Register (TCD10_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD10_DADDR_OFFSET (0x028030) /* TCD10 Destination Address Register (TCD10_DADDR) */
+#define S32K3XX_EDMA_TCD10_DOFF_OFFSET (0x028034) /* TCD10 Signed Destination Address Offset Register (TCD10_DOFF) */
+#define S32K3XX_EDMA_TCD10_CITER_OFFSET (0x028036) /* TCD10 Current Major Loop Count Register (TCD10_CITER) */
+#define S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET (0x028038) /* TCD10 Last Destination Address Adjustment / Scatter Gather Address Register (TCD10_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD10_CSR_OFFSET (0x02803c) /* TCD10 Control and Status Register (TCD10_CSR) */
+#define S32K3XX_EDMA_TCD10_BITER_OFFSET (0x02803e) /* TCD10 Beginning Major Loop Count Register (TCD10_BITER) */
+#define S32K3XX_EDMA_CH11_CSR_OFFSET (0x02c000) /* Channel 11 Control and Status Register (CH11_CSR) */
+#define S32K3XX_EDMA_CH11_ES_OFFSET (0x02c004) /* Channel 11 Error Status Register (CH11_ES) */
+#define S32K3XX_EDMA_CH11_INT_OFFSET (0x02c008) /* Channel 11 Interrupt Status Register (CH11_INT) */
+#define S32K3XX_EDMA_CH11_SBR_OFFSET (0x02c00c) /* Channel 11 System Bus Register (CH11_SBR) */
+#define S32K3XX_EDMA_CH11_PRI_OFFSET (0x02c010) /* Channel 11 Priority Register (CH11_PRI) */
+#define S32K3XX_EDMA_TCD11_SADDR_OFFSET (0x02c020) /* TCD11 Source Address Register (TCD11_SADDR) */
+#define S32K3XX_EDMA_TCD11_SOFF_OFFSET (0x02c024) /* TCD11 Signed Source Address Offset Register (TCD11_SOFF) */
+#define S32K3XX_EDMA_TCD11_ATTR_OFFSET (0x02c026) /* TCD11 Transfer Attributes (TCD11_ATTR) */
+#define S32K3XX_EDMA_TCD11_NBYTES_OFFSET (0x02c028) /* TCD11 Transfer Size (TCD11_NBYTES) */
+#define S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET (0x02c02c) /* TCD11 Last Source Address Adjustment / Store DADDR Address Register (TCD11_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD11_DADDR_OFFSET (0x02c030) /* TCD11 Destination Address Register (TCD11_DADDR) */
+#define S32K3XX_EDMA_TCD11_DOFF_OFFSET (0x02c034) /* TCD11 Signed Destination Address Offset Register (TCD11_DOFF) */
+#define S32K3XX_EDMA_TCD11_CITER_OFFSET (0x02c036) /* TCD11 Current Major Loop Count Register (TCD11_CITER) */
+#define S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET (0x02c038) /* TCD11 Last Destination Address Adjustment / Scatter Gather Address Register (TCD11_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD11_CSR_OFFSET (0x02c03c) /* TCD11 Control and Status Register (TCD11_CSR) */
+#define S32K3XX_EDMA_TCD11_BITER_OFFSET (0x02c03e) /* TCD11 Beginning Major Loop Count Register (TCD11_BITER) */
+
+#define S32K3XX_EDMA_CH12_CSR_OFFSET (0x200000) /* Channel 12 Control and Status Register (CH12_CSR) */
+#define S32K3XX_EDMA_CH12_ES_OFFSET (0x200004) /* Channel 12 Error Status Register (CH12_ES) */
+#define S32K3XX_EDMA_CH12_INT_OFFSET (0x200008) /* Channel 12 Interrupt Status Register (CH12_INT) */
+#define S32K3XX_EDMA_CH12_SBR_OFFSET (0x20000c) /* Channel 12 System Bus Register (CH12_SBR) */
+#define S32K3XX_EDMA_CH12_PRI_OFFSET (0x200010) /* Channel 12 Priority Register (CH12_PRI) */
+#define S32K3XX_EDMA_TCD12_SADDR_OFFSET (0x200020) /* TCD12 Source Address Register (TCD12_SADDR) */
+#define S32K3XX_EDMA_TCD12_SOFF_OFFSET (0x200024) /* TCD12 Signed Source Address Offset Register (TCD12_SOFF) */
+#define S32K3XX_EDMA_TCD12_ATTR_OFFSET (0x200026) /* TCD12 Transfer Attributes (TCD12_ATTR) */
+#define S32K3XX_EDMA_TCD12_NBYTES_OFFSET (0x200028) /* TCD12 Transfer Size (TCD12_NBYTES) */
+#define S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET (0x20002c) /* TCD12 Last Source Address Adjustment / Store DADDR Address Register (TCD12_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD12_DADDR_OFFSET (0x200030) /* TCD12 Destination Address Register (TCD12_DADDR) */
+#define S32K3XX_EDMA_TCD12_DOFF_OFFSET (0x200034) /* TCD12 Signed Destination Address Offset Register (TCD12_DOFF) */
+#define S32K3XX_EDMA_TCD12_CITER_OFFSET (0x200036) /* TCD12 Current Major Loop Count Register (TCD12_CITER) */
+#define S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET (0x200038) /* TCD12 Last Destination Address Adjustment / Scatter Gather Address Register (TCD12_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD12_CSR_OFFSET (0x20003c) /* TCD12 Control and Status Register (TCD12_CSR) */
+#define S32K3XX_EDMA_TCD12_BITER_OFFSET (0x20003e) /* TCD12 Beginning Major Loop Count Register (TCD12_BITER) */
+
+#define S32K3XX_EDMA_CH13_CSR_OFFSET (0x204000) /* Channel 13 Control and Status Register (CH13_CSR) */
+#define S32K3XX_EDMA_CH13_ES_OFFSET (0x204004) /* Channel 13 Error Status Register (CH13_ES) */
+#define S32K3XX_EDMA_CH13_INT_OFFSET (0x204008) /* Channel 13 Interrupt Status Register (CH13_INT) */
+#define S32K3XX_EDMA_CH13_SBR_OFFSET (0x20400c) /* Channel 13 System Bus Register (CH13_SBR) */
+#define S32K3XX_EDMA_CH13_PRI_OFFSET (0x204010) /* Channel 13 Priority Register (CH13_PRI) */
+#define S32K3XX_EDMA_TCD13_SADDR_OFFSET (0x204020) /* TCD13 Source Address Register (TCD13_SADDR) */
+#define S32K3XX_EDMA_TCD13_SOFF_OFFSET (0x204024) /* TCD13 Signed Source Address Offset Register (TCD13_SOFF) */
+#define S32K3XX_EDMA_TCD13_ATTR_OFFSET (0x204026) /* TCD13 Transfer Attributes (TCD13_ATTR) */
+#define S32K3XX_EDMA_TCD13_NBYTES_OFFSET (0x204028) /* TCD13 Transfer Size (TCD13_NBYTES) */
+#define S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET (0x20402c) /* TCD13 Last Source Address Adjustment / Store DADDR Address Register (TCD13_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD13_DADDR_OFFSET (0x204030) /* TCD13 Destination Address Register (TCD13_DADDR) */
+#define S32K3XX_EDMA_TCD13_DOFF_OFFSET (0x204034) /* TCD13 Signed Destination Address Offset Register (TCD13_DOFF) */
+#define S32K3XX_EDMA_TCD13_CITER_OFFSET (0x204036) /* TCD13 Current Major Loop Count Register (TCD13_CITER) */
+#define S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET (0x204038) /* TCD13 Last Destination Address Adjustment / Scatter Gather Address Register (TCD13_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD13_CSR_OFFSET (0x20403c) /* TCD13 Control and Status Register (TCD13_CSR) */
+#define S32K3XX_EDMA_TCD13_BITER_OFFSET (0x20403e) /* TCD13 Beginning Major Loop Count Register (TCD13_BITER) */
+
+#define S32K3XX_EDMA_CH14_CSR_OFFSET (0x208000) /* Channel 14 Control and Status Register (CH14_CSR) */
+#define S32K3XX_EDMA_CH14_ES_OFFSET (0x208004) /* Channel 14 Error Status Register (CH14_ES) */
+#define S32K3XX_EDMA_CH14_INT_OFFSET (0x208008) /* Channel 14 Interrupt Status Register (CH14_INT) */
+#define S32K3XX_EDMA_CH14_SBR_OFFSET (0x20800c) /* Channel 14 System Bus Register (CH14_SBR) */
+#define S32K3XX_EDMA_CH14_PRI_OFFSET (0x208010) /* Channel 14 Priority Register (CH14_PRI) */
+#define S32K3XX_EDMA_TCD14_SADDR_OFFSET (0x208020) /* TCD14 Source Address Register (TCD14_SADDR) */
+#define S32K3XX_EDMA_TCD14_SOFF_OFFSET (0x208024) /* TCD14 Signed Source Address Offset Register (TCD14_SOFF) */
+#define S32K3XX_EDMA_TCD14_ATTR_OFFSET (0x208026) /* TCD14 Transfer Attributes (TCD14_ATTR) */
+#define S32K3XX_EDMA_TCD14_NBYTES_OFFSET (0x208028) /* TCD14 Transfer Size (TCD14_NBYTES) */
+#define S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET (0x20802c) /* TCD14 Last Source Address Adjustment / Store DADDR Address Register (TCD14_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD14_DADDR_OFFSET (0x208030) /* TCD14 Destination Address Register (TCD14_DADDR) */
+#define S32K3XX_EDMA_TCD14_DOFF_OFFSET (0x208034) /* TCD14 Signed Destination Address Offset Register (TCD14_DOFF) */
+#define S32K3XX_EDMA_TCD14_CITER_OFFSET (0x208036) /* TCD14 Current Major Loop Count Register (TCD14_CITER) */
+#define S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET (0x208038) /* TCD14 Last Destination Address Adjustment / Scatter Gather Address Register (TCD14_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD14_CSR_OFFSET (0x20803c) /* TCD14 Control and Status Register (TCD14_CSR) */
+#define S32K3XX_EDMA_TCD14_BITER_OFFSET (0x20803e) /* TCD14 Beginning Major Loop Count Register (TCD14_BITER) */
+
+#define S32K3XX_EDMA_CH15_CSR_OFFSET (0x20c000) /* Channel 15 Control and Status Register (CH15_CSR) */
+#define S32K3XX_EDMA_CH15_ES_OFFSET (0x20c004) /* Channel 15 Error Status Register (CH15_ES) */
+#define S32K3XX_EDMA_CH15_INT_OFFSET (0x20c008) /* Channel 15 Interrupt Status Register (CH15_INT) */
+#define S32K3XX_EDMA_CH15_SBR_OFFSET (0x20c00c) /* Channel 15 System Bus Register (CH15_SBR) */
+#define S32K3XX_EDMA_CH15_PRI_OFFSET (0x20c010) /* Channel 15 Priority Register (CH15_PRI) */
+#define S32K3XX_EDMA_TCD15_SADDR_OFFSET (0x20c020) /* TCD15 Source Address Register (TCD15_SADDR) */
+#define S32K3XX_EDMA_TCD15_SOFF_OFFSET (0x20c024) /* TCD15 Signed Source Address Offset Register (TCD15_SOFF) */
+#define S32K3XX_EDMA_TCD15_ATTR_OFFSET (0x20c026) /* TCD15 Transfer Attributes (TCD15_ATTR) */
+#define S32K3XX_EDMA_TCD15_NBYTES_OFFSET (0x20c028) /* TCD15 Transfer Size (TCD15_NBYTES) */
+#define S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET (0x20c02c) /* TCD15 Last Source Address Adjustment / Store DADDR Address Register (TCD15_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD15_DADDR_OFFSET (0x20c030) /* TCD15 Destination Address Register (TCD15_DADDR) */
+#define S32K3XX_EDMA_TCD15_DOFF_OFFSET (0x20c034) /* TCD15 Signed Destination Address Offset Register (TCD15_DOFF) */
+#define S32K3XX_EDMA_TCD15_CITER_OFFSET (0x20c036) /* TCD15 Current Major Loop Count Register (TCD15_CITER) */
+#define S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET (0x20c038) /* TCD15 Last Destination Address Adjustment / Scatter Gather Address Register (TCD15_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD15_CSR_OFFSET (0x20c03c) /* TCD15 Control and Status Register (TCD15_CSR) */
+#define S32K3XX_EDMA_TCD15_BITER_OFFSET (0x20c03e) /* TCD15 Beginning Major Loop Count Register (TCD15_BITER) */
+
+#define S32K3XX_EDMA_CH16_CSR_OFFSET (0x210000) /* Channel 16 Control and Status Register (CH16_CSR) */
+#define S32K3XX_EDMA_CH16_ES_OFFSET (0x210004) /* Channel 16 Error Status Register (CH16_ES) */
+#define S32K3XX_EDMA_CH16_INT_OFFSET (0x210008) /* Channel 16 Interrupt Status Register (CH16_INT) */
+#define S32K3XX_EDMA_CH16_SBR_OFFSET (0x21000c) /* Channel 16 System Bus Register (CH16_SBR) */
+#define S32K3XX_EDMA_CH16_PRI_OFFSET (0x210010) /* Channel 16 Priority Register (CH16_PRI) */
+#define S32K3XX_EDMA_TCD16_SADDR_OFFSET (0x210020) /* TCD16 Source Address Register (TCD16_SADDR) */
+#define S32K3XX_EDMA_TCD16_SOFF_OFFSET (0x210024) /* TCD16 Signed Source Address Offset Register (TCD16_SOFF) */
+#define S32K3XX_EDMA_TCD16_ATTR_OFFSET (0x210026) /* TCD16 Transfer Attributes (TCD16_ATTR) */
+#define S32K3XX_EDMA_TCD16_NBYTES_OFFSET (0x210028) /* TCD16 Transfer Size (TCD16_NBYTES) */
+#define S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET (0x21002c) /* TCD16 Last Source Address Adjustment / Store DADDR Address Register (TCD16_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD16_DADDR_OFFSET (0x210030) /* TCD16 Destination Address Register (TCD16_DADDR) */
+#define S32K3XX_EDMA_TCD16_DOFF_OFFSET (0x210034) /* TCD16 Signed Destination Address Offset Register (TCD16_DOFF) */
+#define S32K3XX_EDMA_TCD16_CITER_OFFSET (0x210036) /* TCD16 Current Major Loop Count Register (TCD16_CITER) */
+#define S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET (0x210038) /* TCD16 Last Destination Address Adjustment / Scatter Gather Address Register (TCD16_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD16_CSR_OFFSET (0x21003c) /* TCD16 Control and Status Register (TCD16_CSR) */
+#define S32K3XX_EDMA_TCD16_BITER_OFFSET (0x21003e) /* TCD16 Beginning Major Loop Count Register (TCD16_BITER) */
+
+#define S32K3XX_EDMA_CH17_CSR_OFFSET (0x214000) /* Channel 17 Control and Status Register (CH17_CSR) */
+#define S32K3XX_EDMA_CH17_ES_OFFSET (0x214004) /* Channel 17 Error Status Register (CH17_ES) */
+#define S32K3XX_EDMA_CH17_INT_OFFSET (0x214008) /* Channel 17 Interrupt Status Register (CH17_INT) */
+#define S32K3XX_EDMA_CH17_SBR_OFFSET (0x21400c) /* Channel 17 System Bus Register (CH17_SBR) */
+#define S32K3XX_EDMA_CH17_PRI_OFFSET (0x214010) /* Channel 17 Priority Register (CH17_PRI) */
+#define S32K3XX_EDMA_TCD17_SADDR_OFFSET (0x214020) /* TCD17 Source Address Register (TCD17_SADDR) */
+#define S32K3XX_EDMA_TCD17_SOFF_OFFSET (0x214024) /* TCD17 Signed Source Address Offset Register (TCD17_SOFF) */
+#define S32K3XX_EDMA_TCD17_ATTR_OFFSET (0x214026) /* TCD17 Transfer Attributes (TCD17_ATTR) */
+#define S32K3XX_EDMA_TCD17_NBYTES_OFFSET (0x214028) /* TCD17 Transfer Size (TCD17_NBYTES) */
+#define S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET (0x21402c) /* TCD17 Last Source Address Adjustment / Store DADDR Address Register (TCD17_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD17_DADDR_OFFSET (0x214030) /* TCD17 Destination Address Register (TCD17_DADDR) */
+#define S32K3XX_EDMA_TCD17_DOFF_OFFSET (0x214034) /* TCD17 Signed Destination Address Offset Register (TCD17_DOFF) */
+#define S32K3XX_EDMA_TCD17_CITER_OFFSET (0x214036) /* TCD17 Current Major Loop Count Register (TCD17_CITER) */
+#define S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET (0x214038) /* TCD17 Last Destination Address Adjustment / Scatter Gather Address Register (TCD17_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD17_CSR_OFFSET (0x21403c) /* TCD17 Control and Status Register (TCD17_CSR) */
+#define S32K3XX_EDMA_TCD17_BITER_OFFSET (0x21403e) /* TCD17 Beginning Major Loop Count Register (TCD17_BITER) */
+
+#define S32K3XX_EDMA_CH18_CSR_OFFSET (0x218000) /* Channel 18 Control and Status Register (CH18_CSR) */
+#define S32K3XX_EDMA_CH18_ES_OFFSET (0x218004) /* Channel 18 Error Status Register (CH18_ES) */
+#define S32K3XX_EDMA_CH18_INT_OFFSET (0x218008) /* Channel 18 Interrupt Status Register (CH18_INT) */
+#define S32K3XX_EDMA_CH18_SBR_OFFSET (0x21800c) /* Channel 18 System Bus Register (CH18_SBR) */
+#define S32K3XX_EDMA_CH18_PRI_OFFSET (0x218010) /* Channel 18 Priority Register (CH18_PRI) */
+#define S32K3XX_EDMA_TCD18_SADDR_OFFSET (0x218020) /* TCD18 Source Address Register (TCD18_SADDR) */
+#define S32K3XX_EDMA_TCD18_SOFF_OFFSET (0x218024) /* TCD18 Signed Source Address Offset Register (TCD18_SOFF) */
+#define S32K3XX_EDMA_TCD18_ATTR_OFFSET (0x218026) /* TCD18 Transfer Attributes (TCD18_ATTR) */
+#define S32K3XX_EDMA_TCD18_NBYTES_OFFSET (0x218028) /* TCD18 Transfer Size (TCD18_NBYTES) */
+#define S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET (0x21802c) /* TCD18 Last Source Address Adjustment / Store DADDR Address Register (TCD18_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD18_DADDR_OFFSET (0x218030) /* TCD18 Destination Address Register (TCD18_DADDR) */
+#define S32K3XX_EDMA_TCD18_DOFF_OFFSET (0x218034) /* TCD18 Signed Destination Address Offset Register (TCD18_DOFF) */
+#define S32K3XX_EDMA_TCD18_CITER_OFFSET (0x218036) /* TCD18 Current Major Loop Count Register (TCD18_CITER) */
+#define S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET (0x218038) /* TCD18 Last Destination Address Adjustment / Scatter Gather Address Register (TCD18_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD18_CSR_OFFSET (0x21803c) /* TCD18 Control and Status Register (TCD18_CSR) */
+#define S32K3XX_EDMA_TCD18_BITER_OFFSET (0x21803e) /* TCD18 Beginning Major Loop Count Register (TCD18_BITER) */
+
+#define S32K3XX_EDMA_CH19_CSR_OFFSET (0x21c000) /* Channel 19 Control and Status Register (CH19_CSR) */
+#define S32K3XX_EDMA_CH19_ES_OFFSET (0x21c004) /* Channel 19 Error Status Register (CH19_ES) */
+#define S32K3XX_EDMA_CH19_INT_OFFSET (0x21c008) /* Channel 19 Interrupt Status Register (CH19_INT) */
+#define S32K3XX_EDMA_CH19_SBR_OFFSET (0x21c00c) /* Channel 19 System Bus Register (CH19_SBR) */
+#define S32K3XX_EDMA_CH19_PRI_OFFSET (0x21c010) /* Channel 19 Priority Register (CH19_PRI) */
+#define S32K3XX_EDMA_TCD19_SADDR_OFFSET (0x21c020) /* TCD19 Source Address Register (TCD19_SADDR) */
+#define S32K3XX_EDMA_TCD19_SOFF_OFFSET (0x21c024) /* TCD19 Signed Source Address Offset Register (TCD19_SOFF) */
+#define S32K3XX_EDMA_TCD19_ATTR_OFFSET (0x21c026) /* TCD19 Transfer Attributes (TCD19_ATTR) */
+#define S32K3XX_EDMA_TCD19_NBYTES_OFFSET (0x21c028) /* TCD19 Transfer Size (TCD19_NBYTES) */
+#define S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET (0x21c02c) /* TCD19 Last Source Address Adjustment / Store DADDR Address Register (TCD19_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD19_DADDR_OFFSET (0x21c030) /* TCD19 Destination Address Register (TCD19_DADDR) */
+#define S32K3XX_EDMA_TCD19_DOFF_OFFSET (0x21c034) /* TCD19 Signed Destination Address Offset Register (TCD19_DOFF) */
+#define S32K3XX_EDMA_TCD19_CITER_OFFSET (0x21c036) /* TCD19 Current Major Loop Count Register (TCD19_CITER) */
+#define S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET (0x21c038) /* TCD19 Last Destination Address Adjustment / Scatter Gather Address Register (TCD19_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD19_CSR_OFFSET (0x21c03c) /* TCD19 Control and Status Register (TCD19_CSR) */
+#define S32K3XX_EDMA_TCD19_BITER_OFFSET (0x21c03e) /* TCD19 Beginning Major Loop Count Register (TCD19_BITER) */
+
+#define S32K3XX_EDMA_CH20_CSR_OFFSET (0x220000) /* Channel 20 Control and Status Register (CH20_CSR) */
+#define S32K3XX_EDMA_CH20_ES_OFFSET (0x220004) /* Channel 20 Error Status Register (CH20_ES) */
+#define S32K3XX_EDMA_CH20_INT_OFFSET (0x220008) /* Channel 20 Interrupt Status Register (CH20_INT) */
+#define S32K3XX_EDMA_CH20_SBR_OFFSET (0x22000c) /* Channel 20 System Bus Register (CH20_SBR) */
+#define S32K3XX_EDMA_CH20_PRI_OFFSET (0x220010) /* Channel 20 Priority Register (CH20_PRI) */
+#define S32K3XX_EDMA_TCD20_SADDR_OFFSET (0x220020) /* TCD20 Source Address Register (TCD20_SADDR) */
+#define S32K3XX_EDMA_TCD20_SOFF_OFFSET (0x220024) /* TCD20 Signed Source Address Offset Register (TCD20_SOFF) */
+#define S32K3XX_EDMA_TCD20_ATTR_OFFSET (0x220026) /* TCD20 Transfer Attributes (TCD20_ATTR) */
+#define S32K3XX_EDMA_TCD20_NBYTES_OFFSET (0x220028) /* TCD20 Transfer Size (TCD20_NBYTES) */
+#define S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET (0x22002c) /* TCD20 Last Source Address Adjustment / Store DADDR Address Register (TCD20_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD20_DADDR_OFFSET (0x220030) /* TCD20 Destination Address Register (TCD20_DADDR) */
+#define S32K3XX_EDMA_TCD20_DOFF_OFFSET (0x220034) /* TCD20 Signed Destination Address Offset Register (TCD20_DOFF) */
+#define S32K3XX_EDMA_TCD20_CITER_OFFSET (0x220036) /* TCD20 Current Major Loop Count Register (TCD20_CITER) */
+#define S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET (0x220038) /* TCD20 Last Destination Address Adjustment / Scatter Gather Address Register (TCD20_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD20_CSR_OFFSET (0x22003c) /* TCD20 Control and Status Register (TCD20_CSR) */
+#define S32K3XX_EDMA_TCD20_BITER_OFFSET (0x22003e) /* TCD20 Beginning Major Loop Count Register (TCD20_BITER) */
+
+#define S32K3XX_EDMA_CH21_CSR_OFFSET (0x224000) /* Channel 21 Control and Status Register (CH21_CSR) */
+#define S32K3XX_EDMA_CH21_ES_OFFSET (0x224004) /* Channel 21 Error Status Register (CH21_ES) */
+#define S32K3XX_EDMA_CH21_INT_OFFSET (0x224008) /* Channel 21 Interrupt Status Register (CH21_INT) */
+#define S32K3XX_EDMA_CH21_SBR_OFFSET (0x22400c) /* Channel 21 System Bus Register (CH21_SBR) */
+#define S32K3XX_EDMA_CH21_PRI_OFFSET (0x224010) /* Channel 21 Priority Register (CH21_PRI) */
+#define S32K3XX_EDMA_TCD21_SADDR_OFFSET (0x224020) /* TCD21 Source Address Register (TCD21_SADDR) */
+#define S32K3XX_EDMA_TCD21_SOFF_OFFSET (0x224024) /* TCD21 Signed Source Address Offset Register (TCD21_SOFF) */
+#define S32K3XX_EDMA_TCD21_ATTR_OFFSET (0x224026) /* TCD21 Transfer Attributes (TCD21_ATTR) */
+#define S32K3XX_EDMA_TCD21_NBYTES_OFFSET (0x224028) /* TCD21 Transfer Size (TCD21_NBYTES) */
+#define S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET (0x22402c) /* TCD21 Last Source Address Adjustment / Store DADDR Address Register (TCD21_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD21_DADDR_OFFSET (0x224030) /* TCD21 Destination Address Register (TCD21_DADDR) */
+#define S32K3XX_EDMA_TCD21_DOFF_OFFSET (0x224034) /* TCD21 Signed Destination Address Offset Register (TCD21_DOFF) */
+#define S32K3XX_EDMA_TCD21_CITER_OFFSET (0x224036) /* TCD21 Current Major Loop Count Register (TCD21_CITER) */
+#define S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET (0x224038) /* TCD21 Last Destination Address Adjustment / Scatter Gather Address Register (TCD21_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD21_CSR_OFFSET (0x22403c) /* TCD21 Control and Status Register (TCD21_CSR) */
+#define S32K3XX_EDMA_TCD21_BITER_OFFSET (0x22403e) /* TCD21 Beginning Major Loop Count Register (TCD21_BITER) */
+
+#define S32K3XX_EDMA_CH22_CSR_OFFSET (0x228000) /* Channel 22 Control and Status Register (CH22_CSR) */
+#define S32K3XX_EDMA_CH22_ES_OFFSET (0x228004) /* Channel 22 Error Status Register (CH22_ES) */
+#define S32K3XX_EDMA_CH22_INT_OFFSET (0x228008) /* Channel 22 Interrupt Status Register (CH22_INT) */
+#define S32K3XX_EDMA_CH22_SBR_OFFSET (0x22800c) /* Channel 22 System Bus Register (CH22_SBR) */
+#define S32K3XX_EDMA_CH22_PRI_OFFSET (0x228010) /* Channel 22 Priority Register (CH22_PRI) */
+#define S32K3XX_EDMA_TCD22_SADDR_OFFSET (0x228020) /* TCD22 Source Address Register (TCD22_SADDR) */
+#define S32K3XX_EDMA_TCD22_SOFF_OFFSET (0x228024) /* TCD22 Signed Source Address Offset Register (TCD22_SOFF) */
+#define S32K3XX_EDMA_TCD22_ATTR_OFFSET (0x228026) /* TCD22 Transfer Attributes (TCD22_ATTR) */
+#define S32K3XX_EDMA_TCD22_NBYTES_OFFSET (0x228028) /* TCD22 Transfer Size (TCD22_NBYTES) */
+#define S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET (0x22802c) /* TCD22 Last Source Address Adjustment / Store DADDR Address Register (TCD22_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD22_DADDR_OFFSET (0x228030) /* TCD22 Destination Address Register (TCD22_DADDR) */
+#define S32K3XX_EDMA_TCD22_DOFF_OFFSET (0x228034) /* TCD22 Signed Destination Address Offset Register (TCD22_DOFF) */
+#define S32K3XX_EDMA_TCD22_CITER_OFFSET (0x228036) /* TCD22 Current Major Loop Count Register (TCD22_CITER) */
+#define S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET (0x228038) /* TCD22 Last Destination Address Adjustment / Scatter Gather Address Register (TCD22_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD22_CSR_OFFSET (0x22803c) /* TCD22 Control and Status Register (TCD22_CSR) */
+#define S32K3XX_EDMA_TCD22_BITER_OFFSET (0x22803e) /* TCD22 Beginning Major Loop Count Register (TCD22_BITER) */
+
+#define S32K3XX_EDMA_CH23_CSR_OFFSET (0x22c000) /* Channel 23 Control and Status Register (CH23_CSR) */
+#define S32K3XX_EDMA_CH23_ES_OFFSET (0x22c004) /* Channel 23 Error Status Register (CH23_ES) */
+#define S32K3XX_EDMA_CH23_INT_OFFSET (0x22c008) /* Channel 23 Interrupt Status Register (CH23_INT) */
+#define S32K3XX_EDMA_CH23_SBR_OFFSET (0x22c00c) /* Channel 23 System Bus Register (CH23_SBR) */
+#define S32K3XX_EDMA_CH23_PRI_OFFSET (0x22c010) /* Channel 23 Priority Register (CH23_PRI) */
+#define S32K3XX_EDMA_TCD23_SADDR_OFFSET (0x22c020) /* TCD23 Source Address Register (TCD23_SADDR) */
+#define S32K3XX_EDMA_TCD23_SOFF_OFFSET (0x22c024) /* TCD23 Signed Source Address Offset Register (TCD23_SOFF) */
+#define S32K3XX_EDMA_TCD23_ATTR_OFFSET (0x22c026) /* TCD23 Transfer Attributes (TCD23_ATTR) */
+#define S32K3XX_EDMA_TCD23_NBYTES_OFFSET (0x22c028) /* TCD23 Transfer Size (TCD23_NBYTES) */
+#define S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET (0x22c02c) /* TCD23 Last Source Address Adjustment / Store DADDR Address Register (TCD23_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD23_DADDR_OFFSET (0x22c030) /* TCD23 Destination Address Register (TCD23_DADDR) */
+#define S32K3XX_EDMA_TCD23_DOFF_OFFSET (0x22c034) /* TCD23 Signed Destination Address Offset Register (TCD23_DOFF) */
+#define S32K3XX_EDMA_TCD23_CITER_OFFSET (0x22c036) /* TCD23 Current Major Loop Count Register (TCD23_CITER) */
+#define S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET (0x22c038) /* TCD23 Last Destination Address Adjustment / Scatter Gather Address Register (TCD23_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD23_CSR_OFFSET (0x22c03c) /* TCD23 Control and Status Register (TCD23_CSR) */
+#define S32K3XX_EDMA_TCD23_BITER_OFFSET (0x22c03e) /* TCD23 Beginning Major Loop Count Register (TCD23_BITER) */
+
+#define S32K3XX_EDMA_CH24_CSR_OFFSET (0x230000) /* Channel 24 Control and Status Register (CH24_CSR) */
+#define S32K3XX_EDMA_CH24_ES_OFFSET (0x230004) /* Channel 24 Error Status Register (CH24_ES) */
+#define S32K3XX_EDMA_CH24_INT_OFFSET (0x230008) /* Channel 24 Interrupt Status Register (CH24_INT) */
+#define S32K3XX_EDMA_CH24_SBR_OFFSET (0x23000c) /* Channel 24 System Bus Register (CH24_SBR) */
+#define S32K3XX_EDMA_CH24_PRI_OFFSET (0x230010) /* Channel 24 Priority Register (CH24_PRI) */
+#define S32K3XX_EDMA_TCD24_SADDR_OFFSET (0x230020) /* TCD24 Source Address Register (TCD24_SADDR) */
+#define S32K3XX_EDMA_TCD24_SOFF_OFFSET (0x230024) /* TCD24 Signed Source Address Offset Register (TCD24_SOFF) */
+#define S32K3XX_EDMA_TCD24_ATTR_OFFSET (0x230026) /* TCD24 Transfer Attributes (TCD24_ATTR) */
+#define S32K3XX_EDMA_TCD24_NBYTES_OFFSET (0x230028) /* TCD24 Transfer Size (TCD24_NBYTES) */
+#define S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET (0x23002c) /* TCD24 Last Source Address Adjustment / Store DADDR Address Register (TCD24_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD24_DADDR_OFFSET (0x230030) /* TCD24 Destination Address Register (TCD24_DADDR) */
+#define S32K3XX_EDMA_TCD24_DOFF_OFFSET (0x230034) /* TCD24 Signed Destination Address Offset Register (TCD24_DOFF) */
+#define S32K3XX_EDMA_TCD24_CITER_OFFSET (0x230036) /* TCD24 Current Major Loop Count Register (TCD24_CITER) */
+#define S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET (0x230038) /* TCD24 Last Destination Address Adjustment / Scatter Gather Address Register (TCD24_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD24_CSR_OFFSET (0x23003c) /* TCD24 Control and Status Register (TCD24_CSR) */
+#define S32K3XX_EDMA_TCD24_BITER_OFFSET (0x23003e) /* TCD24 Beginning Major Loop Count Register (TCD24_BITER) */
+
+#define S32K3XX_EDMA_CH25_CSR_OFFSET (0x234000) /* Channel 25 Control and Status Register (CH25_CSR) */
+#define S32K3XX_EDMA_CH25_ES_OFFSET (0x234004) /* Channel 25 Error Status Register (CH25_ES) */
+#define S32K3XX_EDMA_CH25_INT_OFFSET (0x234008) /* Channel 25 Interrupt Status Register (CH25_INT) */
+#define S32K3XX_EDMA_CH25_SBR_OFFSET (0x23400c) /* Channel 25 System Bus Register (CH25_SBR) */
+#define S32K3XX_EDMA_CH25_PRI_OFFSET (0x234010) /* Channel 25 Priority Register (CH25_PRI) */
+#define S32K3XX_EDMA_TCD25_SADDR_OFFSET (0x234020) /* TCD25 Source Address Register (TCD25_SADDR) */
+#define S32K3XX_EDMA_TCD25_SOFF_OFFSET (0x234024) /* TCD25 Signed Source Address Offset Register (TCD25_SOFF) */
+#define S32K3XX_EDMA_TCD25_ATTR_OFFSET (0x234026) /* TCD25 Transfer Attributes (TCD25_ATTR) */
+#define S32K3XX_EDMA_TCD25_NBYTES_OFFSET (0x234028) /* TCD25 Transfer Size (TCD25_NBYTES) */
+#define S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET (0x23402c) /* TCD25 Last Source Address Adjustment / Store DADDR Address Register (TCD25_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD25_DADDR_OFFSET (0x234030) /* TCD25 Destination Address Register (TCD25_DADDR) */
+#define S32K3XX_EDMA_TCD25_DOFF_OFFSET (0x234034) /* TCD25 Signed Destination Address Offset Register (TCD25_DOFF) */
+#define S32K3XX_EDMA_TCD25_CITER_OFFSET (0x234036) /* TCD25 Current Major Loop Count Register (TCD25_CITER) */
+#define S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET (0x234038) /* TCD25 Last Destination Address Adjustment / Scatter Gather Address Register (TCD25_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD25_CSR_OFFSET (0x23403c) /* TCD25 Control and Status Register (TCD25_CSR) */
+#define S32K3XX_EDMA_TCD25_BITER_OFFSET (0x23403e) /* TCD25 Beginning Major Loop Count Register (TCD25_BITER) */
+
+#define S32K3XX_EDMA_CH26_CSR_OFFSET (0x238000) /* Channel 26 Control and Status Register (CH26_CSR) */
+#define S32K3XX_EDMA_CH26_ES_OFFSET (0x238004) /* Channel 26 Error Status Register (CH26_ES) */
+#define S32K3XX_EDMA_CH26_INT_OFFSET (0x238008) /* Channel 26 Interrupt Status Register (CH26_INT) */
+#define S32K3XX_EDMA_CH26_SBR_OFFSET (0x23800c) /* Channel 26 System Bus Register (CH26_SBR) */
+#define S32K3XX_EDMA_CH26_PRI_OFFSET (0x238010) /* Channel 26 Priority Register (CH26_PRI) */
+#define S32K3XX_EDMA_TCD26_SADDR_OFFSET (0x238020) /* TCD26 Source Address Register (TCD26_SADDR) */
+#define S32K3XX_EDMA_TCD26_SOFF_OFFSET (0x238024) /* TCD26 Signed Source Address Offset Register (TCD26_SOFF) */
+#define S32K3XX_EDMA_TCD26_ATTR_OFFSET (0x238026) /* TCD26 Transfer Attributes (TCD26_ATTR) */
+#define S32K3XX_EDMA_TCD26_NBYTES_OFFSET (0x238028) /* TCD26 Transfer Size (TCD26_NBYTES) */
+#define S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET (0x23802c) /* TCD26 Last Source Address Adjustment / Store DADDR Address Register (TCD26_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD26_DADDR_OFFSET (0x238030) /* TCD26 Destination Address Register (TCD26_DADDR) */
+#define S32K3XX_EDMA_TCD26_DOFF_OFFSET (0x238034) /* TCD26 Signed Destination Address Offset Register (TCD26_DOFF) */
+#define S32K3XX_EDMA_TCD26_CITER_OFFSET (0x238036) /* TCD26 Current Major Loop Count Register (TCD26_CITER) */
+#define S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET (0x238038) /* TCD26 Last Destination Address Adjustment / Scatter Gather Address Register (TCD26_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD26_CSR_OFFSET (0x23803c) /* TCD26 Control and Status Register (TCD26_CSR) */
+#define S32K3XX_EDMA_TCD26_BITER_OFFSET (0x23803e) /* TCD26 Beginning Major Loop Count Register (TCD26_BITER) */
+
+#define S32K3XX_EDMA_CH27_CSR_OFFSET (0x23c000) /* Channel 27 Control and Status Register (CH27_CSR) */
+#define S32K3XX_EDMA_CH27_ES_OFFSET (0x23c004) /* Channel 27 Error Status Register (CH27_ES) */
+#define S32K3XX_EDMA_CH27_INT_OFFSET (0x23c008) /* Channel 27 Interrupt Status Register (CH27_INT) */
+#define S32K3XX_EDMA_CH27_SBR_OFFSET (0x23c00c) /* Channel 27 System Bus Register (CH27_SBR) */
+#define S32K3XX_EDMA_CH27_PRI_OFFSET (0x23c010) /* Channel 27 Priority Register (CH27_PRI) */
+#define S32K3XX_EDMA_TCD27_SADDR_OFFSET (0x23c020) /* TCD27 Source Address Register (TCD27_SADDR) */
+#define S32K3XX_EDMA_TCD27_SOFF_OFFSET (0x23c024) /* TCD27 Signed Source Address Offset Register (TCD27_SOFF) */
+#define S32K3XX_EDMA_TCD27_ATTR_OFFSET (0x23c026) /* TCD27 Transfer Attributes (TCD27_ATTR) */
+#define S32K3XX_EDMA_TCD27_NBYTES_OFFSET (0x23c028) /* TCD27 Transfer Size (TCD27_NBYTES) */
+#define S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET (0x23c02c) /* TCD27 Last Source Address Adjustment / Store DADDR Address Register (TCD27_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD27_DADDR_OFFSET (0x23c030) /* TCD27 Destination Address Register (TCD27_DADDR) */
+#define S32K3XX_EDMA_TCD27_DOFF_OFFSET (0x23c034) /* TCD27 Signed Destination Address Offset Register (TCD27_DOFF) */
+#define S32K3XX_EDMA_TCD27_CITER_OFFSET (0x23c036) /* TCD27 Current Major Loop Count Register (TCD27_CITER) */
+#define S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET (0x23c038) /* TCD27 Last Destination Address Adjustment / Scatter Gather Address Register (TCD27_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD27_CSR_OFFSET (0x23c03c) /* TCD27 Control and Status Register (TCD27_CSR) */
+#define S32K3XX_EDMA_TCD27_BITER_OFFSET (0x23c03e) /* TCD27 Beginning Major Loop Count Register (TCD27_BITER) */
+
+#define S32K3XX_EDMA_CH28_CSR_OFFSET (0x240000) /* Channel 28 Control and Status Register (CH28_CSR) */
+#define S32K3XX_EDMA_CH28_ES_OFFSET (0x240004) /* Channel 28 Error Status Register (CH28_ES) */
+#define S32K3XX_EDMA_CH28_INT_OFFSET (0x240008) /* Channel 28 Interrupt Status Register (CH28_INT) */
+#define S32K3XX_EDMA_CH28_SBR_OFFSET (0x24000c) /* Channel 28 System Bus Register (CH28_SBR) */
+#define S32K3XX_EDMA_CH28_PRI_OFFSET (0x240010) /* Channel 28 Priority Register (CH28_PRI) */
+#define S32K3XX_EDMA_TCD28_SADDR_OFFSET (0x240020) /* TCD28 Source Address Register (TCD28_SADDR) */
+#define S32K3XX_EDMA_TCD28_SOFF_OFFSET (0x240024) /* TCD28 Signed Source Address Offset Register (TCD28_SOFF) */
+#define S32K3XX_EDMA_TCD28_ATTR_OFFSET (0x240026) /* TCD28 Transfer Attributes (TCD28_ATTR) */
+#define S32K3XX_EDMA_TCD28_NBYTES_OFFSET (0x240028) /* TCD28 Transfer Size (TCD28_NBYTES) */
+#define S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET (0x24002c) /* TCD28 Last Source Address Adjustment / Store DADDR Address Register (TCD28_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD28_DADDR_OFFSET (0x240030) /* TCD28 Destination Address Register (TCD28_DADDR) */
+#define S32K3XX_EDMA_TCD28_DOFF_OFFSET (0x240034) /* TCD28 Signed Destination Address Offset Register (TCD28_DOFF) */
+#define S32K3XX_EDMA_TCD28_CITER_OFFSET (0x240036) /* TCD28 Current Major Loop Count Register (TCD28_CITER) */
+#define S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET (0x240038) /* TCD28 Last Destination Address Adjustment / Scatter Gather Address Register (TCD28_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD28_CSR_OFFSET (0x24003c) /* TCD28 Control and Status Register (TCD28_CSR) */
+#define S32K3XX_EDMA_TCD28_BITER_OFFSET (0x24003e) /* TCD28 Beginning Major Loop Count Register (TCD28_BITER) */
+
+#define S32K3XX_EDMA_CH29_CSR_OFFSET (0x244000) /* Channel 29 Control and Status Register (CH29_CSR) */
+#define S32K3XX_EDMA_CH29_ES_OFFSET (0x244004) /* Channel 29 Error Status Register (CH29_ES) */
+#define S32K3XX_EDMA_CH29_INT_OFFSET (0x244008) /* Channel 29 Interrupt Status Register (CH29_INT) */
+#define S32K3XX_EDMA_CH29_SBR_OFFSET (0x24400c) /* Channel 29 System Bus Register (CH29_SBR) */
+#define S32K3XX_EDMA_CH29_PRI_OFFSET (0x244010) /* Channel 29 Priority Register (CH29_PRI) */
+#define S32K3XX_EDMA_TCD29_SADDR_OFFSET (0x244020) /* TCD29 Source Address Register (TCD29_SADDR) */
+#define S32K3XX_EDMA_TCD29_SOFF_OFFSET (0x244024) /* TCD29 Signed Source Address Offset Register (TCD29_SOFF) */
+#define S32K3XX_EDMA_TCD29_ATTR_OFFSET (0x244026) /* TCD29 Transfer Attributes (TCD29_ATTR) */
+#define S32K3XX_EDMA_TCD29_NBYTES_OFFSET (0x244028) /* TCD29 Transfer Size (TCD29_NBYTES) */
+#define S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET (0x24402c) /* TCD29 Last Source Address Adjustment / Store DADDR Address Register (TCD29_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD29_DADDR_OFFSET (0x244030) /* TCD29 Destination Address Register (TCD29_DADDR) */
+#define S32K3XX_EDMA_TCD29_DOFF_OFFSET (0x244034) /* TCD29 Signed Destination Address Offset Register (TCD29_DOFF) */
+#define S32K3XX_EDMA_TCD29_CITER_OFFSET (0x244036) /* TCD29 Current Major Loop Count Register (TCD29_CITER) */
+#define S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET (0x244038) /* TCD29 Last Destination Address Adjustment / Scatter Gather Address Register (TCD29_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD29_CSR_OFFSET (0x24403c) /* TCD29 Control and Status Register (TCD29_CSR) */
+#define S32K3XX_EDMA_TCD29_BITER_OFFSET (0x24403e) /* TCD29 Beginning Major Loop Count Register (TCD29_BITER) */
+
+#define S32K3XX_EDMA_CH30_CSR_OFFSET (0x248000) /* Channel 30 Control and Status Register (CH30_CSR) */
+#define S32K3XX_EDMA_CH30_ES_OFFSET (0x248004) /* Channel 30 Error Status Register (CH30_ES) */
+#define S32K3XX_EDMA_CH30_INT_OFFSET (0x248008) /* Channel 30 Interrupt Status Register (CH30_INT) */
+#define S32K3XX_EDMA_CH30_SBR_OFFSET (0x24800c) /* Channel 30 System Bus Register (CH30_SBR) */
+#define S32K3XX_EDMA_CH30_PRI_OFFSET (0x248010) /* Channel 30 Priority Register (CH30_PRI) */
+#define S32K3XX_EDMA_TCD30_SADDR_OFFSET (0x248020) /* TCD30 Source Address Register (TCD30_SADDR) */
+#define S32K3XX_EDMA_TCD30_SOFF_OFFSET (0x248024) /* TCD30 Signed Source Address Offset Register (TCD30_SOFF) */
+#define S32K3XX_EDMA_TCD30_ATTR_OFFSET (0x248026) /* TCD30 Transfer Attributes (TCD30_ATTR) */
+#define S32K3XX_EDMA_TCD30_NBYTES_OFFSET (0x248028) /* TCD30 Transfer Size (TCD30_NBYTES) */
+#define S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET (0x24802c) /* TCD30 Last Source Address Adjustment / Store DADDR Address Register (TCD30_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD30_DADDR_OFFSET (0x248030) /* TCD30 Destination Address Register (TCD30_DADDR) */
+#define S32K3XX_EDMA_TCD30_DOFF_OFFSET (0x248034) /* TCD30 Signed Destination Address Offset Register (TCD30_DOFF) */
+#define S32K3XX_EDMA_TCD30_CITER_OFFSET (0x248036) /* TCD30 Current Major Loop Count Register (TCD30_CITER) */
+#define S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET (0x248038) /* TCD30 Last Destination Address Adjustment / Scatter Gather Address Register (TCD30_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD30_CSR_OFFSET (0x24803c) /* TCD30 Control and Status Register (TCD30_CSR) */
+#define S32K3XX_EDMA_TCD30_BITER_OFFSET (0x24803e) /* TCD30 Beginning Major Loop Count Register (TCD30_BITER) */
+
+#define S32K3XX_EDMA_CH31_CSR_OFFSET (0x24c000) /* Channel 31 Control and Status Register (CH31_CSR) */
+#define S32K3XX_EDMA_CH31_ES_OFFSET (0x24c004) /* Channel 31 Error Status Register (CH31_ES) */
+#define S32K3XX_EDMA_CH31_INT_OFFSET (0x24c008) /* Channel 31 Interrupt Status Register (CH31_INT) */
+#define S32K3XX_EDMA_CH31_SBR_OFFSET (0x24c00c) /* Channel 31 System Bus Register (CH31_SBR) */
+#define S32K3XX_EDMA_CH31_PRI_OFFSET (0x24c010) /* Channel 31 Priority Register (CH31_PRI) */
+#define S32K3XX_EDMA_TCD31_SADDR_OFFSET (0x24c020) /* TCD31 Source Address Register (TCD31_SADDR) */
+#define S32K3XX_EDMA_TCD31_SOFF_OFFSET (0x24c024) /* TCD31 Signed Source Address Offset Register (TCD31_SOFF) */
+#define S32K3XX_EDMA_TCD31_ATTR_OFFSET (0x24c026) /* TCD31 Transfer Attributes (TCD31_ATTR) */
+#define S32K3XX_EDMA_TCD31_NBYTES_OFFSET (0x24c028) /* TCD31 Transfer Size (TCD31_NBYTES) */
+#define S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET (0x24c02c) /* TCD31 Last Source Address Adjustment / Store DADDR Address Register (TCD31_SLAST_SDA) */
+#define S32K3XX_EDMA_TCD31_DADDR_OFFSET (0x24c030) /* TCD31 Destination Address Register (TCD31_DADDR) */
+#define S32K3XX_EDMA_TCD31_DOFF_OFFSET (0x24c034) /* TCD31 Signed Destination Address Offset Register (TCD31_DOFF) */
+#define S32K3XX_EDMA_TCD31_CITER_OFFSET (0x24c036) /* TCD31 Current Major Loop Count Register (TCD31_CITER) */
+#define S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET (0x24c038) /* TCD31 Last Destination Address Adjustment / Scatter Gather Address Register (TCD31_DLAST_SGA)*/
+#define S32K3XX_EDMA_TCD31_CSR_OFFSET (0x24c03c) /* TCD31 Control and Status Register (TCD31_CSR) */
+#define S32K3XX_EDMA_TCD31_BITER_OFFSET (0x24c03e) /* TCD31 Beginning Major Loop Count Register (TCD31_BITER) */
+
+/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
+
+#define S32K3XX_EDMA_CH0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_CSR_OFFSET)
+#define S32K3XX_EDMA_CH0_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_ES_OFFSET)
+#define S32K3XX_EDMA_CH0_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_INT_OFFSET)
+#define S32K3XX_EDMA_CH0_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_SBR_OFFSET)
+#define S32K3XX_EDMA_CH0_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH0_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD0_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD0_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD0_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD0_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD0_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD0_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD0_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD0_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD0_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD0_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_CSR_OFFSET)
+#define S32K3XX_EDMA_CH1_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_ES_OFFSET)
+#define S32K3XX_EDMA_CH1_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_INT_OFFSET)
+#define S32K3XX_EDMA_CH1_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_SBR_OFFSET)
+#define S32K3XX_EDMA_CH1_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH1_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD1_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD1_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD1_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD1_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD1_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD1_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD1_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD1_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD1_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD1_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_CSR_OFFSET)
+#define S32K3XX_EDMA_CH2_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_ES_OFFSET)
+#define S32K3XX_EDMA_CH2_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_INT_OFFSET)
+#define S32K3XX_EDMA_CH2_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_SBR_OFFSET)
+#define S32K3XX_EDMA_CH2_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH2_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD2_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD2_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD2_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD2_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD2_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD2_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD2_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD2_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD2_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD2_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_CSR_OFFSET)
+#define S32K3XX_EDMA_CH3_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_ES_OFFSET)
+#define S32K3XX_EDMA_CH3_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_INT_OFFSET)
+#define S32K3XX_EDMA_CH3_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_SBR_OFFSET)
+#define S32K3XX_EDMA_CH3_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH3_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD3_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD3_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD3_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD3_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD3_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD3_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD3_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD3_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD3_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD3_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_CSR_OFFSET)
+#define S32K3XX_EDMA_CH4_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_ES_OFFSET)
+#define S32K3XX_EDMA_CH4_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_INT_OFFSET)
+#define S32K3XX_EDMA_CH4_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_SBR_OFFSET)
+#define S32K3XX_EDMA_CH4_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH4_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD4_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD4_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD4_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD4_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD4_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD4_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD4_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD4_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD4_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD4_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_CSR_OFFSET)
+#define S32K3XX_EDMA_CH5_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_ES_OFFSET)
+#define S32K3XX_EDMA_CH5_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_INT_OFFSET)
+#define S32K3XX_EDMA_CH5_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_SBR_OFFSET)
+#define S32K3XX_EDMA_CH5_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH5_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD5_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD5_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD5_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD5_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD5_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD5_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD5_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD5_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD5_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD5_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_CSR_OFFSET)
+#define S32K3XX_EDMA_CH6_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_ES_OFFSET)
+#define S32K3XX_EDMA_CH6_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_INT_OFFSET)
+#define S32K3XX_EDMA_CH6_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_SBR_OFFSET)
+#define S32K3XX_EDMA_CH6_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH6_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD6_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD6_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD6_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD6_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD6_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD6_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD6_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD6_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD6_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD6_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_CSR_OFFSET)
+#define S32K3XX_EDMA_CH7_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_ES_OFFSET)
+#define S32K3XX_EDMA_CH7_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_INT_OFFSET)
+#define S32K3XX_EDMA_CH7_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_SBR_OFFSET)
+#define S32K3XX_EDMA_CH7_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH7_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD7_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD7_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD7_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD7_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD7_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD7_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD7_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD7_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD7_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD7_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_CSR_OFFSET)
+#define S32K3XX_EDMA_CH8_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_ES_OFFSET)
+#define S32K3XX_EDMA_CH8_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_INT_OFFSET)
+#define S32K3XX_EDMA_CH8_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_SBR_OFFSET)
+#define S32K3XX_EDMA_CH8_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH8_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD8_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD8_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD8_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD8_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD8_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD8_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD8_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD8_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD8_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD8_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_CSR_OFFSET)
+#define S32K3XX_EDMA_CH9_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_ES_OFFSET)
+#define S32K3XX_EDMA_CH9_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_INT_OFFSET)
+#define S32K3XX_EDMA_CH9_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_SBR_OFFSET)
+#define S32K3XX_EDMA_CH9_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH9_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD9_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD9_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD9_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD9_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD9_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD9_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD9_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD9_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD9_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD9_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_CSR_OFFSET)
+#define S32K3XX_EDMA_CH10_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_ES_OFFSET)
+#define S32K3XX_EDMA_CH10_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_INT_OFFSET)
+#define S32K3XX_EDMA_CH10_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_SBR_OFFSET)
+#define S32K3XX_EDMA_CH10_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH10_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD10_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD10_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD10_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD10_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD10_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD10_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD10_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD10_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD10_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD10_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_CSR_OFFSET)
+#define S32K3XX_EDMA_CH11_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_ES_OFFSET)
+#define S32K3XX_EDMA_CH11_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_INT_OFFSET)
+#define S32K3XX_EDMA_CH11_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_SBR_OFFSET)
+#define S32K3XX_EDMA_CH11_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH11_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD11_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD11_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD11_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD11_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD11_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD11_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD11_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD11_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD11_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD11_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_CSR_OFFSET)
+#define S32K3XX_EDMA_CH12_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_ES_OFFSET)
+#define S32K3XX_EDMA_CH12_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_INT_OFFSET)
+#define S32K3XX_EDMA_CH12_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_SBR_OFFSET)
+#define S32K3XX_EDMA_CH12_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH12_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD12_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD12_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD12_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD12_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD12_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD12_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD12_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD12_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD12_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD12_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_CSR_OFFSET)
+#define S32K3XX_EDMA_CH13_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_ES_OFFSET)
+#define S32K3XX_EDMA_CH13_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_INT_OFFSET)
+#define S32K3XX_EDMA_CH13_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_SBR_OFFSET)
+#define S32K3XX_EDMA_CH13_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH13_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD13_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD13_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD13_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD13_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD13_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD13_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD13_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD13_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD13_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD13_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_CSR_OFFSET)
+#define S32K3XX_EDMA_CH14_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_ES_OFFSET)
+#define S32K3XX_EDMA_CH14_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_INT_OFFSET)
+#define S32K3XX_EDMA_CH14_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_SBR_OFFSET)
+#define S32K3XX_EDMA_CH14_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH14_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD14_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD14_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD14_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD14_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD14_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD14_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD14_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD14_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD14_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD14_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_CSR_OFFSET)
+#define S32K3XX_EDMA_CH15_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_ES_OFFSET)
+#define S32K3XX_EDMA_CH15_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_INT_OFFSET)
+#define S32K3XX_EDMA_CH15_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_SBR_OFFSET)
+#define S32K3XX_EDMA_CH15_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH15_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD15_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD15_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD15_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD15_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD15_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD15_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD15_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD15_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD15_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD15_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_CSR_OFFSET)
+#define S32K3XX_EDMA_CH16_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_ES_OFFSET)
+#define S32K3XX_EDMA_CH16_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_INT_OFFSET)
+#define S32K3XX_EDMA_CH16_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_SBR_OFFSET)
+#define S32K3XX_EDMA_CH16_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH16_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD16_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD16_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD16_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD16_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD16_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD16_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD16_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD16_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD16_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD16_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_CSR_OFFSET)
+#define S32K3XX_EDMA_CH17_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_ES_OFFSET)
+#define S32K3XX_EDMA_CH17_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_INT_OFFSET)
+#define S32K3XX_EDMA_CH17_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_SBR_OFFSET)
+#define S32K3XX_EDMA_CH17_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH17_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD17_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD17_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD17_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD17_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD17_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD17_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD17_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD17_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD17_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD17_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_CSR_OFFSET)
+#define S32K3XX_EDMA_CH18_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_ES_OFFSET)
+#define S32K3XX_EDMA_CH18_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_INT_OFFSET)
+#define S32K3XX_EDMA_CH18_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_SBR_OFFSET)
+#define S32K3XX_EDMA_CH18_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH18_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD18_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD18_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD18_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD18_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD18_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD18_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD18_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD18_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD18_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD18_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_CSR_OFFSET)
+#define S32K3XX_EDMA_CH19_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_ES_OFFSET)
+#define S32K3XX_EDMA_CH19_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_INT_OFFSET)
+#define S32K3XX_EDMA_CH19_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_SBR_OFFSET)
+#define S32K3XX_EDMA_CH19_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH19_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD19_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD19_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD19_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD19_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD19_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD19_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD19_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD19_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD19_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD19_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_CSR_OFFSET)
+#define S32K3XX_EDMA_CH20_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_ES_OFFSET)
+#define S32K3XX_EDMA_CH20_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_INT_OFFSET)
+#define S32K3XX_EDMA_CH20_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_SBR_OFFSET)
+#define S32K3XX_EDMA_CH20_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH20_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD20_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD20_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD20_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD20_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD20_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD20_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD20_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD20_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD20_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD20_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_CSR_OFFSET)
+#define S32K3XX_EDMA_CH21_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_ES_OFFSET)
+#define S32K3XX_EDMA_CH21_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_INT_OFFSET)
+#define S32K3XX_EDMA_CH21_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_SBR_OFFSET)
+#define S32K3XX_EDMA_CH21_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH21_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD21_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD21_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD21_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD21_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD21_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD21_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD21_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD21_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD21_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD21_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_CSR_OFFSET)
+#define S32K3XX_EDMA_CH22_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_ES_OFFSET)
+#define S32K3XX_EDMA_CH22_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_INT_OFFSET)
+#define S32K3XX_EDMA_CH22_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_SBR_OFFSET)
+#define S32K3XX_EDMA_CH22_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH22_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD22_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD22_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD22_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD22_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD22_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD22_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD22_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD22_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD22_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD22_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_CSR_OFFSET)
+#define S32K3XX_EDMA_CH23_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_ES_OFFSET)
+#define S32K3XX_EDMA_CH23_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_INT_OFFSET)
+#define S32K3XX_EDMA_CH23_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_SBR_OFFSET)
+#define S32K3XX_EDMA_CH23_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH23_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD23_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD23_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD23_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD23_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD23_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD23_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD23_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD23_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD23_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD23_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_CSR_OFFSET)
+#define S32K3XX_EDMA_CH24_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_ES_OFFSET)
+#define S32K3XX_EDMA_CH24_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_INT_OFFSET)
+#define S32K3XX_EDMA_CH24_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_SBR_OFFSET)
+#define S32K3XX_EDMA_CH24_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH24_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD24_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD24_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD24_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD24_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD24_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD24_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD24_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD24_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD24_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD24_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_CSR_OFFSET)
+#define S32K3XX_EDMA_CH25_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_ES_OFFSET)
+#define S32K3XX_EDMA_CH25_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_INT_OFFSET)
+#define S32K3XX_EDMA_CH25_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_SBR_OFFSET)
+#define S32K3XX_EDMA_CH25_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH25_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD25_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD25_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD25_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD25_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD25_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD25_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD25_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD25_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD25_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD25_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_CSR_OFFSET)
+#define S32K3XX_EDMA_CH26_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_ES_OFFSET)
+#define S32K3XX_EDMA_CH26_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_INT_OFFSET)
+#define S32K3XX_EDMA_CH26_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_SBR_OFFSET)
+#define S32K3XX_EDMA_CH26_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH26_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD26_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD26_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD26_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD26_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD26_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD26_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD26_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD26_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD26_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD26_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_CSR_OFFSET)
+#define S32K3XX_EDMA_CH27_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_ES_OFFSET)
+#define S32K3XX_EDMA_CH27_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_INT_OFFSET)
+#define S32K3XX_EDMA_CH27_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_SBR_OFFSET)
+#define S32K3XX_EDMA_CH27_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH27_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD27_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD27_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD27_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD27_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD27_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD27_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD27_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD27_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD27_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD27_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_CSR_OFFSET)
+#define S32K3XX_EDMA_CH28_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_ES_OFFSET)
+#define S32K3XX_EDMA_CH28_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_INT_OFFSET)
+#define S32K3XX_EDMA_CH28_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_SBR_OFFSET)
+#define S32K3XX_EDMA_CH28_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH28_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD28_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD28_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD28_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD28_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD28_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD28_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD28_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD28_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD28_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD28_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_CSR_OFFSET)
+#define S32K3XX_EDMA_CH29_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_ES_OFFSET)
+#define S32K3XX_EDMA_CH29_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_INT_OFFSET)
+#define S32K3XX_EDMA_CH29_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_SBR_OFFSET)
+#define S32K3XX_EDMA_CH29_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH29_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD29_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD29_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD29_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD29_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD29_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD29_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD29_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD29_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD29_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD29_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_CSR_OFFSET)
+#define S32K3XX_EDMA_CH30_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_ES_OFFSET)
+#define S32K3XX_EDMA_CH30_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_INT_OFFSET)
+#define S32K3XX_EDMA_CH30_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_SBR_OFFSET)
+#define S32K3XX_EDMA_CH30_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH30_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD30_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD30_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD30_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD30_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD30_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD30_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD30_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD30_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD30_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD30_BITER_OFFSET)
+
+#define S32K3XX_EDMA_CH31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_CSR_OFFSET)
+#define S32K3XX_EDMA_CH31_ES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_ES_OFFSET)
+#define S32K3XX_EDMA_CH31_INT (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_INT_OFFSET)
+#define S32K3XX_EDMA_CH31_SBR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_SBR_OFFSET)
+#define S32K3XX_EDMA_CH31_PRI (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_CH31_PRI_OFFSET)
+#define S32K3XX_EDMA_TCD31_SADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_SOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_ATTR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_ATTR_OFFSET)
+#define S32K3XX_EDMA_TCD31_NBYTES (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_NBYTES_OFFSET)
+#define S32K3XX_EDMA_TCD31_SLAST_SDA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_SLAST_SDA_OFFSET)
+#define S32K3XX_EDMA_TCD31_DADDR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DADDR_OFFSET)
+#define S32K3XX_EDMA_TCD31_DOFF (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DOFF_OFFSET)
+#define S32K3XX_EDMA_TCD31_CITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CITER_OFFSET)
+#define S32K3XX_EDMA_TCD31_DLAST_SGA (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_DLAST_SGA_OFFSET)
+#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
+#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
+
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
+/* eDMA Register Bitfield Definitions ***************************************/
+
+/* Management Page Control Register (CSR) */
+
+ /* Bit 0: Reserved */
+#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
+#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
+ /* Bit 3: Reserved */
+#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
+#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
+#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
+#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
+#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
+#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
+ /* Bits 10-23: Reserved */
+#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
+#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
+
+/* Management Page Error Status Register (ES) */
+
+#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
+#define EDMA_ES_UCE (1 << 9) /* Bit 9: Uncorrectable TCD Error During Channel Execution (UCE) */
+ /* Bits 10-23: Reserved */
+#define EDMA_ES_ERRCHN_SHIFT (8) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
+#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
+ /* Bits 29-30: Reserved */
+#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
+
+/* Management Page Interrupt Request Status Register (INT) */
+
+#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
+
+/* Management Page Hardware Request Status Register (HRS) */
+
+#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
+
+/* Channel n Arbitration Group Register (CHn_GRPRI) */
+
+#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
+#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
+ /* Bits 5-31: Reserved */
+
+/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
+
+/* Channel n Control and Status Register (CHn_CSR) */
+
+#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
+#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
+#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
+#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
+ /* Bit 4-29: Reserved */
+#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
+#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
+
+/* Channel n Error Status Register (CHn_ES) */
+
+#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
+#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
+#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
+#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
+#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
+#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
+#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
+#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
+ /* Bit 8-30: Reserved */
+#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
+
+/* Channel n Interrupt Status Register (CHn_INT) */
+
+#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
+ /* Bits 1-31: Reserved */
+
+/* Channel n System Bus Register (CHn_SBR) */
+
+#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
+#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
+ /* Bits 4-14: Reserved */
+#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
+#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
+#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
+#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
+ /* Bits 20-31: Reserved */
+
+/* Channel n Priority Register (CHn_PRI) */
+
+#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
+#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
+ /* Bits 3-29: Reserved */
+#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
+#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
+
+/* TCDn Source Address Register (TCDn_SADDR) */
+
+#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
+#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
+
+/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
+
+#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
+#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
+
+/* TCDn Transfer Attributes (TCDn_ATTR) */
+
+#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
+#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
+#define EDMA_TCD_ATTR_DSIZE(n) ((n << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
+#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
+#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
+#define EDMA_TCD_ATTR_DMOD(n) ((n << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
+#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
+#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
+#define EDMA_TCD_ATTR_SSIZE(n) ((n << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
+# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
+# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
+# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
+# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
+# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
+# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
+
+#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
+#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
+#define EDMA_TCD_ATTR_SMOD(n) ((n << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
+
+/* TCDn Transfer Size (TCDn_NBYTES) */
+
+#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
+#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
+#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
+#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
+#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
+#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
+
+/* TCDn Last Source Address Adjustment / Store DADDR Address Register
+ * (TCDn_SLAST_SDA)
+ */
+
+#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
+#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
+
+/* TCDn Destination Address Register (TCDn_DADDR) */
+
+#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
+#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
+
+/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
+
+#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
+#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
+
+/* TCDn Current Major Loop Count Register (TCDn_CITER) */
+
+#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
+#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
+#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
+#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_LINKCH(n) ((n << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
+#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
+
+/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
+ * (TCDn_DLAST_SGA)
+ */
+
+#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
+#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
+
+/* TCDn Control and Status Register (TCDn_CSR) */
+
+#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
+#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
+#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
+#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
+#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
+#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
+#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
+#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
+#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
+#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
+#define EDMA_TCD_CSR_MAJORLINKCH(n) ((n << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
+ /* Bit 13: Reserved */
+#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
+#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
+# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
+# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */
+# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */
+# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */
+
+/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */
+
+#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */
+#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT)
+#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
+#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
+#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
+#define EDMA_TCD_BITER_LINKCH(n) ((n << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
+#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/* In-memory representation of the 32-byte Transfer Control Descriptor
+ * (TCD)
+ */
+
+struct s32k3xx_edmatcd_s
+{
+ sq_entry_t node;
+ uint8_t flags; /* See EDMA_CONFIG_* definitions */
+ uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
+ uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
+ uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
+ uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
+ uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
+ uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
+ uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
+ uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
+ uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
+ uint16_t csr; /* Offset: 0x001c TCD Control and Status */
+ uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
+};
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EDMA_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h
new file mode 100644
index 0000000000..badcdec457
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h
@@ -0,0 +1,254 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_eim.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EIM_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EIM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EIM Register Offsets *****************************************************/
+
+#define S32K3XX_EIM_EIMCR_OFFSET (0x0000) /* Error Injection Module Configuration Register (EIMCR) */
+#define S32K3XX_EIM_EICHEN_OFFSET (0x0004) /* Error Injection Channel Enable Register (EICHEN) */
+
+/* Note: Not all Error Injection Channel Descriptors consist of 6 words.
+ * See the S32K3xx Reference Manual for more information and to check which
+ * registers are available.
+ */
+
+#define S32K3XX_EIM_EICHD_WORD0_OFFSET(n) (0x0100 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0) */
+#define S32K3XX_EIM_EICHD_WORD1_OFFSET(n) (0x0104 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1) */
+#define S32K3XX_EIM_EICHD_WORD2_OFFSET(n) (0x0108 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 2 (EICHDn_WORD2) */
+#define S32K3XX_EIM_EICHD_WORD3_OFFSET(n) (0x010c + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 3 (EICHDn_WORD3) */
+#define S32K3XX_EIM_EICHD_WORD4_OFFSET(n) (0x0110 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 4 (EICHDn_WORD4) */
+#define S32K3XX_EIM_EICHD_WORD5_OFFSET(n) (0x0114 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 5 (EICHDn_WORD5) */
+#define S32K3XX_EIM_EICHD_WORD6_OFFSET(n) (0x0118 + ((n) << 6)) /* Error Injection Channel Descriptor n, Word 6 (EICHDn_WORD6) */
+
+/* EIM Register Addresses ***************************************************/
+
+#define S32K3XX_EIM_EIMCR (S32K3XX_EIM_BASE + S32K3XX_EIM_EIMCR_OFFSET)
+#define S32K3XX_EIM_EICHEN (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHEN_OFFSET)
+#define S32K3XX_EIM_EICHD_WORD0(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD0_OFFSET(n))
+#define S32K3XX_EIM_EICHD_WORD1(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD1_OFFSET(n))
+#define S32K3XX_EIM_EICHD_WORD2(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD2_OFFSET(n))
+#define S32K3XX_EIM_EICHD_WORD3(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD3_OFFSET(n))
+#define S32K3XX_EIM_EICHD_WORD4(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD4_OFFSET(n))
+#define S32K3XX_EIM_EICHD_WORD5(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD5_OFFSET(n))
+#define S32K3XX_EIM_EICHD_WORD6(n) (S32K3XX_EIM_BASE + S32K3XX_EIM_EICHD_WORD6_OFFSET(n))
+
+/* EIM Register Bitfield Definitions ****************************************/
+
+/* Error Injection Module Configuration Register (EIMCR) */
+
+#define EIM_EIMCR_GEIEN (1 << 0) /* Bit 0: Global Error Injection Enable (GEIEN) */
+ /* Bits 1-31: Reserved */
+
+/* Error Injection Channel Enable Register (EICHEN) */
+
+ /* Bit 0: Reserved */
+#define EIM_EICHEN_EICH30EN (1 << 1) /* Bit 1: Error Injection Channel 30 Enable (EICH30EN) */
+#define EIM_EICHEN_EICH29EN (1 << 2) /* Bit 2: Error Injection Channel 29 Enable (EICH29EN) */
+#define EIM_EICHEN_EICH28EN (1 << 3) /* Bit 3: Error Injection Channel 28 Enable (EICH28EN) */
+#define EIM_EICHEN_EICH27EN (1 << 4) /* Bit 4: Error Injection Channel 27 Enable (EICH27EN) */
+#define EIM_EICHEN_EICH26EN (1 << 5) /* Bit 5: Error Injection Channel 26 Enable (EICH26EN) */
+#define EIM_EICHEN_EICH25EN (1 << 6) /* Bit 6: Error Injection Channel 25 Enable (EICH25EN) */
+#define EIM_EICHEN_EICH24EN (1 << 7) /* Bit 7: Error Injection Channel 24 Enable (EICH24EN) */
+#define EIM_EICHEN_EICH23EN (1 << 8) /* Bit 8: Error Injection Channel 23 Enable (EICH23EN) */
+#define EIM_EICHEN_EICH22EN (1 << 9) /* Bit 9: Error Injection Channel 22 Enable (EICH22EN) */
+#define EIM_EICHEN_EICH21EN (1 << 10) /* Bit 10: Error Injection Channel 21 Enable (EICH21EN) */
+#define EIM_EICHEN_EICH20EN (1 << 11) /* Bit 11: Error Injection Channel 20 Enable (EICH20EN) */
+#define EIM_EICHEN_EICH19EN (1 << 12) /* Bit 12: Error Injection Channel 19 Enable (EICH19EN) */
+#define EIM_EICHEN_EICH18EN (1 << 13) /* Bit 13: Error Injection Channel 18 Enable (EICH18EN) */
+#define EIM_EICHEN_EICH17EN (1 << 14) /* Bit 14: Error Injection Channel 17 Enable (EICH17EN) */
+#define EIM_EICHEN_EICH16EN (1 << 15) /* Bit 15: Error Injection Channel 16 Enable (EICH16EN) */
+#define EIM_EICHEN_EICH15EN (1 << 16) /* Bit 16: Error Injection Channel 15 Enable (EICH15EN) */
+#define EIM_EICHEN_EICH14EN (1 << 17) /* Bit 17: Error Injection Channel 14 Enable (EICH14EN) */
+#define EIM_EICHEN_EICH13EN (1 << 18) /* Bit 18: Error Injection Channel 13 Enable (EICH13EN) */
+#define EIM_EICHEN_EICH12EN (1 << 19) /* Bit 19: Error Injection Channel 12 Enable (EICH12EN) */
+#define EIM_EICHEN_EICH11EN (1 << 20) /* Bit 20: Error Injection Channel 11 Enable (EICH11EN) */
+#define EIM_EICHEN_EICH10EN (1 << 21) /* Bit 21: Error Injection Channel 10 Enable (EICH10EN) */
+#define EIM_EICHEN_EICH9EN (1 << 22) /* Bit 22: Error Injection Channel 9 Enable (EICH9EN) */
+#define EIM_EICHEN_EICH8EN (1 << 23) /* Bit 23: Error Injection Channel 8 Enable (EICH8EN) */
+#define EIM_EICHEN_EICH7EN (1 << 24) /* Bit 24: Error Injection Channel 7 Enable (EICH7EN) */
+#define EIM_EICHEN_EICH6EN (1 << 25) /* Bit 25: Error Injection Channel 6 Enable (EICH6EN) */
+#define EIM_EICHEN_EICH5EN (1 << 26) /* Bit 26: Error Injection Channel 5 Enable (EICH5EN) */
+#define EIM_EICHEN_EICH4EN (1 << 27) /* Bit 27: Error Injection Channel 4 Enable (EICH4EN) */
+#define EIM_EICHEN_EICH3EN (1 << 28) /* Bit 28: Error Injection Channel 3 Enable (EICH3EN) */
+#define EIM_EICHEN_EICH2EN (1 << 29) /* Bit 29: Error Injection Channel 2 Enable (EICH2EN) */
+#define EIM_EICHEN_EICH1EN (1 << 30) /* Bit 30: Error Injection Channel 1 Enable (EICH1EN) */
+#define EIM_EICHEN_EICH0EN (1 << 31) /* Bit 31: Error Injection Channel 0 Enable (EICH0EN) */
+
+/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=0,1,2) */
+
+ /* Bits 0-23: Reserved */
+#define EIM_EICHD0_2_WORD0_CHKBIT_SHIFT (24) /* Bits 24-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD0_2_WORD0_CHKBIT_MASK (0xff << EIM_EICHD0_2_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor 3, Word 0 (EICHD3_WORD0) */
+
+ /* Bits 0-17: Reserved */
+#define EIM_EICHD3_WORD0_CHKBIT_SHIFT (18) /* Bits 18-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD3_WORD0_CHKBIT_MASK (0x3fff << EIM_EICHD3_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor 4, Word 0 (EICHD4_WORD0) */
+
+ /* Bits 0-15: Reserved */
+#define EIM_EICHD4_WORD0_CHKBIT_SHIFT (16) /* Bits 16-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD4_WORD0_CHKBIT_MASK (0xffff << EIM_EICHD4_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=5,6,7) */
+
+ /* Bits 0-3: Reserved */
+#define EIM_EICHD5_7_WORD0_CHKBIT_SHIFT (4) /* Bits 4-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD5_7_WORD0_CHKBIT_MASK (0x0fffffff << EIM_EICHD5_7_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor 8, Word 0 (EICHD8_WORD0) */
+
+ /* Bits 0-17: Reserved */
+#define EIM_EICHD8_WORD0_CHKBIT_SHIFT (18) /* Bits 18-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD8_WORD0_CHKBIT_MASK (0x3fff << EIM_EICHD8_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor 9, Word 0 (EICHD9_WORD0) */
+
+ /* Bits 0-15: Reserved */
+#define EIM_EICHD9_WORD0_CHKBIT_SHIFT (16) /* Bits 16-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD9_WORD0_CHKBIT_MASK (0xffff << EIM_EICHD9_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=10,11,12) */
+
+ /* Bits 0-3: Reserved */
+#define EIM_EICHD10_12_WORD0_CHKBIT_SHIFT (4) /* Bits 4-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD10_12_WORD0_CHKBIT_MASK (0x0fffffff << EIM_EICHD10_12_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 0 (EICHDn_WORD0, n=13,...,18) */
+
+ /* Bits 0-23: Reserved */
+#define EIM_EICHD13_18_WORD0_CHKBIT_SHIFT (24) /* Bits 24-31: Checkbit Mask (CHKBIT_MASK) */
+#define EIM_EICHD13_18_WORD0_CHKBIT_MASK (0xff << EIM_EICHD13_18_WORD0_CHKBIT_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=0,1,2) */
+
+#define EIM_EICHD0_2_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD0_2_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD0_2_WORD1_B0_3DATA_SHIFT)
+
+/* Error Injection Channel Descriptor 3, Word 1 (EICHD3_WORD1) */
+
+#define EIM_EICHD3_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-11: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD3_WORD1_B0_3DATA_MASK (0x0fff << EIM_EICHD3_WORD1_B0_3DATA_SHIFT)
+ /* Bits 12-31: Reserved */
+
+/* Error Injection Channel Descriptor 4, Word 1 (EICHD4_WORD1) */
+
+#define EIM_EICHD4_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD4_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD4_WORD1_B0_3DATA_SHIFT)
+
+/* Error Injection Channel Descriptor 5, Word 1 (EICHD5_WORD1) */
+
+#define EIM_EICHD5_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-7: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD5_WORD1_B0_3DATA_MASK (0xff << EIM_EICHD5_WORD1_B0_3DATA_SHIFT)
+ /* Bits 8-31: Reserved */
+
+/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=6,7) */
+
+#define EIM_EICHD6_7_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD6_7_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD6_7_WORD1_B0_3DATA_SHIFT)
+
+/* Error Injection Channel Descriptor 8, Word 1 (EICHD8_WORD1) */
+
+#define EIM_EICHD8_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-11: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD8_WORD1_B0_3DATA_MASK (0x0fff << EIM_EICHD8_WORD1_B0_3DATA_SHIFT)
+ /* Bits 12-31: Reserved */
+
+/* Error Injection Channel Descriptor 9, Word 1 (EICHD9_WORD1) */
+
+#define EIM_EICHD9_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD9_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD9_WORD1_B0_3DATA_SHIFT)
+
+/* Error Injection Channel Descriptor 10, Word 1 (EICHD10_WORD1) */
+
+#define EIM_EICHD10_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-7: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD10_WORD1_B0_3DATA_MASK (0xff << EIM_EICHD10_WORD1_B0_3DATA_SHIFT)
+ /* Bits 8-31: Reserved */
+
+/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=11,...,18) */
+
+#define EIM_EICHD11_18_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD11_18_WORD1_B0_3DATA_MASK (0xffffffff << EIM_EICHD11_18_WORD1_B0_3DATA_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=19,...,26) */
+
+#define EIM_EICHD19_26_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-27: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD19_26_WORD1_B0_3DATA_MASK (0x0fffffff << EIM_EICHD19_26_WORD1_B0_3DATA_SHIFT)
+ /* Bits 28-31: Reserved */
+
+/* Error Injection Channel Descriptor 27, Word 1 (EICHD27_WORD1) */
+
+#define EIM_EICHD27_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-29: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD27_WORD1_B0_3DATA_MASK (0x3fffffff << EIM_EICHD27_WORD1_B0_3DATA_SHIFT)
+ /* Bits 30-31: Reserved */
+
+/* Error Injection Channel Descriptor 28, Word 1 (EICHD28_WORD1) */
+
+#define EIM_EICHD28_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-23: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD28_WORD1_B0_3DATA_MASK (0xffffff << EIM_EICHD28_WORD1_B0_3DATA_SHIFT)
+ /* Bits 24-31: Reserved */
+
+/* Error Injection Channel Descriptor n, Word 1 (EICHDn_WORD1, n=29,30) */
+
+#define EIM_EICHD29_30_WORD1_B0_3DATA_SHIFT (0) /* Bits 0-17: Data Mask Bytes 0-3 (B0_3DATA_MASK) */
+#define EIM_EICHD29_30_WORD1_B0_3DATA_MASK (0x03ffff << EIM_EICHD29_30_WORD1_B0_3DATA_SHIFT)
+ /* Bits 18-31: Reserved */
+
+/* Error Injection Channel Descriptor n, Word 2 (EICHDn_WORD2) */
+
+#define EIM_EICHD_WORD2_B4_7DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 4-7 (B4_7DATA_MASK) */
+#define EIM_EICHD_WORD2_B4_7DATA_MASK (0xffffffff << EIM_EICHD_WORD2_B4_7DATA_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 3 (EICHDn_WORD3) */
+
+#define EIM_EICHD_WORD3_B8_11DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 8-11 (B8_11DATA_MASK) */
+#define EIM_EICHD_WORD3_B8_11DATA_MASK (0xffffffff << EIM_EICHD_WORD3_B8_11DATA_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 4 (EICHDn_WORD4) */
+
+#define EIM_EICHD_WORD4_B12_15DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 12-15 (B12_15DATA_MASK) */
+#define EIM_EICHD_WORD4_B12_15DATA_MASK (0xffffffff << EIM_EICHD_WORD4_B12_15DATA_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 5 (EICHDn_WORD5) */
+
+#define EIM_EICHD_WORD5_B16_19DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 16-19 (B16_19DATA_MASK) */
+#define EIM_EICHD_WORD5_B16_19DATA_MASK (0xffffffff << EIM_EICHD_WORD5_B16_19DATA_SHIFT)
+
+/* Error Injection Channel Descriptor n, Word 6 (EICHDn_WORD6) */
+
+#define EIM_EICHD_WORD6_B20_23DATA_SHIFT (0) /* Bits 0-31: Data Mask Bytes 20-23 (B20_23DATA_MASK) */
+#define EIM_EICHD_WORD6_B20_23DATA_MASK (0xffffffff << EIM_EICHD_WORD6_B20_23DATA_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EIM_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
new file mode 100644
index 0000000000..3ebb256b27
--- /dev/null
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
@@ -0,0 +1,3084 @@
+/****************************************************************************
+ * arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMAC_H
+#define __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMAC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <hardware/s32k3xx_memorymap.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EMAC Register Offsets ****************************************************/
+
+#define S32K3XX_EMAC_MAC_CONFIGURATION_OFFSET (0x0000)
+#define S32K3XX_EMAC_MAC_EXT_CONFIGURATION_OFFSET (0x0004)
+#define S32K3XX_EMAC_MAC_PACKET_FILTER_OFFSET (0x0008)
+#define S32K3XX_EMAC_MAC_WATCHDOG_TIMEOUT_OFFSET (0x000c)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG0_OFFSET (0x0010)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG1_OFFSET (0x0014)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_OFFSET (0x0050)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_CTRL_OFFSET (0x0050)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_DATA_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER0_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER1_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER2_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER3_OFFSET (0x0054)
+#define S32K3XX_EMAC_MAC_VLAN_HASH_TABLE_OFFSET (0x0058)
+#define S32K3XX_EMAC_MAC_VLAN_INCL_OFFSET (0x0060)
+#define S32K3XX_EMAC_MAC_INNER_VLAN_INCL_OFFSET (0x0064)
+#define S32K3XX_EMAC_MAC_Q0_TX_FLOW_CTRL_OFFSET (0x0070)
+#define S32K3XX_EMAC_MAC_RX_FLOW_CTRL_OFFSET (0x0090)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL4_OFFSET (0x0094)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL0_OFFSET (0x00a0)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL1_OFFSET (0x00a4)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL2_OFFSET (0x00a8)
+#define S32K3XX_EMAC_MAC_INTERRUPT_STATUS_OFFSET (0x00b0)
+#define S32K3XX_EMAC_MAC_INTERRUPT_ENABLE_OFFSET (0x00b4)
+#define S32K3XX_EMAC_MAC_RX_TX_STATUS_OFFSET (0x00b8)
+#define S32K3XX_EMAC_MAC_VERSION_OFFSET (0x0110)
+#define S32K3XX_EMAC_MAC_DEBUG_OFFSET (0x0114)
+#define S32K3XX_EMAC_MAC_HW_FEATURE0_OFFSET (0x011c)
+#define S32K3XX_EMAC_MAC_HW_FEATURE1_OFFSET (0x0120)
+#define S32K3XX_EMAC_MAC_HW_FEATURE2_OFFSET (0x0124)
+#define S32K3XX_EMAC_MAC_HW_FEATURE3_OFFSET (0x0128)
+#define S32K3XX_EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_OFFSET (0x0140)
+#define S32K3XX_EMAC_MAC_FSM_CONTROL_OFFSET (0x0148)
+#define S32K3XX_EMAC_MAC_FSM_ACT_TIMER_OFFSET (0x014c)
+#define S32K3XX_EMAC_SCS_REG1_OFFSET (0x0150)
+#define S32K3XX_EMAC_MAC_MDIO_ADDRESS_OFFSET (0x0200)
+#define S32K3XX_EMAC_MAC_MDIO_DATA_OFFSET (0x0204)
+#define S32K3XX_EMAC_MAC_CSR_SW_CTRL_OFFSET (0x0230)
+#define S32K3XX_EMAC_MAC_FPE_CTRL_STS_OFFSET (0x0234)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_NS_OFFSET (0x0240)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_UPDT_OFFSET (0x0244)
+#define S32K3XX_EMAC_MAC_ADDRESS0_HIGH_OFFSET (0x0300)
+#define S32K3XX_EMAC_MAC_ADDRESS0_LOW_OFFSET (0x0304)
+#define S32K3XX_EMAC_MAC_ADDRESS1_HIGH_OFFSET (0x0308)
+#define S32K3XX_EMAC_MAC_ADDRESS1_LOW_OFFSET (0x030c)
+#define S32K3XX_EMAC_MAC_ADDRESS2_HIGH_OFFSET (0x0310)
+#define S32K3XX_EMAC_MAC_ADDRESS2_LOW_OFFSET (0x0314)
+#define S32K3XX_EMAC_MMC_CONTROL_OFFSET (0x0700)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT_OFFSET (0x0704)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT_OFFSET (0x0708)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT_MASK_OFFSET (0x070c)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT_MASK_OFFSET (0x0710)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_BAD_OFFSET (0x0714)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_BAD_OFFSET (0x0718)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_OFFSET (0x071c)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_OFFSET (0x0720)
+#define S32K3XX_EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0724)
+#define S32K3XX_EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0728)
+#define S32K3XX_EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET (0x072c)
+#define S32K3XX_EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0730)
+#define S32K3XX_EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET (0x0734)
+#define S32K3XX_EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET (0x0738)
+#define S32K3XX_EMAC_TX_UNICAST_PACKETS_GOOD_BAD_OFFSET (0x073c)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_OFFSET (0x0740)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_OFFSET (0x0744)
+#define S32K3XX_EMAC_TX_UNDERFLOW_ERROR_PACKETS_OFFSET (0x0748)
+#define S32K3XX_EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_OFFSET (0x074c)
+#define S32K3XX_EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_OFFSET (0x0750)
+#define S32K3XX_EMAC_TX_DEFERRED_PACKETS_OFFSET (0x0754)
+#define S32K3XX_EMAC_TX_LATE_COLLISION_PACKETS_OFFSET (0x0758)
+#define S32K3XX_EMAC_TX_EXCESSIVE_COLLISION_PACKETS_OFFSET (0x075c)
+#define S32K3XX_EMAC_TX_CARRIER_ERROR_PACKETS_OFFSET (0x0760)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_OFFSET (0x0764)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_OFFSET (0x0768)
+#define S32K3XX_EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET (0x076c)
+#define S32K3XX_EMAC_TX_PAUSE_PACKETS_OFFSET (0x0770)
+#define S32K3XX_EMAC_TX_VLAN_PACKETS_GOOD_OFFSET (0x0774)
+#define S32K3XX_EMAC_TX_OSIZE_PACKETS_GOOD_OFFSET (0x0778)
+#define S32K3XX_EMAC_RX_PACKETS_COUNT_GOOD_BAD_OFFSET (0x0780)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_BAD_OFFSET (0x0784)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_OFFSET (0x0788)
+#define S32K3XX_EMAC_RX_BROADCAST_PACKETS_GOOD_OFFSET (0x078c)
+#define S32K3XX_EMAC_RX_MULTICAST_PACKETS_GOOD_OFFSET (0x0790)
+#define S32K3XX_EMAC_RX_CRC_ERROR_PACKETS_OFFSET (0x0794)
+#define S32K3XX_EMAC_RX_ALIGNMENT_ERROR_PACKETS_OFFSET (0x0798)
+#define S32K3XX_EMAC_RX_RUNT_ERROR_PACKETS_OFFSET (0x079c)
+#define S32K3XX_EMAC_RX_JABBER_ERROR_PACKETS_OFFSET (0x07a0)
+#define S32K3XX_EMAC_RX_UNDERSIZE_PACKETS_GOOD_OFFSET (0x07a4)
+#define S32K3XX_EMAC_RX_OVERSIZE_PACKETS_GOOD_OFFSET (0x07a8)
+#define S32K3XX_EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07ac)
+#define S32K3XX_EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07b0)
+#define S32K3XX_EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07b4)
+#define S32K3XX_EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07b8)
+#define S32K3XX_EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET (0x07bc)
+#define S32K3XX_EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET (0x07c0)
+#define S32K3XX_EMAC_RX_UNICAST_PACKETS_GOOD_OFFSET (0x07c4)
+#define S32K3XX_EMAC_RX_LENGTH_ERROR_PACKETS_OFFSET (0x07c8)
+#define S32K3XX_EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_OFFSET (0x07cc)
+#define S32K3XX_EMAC_RX_PAUSE_PACKETS_OFFSET (0x07d0)
+#define S32K3XX_EMAC_RX_FIFO_OVERFLOW_PACKETS_OFFSET (0x07d4)
+#define S32K3XX_EMAC_RX_VLAN_PACKETS_GOOD_BAD_OFFSET (0x07d8)
+#define S32K3XX_EMAC_RX_WATCHDOG_ERROR_PACKETS_OFFSET (0x07dc)
+#define S32K3XX_EMAC_RX_RECEIVE_ERROR_PACKETS_OFFSET (0x07e0)
+#define S32K3XX_EMAC_RX_CONTROL_PACKETS_GOOD_OFFSET (0x07e4)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_OFFSET (0x08a0)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_MASK_OFFSET (0x08a4)
+#define S32K3XX_EMAC_MMC_TX_FPE_FRAGMENT_CNTR_OFFSET (0x08a8)
+#define S32K3XX_EMAC_MMC_TX_HOLD_REQ_CNTR_OFFSET (0x08ac)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_OFFSET (0x08c0)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_MASK_OFFSET (0x08c4)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_OFFSET (0x08c8)
+#define S32K3XX_EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_OFFSET (0x08cc)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_OFFSET (0x08d0)
+#define S32K3XX_EMAC_MMC_RX_FPE_FRAGMENT_CNTR_OFFSET (0x08d4)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL0_OFFSET (0x0900)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS0_OFFSET (0x0904)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG0_OFFSET (0x0910)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG0_OFFSET (0x0914)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG0_OFFSET (0x0918)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG0_OFFSET (0x091c)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL1_OFFSET (0x0930)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS1_OFFSET (0x0934)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG1_OFFSET (0x0940)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG1_OFFSET (0x0944)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG1_OFFSET (0x0948)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG1_OFFSET (0x094c)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL2_OFFSET (0x0960)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS2_OFFSET (0x0964)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG2_OFFSET (0x0970)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG2_OFFSET (0x0974)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG2_OFFSET (0x0978)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG2_OFFSET (0x097c)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL3_OFFSET (0x0990)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS3_OFFSET (0x0994)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG3_OFFSET (0x09a0)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG3_OFFSET (0x09a4)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG3_OFFSET (0x09a8)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG3_OFFSET (0x09ac)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_CONTROL_OFFSET (0x0b00)
+#define S32K3XX_EMAC_MAC_SUB_SECOND_INCREMENT_OFFSET (0x0b04)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_OFFSET (0x0b08)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_OFFSET (0x0b0c)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_OFFSET (0x0b10)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_OFFSET (0x0b14)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_ADDEND_OFFSET (0x0b18)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET (0x0b1c)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_STATUS_OFFSET (0x0b20)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_OFFSET (0x0b30)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_OFFSET (0x0b34)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OFFSET (0x0b50)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OFFSET (0x0b54)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_OFFSET (0x0b58)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_OFFSET (0x0b5c)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_OFFSET (0x0b60)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_OFFSET (0x0b64)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_OFFSET (0x0b68)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_OFFSET (0x0b6c)
+#define S32K3XX_EMAC_MAC_PPS_CONTROL_OFFSET (0x0b70)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_SECONDS_OFFSET (0x0b80)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_OFFSET (0x0b84)
+#define S32K3XX_EMAC_MAC_PPS0_INTERVAL_OFFSET (0x0b88)
+#define S32K3XX_EMAC_MAC_PPS0_WIDTH_OFFSET (0x0b8c)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_SECONDS_OFFSET (0x0b90)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_OFFSET (0x0b94)
+#define S32K3XX_EMAC_MAC_PPS1_INTERVAL_OFFSET (0x0b98)
+#define S32K3XX_EMAC_MAC_PPS1_WIDTH_OFFSET (0x0b9c)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_SECONDS_OFFSET (0x0ba0)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_OFFSET (0x0ba4)
+#define S32K3XX_EMAC_MAC_PPS2_INTERVAL_OFFSET (0x0ba8)
+#define S32K3XX_EMAC_MAC_PPS2_WIDTH_OFFSET (0x0bac)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_SECONDS_OFFSET (0x0bb0)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_OFFSET (0x0bb4)
+#define S32K3XX_EMAC_MAC_PPS3_INTERVAL_OFFSET (0x0bb8)
+#define S32K3XX_EMAC_MAC_PPS3_WIDTH_OFFSET (0x0bbc)
+#define S32K3XX_EMAC_MTL_OPERATION_MODE_OFFSET (0x0c00)
+#define S32K3XX_EMAC_MTL_DBG_CTL_OFFSET (0x0c08)
+#define S32K3XX_EMAC_MTL_DBG_STS_OFFSET (0x0c0c)
+#define S32K3XX_EMAC_MTL_FIFO_DEBUG_DATA_OFFSET (0x0c10)
+#define S32K3XX_EMAC_MTL_INTERRUPT_STATUS_OFFSET (0x0c20)
+#define S32K3XX_EMAC_MTL_RXQ_DMA_MAP0_OFFSET (0x0c30)
+#define S32K3XX_EMAC_MTL_TBS_CTRL_OFFSET (0x0c40)
+#define S32K3XX_EMAC_MTL_EST_CONTROL_OFFSET (0x0c50)
+#define S32K3XX_EMAC_MTL_EST_STATUS_OFFSET (0x0c58)
+#define S32K3XX_EMAC_MTL_EST_SCH_ERROR_OFFSET (0x0c60)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_ERROR_OFFSET (0x0c64)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_CAPTURE_OFFSET (0x0c68)
+#define S32K3XX_EMAC_MTL_EST_INTR_ENABLE_OFFSET (0x0c70)
+#define S32K3XX_EMAC_MTL_EST_GCL_CONTROL_OFFSET (0x0c80)
+#define S32K3XX_EMAC_MTL_EST_GCL_DATA_OFFSET (0x0c84)
+#define S32K3XX_EMAC_MTL_FPE_CTRL_STS_OFFSET (0x0c90)
+#define S32K3XX_EMAC_MTL_FPE_ADVANCE_OFFSET (0x0c94)
+#define S32K3XX_EMAC_MTL_RXP_CONTROL_STATUS_OFFSET (0x0ca0)
+#define S32K3XX_EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_OFFSET (0x0ca4)
+#define S32K3XX_EMAC_MTL_RXP_DROP_CNT_OFFSET (0x0ca8)
+#define S32K3XX_EMAC_MTL_RXP_ERROR_CNT_OFFSET (0x0cac)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_OFFSET (0x0cb0)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_DATA_OFFSET (0x0cb4)
+#define S32K3XX_EMAC_MTL_ECC_CONTROL_OFFSET (0x0cc0)
+#define S32K3XX_EMAC_MTL_SAFETY_INTERRUPT_STATUS_OFFSET (0x0cc4)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_ENABLE_OFFSET (0x0cc8)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_STATUS_OFFSET (0x0ccc)
+#define S32K3XX_EMAC_MTL_ECC_ERR_STS_RCTL_OFFSET (0x0cd0)
+#define S32K3XX_EMAC_MTL_ECC_ERR_ADDR_STATUS_OFFSET (0x0cd4)
+#define S32K3XX_EMAC_MTL_ECC_ERR_CNTR_STATUS_OFFSET (0x0cd8)
+#define S32K3XX_EMAC_MTL_DPP_CONTROL_OFFSET (0x0ce0)
+#define S32K3XX_EMAC_MTL_TXQ0_OPERATION_MODE_OFFSET (0x0d00)
+#define S32K3XX_EMAC_MTL_TXQ0_UNDERFLOW_OFFSET (0x0d04)
+#define S32K3XX_EMAC_MTL_TXQ0_DEBUG_OFFSET (0x0d08)
+#define S32K3XX_EMAC_MTL_TXQ0_ETS_STATUS_OFFSET (0x0d14)
+#define S32K3XX_EMAC_MTL_TXQ0_QUANTUM_WEIGHT_OFFSET (0x0d18)
+#define S32K3XX_EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_OFFSET (0x0d2c)
+#define S32K3XX_EMAC_MTL_RXQ0_OPERATION_MODE_OFFSET (0x0d30)
+#define S32K3XX_EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OFFSET (0x0d34)
+#define S32K3XX_EMAC_MTL_RXQ0_DEBUG_OFFSET (0x0d38)
+#define S32K3XX_EMAC_MTL_RXQ0_CONTROL_OFFSET (0x0d3c)
+#define S32K3XX_EMAC_MTL_TXQ1_OPERATION_MODE_OFFSET (0x0d40)
+#define S32K3XX_EMAC_MTL_TXQ1_UNDERFLOW_OFFSET (0x0d44)
+#define S32K3XX_EMAC_MTL_TXQ1_DEBUG_OFFSET (0x0d48)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_CONTROL_OFFSET (0x0d50)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_STATUS_OFFSET (0x0d54)
+#define S32K3XX_EMAC_MTL_TXQ1_QUANTUM_WEIGHT_OFFSET (0x0d58)
+#define S32K3XX_EMAC_MTL_TXQ1_SENDSLOPECREDIT_OFFSET (0x0d5c)
+#define S32K3XX_EMAC_MTL_TXQ1_HICREDIT_OFFSET (0x0d60)
+#define S32K3XX_EMAC_MTL_TXQ1_LOCREDIT_OFFSET (0x0d64)
+#define S32K3XX_EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_OFFSET (0x0d6c)
+#define S32K3XX_EMAC_MTL_RXQ1_OPERATION_MODE_OFFSET (0x0d70)
+#define S32K3XX_EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OFFSET (0x0d74)
+#define S32K3XX_EMAC_MTL_RXQ1_DEBUG_OFFSET (0x0d78)
+#define S32K3XX_EMAC_MTL_RXQ1_CONTROL_OFFSET (0x0d7c)
+#define S32K3XX_EMAC_DMA_MODE_OFFSET (0x1000)
+#define S32K3XX_EMAC_DMA_SYSBUS_MODE_OFFSET (0x1004)
+#define S32K3XX_EMAC_DMA_INTERRUPT_STATUS_OFFSET (0x1008)
+#define S32K3XX_EMAC_DMA_DEBUG_STATUS0_OFFSET (0x100c)
+#define S32K3XX_EMAC_DMA_TBS_CTRL_OFFSET (0x1050)
+#define S32K3XX_EMAC_DMA_SAFETY_INTERRUPT_STATUS_OFFSET (0x1080)
+#define S32K3XX_EMAC_DMA_CH0_CONTROL_OFFSET (0x1100)
+#define S32K3XX_EMAC_DMA_CH0_TX_CONTROL_OFFSET (0x1104)
+#define S32K3XX_EMAC_DMA_CH0_RX_CONTROL_OFFSET (0x1108)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_OFFSET (0x1114)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_OFFSET (0x111c)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_TAIL_POINTER_OFFSET (0x1120)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_TAIL_POINTER_OFFSET (0x1128)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_RING_LENGTH_OFFSET (0x112c)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_RING_LENGTH_OFFSET (0x1130)
+#define S32K3XX_EMAC_DMA_CH0_INTERRUPT_ENABLE_OFFSET (0x1134)
+#define S32K3XX_EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET (0x1138)
+#define S32K3XX_EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_OFFSET (0x113c)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXDESC_OFFSET (0x1144)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXDESC_OFFSET (0x114c)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_OFFSET (0x1154)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_OFFSET (0x115c)
+#define S32K3XX_EMAC_DMA_CH0_STATUS_OFFSET (0x1160)
+#define S32K3XX_EMAC_DMA_CH0_MISS_FRAME_CNT_OFFSET (0x1164)
+#define S32K3XX_EMAC_DMA_CH0_RXP_ACCEPT_CNT_OFFSET (0x1168)
+#define S32K3XX_EMAC_DMA_CH0_RX_ERI_CNT_OFFSET (0x116c)
+#define S32K3XX_EMAC_DMA_CH1_CONTROL_OFFSET (0x1180)
+#define S32K3XX_EMAC_DMA_CH1_TX_CONTROL_OFFSET (0x1184)
+#define S32K3XX_EMAC_DMA_CH1_RX_CONTROL_OFFSET (0x1188)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_OFFSET (0x1194)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_OFFSET (0x119c)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_TAIL_POINTER_OFFSET (0x11a0)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_TAIL_POINTER_OFFSET (0x11a8)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_RING_LENGTH_OFFSET (0x11ac)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_RING_LENGTH_OFFSET (0x11b0)
+#define S32K3XX_EMAC_DMA_CH1_INTERRUPT_ENABLE_OFFSET (0x11b4)
+#define S32K3XX_EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET (0x11b8)
+#define S32K3XX_EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_OFFSET (0x11bc)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXDESC_OFFSET (0x11c4)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXDESC_OFFSET (0x11cc)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_OFFSET (0x11d4)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_OFFSET (0x11dc)
+#define S32K3XX_EMAC_DMA_CH1_STATUS_OFFSET (0x11e0)
+#define S32K3XX_EMAC_DMA_CH1_MISS_FRAME_CNT_OFFSET (0x11e4)
+#define S32K3XX_EMAC_DMA_CH1_RXP_ACCEPT_CNT_OFFSET (0x11e8)
+#define S32K3XX_EMAC_DMA_CH1_RX_ERI_CNT_OFFSET (0x11ec)
+
+/* EMAC Register Addresses **************************************************/
+
+#define S32K3XX_EMAC_MAC_CONFIGURATION (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_CONFIGURATION_OFFSET)
+#define S32K3XX_EMAC_MAC_EXT_CONFIGURATION (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_EXT_CONFIGURATION_OFFSET)
+#define S32K3XX_EMAC_MAC_PACKET_FILTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PACKET_FILTER_OFFSET)
+#define S32K3XX_EMAC_MAC_WATCHDOG_TIMEOUT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_WATCHDOG_TIMEOUT_OFFSET)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HASH_TABLE_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_HASH_TABLE_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HASH_TABLE_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_DATA_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER0_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER1_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER2_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_TAG_FILTER3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_TAG_FILTER3_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_HASH_TABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_HASH_TABLE_OFFSET)
+#define S32K3XX_EMAC_MAC_VLAN_INCL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VLAN_INCL_OFFSET)
+#define S32K3XX_EMAC_MAC_INNER_VLAN_INCL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_INNER_VLAN_INCL_OFFSET)
+#define S32K3XX_EMAC_MAC_Q0_TX_FLOW_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_Q0_TX_FLOW_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_RX_FLOW_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RX_FLOW_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL4 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL4_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL0_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL1_OFFSET)
+#define S32K3XX_EMAC_MAC_RXQ_CTRL2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RXQ_CTRL2_OFFSET)
+#define S32K3XX_EMAC_MAC_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_MAC_RX_TX_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_RX_TX_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_VERSION (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_VERSION_OFFSET)
+#define S32K3XX_EMAC_MAC_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE0_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE1_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE2_OFFSET)
+#define S32K3XX_EMAC_MAC_HW_FEATURE3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_HW_FEATURE3_OFFSET)
+#define S32K3XX_EMAC_MAC_DPP_FSM_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_FSM_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_FSM_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MAC_FSM_ACT_TIMER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_FSM_ACT_TIMER_OFFSET)
+#define S32K3XX_EMAC_SCS_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_SCS_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_MDIO_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_MDIO_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_MAC_MDIO_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_MDIO_DATA_OFFSET)
+#define S32K3XX_EMAC_MAC_CSR_SW_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_CSR_SW_CTRL_OFFSET)
+#define S32K3XX_EMAC_MAC_FPE_CTRL_STS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_FPE_CTRL_STS_OFFSET)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_NS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PRESN_TIME_NS_OFFSET)
+#define S32K3XX_EMAC_MAC_PRESN_TIME_UPDT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PRESN_TIME_UPDT_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS0_HIGH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS0_HIGH_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS0_LOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS0_LOW_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS1_HIGH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS1_HIGH_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS1_LOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS1_LOW_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS2_HIGH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS2_HIGH_OFFSET)
+#define S32K3XX_EMAC_MAC_ADDRESS2_LOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_ADDRESS2_LOW_OFFSET)
+#define S32K3XX_EMAC_MMC_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_64OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_UNICAST_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_UNICAST_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_TX_UNDERFLOW_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_UNDERFLOW_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_DEFERRED_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_DEFERRED_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_LATE_COLLISION_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_LATE_COLLISION_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_EXCESSIVE_COLLISION_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_EXCESSIVE_COLLISION_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_CARRIER_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_CARRIER_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_OCTET_COUNT_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_OCTET_COUNT_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_PACKET_COUNT_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_PACKET_COUNT_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_EXCESSIVE_DEFERRAL_ERROR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_OFFSET)
+#define S32K3XX_EMAC_TX_PAUSE_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_PAUSE_PACKETS_OFFSET)
+#define S32K3XX_EMAC_TX_VLAN_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_VLAN_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_TX_OSIZE_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_TX_OSIZE_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_PACKETS_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_PACKETS_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_OCTET_COUNT_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OCTET_COUNT_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_BROADCAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_BROADCAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_MULTICAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_MULTICAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_CRC_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_CRC_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_ALIGNMENT_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_ALIGNMENT_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_RUNT_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_RUNT_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_JABBER_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_JABBER_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_UNDERSIZE_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_UNDERSIZE_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_OVERSIZE_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OVERSIZE_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_64OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_UNICAST_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_UNICAST_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_RX_LENGTH_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_LENGTH_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_PAUSE_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_PAUSE_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_FIFO_OVERFLOW_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_FIFO_OVERFLOW_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_VLAN_PACKETS_GOOD_BAD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_VLAN_PACKETS_GOOD_BAD_OFFSET)
+#define S32K3XX_EMAC_RX_WATCHDOG_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_WATCHDOG_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_RECEIVE_ERROR_PACKETS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_RECEIVE_ERROR_PACKETS_OFFSET)
+#define S32K3XX_EMAC_RX_CONTROL_PACKETS_GOOD (S32K3XX_EMAC_BASE + S32K3XX_EMAC_RX_CONTROL_PACKETS_GOOD_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_TX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_FPE_FRAGMENT_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_FPE_FRAGMENT_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_TX_HOLD_REQ_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_TX_HOLD_REQ_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_OFFSET)
+#define S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_MASK (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_FPE_RX_INTERRUPT_MASK_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_PACKET_SMD_ERR_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_OFFSET)
+#define S32K3XX_EMAC_MMC_RX_FPE_FRAGMENT_CNTR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MMC_RX_FPE_FRAGMENT_CNTR_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG0_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG1 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG1_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG2 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG2_OFFSET)
+#define S32K3XX_EMAC_MAC_L3_L4_CONTROL3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_L3_L4_CONTROL3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER4_ADDRESS3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER4_ADDRESS3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR0_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR1_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR2_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG3 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_LAYER3_ADDR3_REG3_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MAC_SUB_SECOND_INCREMENT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SUB_SECOND_INCREMENT_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_ADDEND (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_ADDEND_OFFSET)
+#define S32K3XX_EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_STATUS_OFFSET)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_LATENCY (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_OFFSET)
+#define S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_LATENCY (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS0_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS0_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS1_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS1_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS2_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS2_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_SECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_SECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_INTERVAL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_INTERVAL_OFFSET)
+#define S32K3XX_EMAC_MAC_PPS3_WIDTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MAC_PPS3_WIDTH_OFFSET)
+#define S32K3XX_EMAC_MTL_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_DBG_CTL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_DBG_CTL_OFFSET)
+#define S32K3XX_EMAC_MTL_DBG_STS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_DBG_STS_OFFSET)
+#define S32K3XX_EMAC_MTL_FIFO_DEBUG_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_FIFO_DEBUG_DATA_OFFSET)
+#define S32K3XX_EMAC_MTL_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ_DMA_MAP0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ_DMA_MAP0_OFFSET)
+#define S32K3XX_EMAC_MTL_TBS_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TBS_CTRL_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_SCH_ERROR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_SCH_ERROR_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_ERROR (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_FRM_SIZE_ERROR_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_FRM_SIZE_CAPTURE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_FRM_SIZE_CAPTURE_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_INTR_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_INTR_ENABLE_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_GCL_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_GCL_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_EST_GCL_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_EST_GCL_DATA_OFFSET)
+#define S32K3XX_EMAC_MTL_FPE_CTRL_STS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_FPE_CTRL_STS_OFFSET)
+#define S32K3XX_EMAC_MTL_FPE_ADVANCE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_FPE_ADVANCE_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_INTERRUPT_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_DROP_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_DROP_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_ERROR_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_ERROR_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_DATA (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXP_INDIRECT_ACC_DATA_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_SAFETY_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_SAFETY_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_ERR_STS_RCTL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_ERR_STS_RCTL_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_ERR_ADDR_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_ERR_ADDR_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_ECC_ERR_CNTR_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_ECC_ERR_CNTR_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_DPP_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_DPP_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_UNDERFLOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_UNDERFLOW_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_ETS_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_ETS_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ0_QUANTUM_WEIGHT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ0_QUANTUM_WEIGHT_OFFSET)
+#define S32K3XX_EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_Q0_INTERRUPT_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ0_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ0_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_UNDERFLOW (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_UNDERFLOW_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_ETS_CONTROL_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_ETS_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_ETS_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_QUANTUM_WEIGHT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_QUANTUM_WEIGHT_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_SENDSLOPECREDIT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_SENDSLOPECREDIT_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_HICREDIT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_HICREDIT_OFFSET)
+#define S32K3XX_EMAC_MTL_TXQ1_LOCREDIT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_TXQ1_LOCREDIT_OFFSET)
+#define S32K3XX_EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_Q1_INTERRUPT_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_OPERATION_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_OPERATION_MODE_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_DEBUG (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_DEBUG_OFFSET)
+#define S32K3XX_EMAC_MTL_RXQ1_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_MTL_RXQ1_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_MODE_OFFSET)
+#define S32K3XX_EMAC_DMA_SYSBUS_MODE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_SYSBUS_MODE_OFFSET)
+#define S32K3XX_EMAC_DMA_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_DEBUG_STATUS0 (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_DEBUG_STATUS0_OFFSET)
+#define S32K3XX_EMAC_DMA_TBS_CTRL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_TBS_CTRL_OFFSET)
+#define S32K3XX_EMAC_DMA_SAFETY_INTERRUPT_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_SAFETY_INTERRUPT_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_TXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_TXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_MISS_FRAME_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_MISS_FRAME_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RXP_ACCEPT_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RXP_ACCEPT_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH0_RX_ERI_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH0_RX_ERI_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RX_CONTROL (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RX_CONTROL_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_LIST_ADDRESS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_TAIL_POINTER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXDESC_TAIL_POINTER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_TXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_TXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXDESC_RING_LENGTH (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXDESC_RING_LENGTH_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_INTERRUPT_ENABLE (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_INTERRUPT_ENABLE_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXDESC (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXDESC_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXBUFFER (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_STATUS (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_STATUS_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_MISS_FRAME_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_MISS_FRAME_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RXP_ACCEPT_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RXP_ACCEPT_CNT_OFFSET)
+#define S32K3XX_EMAC_DMA_CH1_RX_ERI_CNT (S32K3XX_EMAC_BASE + S32K3XX_EMAC_DMA_CH1_RX_ERI_CNT_OFFSET)
+
+/* MAC Configuration (MAC_CONFIGURATION) */
+#define EMAC_MAC_CONFIGURATION_RE (1 << 0) /* Bit 0: Receiver Enable */
+#define EMAC_MAC_CONFIGURATION_TE (1 << 1) /* Bit 1: Transmitter Enable */
+#define EMAC_MAC_CONFIGURATION_PRELEN_SHIFT (2) /* Bits 2-4: Preamble Length for Transmit Packets */
+#define EMAC_MAC_CONFIGURATION_PRELEN_MASK (0x3 << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT)
+#define EMAC_MAC_CONFIGURATION_PRELEN(n) ((n << EMAC_MAC_CONFIGURATION_PRELEN_SHIFT) & EMAC_MAC_CONFIGURATION_PRELEN_MASK)
+#define EMAC_MAC_CONFIGURATION_DC (1 << 4) /* Bit 4: Deferral Check */
+#define EMAC_MAC_CONFIGURATION_BL_SHIFT (5) /* Bits 5-7: Back-Off Limit */
+#define EMAC_MAC_CONFIGURATION_BL_MASK (0x3 << EMAC_MAC_CONFIGURATION_BL_SHIFT)
+#define EMAC_MAC_CONFIGURATION_BL(n) ((n << EMAC_MAC_CONFIGURATION_BL_SHIFT) & EMAC_MAC_CONFIGURATION_BL_MASK)
+#define EMAC_MAC_CONFIGURATION_DR (1 << 8) /* Bit 8: Disable Retry */
+#define EMAC_MAC_CONFIGURATION_DCRS (1 << 9) /* Bit 9: Disable Carrier Sense During Transmission */
+#define EMAC_MAC_CONFIGURATION_DO (1 << 10) /* Bit 10: Disable Receive Own */
+#define EMAC_MAC_CONFIGURATION_ECRSFD (1 << 11) /* Bit 11: Enable Carrier Sense In Full-Duplex Mode */
+#define EMAC_MAC_CONFIGURATION_LM (1 << 12) /* Bit 12: Loopback Mode */
+#define EMAC_MAC_CONFIGURATION_DM (1 << 13) /* Bit 13: Duplex Mode */
+#define EMAC_MAC_CONFIGURATION_FES (1 << 14) /* Bit 14: Speed */
+#define EMAC_MAC_CONFIGURATION_PS (1 << 15) /* Bit 15: Port Select */
+#define EMAC_MAC_CONFIGURATION_JE (1 << 16) /* Bit 16: Jumbo Packet Enable */
+#define EMAC_MAC_CONFIGURATION_JD (1 << 17) /* Bit 17: Jabber Disable */
+#define EMAC_MAC_CONFIGURATION_WD (1 << 19) /* Bit 19: Watchdog Disable */
+#define EMAC_MAC_CONFIGURATION_ACS (1 << 20) /* Bit 20: Automatic Pad Or CRC Stripping */
+#define EMAC_MAC_CONFIGURATION_CST (1 << 21) /* Bit 21: CRC Stripping For Type Packets */
+#define EMAC_MAC_CONFIGURATION_S2KP (1 << 22) /* Bit 22: IEEE 802.3 Support For 2K Packets */
+#define EMAC_MAC_CONFIGURATION_GPSLCE (1 << 23) /* Bit 23: Giant Packet Size Limit Control Enable */
+#define EMAC_MAC_CONFIGURATION_IPG_SHIFT (24) /* Bits 24-27: Inter-Packet Gap */
+#define EMAC_MAC_CONFIGURATION_IPG_MASK (0x7 << EMAC_MAC_CONFIGURATION_IPG_SHIFT)
+#define EMAC_MAC_CONFIGURATION_IPG(n) ((n << EMAC_MAC_CONFIGURATION_IPG_SHIFT) & EMAC_MAC_CONFIGURATION_IPG_MASK)
+#define EMAC_MAC_CONFIGURATION_IPC (1 << 27) /* Bit 27: Checksum Offload */
+#define EMAC_MAC_CONFIGURATION_SARC_SHIFT (28) /* Bits 28-31: Source Address Insertion Or Replacement Control */
+#define EMAC_MAC_CONFIGURATION_SARC_MASK (0x7 << EMAC_MAC_CONFIGURATION_SARC_SHIFT)
+#define EMAC_MAC_CONFIGURATION_SARC(n) ((n << EMAC_MAC_CONFIGURATION_SARC_SHIFT) & EMAC_MAC_CONFIGURATION_SARC_MASK)
+
+/* MAC Extended Configuration (MAC_EXT_CONFIGURATION) */
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0) /* Bits 0-14: Giant Packet Size Limit */
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFF << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT)
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) ((n << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK)
+#define EMAC_MAC_EXT_CONFIGURATION_DCRCC (1 << 16) /* Bit 16: Disable CRC Checking For Received Packets */
+#define EMAC_MAC_EXT_CONFIGURATION_SPEN (1 << 17) /* Bit 17: Slow Protocol Detection Enable */
+#define EMAC_MAC_EXT_CONFIGURATION_USP (1 << 18) /* Bit 18: Unicast Slow Protocol Packet Detect */
+#define EMAC_MAC_EXT_CONFIGURATION_PDC (1 << 19) /* Bit 19: Packet Duplication Control */
+#define EMAC_MAC_EXT_CONFIGURATION_EIPGEN (1 << 24) /* Bit 24: Extended Inter-Packet Gap Enable */
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25) /* Bits 25-30: Extended Inter-Packet Gap */
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1F << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT)
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) ((n << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK)
+
+/* MAC Packet Filter (MAC_PACKET_FILTER) */
+#define EMAC_MAC_PACKET_FILTER_PR (1 << 0) /* Bit 0: Promiscuous Mode */
+#define EMAC_MAC_PACKET_FILTER_HUC (1 << 1) /* Bit 1: Hash Unicast */
+#define EMAC_MAC_PACKET_FILTER_HMC (1 << 2) /* Bit 2: Hash Multicast */
+#define EMAC_MAC_PACKET_FILTER_DAIF (1 << 3) /* Bit 3: DA Inverse Filtering */
+#define EMAC_MAC_PACKET_FILTER_PM (1 << 4) /* Bit 4: Pass All Multicast */
+#define EMAC_MAC_PACKET_FILTER_DBF (1 << 5) /* Bit 5: Disable Broadcast Packets */
+#define EMAC_MAC_PACKET_FILTER_PCF_SHIFT (6) /* Bits 6-8: Pass Control Packets */
+#define EMAC_MAC_PACKET_FILTER_PCF_MASK (0x3 << EMAC_MAC_PACKET_FILTER_PCF_SHIFT)
+#define EMAC_MAC_PACKET_FILTER_PCF(n) ((n << EMAC_MAC_PACKET_FILTER_PCF_SHIFT) & EMAC_MAC_PACKET_FILTER_PCF_MASK)
+#define EMAC_MAC_PACKET_FILTER_SAIF (1 << 8) /* Bit 8: SA Inverse Filtering */
+#define EMAC_MAC_PACKET_FILTER_SAF (1 << 9) /* Bit 9: Source Address Filter Enable */
+#define EMAC_MAC_PACKET_FILTER_HPF (1 << 10) /* Bit 10: Hash Or Perfect Filter */
+#define EMAC_MAC_PACKET_FILTER_VTFE (1 << 16) /* Bit 16: VLAN Tag Filter Enable */
+#define EMAC_MAC_PACKET_FILTER_IPFE (1 << 20) /* Bit 20: Layer 3 and Layer 4 Filter Enable */
+#define EMAC_MAC_PACKET_FILTER_DNTU (1 << 21) /* Bit 21: Drop Non-TCP/UDP Over IP Packets */
+#define EMAC_MAC_PACKET_FILTER_RA (1 << 31) /* Bit 31: Receive All */
+
+/* MAC Watchdog Timeout (MAC_WATCHDOG_TIMEOUT) */
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0) /* Bits 0-4: Watchdog Timeout */
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xF << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) ((n << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
+#define EMAC_MAC_WATCHDOG_TIMEOUT_PWE (1 << 8) /* Bit 8: Programmable Watchdog Enable */
+
+/* MAC Hash Table First 32 Bits (MAC_HASH_TABLE_REG0) */
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0) /* Bits 0-32: MAC Hash Table First 32 Bits */
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) ((n << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK)
+
+/* MAC Hash Table Second 32 Bits (MAC_HASH_TABLE_REG1) */
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0) /* Bits 0-32: MAC Hash Table Second 32 Bits */
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) ((n << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK)
+
+/* MAC VLAN Tag (MAC_VLAN_TAG) */
+#define EMAC_MAC_VLAN_TAG_VL_SHIFT (0) /* Bits 0-16: VLAN Tag Identifier for Receive Packets */
+#define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_VL_SHIFT)
+#define EMAC_MAC_VLAN_TAG_VL(n) ((n << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK)
+#define EMAC_MAC_VLAN_TAG_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */
+#define EMAC_MAC_VLAN_TAG_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */
+#define EMAC_MAC_VLAN_TAG_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */
+#define EMAC_MAC_VLAN_TAG_ERSVLM (1 << 19) /* Bit 19: Enable Receive S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */
+#define EMAC_MAC_VLAN_TAG_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */
+#define EMAC_MAC_VLAN_TAG_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EVLS_SHIFT)
+#define EMAC_MAC_VLAN_TAG_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_EVLRXS (1 << 24) /* Bit 24: Enable VLAN Tag In Receive Status */
+#define EMAC_MAC_VLAN_TAG_VTHM (1 << 25) /* Bit 25: VLAN Tag Hash Table Match */
+#define EMAC_MAC_VLAN_TAG_EDVLP (1 << 26) /* Bit 26: Enable Double VLAN Processing */
+#define EMAC_MAC_VLAN_TAG_ERIVLT (1 << 27) /* Bit 27: Enable Inner VLAN Tag Comparison */
+#define EMAC_MAC_VLAN_TAG_EIVLS_SHIFT (28) /* Bits 28-30: Enable Inner VLAN Tag Stripping */
+#define EMAC_MAC_VLAN_TAG_EIVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT)
+#define EMAC_MAC_VLAN_TAG_EIVLS(n) ((n << EMAC_MAC_VLAN_TAG_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_EIVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_EIVLRXS (1 << 31) /* Bit 31: Enable Inner VLAN Tag In Receive Status */
+
+/* MAC VLAN Tag Control (MAC_VLAN_TAG_CTRL) */
+#define EMAC_MAC_VLAN_TAG_CTRL_OB (1 << 0) /* Bit 0: Operation Busy */
+#define EMAC_MAC_VLAN_TAG_CTRL_CT (1 << 1) /* Bit 1: Command Type */
+#define EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2) /* Bits 2-4: Offset */
+#define EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT)
+#define EMAC_MAC_VLAN_TAG_CTRL_OFS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_OFS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_OFS_MASK)
+#define EMAC_MAC_VLAN_TAG_CTRL_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */
+#define EMAC_MAC_VLAN_TAG_CTRL_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */
+#define EMAC_MAC_VLAN_TAG_CTRL_ESVL (1 << 18) /* Bit 18: Enable S-VLAN */
+#define EMAC_MAC_VLAN_TAG_CTRL_ERSVLM (1 << 19) /* Bit 19: Enable Receive S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_CTRL_DOVLTC (1 << 20) /* Bit 20: Disable VLAN Type Check */
+#define EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21) /* Bits 21-23: Enable VLAN Tag Stripping */
+#define EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)
+#define EMAC_MAC_VLAN_TAG_CTRL_EVLS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_EVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_CTRL_EVLRXS (1 << 24) /* Bit 24: Enable VLAN Tag In Receive Status */
+#define EMAC_MAC_VLAN_TAG_CTRL_VTHM (1 << 25) /* Bit 25: VLAN Tag Hash Table Match */
+#define EMAC_MAC_VLAN_TAG_CTRL_EDVLP (1 << 26) /* Bit 26: Enable Double VLAN Processing */
+#define EMAC_MAC_VLAN_TAG_CTRL_ERIVLT (1 << 27) /* Bit 27: Enable Inner VLAN Tag Comparison */
+#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28) /* Bits 28-30: Enable Inner VLAN Tag Stripping */
+#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x3 << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)
+#define EMAC_MAC_VLAN_TAG_CTRL_EIVLS(n) ((n << EMAC_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT) & EMAC_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
+#define EMAC_MAC_VLAN_TAG_CTRL_EIVLRXS (1 << 31) /* Bit 31: Enable Inner VLAN Tag In Receive Status */
+
+/* MAC VLAN Tag Data (MAC_VLAN_TAG_DATA) */
+#define EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
+#define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_DATA_VID(n) ((n << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_DATA_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
+#define EMAC_MAC_VLAN_TAG_DATA_ETV (1 << 17) /* Bit 17: VLAN Comparison */
+#define EMAC_MAC_VLAN_TAG_DATA_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
+#define EMAC_MAC_VLAN_TAG_DATA_ERSVLM (1 << 19) /* Bit 19: Enable S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_DATA_ERIVLT (1 << 20) /* Bit 20: Enable Inner VLAN Tag */
+#define EMAC_MAC_VLAN_TAG_DATA_DMACHEN (1 << 24) /* Bit 24: DMA Channel Number Enable */
+#define EMAC_MAC_VLAN_TAG_DATA_DMACHN (1 << 25) /* Bit 25: DMA Channel Number */
+
+/* MAC VLAN Tag Filter 0 (MAC_VLAN_TAG_FILTER0) */
+#define EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
+#define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER0_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER0_ETV (1 << 17) /* Bit 17: VLAN Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER0_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER0_ERSVLM (1 << 19) /* Bit 19: Enable S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_FILTER0_ERIVLT (1 << 20) /* Bit 20: Enable Inner VLAN Tag */
+#define EMAC_MAC_VLAN_TAG_FILTER0_DMACHEN (1 << 24) /* Bit 24: DMA Channel Number Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER0_DMACHN (1 << 25) /* Bit 25: DMA Channel Number */
+
+/* MAC VLAN Tag Filter 1 (MAC_VLAN_TAG_FILTER1) */
+#define EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
+#define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER1_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER1_ETV (1 << 17) /* Bit 17: VLAN Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER1_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER1_ERSVLM (1 << 19) /* Bit 19: Enable S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_FILTER1_ERIVLT (1 << 20) /* Bit 20: Enable Inner VLAN Tag */
+#define EMAC_MAC_VLAN_TAG_FILTER1_DMACHEN (1 << 24) /* Bit 24: DMA Channel Number Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER1_DMACHN (1 << 25) /* Bit 25: DMA Channel Number */
+
+/* MAC VLAN Tag Filter 2 (MAC_VLAN_TAG_FILTER2) */
+#define EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
+#define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER2_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER2_ETV (1 << 17) /* Bit 17: VLAN Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER2_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER2_ERSVLM (1 << 19) /* Bit 19: Enable S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_FILTER2_ERIVLT (1 << 20) /* Bit 20: Enable Inner VLAN Tag */
+#define EMAC_MAC_VLAN_TAG_FILTER2_DMACHEN (1 << 24) /* Bit 24: DMA Channel Number Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER2_DMACHN (1 << 25) /* Bit 25: DMA Channel Number */
+
+/* MAC VLAN Tag Filter 3 (MAC_VLAN_TAG_FILTER3) */
+#define EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
+#define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) ((n << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK)
+#define EMAC_MAC_VLAN_TAG_FILTER3_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER3_ETV (1 << 17) /* Bit 17: VLAN Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER3_DOVLTC (1 << 18) /* Bit 18: Disable VLAN Type Comparison */
+#define EMAC_MAC_VLAN_TAG_FILTER3_ERSVLM (1 << 19) /* Bit 19: Enable S-VLAN Match */
+#define EMAC_MAC_VLAN_TAG_FILTER3_ERIVLT (1 << 20) /* Bit 20: Enable Inner VLAN Tag */
+#define EMAC_MAC_VLAN_TAG_FILTER3_DMACHEN (1 << 24) /* Bit 24: DMA Channel Number Enable */
+#define EMAC_MAC_VLAN_TAG_FILTER3_DMACHN (1 << 25) /* Bit 25: DMA Channel Number */
+
+/* MAC VLAN Hash Table (MAC_VLAN_HASH_TABLE) */
+#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0) /* Bits 0-16: VLAN Hash Table */
+#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFF << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)
+#define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) ((n << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK)
+
+/* MAC VLAN Inclusion Or Replacement (MAC_VLAN_INCL) */
+#define EMAC_MAC_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */
+#define EMAC_MAC_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_VLAN_INCL_VLT_SHIFT)
+#define EMAC_MAC_VLAN_INCL_VLT(n) ((n << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK)
+#define EMAC_MAC_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control */
+#define EMAC_MAC_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_VLAN_INCL_VLC_SHIFT)
+#define EMAC_MAC_VLAN_INCL_VLC(n) ((n << EMAC_MAC_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_VLAN_INCL_VLC_MASK)
+#define EMAC_MAC_VLAN_INCL_VLP (1 << 18) /* Bit 18: VLAN Priority Control */
+#define EMAC_MAC_VLAN_INCL_CSVL (1 << 19) /* Bit 19: C-VLAN Or S-VLAN */
+#define EMAC_MAC_VLAN_INCL_VLTI (1 << 20) /* Bit 20: VLAN Tag Input */
+#define EMAC_MAC_VLAN_INCL_CBTI (1 << 21) /* Bit 21: Channel-Based Tag Insertion */
+#define EMAC_MAC_VLAN_INCL_ADDR (1 << 24) /* Bit 24: Address */
+#define EMAC_MAC_VLAN_INCL_RDWR (1 << 30) /* Bit 30: Read Write Control */
+#define EMAC_MAC_VLAN_INCL_BUSY (1 << 31) /* Bit 31: Busy */
+
+/* Inner VLAN Tag Inclusion Or Replacement (MAC_INNER_VLAN_INCL) */
+#define EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */
+#define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT)
+#define EMAC_MAC_INNER_VLAN_INCL_VLT(n) ((n << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK)
+#define EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control in Transmit Packets */
+#define EMAC_MAC_INNER_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT)
+#define EMAC_MAC_INNER_VLAN_INCL_VLC(n) ((n << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLC_MASK)
+#define EMAC_MAC_INNER_VLAN_INCL_VLP (1 << 18) /* Bit 18: VLAN Priority Control */
+#define EMAC_MAC_INNER_VLAN_INCL_CSVL (1 << 19) /* Bit 19: C-VLAN Or S-VLAN */
+#define EMAC_MAC_INNER_VLAN_INCL_VLTI (1 << 20) /* Bit 20: VLAN Tag Input */
+
+/* MAC Q0 Tx Flow Control (MAC_Q0_TX_FLOW_CTRL) */
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_FCB_BPA (1 << 0) /* Bit 0: Flow Control Busy Or Backpressure Activate */
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_TFE (1 << 1) /* Bit 1: Transmit Flow Control Enable */
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT (4) /* Bits 4-7: Pause Low Threshold */
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK (0x7 << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT)
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) ((n << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK)
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ (1 << 7) /* Bit 7: Disable Zero-Quanta Pause */
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16) /* Bits 16-32: Pause Time */
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT)
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) ((n << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK)
+
+/* MAC Receive Flow Control (MAC_RX_FLOW_CTRL) */
+#define EMAC_MAC_RX_FLOW_CTRL_RFE (1 << 0) /* Bit 0: Receive Flow Control Enable */
+#define EMAC_MAC_RX_FLOW_CTRL_UP (1 << 1) /* Bit 1: Unicast Pause Packet Detect */
+
+/* MAC RxQ Control 4 (MAC_RXQ_CTRL4) */
+#define EMAC_MAC_RXQ_CTRL4_UFFQE (1 << 0) /* Bit 0: Unicast Address Filter Fail Packets Queuing Enable */
+#define EMAC_MAC_RXQ_CTRL4_UFFQ (1 << 1) /* Bit 1: Unicast Address Filter Fail Packets Queue */
+#define EMAC_MAC_RXQ_CTRL4_MFFQE (1 << 8) /* Bit 8: Multicast Address Filter Fail Packets Queuing Enable */
+#define EMAC_MAC_RXQ_CTRL4_MFFQ (1 << 9) /* Bit 9: Multicast Address Filter Fail Packets Queue */
+#define EMAC_MAC_RXQ_CTRL4_VFFQE (1 << 16) /* Bit 16: VLAN Tag Filter Fail Packets Queuing Enable */
+#define EMAC_MAC_RXQ_CTRL4_VFFQ (1 << 17) /* Bit 17: VLAN Tag Filter Fail Packets Queue */
+
+/* MAC RxQ Control 0 (MAC_RXQ_CTRL0) */
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT (0) /* Bits 0-2: Receive Queue 0 Enable */
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK (0x3 << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT)
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN(n) ((n << EMAC_MAC_RXQ_CTRL0_RXQ0EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ0EN_MASK)
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_DISABLE EMAC_MAC_RXQ_CTRL0_RXQ0EN(0)
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_AVB EMAC_MAC_RXQ_CTRL0_RXQ0EN(0x1)
+#define EMAC_MAC_RXQ_CTRL0_RXQ0EN_DCB_GEN EMAC_MAC_RXQ_CTRL0_RXQ0EN(0x2)
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT (2) /* Bits 2-4: Receive Queue 1 Enable */
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK (0x3 << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT)
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN(n) ((n << EMAC_MAC_RXQ_CTRL0_RXQ1EN_SHIFT) & EMAC_MAC_RXQ_CTRL0_RXQ1EN_MASK)
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_DISABLE EMAC_MAC_RXQ_CTRL0_RXQ1EN(0)
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_AVB EMAC_MAC_RXQ_CTRL0_RXQ1EN(0x1)
+#define EMAC_MAC_RXQ_CTRL0_RXQ1EN_DCB_GEN EMAC_MAC_RXQ_CTRL0_RXQ1EN(0x2)
+
+/* Receive Queue Control 1 (MAC_RXQ_CTRL1) */
+#define EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT (0) /* Bits 0-3: AV Untagged Control Packets Queue */
+#define EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT)
+#define EMAC_MAC_RXQ_CTRL1_AVCPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_AVCPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_AVCPQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT (4) /* Bits 4-7: PTP Packets Queue */
+#define EMAC_MAC_RXQ_CTRL1_PTPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT)
+#define EMAC_MAC_RXQ_CTRL1_PTPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_PTPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_PTPQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT (12) /* Bits 12-15: Untagged Packet Queue */
+#define EMAC_MAC_RXQ_CTRL1_UPQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT)
+#define EMAC_MAC_RXQ_CTRL1_UPQ(n) ((n << EMAC_MAC_RXQ_CTRL1_UPQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_UPQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT (16) /* Bits 16-19: Multicast And Broadcast Queue */
+#define EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT)
+#define EMAC_MAC_RXQ_CTRL1_MCBCQ(n) ((n << EMAC_MAC_RXQ_CTRL1_MCBCQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_MCBCQ_MASK)
+#define EMAC_MAC_RXQ_CTRL1_MCBCQEN (1 << 20) /* Bit 20: Multicast And Broadcast Queue Enable */
+#define EMAC_MAC_RXQ_CTRL1_TACPQE (1 << 21) /* Bit 21: Tagged AV Control Packets Queuing Enable */
+#define EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT (22) /* Bits 22-24: Tagged PTP Over Ethernet Packets Queuing Control */
+#define EMAC_MAC_RXQ_CTRL1_TPQC_MASK (0x3 << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT)
+#define EMAC_MAC_RXQ_CTRL1_TPQC(n) ((n << EMAC_MAC_RXQ_CTRL1_TPQC_SHIFT) & EMAC_MAC_RXQ_CTRL1_TPQC_MASK)
+#define EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT (24) /* Bits 24-27: Frame Preemption Residue Queue */
+#define EMAC_MAC_RXQ_CTRL1_FPRQ_MASK (0x7 << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT)
+#define EMAC_MAC_RXQ_CTRL1_FPRQ(n) ((n << EMAC_MAC_RXQ_CTRL1_FPRQ_SHIFT) & EMAC_MAC_RXQ_CTRL1_FPRQ_MASK)
+
+/* MAC RxQ Control 2 (MAC_RXQ_CTRL2) */
+#define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0) /* Bits 0-8: Priorities Selected In Receive Queue 0 */
+#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) ((n << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8) /* Bits 8-16: Priorities Selected In Receive Queue 1 */
+#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) ((n << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK)
+
+/* MAC Interrupt Status (MAC_INTERRUPT_STATUS) */
+#define EMAC_MAC_INTERRUPT_STATUS_PHYIS (1 << 3) /* Bit 3: PHY Interrupt */
+#define EMAC_MAC_INTERRUPT_STATUS_MMCIS (1 << 8) /* Bit 8: MMC Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_MMCRXIS (1 << 9) /* Bit 9: MMC Receive Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_MMCTXIS (1 << 10) /* Bit 10: MMC Transmit Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_TSIS (1 << 12) /* Bit 12: Timestamp Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_TXSTSIS (1 << 13) /* Bit 13: Transmit Status Interrupt */
+#define EMAC_MAC_INTERRUPT_STATUS_RXSTSIS (1 << 14) /* Bit 14: Receive Status Interrupt */
+#define EMAC_MAC_INTERRUPT_STATUS_FPEIS (1 << 17) /* Bit 17: Frame Preemption Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_MDIOIS (1 << 18) /* Bit 18: MDIO Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_MFTIS (1 << 19) /* Bit 19: MMC FPE Transmit Interrupt Status */
+#define EMAC_MAC_INTERRUPT_STATUS_MFRIS (1 << 20) /* Bit 20: MMC FPE Receive Interrupt Status */
+
+/* MAC Interrupt Enable (MAC_INTERRUPT_ENABLE) */
+#define EMAC_MAC_INTERRUPT_ENABLE_PHYIE (1 << 3) /* Bit 3: PHY Interrupt Enable */
+#define EMAC_MAC_INTERRUPT_ENABLE_TSIE (1 << 12) /* Bit 12: Timestamp Interrupt Enable */
+#define EMAC_MAC_INTERRUPT_ENABLE_TXSTSIE (1 << 13) /* Bit 13: Transmit Status Interrupt Enable */
+#define EMAC_MAC_INTERRUPT_ENABLE_RXSTSIE (1 << 14) /* Bit 14: Receive Status Interrupt Enable */
+#define EMAC_MAC_INTERRUPT_ENABLE_FPEIE (1 << 17) /* Bit 17: Frame Preemption Interrupt Enable */
+#define EMAC_MAC_INTERRUPT_ENABLE_MDIOIE (1 << 18) /* Bit 18: MDIO Interrupt Enable */
+
+/* MAC Rx Transmit Status (MAC_RX_TX_STATUS) */
+#define EMAC_MAC_RX_TX_STATUS_TJT (1 << 0) /* Bit 0: Transmit Jabber Timeout */
+#define EMAC_MAC_RX_TX_STATUS_NCARR (1 << 1) /* Bit 1: No Carrier */
+#define EMAC_MAC_RX_TX_STATUS_LCARR (1 << 2) /* Bit 2: Loss of Carrier */
+#define EMAC_MAC_RX_TX_STATUS_EXDEF (1 << 3) /* Bit 3: Excessive Deferral */
+#define EMAC_MAC_RX_TX_STATUS_LCOL (1 << 4) /* Bit 4: Late Collision */
+#define EMAC_MAC_RX_TX_STATUS_EXCOL (1 << 5) /* Bit 5: Excessive Collisions */
+#define EMAC_MAC_RX_TX_STATUS_RWT (1 << 8) /* Bit 8: Receive Watchdog Timeout */
+
+/* MAC Version (MAC_VERSION) */
+#define EMAC_MAC_VERSION_IPVER_SHIFT (0) /* Bits 0-8: IP Version */
+#define EMAC_MAC_VERSION_IPVER_MASK (0xFF << EMAC_MAC_VERSION_IPVER_SHIFT)
+#define EMAC_MAC_VERSION_IPVER(n) ((n << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK)
+#define EMAC_MAC_VERSION_CFGVER_SHIFT (8) /* Bits 8-16: IP Configuration Version */
+#define EMAC_MAC_VERSION_CFGVER_MASK (0xFF << EMAC_MAC_VERSION_CFGVER_SHIFT)
+#define EMAC_MAC_VERSION_CFGVER(n) ((n << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK)
+
+/* MAC Debug (MAC_DEBUG) */
+#define EMAC_MAC_DEBUG_RPESTS (1 << 0) /* Bit 0: Receive Protocol Engine Status */
+#define EMAC_MAC_DEBUG_RFCFCSTS_SHIFT (1) /* Bits 1-3: MAC Receive Packet Controller FIFO Status */
+#define EMAC_MAC_DEBUG_RFCFCSTS_MASK (0x3 << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT)
+#define EMAC_MAC_DEBUG_RFCFCSTS(n) ((n << EMAC_MAC_DEBUG_RFCFCSTS_SHIFT) & EMAC_MAC_DEBUG_RFCFCSTS_MASK)
+#define EMAC_MAC_DEBUG_TPESTS (1 << 16) /* Bit 16: MAC GMII Or MII Transmit Protocol Engine Status */
+#define EMAC_MAC_DEBUG_TFCSTS_SHIFT (17) /* Bits 17-19: MAC Transmit Packet Controller Status */
+#define EMAC_MAC_DEBUG_TFCSTS_MASK (0x3 << EMAC_MAC_DEBUG_TFCSTS_SHIFT)
+#define EMAC_MAC_DEBUG_TFCSTS(n) ((n << EMAC_MAC_DEBUG_TFCSTS_SHIFT) & EMAC_MAC_DEBUG_TFCSTS_MASK)
+
+/* MAC Hardware Feature 0 (MAC_HW_FEATURE0) */
+#define EMAC_MAC_HW_FEATURE0_MIISEL (1 << 0) /* Bit 0: 10 or 100 Mbit/s Support Feature */
+#define EMAC_MAC_HW_FEATURE0_GMIISEL (1 << 1) /* Bit 1: 1000 Mbit/s Support Feature */
+#define EMAC_MAC_HW_FEATURE0_HDSEL (1 << 2) /* Bit 2: Half-Duplex Support Feature */
+#define EMAC_MAC_HW_FEATURE0_PCSSEL (1 << 3) /* Bit 3: PCS Select */
+#define EMAC_MAC_HW_FEATURE0_VLHASH (1 << 4) /* Bit 4: VLAN Hash Filter Feature */
+#define EMAC_MAC_HW_FEATURE0_SMASEL (1 << 5) /* Bit 5: SMA (MDIO) Interface Feature */
+#define EMAC_MAC_HW_FEATURE0_RWKSEL (1 << 6) /* Bit 6: PMT Remote Wake-Up Packet Feature */
+#define EMAC_MAC_HW_FEATURE0_MGKSEL (1 << 7) /* Bit 7: PMT Magic Packet Feature */
+#define EMAC_MAC_HW_FEATURE0_MMCSEL (1 << 8) /* Bit 8: MAC Management Counters (MMC) Feature */
+#define EMAC_MAC_HW_FEATURE0_ARPOFFSEL (1 << 9) /* Bit 9: ARP Offload Feature */
+#define EMAC_MAC_HW_FEATURE0_TSSEL (1 << 12) /* Bit 12: IEEE 1588-2008 Timestamp Feature */
+#define EMAC_MAC_HW_FEATURE0_EEESEL (1 << 13) /* Bit 13: Energy Efficient Ethernet (EEE) Feature */
+#define EMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14) /* Bit 14: Transmit Checksum Offload Feature */
+#define EMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) /* Bit 16: Receive Checksum Offload Feature */
+#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18) /* Bits 18-23: MAC Addresses 1-31 */
+#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1F << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT)
+#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) ((n << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK)
+#define EMAC_MAC_HW_FEATURE0_MACADR32SEL (1 << 23) /* Bit 23: MAC Addresses 32-63 */
+#define EMAC_MAC_HW_FEATURE0_MACADR64SEL (1 << 24) /* Bit 24: MAC Addresses 64-127 */
+#define EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT (25) /* Bits 25-27: Timestamp System Time Source Feature */
+#define EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK (0x3 << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT)
+#define EMAC_MAC_HW_FEATURE0_TSSTSSEL(n) ((n << EMAC_MAC_HW_FEATURE0_TSSTSSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_TSSTSSEL_MASK)
+#define EMAC_MAC_HW_FEATURE0_SAVLANINS (1 << 27) /* Bit 27: SA or VLAN Insertion Feature */
+#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT (28) /* Bits 28-31: Active PHY Feature */
+#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK (0x7 << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT)
+#define EMAC_MAC_HW_FEATURE0_ACTPHYSEL(n) ((n << EMAC_MAC_HW_FEATURE0_ACTPHYSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ACTPHYSEL_MASK)
+
+/* MAC Hardware Feature 1 (MAC_HW_FEATURE1) */
+#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0) /* Bits 0-5: MTL Receive FIFO Size Feature */
+#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) ((n << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK)
+#define EMAC_MAC_HW_FEATURE1_SPRAM (1 << 5) /* Bit 5: Single Port RAM Feature */
+#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6) /* Bits 6-11: MTL Transmit FIFO Size Feature */
+#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) ((n << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK)
+#define EMAC_MAC_HW_FEATURE1_OSTEN (1 << 11) /* Bit 11: One-Step Timestamping Enable Feature */
+#define EMAC_MAC_HW_FEATURE1_PTOEN (1 << 12) /* Bit 12: PTP Offload Enable Feature */
+#define EMAC_MAC_HW_FEATURE1_ADVTHWORD (1 << 13) /* Bit 13: IEEE 1588 High-Word Feature */
+#define EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT (14) /* Bits 14-16: Address Width Feature */
+#define EMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3 << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_ADDR64(n) ((n << EMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) & EMAC_MAC_HW_FEATURE1_ADDR64_MASK)
+#define EMAC_MAC_HW_FEATURE1_DCBEN (1 << 16) /* Bit 16: DCB Enable Feature */
+#define EMAC_MAC_HW_FEATURE1_SPHEN (1 << 17) /* Bit 17: Split Header Enable Feature */
+#define EMAC_MAC_HW_FEATURE1_TSOEN (1 << 18) /* Bit 18: TCP Segmentation Offload Enable Feature */
+#define EMAC_MAC_HW_FEATURE1_DBGMEMA (1 << 19) /* Bit 19: DMA Debug Registers Enable Feature */
+#define EMAC_MAC_HW_FEATURE1_AVSEL (1 << 20) /* Bit 20: AV Feature */
+#define EMAC_MAC_HW_FEATURE1_RAVSEL (1 << 21) /* Bit 21: Receive Side-Only AV Feature */
+#define EMAC_MAC_HW_FEATURE1_POUOST (1 << 23) /* Bit 23: One Step For PTP Over UDP/IP Feature */
+#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT (24) /* Bits 24-26: Hash Table Size */
+#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3 << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) ((n << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK)
+#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27) /* Bits 27-31: L3 Or L4 Filter Number */
+#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xF << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) ((n << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK)
+
+/* MAC Hardware Feature 2 (MAC_HW_FEATURE2) */
+#define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0) /* Bits 0-4: Number Of MTL Receive Queues */
+#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_RXQCNT(n) ((n << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6) /* Bits 6-10: Number Of MTL Transmit Queues */
+#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_TXQCNT(n) ((n << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12) /* Bits 12-16: Number Of DMA Receive Channels */
+#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) ((n << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18) /* Bits 18-22: Number Of DMA Transmit Channels */
+#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) ((n << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK)
+#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24) /* Bits 24-27: Number Of PPS Outputs */
+#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM(n) ((n << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK)
+#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT (28) /* Bits 28-31: Number Of Auxiliary Snapshot Inputs */
+#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_AUXSNAPNUM(n) ((n << EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_SHIFT) & EMAC_MAC_HW_FEATURE2_AUXSNAPNUM_MASK)
+
+/* MAC Hardware Feature 3 (MAC_HW_FEATURE3) */
+#define EMAC_MAC_HW_FEATURE3_NRVF_SHIFT (0) /* Bits 0-3: Number Of Extended VLAN Tag Filters Indicates the number of selected extended VLAN tag filters. */
+#define EMAC_MAC_HW_FEATURE3_NRVF_MASK (0x7 << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT)
+#define EMAC_MAC_HW_FEATURE3_NRVF(n) ((n << EMAC_MAC_HW_FEATURE3_NRVF_SHIFT) & EMAC_MAC_HW_FEATURE3_NRVF_MASK)
+#define EMAC_MAC_HW_FEATURE3_CBTISEL (1 << 4) /* Bit 4: Queue/Channel Based VLAN Tag Insertion On Transmit Feature */
+#define EMAC_MAC_HW_FEATURE3_DVLAN (1 << 5) /* Bit 5: Double VLAN Tag Processing Feature */
+#define EMAC_MAC_HW_FEATURE3_PDUPSEL (1 << 9) /* Bit 9: Broadcast/Multicast Packet Duplication Feature */
+#define EMAC_MAC_HW_FEATURE3_FRPSEL (1 << 10) /* Bit 10: Flexible Receive Parser Feature */
+#define EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT (11) /* Bits 11-13: Flexible Receive Parser Buffer Size */
+#define EMAC_MAC_HW_FEATURE3_FRPBS_MASK (0x3 << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT)
+#define EMAC_MAC_HW_FEATURE3_FRPBS(n) ((n << EMAC_MAC_HW_FEATURE3_FRPBS_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPBS_MASK)
+#define EMAC_MAC_HW_FEATURE3_FRPES_SHIFT (13) /* Bits 13-15: Flexible Receive Parser Table Entry Size */
+#define EMAC_MAC_HW_FEATURE3_FRPES_MASK (0x3 << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT)
+#define EMAC_MAC_HW_FEATURE3_FRPES(n) ((n << EMAC_MAC_HW_FEATURE3_FRPES_SHIFT) & EMAC_MAC_HW_FEATURE3_FRPES_MASK)
+#define EMAC_MAC_HW_FEATURE3_ESTSEL (1 << 16) /* Bit 16: Enhancements To Scheduling Traffic Feature */
+#define EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT (17) /* Bits 17-20: Depth Of Gate Control List */
+#define EMAC_MAC_HW_FEATURE3_ESTDEP_MASK (0x7 << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT)
+#define EMAC_MAC_HW_FEATURE3_ESTDEP(n) ((n << EMAC_MAC_HW_FEATURE3_ESTDEP_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTDEP_MASK)
+#define EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT (20) /* Bits 20-22: Estimated Time Interval Width */
+#define EMAC_MAC_HW_FEATURE3_ESTWID_MASK (0x3 << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT)
+#define EMAC_MAC_HW_FEATURE3_ESTWID(n) ((n << EMAC_MAC_HW_FEATURE3_ESTWID_SHIFT) & EMAC_MAC_HW_FEATURE3_ESTWID_MASK)
+#define EMAC_MAC_HW_FEATURE3_FPESEL (1 << 26) /* Bit 26: Frame Preemption Feature */
+#define EMAC_MAC_HW_FEATURE3_TBSSEL (1 << 27) /* Bit 27: Time-Based Scheduling Feature */
+#define EMAC_MAC_HW_FEATURE3_ASP_SHIFT (28) /* Bits 28-30: Automotive Safety Package */
+#define EMAC_MAC_HW_FEATURE3_ASP_MASK (0x3 << EMAC_MAC_HW_FEATURE3_ASP_SHIFT)
+#define EMAC_MAC_HW_FEATURE3_ASP(n) ((n << EMAC_MAC_HW_FEATURE3_ASP_SHIFT) & EMAC_MAC_HW_FEATURE3_ASP_MASK)
+
+/* MAC DPP FSM Interrupt Status (MAC_DPP_FSM_INTERRUPT_STATUS) */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RDPES (1 << 2) /* Bit 2: Read Descriptor Parity Checker Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MPES (1 << 3) /* Bit 3: MTL Data Path Parity Checker Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MTSPES (1 << 4) /* Bit 4: MTL Transmit Status Data Path Parity Checker Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ARPES (1 << 5) /* Bit 5: Application Receive Interface Data Path Parity Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_TTES (1 << 8) /* Bit 8: Transmit FSM Timeout Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_RTES (1 << 9) /* Bit 9: Receive FSM Timeout Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_ATES (1 << 11) /* Bit 11: APP FSM Timeout Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_PTES (1 << 12) /* Bit 12: PTP FSM Timeout Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_MSTTES (1 << 16) /* Bit 16: Master Read Or Write Timeout Error Status */
+#define EMAC_MAC_DPP_FSM_INTERRUPT_STATUS_FSMPES (1 << 24) /* Bit 24: FSM State Parity Error Status */
+
+/* MAC FSM Control (MAC_FSM_CONTROL) */
+#define EMAC_MAC_FSM_CONTROL_TMOUTEN (1 << 0) /* Bit 0: Time Out Enable */
+#define EMAC_MAC_FSM_CONTROL_PRTYEN (1 << 1) /* Bit 1: Parity Enable */
+#define EMAC_MAC_FSM_CONTROL_TTEIN (1 << 8) /* Bit 8: Transmit FSM Timeout Error Injection */
+#define EMAC_MAC_FSM_CONTROL_RTEIN (1 << 9) /* Bit 9: Receive FSM Timeout Error Injection */
+#define EMAC_MAC_FSM_CONTROL_ATEIN (1 << 11) /* Bit 11: APP FSM Timeout Error Injection */
+#define EMAC_MAC_FSM_CONTROL_PTEIN (1 << 12) /* Bit 12: PTP FSM Timeout Error Injection */
+#define EMAC_MAC_FSM_CONTROL_TPEIN (1 << 16) /* Bit 16: Transmit FSM Parity Error Injection */
+#define EMAC_MAC_FSM_CONTROL_RPEIN (1 << 17) /* Bit 17: Receive FSM Parity Error Injection */
+#define EMAC_MAC_FSM_CONTROL_APEIN (1 << 19) /* Bit 19: APP FSM Parity Error Injection */
+#define EMAC_MAC_FSM_CONTROL_PPEIN (1 << 20) /* Bit 20: PTP FSM Parity Error Injection */
+#define EMAC_MAC_FSM_CONTROL_TLGRNML (1 << 24) /* Bit 24: Transmit Large Or Normal Mode Select */
+#define EMAC_MAC_FSM_CONTROL_RLGRNML (1 << 25) /* Bit 25: Receive Large Or Normal Mode Select */
+#define EMAC_MAC_FSM_CONTROL_ALGRNML (1 << 27) /* Bit 27: APP Large Or Normal Mode Select */
+#define EMAC_MAC_FSM_CONTROL_PLGRNML (1 << 28) /* Bit 28: PTP Large Or Normal Mode Select */
+
+/* MAC FSM ACT Timer (MAC_FSM_ACT_TIMER) */
+#define EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT (0) /* Bits 0-10: CSR Clocks For 1 us Tic */
+#define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3FF << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT)
+#define EMAC_MAC_FSM_ACT_TIMER_TMR(n) ((n << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK)
+#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT (16) /* Bits 16-20: Normal Mode Timeout Value */
+#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT)
+#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) ((n << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK)
+#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT (20) /* Bits 20-24: Large Mode Timeout Value */
+#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT)
+#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) ((n << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK)
+
+/* SCS_REG 1 (SCS_REG1) */
+#define EMAC_SCS_REG1_MAC_SCS1_SHIFT (0) /* Bits 0-32: MAC SCS 1 */
+#define EMAC_SCS_REG1_MAC_SCS1_MASK (0xFFFFFFFF << EMAC_SCS_REG1_MAC_SCS1_SHIFT)
+#define EMAC_SCS_REG1_MAC_SCS1(n) ((n << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK)
+
+/* MAC MDIO Address (MAC_MDIO_ADDRESS) */
+#define EMAC_MAC_MDIO_ADDRESS_GB (1 << 0) /* Bit 0: GMII Busy */
+#define EMAC_MAC_MDIO_ADDRESS_C45E (1 << 1) /* Bit 1: Clause 45 PHY Enable */
+#define EMAC_MAC_MDIO_ADDRESS_GOC_0 (1 << 2) /* Bit 2: GMII Operation Command 0 */
+#define EMAC_MAC_MDIO_ADDRESS_GOC_1 (1 << 3) /* Bit 3: GMII Operation Command 1 */
+#define EMAC_MAC_MDIO_ADDRESS_SKAP (1 << 4) /* Bit 4: Skip Address Packet */
+#define EMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8) /* Bits 8-12: CSR Clock Range */
+#define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xF << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_CR(n) ((n << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12) /* Bits 12-15: Number Of Trailing Clocks */
+#define EMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7 << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_NTC(n) ((n << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16) /* Bits 16-21: Register Or Device Address */
+#define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_RDA(n) ((n << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21) /* Bits 21-26: Physical Layer Address */
+#define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_PA(n) ((n << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK)
+#define EMAC_MAC_MDIO_ADDRESS_BTB (1 << 26) /* Bit 26: Back-To-Back Transactions */
+#define EMAC_MAC_MDIO_ADDRESS_PSE (1 << 27) /* Bit 27: Preamble Suppression Enable */
+
+/* MAC MDIO Data (MAC_MDIO_DATA) */
+#define EMAC_MAC_MDIO_DATA_GD_SHIFT (0) /* Bits 0-16: GMII Data */
+#define EMAC_MAC_MDIO_DATA_GD_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_GD_SHIFT)
+#define EMAC_MAC_MDIO_DATA_GD(n) ((n << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK)
+#define EMAC_MAC_MDIO_DATA_RA_SHIFT (16) /* Bits 16-32: Register Address */
+#define EMAC_MAC_MDIO_DATA_RA_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_RA_SHIFT)
+#define EMAC_MAC_MDIO_DATA_RA(n) ((n << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK)
+
+/* MAC CSR Software Control (MAC_CSR_SW_CTRL) */
+#define EMAC_MAC_CSR_SW_CTRL_RCWE (1 << 0) /* Bit 0: Enable Register Write 1 To Clear (W1C) */
+#define EMAC_MAC_CSR_SW_CTRL_SEEN (1 << 8) /* Bit 8: Slave Error Response Enable */
+
+/* MAC FPE Control STS (MAC_FPE_CTRL_STS) */
+#define EMAC_MAC_FPE_CTRL_STS_EFPE (1 << 0) /* Bit 0: Enable Transmit Frame Preemption */
+#define EMAC_MAC_FPE_CTRL_STS_SVER (1 << 1) /* Bit 1: Send Verify mPacket */
+#define EMAC_MAC_FPE_CTRL_STS_SRSP (1 << 2) /* Bit 2: Send Respond mPacket */
+#define EMAC_MAC_FPE_CTRL_STS_S1_SET_0 (1 << 3) /* Bit 3: S1 SET 0 */
+#define EMAC_MAC_FPE_CTRL_STS_RVER (1 << 16) /* Bit 16: Received Verify Frame */
+#define EMAC_MAC_FPE_CTRL_STS_RRSP (1 << 17) /* Bit 17: Received Respond Frame */
+#define EMAC_MAC_FPE_CTRL_STS_TVER (1 << 18) /* Bit 18: Transmitted Verify Frame */
+#define EMAC_MAC_FPE_CTRL_STS_TRSP (1 << 19) /* Bit 19: Transmitted Respond Frame */
+
+/* MAC Presentation Time (MAC_PRESN_TIME_NS) */
+#define EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time (In Nanoseconds) */
+#define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT)
+#define EMAC_MAC_PRESN_TIME_NS_MPTN(n) ((n << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK)
+
+/* MAC Presentation Time Update (MAC_PRESN_TIME_UPDT) */
+#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time Update */
+#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)
+#define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) ((n << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK)
+
+/* MAC Address 0 High (MAC_ADDRESS0_HIGH) */
+#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 0 [47:32] */
+#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)
+#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK)
+#define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
+#define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT)
+#define EMAC_MAC_ADDRESS0_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_DCS_MASK)
+#define EMAC_MAC_ADDRESS0_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
+
+/* MAC Address 0 Low (MAC_ADDRESS0_LOW) */
+#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 0 [31:0] */
+#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)
+#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK)
+
+/* MAC Address 1 High (MAC_ADDRESS1_HIGH) */
+#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */
+#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT)
+#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK)
+#define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
+#define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT)
+#define EMAC_MAC_ADDRESS1_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK)
+#define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */
+#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT)
+#define EMAC_MAC_ADDRESS1_HIGH_MBC(n) ((n << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK)
+#define EMAC_MAC_ADDRESS1_HIGH_SA (1 << 30) /* Bit 30: Source Address */
+#define EMAC_MAC_ADDRESS1_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
+
+/* MAC Address 1 Low (MAC_ADDRESS1_LOW) */
+#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */
+#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT)
+#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK)
+
+/* MAC Address 2 High (MAC_ADDRESS2_HIGH) */
+#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */
+#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT)
+#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) ((n << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK)
+#define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
+#define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT)
+#define EMAC_MAC_ADDRESS2_HIGH_DCS(n) ((n << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK)
+#define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */
+#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT)
+#define EMAC_MAC_ADDRESS2_HIGH_MBC(n) ((n << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK)
+#define EMAC_MAC_ADDRESS2_HIGH_SA (1 << 30) /* Bit 30: Source Address */
+#define EMAC_MAC_ADDRESS2_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
+
+/* MAC Address 2 Low (MAC_ADDRESS2_LOW) */
+#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */
+#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT)
+#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) ((n << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK)
+
+/* MMC Control (MMC_CONTROL) */
+#define EMAC_MMC_CONTROL_CNTRST (1 << 0) /* Bit 0: Counters Reset */
+#define EMAC_MMC_CONTROL_CNTSTOPRO (1 << 1) /* Bit 1: Counter Stop Rollover */
+#define EMAC_MMC_CONTROL_RSTONRD (1 << 2) /* Bit 2: Reset On Read */
+#define EMAC_MMC_CONTROL_CNTFREEZ (1 << 3) /* Bit 3: MMC Counter Freeze */
+#define EMAC_MMC_CONTROL_CNTPRST (1 << 4) /* Bit 4: Counters Preset */
+#define EMAC_MMC_CONTROL_CNTPRSTLVL (1 << 5) /* Bit 5: Full-Half Preset */
+#define EMAC_MMC_CONTROL_UCDBC (1 << 8) /* Bit 8: Update MMC Counters For Dropped Broadcast Packets */
+
+/* MMC Receive Interrupt (MMC_RX_INTERRUPT) */
+#define EMAC_MMC_RX_INTERRUPT_RXGBPKTIS (1 << 0) /* Bit 0: MMC Receive Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXGBOCTIS (1 << 1) /* Bit 1: MMC Receive Good Bad Octet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXGOCTIS (1 << 2) /* Bit 2: MMC Receive Good Octet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXBCGPIS (1 << 3) /* Bit 3: MMC Receive Broadcast Good Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXMCGPIS (1 << 4) /* Bit 4: MMC Receive Multicast Good Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXCRCERPIS (1 << 5) /* Bit 5: MMC Receive CRC Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXALGNERPIS (1 << 6) /* Bit 6: MMC Receive Alignment Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXRUNTPIS (1 << 7) /* Bit 7: MMC Receive Runt Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXJABERPIS (1 << 8) /* Bit 8: MMC Receive Jabber Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXUSIZEGPIS (1 << 9) /* Bit 9: MMC Receive Undersize Good Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXOSIZEGPIS (1 << 10) /* Bit 10: MMC Receive Oversize Good Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RX64OCTGBPIS (1 << 11) /* Bit 11: MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS (1 << 12) /* Bit 12: MMC Receive 65 To 127 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS (1 << 13) /* Bit 13: MMC Receive 128 To 255 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS (1 << 14) /* Bit 14: MMC Receive 256 To 511 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS (1 << 15) /* Bit 15: MMC Receive 512 To 1023 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS (1 << 16) /* Bit 16: MMC Receive 1024 To Maximum Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXUCGPIS (1 << 17) /* Bit 17: MMC Receive Unicast Good Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXLENERPIS (1 << 18) /* Bit 18: MMC Receive Length Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXORANGEPIS (1 << 19) /* Bit 19: MMC Receive Out-Of-Range Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXPAUSPIS (1 << 20) /* Bit 20: MMC Receive Pause Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXFOVPIS (1 << 21) /* Bit 21: MMC Receive FIFO Overflow Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXVLANGBPIS (1 << 22) /* Bit 22: MMC Receive VLAN Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXWDOGPIS (1 << 23) /* Bit 23: MMC Receive Watchdog Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXRCVERRPIS (1 << 24) /* Bit 24: MMC Receive Error Packet Counter Interrupt Status */
+#define EMAC_MMC_RX_INTERRUPT_RXCTRLPIS (1 << 25) /* Bit 25: MMC Receive Control Packet Counter Interrupt Status */
+
+/* MMC Transmit Interrupt (MMC_TX_INTERRUPT) */
+#define EMAC_MMC_TX_INTERRUPT_TXGBOCTIS (1 << 0) /* Bit 0: MMC Transmit Good Bad Octet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXGBPKTIS (1 << 1) /* Bit 1: MMC Transmit Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXBCGPIS (1 << 2) /* Bit 2: MMC Transmit Broadcast Good Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXMCGPIS (1 << 3) /* Bit 3: MMC Transmit Multicast Good Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TX64OCTGBPIS (1 << 4) /* Bit 4: MMC Transmit 64-Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS (1 << 5) /* Bit 5: MMC Transmit 65 To 127 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS (1 << 6) /* Bit 6: MMC Transmit 128 To 255 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS (1 << 7) /* Bit 7: MMC Transmit 256 To 511 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS (1 << 8) /* Bit 8: MMC Transmit 512 To 1023 Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS (1 << 9) /* Bit 9: MMC Transmit 1024 To Maximum Octet Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXUCGBPIS (1 << 10) /* Bit 10: MMC Transmit Unicast Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXMCGBPIS (1 << 11) /* Bit 11: MMC Transmit Multicast Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXBCGBPIS (1 << 12) /* Bit 12: MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXUFLOWERPIS (1 << 13) /* Bit 13: MMC Transmit Underflow Error Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXSCOLGPIS (1 << 14) /* Bit 14: MMC Transmit Single Collision Good Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXMCOLGPIS (1 << 15) /* Bit 15: MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXDEFPIS (1 << 16) /* Bit 16: MMC Transmit Deferred Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXLATCOLPIS (1 << 17) /* Bit 17: MMC Transmit Late Collision Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXEXCOLPIS (1 << 18) /* Bit 18: MMC Transmit Excessive Collision Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXCARERPIS (1 << 19) /* Bit 19: MMC Transmit Carrier Error Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXGOCTIS (1 << 20) /* Bit 20: MMC Transmit Good Octet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXGPKTIS (1 << 21) /* Bit 21: MMC Transmit Good Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXEXDEFPIS (1 << 22) /* Bit 22: MMC Transmit Excessive Deferral Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXPAUSPIS (1 << 23) /* Bit 23: MMC Transmit Pause Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXVLANGPIS (1 << 24) /* Bit 24: MMC Transmit VLAN Good Packet Counter Interrupt Status */
+#define EMAC_MMC_TX_INTERRUPT_TXOSIZEGPIS (1 << 25) /* Bit 25: MMC Transmit Oversize Good Packet Counter Interrupt Status */
+
+/* MMC Receive Interrupt Mask (MMC_RX_INTERRUPT_MASK) */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM (1 << 0) /* Bit 0: MMC Receive Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM (1 << 1) /* Bit 1: MMC Receive Good Bad Octet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM (1 << 2) /* Bit 2: MMC Receive Good Octet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM (1 << 3) /* Bit 3: MMC Receive Broadcast Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM (1 << 4) /* Bit 4: MMC Receive Multicast Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM (1 << 5) /* Bit 5: MMC Receive CRC Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM (1 << 6) /* Bit 6: MMC Receive Alignment Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM (1 << 7) /* Bit 7: MMC Receive Runt Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM (1 << 8) /* Bit 8: MMC Receive Jabber Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM (1 << 9) /* Bit 9: MMC Receive Undersize Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM (1 << 10) /* Bit 10: MMC Receive Oversize Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM (1 << 11) /* Bit 11: MMC Receive 64-Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM (1 << 12) /* Bit 12: MMC Receive 65 To 127 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM (1 << 13) /* Bit 13: MMC Receive 128 To 255 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM (1 << 14) /* Bit 14: MMC Receive 256 To 511 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM (1 << 15) /* Bit 15: MMC Receive 512 To 1023 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM (1 << 16) /* Bit 16: MMC Receive 1024 To Maximum Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM (1 << 17) /* Bit 17: MMC Receive Unicast Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM (1 << 18) /* Bit 18: MMC Receive Length Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM (1 << 19) /* Bit 19: MMC Receive Out-Of-Range Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM (1 << 20) /* Bit 20: MMC Receive Pause Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM (1 << 21) /* Bit 21: MMC Receive FIFO Overflow Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM (1 << 22) /* Bit 22: MMC Receive VLAN Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM (1 << 23) /* Bit 23: MMC Receive Watchdog Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM (1 << 24) /* Bit 24: MMC Receive Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM (1 << 25) /* Bit 25: MMC Receive Control Packet Counter Interrupt Mask */
+
+/* MMC Transmit Interrupt Mask (MMC_TX_INTERRUPT_MASK) */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM (1 << 0) /* Bit 0: MMC Transmit Good Bad Octet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM (1 << 1) /* Bit 1: MMC Transmit Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM (1 << 2) /* Bit 2: MMC Transmit Broadcast Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM (1 << 3) /* Bit 3: MMC Transmit Multicast Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM (1 << 4) /* Bit 4: MMC Transmit 64-Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM (1 << 5) /* Bit 5: MMC Transmit 65 To 127 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM (1 << 6) /* Bit 6: MMC Transmit 128 To 255 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM (1 << 7) /* Bit 7: MMC Transmit 256 To 511 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM (1 << 8) /* Bit 8: MMC Transmit 512 To 1023 Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM (1 << 9) /* Bit 9: MMC Transmit 1024 To Maximum Octet Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM (1 << 10) /* Bit 10: MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM (1 << 11) /* Bit 11: MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM (1 << 12) /* Bit 12: MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM (1 << 13) /* Bit 13: MMC Transmit Underflow Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM (1 << 14) /* Bit 14: MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM (1 << 15) /* Bit 15: MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM (1 << 16) /* Bit 16: MMC Transmit Deferred Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM (1 << 17) /* Bit 17: MMC Transmit Late Collision Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM (1 << 18) /* Bit 18: MMC Transmit Excessive Collision Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM (1 << 19) /* Bit 19: MMC Transmit Carrier Error Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM (1 << 20) /* Bit 20: MMC Transmit Good Octet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM (1 << 21) /* Bit 21: MMC Transmit Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM (1 << 22) /* Bit 22: MMC Transmit Excessive Deferral Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM (1 << 23) /* Bit 23: MMC Transmit Pause Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM (1 << 24) /* Bit 24: MMC Transmit VLAN Good Packet Counter Interrupt Mask */
+#define EMAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM (1 << 25) /* Bit 25: MMC Transmit Oversize Good Packet Counter Interrupt Mask */
+
+/* Transmit Octet Count Good Bad (TX_OCTET_COUNT_GOOD_BAD) */
+#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good Bad */
+#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)
+#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) ((n << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
+
+/* Transmit Packet Count Good Bad (TX_PACKET_COUNT_GOOD_BAD) */
+#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good Bad */
+#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)
+#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) ((n << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
+
+/* Transmit Broadcast Packets Good (TX_BROADCAST_PACKETS_GOOD) */
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good */
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) ((n << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
+
+/* Transmit Multicast Packets Good (TX_MULTICAST_PACKETS_GOOD) */
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good */
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) ((n << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
+
+/* Transmit 64-Octet Packets Good Bad (TX_64OCTETS_PACKETS_GOOD_BAD) */
+#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0) /* Bits 0-32: Transmit 64-Octet Packets Good Bad */
+#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFF << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)
+#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) ((n << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
+
+/* Transmit 65 To 127 Octet Packets Good Bad
+ * (TX_65TO127OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0) /* Bits 0-32: Transmit 65 To 127 Octet Packets Good Bad */
+#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)
+#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) ((n << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
+
+/* Transmit 128 To 255 Octet Packets Good Bad
+ * (TX_128TO255OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0) /* Bits 0-32: Transmit 128 To 255 Octet Packets Good Bad */
+#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)
+#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) ((n << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
+
+/* Transmit 256 To 511 Octet Packets Good Bad
+ * (TX_256TO511OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0) /* Bits 0-32: Transmit 256 To 511 Octet Packets Good Bad */
+#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)
+#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) ((n << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
+
+/* Transmit 512 To 1023 Octet Packets Good Bad
+ * (TX_512TO1023OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Transmit 512 To 1023 Octet Packets Good Bad */
+#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)
+#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) ((n << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
+
+/* Transmit 1024 To Max Octet Packets Good Bad
+ * (TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Transmit 1024 To Max Octet Packets Good Bad */
+#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)
+#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) ((n << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
+
+/* Transmit Unicast Packets Good Bad
+ * (TX_UNICAST_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0) /* Bits 0-32: Transmit Unicast Packets Good Bad */
+#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFF << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)
+#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) ((n << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
+
+/* Transmit Multicast Packets Good Bad (TX_MULTICAST_PACKETS_GOOD_BAD) */
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good Bad */
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) ((n << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
+
+/* Transmit Broadcast Packets Good Bad (TX_BROADCAST_PACKETS_GOOD_BAD) */
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good Bad */
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) ((n << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
+
+/* Transmit Underflow Error Packets (TX_UNDERFLOW_ERROR_PACKETS) */
+#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0) /* Bits 0-32: Transmit Underflow Error Packets */
+#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFF << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)
+#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) ((n << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
+
+/* Transmit Single Collision Good Packets
+ * (TX_SINGLE_COLLISION_GOOD_PACKETS)
+ */
+
+#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0) /* Bits 0-32: Transmit Single Collision Good Packets */
+#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFF << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)
+#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) ((n << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
+
+/* Transmit Multiple Collision Good Packets
+ * (TX_MULTIPLE_COLLISION_GOOD_PACKETS)
+ */
+
+#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0) /* Bits 0-32: Transmit Multiple Collision Good Packets */
+#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFF << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)
+#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) ((n << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
+
+/* Transmit Deferred Packets (TX_DEFERRED_PACKETS) */
+#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0) /* Bits 0-32: Transmit Deferred Packets */
+#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFF << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)
+#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) ((n << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
+
+/* Transmit Late Collision Packets (TX_LATE_COLLISION_PACKETS) */
+#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0) /* Bits 0-32: Transmit Late Collision Packets */
+#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFF << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)
+#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) ((n << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
+
+/* Transmit Excessive Collision Packets (TX_EXCESSIVE_COLLISION_PACKETS) */
+#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0) /* Bits 0-32: Transmit Excessive Collision Packets */
+#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)
+#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) ((n << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
+
+/* Transmit Carrier Error Packets (TX_CARRIER_ERROR_PACKETS) */
+#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0) /* Bits 0-32: Transmit Carrier Error Packets */
+#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFF << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)
+#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) ((n << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
+
+/* Transmit Octet Count Good (TX_OCTET_COUNT_GOOD) */
+#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good */
+#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)
+#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) ((n << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
+
+/* Transmit Packet Count Good (TX_PACKET_COUNT_GOOD) */
+#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good */
+#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)
+#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) ((n << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
+
+/* Transmit Excessive Deferral Error (TX_EXCESSIVE_DEFERRAL_ERROR) */
+#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0) /* Bits 0-32: Transmit Excessive Deferral Error */
+#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)
+#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) ((n << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
+
+/* Transmit Pause Packets (TX_PAUSE_PACKETS) */
+#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0) /* Bits 0-32: Transmit Pause Packets */
+#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFF << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)
+#define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) ((n << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
+
+/* Transmit VLAN Packets Good (TX_VLAN_PACKETS_GOOD) */
+#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0) /* Bits 0-32: Transmit VLAN Packets Good */
+#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFF << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)
+#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) ((n << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
+
+/* Transmit O Size Packets Good (TX_OSIZE_PACKETS_GOOD) */
+#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0) /* Bits 0-32: Transmit O Size Packets Good */
+#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFF << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)
+#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) ((n << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
+
+/* Receive Packets Count Good Bad (RX_PACKETS_COUNT_GOOD_BAD) */
+#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0) /* Bits 0-32: Receive Packets Count Good Bad */
+#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFF << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)
+#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) ((n << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
+
+/* Receive Octet Count Good Bad (RX_OCTET_COUNT_GOOD_BAD) */
+#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0) /* Bits 0-32: Receive Octet Count Good Bad */
+#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)
+#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) ((n << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
+
+/* Receive Octet Count Good (RX_OCTET_COUNT_GOOD) */
+#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0) /* Bits 0-32: Receive Octet Count Good */
+#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)
+#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) ((n << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
+
+/* Receive Broadcast Packets Good (RX_BROADCAST_PACKETS_GOOD) */
+#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0) /* Bits 0-32: Receive Broadcast Packets Good */
+#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFF << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)
+#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) ((n << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
+
+/* Receive Multicast Packets Good (RX_MULTICAST_PACKETS_GOOD) */
+#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0) /* Bits 0-32: Receive Multicast Packets Good */
+#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFF << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)
+#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) ((n << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
+
+/* Receive CRC Error Packets (RX_CRC_ERROR_PACKETS) */
+#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0) /* Bits 0-32: Receive CRC Error Packets */
+#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFF << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)
+#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) ((n << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
+
+/* Receive Alignment Error Packets (RX_ALIGNMENT_ERROR_PACKETS) */
+#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0) /* Bits 0-32: Receive Alignment Error Packets */
+#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFF << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)
+#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) ((n << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
+
+/* Receive Runt Error Packets (RX_RUNT_ERROR_PACKETS) */
+#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0) /* Bits 0-32: Receive Runt Error Packets */
+#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFF << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)
+#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) ((n << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
+
+/* Receive Jabber Error Packets (RX_JABBER_ERROR_PACKETS) */
+#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0) /* Bits 0-32: Receive Jabber Error Packets */
+#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFF << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)
+#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) ((n << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
+
+/* Receive Undersize Packets Good (RX_UNDERSIZE_PACKETS_GOOD) */
+#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0) /* Bits 0-32: Receive Undersize Packets Good */
+#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFF << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)
+#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) ((n << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
+
+/* Receive Oversize Packets Good (RX_OVERSIZE_PACKETS_GOOD) */
+#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0) /* Bits 0-32: Receive Oversize Packets Good */
+#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFF << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)
+#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) ((n << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
+
+/* Receive 64 Octets Packets Good Bad (RX_64OCTETS_PACKETS_GOOD_BAD) */
+#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0) /* Bits 0-32: Receive 64 Octets Packets Good Bad */
+#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFF << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)
+#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) ((n << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
+
+/* Receive 65-127 Octets Packets Good Bad
+ * (RX_65TO127OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0) /* Bits 0-32: Receive 65-127 Octets Packets Good Bad */
+#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)
+#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) ((n << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
+
+/* Receive 128-255 Octets Packets Good Bad
+ * (RX_128TO255OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0) /* Bits 0-32: Receive 128-255 Octets Packets Good Bad */
+#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)
+#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) ((n << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
+
+/* Receive 256-511 Octets Packets Good Bad
+ * (RX_256TO511OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0) /* Bits 0-32: Receive 256-511 Octets Packets Good Bad */
+#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)
+#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) ((n << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
+
+/* Receive 512-1023 Octets Packets Good Bad
+ * (RX_512TO1023OCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Receive 512-1023 Octets Packets Good Bad */
+#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)
+#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) ((n << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
+
+/* Receive 1024 To Max Octets Good Bad
+ * (RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD)
+ */
+
+#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Receive 1024-Max Octets Good Bad */
+#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)
+#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) ((n << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
+
+/* Receive Unicast Packets Good (RX_UNICAST_PACKETS_GOOD) */
+#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0) /* Bits 0-32: Receive Unicast Packets Good */
+#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFF << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)
+#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) ((n << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
+
+/* Receive Length Error Packets (RX_LENGTH_ERROR_PACKETS) */
+#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0) /* Bits 0-32: Receive Length Error Packets */
+#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFF << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)
+#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) ((n << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
+
+/* Receive Out of Range Type Packet (RX_OUT_OF_RANGE_TYPE_PACKETS) */
+#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0) /* Bits 0-32: Receive Out of Range Type Packet */
+#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFF << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)
+#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) ((n << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
+
+/* Receive Pause Packets (RX_PAUSE_PACKETS) */
+#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0) /* Bits 0-32: Receive Pause Packets */
+#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFF << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)
+#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) ((n << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
+
+/* Receive FIFO Overflow Packets (RX_FIFO_OVERFLOW_PACKETS) */
+#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0) /* Bits 0-32: Receive FIFO Overflow Packets */
+#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFF << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)
+#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) ((n << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
+
+/* Receive VLAN Packets Good Bad (RX_VLAN_PACKETS_GOOD_BAD) */
+#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0) /* Bits 0-32: Receive VLAN Packets Good Bad */
+#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFF << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)
+#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) ((n << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
+
+/* Receive Watchdog Error Packets (RX_WATCHDOG_ERROR_PACKETS) */
+#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0) /* Bits 0-32: Receive Watchdog Error Packets */
+#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFF << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)
+#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) ((n << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
+
+/* Receive Receive Error Packets (RX_RECEIVE_ERROR_PACKETS) */
+#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0) /* Bits 0-32: Receive Receive Error Packets */
+#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFF << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)
+#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) ((n << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
+
+/* Receive Control Packets Good (RX_CONTROL_PACKETS_GOOD) */
+#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0) /* Bits 0-32: Receive Control Packets Good */
+#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFF << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)
+#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) ((n << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
... 39862 lines suppressed ...
[incubator-nuttx] 08/09: NX style fixes
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit ec118743ea0bdc1201263f3f2c460000018faf66
Author: Peter van der Perk <pe...@nxp.com>
AuthorDate: Fri Jul 22 20:23:16 2022 +0200
NX style fixes
---
arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h | 36 --
arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h | 590 ++++++++++-----------
arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h | 58 +-
arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h | 8 +-
arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h | 76 +--
arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h | 2 +-
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h | 71 ++-
.../arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h | 4 +-
arch/arm/src/s32k3xx/s32k3xx_edma.c | 38 +-
9 files changed, 441 insertions(+), 442 deletions(-)
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
index cb39c54d5e..7f2978c3b1 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_edma.h
@@ -1160,42 +1160,6 @@
#define S32K3XX_EDMA_TCD31_CSR (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_CSR_OFFSET)
#define S32K3XX_EDMA_TCD31_BITER (S32K3XX_EDMA_TCD_BASE + S32K3XX_EDMA_TCD31_BITER_OFFSET)
-uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
-{
- S32K3XX_EDMA_CH0_CSR,
- S32K3XX_EDMA_CH1_CSR,
- S32K3XX_EDMA_CH2_CSR,
- S32K3XX_EDMA_CH3_CSR,
- S32K3XX_EDMA_CH4_CSR,
- S32K3XX_EDMA_CH5_CSR,
- S32K3XX_EDMA_CH6_CSR,
- S32K3XX_EDMA_CH7_CSR,
- S32K3XX_EDMA_CH8_CSR,
- S32K3XX_EDMA_CH9_CSR,
- S32K3XX_EDMA_CH10_CSR,
- S32K3XX_EDMA_CH11_CSR,
- S32K3XX_EDMA_CH12_CSR,
- S32K3XX_EDMA_CH13_CSR,
- S32K3XX_EDMA_CH14_CSR,
- S32K3XX_EDMA_CH15_CSR,
- S32K3XX_EDMA_CH16_CSR,
- S32K3XX_EDMA_CH17_CSR,
- S32K3XX_EDMA_CH18_CSR,
- S32K3XX_EDMA_CH19_CSR,
- S32K3XX_EDMA_CH20_CSR,
- S32K3XX_EDMA_CH21_CSR,
- S32K3XX_EDMA_CH22_CSR,
- S32K3XX_EDMA_CH23_CSR,
- S32K3XX_EDMA_CH24_CSR,
- S32K3XX_EDMA_CH25_CSR,
- S32K3XX_EDMA_CH26_CSR,
- S32K3XX_EDMA_CH27_CSR,
- S32K3XX_EDMA_CH28_CSR,
- S32K3XX_EDMA_CH29_CSR,
- S32K3XX_EDMA_CH30_CSR,
- S32K3XX_EDMA_CH31_CSR
-};
-
/* eDMA Register Bitfield Definitions ***************************************/
/* Management Page Control Register (CSR) */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
index b53f34ef87..1ac45a4380 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emac.h
@@ -624,7 +624,7 @@
/* MAC Extended Configuration (MAC_EXT_CONFIGURATION) */
#define EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0) /* Bits 0-14: Giant Packet Size Limit */
-#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFF << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT)
+#define EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3fff << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT)
#define EMAC_MAC_EXT_CONFIGURATION_GPSL(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_GPSL_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_GPSL_MASK)
#define EMAC_MAC_EXT_CONFIGURATION_DCRCC (1 << 16) /* Bit 16: Disable CRC Checking For Received Packets */
#define EMAC_MAC_EXT_CONFIGURATION_SPEN (1 << 17) /* Bit 17: Slow Protocol Detection Enable */
@@ -632,7 +632,7 @@
#define EMAC_MAC_EXT_CONFIGURATION_PDC (1 << 19) /* Bit 19: Packet Duplication Control */
#define EMAC_MAC_EXT_CONFIGURATION_EIPGEN (1 << 24) /* Bit 24: Extended Inter-Packet Gap Enable */
#define EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25) /* Bits 25-30: Extended Inter-Packet Gap */
-#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1F << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT)
+#define EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK (0x1f << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT)
#define EMAC_MAC_EXT_CONFIGURATION_EIPG(n) (((n) << EMAC_MAC_EXT_CONFIGURATION_EIPG_SHIFT) & EMAC_MAC_EXT_CONFIGURATION_EIPG_MASK)
/* MAC Packet Filter (MAC_PACKET_FILTER) */
@@ -655,23 +655,23 @@
/* MAC Watchdog Timeout (MAC_WATCHDOG_TIMEOUT) */
#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0) /* Bits 0-4: Watchdog Timeout */
-#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xF << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)
+#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xf << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)
#define EMAC_MAC_WATCHDOG_TIMEOUT_WTO(n) (((n) << EMAC_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT) & EMAC_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
#define EMAC_MAC_WATCHDOG_TIMEOUT_PWE (1 << 8) /* Bit 8: Programmable Watchdog Enable */
/* MAC Hash Table First 32 Bits (MAC_HASH_TABLE_REG0) */
#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0) /* Bits 0-32: MAC Hash Table First 32 Bits */
-#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)
+#define EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xffffffff << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)
#define EMAC_MAC_HASH_TABLE_REG0_HT31T0(n) (((n) << EMAC_MAC_HASH_TABLE_REG0_HT31T0_SHIFT) & EMAC_MAC_HASH_TABLE_REG0_HT31T0_MASK)
/* MAC Hash Table Second 32 Bits (MAC_HASH_TABLE_REG1) */
#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0) /* Bits 0-32: MAC Hash Table Second 32 Bits */
-#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFF << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)
+#define EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xffffffff << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)
#define EMAC_MAC_HASH_TABLE_REG1_HT63T32(n) (((n) << EMAC_MAC_HASH_TABLE_REG1_HT63T32_SHIFT) & EMAC_MAC_HASH_TABLE_REG1_HT63T32_MASK)
/* MAC VLAN Tag (MAC_VLAN_TAG) */
#define EMAC_MAC_VLAN_TAG_VL_SHIFT (0) /* Bits 0-16: VLAN Tag Identifier for Receive Packets */
-#define EMAC_MAC_VLAN_TAG_VL_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_VL_SHIFT)
+#define EMAC_MAC_VLAN_TAG_VL_MASK (0xffff << EMAC_MAC_VLAN_TAG_VL_SHIFT)
#define EMAC_MAC_VLAN_TAG_VL(n) (((n) << EMAC_MAC_VLAN_TAG_VL_SHIFT) & EMAC_MAC_VLAN_TAG_VL_MASK)
#define EMAC_MAC_VLAN_TAG_ETV (1 << 16) /* Bit 16: Enable Tag For VLAN */
#define EMAC_MAC_VLAN_TAG_VTIM (1 << 17) /* Bit 17: VLAN Tag Inverse Match Enable */
@@ -715,7 +715,7 @@
/* MAC VLAN Tag Data (MAC_VLAN_TAG_DATA) */
#define EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
-#define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_DATA_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT)
#define EMAC_MAC_VLAN_TAG_DATA_VID(n) (((n) << EMAC_MAC_VLAN_TAG_DATA_VID_SHIFT) & EMAC_MAC_VLAN_TAG_DATA_VID_MASK)
#define EMAC_MAC_VLAN_TAG_DATA_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_DATA_ETV (1 << 17) /* Bit 17: VLAN Comparison */
@@ -727,7 +727,7 @@
/* MAC VLAN Tag Filter 0 (MAC_VLAN_TAG_FILTER0) */
#define EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
-#define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT)
#define EMAC_MAC_VLAN_TAG_FILTER0_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER0_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER0_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER0_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER0_ETV (1 << 17) /* Bit 17: VLAN Comparison */
@@ -739,7 +739,7 @@
/* MAC VLAN Tag Filter 1 (MAC_VLAN_TAG_FILTER1) */
#define EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
-#define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT)
#define EMAC_MAC_VLAN_TAG_FILTER1_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER1_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER1_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER1_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER1_ETV (1 << 17) /* Bit 17: VLAN Comparison */
@@ -751,7 +751,7 @@
/* MAC VLAN Tag Filter 2 (MAC_VLAN_TAG_FILTER2) */
#define EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
-#define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT)
#define EMAC_MAC_VLAN_TAG_FILTER2_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER2_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER2_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER2_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER2_ETV (1 << 17) /* Bit 17: VLAN Comparison */
@@ -763,7 +763,7 @@
/* MAC VLAN Tag Filter 3 (MAC_VLAN_TAG_FILTER3) */
#define EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT (0) /* Bits 0-16: VLAN Tag ID */
-#define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xFFFF << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT)
+#define EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK (0xffff << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT)
#define EMAC_MAC_VLAN_TAG_FILTER3_VID(n) (((n) << EMAC_MAC_VLAN_TAG_FILTER3_VID_SHIFT) & EMAC_MAC_VLAN_TAG_FILTER3_VID_MASK)
#define EMAC_MAC_VLAN_TAG_FILTER3_VEN (1 << 16) /* Bit 16: VLAN Tag Enable */
#define EMAC_MAC_VLAN_TAG_FILTER3_ETV (1 << 17) /* Bit 17: VLAN Comparison */
@@ -775,12 +775,12 @@
/* MAC VLAN Hash Table (MAC_VLAN_HASH_TABLE) */
#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0) /* Bits 0-16: VLAN Hash Table */
-#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFF << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)
+#define EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xffff << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)
#define EMAC_MAC_VLAN_HASH_TABLE_VLHT(n) (((n) << EMAC_MAC_VLAN_HASH_TABLE_VLHT_SHIFT) & EMAC_MAC_VLAN_HASH_TABLE_VLHT_MASK)
/* MAC VLAN Inclusion Or Replacement (MAC_VLAN_INCL) */
#define EMAC_MAC_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */
-#define EMAC_MAC_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_VLAN_INCL_VLT_SHIFT)
+#define EMAC_MAC_VLAN_INCL_VLT_MASK (0xffff << EMAC_MAC_VLAN_INCL_VLT_SHIFT)
#define EMAC_MAC_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_VLAN_INCL_VLT_MASK)
#define EMAC_MAC_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control */
#define EMAC_MAC_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_VLAN_INCL_VLC_SHIFT)
@@ -795,7 +795,7 @@
/* Inner VLAN Tag Inclusion Or Replacement (MAC_INNER_VLAN_INCL) */
#define EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT (0) /* Bits 0-16: VLAN Tag For Transmit Packets */
-#define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFF << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT)
+#define EMAC_MAC_INNER_VLAN_INCL_VLT_MASK (0xffff << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT)
#define EMAC_MAC_INNER_VLAN_INCL_VLT(n) (((n) << EMAC_MAC_INNER_VLAN_INCL_VLT_SHIFT) & EMAC_MAC_INNER_VLAN_INCL_VLT_MASK)
#define EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT (16) /* Bits 16-18: VLAN Tag Control in Transmit Packets */
#define EMAC_MAC_INNER_VLAN_INCL_VLC_MASK (0x3 << EMAC_MAC_INNER_VLAN_INCL_VLC_SHIFT)
@@ -812,7 +812,7 @@
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PLT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PLT_MASK)
#define EMAC_MAC_Q0_TX_FLOW_CTRL_DZPQ (1 << 7) /* Bit 7: Disable Zero-Quanta Pause */
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT (16) /* Bits 16-32: Pause Time */
-#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xFFFF << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT)
+#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK (0xffff << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT)
#define EMAC_MAC_Q0_TX_FLOW_CTRL_PT(n) (((n) << EMAC_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT) & EMAC_MAC_Q0_TX_FLOW_CTRL_PT_MASK)
/* MAC Receive Flow Control (MAC_RX_FLOW_CTRL) */
@@ -865,10 +865,10 @@
/* MAC RxQ Control 2 (MAC_RXQ_CTRL2) */
#define EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT (0) /* Bits 0-8: Priorities Selected In Receive Queue 0 */
-#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK (0xff << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT)
#define EMAC_MAC_RXQ_CTRL2_PSRQ0(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ0_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ0_MASK)
#define EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT (8) /* Bits 8-16: Priorities Selected In Receive Queue 1 */
-#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xFF << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT)
+#define EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK (0xff << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT)
#define EMAC_MAC_RXQ_CTRL2_PSRQ1(n) (((n) << EMAC_MAC_RXQ_CTRL2_PSRQ1_SHIFT) & EMAC_MAC_RXQ_CTRL2_PSRQ1_MASK)
/* MAC Interrupt Status (MAC_INTERRUPT_STATUS) */
@@ -903,10 +903,10 @@
/* MAC Version (MAC_VERSION) */
#define EMAC_MAC_VERSION_IPVER_SHIFT (0) /* Bits 0-8: IP Version */
-#define EMAC_MAC_VERSION_IPVER_MASK (0xFF << EMAC_MAC_VERSION_IPVER_SHIFT)
+#define EMAC_MAC_VERSION_IPVER_MASK (0xff << EMAC_MAC_VERSION_IPVER_SHIFT)
#define EMAC_MAC_VERSION_IPVER(n) (((n) << EMAC_MAC_VERSION_IPVER_SHIFT) & EMAC_MAC_VERSION_IPVER_MASK)
#define EMAC_MAC_VERSION_CFGVER_SHIFT (8) /* Bits 8-16: IP Configuration Version */
-#define EMAC_MAC_VERSION_CFGVER_MASK (0xFF << EMAC_MAC_VERSION_CFGVER_SHIFT)
+#define EMAC_MAC_VERSION_CFGVER_MASK (0xff << EMAC_MAC_VERSION_CFGVER_SHIFT)
#define EMAC_MAC_VERSION_CFGVER(n) (((n) << EMAC_MAC_VERSION_CFGVER_SHIFT) & EMAC_MAC_VERSION_CFGVER_MASK)
/* MAC Debug (MAC_DEBUG) */
@@ -935,7 +935,7 @@
#define EMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14) /* Bit 14: Transmit Checksum Offload Feature */
#define EMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) /* Bit 16: Receive Checksum Offload Feature */
#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT (18) /* Bits 18-23: MAC Addresses 1-31 */
-#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1F << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT)
+#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK (0x1f << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT)
#define EMAC_MAC_HW_FEATURE0_ADDMACADRSEL(n) (((n) << EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_SHIFT) & EMAC_MAC_HW_FEATURE0_ADDMACADRSEL_MASK)
#define EMAC_MAC_HW_FEATURE0_MACADR32SEL (1 << 23) /* Bit 23: MAC Addresses 32-63 */
#define EMAC_MAC_HW_FEATURE0_MACADR64SEL (1 << 24) /* Bit 24: MAC Addresses 64-127 */
@@ -949,11 +949,11 @@
/* MAC Hardware Feature 1 (MAC_HW_FEATURE1) */
#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT (0) /* Bits 0-5: MTL Receive FIFO Size Feature */
-#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK (0x1f << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT)
#define EMAC_MAC_HW_FEATURE1_RXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_RXFIFOSIZE_MASK)
#define EMAC_MAC_HW_FEATURE1_SPRAM (1 << 5) /* Bit 5: Single Port RAM Feature */
#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT (6) /* Bits 6-11: MTL Transmit FIFO Size Feature */
-#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1F << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK (0x1f << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT)
#define EMAC_MAC_HW_FEATURE1_TXFIFOSIZE(n) (((n) << EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) & EMAC_MAC_HW_FEATURE1_TXFIFOSIZE_MASK)
#define EMAC_MAC_HW_FEATURE1_OSTEN (1 << 11) /* Bit 11: One-Step Timestamping Enable Feature */
#define EMAC_MAC_HW_FEATURE1_PTOEN (1 << 12) /* Bit 12: PTP Offload Enable Feature */
@@ -972,21 +972,21 @@
#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK (0x3 << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT)
#define EMAC_MAC_HW_FEATURE1_HASHTBLSZ(n) (((n) << EMAC_MAC_HW_FEATURE1_HASHTBLSZ_SHIFT) & EMAC_MAC_HW_FEATURE1_HASHTBLSZ_MASK)
#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT (27) /* Bits 27-31: L3 Or L4 Filter Number */
-#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xF << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT)
+#define EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK (0xf << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT)
#define EMAC_MAC_HW_FEATURE1_L3L4FNUM(n) (((n) << EMAC_MAC_HW_FEATURE1_L3L4FNUM_SHIFT) & EMAC_MAC_HW_FEATURE1_L3L4FNUM_MASK)
/* MAC Hardware Feature 2 (MAC_HW_FEATURE2) */
#define EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT (0) /* Bits 0-4: Number Of MTL Receive Queues */
-#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_RXQCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT)
#define EMAC_MAC_HW_FEATURE2_RXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXQCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT (6) /* Bits 6-10: Number Of MTL Transmit Queues */
-#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_TXQCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT)
#define EMAC_MAC_HW_FEATURE2_TXQCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXQCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXQCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT (12) /* Bits 12-16: Number Of DMA Receive Channels */
-#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT)
#define EMAC_MAC_HW_FEATURE2_RXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_RXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_RXCHCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT (18) /* Bits 18-22: Number Of DMA Transmit Channels */
-#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xF << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT)
+#define EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK (0xf << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT)
#define EMAC_MAC_HW_FEATURE2_TXCHCNT(n) (((n) << EMAC_MAC_HW_FEATURE2_TXCHCNT_SHIFT) & EMAC_MAC_HW_FEATURE2_TXCHCNT_MASK)
#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT (24) /* Bits 24-27: Number Of PPS Outputs */
#define EMAC_MAC_HW_FEATURE2_PPSOUTNUM_MASK (0x7 << EMAC_MAC_HW_FEATURE2_PPSOUTNUM_SHIFT)
@@ -1052,18 +1052,18 @@
/* MAC FSM ACT Timer (MAC_FSM_ACT_TIMER) */
#define EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT (0) /* Bits 0-10: CSR Clocks For 1 us Tic */
-#define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3FF << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT)
+#define EMAC_MAC_FSM_ACT_TIMER_TMR_MASK (0x3ff << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT)
#define EMAC_MAC_FSM_ACT_TIMER_TMR(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_TMR_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_TMR_MASK)
#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT (16) /* Bits 16-20: Normal Mode Timeout Value */
-#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT)
+#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK (0xf << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT)
#define EMAC_MAC_FSM_ACT_TIMER_NTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_NTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_NTMRMD_MASK)
#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT (20) /* Bits 20-24: Large Mode Timeout Value */
-#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xF << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT)
+#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK (0xf << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT)
#define EMAC_MAC_FSM_ACT_TIMER_LTMRMD(n) (((n) << EMAC_MAC_FSM_ACT_TIMER_LTMRMD_SHIFT) & EMAC_MAC_FSM_ACT_TIMER_LTMRMD_MASK)
/* SCS_REG 1 (SCS_REG1) */
#define EMAC_SCS_REG1_MAC_SCS1_SHIFT (0) /* Bits 0-32: MAC SCS 1 */
-#define EMAC_SCS_REG1_MAC_SCS1_MASK (0xFFFFFFFF << EMAC_SCS_REG1_MAC_SCS1_SHIFT)
+#define EMAC_SCS_REG1_MAC_SCS1_MASK (0xffffffff << EMAC_SCS_REG1_MAC_SCS1_SHIFT)
#define EMAC_SCS_REG1_MAC_SCS1(n) (((n) << EMAC_SCS_REG1_MAC_SCS1_SHIFT) & EMAC_SCS_REG1_MAC_SCS1_MASK)
/* MAC MDIO Address (MAC_MDIO_ADDRESS) */
@@ -1073,26 +1073,26 @@
#define EMAC_MAC_MDIO_ADDRESS_GOC_1 (1 << 3) /* Bit 3: GMII Operation Command 1 */
#define EMAC_MAC_MDIO_ADDRESS_SKAP (1 << 4) /* Bit 4: Skip Address Packet */
#define EMAC_MAC_MDIO_ADDRESS_CR_SHIFT (8) /* Bits 8-12: CSR Clock Range */
-#define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xF << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_CR_MASK (0xf << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT)
#define EMAC_MAC_MDIO_ADDRESS_CR(n) (((n) << EMAC_MAC_MDIO_ADDRESS_CR_SHIFT) & EMAC_MAC_MDIO_ADDRESS_CR_MASK)
#define EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT (12) /* Bits 12-15: Number Of Trailing Clocks */
#define EMAC_MAC_MDIO_ADDRESS_NTC_MASK (0x7 << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT)
#define EMAC_MAC_MDIO_ADDRESS_NTC(n) (((n) << EMAC_MAC_MDIO_ADDRESS_NTC_SHIFT) & EMAC_MAC_MDIO_ADDRESS_NTC_MASK)
#define EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT (16) /* Bits 16-21: Register Or Device Address */
-#define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_RDA_MASK (0x1f << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT)
#define EMAC_MAC_MDIO_ADDRESS_RDA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_RDA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_RDA_MASK)
#define EMAC_MAC_MDIO_ADDRESS_PA_SHIFT (21) /* Bits 21-26: Physical Layer Address */
-#define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1F << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT)
+#define EMAC_MAC_MDIO_ADDRESS_PA_MASK (0x1f << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT)
#define EMAC_MAC_MDIO_ADDRESS_PA(n) (((n) << EMAC_MAC_MDIO_ADDRESS_PA_SHIFT) & EMAC_MAC_MDIO_ADDRESS_PA_MASK)
#define EMAC_MAC_MDIO_ADDRESS_BTB (1 << 26) /* Bit 26: Back-To-Back Transactions */
#define EMAC_MAC_MDIO_ADDRESS_PSE (1 << 27) /* Bit 27: Preamble Suppression Enable */
/* MAC MDIO Data (MAC_MDIO_DATA) */
#define EMAC_MAC_MDIO_DATA_GD_SHIFT (0) /* Bits 0-16: GMII Data */
-#define EMAC_MAC_MDIO_DATA_GD_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_GD_SHIFT)
+#define EMAC_MAC_MDIO_DATA_GD_MASK (0xffff << EMAC_MAC_MDIO_DATA_GD_SHIFT)
#define EMAC_MAC_MDIO_DATA_GD(n) (((n) << EMAC_MAC_MDIO_DATA_GD_SHIFT) & EMAC_MAC_MDIO_DATA_GD_MASK)
#define EMAC_MAC_MDIO_DATA_RA_SHIFT (16) /* Bits 16-32: Register Address */
-#define EMAC_MAC_MDIO_DATA_RA_MASK (0xFFFF << EMAC_MAC_MDIO_DATA_RA_SHIFT)
+#define EMAC_MAC_MDIO_DATA_RA_MASK (0xffff << EMAC_MAC_MDIO_DATA_RA_SHIFT)
#define EMAC_MAC_MDIO_DATA_RA(n) (((n) << EMAC_MAC_MDIO_DATA_RA_SHIFT) & EMAC_MAC_MDIO_DATA_RA_MASK)
/* MAC CSR Software Control (MAC_CSR_SW_CTRL) */
@@ -1111,17 +1111,17 @@
/* MAC Presentation Time (MAC_PRESN_TIME_NS) */
#define EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time (In Nanoseconds) */
-#define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT)
+#define EMAC_MAC_PRESN_TIME_NS_MPTN_MASK (0xffffffff << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT)
#define EMAC_MAC_PRESN_TIME_NS_MPTN(n) (((n) << EMAC_MAC_PRESN_TIME_NS_MPTN_SHIFT) & EMAC_MAC_PRESN_TIME_NS_MPTN_MASK)
/* MAC Presentation Time Update (MAC_PRESN_TIME_UPDT) */
#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0) /* Bits 0-32: MAC 1722 Presentation Time Update */
-#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFF << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)
+#define EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xffffffff << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)
#define EMAC_MAC_PRESN_TIME_UPDT_MPTU(n) (((n) << EMAC_MAC_PRESN_TIME_UPDT_MPTU_SHIFT) & EMAC_MAC_PRESN_TIME_UPDT_MPTU_MASK)
/* MAC Address 0 High (MAC_ADDRESS0_HIGH) */
#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 0 [47:32] */
-#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)
+#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK (0xffff << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT)
#define EMAC_MAC_ADDRESS0_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS0_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS0_HIGH_ADDRHI_MASK)
#define EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
#define EMAC_MAC_ADDRESS0_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS0_HIGH_DCS_SHIFT)
@@ -1130,43 +1130,43 @@
/* MAC Address 0 Low (MAC_ADDRESS0_LOW) */
#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 0 [31:0] */
-#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)
+#define EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK (0xffffffff << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT)
#define EMAC_MAC_ADDRESS0_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS0_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS0_LOW_ADDRLO_MASK)
/* MAC Address 1 High (MAC_ADDRESS1_HIGH) */
#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */
-#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT)
+#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK (0xffff << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT)
#define EMAC_MAC_ADDRESS1_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_ADDRHI_MASK)
#define EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
#define EMAC_MAC_ADDRESS1_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT)
#define EMAC_MAC_ADDRESS1_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_DCS_MASK)
#define EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */
-#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT)
+#define EMAC_MAC_ADDRESS1_HIGH_MBC_MASK (0x3f << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT)
#define EMAC_MAC_ADDRESS1_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS1_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS1_HIGH_MBC_MASK)
#define EMAC_MAC_ADDRESS1_HIGH_SA (1 << 30) /* Bit 30: Source Address */
#define EMAC_MAC_ADDRESS1_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
/* MAC Address 1 Low (MAC_ADDRESS1_LOW) */
#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */
-#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT)
+#define EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK (0xffffffff << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT)
#define EMAC_MAC_ADDRESS1_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS1_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS1_LOW_ADDRLO_MASK)
/* MAC Address 2 High (MAC_ADDRESS2_HIGH) */
#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT (0) /* Bits 0-16: MAC Address 1 [47:32] */
-#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xFFFF << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT)
+#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK (0xffff << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT)
#define EMAC_MAC_ADDRESS2_HIGH_ADDRHI(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_ADDRHI_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_ADDRHI_MASK)
#define EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT (16) /* Bits 16-18: DMA Channel Select */
#define EMAC_MAC_ADDRESS2_HIGH_DCS_MASK (0x3 << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT)
#define EMAC_MAC_ADDRESS2_HIGH_DCS(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_DCS_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_DCS_MASK)
#define EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT (24) /* Bits 24-30: Mask Byte Control */
-#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3F << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT)
+#define EMAC_MAC_ADDRESS2_HIGH_MBC_MASK (0x3f << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT)
#define EMAC_MAC_ADDRESS2_HIGH_MBC(n) (((n) << EMAC_MAC_ADDRESS2_HIGH_MBC_SHIFT) & EMAC_MAC_ADDRESS2_HIGH_MBC_MASK)
#define EMAC_MAC_ADDRESS2_HIGH_SA (1 << 30) /* Bit 30: Source Address */
#define EMAC_MAC_ADDRESS2_HIGH_AE (1 << 31) /* Bit 31: Address Enable */
/* MAC Address 2 Low (MAC_ADDRESS2_LOW) */
#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT (0) /* Bits 0-32: MAC Address 1 [31:0] */
-#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xFFFFFFFF << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT)
+#define EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK (0xffffffff << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT)
#define EMAC_MAC_ADDRESS2_LOW_ADDRLO(n) (((n) << EMAC_MAC_ADDRESS2_LOW_ADDRLO_SHIFT) & EMAC_MAC_ADDRESS2_LOW_ADDRLO_MASK)
/* MMC Control (MMC_CONTROL) */
@@ -1292,27 +1292,27 @@
/* Transmit Octet Count Good Bad (TX_OCTET_COUNT_GOOD_BAD) */
#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good Bad */
-#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)
+#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xffffffff << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)
#define EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
/* Transmit Packet Count Good Bad (TX_PACKET_COUNT_GOOD_BAD) */
#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good Bad */
-#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)
+#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xffffffff << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)
#define EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
/* Transmit Broadcast Packets Good (TX_BROADCAST_PACKETS_GOOD) */
#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good */
-#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xffffffff << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)
#define EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
/* Transmit Multicast Packets Good (TX_MULTICAST_PACKETS_GOOD) */
#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good */
-#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xffffffff << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)
#define EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
/* Transmit 64-Octet Packets Good Bad (TX_64OCTETS_PACKETS_GOOD_BAD) */
#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0) /* Bits 0-32: Transmit 64-Octet Packets Good Bad */
-#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFF << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)
+#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xffffffff << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)
#define EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(n) (((n) << EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT) & EMAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
/* Transmit 65 To 127 Octet Packets Good Bad
@@ -1320,7 +1320,7 @@
*/
#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0) /* Bits 0-32: Transmit 65 To 127 Octet Packets Good Bad */
-#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)
+#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xffffffff << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)
#define EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(n) (((n) << EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT) & EMAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
/* Transmit 128 To 255 Octet Packets Good Bad
@@ -1328,7 +1328,7 @@
*/
#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0) /* Bits 0-32: Transmit 128 To 255 Octet Packets Good Bad */
-#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)
+#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xffffffff << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)
#define EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(n) (((n) << EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT) & EMAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
/* Transmit 256 To 511 Octet Packets Good Bad
@@ -1336,7 +1336,7 @@
*/
#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0) /* Bits 0-32: Transmit 256 To 511 Octet Packets Good Bad */
-#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)
+#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xffffffff << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)
#define EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(n) (((n) << EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT) & EMAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
/* Transmit 512 To 1023 Octet Packets Good Bad
@@ -1344,7 +1344,7 @@
*/
#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Transmit 512 To 1023 Octet Packets Good Bad */
-#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)
+#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xffffffff << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)
#define EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(n) (((n) << EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT) & EMAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
/* Transmit 1024 To Max Octet Packets Good Bad
@@ -1352,7 +1352,7 @@
*/
#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Transmit 1024 To Max Octet Packets Good Bad */
-#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)
+#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xffffffff << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)
#define EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(n) (((n) << EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT) & EMAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
/* Transmit Unicast Packets Good Bad
@@ -1360,22 +1360,22 @@
*/
#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0) /* Bits 0-32: Transmit Unicast Packets Good Bad */
-#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFF << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)
+#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xffffffff << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)
#define EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(n) (((n) << EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT) & EMAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
/* Transmit Multicast Packets Good Bad (TX_MULTICAST_PACKETS_GOOD_BAD) */
#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0) /* Bits 0-32: Transmit Multicast Packets Good Bad */
-#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFF << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)
+#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xffffffff << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)
#define EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(n) (((n) << EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT) & EMAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
/* Transmit Broadcast Packets Good Bad (TX_BROADCAST_PACKETS_GOOD_BAD) */
#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0) /* Bits 0-32: Transmit Broadcast Packets Good Bad */
-#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFF << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)
+#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xffffffff << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)
#define EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(n) (((n) << EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT) & EMAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
/* Transmit Underflow Error Packets (TX_UNDERFLOW_ERROR_PACKETS) */
#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0) /* Bits 0-32: Transmit Underflow Error Packets */
-#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFF << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)
+#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xffffffff << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)
#define EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(n) (((n) << EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT) & EMAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
/* Transmit Single Collision Good Packets
@@ -1383,7 +1383,7 @@
*/
#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0) /* Bits 0-32: Transmit Single Collision Good Packets */
-#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFF << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)
+#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xffffffff << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)
#define EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(n) (((n) << EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT) & EMAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
/* Transmit Multiple Collision Good Packets
@@ -1391,117 +1391,117 @@
*/
#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0) /* Bits 0-32: Transmit Multiple Collision Good Packets */
-#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFF << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)
+#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xffffffff << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)
#define EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(n) (((n) << EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT) & EMAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
/* Transmit Deferred Packets (TX_DEFERRED_PACKETS) */
#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0) /* Bits 0-32: Transmit Deferred Packets */
-#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFF << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)
+#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xffffffff << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)
#define EMAC_TX_DEFERRED_PACKETS_TXDEFRD(n) (((n) << EMAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT) & EMAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
/* Transmit Late Collision Packets (TX_LATE_COLLISION_PACKETS) */
#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0) /* Bits 0-32: Transmit Late Collision Packets */
-#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFF << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)
+#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xffffffff << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)
#define EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(n) (((n) << EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT) & EMAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
/* Transmit Excessive Collision Packets (TX_EXCESSIVE_COLLISION_PACKETS) */
#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0) /* Bits 0-32: Transmit Excessive Collision Packets */
-#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)
+#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xffffffff << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)
#define EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(n) (((n) << EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT) & EMAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
/* Transmit Carrier Error Packets (TX_CARRIER_ERROR_PACKETS) */
#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0) /* Bits 0-32: Transmit Carrier Error Packets */
-#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFF << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)
+#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xffffffff << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)
#define EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR(n) (((n) << EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT) & EMAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
/* Transmit Octet Count Good (TX_OCTET_COUNT_GOOD) */
#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0) /* Bits 0-32: Transmit Octet Count Good */
-#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFF << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)
+#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xffffffff << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)
#define EMAC_TX_OCTET_COUNT_GOOD_TXOCTG(n) (((n) << EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT) & EMAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
/* Transmit Packet Count Good (TX_PACKET_COUNT_GOOD) */
#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0) /* Bits 0-32: Transmit Packet Count Good */
-#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFF << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)
+#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xffffffff << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)
#define EMAC_TX_PACKET_COUNT_GOOD_TXPKTG(n) (((n) << EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT) & EMAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
/* Transmit Excessive Deferral Error (TX_EXCESSIVE_DEFERRAL_ERROR) */
#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0) /* Bits 0-32: Transmit Excessive Deferral Error */
-#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFF << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)
+#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xffffffff << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)
#define EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(n) (((n) << EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT) & EMAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
/* Transmit Pause Packets (TX_PAUSE_PACKETS) */
#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0) /* Bits 0-32: Transmit Pause Packets */
-#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFF << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)
+#define EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xffffffff << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)
#define EMAC_TX_PAUSE_PACKETS_TXPAUSE(n) (((n) << EMAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT) & EMAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
/* Transmit VLAN Packets Good (TX_VLAN_PACKETS_GOOD) */
#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0) /* Bits 0-32: Transmit VLAN Packets Good */
-#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFF << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)
+#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xffffffff << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)
#define EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG(n) (((n) << EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT) & EMAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
/* Transmit O Size Packets Good (TX_OSIZE_PACKETS_GOOD) */
#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0) /* Bits 0-32: Transmit O Size Packets Good */
-#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFF << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)
+#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xffffffff << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)
#define EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(n) (((n) << EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT) & EMAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
/* Receive Packets Count Good Bad (RX_PACKETS_COUNT_GOOD_BAD) */
#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0) /* Bits 0-32: Receive Packets Count Good Bad */
-#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFF << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)
+#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xffffffff << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)
#define EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(n) (((n) << EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT) & EMAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
/* Receive Octet Count Good Bad (RX_OCTET_COUNT_GOOD_BAD) */
#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0) /* Bits 0-32: Receive Octet Count Good Bad */
-#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)
+#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xffffffff << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)
#define EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
/* Receive Octet Count Good (RX_OCTET_COUNT_GOOD) */
#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0) /* Bits 0-32: Receive Octet Count Good */
-#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFF << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)
+#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xffffffff << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)
#define EMAC_RX_OCTET_COUNT_GOOD_RXOCTG(n) (((n) << EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT) & EMAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
/* Receive Broadcast Packets Good (RX_BROADCAST_PACKETS_GOOD) */
#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0) /* Bits 0-32: Receive Broadcast Packets Good */
-#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFF << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)
+#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xffffffff << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)
#define EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(n) (((n) << EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT) & EMAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
/* Receive Multicast Packets Good (RX_MULTICAST_PACKETS_GOOD) */
#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0) /* Bits 0-32: Receive Multicast Packets Good */
-#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFF << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)
+#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xffffffff << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)
#define EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(n) (((n) << EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT) & EMAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
/* Receive CRC Error Packets (RX_CRC_ERROR_PACKETS) */
#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0) /* Bits 0-32: Receive CRC Error Packets */
-#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFF << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)
+#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xffffffff << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)
#define EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR(n) (((n) << EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT) & EMAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
/* Receive Alignment Error Packets (RX_ALIGNMENT_ERROR_PACKETS) */
#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0) /* Bits 0-32: Receive Alignment Error Packets */
-#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFF << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)
+#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xffffffff << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)
#define EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(n) (((n) << EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT) & EMAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
/* Receive Runt Error Packets (RX_RUNT_ERROR_PACKETS) */
#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0) /* Bits 0-32: Receive Runt Error Packets */
-#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFF << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)
+#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xffffffff << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)
#define EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(n) (((n) << EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT) & EMAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
/* Receive Jabber Error Packets (RX_JABBER_ERROR_PACKETS) */
#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0) /* Bits 0-32: Receive Jabber Error Packets */
-#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFF << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)
+#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xffffffff << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)
#define EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR(n) (((n) << EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT) & EMAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
/* Receive Undersize Packets Good (RX_UNDERSIZE_PACKETS_GOOD) */
#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0) /* Bits 0-32: Receive Undersize Packets Good */
-#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFF << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)
+#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xffffffff << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)
#define EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(n) (((n) << EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT) & EMAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
/* Receive Oversize Packets Good (RX_OVERSIZE_PACKETS_GOOD) */
#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0) /* Bits 0-32: Receive Oversize Packets Good */
-#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFF << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)
+#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xffffffff << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)
#define EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(n) (((n) << EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT) & EMAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
/* Receive 64 Octets Packets Good Bad (RX_64OCTETS_PACKETS_GOOD_BAD) */
#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0) /* Bits 0-32: Receive 64 Octets Packets Good Bad */
-#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFF << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)
+#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xffffffff << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)
#define EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(n) (((n) << EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT) & EMAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
/* Receive 65-127 Octets Packets Good Bad
@@ -1509,7 +1509,7 @@
*/
#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0) /* Bits 0-32: Receive 65-127 Octets Packets Good Bad */
-#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFF << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)
+#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xffffffff << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)
#define EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(n) (((n) << EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT) & EMAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
/* Receive 128-255 Octets Packets Good Bad
@@ -1517,7 +1517,7 @@
*/
#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0) /* Bits 0-32: Receive 128-255 Octets Packets Good Bad */
-#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFF << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)
+#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xffffffff << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)
#define EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(n) (((n) << EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT) & EMAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
/* Receive 256-511 Octets Packets Good Bad
@@ -1525,7 +1525,7 @@
*/
#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0) /* Bits 0-32: Receive 256-511 Octets Packets Good Bad */
-#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFF << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)
+#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xffffffff << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)
#define EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(n) (((n) << EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT) & EMAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
/* Receive 512-1023 Octets Packets Good Bad
@@ -1533,7 +1533,7 @@
*/
#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0) /* Bits 0-32: Receive 512-1023 Octets Packets Good Bad */
-#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFF << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)
+#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xffffffff << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)
#define EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(n) (((n) << EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT) & EMAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
/* Receive 1024 To Max Octets Good Bad
@@ -1541,52 +1541,52 @@
*/
#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0) /* Bits 0-32: Receive 1024-Max Octets Good Bad */
-#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFF << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)
+#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xffffffff << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)
#define EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(n) (((n) << EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT) & EMAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
/* Receive Unicast Packets Good (RX_UNICAST_PACKETS_GOOD) */
#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0) /* Bits 0-32: Receive Unicast Packets Good */
-#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFF << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)
+#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xffffffff << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)
#define EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(n) (((n) << EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT) & EMAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
/* Receive Length Error Packets (RX_LENGTH_ERROR_PACKETS) */
#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0) /* Bits 0-32: Receive Length Error Packets */
-#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFF << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)
+#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xffffffff << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)
#define EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(n) (((n) << EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT) & EMAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
/* Receive Out of Range Type Packet (RX_OUT_OF_RANGE_TYPE_PACKETS) */
#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0) /* Bits 0-32: Receive Out of Range Type Packet */
-#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFF << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)
+#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xffffffff << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)
#define EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(n) (((n) << EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT) & EMAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
/* Receive Pause Packets (RX_PAUSE_PACKETS) */
#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0) /* Bits 0-32: Receive Pause Packets */
-#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFF << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)
+#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xffffffff << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)
#define EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT(n) (((n) << EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT) & EMAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
/* Receive FIFO Overflow Packets (RX_FIFO_OVERFLOW_PACKETS) */
#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0) /* Bits 0-32: Receive FIFO Overflow Packets */
-#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFF << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)
+#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xffffffff << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)
#define EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(n) (((n) << EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT) & EMAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
/* Receive VLAN Packets Good Bad (RX_VLAN_PACKETS_GOOD_BAD) */
#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0) /* Bits 0-32: Receive VLAN Packets Good Bad */
-#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFF << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)
+#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xffffffff << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)
#define EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(n) (((n) << EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT) & EMAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
/* Receive Watchdog Error Packets (RX_WATCHDOG_ERROR_PACKETS) */
#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0) /* Bits 0-32: Receive Watchdog Error Packets */
-#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFF << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)
+#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xffffffff << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)
#define EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(n) (((n) << EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT) & EMAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
/* Receive Receive Error Packets (RX_RECEIVE_ERROR_PACKETS) */
#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0) /* Bits 0-32: Receive Receive Error Packets */
-#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFF << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)
+#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xffffffff << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)
#define EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(n) (((n) << EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT) & EMAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
/* Receive Control Packets Good (RX_CONTROL_PACKETS_GOOD) */
#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0) /* Bits 0-32: Receive Control Packets Good */
-#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFF << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)
+#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xffffffff << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)
#define EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(n) (((n) << EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT) & EMAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
/* MMC Transmit FPE Fragment Counter Interrupt Status
@@ -1602,12 +1602,12 @@
/* Transmit FPE Fragment Counter (MMC_TX_FPE_FRAGMENT_CNTR) */
#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0) /* Bits 0-32: Transmit FPE Fragment Counter */
-#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFF << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)
+#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xffffffff << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)
#define EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(n) (((n) << EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT) & EMAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
/* Transmit Hold Request Counter (MMC_TX_HOLD_REQ_CNTR) */
#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0) /* Bits 0-32: Transmit Hold Request Counter */
-#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFF << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)
+#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xffffffff << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)
#define EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(n) (((n) << EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT) & EMAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
/* MMC Receive Packet Assembly Error Counter Interrupt Status
@@ -1630,22 +1630,22 @@
*/
#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0) /* Bits 0-32: Packet Assembly Error Counter */
-#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)
+#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xffffffff << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)
#define EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
/* MMC Receive Packet SMD Error Counter (MMC_RX_PACKET_SMD_ERR_CNTR) */
#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0) /* Bits 0-32: Packet SMD Error Counter */
-#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)
+#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xffffffff << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)
#define EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(n) (((n) << EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT) & EMAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
/* MMC Receive Packet Assembly OK Counter (MMC_RX_PACKET_ASSEMBLY_OK_CNTR) */
#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0) /* Bits 0-32: Packet Assembly OK Counter */
-#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFF << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)
+#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xffffffff << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)
#define EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(n) (((n) << EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT) & EMAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
/* MMC Receive FPE Fragment Counter (MMC_RX_FPE_FRAGMENT_CNTR) */
#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0) /* Bits 0-32: FPE Fragment Counter */
-#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFF << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)
+#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xffffffff << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)
#define EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(n) (((n) << EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT) & EMAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
/* MAC Layer 3 Layer 4 Control 0 (MAC_L3_L4_CONTROL0) */
@@ -1655,10 +1655,10 @@
#define EMAC_MAC_L3_L4_CONTROL0_L3DAM0 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable */
#define EMAC_MAC_L3_L4_CONTROL0_L3DAIM0 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable */
#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match */
-#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL0_L3HSBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match */
-#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL0_L3HDBM0(n) (((n) << EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT) & EMAC_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
#define EMAC_MAC_L3_L4_CONTROL0_L4PEN0 (1 << 16) /* Bit 16: Layer 4 Protocol Enable */
#define EMAC_MAC_L3_L4_CONTROL0_L4SPM0 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable */
@@ -1670,30 +1670,30 @@
/* MAC Layer 4 Address 0 (MAC_LAYER4_ADDRESS0) */
#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number */
-#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS0_L4SP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number */
-#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS0_L4DP0(n) (((n) << EMAC_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT) & EMAC_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
/* MAC Layer 3 Address 0 Reg 0 (MAC_LAYER3_ADDR0_REG0) */
#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
-#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)
#define EMAC_MAC_LAYER3_ADDR0_REG0_L3A00(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
/* MAC Layer 3 Address 1 Reg 0 (MAC_LAYER3_ADDR1_REG0) */
#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
-#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)
#define EMAC_MAC_LAYER3_ADDR1_REG0_L3A10(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
/* MAC Layer 3 Address 2 Reg 0 (MAC_LAYER3_ADDR2_REG0) */
#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
-#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)
#define EMAC_MAC_LAYER3_ADDR2_REG0_L3A20(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
/* MAC Layer 3 Address 3 Reg 0 (MAC_LAYER3_ADDR3_REG0) */
#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
-#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)
#define EMAC_MAC_LAYER3_ADDR3_REG0_L3A30(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
/* MAC L3 L4 Control 1 (MAC_L3_L4_CONTROL1) */
@@ -1703,10 +1703,10 @@
#define EMAC_MAC_L3_L4_CONTROL1_L3DAM1 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L3DAIM1 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 1 */
-#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL1_L3HSBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 1 */
-#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL1_L3HDBM1(n) (((n) << EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT) & EMAC_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
#define EMAC_MAC_L3_L4_CONTROL1_L4PEN1 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 1 */
#define EMAC_MAC_L3_L4_CONTROL1_L4SPM1 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 1 */
@@ -1718,30 +1718,30 @@
/* MAC Layer 4 Address 1 (MAC_LAYER4_ADDRESS1) */
#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 1 */
-#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS1_L4SP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 1 */
-#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS1_L4DP1(n) (((n) << EMAC_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT) & EMAC_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
/* MAC Layer 3 Address 0 Reg 1 (MAC_LAYER3_ADDR0_REG1) */
#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
-#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)
#define EMAC_MAC_LAYER3_ADDR0_REG1_L3A01(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
/* MAC Layer 3 Address 1 Reg 1 (MAC_LAYER3_ADDR1_REG1) */
#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
-#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)
#define EMAC_MAC_LAYER3_ADDR1_REG1_L3A11(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
/* MAC Layer 3 Address 2 Reg 1 (MAC_LAYER3_ADDR2_REG1) */
#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
-#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)
#define EMAC_MAC_LAYER3_ADDR2_REG1_L3A21(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
/* MAC Layer 3 Address 3 Reg 1 (MAC_LAYER3_ADDR3_REG1) */
#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
-#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)
#define EMAC_MAC_LAYER3_ADDR3_REG1_L3A31(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
/* MAC L3 L4 Control 2 (MAC_L3_L4_CONTROL2) */
@@ -1751,10 +1751,10 @@
#define EMAC_MAC_L3_L4_CONTROL2_L3DAM2 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L3DAIM2 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 2 */
-#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL2_L3HSBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 2 */
-#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL2_L3HDBM2(n) (((n) << EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT) & EMAC_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
#define EMAC_MAC_L3_L4_CONTROL2_L4PEN2 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 2 */
#define EMAC_MAC_L3_L4_CONTROL2_L4SPM2 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 2 */
@@ -1766,30 +1766,30 @@
/* MAC Layer 4 Address 2 (MAC_LAYER4_ADDRESS2) */
#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 2 */
-#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS2_L4SP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 2 */
-#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS2_L4DP2(n) (((n) << EMAC_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT) & EMAC_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
/* MAC Layer 3 Address 0 Reg 2 (MAC_LAYER3_ADDR0_REG2) */
#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
-#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)
#define EMAC_MAC_LAYER3_ADDR0_REG2_L3A02(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
/* MAC Layer 3 Address 1 Reg 2 (MAC_LAYER3_ADDR1_REG2) */
#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
-#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)
#define EMAC_MAC_LAYER3_ADDR1_REG2_L3A12(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
/* MAC Layer 3 Address 2 Reg 2 (MAC_LAYER3_ADDR2_REG2) */
#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
-#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)
#define EMAC_MAC_LAYER3_ADDR2_REG2_L3A22(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
/* MAC Layer 3 Address 3 Reg 2 (MAC_LAYER3_ADDR3_REG2) */
#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
-#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)
#define EMAC_MAC_LAYER3_ADDR3_REG2_L3A32(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
/* MAC L3 L4 Control 3 (MAC_L3_L4_CONTROL3) */
@@ -1799,10 +1799,10 @@
#define EMAC_MAC_L3_L4_CONTROL3_L3DAM3 (1 << 4) /* Bit 4: Layer 3 IP DA Match Enable 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L3DAIM3 (1 << 5) /* Bit 5: Layer 3 IP DA Inverse Match Enable 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6) /* Bits 6-11: Layer 3 IP SA Higher Bits Match 3 */
-#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL3_L3HSBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11) /* Bits 11-16: Layer 3 IP DA Higher Bits Match 3 */
-#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0x1F << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)
+#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0x1f << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)
#define EMAC_MAC_L3_L4_CONTROL3_L3HDBM3(n) (((n) << EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT) & EMAC_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
#define EMAC_MAC_L3_L4_CONTROL3_L4PEN3 (1 << 16) /* Bit 16: Layer 4 Protocol Enable 3 */
#define EMAC_MAC_L3_L4_CONTROL3_L4SPM3 (1 << 18) /* Bit 18: Layer 4 Source Port Match Enable 3 */
@@ -1814,30 +1814,30 @@
/* MAC Layer 4 Address 3 (MAC_LAYER4_ADDRESS3) */
#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0) /* Bits 0-16: Layer 4 Source Port Number 3 */
-#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS3_L4SP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16) /* Bits 16-32: Layer 4 Destination Port Number 3 */
-#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)
+#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xffff << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)
#define EMAC_MAC_LAYER4_ADDRESS3_L4DP3(n) (((n) << EMAC_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT) & EMAC_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
/* MAC Layer 3 Address 0 Reg 3 (MAC_LAYER3_ADDR0_REG3) */
#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0) /* Bits 0-32: Layer 3 Address 0 */
-#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)
#define EMAC_MAC_LAYER3_ADDR0_REG3_L3A03(n) (((n) << EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT) & EMAC_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
/* MAC Layer 3 Address 1 Reg 3 (MAC_LAYER3_ADDR1_REG3) */
#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0) /* Bits 0-32: Layer 3 Address 1 */
-#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)
#define EMAC_MAC_LAYER3_ADDR1_REG3_L3A13(n) (((n) << EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT) & EMAC_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
/* MAC Layer 3 Address 2 Reg 3 (MAC_LAYER3_ADDR2_REG3) */
#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0) /* Bits 0-32: Layer 3 Address 2 */
-#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)
#define EMAC_MAC_LAYER3_ADDR2_REG3_L3A23(n) (((n) << EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT) & EMAC_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
/* MAC Layer 3 Address 3 Reg 3 (MAC_LAYER3_ADDR3_REG3) */
#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0) /* Bits 0-32: Layer 3 Address 3 */
-#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFF << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)
+#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xffffffff << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)
#define EMAC_MAC_LAYER3_ADDR3_REG3_L3A33(n) (((n) << EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT) & EMAC_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
/* MAC Timestamp Control (MAC_TIMESTAMP_CONTROL) */
@@ -1865,36 +1865,36 @@
/* MAC Sub Second Increment (MAC_SUB_SECOND_INCREMENT) */
#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8) /* Bits 8-16: Sub-Nanosecond Increment Value */
-#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)
+#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xff << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)
#define EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16) /* Bits 16-24: Sub-Second Increment Value */
-#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)
+#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xff << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)
#define EMAC_MAC_SUB_SECOND_INCREMENT_SSINC(n) (((n) << EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT) & EMAC_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
/* MAC System Time In Seconds (MAC_SYSTEM_TIME_SECONDS) */
#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0) /* Bits 0-32: Timestamp Second */
-#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)
+#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xffffffff << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)
#define EMAC_MAC_SYSTEM_TIME_SECONDS_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
/* MAC System Time In Nanoseconds (MAC_SYSTEM_TIME_NANOSECONDS) */
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Sub Seconds */
-#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)
+#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7fffffff << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
/* MAC System Time Seconds Update (MAC_SYSTEM_TIME_SECONDS_UPDATE) */
#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0) /* Bits 0-32: Timestamp Seconds */
-#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFF << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)
+#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xffffffff << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)
#define EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
/* MAC System Time Nanoseconds Update (MAC_SYSTEM_TIME_NANOSECONDS_UPDATE) */
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0) /* Bits 0-31: Timestamp Subseconds */
-#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFF << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)
+#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7fffffff << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(n) (((n) << EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT) & EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
#define EMAC_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB (1 << 31) /* Bit 31: Add Or Subtract Time */
/* MAC Timestamp Addend (MAC_TIMESTAMP_ADDEND) */
#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0) /* Bits 0-32: Timestamp Addend Register */
-#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)
+#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)
#define EMAC_MAC_TIMESTAMP_ADDEND_TSAR(n) (((n) << EMAC_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT) & EMAC_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
/* MAC System Time Higher Word In Seconds
@@ -1902,7 +1902,7 @@
*/
#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0) /* Bits 0-16: Timestamp Higher Word Register */
-#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFF << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)
+#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xffff << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)
#define EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(n) (((n) << EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT) & EMAC_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
/* MAC Timestamp Status (MAC_TIMESTAMP_STATUS) */
@@ -1922,7 +1922,7 @@
*/
#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0) /* Bits 0-31: Transmit Timestamp Status Low */
-#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)
+#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7fffffff << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)
#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
#define EMAC_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS (1 << 31) /* Bit 31: Transmit Timestamp Status Missed */
@@ -1931,7 +1931,7 @@
*/
#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0) /* Bits 0-32: Transmit Timestamp Status High */
-#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFF << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)
+#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xffffffff << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)
#define EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(n) (((n) << EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT) & EMAC_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
/* MAC Timestamp Ingress Asymmetry Correction
@@ -1939,7 +1939,7 @@
*/
#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Ingress Asymmetry Correction */
-#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)
+#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)
#define EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
/* MAC Timestamp Egress Asymmetry Correction
@@ -1947,7 +1947,7 @@
*/
#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0) /* Bits 0-32: One-Step Timestamp Egress Asymmetry Correction */
-#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)
+#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)
#define EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
/* MAC Timestamp Ingress Correction In Nanoseconds
@@ -1955,7 +1955,7 @@
*/
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0) /* Bits 0-32: Timestamp Ingress Correction */
-#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)
+#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
/* MAC Timestamp Egress Correction In Nanoseconds
@@ -1963,7 +1963,7 @@
*/
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0) /* Bits 0-32: Timestamp Egress Correction */
-#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)
+#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xffffffff << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
/* MAC Timestamp Ingress Correction In Subnanoseconds
@@ -1971,7 +1971,7 @@
*/
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8) /* Bits 8-16: Timestamp Ingress Correction In Sub-Nanoseconds */
-#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)
+#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)
#define EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
/* MAC Timestamp Engress Correction In Subnanoseconds
@@ -1979,28 +1979,28 @@
*/
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8) /* Bits 8-16: Timestamp Egress Correction In Sub-Nanoseconds */
-#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)
+#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)
#define EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
/* MAC Timestamp Ingress Latency (MAC_TIMESTAMP_INGRESS_LATENCY) */
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8) /* Bits 8-16: Ingress Timestamp Latency In Nanoseconds */
-#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)
+#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16) /* Bits 16-28: Ingress Timestamp Latency In Sub-Nanoseconds */
-#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)
+#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xfff << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)
#define EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(n) (((n) << EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT) & EMAC_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
/* MAC Timestamp Egress Latecy (MAC_TIMESTAMP_EGRESS_LATENCY) */
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8) /* Bits 8-16: Egress Timestamp Latency In Sub-Nanoseconds */
-#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)
+#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xff << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16) /* Bits 16-28: Egress Timestamp Latency In Nanoseconds */
-#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)
+#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xfff << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)
#define EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(n) (((n) << EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT) & EMAC_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
/* MAC PPS Control (MAC_PPS_CONTROL) */
#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0) /* Bits 0-4: PPS Output Frequency Control */
-#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)
+#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)
#define EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
#define EMAC_MAC_PPS_CONTROL_PPSEN0 (1 << 4) /* Bit 4: Flexible PPS Output Mode Enable 0 */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5) /* Bits 5-7: Target Time Register Mode For PPS0 Output */
@@ -2008,21 +2008,21 @@
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL0(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN0 (1 << 7) /* Bit 7: MCGR Mode Enable For PPS0 Output */
#define EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8) /* Bits 8-12: Flexible PPS1 Output Control */
-#define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT)
+#define EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT)
#define EMAC_MAC_PPS_CONTROL_PPSCMD1(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD1_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD1_MASK)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13) /* Bits 13-15: Target Time Register Mode For PPS1 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL1(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN1 (1 << 15) /* Bit 15: MCGR Mode Enable For PPS1 Output */
#define EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16) /* Bits 16-20: Flexible PPS2 Output Control */
-#define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT)
+#define EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT)
#define EMAC_MAC_PPS_CONTROL_PPSCMD2(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD2_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD2_MASK)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21) /* Bits 21-23: Target Time Register Mode For PPS2 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL2(n) (((n) << EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT) & EMAC_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
#define EMAC_MAC_PPS_CONTROL_MCGREN2 (1 << 23) /* Bit 23: MCGR Mode Enable For PPS2 Output */
#define EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24) /* Bits 24-28: Flexible PPS3 Output Control */
-#define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT)
+#define EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK (0xf << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT)
#define EMAC_MAC_PPS_CONTROL_PPSCMD3(n) (((n) << EMAC_MAC_PPS_CONTROL_PPSCMD3_SHIFT) & EMAC_MAC_PPS_CONTROL_PPSCMD3_MASK)
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29) /* Bits 29-31: Target Time Register Mode For PPS3 Output */
#define EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x3 << EMAC_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)
@@ -2031,86 +2031,86 @@
/* MAC PPS0 Target Time In Seconds (MAC_PPS0_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds Register */
-#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)
+#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xffffffff << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)
#define EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
/* MAC PPS0 Target Time In Nanoseconds (MAC_PPS0_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0) /* Bits 0-31: Target Time Low For PPS0 */
-#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFF << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)
+#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7fffffff << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)
#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(n) (((n) << EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT) & EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
#define EMAC_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0 (1 << 31) /* Bit 31: PPS Target Time Busy Status 0 */
/* MAC PPS0 Interval (MAC_PPS0_INTERVAL) */
#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 0 */
-#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)
+#define EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xffffffff << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)
#define EMAC_MAC_PPS0_INTERVAL_PPSINT0(n) (((n) << EMAC_MAC_PPS0_INTERVAL_PPSINT0_SHIFT) & EMAC_MAC_PPS0_INTERVAL_PPSINT0_MASK)
/* MAC PPS0 Width (MAC_PPS0_WIDTH) */
#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 0 */
-#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFF << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)
+#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xffffffff << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)
#define EMAC_MAC_PPS0_WIDTH_PPSWIDTH0(n) (((n) << EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT) & EMAC_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
/* MAC PPS1 Target Time In Seconds (MAC_PPS1_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 1 */
-#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)
+#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xffffffff << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)
#define EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
/* MAC PPS1 Target Time In Nanoseconds (MAC_PPS1_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0) /* Bits 0-31: Target Time Low For PPS1 */
-#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFF << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)
+#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7fffffff << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)
#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(n) (((n) << EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT) & EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
#define EMAC_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1 (1 << 31) /* Bit 31: PPS Target Time Busy Status 1 */
/* MAC PPS1 Interval (MAC_PPS1_INTERVAL) */
#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 1 */
-#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)
+#define EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xffffffff << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)
#define EMAC_MAC_PPS1_INTERVAL_PPSINT1(n) (((n) << EMAC_MAC_PPS1_INTERVAL_PPSINT1_SHIFT) & EMAC_MAC_PPS1_INTERVAL_PPSINT1_MASK)
/* MAC PPS1 Width (MAC_PPS1_WIDTH) */
#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 1 */
-#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFF << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)
+#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xffffffff << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)
#define EMAC_MAC_PPS1_WIDTH_PPSWIDTH1(n) (((n) << EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT) & EMAC_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
/* MAC PPS2 Taget Time In Seconds (MAC_PPS2_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 2 */
-#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)
+#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xffffffff << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)
#define EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
/* MAC PPS2 Target Time In Nanoseconds (MAC_PPS2_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0) /* Bits 0-31: Target Time Low For PPS2 */
-#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFF << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)
+#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7fffffff << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)
#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(n) (((n) << EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT) & EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
#define EMAC_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2 (1 << 31) /* Bit 31: PPS Target Time Busy Status 2 */
/* MAC PPS2 Interval (MAC_PPS2_INTERVAL) */
#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval 2 */
-#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)
+#define EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xffffffff << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)
#define EMAC_MAC_PPS2_INTERVAL_PPSINT2(n) (((n) << EMAC_MAC_PPS2_INTERVAL_PPSINT2_SHIFT) & EMAC_MAC_PPS2_INTERVAL_PPSINT2_MASK)
/* MAC PPS2 Width (MAC_PPS2_WIDTH) */
#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 2 */
-#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFF << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)
+#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xffffffff << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)
#define EMAC_MAC_PPS2_WIDTH_PPSWIDTH2(n) (((n) << EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT) & EMAC_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
/* MAC PPS3 Target Time In Seconds (MAC_PPS3_TARGET_TIME_SECONDS) */
#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0) /* Bits 0-32: PPS Target Time In Seconds 3 */
-#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)
+#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xffffffff << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)
#define EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
/* MAC PPS3 Target Time In Nanoseconds (MAC_PPS3_TARGET_TIME_NANOSECONDS) */
#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0) /* Bits 0-31: Target Time Low For PPS3 */
-#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFF << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)
+#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7fffffff << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)
#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(n) (((n) << EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT) & EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
#define EMAC_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3 (1 << 31) /* Bit 31: PPS Target Time Register Busy 3 */
/* MAC PPS3 Interval (MAC_PPS3_INTERVAL) */
#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0) /* Bits 0-32: PPS Output Signal Interval */
-#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)
+#define EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xffffffff << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)
#define EMAC_MAC_PPS3_INTERVAL_PPSINT3(n) (((n) << EMAC_MAC_PPS3_INTERVAL_PPSINT3_SHIFT) & EMAC_MAC_PPS3_INTERVAL_PPSINT3_MASK)
/* MAC PPS3 Width (MAC_PPS3_WIDTH) */
#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0) /* Bits 0-32: PPS Output Signal Width 3 */
-#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFF << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)
+#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xffffffff << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)
#define EMAC_MAC_PPS3_WIDTH_PPSWIDTH3(n) (((n) << EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT) & EMAC_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
/* MTL Operation Mode (MTL_OPERATION_MODE) */
@@ -2161,12 +2161,12 @@
#define EMAC_MTL_DBG_STS_PKTI (1 << 8) /* Bit 8: Receive Packet Available Interrupt Status */
#define EMAC_MTL_DBG_STS_STSI (1 << 9) /* Bit 9: Transmit Status Available Interrupt Status */
#define EMAC_MTL_DBG_STS_LOCR_SHIFT (15) /* Bits 15-32: Remaining Locations In FIFO */
-#define EMAC_MTL_DBG_STS_LOCR_MASK (0x1FFFF << EMAC_MTL_DBG_STS_LOCR_SHIFT)
+#define EMAC_MTL_DBG_STS_LOCR_MASK (0x1fFFF << EMAC_MTL_DBG_STS_LOCR_SHIFT)
#define EMAC_MTL_DBG_STS_LOCR(n) (((n) << EMAC_MTL_DBG_STS_LOCR_SHIFT) & EMAC_MTL_DBG_STS_LOCR_MASK)
/* MTL FIFO Debug Data (MTL_FIFO_DEBUG_DATA) */
#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0) /* Bits 0-32: FIFO Debug Data */
-#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFF << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)
+#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xffffffff << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)
#define EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA(n) (((n) << EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT) & EMAC_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
/* MTL Interrupt Status (MTL_INTERRUPT_STATUS) */
@@ -2189,7 +2189,7 @@
#define EMAC_MTL_TBS_CTRL_LEGOS_MASK (0x7 << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT)
#define EMAC_MTL_TBS_CTRL_LEGOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEGOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEGOS_MASK)
#define EMAC_MTL_TBS_CTRL_LEOS_SHIFT (8) /* Bits 8-32: Launch Expiry Offset */
-#define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF << EMAC_MTL_TBS_CTRL_LEOS_SHIFT)
+#define EMAC_MTL_TBS_CTRL_LEOS_MASK (0xffffff << EMAC_MTL_TBS_CTRL_LEOS_SHIFT)
#define EMAC_MTL_TBS_CTRL_LEOS(n) (((n) << EMAC_MTL_TBS_CTRL_LEOS_SHIFT) & EMAC_MTL_TBS_CTRL_LEOS_MASK)
/* MTL EST Control (MTL_EST_CONTROL) */
@@ -2204,10 +2204,10 @@
#define EMAC_MTL_EST_CONTROL_TILS_MASK (0x7 << EMAC_MTL_EST_CONTROL_TILS_SHIFT)
#define EMAC_MTL_EST_CONTROL_TILS(n) (((n) << EMAC_MTL_EST_CONTROL_TILS_SHIFT) & EMAC_MTL_EST_CONTROL_TILS_MASK)
#define EMAC_MTL_EST_CONTROL_CTOV_SHIFT (12) /* Bits 12-24: Current Time Offset Value */
-#define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xFFF << EMAC_MTL_EST_CONTROL_CTOV_SHIFT)
+#define EMAC_MTL_EST_CONTROL_CTOV_MASK (0xfff << EMAC_MTL_EST_CONTROL_CTOV_SHIFT)
#define EMAC_MTL_EST_CONTROL_CTOV(n) (((n) << EMAC_MTL_EST_CONTROL_CTOV_SHIFT) & EMAC_MTL_EST_CONTROL_CTOV_MASK)
#define EMAC_MTL_EST_CONTROL_PTOV_SHIFT (24) /* Bits 24-32: PTP Time Offset Value */
-#define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xFF << EMAC_MTL_EST_CONTROL_PTOV_SHIFT)
+#define EMAC_MTL_EST_CONTROL_PTOV_MASK (0xff << EMAC_MTL_EST_CONTROL_PTOV_SHIFT)
#define EMAC_MTL_EST_CONTROL_PTOV(n) (((n) << EMAC_MTL_EST_CONTROL_PTOV_SHIFT) & EMAC_MTL_EST_CONTROL_PTOV_MASK)
/* MTL EST Status (MTL_EST_STATUS) */
@@ -2218,10 +2218,10 @@
#define EMAC_MTL_EST_STATUS_CGCE (1 << 4) /* Bit 4: Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the Cycle Time (CTR) is less than or equal to the programmed Time Interval (TI) value after the optional Left Shifting */
#define EMAC_MTL_EST_STATUS_SWOL (1 << 7) /* Bit 7: S/W owned list When '0' indicates Gate control list number "0" is owned by software and when "1" indicates the Gate Control list "1" is owned by the software */
#define EMAC_MTL_EST_STATUS_BTRL_SHIFT (8) /* Bits 8-12: BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + ((n) * New Cycle Time) becomes true */
-#define EMAC_MTL_EST_STATUS_BTRL_MASK (0xF << EMAC_MTL_EST_STATUS_BTRL_SHIFT)
+#define EMAC_MTL_EST_STATUS_BTRL_MASK (0xf << EMAC_MTL_EST_STATUS_BTRL_SHIFT)
#define EMAC_MTL_EST_STATUS_BTRL(n) (((n) << EMAC_MTL_EST_STATUS_BTRL_SHIFT) & EMAC_MTL_EST_STATUS_BTRL_MASK)
#define EMAC_MTL_EST_STATUS_CGSN_SHIFT (16) /* Bits 16-20: Current GCL Slot Number Indicates the slot number of the GCL list */
-#define EMAC_MTL_EST_STATUS_CGSN_MASK (0xF << EMAC_MTL_EST_STATUS_CGSN_SHIFT)
+#define EMAC_MTL_EST_STATUS_CGSN_MASK (0xf << EMAC_MTL_EST_STATUS_CGSN_SHIFT)
#define EMAC_MTL_EST_STATUS_CGSN(n) (((n) << EMAC_MTL_EST_STATUS_CGSN_SHIFT) & EMAC_MTL_EST_STATUS_CGSN_MASK)
/* MTL EST Scheduling Error (MTL_EST_SCH_ERROR) */
@@ -2236,7 +2236,7 @@
/* MTL EST Frame Size Capture (MTL_EST_FRM_SIZE_CAPTURE) */
#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0) /* Bits 0-15: Frame Size of HLBF */
-#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFF << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)
+#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7ffF << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)
#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS(n) (((n) << EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT) & EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
#define EMAC_MTL_EST_FRM_SIZE_CAPTURE_HBFQ (1 << 16) /* Bit 16: Queue Number of HLBF */
@@ -2254,7 +2254,7 @@
#define EMAC_MTL_EST_GCL_CONTROL_DBGM (1 << 4) /* Bit 4: Debug Mode */
#define EMAC_MTL_EST_GCL_CONTROL_DBGB (1 << 5) /* Bit 5: Debug Mode Bank Select */
#define EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8) /* Bits 8-16: Gate Control List Address: (GCLA when GCRR is "0") */
-#define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xFF << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT)
+#define EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK (0xff << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT)
#define EMAC_MTL_EST_GCL_CONTROL_ADDR(n) (((n) << EMAC_MTL_EST_GCL_CONTROL_ADDR_SHIFT) & EMAC_MTL_EST_GCL_CONTROL_ADDR_MASK)
#define EMAC_MTL_EST_GCL_CONTROL_ERR0 (1 << 20) /* Bit 20: If this field is 1, it indicates that when the software writes to GCL the last write operation was aborted and when MTL_EST_Control[SSWL] is 1, GCL registers are prohibited */
#define EMAC_MTL_EST_GCL_CONTROL_ESTEIEE (1 << 21) /* Bit 21: EST ECC Inject Error Enable */
@@ -2264,7 +2264,7 @@
/* MTL EST GCL Data (MTL_EST_GCL_DATA) */
#define EMAC_MTL_EST_GCL_DATA_GCD_SHIFT (0) /* Bits 0-32: Gate Control Data */
-#define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFF << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT)
+#define EMAC_MTL_EST_GCL_DATA_GCD_MASK (0xffffffff << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT)
#define EMAC_MTL_EST_GCL_DATA_GCD(n) (((n) << EMAC_MTL_EST_GCL_DATA_GCD_SHIFT) & EMAC_MTL_EST_GCL_DATA_GCD_MASK)
/* MTL FPE Control Status (MTL_FPE_CTRL_STS) */
@@ -2278,19 +2278,19 @@
/* MTL FPE Advance (MTL_FPE_ADVANCE) */
#define EMAC_MTL_FPE_ADVANCE_HADV_SHIFT (0) /* Bits 0-16: Hold Advance */
-#define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT)
+#define EMAC_MTL_FPE_ADVANCE_HADV_MASK (0xffff << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT)
#define EMAC_MTL_FPE_ADVANCE_HADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_HADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_HADV_MASK)
#define EMAC_MTL_FPE_ADVANCE_RADV_SHIFT (16) /* Bits 16-32: Release Advance */
-#define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT)
+#define EMAC_MTL_FPE_ADVANCE_RADV_MASK (0xffff << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT)
#define EMAC_MTL_FPE_ADVANCE_RADV(n) (((n) << EMAC_MTL_FPE_ADVANCE_RADV_SHIFT) & EMAC_MTL_FPE_ADVANCE_RADV_MASK)
/* MTL Rx Parser Control Status (MTL_RXP_CONTROL_STATUS) */
#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0) /* Bits 0-6: Number Of Valid Entry Address Or Index In The Instruction Table */
-#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)
+#define EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK (0x3f << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)
#define EMAC_MTL_RXP_CONTROL_STATUS_NVE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NVE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NVE_MASK)
#define EMAC_MTL_RXP_CONTROL_STATUS_MTL_SCS1 (1 << 15) /* Bit 15: MTL_SCS1 */
#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16) /* Bits 16-22: Number of parsable entries in the Instruction table */
-#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3F << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)
+#define EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK (0x3f << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)
#define EMAC_MTL_RXP_CONTROL_STATUS_NPE(n) (((n) << EMAC_MTL_RXP_CONTROL_STATUS_NPE_SHIFT) & EMAC_MTL_RXP_CONTROL_STATUS_NPE_MASK)
#define EMAC_MTL_RXP_CONTROL_STATUS_RXPI (1 << 31) /* Bit 31: RX Parser in Idle State */
@@ -2309,13 +2309,13 @@
/* MTL Rx Parser Drop Count (MTL_RXP_DROP_CNT) */
#define EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0) /* Bits 0-31: Rx Parser Drop Count */
-#define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT)
+#define EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7fffffff << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT)
#define EMAC_MTL_RXP_DROP_CNT_RXPDC(n) (((n) << EMAC_MTL_RXP_DROP_CNT_RXPDC_SHIFT) & EMAC_MTL_RXP_DROP_CNT_RXPDC_MASK)
#define EMAC_MTL_RXP_DROP_CNT_RXPDCOVF (1 << 31) /* Bit 31: Rx Parser Drop Counter Overflow Bit */
/* MTL Rx Parser Error Count (MTL_RXP_ERROR_CNT) */
#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0) /* Bits 0-31: Rx Parser Error Count */
-#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFF << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)
+#define EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7fffffff << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)
#define EMAC_MTL_RXP_ERROR_CNT_RXPEC(n) (((n) << EMAC_MTL_RXP_ERROR_CNT_RXPEC_SHIFT) & EMAC_MTL_RXP_ERROR_CNT_RXPEC_MASK)
#define EMAC_MTL_RXP_ERROR_CNT_RXPECOVF (1 << 31) /* Bit 31: Rx Parser Error Counter Overflow Bit */
@@ -2324,7 +2324,7 @@
*/
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0) /* Bits 0-8: FRP Instruction Table Offset Address */
-#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xFF << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)
+#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0xff << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN (1 << 16) /* Bit 16: Read Write Control */
#define EMAC_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_RXPEIEE (1 << 20) /* Bit 20: ECC Inject Error Enable for Rx Parser Memory */
@@ -2335,7 +2335,7 @@
/* MTL Rx Parser Indirect Access Data (MTL_RXP_INDIRECT_ACC_DATA) */
#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0) /* Bits 0-32: FRP Instruction Table Write/Read Data */
-#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFF << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)
+#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xffffffff << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)
#define EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA(n) (((n) << EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT) & EMAC_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
/* MTL ECC Control (MTL_ECC_CONTROL) */
@@ -2379,18 +2379,18 @@
/* MTL ECC Error Adress Status (MTL_ECC_ERR_ADDR_STATUS) */
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT (0) /* Bits 0-16: MTL ECC Correctable Error Address Status */
-#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT)
+#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK (0xffff << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT)
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_ECEAS_MASK)
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT (16) /* Bits 16-32: MTL ECC Uncorrectable Error Address Status */
-#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xFFFF << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT)
+#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK (0xffff << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT)
#define EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS(n) (((n) << EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_SHIFT) & EMAC_MTL_ECC_ERR_ADDR_STATUS_EUEAS_MASK)
/* MTL ECC Error Control Status (MTL_ECC_ERR_CNTR_STATUS) */
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT (0) /* Bits 0-8: MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's correctable error count value */
-#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xFF << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT)
+#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK (0xff << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT)
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_ECECS_MASK)
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT (16) /* Bits 16-20: MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register, this field holds the respective memory's uncorrectable error count value */
-#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xF << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT)
+#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK (0xf << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT)
#define EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS(n) (((n) << EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_SHIFT) & EMAC_MTL_ECC_ERR_CNTR_STATUS_EUECS_MASK)
/* MTL DPP Control (MTL_DPP_CONTROL) */
@@ -2417,12 +2417,12 @@
#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TTC_MASK)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */
-#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT)
+#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK (0x1f << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT)
#define EMAC_MTL_TXQ0_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ0_OPERATION_MODE_TQS_MASK)
/* MTL Tx Queue 0 Underflow (MTL_TXQ0_UNDERFLOW) */
#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */
-#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT)
+#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK (0x7ff << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT)
#define EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ0_UNDERFLOW_UFFRMCNT_MASK)
#define EMAC_MTL_TXQ0_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */
@@ -2443,12 +2443,12 @@
/* MTL Tx Queue 0 ETS Status (MTL_TXQ0_ETS_STATUS) */
#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */
-#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT)
+#define EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK (0xffffff << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT)
#define EMAC_MTL_TXQ0_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ0_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ0_ETS_STATUS_ABS_MASK)
/* MTL Tx Queue Quantum Weight (MTL_TXQ0_QUANTUM_WEIGHT) */
#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: Quantum or Weights */
-#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT)
+#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK (0x1fffff << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT)
#define EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ0_QUANTUM_WEIGHT_ISCQW_MASK)
/* MTL Queue 0 Interrupt Control Status (MTL_Q0_INTERRUPT_CONTROL_STATUS) */
@@ -2469,13 +2469,13 @@
#define EMAC_MTL_RXQ0_OPERATION_MODE_DIS_TCP_EF (1 << 6) /* Bit 6: Disable Dropping of TCP/IP Checksum Error Packets */
#define EMAC_MTL_RXQ0_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex) */
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK (0xf << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFA_MASK)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK (0xf << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RFD_MASK)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */
-#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT)
+#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK (0x1f << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT)
#define EMAC_MTL_RXQ0_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ0_OPERATION_MODE_RQS_MASK)
/* MTL Rx Queue Missed Packet Overflow Count
@@ -2483,11 +2483,11 @@
*/
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */
-#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)
+#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK)
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */
-#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)
+#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK)
#define EMAC_MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */
@@ -2500,7 +2500,7 @@
#define EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT)
#define EMAC_MTL_RXQ0_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ0_DEBUG_RXQSTS_MASK)
#define EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */
-#define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT)
+#define EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK (0x3fff << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT)
#define EMAC_MTL_RXQ0_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ0_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ0_DEBUG_PRXQ_MASK)
/* MTL Rx Queue 0 Control 0 (MTL_RXQ0_CONTROL) */
@@ -2519,12 +2519,12 @@
#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK (0x7 << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT)
#define EMAC_MTL_TXQ1_OPERATION_MODE_TTC(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TTC_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TTC_MASK)
#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT (16) /* Bits 16-21: Transmit Queue Size */
-#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1F << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT)
+#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK (0x1f << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT)
#define EMAC_MTL_TXQ1_OPERATION_MODE_TQS(n) (((n) << EMAC_MTL_TXQ1_OPERATION_MODE_TQS_SHIFT) & EMAC_MTL_TXQ1_OPERATION_MODE_TQS_MASK)
/* MTL Tx Queue 1 Underflow (MTL_TXQ1_UNDERFLOW) */
#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT (0) /* Bits 0-11: Underflow Packet Counter */
-#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7FF << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT)
+#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK (0x7ff << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT)
#define EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT(n) (((n) << EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_SHIFT) & EMAC_MTL_TXQ1_UNDERFLOW_UFFRMCNT_MASK)
#define EMAC_MTL_TXQ1_UNDERFLOW_UFCNTOVF (1 << 11) /* Bit 11: Overflow Bit for Underflow Packet Counter */
@@ -2552,27 +2552,27 @@
/* MTL Tx Queue 1 ETS Status (MTL_TXQ1_ETS_STATUS) */
#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT (0) /* Bits 0-24: Average Bits per Slot */
-#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xFFFFFF << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT)
+#define EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK (0xffffff << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT)
#define EMAC_MTL_TXQ1_ETS_STATUS_ABS(n) (((n) << EMAC_MTL_TXQ1_ETS_STATUS_ABS_SHIFT) & EMAC_MTL_TXQ1_ETS_STATUS_ABS_MASK)
/* MTL Tx Queue 1 Quantum Weight (MTL_TXQ1_QUANTUM_WEIGHT) */
#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT (0) /* Bits 0-21: idleSlopeCredit, Quantum or Weights */
-#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1FFFFF << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT)
+#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK (0x1fffff << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT)
#define EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW(n) (((n) << EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_SHIFT) & EMAC_MTL_TXQ1_QUANTUM_WEIGHT_ISCQW_MASK)
/* MTL Tx Queue 1 Sendslope Credit (MTL_TXQ1_SENDSLOPECREDIT) */
#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT (0) /* Bits 0-14: sendSlopeCredit Value */
-#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3FFF << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT)
+#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK (0x3fff << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT)
#define EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC(n) (((n) << EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_SHIFT) & EMAC_MTL_TXQ1_SENDSLOPECREDIT_SSC_MASK)
/* MTL Tx Queue 1 HiCredit (MTL_TXQ1_HICREDIT) */
#define EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT (0) /* Bits 0-29: hiCredit Value */
-#define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT)
+#define EMAC_MTL_TXQ1_HICREDIT_HC_MASK (0x1fffffff << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT)
#define EMAC_MTL_TXQ1_HICREDIT_HC(n) (((n) << EMAC_MTL_TXQ1_HICREDIT_HC_SHIFT) & EMAC_MTL_TXQ1_HICREDIT_HC_MASK)
/* MTL Tx Queue 1 LoCredit (MTL_TXQ1_LOCREDIT) */
#define EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT (0) /* Bits 0-29: loCredit Value */
-#define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1FFFFFFF << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT)
+#define EMAC_MTL_TXQ1_LOCREDIT_LC_MASK (0x1fffffff << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT)
#define EMAC_MTL_TXQ1_LOCREDIT_LC(n) (((n) << EMAC_MTL_TXQ1_LOCREDIT_LC_SHIFT) & EMAC_MTL_TXQ1_LOCREDIT_LC_MASK)
/* MTL Queue 1 Interrupt Control Status (MTL_Q1_INTERRUPT_CONTROL_STATUS) */
@@ -2593,13 +2593,13 @@
#define EMAC_MTL_RXQ1_OPERATION_MODE_DIS_TCP_EF (1 << 6) /* Bit 6: Disable Dropping of TCP or IP Checksum Error Packets */
#define EMAC_MTL_RXQ1_OPERATION_MODE_EHFC (1 << 7) /* Bit 7: Enable Hardware Flow Control */
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT (8) /* Bits 8-12: Threshold for Activating Flow Control (in half-duplex and full-duplex */
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK (0xf << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFA(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFA_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFA_MASK)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT (14) /* Bits 14-18: Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0xF << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK (0xf << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RFD(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RFD_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RFD_MASK)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT (20) /* Bits 20-25: Receive Queue Size */
-#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1F << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT)
+#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK (0x1f << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT)
#define EMAC_MTL_RXQ1_OPERATION_MODE_RQS(n) (((n) << EMAC_MTL_RXQ1_OPERATION_MODE_RQS_SHIFT) & EMAC_MTL_RXQ1_OPERATION_MODE_RQS_MASK)
/* MTL Rx Queue 1 Missed Packet Overflow Counter
@@ -2607,11 +2607,11 @@
*/
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT (0) /* Bits 0-11: Overflow Packet Counter */
-#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)
+#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT)
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFPKTCNT_MASK)
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_OVFCNTOVF (1 << 11) /* Bit 11: Overflow Counter Overflow Bit */
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT (16) /* Bits 16-27: Missed Packet Counter */
-#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7FF << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)
+#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK (0x7ff << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT)
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT(n) (((n) << EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_SHIFT) & EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISPKTCNT_MASK)
#define EMAC_MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT_MISCNTOVF (1 << 27) /* Bit 27: Missed Packet Counter Overflow Bit */
@@ -2624,7 +2624,7 @@
#define EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK (0x3 << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT)
#define EMAC_MTL_RXQ1_DEBUG_RXQSTS(n) (((n) << EMAC_MTL_RXQ1_DEBUG_RXQSTS_SHIFT) & EMAC_MTL_RXQ1_DEBUG_RXQSTS_MASK)
#define EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT (16) /* Bits 16-30: Number of Packets in Receive Queue */
-#define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3FFF << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT)
+#define EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK (0x3fff << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT)
#define EMAC_MTL_RXQ1_DEBUG_PRXQ(n) (((n) << EMAC_MTL_RXQ1_DEBUG_PRXQ_SHIFT) & EMAC_MTL_RXQ1_DEBUG_PRXQ_MASK)
/* MTL Rx Queue 1 Control (MTL_RXQ1_CONTROL) */
@@ -2663,16 +2663,16 @@
/* DMA Debug Status 0 (DMA_DEBUG_STATUS0) */
#define EMAC_DMA_DEBUG_STATUS0_AXWHSTS (1 << 0) /* Bit 0: AHB Master Status */
#define EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT (8) /* Bits 8-12: DMA Channel 0 Receive Process State */
-#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT)
+#define EMAC_DMA_DEBUG_STATUS0_RPS0_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT)
#define EMAC_DMA_DEBUG_STATUS0_RPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS0_MASK)
#define EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT (12) /* Bits 12-16: DMA Channel 0 Transmit Process State */
-#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT)
+#define EMAC_DMA_DEBUG_STATUS0_TPS0_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT)
#define EMAC_DMA_DEBUG_STATUS0_TPS0(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS0_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS0_MASK)
#define EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT (16) /* Bits 16-20: DMA Channel 1 Receive Process State */
-#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT)
+#define EMAC_DMA_DEBUG_STATUS0_RPS1_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT)
#define EMAC_DMA_DEBUG_STATUS0_RPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_RPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_RPS1_MASK)
#define EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT (20) /* Bits 20-24: DMA Channel 1 Transmit Process State */
-#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xF << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT)
+#define EMAC_DMA_DEBUG_STATUS0_TPS1_MASK (0xf << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT)
#define EMAC_DMA_DEBUG_STATUS0_TPS1(n) (((n) << EMAC_DMA_DEBUG_STATUS0_TPS1_SHIFT) & EMAC_DMA_DEBUG_STATUS0_TPS1_MASK)
/* DMA TBS Control (DMA_TBS_CTRL) */
@@ -2681,7 +2681,7 @@
#define EMAC_DMA_TBS_CTRL_FGOS_MASK (0x7 << EMAC_DMA_TBS_CTRL_FGOS_SHIFT)
#define EMAC_DMA_TBS_CTRL_FGOS(n) (((n) << EMAC_DMA_TBS_CTRL_FGOS_SHIFT) & EMAC_DMA_TBS_CTRL_FGOS_MASK)
#define EMAC_DMA_TBS_CTRL_FTOS_SHIFT (8) /* Bits 8-32: Fetch Time Offset */
-#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF << EMAC_DMA_TBS_CTRL_FTOS_SHIFT)
+#define EMAC_DMA_TBS_CTRL_FTOS_MASK (0xffffff << EMAC_DMA_TBS_CTRL_FTOS_SHIFT)
#define EMAC_DMA_TBS_CTRL_FTOS(n) (((n) << EMAC_DMA_TBS_CTRL_FTOS_SHIFT) & EMAC_DMA_TBS_CTRL_FTOS_MASK)
/* DMA Safety Interrupt Status (DMA_SAFETY_INTERRUPT_STATUS) */
@@ -2704,7 +2704,7 @@
#define EMAC_DMA_CH0_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TCW_MASK)
#define EMAC_DMA_CH0_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */
#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */
-#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT)
+#define EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK (0x3f << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT)
#define EMAC_DMA_CH0_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH0_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH0_TX_CONTROL_TXPBL_MASK)
#define EMAC_DMA_CH0_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */
#define EMAC_DMA_CH0_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */
@@ -2715,42 +2715,42 @@
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT)
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_X_0_MASK)
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */
-#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT)
+#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK (0xfff << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT)
#define EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RBSZ_13_Y_MASK)
#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */
-#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT)
+#define EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK (0x3f << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT)
#define EMAC_DMA_CH0_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH0_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH0_RX_CONTROL_RXPBL_MASK)
#define EMAC_DMA_CH0_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */
#define EMAC_DMA_CH0_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */
/* DMA Channel 0 Tx Descriptor List Address (DMA_CH0_TXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */
-#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)
+#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3fffffff << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)
#define EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH0_TXDESC_LIST_ADDRESS_TDESLA_MASK)
/* DMA Channel 0 Rx Descriptor List Address (DMA_CH0_RXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */
-#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)
+#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3fffffff << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)
#define EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH0_RXDESC_LIST_ADDRESS_RDESLA_MASK)
/* DMA Channel 0 Tx Descriptor Tail Pointer (DMA_CH0_TXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */
-#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT)
+#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK (0x3fffffff << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT)
#define EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH0_TXDESC_TAIL_POINTER_TDTP_MASK)
/* DMA Channeli 0 Rx Descriptor List Pointer (DMA_CH0_RXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */
-#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT)
+#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK (0x3fffffff << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT)
#define EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH0_RXDESC_TAIL_POINTER_RDTP_MASK)
/* DMA Channel 0 Tx Descriptor Ring Length (DMA_CH0_TXDESC_RING_LENGTH) */
#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */
-#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT)
+#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK (0x3ff << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT)
#define EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH0_TXDESC_RING_LENGTH_TDRL_MASK)
/* DMA Channel 0 Rx Descriptor Ring Length (DMA_CH0_RXDESC_RING_LENGTH) */
#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */
-#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT)
+#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK (0x3ff << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT)
#define EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH0_RXDESC_RING_LENGTH_RDRL_MASK)
/* DMA Channel 0 Interrupt Enable (DMA_CH0_INTERRUPT_ENABLE) */
@@ -2773,7 +2773,7 @@
*/
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */
-#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)
+#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xff << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */
#define EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)
@@ -2786,10 +2786,10 @@
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ESC (1 << 0) /* Bit 0: Enable Slot Comparison */
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */
-#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)
+#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xfff << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */
-#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)
+#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xf << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)
#define EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)
/* DMA Channel 0 Current Application Transmit Descriptor
@@ -2797,7 +2797,7 @@
*/
#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */
-#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)
+#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)
#define EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXDESC_CURTDESAPTR_MASK)
/* DMA Channel 0 Current Application Receive Descriptor
@@ -2805,7 +2805,7 @@
*/
#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */
-#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)
+#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)
#define EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXDESC_CURRDESAPTR_MASK)
/* DMA Channel 0 Current Application Transmit Descriptor
@@ -2813,7 +2813,7 @@
*/
#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */
-#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)
+#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)
#define EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK)
/* DMA Channel 0 Current Application Receive Buffer
@@ -2821,7 +2821,7 @@
*/
#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */
-#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)
+#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)
#define EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH0_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK)
/* DMA Channel 0 Status (DMA_CH0_STATUS) */
@@ -2847,19 +2847,19 @@
/* DMA Channel 0 Miss Frame Counter (DMA_CH0_MISS_FRAME_CNT) */
#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters Indicates the number of packet counters that DMA drops either because of bus error or because of programing RPF field in DMA_CH${i}_Rx_Control register */
-#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT)
+#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK (0x7ff << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT)
#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH0_MISS_FRAME_CNT_MFC_MASK)
#define EMAC_DMA_CH0_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */
/* DMA Channel 0 Rx Parser Accept Count (DMA_CH0_RXP_ACCEPT_CNT) */
#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */
-#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT)
+#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK (0x7fffffff << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT)
#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPAC_MASK)
#define EMAC_DMA_CH0_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */
/* DMA Channel 0 Rx ERI Count (DMA_CH0_RX_ERI_CNT) */
#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */
-#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT)
+#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK (0xfff << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT)
#define EMAC_DMA_CH0_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH0_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH0_RX_ERI_CNT_ECNT_MASK)
/* DMA Channel 1 Control (DMA_CH1_CONTROL) */
@@ -2875,7 +2875,7 @@
#define EMAC_DMA_CH1_TX_CONTROL_TCW(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TCW_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TCW_MASK)
#define EMAC_DMA_CH1_TX_CONTROL_OSF (1 << 4) /* Bit 4: Operate on Second Packet */
#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT (16) /* Bits 16-22: Transmit Programmable Burst Length */
-#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK (0x3F << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT)
+#define EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK (0x3f << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT)
#define EMAC_DMA_CH1_TX_CONTROL_TXPBL(n) (((n) << EMAC_DMA_CH1_TX_CONTROL_TXPBL_SHIFT) & EMAC_DMA_CH1_TX_CONTROL_TXPBL_MASK)
#define EMAC_DMA_CH1_TX_CONTROL_ETIC (1 << 22) /* Bit 22: Early Transmit Interrupt Control */
#define EMAC_DMA_CH1_TX_CONTROL_EDSE (1 << 28) /* Bit 28: Enhanced Descriptor Enable */
@@ -2886,42 +2886,42 @@
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK (0x3 << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT)
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_X_0_MASK)
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT (3) /* Bits 3-15: Receive Buffer size High */
-#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK (0xFFF << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT)
+#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK (0xfff << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT)
#define EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RBSZ_13_Y_MASK)
#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT (16) /* Bits 16-22: Receive Programmable Burst Length */
-#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK (0x3F << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT)
+#define EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK (0x3f << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT)
#define EMAC_DMA_CH1_RX_CONTROL_RXPBL(n) (((n) << EMAC_DMA_CH1_RX_CONTROL_RXPBL_SHIFT) & EMAC_DMA_CH1_RX_CONTROL_RXPBL_MASK)
#define EMAC_DMA_CH1_RX_CONTROL_ERIC (1 << 22) /* Bit 22: Early Receive Interrupt Control */
#define EMAC_DMA_CH1_RX_CONTROL_RPF (1 << 31) /* Bit 31: Rx Packet Flush */
/* DMA Channel 1 Tx Descriptor List Address (DMA_CH1_TXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT (2) /* Bits 2-32: Start of Transmit List */
-#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)
+#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK (0x3fffffff << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT)
#define EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA(n) (((n) << EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_SHIFT) & EMAC_DMA_CH1_TXDESC_LIST_ADDRESS_TDESLA_MASK)
/* DMA Channel 1 Rx Descriptor List Address (DMA_CH1_RXDESC_LIST_ADDRESS) */
#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT (2) /* Bits 2-32: Start of Receive List */
-#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)
+#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK (0x3fffffff << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT)
#define EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA(n) (((n) << EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_SHIFT) & EMAC_DMA_CH1_RXDESC_LIST_ADDRESS_RDESLA_MASK)
/* DMA Channel 1 Tx Descriptor Tail Pointer (DMA_CH1_TXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT (2) /* Bits 2-32: Transmit Descriptor Tail Pointer */
-#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT)
+#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK (0x3fffffff << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT)
#define EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP(n) (((n) << EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_SHIFT) & EMAC_DMA_CH1_TXDESC_TAIL_POINTER_TDTP_MASK)
/* DMA Channel 1 Rx Descriptor Tail Pointer (DMA_CH1_RXDESC_TAIL_POINTER) */
#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT (2) /* Bits 2-32: Receive Descriptor Tail Pointer */
-#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0x3FFFFFFF << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT)
+#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK (0x3fffffff << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT)
#define EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP(n) (((n) << EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_SHIFT) & EMAC_DMA_CH1_RXDESC_TAIL_POINTER_RDTP_MASK)
/* DMA Channel 1 Tx Descriptor Ring Length (DMA_CH1_TXDESC_RING_LENGTH) */
#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT (0) /* Bits 0-10: Transmit Descriptor Ring Length */
-#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3FF << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT)
+#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK (0x3ff << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT)
#define EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL(n) (((n) << EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_SHIFT) & EMAC_DMA_CH1_TXDESC_RING_LENGTH_TDRL_MASK)
/* DMA Channel 1 Rx Descriptor Ring Length (DMA_CH1_RXDESC_RING_LENGTH) */
#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT (0) /* Bits 0-10: Receive Descriptor Ring Length */
-#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3FF << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT)
+#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK (0x3ff << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT)
#define EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL(n) (((n) << EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_SHIFT) & EMAC_DMA_CH1_RXDESC_RING_LENGTH_RDRL_MASK)
/* DMA Channel 1 Interrupt Enable (DMA_CH1_INTERRUPT_ENABLE) */
@@ -2944,7 +2944,7 @@
*/
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT (0) /* Bits 0-8: Receive Interrupt Watchdog Timer Count */
-#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xFF << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)
+#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK (0xff << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT)
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT(n) (((n) << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_SHIFT) & EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWT_MASK)
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT (16) /* Bits 16-18: Receive Interrupt Watchdog Timer Count Units */
#define EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_MASK (0x3 << EMAC_DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER_RWTU_SHIFT)
@@ -2957,10 +2957,10 @@
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ESC (1 << 0) /* Bit 0: Enable Slot Comparison */
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_ASC (1 << 1) /* Bit 1: Advance Slot Check */
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT (4) /* Bits 4-16: Slot Interval Value */
-#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xFFF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)
+#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK (0xfff << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT)
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_SIV_MASK)
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT (16) /* Bits 16-20: Reference Slot Number */
-#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xF << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)
+#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK (0xf << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT)
#define EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN(n) (((n) << EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_SHIFT) & EMAC_DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS_RSN_MASK)
/* DMA Channel 1 Current Application Transmit Descriptor
@@ -2968,7 +2968,7 @@
*/
#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Descriptor Address Pointer */
-#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)
+#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT)
#define EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXDESC_CURTDESAPTR_MASK)
/* DMA Channel 1 Current Application Receive Descriptor
@@ -2976,7 +2976,7 @@
*/
#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT (0) /* Bits 0-32: Application Receive Descriptor Address Pointer */
-#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)
+#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT)
#define EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXDESC_CURRDESAPTR_MASK)
/* DMA Channel 1 Current Application Transmit Buffer
@@ -2984,7 +2984,7 @@
*/
#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT (0) /* Bits 0-32: Application Transmit Buffer Address Pointer */
-#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)
+#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT)
#define EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_TXBUFFER_CURTBUFAPTR_MASK)
/* DMA Channel 1 Current Application Receive Buffer
@@ -2992,7 +2992,7 @@
*/
#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT (0) /* Bits 0-32: Application Receive Buffer Address Pointer */
-#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xFFFFFFFF << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)
+#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK (0xffffffff << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT)
#define EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR(n) (((n) << EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_SHIFT) & EMAC_DMA_CH1_CURRENT_APP_RXBUFFER_CURRBUFAPTR_MASK)
/* DMA Channel 1 Status (DMA_CH1_STATUS) */
@@ -3018,54 +3018,54 @@
/* DMA Channel 1 Miss Frame Counter (DMA_CH1_MISS_FRAME_CNT) */
#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT (0) /* Bits 0-11: Dropped Packet Counters */
-#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7FF << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT)
+#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK (0x7ff << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT)
#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFC(n) (((n) << EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_SHIFT) & EMAC_DMA_CH1_MISS_FRAME_CNT_MFC_MASK)
#define EMAC_DMA_CH1_MISS_FRAME_CNT_MFCO (1 << 15) /* Bit 15: Overflow status of the MFC Counter */
/* DMA Channel 1 Rx Parser Accept Count (DMA_CH1_RXP_ACCEPT_CNT) */
#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT (0) /* Bits 0-31: Rx Parser Accept Counter */
-#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFF << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT)
+#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK (0x7fffffff << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT)
#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC(n) (((n) << EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_SHIFT) & EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPAC_MASK)
#define EMAC_DMA_CH1_RXP_ACCEPT_CNT_RXPACOF (1 << 31) /* Bit 31: Rx Parser Accept Counter Overflow Bit */
/* DMA Channel 1 Rx ERI Count (DMA_CH1_RX_ERI_CNT) */
#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT (0) /* Bits 0-12: ERI Counter */
-#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xFFF << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT)
+#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK (0xfff << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT)
#define EMAC_DMA_CH1_RX_ERI_CNT_ECNT(n) (((n) << EMAC_DMA_CH1_RX_ERI_CNT_ECNT_SHIFT) & EMAC_DMA_CH1_RX_ERI_CNT_ECNT_MASK)
#define EMAC_TDES3_CPC(x) (((uint32_t)(((uint32_t)(x)) << 26U)) & 0x0C000000U)
#define EMAC_TDES3_CIC(x) (((uint32_t)(((uint32_t)(x)) << 16U)) & 0x00030000U)
-#define EMAC_TDES3_OWN_MASK (0x80000000U)
-#define EMAC_TDES3_FD_MASK (0x20000000U)
-#define EMAC_TDES3_LD_MASK (0x10000000U)
-
-#define EMAC_TDES2_IOC_MASK (0x80000000U)
-#define EMAC_TDES2_TTSE_MASK (0x40000000U)
-#define EMAC_TDES2_B1L_MASK (0x00003FFFU)
-
-#define EMAC_RDES0_IVT_MASK (0xFFFF0000U)
-#define EMAC_RDES0_IVT_SHIFT (16U)
-#define EMAC_RDES0_OVT_MASK (0x0000FFFFU)
-
-#define EMAC_RDES1_TSA_MASK (0x00004000U)
-#define EMAC_RDES1_IPCE_MASK (0x00000080U)
-#define EMAC_RDES1_IPV6_MASK (0x00000020U)
-#define EMAC_RDES1_IPV4_MASK (0x00000010U)
-#define EMAC_RDES1_IPHE_MASK (0x00000008U)
-#define EMAC_RDES1_PT_MASK (0x00000007U)
-
-#define EMAC_RDES3_PL_MASK (0x00007FFFU)
-#define EMAC_RDES3_OWN_MASK (0x80000000U)
-#define EMAC_RDES3_INTE_MASK (0x40000000U)
-#define EMAC_RDES3_BUF1V_MASK (0x01000000U)
-#define EMAC_RDES3_RS1V_MASK (0x04000000U)
-#define EMAC_RDES3_RS0V_MASK (0x02000000U)
-
-#define EMAC_RDES3_CTXT_MASK (0x40000000U)
-
-#define EMAC_INFO1_CONSUMED_MASK (0x00000001U)
-#define EMAC_INFO1_LOCKED_MASK (0x10000000U)
-#define EMAC_INFO1_LENGTH_MASK (0x00003FFFU)
+#define EMAC_TDES3_OWN_MASK (0x80000000u)
+#define EMAC_TDES3_FD_MASK (0x20000000u)
+#define EMAC_TDES3_LD_MASK (0x10000000u)
+
+#define EMAC_TDES2_IOC_MASK (0x80000000u)
+#define EMAC_TDES2_TTSE_MASK (0x40000000u)
+#define EMAC_TDES2_B1L_MASK (0x00003fffu)
+
+#define EMAC_RDES0_IVT_MASK (0xffff0000u)
+#define EMAC_RDES0_IVT_SHIFT (16u)
+#define EMAC_RDES0_OVT_MASK (0x0000ffffu)
+
+#define EMAC_RDES1_TSA_MASK (0x00004000u)
+#define EMAC_RDES1_IPCE_MASK (0x00000080u)
+#define EMAC_RDES1_IPV6_MASK (0x00000020u)
+#define EMAC_RDES1_IPV4_MASK (0x00000010u)
+#define EMAC_RDES1_IPHE_MASK (0x00000008u)
+#define EMAC_RDES1_PT_MASK (0x00000007u)
+
+#define EMAC_RDES3_PL_MASK (0x00007fffu)
+#define EMAC_RDES3_OWN_MASK (0x80000000u)
+#define EMAC_RDES3_INTE_MASK (0x40000000u)
+#define EMAC_RDES3_BUF1V_MASK (0x01000000u)
+#define EMAC_RDES3_RS1V_MASK (0x04000000u)
+#define EMAC_RDES3_RS0V_MASK (0x02000000u)
+
+#define EMAC_RDES3_CTXT_MASK (0x40000000u)
+
+#define EMAC_INFO1_CONSUMED_MASK (0x00000001u)
+#define EMAC_INFO1_LOCKED_MASK (0x10000000u)
+#define EMAC_INFO1_LENGTH_MASK (0x00003fffu)
/****************************************************************************
* Public Types
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
index 715a4380ed..4b6e8cd43a 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_emios.h
@@ -132,32 +132,32 @@
/* Output Update Disable Register (OUDIS) */
-#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */
-#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */
-#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */
-#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */
-#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */
-#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */
-#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */
-#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */
-#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */
-#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */
-#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */
-#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */
-#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */
-#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */
-#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */
-#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */
-#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */
-#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */
-#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */
-#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */
-#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */
-#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */
-#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */
-#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */
-#define EMIOS_OUDIS_OU(n) (1 << n) /* Bit n: Channel n Output Update Disable (OU23) */
- /* Bits 24-31: Reserved */
+#define EMIOS_OUDIS_OU0 (1 << 0) /* Bit 0: Channel 0 Output Update Disable (OU0) */
+#define EMIOS_OUDIS_OU1 (1 << 1) /* Bit 1: Channel 1 Output Update Disable (OU1) */
+#define EMIOS_OUDIS_OU2 (1 << 2) /* Bit 2: Channel 2 Output Update Disable (OU2) */
+#define EMIOS_OUDIS_OU3 (1 << 3) /* Bit 3: Channel 3 Output Update Disable (OU3) */
+#define EMIOS_OUDIS_OU4 (1 << 4) /* Bit 4: Channel 4 Output Update Disable (OU4) */
+#define EMIOS_OUDIS_OU5 (1 << 5) /* Bit 5: Channel 5 Output Update Disable (OU5) */
+#define EMIOS_OUDIS_OU6 (1 << 6) /* Bit 6: Channel 6 Output Update Disable (OU6) */
+#define EMIOS_OUDIS_OU7 (1 << 7) /* Bit 7: Channel 7 Output Update Disable (OU7) */
+#define EMIOS_OUDIS_OU8 (1 << 8) /* Bit 8: Channel 8 Output Update Disable (OU8) */
+#define EMIOS_OUDIS_OU9 (1 << 9) /* Bit 9: Channel 9 Output Update Disable (OU9) */
+#define EMIOS_OUDIS_OU10 (1 << 10) /* Bit 10: Channel 10 Output Update Disable (OU10) */
+#define EMIOS_OUDIS_OU11 (1 << 11) /* Bit 11: Channel 11 Output Update Disable (OU11) */
+#define EMIOS_OUDIS_OU12 (1 << 12) /* Bit 12: Channel 12 Output Update Disable (OU12) */
+#define EMIOS_OUDIS_OU13 (1 << 13) /* Bit 13: Channel 13 Output Update Disable (OU13) */
+#define EMIOS_OUDIS_OU14 (1 << 14) /* Bit 14: Channel 14 Output Update Disable (OU14) */
+#define EMIOS_OUDIS_OU15 (1 << 15) /* Bit 15: Channel 15 Output Update Disable (OU15) */
+#define EMIOS_OUDIS_OU16 (1 << 16) /* Bit 16: Channel 16 Output Update Disable (OU16) */
+#define EMIOS_OUDIS_OU17 (1 << 17) /* Bit 17: Channel 17 Output Update Disable (OU17) */
+#define EMIOS_OUDIS_OU18 (1 << 18) /* Bit 18: Channel 18 Output Update Disable (OU18) */
+#define EMIOS_OUDIS_OU19 (1 << 19) /* Bit 19: Channel 19 Output Update Disable (OU19) */
+#define EMIOS_OUDIS_OU20 (1 << 20) /* Bit 20: Channel 20 Output Update Disable (OU20) */
+#define EMIOS_OUDIS_OU21 (1 << 21) /* Bit 21: Channel 21 Output Update Disable (OU21) */
+#define EMIOS_OUDIS_OU22 (1 << 22) /* Bit 22: Channel 22 Output Update Disable (OU22) */
+#define EMIOS_OUDIS_OU23 (1 << 23) /* Bit 23: Channel 23 Output Update Disable (OU23) */
+#define EMIOS_OUDIS_OU(n) (1 << (n)) /* Bit n: Channel n Output Update Disable (OU23) */
+ /* Bits 24-31: Reserved */
/* Disable Channel Register (UCDIS) */
@@ -191,14 +191,14 @@
#define EMIOS_A_SHIFT (0) /* Bits 0-15: A */
#define EMIOS_A_MASK (0xffff << EMIOS_A_SHIFT)
-#define EMIOS_A(n) ((n << EMIOS_A_SHIFT) & EMIOS_A_MASK)
+#define EMIOS_A(n) (((n) << EMIOS_A_SHIFT) & EMIOS_A_MASK)
/* Bits 16-31: Reserved */
/* UC B n (Bn) */
#define EMIOS_B_SHIFT (0) /* Bits 0-15: B */
#define EMIOS_B_MASK (0xffff << EMIOS_B_SHIFT)
-#define EMIOS_B(n) ((n << EMIOS_B_SHIFT) & EMIOS_B_MASK)
+#define EMIOS_B(n) (((n) << EMIOS_B_SHIFT) & EMIOS_B_MASK)
/* Bits 16-31: Reserved */
/* UC Counter n (CNTn) */
@@ -314,7 +314,7 @@
/* Bit 15: Reserved */
#define EMIOS_C2_UCEXTPRE_SHIFT (16) /* Bits 16-19: Extended Prescaler (UCEXTPRE) */
#define EMIOS_C2_UCEXTPRE_MASK (0x0f << EMIOS_C2_UCEXTPRE_SHIFT)
-#define EMIOS_C2_UCEXTPRE(n) ((n << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
+#define EMIOS_C2_UCEXTPRE(n) (((n) << EMIOS_C2_UCEXTPRE_SHIFT) & EMIOS_C2_UCEXTPRE_MASK)
/* Bits 20-31: Reserved */
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_EMIOS_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h
index 70cdb9c3dd..5ef603e133 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_flexcan.h
@@ -2669,7 +2669,7 @@
/* Bit 13: Reserved */
#define CAN_CTRL1_ERRMSK (1 << 14) /* Bit 14: Error Interrupt Mask (ERRMSK) */
#define CAN_CTRL1_BOFFMSK (1 << 15) /* Bit 15: Bus Off Interrupt Mask (BOFFMSK) */
-#define CAN_CTRL1_TIMINGMSK (0xFFFF << 16)
+#define CAN_CTRL1_TIMINGMSK (0xffff << 16)
#define CAN_CTRL1_PSEG2_SHIFT (16) /* Bits 16-18: Phase Segment 2 (PSEG2) */
#define CAN_CTRL1_PSEG2_MASK (0x07 << CAN_CTRL1_PSEG2_SHIFT)
#define CAN_CTRL1_PSEG2(x) (((x) << CAN_CTRL1_PSEG2_SHIFT) & CAN_CTRL1_PSEG2_MASK)
@@ -3121,10 +3121,10 @@
/* CAN MB TX codes */
#define CAN_TXMB_INACTIVE 0x8 /* MB is not active. */
#define CAN_TXMB_ABORT 0x9 /* MB is aborted. */
-#define CAN_TXMB_DATAORREMOTE 0xC /* MB is a TX Data Frame(when MB RTR = 0) or */
+#define CAN_TXMB_DATAORREMOTE 0xc /* MB is a TX Data Frame(when MB RTR = 0) or */
/* MB is a TX Remote Request Frame (when MB RTR = 1). */
-#define CAN_TXMB_TANSWER 0xE /* MB is a TX Response Request Frame from */
+#define CAN_TXMB_TANSWER 0xe /* MB is a TX Response Request Frame from */
/* an incoming Remote Request Frame. */
-#define CAN_TXMB_NOTUSED 0xF /* Not used.*/
+#define CAN_TXMB_NOTUSED 0xf /* Not used.*/
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_CAN_H */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
index 4e2abafda5..9c7e4a3a9c 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_fs26.h
@@ -31,7 +31,7 @@
#define FS26_M_FS (1 << 31) /* Bit 31: Main or Fail-safe register selection (M/FS) */
#define FS26_REG_ADDR_SHIFT (25) /* Bits 25-31: Register Address + M/FS */
-#define FS26_REG_ADDR_MASK (0x7F << FS26_REG_ADDR_SHIFT)
+#define FS26_REG_ADDR_MASK (0x7f << FS26_REG_ADDR_SHIFT)
#define FS26_REG_ADDR(n) (((n) << FS26_REG_ADDR_SHIFT) & FS26_REG_ADDR_MASK)
#define FS26_RW (1 << 24) /* Bit 24: Read/Write (reading Bit 24 = 0) */
@@ -49,17 +49,17 @@
/* FS26 Data encoding********************************************************/
#define FS26_DATA_LSB_SHIFT (8) /* Bits 8-15: DATA_LSB */
-#define FS26_DATA_LSB_MASK (0xFF << FS26_DATA_LSB_SHIFT)
+#define FS26_DATA_LSB_MASK (0xff << FS26_DATA_LSB_SHIFT)
#define FS26_DATA_LSB(n) (((n) << FS26_DATA_LSB_SHIFT) & FS26_DATA_LSB_MASK)
#define FS26_DATA_MSB_SHIFT (16) /* Bits 16-23: DATA_MSB */
-#define FS26_DATA_MSB_MASK (0xFF << FS26_DATA_MSB_SHIFT)
+#define FS26_DATA_MSB_MASK (0xff << FS26_DATA_MSB_SHIFT)
#define FS26_DATA_MSB(n) (((n) << FS26_DATA_MSB_SHIFT) & FS26_DATA_MSB_MASK)
#define FS26_DATA_SHIFT (8) /* Bits 8-23: DATA_MSB */
-#define FS26_DATA_MASK (0xFFFF << FS26_DATA_SHIFT)
+#define FS26_DATA_MASK (0xffff << FS26_DATA_SHIFT)
#define FS26_SET_DATA(n) (((n) << FS26_DATA_SHIFT) & FS26_DATA_MASK)
#define FS26_GET_DATA(n) (((n) & FS26_DATA_MASK) >> FS26_DATA_SHIFT)
#define FS26_CRC_SHIFT (0) /* Bits 0-7: CRC */
-#define FS26_CRC_MASK (0xFF << FS26_CRC_SHIFT)
+#define FS26_CRC_MASK (0xff << FS26_CRC_SHIFT)
#define FS26_CRC(n) (((n) << FS26_CRC_SHIFT) & FS26_CRC_MASK)
/* FS26 SPI register map */
@@ -74,12 +74,12 @@
#define FS26_M_VSUP_FLG (0x7) /* */
#define FS26_M_VSUP_MSK (0x8) /* */
#define FS26_M_WIO_FLG (0x9) /* */
-#define FS26_M_WIO_MSK (0xA) /* */
-#define FS26_M_COM_FLG (0xB) /* */
-#define FS26_M_COM_MSK (0xC) /* */
-#define FS26_M_SYS_CFG (0xD) /* */
-#define FS26_M_TSD_CFG (0xE) /* */
-#define FS26_M_REG_CFG (0xF) /* */
+#define FS26_M_WIO_MSK (0xa) /* */
+#define FS26_M_COM_FLG (0xb) /* */
+#define FS26_M_COM_MSK (0xc) /* */
+#define FS26_M_SYS_CFG (0xd) /* */
+#define FS26_M_TSD_CFG (0xe) /* */
+#define FS26_M_REG_CFG (0xf) /* */
#define FS26_M_WIO_CFG (0x10) /* */
#define FS26_M_REG_CTRL1 (0x11) /* */
#define FS26_M_REG_CTRL2 (0x12) /* */
@@ -102,12 +102,12 @@
#define FS26_FS_I_SAFE_INPUTS (0x47) /* */
#define FS26_FS_I_NOT_SAFE_INPUTS (0x48) /* */
#define FS26_FS_I_FSSM (0x49) /* */
-#define FS26_FS_I_NOT_FSSM (0x4A) /* */
-#define FS26_FS_WDW_DURATION (0x4B) /* */
-#define FS26_FS_NOT_WDW_DURATION (0x4C) /* */
-#define FS26_FS_WD_ANSWER (0x4D) /* */
-#define FS26_FS_WD_TOKEN (0x4E) /* */
-#define FS26_FS_ABIST_ON_DEMAND (0x4F) /* */
+#define FS26_FS_I_NOT_FSSM (0x4a) /* */
+#define FS26_FS_WDW_DURATION (0x4b) /* */
+#define FS26_FS_NOT_WDW_DURATION (0x4c) /* */
+#define FS26_FS_WD_ANSWER (0x4d) /* */
+#define FS26_FS_WD_TOKEN (0x4e) /* */
+#define FS26_FS_ABIST_ON_DEMAND (0x4f) /* */
#define FS26_FS_OVUV_REG_STATUS (0x50) /* */
#define FS26_FS_RELEASE_FS0B_FS1B (0x51) /* */
#define FS26_FS_SAFE_IOS_1 (0x52) /* */
@@ -243,11 +243,11 @@
#define WD_RFR_CNT_SHIFT (8) /* Reflect the value of the Watchdog Refresh Counter */
#define WD_RFR_CNT_MASK (0x7 << WD_RFR_CNT_SHIFT)
-#define WD_RFR_CNT(n) (n & (0x7 << WD_RFR_CNT_SHIFT))
+#define WD_RFR_CNT(n) ((n) & (0x7 << WD_RFR_CNT_SHIFT))
#define WD_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
-#define WD_ERR_CNT_MASK (0xF << WD_ERR_CNT_SHIFT)
-#define WD_ERR_CNT(n) ((n & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : ((n & (0x7 << WD_RFR_CNT_SHIFT)))
+#define WD_ERR_CNT_MASK (0xf << WD_ERR_CNT_SHIFT)
+#define WD_ERR_CNT(n) (((n) & (0x7 << WD_RFR_CNT_SHIFT)) > 11) ? (11) : (((n) & (0x7 << WD_RFR_CNT_SHIFT)))
/* FS26_FS_I_SAFE_INPUTS register */
@@ -349,13 +349,13 @@
#define DIS8S DIS8S_MASK
#define FLT_ERR_CNT_SHIFT (0) /* Reflect the value of the Watchdog Error Counter */
-#define FLT_ERR_CNT_MASK (0xF << FLT_ERR_CNT_SHIFT)
+#define FLT_ERR_CNT_MASK (0xf << FLT_ERR_CNT_SHIFT)
#define FLT_ERR_CNT(n) ((n & (0x7 << FLT_ERR_CNT_SHIFT)) > 12) ? (12) : ((n & (0x7 << FLT_ERR_CNT_SHIFT)))
/* FS26_FS_WDW_DURATION register */
#define WDW_PERIOD_SHIFT (12) /* Watchdog window period */
-#define WDW_PERIOD_MASK (0xF << WDW_PERIOD_SHIFT)
+#define WDW_PERIOD_MASK (0xf << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_DISABLE (0x0 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_1MS (0x1 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_2MS (0x2 << WDW_PERIOD_SHIFT)
@@ -366,12 +366,12 @@
# define WDW_PERIOD_12MS (0x7 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_16MS (0x8 << WDW_PERIOD_SHIFT)
# define WDW_PERIOD_24MS (0x9 << WDW_PERIOD_SHIFT)
-# define WDW_PERIOD_32MS (0xA << WDW_PERIOD_SHIFT)
-# define WDW_PERIOD_64MS (0xB << WDW_PERIOD_SHIFT)
-# define WDW_PERIOD_128MS (0xC << WDW_PERIOD_SHIFT)
-# define WDW_PERIOD_256MS (0xD << WDW_PERIOD_SHIFT)
-# define WDW_PERIOD_512MS (0xE << WDW_PERIOD_SHIFT)
-# define WDW_PERIOD_1024MS (0xF << WDW_PERIOD_SHIFT)
+# define WDW_PERIOD_32MS (0xa << WDW_PERIOD_SHIFT)
+# define WDW_PERIOD_64MS (0xb << WDW_PERIOD_SHIFT)
+# define WDW_PERIOD_128MS (0xc << WDW_PERIOD_SHIFT)
+# define WDW_PERIOD_256MS (0xd << WDW_PERIOD_SHIFT)
+# define WDW_PERIOD_512MS (0xe << WDW_PERIOD_SHIFT)
+# define WDW_PERIOD_1024MS (0xf << WDW_PERIOD_SHIFT)
#define WDW_DC_SHIFT (6) /* Watchdog window duty cycle */
#define WDW_DC_MASK (0x7 << WDW_DC_SHIFT)
@@ -382,7 +382,7 @@
# define WDW_DC_68_31 (0x4 << WDW_PERIOD_SHIFT)
#define WDW_RECOVERY_SHIFT (0) /* Watchdog window period */
-#define WDW_RECOVERY_MASK (0xF << WDW_RECOVERY_SHIFT)
+#define WDW_RECOVERY_MASK (0xf << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_DISABLE (0x0 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_1MS (0x1 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_2MS (0x2 << WDW_RECOVERY_SHIFT)
@@ -393,12 +393,12 @@
# define WDW_RECOVERY_12MS (0x7 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_16MS (0x8 << WDW_RECOVERY_SHIFT)
# define WDW_RECOVERY_24MS (0x9 << WDW_RECOVERY_SHIFT)
-# define WDW_RECOVERY_32MS (0xA << WDW_RECOVERY_SHIFT)
-# define WDW_RECOVERY_64MS (0xB << WDW_RECOVERY_SHIFT)
-# define WDW_RECOVERY_128MS (0xC << WDW_RECOVERY_SHIFT)
-# define WDW_RECOVERY_256MS (0xD << WDW_RECOVERY_SHIFT)
-# define WDW_RECOVERY_512MS (0xE << WDW_RECOVERY_SHIFT)
-# define WDW_RECOVERY_1024MS (0xF << WDW_RECOVERY_SHIFT)
+# define WDW_RECOVERY_32MS (0xa << WDW_RECOVERY_SHIFT)
+# define WDW_RECOVERY_64MS (0xb << WDW_RECOVERY_SHIFT)
+# define WDW_RECOVERY_128MS (0xc << WDW_RECOVERY_SHIFT)
+# define WDW_RECOVERY_256MS (0xd << WDW_RECOVERY_SHIFT)
+# define WDW_RECOVERY_512MS (0xe << WDW_RECOVERY_SHIFT)
+# define WDW_RECOVERY_1024MS (0xf << WDW_RECOVERY_SHIFT)
/* FS26_FS_DIAG_SAFETY1 register */
@@ -465,14 +465,14 @@
#define REG_CORRUPT REG_CORRUPT_MASK
#define FS_STATES_SHIFT (0) /* LBIST STATUS */
-#define FS_STATES_MASK (0x1F << FS_STATES_SHIFT)
+#define FS_STATES_MASK (0x1f << FS_STATES_SHIFT)
#define FS_STATES FS_STATES_MASK
# define FS_STATES_DEBUG_ENTRY (0x4 << FS_STATES_SHIFT)
# define FS_STATES_ENABLE_MON (0x6 << FS_STATES_SHIFT)
# define FS_STATES_RSTB_RELEASE (0x8 << FS_STATES_SHIFT)
# define FS_STATES_INIT_FS (0x9 << FS_STATES_SHIFT)
-# define FS_STATES_SAFETY_OUT_NOT (0xA << FS_STATES_SHIFT)
-# define FS_STATES_NORMAL (0xB << FS_STATES_SHIFT)
+# define FS_STATES_SAFETY_OUT_NOT (0xa << FS_STATES_SHIFT)
+# define FS_STATES_NORMAL (0xb << FS_STATES_SHIFT)
/* FS26_FS_GRL_FLAGS register */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
index 0eb9f99c3f..ef189d6063 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_fxosc.h
@@ -72,7 +72,7 @@
/* Bits 8-15: Reserved */
#define FXOSC_CTRL_EOCV_SHIFT (16) /* Bits 16-23: End of count value (EOCV) */
#define FXOSC_CTRL_EOCV_MASK (0xff << FXOSC_CTRL_EOCV_SHIFT)
-#define FXOSC_CTRL_EOCV(n) ((n << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
+#define FXOSC_CTRL_EOCV(n) (((n) << FXOSC_CTRL_EOCV_SHIFT) & FXOSC_CTRL_EOCV_MASK)
#define FXOSC_CTRL_COMP_EN (1 << 24) /* Bit 24: Comparator enable (COMP_EN) */
# define FXOSC_CTRL_COMP_DIS (0 << 24) /* Comparator disable */
/* Bits 25-30: Reserved */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
index e8ac632f10..fab62c1d9e 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
@@ -403,7 +403,7 @@
#define QSPI_LUTKEY_KEY_SHIFT (0) /* Bits 0-31: Key to lock or unlock the LUT (KEY) */
#define QSPI_LUTKEY_KEY_MASK (0xffffffff << QSPI_LUTKEY_KEY_SHIFT)
-#define QSPI_LUTKEY_KEY (0x5AF05AF0UL)
+#define QSPI_LUTKEY_KEY (0x5AF05AF0ul)
/* LUT Lock Configuration Register (LKCR) */
@@ -447,59 +447,58 @@
typedef enum
{
- QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
- QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
- QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
- QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
+ QSPI_SIDE_A1 = 0x00u, /* Serial flash connected on side A1 */
+ QSPI_SIDE_A2 = 0x01u, /* Serial flash connected on side A2 */
+ QSPI_SIDE_B1 = 0x02u, /* Serial flash connected on side B1 */
+ QSPI_SIDE_B2 = 0x03u, /* Serial flash connected on side B2 */
} s32k3xx_qspi_connectiontype;
/* flash operation type */
typedef enum
{
- QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
- QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
- QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
- QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
- QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
+ QSPI_OP_TYPE_CMD = 0x00u, /* Simple command */
+ QSPI_OP_TYPE_WRITE_REG = 0x01u, /* Write value in external flash register */
+ QSPI_OP_TYPE_RMW_REG = 0x02u, /* RMW command on external flash register */
+ QSPI_OP_TYPE_READ_REG = 0x03u, /* Read external flash register until expected value is read */
+ QSPI_OP_TYPE_QSPI_CFG = 0x04u, /* Re-configure QSPI controller */
} s32k3xx_qspi_optype;
/* Lut commands */
typedef enum
{
- QSPI_LUT_INSTR_STOP = (0U << 10U), /* End of sequence */
- QSPI_LUT_INSTR_CMD = (1U << 10U), /* Command */
- QSPI_LUT_INSTR_ADDR = (2U << 10U), /* Address */
- QSPI_LUT_INSTR_DUMMY = (3U << 10U), /* Dummy cycles */
- QSPI_LUT_INSTR_MODE = (4U << 10U), /* 8-bit mode */
- QSPI_LUT_INSTR_MODE2 = (5U << 10U), /* 2-bit mode */
- QSPI_LUT_INSTR_MODE4 = (6U << 10U), /* 4-bit mode */
- QSPI_LUT_INSTR_READ = (7U << 10U), /* Read data */
- QSPI_LUT_INSTR_WRITE = (8U << 10U), /* Write data */
- QSPI_LUT_INSTR_JMP_ON_CS = (9U << 10U), /* Jump on chip select deassert and stop */
- QSPI_LUT_INSTR_ADDR_DDR = (10U << 10U), /* Address - DDR mode */
- QSPI_LUT_INSTR_MODE_DDR = (11U << 10U), /* 8-bit mode - DDR mode */
- QSPI_LUT_INSTR_MODE2_DDR = (12U << 10U), /* 2-bit mode - DDR mode */
- QSPI_LUT_INSTR_MODE4_DDR = (13U << 10U), /* 4-bit mode - DDR mode */
- QSPI_LUT_INSTR_READ_DDR = (14U << 10U), /* Read data - DDR mode */
- QSPI_LUT_INSTR_WRITE_DDR = (15U << 10U), /* Write data - DDR mode */
- QSPI_LUT_INSTR_DATA_LEARN = (16U << 10U), /* Data learning pattern */
- QSPI_LUT_INSTR_CMD_DDR = (17U << 10U), /* Command - DDR mode */
- QSPI_LUT_INSTR_CADDR = (18U << 10U), /* Column address */
- QSPI_LUT_INSTR_CADDR_DDR = (19U << 10U), /* Column address - DDR mode */
- QSPI_LUT_INSTR_JMP_TO_SEQ = (20U << 10U), /* Jump on chip select deassert and continue */
+ QSPI_LUT_INSTR_STOP = (0u << 10u), /* End of sequence */
+ QSPI_LUT_INSTR_CMD = (1u << 10u), /* Command */
+ QSPI_LUT_INSTR_ADDR = (2u << 10u), /* Address */
+ QSPI_LUT_INSTR_DUMMY = (3u << 10u), /* Dummy cycles */
+ QSPI_LUT_INSTR_MODE = (4u << 10u), /* 8-bit mode */
+ QSPI_LUT_INSTR_MODE2 = (5u << 10u), /* 2-bit mode */
+ QSPI_LUT_INSTR_MODE4 = (6u << 10u), /* 4-bit mode */
+ QSPI_LUT_INSTR_READ = (7u << 10u), /* Read data */
+ QSPI_LUT_INSTR_WRITE = (8u << 10u), /* Write data */
+ QSPI_LUT_INSTR_JMP_ON_CS = (9u << 10u), /* Jump on chip select deassert and stop */
+ QSPI_LUT_INSTR_ADDR_DDR = (10u << 10u), /* Address - DDR mode */
+ QSPI_LUT_INSTR_MODE_DDR = (11u << 10u), /* 8-bit mode - DDR mode */
+ QSPI_LUT_INSTR_MODE2_DDR = (12u << 10u), /* 2-bit mode - DDR mode */
+ QSPI_LUT_INSTR_MODE4_DDR = (13u << 10u), /* 4-bit mode - DDR mode */
+ QSPI_LUT_INSTR_READ_DDR = (14u << 10u), /* Read data - DDR mode */
+ QSPI_LUT_INSTR_WRITE_DDR = (15u << 10u), /* Write data - DDR mode */
+ QSPI_LUT_INSTR_DATA_LEARN = (16u << 10u), /* Data learning pattern */
+ QSPI_LUT_INSTR_CMD_DDR = (17u << 10u), /* Command - DDR mode */
+ QSPI_LUT_INSTR_CADDR = (18u << 10u), /* Column address */
+ QSPI_LUT_INSTR_CADDR_DDR = (19u << 10u), /* Column address - DDR mode */
+ QSPI_LUT_INSTR_JMP_TO_SEQ = (20u << 10u), /* Jump on chip select deassert and continue */
} s32k3xx_qspi_lutcommandstype;
/* Lut pad options */
typedef enum
{
- QSPI_LUT_PADS_1 = (0U << 8U), /* 1 Pad */
- QSPI_LUT_PADS_2 = (1U << 8U), /* 2 Pads */
- QSPI_LUT_PADS_4 = (2U << 8U), /* 4 Pads */
- QSPI_LUT_PADS_8 = (3U << 8U), /* 8 Pads */
+ QSPI_LUT_PADS_1 = (0u << 8u), /* 1 Pad */
+ QSPI_LUT_PADS_2 = (1u << 8u), /* 2 Pads */
+ QSPI_LUT_PADS_4 = (2u << 8u), /* 4 Pads */
+ QSPI_LUT_PADS_8 = (3u << 8u), /* 8 Pads */
} s32k3xx_qspi_lutpadstype;
#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_QSPI_H */
-
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
index bb148f3e56..5340443375 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_virtwrapper.h
@@ -198,7 +198,7 @@
/* Parameter_n Register (REG_D1055_1040) */
/* Bits 0-29: Reserved */
-#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR REgister Of REG_PROT (REG_GCR) */
+#define VIRTWRAPPER_REG_D_REG_GCR_SHIFT (30) /* Bits 30-31: GCR Register Of REG_PROT (REG_GCR) */
#define VIRTWRAPPER_REG_D_REG_GCR_MASK (0x03 << VIRTWRAPPER_REG_D_REG_GCR_SHIFT)
-#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */
\ No newline at end of file
+#endif /* __ARCH_ARM_SRC_S32K3XX_HARDWARE_S32K3XX_VIRTWRAPPER_H */
diff --git a/arch/arm/src/s32k3xx/s32k3xx_edma.c b/arch/arm/src/s32k3xx/s32k3xx_edma.c
index 1e1c210b20..49d4e4cc30 100644
--- a/arch/arm/src/s32k3xx/s32k3xx_edma.c
+++ b/arch/arm/src/s32k3xx/s32k3xx_edma.c
@@ -94,7 +94,7 @@
/* Align to the cache line size which we assume is >= 8 */
# define EDMA_ALIGN ARMV7M_DCACHE_LINESIZE
-# define EDMA_ALIGN_MASK (EDMA_ALIGN-1)
+# define EDMA_ALIGN_MASK (EDMA_ALIGN - 1)
# define EDMA_ALIGN_UP(n) (((n) + EDMA_ALIGN_MASK) & ~EDMA_ALIGN_MASK)
#else
@@ -164,6 +164,42 @@ struct s32k3xx_edma_s
* Private Data
****************************************************************************/
+uintptr_t const S32K3XX_EDMA_TCD[S32K3XX_EDMA_NCHANNELS] =
+{
+ S32K3XX_EDMA_CH0_CSR,
+ S32K3XX_EDMA_CH1_CSR,
+ S32K3XX_EDMA_CH2_CSR,
+ S32K3XX_EDMA_CH3_CSR,
+ S32K3XX_EDMA_CH4_CSR,
+ S32K3XX_EDMA_CH5_CSR,
+ S32K3XX_EDMA_CH6_CSR,
+ S32K3XX_EDMA_CH7_CSR,
+ S32K3XX_EDMA_CH8_CSR,
+ S32K3XX_EDMA_CH9_CSR,
+ S32K3XX_EDMA_CH10_CSR,
+ S32K3XX_EDMA_CH11_CSR,
+ S32K3XX_EDMA_CH12_CSR,
+ S32K3XX_EDMA_CH13_CSR,
+ S32K3XX_EDMA_CH14_CSR,
+ S32K3XX_EDMA_CH15_CSR,
+ S32K3XX_EDMA_CH16_CSR,
+ S32K3XX_EDMA_CH17_CSR,
+ S32K3XX_EDMA_CH18_CSR,
+ S32K3XX_EDMA_CH19_CSR,
+ S32K3XX_EDMA_CH20_CSR,
+ S32K3XX_EDMA_CH21_CSR,
+ S32K3XX_EDMA_CH22_CSR,
+ S32K3XX_EDMA_CH23_CSR,
+ S32K3XX_EDMA_CH24_CSR,
+ S32K3XX_EDMA_CH25_CSR,
+ S32K3XX_EDMA_CH26_CSR,
+ S32K3XX_EDMA_CH27_CSR,
+ S32K3XX_EDMA_CH28_CSR,
+ S32K3XX_EDMA_CH29_CSR,
+ S32K3XX_EDMA_CH30_CSR,
+ S32K3XX_EDMA_CH31_CSR
+};
+
/* The state of the eDMA */
static struct s32k3xx_edma_s g_edma;
[incubator-nuttx] 04/09: NXP S32K3XX: add initial support for NXP S32K344EVB board
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7816ba9a7be42bf359a746c7884adac2da76d0f4
Author: Jari van Ewijk <ja...@nxp.com>
AuthorDate: Fri Jul 22 10:29:40 2022 +0200
NXP S32K3XX: add initial support for NXP S32K344EVB board
Co-authored-by: Peter van der Perk <pe...@nxp.com>
---
boards/Kconfig | 37 ++-
boards/arm/s32k3xx/s32k344evb/Kconfig | 8 +
boards/arm/s32k3xx/s32k344evb/README.txt | 134 ++++++++
.../arm/s32k3xx/s32k344evb/configs/nsh/defconfig | 44 +++
boards/arm/s32k3xx/s32k344evb/include/board.h | 168 ++++++++++
boards/arm/s32k3xx/s32k344evb/scripts/Make.defs | 49 +++
boards/arm/s32k3xx/s32k344evb/scripts/flash.ld | 156 +++++++++
boards/arm/s32k3xx/s32k344evb/src/Makefile | 50 +++
boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h | 133 ++++++++
.../arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c | 82 +++++
.../arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c | 166 ++++++++++
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c | 77 +++++
.../arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c | 122 +++++++
.../arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c | 154 +++++++++
.../s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c | 157 +++++++++
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c | 104 ++++++
.../s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c | 250 ++++++++++++++
boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c | 366 +++++++++++++++++++++
.../arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c | 124 +++++++
19 files changed, 2369 insertions(+), 12 deletions(-)
diff --git a/boards/Kconfig b/boards/Kconfig
index 01b502fb45..63b5baf381 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -1580,24 +1580,24 @@ config ARCH_BOARD_S32K144EVB
This options selects support for NuttX on the NXP S32K144EVB board
featuring the S32K144 Cortex-M4F.
-config ARCH_BOARD_UCANS32K146
- bool "NXP UCANS32K146"
+config ARCH_BOARD_S32K146EVB
+ bool "NXP S32K146EVB"
depends on ARCH_CHIP_S32K146
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
- This options selects support for NuttX on the NXP UCANS32K board
+ This options selects support for NuttX on the NXP S32K146EVB board
featuring the S32K146 Cortex-M4F.
-config ARCH_BOARD_S32K146EVB
- bool "NXP S32K146EVB"
+config ARCH_BOARD_UCANS32K146
+ bool "NXP UCANS32K146"
depends on ARCH_CHIP_S32K146
select ARCH_HAVE_LEDS
select ARCH_HAVE_BUTTONS
select ARCH_HAVE_IRQBUTTONS
---help---
- This options selects support for NuttX on the NXP S32K146EVB board
+ This options selects support for NuttX on the NXP UCANS32K1 board
featuring the S32K146 Cortex-M4F.
config ARCH_BOARD_S32K148EVB
@@ -1610,6 +1610,16 @@ config ARCH_BOARD_S32K148EVB
This options selects support for NuttX on the NXP S32K148EVB board
featuring the S32K148 Cortex-M4F.
+config ARCH_BOARD_S32K344EVB
+ bool "NXP S32K344EVB"
+ depends on ARCH_CHIP_S32K344
+ select ARCH_HAVE_LEDS
+ select ARCH_HAVE_BUTTONS
+ select ARCH_HAVE_IRQBUTTONS
+ ---help---
+ This options selects support for NuttX on the NXP S32K344EVB board
+ featuring the S32K344 Cortex-M7.
+
config ARCH_BOARD_SABRE_6QUAD
bool "NXP/Freescale i.MX6 Sabre-6Quad board"
depends on ARCH_CHIP_IMX6_6QUAD
@@ -1620,7 +1630,6 @@ config ARCH_BOARD_SABRE_6QUAD
This options selects support for NuttX on the NXP/Freescale Sabre
board featuring the iMX 6Quad CPU.
-
config ARCH_BOARD_QEMU_A53
bool "Qemu A53 board"
depends on ARCH_CHIP_QEMU_A53
@@ -2667,11 +2676,12 @@ config ARCH_BOARD
default "rx65n-grrose" if ARCH_BOARD_RX65N_GRROSE
default "s32k118evb" if ARCH_BOARD_S32K118EVB
default "s32k144evb" if ARCH_BOARD_S32K144EVB
+ default "s32k146evb" if ARCH_BOARD_S32K146EVB
default "ucans32k146" if ARCH_BOARD_UCANS32K146
+ default "s32k148evb" if ARCH_BOARD_S32K148EVB
+ default "s32k344evb" if ARCH_BOARD_S32K344EVB
default "rv32m1-vega" if ARCH_BOARD_RV32M1_VEGA
default "rv-virt" if ARCH_BOARD_QEMU_RV_VIRT
- default "s32k146evb" if ARCH_BOARD_S32K146EVB
- default "s32k148evb" if ARCH_BOARD_S32K148EVB
default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD
default "qemu-a53" if ARCH_BOARD_QEMU_A53
default "sama5d2-xult" if ARCH_BOARD_SAMA5D2_XULT
@@ -2834,15 +2844,18 @@ endif
if ARCH_BOARD_S32K144EVB
source "boards/arm/s32k1xx/s32k144evb/Kconfig"
endif
-if ARCH_BOARD_UCANS32K146
-source "boards/arm/s32k1xx/ucans32k146/Kconfig"
-endif
if ARCH_BOARD_S32K146EVB
source "boards/arm/s32k1xx/s32k146evb/Kconfig"
endif
+if ARCH_BOARD_UCANS32K146
+source "boards/arm/s32k1xx/ucans32k146/Kconfig"
+endif
if ARCH_BOARD_S32K148EVB
source "boards/arm/s32k1xx/s32k148evb/Kconfig"
endif
+if ARCH_BOARD_S32K344EVB
+source "boards/arm/s32k3xx/s32k344evb/Kconfig"
+endif
if ARCH_BOARD_SABRE_6QUAD
source "boards/arm/imx6/sabre-6quad/Kconfig"
endif
diff --git a/boards/arm/s32k3xx/s32k344evb/Kconfig b/boards/arm/s32k3xx/s32k344evb/Kconfig
new file mode 100644
index 0000000000..beb7e5752f
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/Kconfig
@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_S32K344EVB
+
+endif # ARCH_BOARD_S32K344EVB
diff --git a/boards/arm/s32k3xx/s32k344evb/README.txt b/boards/arm/s32k3xx/s32k344evb/README.txt
new file mode 100644
index 0000000000..6dc6f5679d
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/README.txt
@@ -0,0 +1,134 @@
+README
+======
+
+This directory holds the port to the NXP S32K344EVB-Q257 development board.
+
+Contents
+========
+
+ o Status
+ o Serial Console
+ o LEDs and Buttons
+ o OpenSDA Notes
+ o Configurations
+
+Status
+======
+
+ 2021-07-05: Configuration created.
+
+ TODO: Need to calibrate the delay loop. The current value of
+ CONFIG_BOARD_LOOPSPERMSEC is a bogus value retained from a copy-paste
+ (see apps/examples/calib_udelay).
+
+Serial Console
+==============
+
+ By default, the serial console will be provided on the OpenSDA VCOM port:
+
+ OpenSDA UART RX PTA15 (LPUART6_RX)
+ OpenSDA UART TX PTA16 (LPUART6_TX)
+
+ USB drivers for the PEmicro CDC Serial Port are available here:
+ http://www.pemicro.com/opensda/
+
+LEDs and Buttons
+================
+
+ LEDs
+ ----
+ The S32K344EVB has two RGB LEDs:
+
+ RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12)
+ GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13)
+ BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0)
+
+ RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1)
+ GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6)
+ BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8)
+
+ An output of '1' illuminates the LED.
+
+ If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
+ any way. The following definitions are used to access individual RGB
+ components (see s32k344evb.h):
+
+ GPIO_LED0_R
+ GPIO_LED0_G
+ GPIO_LED0_B
+
+ GPIO_LED1_R
+ GPIO_LED1_G
+ GPIO_LED1_B
+
+ The RGB components could, alternatively, be controlled through PWM using
+ the common RGB LED driver.
+
+ If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
+ the S32K344EVB. The following definitions describe how NuttX controls the
+ LEDs:
+
+ ==========================================+========+========+=========
+ RED GREEN BLUE
+ ==========================================+========+========+=========
+
+ LED_STARTED NuttX has been started OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ LED_STACKCREATED Idle stack created OFF ON OFF
+ LED_INIRQ In an interrupt (no change)
+ LED_SIGNAL In a signal handler (no change)
+ LED_ASSERTION An assertion failed (no change)
+ LED_PANIC The system has crashed FLASH OFF OFF
+ LED_IDLE S32K344 in sleep mode (no change)
+ ==========================================+========+========+=========
+
+ Buttons
+ -------
+ The S32K344EVB supports two buttons:
+
+ SW0 PTB26 (EIRQ13 / WKPU41)
+ SW1 PTB19 (WKPU38)
+
+OpenSDA Notes
+=============
+
+ - USB drivers for the PEmicro CDC Serial Port are available here:
+ http://www.pemicro.com/opensda/
+
+ - The drag'n'drog interface expects files in .srec format.
+
+Configurations
+==============
+
+ Common Information
+ ------------------
+ Each S32K344EVB configuration is maintained in a sub-directory and can be
+ selected as follows:
+
+ tools/configure.sh s32k344evb:<subdir>
+
+ Where <subdir> is one of the sub-directories listed in the next paragraph.
+
+ NOTES (common for all configurations):
+
+ 1. This configuration uses the mconf-based configuration tool. To change
+ this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt.
+ Also see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. Unless otherwise stated, the serial console used is LPUART1 at
+ 115,200 8N1. This corresponds to the OpenSDA VCOM port.
+
+ Configuration Sub-directories
+ -----------------------------
+
+ nsh:
+ ---
+ Configures the NuttShell (nsh) located at apps/examples/nsh. Support
+ for builtin applications is enabled, but in the base configuration the
+ only application selected is the "Hello, World!" example.
diff --git a/boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig b/boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig
new file mode 100644
index 0000000000..36bacd0f87
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/configs/nsh/defconfig
@@ -0,0 +1,44 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="s32k344evb"
+CONFIG_ARCH_BOARD_S32K344EVB=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="s32k3xx"
+CONFIG_ARCH_CHIP_S32K344=y
+CONFIG_ARCH_CHIP_S32K3XX=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=14539
+CONFIG_BUILTIN=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_LPUART13_SERIAL_CONSOLE=y
+CONFIG_MOTOROLA_SREC=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=288000
+CONFIG_RAM_START=0x20408000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_S32K3XX_LPUART13=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2022
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_NSH=y
diff --git a/boards/arm/s32k3xx/s32k344evb/include/board.h b/boards/arm/s32k3xx/s32k344evb/include/board.h
new file mode 100644
index 0000000000..a6d8d0623c
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/include/board.h
@@ -0,0 +1,168 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __BOARDS_ARM_S32K3XX_S32K344EVB_INCLUDE_BOARD_H
+#define __BOARDS_ARM_S32K3XX_S32K344EVB_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* The S32K344EVB is fitted with a 16 MHz crystal */
+
+#define BOARD_XTAL_FREQUENCY 16000000
+
+/* The S32K344 will run at 160 MHz */
+
+/* LED definitions **********************************************************/
+
+/* The S32K344EVB has two RGB LEDs:
+ *
+ * RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12)
+ * GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13)
+ * BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0)
+ *
+ * RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1)
+ * GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6)
+ * BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8)
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
+ * any way. The following definitions are used to access individual RGB
+ * components.
+ *
+ * The RGB components could, alternatively be controlled through PWM using
+ * the common RGB LED driver.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED0_R 0
+#define BOARD_LED0_G 1
+#define BOARD_LED0_B 2
+
+#define BOARD_LED1_R 3
+#define BOARD_LED1_G 4
+#define BOARD_LED1_B 5
+
+#define BOARD_NLEDS 6
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED0_R_BIT (1 << BOARD_LED0_R)
+#define BOARD_LED0_G_BIT (1 << BOARD_LED0_G)
+#define BOARD_LED0_B_BIT (1 << BOARD_LED0_B)
+
+#define BOARD_LED1_R_BIT (1 << BOARD_LED1_R)
+#define BOARD_LED1_G_BIT (1 << BOARD_LED1_G)
+#define BOARD_LED1_B_BIT (1 << BOARD_LED1_B)
+
+/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
+ * the S32K344EVB. The following definitions describe how NuttX controls the
+ * LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ---------------- ----------------------------- -------------------
+ */
+
+#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */
+#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */
+#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */
+#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */
+#define LED_INIRQ 0 /* In an interrupt (No change) */
+#define LED_SIGNAL 0 /* In a signal handler (No change) */
+#define LED_ASSERTION 0 /* An assertion failed (No change) */
+#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */
+#undef LED_IDLE /* S32K344 is in sleep mode (Not used) */
+
+/* Button definitions *******************************************************/
+
+/* The S32K344EVB supports two buttons:
+ *
+ * SW0 PTB26 (EIRQ13 / WKPU41)
+ * SW1 PTB19 (WKPU38)
+ */
+
+#define BUTTON_SW0 0
+#define BUTTON_SW1 1
+#define NUM_BUTTONS 2
+
+#define BUTTON_SW0_BIT (1 << BUTTON_SW0)
+#define BUTTON_SW1_BIT (1 << BUTTON_SW1)
+
+/* UART selections **********************************************************/
+
+/* By default, the serial console will be provided on the OpenSDA VCOM port:
+ *
+ * OpenSDA UART RX PTA15 (LPUART6_RX)
+ * OpenSDA UART TX PTA16 (LPUART6_TX)
+ */
+
+#define PIN_LPUART6_RX PIN_LPUART6_RX_1 /* PTA15 */
+#define PIN_LPUART6_TX PIN_LPUART6_TX_1 /* PTA16 */
+
+/* LPUART13 J58 USB-UART */
+
+#define PIN_LPUART13_RX PIN_LPUART13_RX_2 /* PTC27 */
+#define PIN_LPUART13_TX PIN_LPUART13_TX_2 /* PTC26 */
+
+/* SPI selections ***********************************************************/
+
+/* LPSPI0 FS26 Safety SBC */
+
+#define PIN_LPSPI0_SCK PIN_LPSPI0_SCK_1 /* PTC8 */
+#define PIN_LPSPI0_MISO PIN_LPSPI0_SIN_1 /* PTC9 */
+#define PIN_LPSPI0_MOSI PIN_LPSPI0_SOUT_2 /* PTB1 */
+
+#define PIN_LPSPI0_PCS (PIN_PTB0 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE) /* PTB0 */
+
+/* LPSPI1 J353 Arduino Header */
+
+#define PIN_LPSPI1_SCK PIN_LPSPI1_SCK_4 /* PTB14 */
+#define PIN_LPSPI1_MISO PIN_LPSPI1_SIN_4 /* PTB15 */
+#define PIN_LPSPI1_MOSI PIN_LPSPI1_SOUT_3 /* PTB16 */
+
+#define PIN_LPSPI1_PCS PIN_LPSPI1_PCS3_2 /* PTB17 */
+
+/* I2C selections ***********************************************************/
+
+/* LPI2C1 J353 Arduino Header / J63 ENET PHY / MMA8452Q Accelerometer
+ * / SGTL5000 Audio Codec
+ */
+
+#define PIN_LPI2C1_SCL PIN_LPI2C1_SCL_1 /* PTC7 */
+#define PIN_LPI2C1_SDA PIN_LPI2C1_SDA_1 /* PTC6 */
+
+/* FLEXCAN selections *******************************************************/
+
+#define PIN_CAN0_TX PIN_CAN0_TX_1 /* PTA7 */
+#define PIN_CAN0_RX PIN_CAN0_RX_1 /* PTA6 */
+
+#endif /* __BOARDS_ARM_S32K3XX_S32K344EVB_INCLUDE_BOARD_H */
diff --git a/boards/arm/s32k3xx/s32k344evb/scripts/Make.defs b/boards/arm/s32k3xx/s32k344evb/scripts/Make.defs
new file mode 100644
index 0000000000..19a99cd837
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/scripts/Make.defs
@@ -0,0 +1,49 @@
+############################################################################
+# boards/arm/s32k3xx/s32k344evb/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Copyright 2022 NXP
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
+ LDSCRIPT = sram.ld
+endif
+
+$(warning, LDSCRIPT is $(LDSCRIPT))
+ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
+$(warning, LDSCRIPT is $(LDSCRIPT))
+$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
+
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
diff --git a/boards/arm/s32k3xx/s32k344evb/scripts/flash.ld b/boards/arm/s32k3xx/s32k344evb/scripts/flash.ld
new file mode 100644
index 0000000000..5822d4865b
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/scripts/flash.ld
@@ -0,0 +1,156 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/scripts/flash.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* TO DO: ADD DESCRIPTION
+ *
+ * 0x00400000 - 0x007fffff 4194304 Program Flash (last 64K sBAF)
+ * 0x10000000 - 0x1003ffff 262144 Data Flash (last 32K HSE_NVM)
+ * 0x20400000 - 0x20408000 32768 Standby RAM_0 (32K)
+ * 0x20400000 - 0x20427fff 163840 SRAM_0
+ * 0x20428000 - 0x2044ffff 163840 SRAM_1
+ *
+ * Last 48 KB of SRAM_1 reserved by HSE Firmware
+ * Last 128 KB of CODE_FLASH_3 reserved by HSE Firmware
+ * Last 128 KB of DATA_FLASH reserved by HSE Firmware (not supported in this linker file)
+ */
+
+MEMORY
+{
+ BOOT_HEADER (R) : ORIGIN = 0x00400000, LENGTH = 0x00001000 /* 0x00400000 - 0x00400fff */
+ flash (rx) : ORIGIN = 0x00401000, LENGTH = 0x003cffff /* 0x00401000 - (0x007fffff - 0x20000 (128 KB) = 0x007dffff) */
+ sram0_stdby (rwx) : ORIGIN = 0x20400000, LENGTH = 32K
+ sram (rwx) : ORIGIN = 0x20408000, LENGTH = 240K
+ itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
+ dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+EXTERN(boot_header)
+ENTRY(_stext)
+
+SECTIONS
+{
+
+ .boot_header :
+ {
+ KEEP(*(.boot_header))
+ } > BOOT_HEADER
+
+ .text :
+ {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text.__start)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section :
+ {
+ _sinit = ABSOLUTE(.);
+ KEEP(*(.init_array .init_array.*))
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >flash
+
+ .ARM.exidx :
+ {
+ __exidx_start = ABSOLUTE(.);
+ *(.ARM.exidx*)
+ __exidx_end = ABSOLUTE(.);
+ } >flash
+
+ /* Due ECC initialization sequence __data_start__ and __data_end__ should be aligned on 8 bytes */
+ .data :
+ {
+ . = ALIGN(8);
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(8);
+ _edata = ABSOLUTE(.);
+ } > sram AT > flash
+
+ _eronly = LOADADDR(.data);
+
+ .ramfunc ALIGN(8):
+ {
+ _sramfuncs = ABSOLUTE(.);
+ *(.ramfunc .ramfunc.*)
+ _eramfuncs = ABSOLUTE(.);
+ } > sram AT > flash
+
+ _framfuncs = LOADADDR(.ramfunc);
+
+ /* Due ECC initialization sequence __bss_start__ and __bss_end__ should be aligned on 8 bytes */
+ .bss :
+ {
+ . = ALIGN(8);
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ CM7_0_START_ADDRESS = ORIGIN(flash);
+
+ /* Stabs debugging sections. */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+
+ SRAM_BASE_ADDR = ORIGIN(sram);
+ SRAM_END_ADDR = ORIGIN(sram) + LENGTH(sram);
+ SRAM_STDBY_BASE_ADDR = ORIGIN(sram0_stdby);
+ SRAM_STDBY_END_ADDR = ORIGIN(sram0_stdby) + LENGTH(sram0_stdby);
+ ITCM_BASE_ADDR = ORIGIN(itcm);
+ ITCM_END_ADDR = ORIGIN(itcm) + LENGTH(itcm);
+ DTCM_BASE_ADDR = ORIGIN(dtcm);
+ DTCM_END_ADDR = ORIGIN(dtcm) + LENGTH(dtcm);
+}
diff --git a/boards/arm/s32k3xx/s32k344evb/src/Makefile b/boards/arm/s32k3xx/s32k344evb/src/Makefile
new file mode 100644
index 0000000000..325b455763
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/Makefile
@@ -0,0 +1,50 @@
+############################################################################
+# boards/arm/s32k3xx/s32k344evb/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Copyright 2022 NXP
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = s32k3xx_boot.c s32k3xx_bringup.c s32k3xx_clockconfig.c
+CSRCS += s32k3xx_periphclocks.c
+
+ifeq ($(CONFIG_ARCH_BUTTONS),y)
+CSRCS += s32k3xx_buttons.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += s32k3xx_autoleds.c
+else
+CSRCS += s32k3xx_userleds.c
+endif
+
+ifeq ($(CONFIG_BOARDCTL),y)
+CSRCS += s32k3xx_appinit.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPI2C),y)
+CSRCS += s32k3xx_i2c.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPSPI),y)
+CSRCS += s32k3xx_spi.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h b/boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h
new file mode 100644
index 0000000000..abe697c6fc
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h
@@ -0,0 +1,133 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k344evb.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __BOARDS_ARM_S32K3XX_S32K344EVB_SRC_S32K344EVB_H
+#define __BOARDS_ARM_S32K3XX_S32K344EVB_SRC_S32K344EVB_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <stdint.h>
+
+#include "hardware/s32k344_pinmux.h"
+#include "s32k3xx_periphclocks.h"
+#include "s32k3xx_pin.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* S32K344EVB GPIOs *********************************************************/
+
+/* LEDs. The S32K344EVB has two RGB LEDs:
+ *
+ * RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12)
+ * GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13)
+ * BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0)
+ *
+ * RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1)
+ * GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6)
+ * BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8)
+ *
+ * An output of '1' illuminates the LED.
+ */
+
+#define GPIO_LED0_R (PIN_PTA29 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED0_G (PIN_PTA30 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED0_B (PIN_PTA31 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+
+#define GPIO_LED1_R (PIN_PTB18 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED1_G (PIN_PTB25 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+#define GPIO_LED1_B (PIN_PTE12 | GPIO_LOWDRIVE | GPIO_OUTPUT_ZERO)
+
+/* Buttons. The S32K344EVB supports two buttons:
+ *
+ * SW0 PTB26 (EIRQ13 / WKPU41)
+ * SW1 PTB19 (WKPU38)
+ */
+
+#define GPIO_SW0 (PIN_WKPU41 | PIN_INT_BOTH)
+#define GPIO_SW1 (PIN_WKPU38 | PIN_INT_BOTH)
+
+/* Count of peripheral clock user configurations */
+
+#define NUM_OF_PERIPHERAL_CLOCKS_0 25
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* User peripheral configuration structure 0 */
+
+extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int s32k3xx_bringup(void);
+
+/****************************************************************************
+ * Name: s32k3xx_i2cdev_initialize
+ *
+ * Description:
+ * Initialize I2C driver and register /dev/i2cN devices.
+ *
+ ****************************************************************************/
+
+int s32k3xx_i2cdev_initialize(void);
+
+/****************************************************************************
+ * Name: s32k3xx_spidev_initialize
+ *
+ * Description:
+ * Configure chip select pins, initialize the SPI driver and register
+ * /dev/spiN devices.
+ *
+ ****************************************************************************/
+
+int s32k3xx_spidev_initialize(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM_S32K3XX_S32K344EVB_SRC_S32K344EVB_H */
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
new file mode 100644
index 0000000000..efbe5b9aa4
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+
+#include <stdint.h>
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+# define OK 0
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no meaning
+ * to NuttX; the meaning of the argument is a contract between the
+ * board-specific initialization logic and the matching application
+ * logic. The value could be such things as a mode enumeration
+ * value, a set of DIP switch settings, a pointer to configuration
+ * data read from a file or serial FLASH, or whatever you would like
+ * to do with it. Every implementation should accept zero/NULL as a
+ * default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
+
+ return OK;
+#else
+ /* Perform board-specific initialization */
+
+ return s32k3xx_bringup();
+#endif
+}
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c
new file mode 100644
index 0000000000..3d4b584c66
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c
@@ -0,0 +1,166 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_autoleds.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* The S32K344EVB has two RGB LEDs:
+ *
+ * RedLED0 PTA29 (EMIOS1 CH12 / EMIOS2 CH12)
+ * GreenLED0 PTA30 (EMIOS1 CH13 / EMIOS2 CH13)
+ * BlueLED0 PTA31 (EMIOS1 CH14 / FXIO D0)
+ *
+ * RedLED1 PTB18 (EMIOS1 CH15 / EMIOS2 CH14 / FXIO D1)
+ * GreenLED1 PTB25 (EMIOS1 CH21 / EMIOS2 CH21 / FXIO D6)
+ * BlueLED1 PTE12 (EMIOS1 CH5 / FXIO D8)
+ *
+ * An output of '1' illuminates the LED.
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the S32K344EVB. The following definitions describe how NuttX controls the
+ * LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ---------------- ------------------------ --------------------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ * LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ * LED_STACKCREATED Idle stack created OFF ON OFF
+ * LED_INIRQ In an interrupt (No change)
+ * LED_SIGNAL In a signal handler (No change)
+ * LED_ASSERTION An assertion failed (No change)
+ * LED_PANIC The system has crashed FLASH OFF OFF
+ * LED_IDLE S32K344 is in sleep mode (Optional, not used)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include "s32k344evb.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Summary of all possible settings */
+
+#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */
+#define LED_OFF_OFF_OFF 1 /* LED_STARTED */
+#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */
+#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */
+#define LED_ON_OFF_OFF 4 /* LED_PANIC */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k3xx_pinconfig(GPIO_LED0_R);
+ s32k3xx_pinconfig(GPIO_LED0_G);
+ s32k3xx_pinconfig(GPIO_LED0_B);
+
+ s32k3xx_pinconfig(GPIO_LED1_R);
+ s32k3xx_pinconfig(GPIO_LED1_G);
+ s32k3xx_pinconfig(GPIO_LED1_B);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+ if (led != LED_NOCHANGE)
+ {
+ bool redon = false;
+ bool greenon = false;
+ bool blueon = false;
+
+ switch (led)
+ {
+ default:
+ case LED_OFF_OFF_OFF:
+ break;
+
+ case LED_OFF_OFF_ON:
+ blueon = true;
+ break;
+
+ case LED_OFF_ON_OFF:
+ greenon = true;
+ break;
+
+ case LED_ON_OFF_OFF:
+ redon = true;
+ break;
+ }
+
+ /* An output of '1' illuminates the LED */
+
+ s32k3xx_gpiowrite(GPIO_LED0_R, redon);
+ s32k3xx_gpiowrite(GPIO_LED0_G, greenon);
+ s32k3xx_gpiowrite(GPIO_LED0_B, blueon);
+
+ s32k3xx_gpiowrite(GPIO_LED1_R, redon);
+ s32k3xx_gpiowrite(GPIO_LED1_G, greenon);
+ s32k3xx_gpiowrite(GPIO_LED1_B, blueon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+ if (led == LED_ON_OFF_OFF)
+ {
+ /* An output of '1' illuminates the LED */
+
+ s32k3xx_gpiowrite(GPIO_LED0_R, true);
+ s32k3xx_gpiowrite(GPIO_LED0_G, false);
+ s32k3xx_gpiowrite(GPIO_LED0_B, false);
+
+ s32k3xx_gpiowrite(GPIO_LED1_R, true);
+ s32k3xx_gpiowrite(GPIO_LED1_G, false);
+ s32k3xx_gpiowrite(GPIO_LED1_B, false);
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c
new file mode 100644
index 0000000000..40c4305a3d
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c
@@ -0,0 +1,77 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_board_initialize
+ *
+ * Description:
+ * All S32K3XX architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
+
+void s32k3xx_board_initialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected. */
+
+ board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
+
+ s32k3xx_bringup();
+}
+#endif
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c
new file mode 100644
index 0000000000..14915834a5
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c
@@ -0,0 +1,122 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <syslog.h>
+
+#ifdef CONFIG_INPUT_BUTTONS
+# include <nuttx/input/buttons.h>
+#endif
+
+#ifdef CONFIG_USERLED
+# include <nuttx/leds/userled.h>
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+# include <nuttx/fs/fs.h>
+#endif
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int s32k3xx_bringup(void)
+{
+ int ret = OK;
+
+#ifdef CONFIG_INPUT_BUTTONS
+ /* Register the BUTTON driver */
+
+ ret = btn_lower_initialize("/dev/buttons");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: btn_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_USERLED
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize("/dev/userleds");
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", ret);
+ }
+#endif
+
+#ifdef CONFIG_S32K3XX_LPI2C
+ /* Initialize I2C driver */
+
+ ret = s32k3xx_i2cdev_initialize();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: s32k3xx_i2cdev_initialize() failed: %d\n",
+ ret);
+ }
+#endif
+
+#ifdef CONFIG_S32K3XX_LPSPI
+ /* Initialize SPI driver */
+
+ ret = s32k3xx_spidev_initialize();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: s32k3xx_spidev_initialize() failed: %d\n",
+ ret);
+ }
+#endif
+
+ return ret;
+}
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c
new file mode 100644
index 0000000000..b4e0d7e9cc
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_buttons.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* The S32K344EVB supports two buttons:
+ *
+ * SW0 PTB26 (EIRQ13 / WKPU41)
+ * SW1 PTB19 (WKPU38)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <errno.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include <arch/board/board.h>
+
+#include "s32k344evb.h"
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_button_initialize
+ *
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ ****************************************************************************/
+
+uint32_t board_button_initialize(void)
+{
+ /* Configure the GPIO pins as interrupting inputs */
+
+ s32k3xx_pinconfig(GPIO_SW0);
+ s32k3xx_pinconfig(GPIO_SW1);
+
+ return NUM_BUTTONS;
+}
+
+/****************************************************************************
+ * Name: board_buttons
+ ****************************************************************************/
+
+uint32_t board_buttons(void)
+{
+ uint32_t ret = 0;
+
+ if (s32k3xx_gpioread(GPIO_SW0))
+ {
+ ret |= BUTTON_SW0_BIT;
+ }
+
+ if (s32k3xx_gpioread(GPIO_SW1))
+ {
+ ret |= BUTTON_SW1_BIT;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_ARCH_IRQBUTTONS
+/****************************************************************************
+ * Button support.
+ *
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ * After board_button_initialize() has been called, board_buttons() may be
+ * called to collect the state of all buttons. board_buttons() returns a
+ * 32-bit bit set with each bit associated with a button. See the
+ * BUTTON_*_BIT definitions in board.h for the meaning of each bit.
+ *
+ * board_button_irq() may be called to register an interrupt handler that
+ * will be called when a button is pressed or released. The ID value is a
+ * button enumeration value that uniquely identifies a button resource.
+ * See the BUTTON_* definitions in board.h for the meaning of enumeration
+ * value.
+ *
+ ****************************************************************************/
+
+int board_button_irq(int id, xcpt_t irqhandler, void *arg)
+{
+ uint32_t pinset;
+ int ret;
+
+ /* Map the button id to the GPIO bit set */
+
+ if (id == BUTTON_SW0)
+ {
+ pinset = GPIO_SW0;
+ }
+ else if (id == BUTTON_SW1)
+ {
+ pinset = GPIO_SW1;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ /* The button has already been configured as an interrupting input (by
+ * board_button_initialize() above).
+ *
+ * Attach the new button handler.
+ */
+
+ ret = s32k3xx_pinirqattach(pinset, irqhandler, NULL);
+ if (ret >= 0)
+ {
+ /* Then make sure that interrupts are enabled on the pin */
+
+ s32k3xx_pinirqenable(pinset);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_ARCH_IRQBUTTONS */
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c
new file mode 100644
index 0000000000..b52e88670c
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c
@@ -0,0 +1,157 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "s32k3xx_clockconfig.h"
+#include "s32k3xx_start.h"
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K3XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .cgm =
+ {
+ .sirc =
+ {
+ .range = CGM_FIRC_RANGE_32K, /* Slow IRC is trimmed to 32 kHz */
+ },
+ .firc =
+ {
+ .range = CGM_FIRC_RANGE_HIGH, /* RANGE */
+ .div = CGM_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ },
+ .scs =
+ {
+ .scs_source = CGM_SCS_SOURCE_PLL_PHI0,
+ .core_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .aips_plat_clk =
+ {
+ .div = CGM_MUX_DIV_BY_2,
+ .trigger = false,
+ },
+ .aips_slow_clk =
+ {
+ .div = CGM_MUX_DIV_SLOW_BY_4,
+ .trigger = false,
+ },
+ .hse_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .dcm_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .lbist_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+#ifdef CONFIG_S32K3XX_QSPI
+ .qspi_mem_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+#endif
+ .mux_3 =
+ {
+ .source = CGM_CLK_SRC_AIPS_PLAT_CLK,
+ .div = CGM_MUX_DIV_BY_2,
+ },
+#ifdef CONFIG_S32K3XX_ENET
+ .mux_7_emac_rx =
+ {
+ .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK,
+ .div = CGM_MUX_DIV_BY_2,
+ },
+ .mux_8_emac_tx =
+ {
+ .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK,
+ .div = CGM_MUX_DIV_BY_2,
+ },
+ .mux_9_emac_ts =
+ {
+ .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK,
+ .div = CGM_MUX_DIV_BY_2, /* FIXME check div value */
+ },
+#endif
+#ifdef CONFIG_S32K3XX_QSPI
+ .mux_10_qspi_sfck =
+ {
+ .source = CGM_CLK_SRC_PLL_PHI1_CLK,
+ .div = CGM_MUX_DIV_BY_2,
+ },
+#endif
+ },
+ .pll =
+ {
+ .modul_freq = 0,
+ .modul_depth = 0,
+ .core_pll_power = true,
+ .modulation_type = false,
+ .sigma_delta = CGM_PLL_SIGMA_DELTA,
+ .enable_dither = false,
+ .mode = CGM_PLL_INTEGER_MODE,
+ .prediv = 4,
+ .mult = 240,
+ .postdiv = 2,
+ .phi0 = CGM_PLL_PHI_DIV_BY_3,
+ .phi1 = CGM_PLL_PHI_DIV_BY_3,
+ },
+ .clkout =
+ {
+ .source = CGM_CLK_SRC_AIPS_SLOW_CLK,
+ .div = CGM_CLKOUT_DIV_BY_1,
+ }
+ },
+ .pcc =
+ {
+ .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number of peripheral clock configurations */
+ .pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
+ },
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c
new file mode 100644
index 0000000000..727c1bd711
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c
@@ -0,0 +1,104 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_i2c.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/i2c/i2c_master.h>
+
+#include "s32k3xx_lpi2c.h"
+
+#include "s32k344evb.h"
+
+#ifdef CONFIG_S32K3XX_LPI2C
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_i2cdev_initialize
+ *
+ * Description:
+ * Initialize I2C driver and register /dev/i2cN devices.
+ *
+ ****************************************************************************/
+
+int weak_function s32k3xx_i2cdev_initialize(void)
+{
+ int ret = OK;
+
+#if defined(CONFIG_S32K3XX_LPI2C0) && defined(CONFIG_I2C_DRIVER)
+ /* LPI2C0 *****************************************************************/
+
+ /* Initialize the I2C driver for LPI2C0 */
+
+ struct i2c_master_s *lpi2c0 = s32k3xx_i2cbus_initialize(0);
+ if (lpi2c0 == NULL)
+ {
+ i2cerr("ERROR: FAILED to initialize LPI2C0\n");
+ return -ENODEV;
+ }
+
+ ret = i2c_register(lpi2c0, 0);
+ if (ret < 0)
+ {
+ i2cerr("ERROR: FAILED to register LPI2C0 driver\n");
+ s32k3xx_i2cbus_uninitialize(lpi2c0);
+ return ret;
+ }
+#endif /* CONFIG_S32K3XX_LPI2C0 && CONFIG_I2C_DRIVER */
+
+#if defined(CONFIG_S32K3XX_LPI2C1) && defined(CONFIG_I2C_DRIVER)
+ /* LPI2C1 *****************************************************************/
+
+ /* Initialize the I2C driver for LPI2C1 */
+
+ struct i2c_master_s *lpi2c1 = s32k3xx_i2cbus_initialize(1);
+ if (lpi2c1 == NULL)
+ {
+ i2cerr("ERROR: FAILED to initialize LPI2C1\n");
+ return -ENODEV;
+ }
+
+ ret = i2c_register(lpi2c1, 0);
+ if (ret < 0)
+ {
+ i2cerr("ERROR: FAILED to register LPI2C1 driver\n");
+ s32k3xx_i2cbus_uninitialize(lpi2c1);
+ return ret;
+ }
+#endif /* CONFIG_S32K3XX_LPI2C1 && CONFIG_I2C_DRIVER */
+
+ return ret;
+}
+
+#endif /* CONFIG_S32K3XX_LPI2C */
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c
new file mode 100644
index 0000000000..85a3ad1469
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c
@@ -0,0 +1,250 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_periphclocks.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "s32k3xx_clocknames.h"
+#include "s32k3xx_periphclocks.h"
+
+#include "s32k344evb.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K3XX board must provide the following initialized structure.
+ * This is needed to establish the initial peripheral clocking.
+ */
+
+const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
+{
+ {
+ .clkname = LPI2C0_CLK,
+#ifdef CONFIG_S32K3XX_LPI2C0
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPI2C1_CLK,
+#ifdef CONFIG_S32K3XX_LPI2C1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI0_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI0
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI1_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI2_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI2
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI3_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI3
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI4_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI4
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI5_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI5
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART0_CLK,
+#ifdef CONFIG_S32K3XX_LPUART0
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART1_CLK,
+#ifdef CONFIG_S32K3XX_LPUART1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART2_CLK,
+#ifdef CONFIG_S32K3XX_LPUART2
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART3_CLK,
+#ifdef CONFIG_S32K3XX_LPUART3
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART4_CLK,
+#ifdef CONFIG_S32K3XX_LPUART4
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART5_CLK,
+#ifdef CONFIG_S32K3XX_LPUART5
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART6_CLK,
+#ifdef CONFIG_S32K3XX_LPUART6
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART7_CLK,
+#ifdef CONFIG_S32K3XX_LPUART7
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART8_CLK,
+#ifdef CONFIG_S32K3XX_LPUART8
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART9_CLK,
+#ifdef CONFIG_S32K3XX_LPUART9
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART10_CLK,
+#ifdef CONFIG_S32K3XX_LPUART10
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART11_CLK,
+#ifdef CONFIG_S32K3XX_LPUART11
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART12_CLK,
+#ifdef CONFIG_S32K3XX_LPUART12
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART13_CLK,
+#ifdef CONFIG_S32K3XX_LPUART13
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART14_CLK,
+#ifdef CONFIG_S32K3XX_LPUART14
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART15_CLK,
+#ifdef CONFIG_S32K3XX_LPUART15
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = WKPU_CLK,
+#ifdef CONFIG_S32K3XX_WKPUINTS
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c
new file mode 100644
index 0000000000..a9db32aa1e
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c
@@ -0,0 +1,366 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_spi.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <nuttx/spi/spi_transfer.h>
+
+#include "s32k3xx_pin.h"
+#include "s32k3xx_lpspi.h"
+
+#include <arch/board/board.h>
+
+#include "s32k344evb.h"
+
+#ifdef CONFIG_S32K3XX_FS26
+#include "s32k3xx_fs26.h"
+#endif
+
+#ifdef CONFIG_S32K3XX_LPSPI
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_spidev_initialize
+ *
+ * Description:
+ * Configure chip select pins, initialize the SPI driver and register
+ * /dev/spiN devices.
+ *
+ ****************************************************************************/
+
+int weak_function s32k3xx_spidev_initialize(void)
+{
+ int ret = OK;
+
+#ifdef CONFIG_S32K3XX_LPSPI0
+ /* LPSPI0 *****************************************************************/
+
+ /* Configure LPSPI0 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI0_PCS);
+
+ /* Initialize the SPI driver for LPSPI0 */
+
+ struct spi_dev_s *g_lpspi0 = s32k3xx_lpspibus_initialize(0);
+ if (g_lpspi0 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI0\n");
+ return -ENODEV;
+ }
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi0, 0);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI0 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+
+# ifdef CONFIG_S32K3XX_FS26
+ fs26_initialize(g_lpspi0);
+# endif
+
+#endif /* CONFIG_S32K3XX_LPSPI0 */
+
+#ifdef CONFIG_S32K3XX_LPSPI1
+ /* LPSPI1 *****************************************************************/
+
+ /* Configure LPSPI1 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI1_PCS);
+
+ /* Initialize the SPI driver for LPSPI1 */
+
+ struct spi_dev_s *g_lpspi1 = s32k3xx_lpspibus_initialize(1);
+ if (g_lpspi1 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI1\n");
+ return -ENODEV;
+ }
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi1, 1);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI1 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI1 */
+
+#ifdef CONFIG_S32K3XX_LPSPI2
+ /* LPSPI2 *****************************************************************/
+
+ /* Configure LPSPI2 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI2_PCS);
+
+ /* Initialize the SPI driver for LPSPI2 */
+
+ struct spi_dev_s *g_lpspi2 = s32k3xx_lpspibus_initialize(2);
+ if (g_lpspi2 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI2\n");
+ return -ENODEV;
+ }
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi2, 2);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI2 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI2 */
+
+#ifdef CONFIG_S32K3XX_LPSPI3
+ /* LPSPI3 *****************************************************************/
+
+ /* Configure LPSPI3 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI3_PCS);
+
+ /* Initialize the SPI driver for LPSPI3 */
+
+ struct spi_dev_s *g_lpspi3 = s32k3xx_lpspibus_initialize(3);
+ if (g_lpspi3 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI3\n");
+ return -ENODEV;
+ }
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi3, 3);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI3 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI3 */
+
+#ifdef CONFIG_S32K3XX_LPSPI4
+ /* LPSPI4 *****************************************************************/
+
+ /* Configure LPSPI4 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI4_PCS);
+
+ /* Initialize the SPI driver for LPSPI4 */
+
+ struct spi_dev_s *g_lpspi4 = s32k3xx_lpspibus_initialize(4);
+ if (g_lpspi4 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI4\n");
+ return -ENODEV;
+ }
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi4, 4);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI4 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI4 */
+
+#ifdef CONFIG_S32K3XX_LPSPI5
+ /* LPSPI5 *****************************************************************/
+
+ /* Configure LPSPI5 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI5_PCS);
+
+ /* Initialize the SPI driver for LPSPI5 */
+
+ struct spi_dev_s *g_lpspi5 = s32k3xx_lpspibus_initialize(5);
+ if (g_lpspi5 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI5\n");
+ return -ENODEV;
+ }
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi5, 5);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI5 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI5 */
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: s32k3xx_lpspiNselect and s32k3xx_lpspiNstatus
+ *
+ * Description:
+ * The external functions, s32k3xx_lpspiNselect and s32k3xx_lpspiNstatus
+ * must be provided by board-specific logic. They are implementations of
+ * the select and status methods of the SPI interface defined by struct
+ * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including
+ * s32k3xx_lpspibus_initialize()) are provided by common logic. To use
+ * this common SPI logic on your board:
+ *
+ * 1. Provide logic in s32k3xx_boardinitialize() to configure SPI chip
+ * select pins.
+ * 2. Provide s32k3xx_lpspiNselect() and s32k3xx_lpspiNstatus() functions
+ * in your board-specific logic. These functions will perform chip
+ * selection and status operations using GPIOs in the way your board is
+ * configured.
+ * 3. Add a calls to s32k3xx_lpspibus_initialize() in your low level
+ * application initialization logic.
+ * 4. The handle returned by s32k3xx_lpspibus_initialize() may then be used
+ * to bind the SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_S32K3XX_LPSPI0
+/* LPSPI0 *******************************************************************/
+
+void s32k3xx_lpspi0select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI0_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi0status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI0 */
+
+#ifdef CONFIG_S32K3XX_LPSPI1
+/* LPSPI1 *******************************************************************/
+
+void s32k3xx_lpspi1select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI1_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi1status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI1 */
+
+#ifdef CONFIG_S32K3XX_LPSPI2
+/* LPSPI2 *******************************************************************/
+
+void s32k3xx_lpspi2select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI2_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi2status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI2 */
+
+#ifdef CONFIG_S32K3XX_LPSPI3
+/* LPSPI3 *******************************************************************/
+
+void s32k3xx_lpspi3select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI3_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi3status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI3 */
+
+#ifdef CONFIG_S32K3XX_LPSPI4
+/* LPSPI4 *******************************************************************/
+
+void s32k3xx_lpspi4select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI4_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi4status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI4 */
+
+#ifdef CONFIG_S32K3XX_LPSPI5
+/* LPSPI5 *******************************************************************/
+
+void s32k3xx_lpspi5select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI5_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi5status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI5 */
+#endif /* CONFIG_S32K3XX_LPSPI */
diff --git a/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
new file mode 100644
index 0000000000..daceb4fb28
--- /dev/null
+++ b/boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
@@ -0,0 +1,124 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/s32k344evb/src/s32k3xx_userleds.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include <arch/board/board.h>
+
+#include "s32k344evb.h"
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+uint32_t board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k3xx_pinconfig(GPIO_LED0_R);
+ s32k3xx_pinconfig(GPIO_LED0_G);
+ s32k3xx_pinconfig(GPIO_LED0_B);
+
+ s32k3xx_pinconfig(GPIO_LED1_R);
+ s32k3xx_pinconfig(GPIO_LED1_G);
+ s32k3xx_pinconfig(GPIO_LED1_B);
+
+ return BOARD_NLEDS;
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ uint32_t ledcfg;
+
+ if (led == BOARD_LED0_R)
+ {
+ ledcfg = GPIO_LED0_R;
+ }
+ else if (led == BOARD_LED0_G)
+ {
+ ledcfg = GPIO_LED0_G;
+ }
+ else if (led == BOARD_LED0_B)
+ {
+ ledcfg = GPIO_LED0_B;
+ }
+ else if (led == BOARD_LED1_R)
+ {
+ ledcfg = GPIO_LED1_R;
+ }
+ else if (led == BOARD_LED1_G)
+ {
+ ledcfg = GPIO_LED1_G;
+ }
+ else if (led == BOARD_LED1_B)
+ {
+ ledcfg = GPIO_LED1_B;
+ }
+ else
+ {
+ return;
+ }
+
+ /* An output of '1' illuminates the LED */
+
+ s32k3xx_gpiowrite(ledcfg, ledon);
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint32_t ledset)
+{
+ /* An output of '1' illuminates the LED */
+
+ s32k3xx_gpiowrite(GPIO_LED0_R, (ledset & BOARD_LED0_R_BIT) != 0);
+ s32k3xx_gpiowrite(GPIO_LED0_G, (ledset & BOARD_LED0_G_BIT) != 0);
+ s32k3xx_gpiowrite(GPIO_LED0_B, (ledset & BOARD_LED0_B_BIT) != 0);
+
+ s32k3xx_gpiowrite(GPIO_LED1_R, (ledset & BOARD_LED1_R_BIT) != 0);
+ s32k3xx_gpiowrite(GPIO_LED1_G, (ledset & BOARD_LED1_G_BIT) != 0);
+ s32k3xx_gpiowrite(GPIO_LED1_B, (ledset & BOARD_LED1_B_BIT) != 0);
+}
+
+#endif /* !CONFIG_ARCH_LEDS */
[incubator-nuttx] 05/09: NXP S32K3XX: add initial support for NXP MR-CANHUBK3 board
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 7f3fc23dd6d78a6c0e56d6209b2f20d3c1c7fb6e
Author: Jari van Ewijk <ja...@nxp.com>
AuthorDate: Fri Jul 22 10:32:05 2022 +0200
NXP S32K3XX: add initial support for NXP MR-CANHUBK3 board
Co-authored-by: Peter van der Perk <pe...@nxp.com>
---
boards/Kconfig | 14 +
boards/arm/s32k3xx/mr-canhubk3/Kconfig | 24 ++
boards/arm/s32k3xx/mr-canhubk3/README.txt | 116 ++++++
.../arm/s32k3xx/mr-canhubk3/configs/net/defconfig | 113 +++++
.../arm/s32k3xx/mr-canhubk3/configs/nsh/defconfig | 52 +++
boards/arm/s32k3xx/mr-canhubk3/include/board.h | 324 ++++++++++++++
boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs | 49 +++
boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld | 159 +++++++
boards/arm/s32k3xx/mr-canhubk3/src/Makefile | 62 +++
boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h | 147 +++++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c | 82 ++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c | 150 +++++++
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c | 82 ++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c | 320 ++++++++++++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c | 154 +++++++
.../s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c | 162 +++++++
.../s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c | 105 +++++
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c | 105 +++++
.../s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c | 258 ++++++++++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c | 464 +++++++++++++++++++++
boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c | 376 +++++++++++++++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c | 334 +++++++++++++++
.../arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c | 103 +++++
23 files changed, 3755 insertions(+)
diff --git a/boards/Kconfig b/boards/Kconfig
index 63b5baf381..12d27a8853 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -1620,6 +1620,16 @@ config ARCH_BOARD_S32K344EVB
This options selects support for NuttX on the NXP S32K344EVB board
featuring the S32K344 Cortex-M7.
+config ARCH_BOARD_MR_CANHUBK3
+ bool "NXP MR-CANHUBK3"
+ depends on ARCH_CHIP_S32K344
+ select ARCH_HAVE_LEDS
+ select ARCH_HAVE_BUTTONS
+ select ARCH_HAVE_IRQBUTTONS
+ ---help---
+ This options selects support for NuttX on the NXP MR-CANHUBK3 board
+ featuring the S32K344 Cortex-M7.
+
config ARCH_BOARD_SABRE_6QUAD
bool "NXP/Freescale i.MX6 Sabre-6Quad board"
depends on ARCH_CHIP_IMX6_6QUAD
@@ -2680,6 +2690,7 @@ config ARCH_BOARD
default "ucans32k146" if ARCH_BOARD_UCANS32K146
default "s32k148evb" if ARCH_BOARD_S32K148EVB
default "s32k344evb" if ARCH_BOARD_S32K344EVB
+ default "mr-canhubk3" if ARCH_BOARD_MR_CANHUBK3
default "rv32m1-vega" if ARCH_BOARD_RV32M1_VEGA
default "rv-virt" if ARCH_BOARD_QEMU_RV_VIRT
default "sabre-6quad" if ARCH_BOARD_SABRE_6QUAD
@@ -2856,6 +2867,9 @@ endif
if ARCH_BOARD_S32K344EVB
source "boards/arm/s32k3xx/s32k344evb/Kconfig"
endif
+if ARCH_BOARD_MR_CANHUBK3
+source "boards/arm/s32k3xx/mr-canhubk3/Kconfig"
+endif
if ARCH_BOARD_SABRE_6QUAD
source "boards/arm/imx6/sabre-6quad/Kconfig"
endif
diff --git a/boards/arm/s32k3xx/mr-canhubk3/Kconfig b/boards/arm/s32k3xx/mr-canhubk3/Kconfig
new file mode 100644
index 0000000000..a4355bffbc
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/Kconfig
@@ -0,0 +1,24 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_MR_CANHUBK3
+
+config S32K3XX_TJA1153
+ bool "TJA1153 Initialization Sequence"
+ default n
+ depends on S32K3XX_FLEXCAN
+ ---help---
+ Enables a basic NXP TJA1153 initialization routine to
+ configure the CAN PHY to allow all incoming and outgoing traffic.
+
+config S32K3XX_SELFTEST
+ bool "MR-CANHUBK3 Board Self-Test"
+ default n
+ ---help---
+ Run basic routines to verify that all board components are up and
+ running. Results are send to the syslog, it is recommended to
+ enable all output levels (error, warning and info).
+
+endif # ARCH_BOARD_MR_CANHUBK3
diff --git a/boards/arm/s32k3xx/mr-canhubk3/README.txt b/boards/arm/s32k3xx/mr-canhubk3/README.txt
new file mode 100644
index 0000000000..3fe2805aab
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/README.txt
@@ -0,0 +1,116 @@
+README
+======
+
+This directory holds the port to the NXP MR-CANHUBK3 board.
+
+Contents
+========
+
+ o Status
+ o Serial Console
+ o LEDs and Buttons
+ o Configurations
+
+Status
+======
+
+ 2021-09-28: Configuration created (copy-paste from S32K344EVB).
+ Remains untested, because hardware is not available yet.
+
+ TODO: Need to calibrate the delay loop. The current value of
+ CONFIG_BOARD_LOOPSPERMSEC is a bogus value retained from a copy-paste
+ (see apps/examples/calib_udelay).
+
+Serial Console
+==============
+
+ By default, the serial console will be provided on the DCD-LZ UART
+ (available on the 7-pin DCD-LZ debug connector P6):
+
+ DCD-LZ UART RX PTA8 (LPUART2_RX)
+ DCD-LZ UART TX PTA9 (LPUART2_TX)
+
+LEDs and Buttons
+================
+
+ LEDs
+ ----
+ The MR-CANHUBK3 has one RGB LED:
+
+ RedLED PTE14 (FXIO D7 / EMIOS0 CH19)
+ GreenLED PTA27 (FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10)
+ BlueLED PTE12 (FXIO D8 / EMIOS1 CH5)
+
+ An output of '0' illuminates the LED.
+
+ If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
+ any way. The following definitions are used to access individual RGB
+ components (see mr-canhubk3.h):
+
+ GPIO_LED_R
+ GPIO_LED_G
+ GPIO_LED_B
+
+ The RGB components could, alternatively, be controlled through PWM using
+ the common RGB LED driver.
+
+ If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
+ the MR-CANHUBK3. The following definitions describe how NuttX controls the
+ LEDs:
+
+ ==========================================+========+========+=========
+ RED GREEN BLUE
+ ==========================================+========+========+=========
+
+ LED_STARTED NuttX has been started OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ LED_STACKCREATED Idle stack created OFF ON OFF
+ LED_INIRQ In an interrupt (no change)
+ LED_SIGNAL In a signal handler (no change)
+ LED_ASSERTION An assertion failed (no change)
+ LED_PANIC The system has crashed FLASH OFF OFF
+ LED_IDLE S32K344 in sleep mode (no change)
+ ==========================================+========+========+=========
+
+ Buttons
+ -------
+ The MR-CANHUBK3 supports two buttons:
+
+ SW1 PTD15 (EIRQ31)
+ SW2 PTA25 (EIRQ5 / WKPU34)
+
+Configurations
+==============
+
+ Common Information
+ ------------------
+ Each MR-CANHUBK3 configuration is maintained in a sub-directory and can be
+ selected as follows:
+
+ tools/configure.sh mr-canhubk3:<subdir>
+
+ Where <subdir> is one of the sub-directories listed in the next paragraph.
+
+ NOTES (common for all configurations):
+
+ 1. This configuration uses the mconf-based configuration tool. To change
+ this configuration using that tool, you should:
+
+ a. Build and install the kconfig-mconf tool. See nuttx/README.txt.
+ Also see additional README.txt files in the NuttX tools repository.
+
+ b. Execute 'make menuconfig' in nuttx/ in order to start the
+ reconfiguration process.
+
+ 2. Unless otherwise stated, the serial console used is LPUART1 at
+ 115,200 8N1. This corresponds to the OpenSDA VCOM port.
+
+ Configuration Sub-directories
+ -----------------------------
+
+ nsh:
+ ---
+ Configures the NuttShell (nsh) located at apps/examples/nsh. Support
+ for builtin applications is enabled, but in the base configuration the
+ only application selected is the "Hello, World!" example.
diff --git a/boards/arm/s32k3xx/mr-canhubk3/configs/net/defconfig b/boards/arm/s32k3xx/mr-canhubk3/configs/net/defconfig
new file mode 100644
index 0000000000..e5a33c4690
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/configs/net/defconfig
@@ -0,0 +1,113 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+# CONFIG_NSH_DISABLE_DATE is not set
+CONFIG_ALLOW_GPL_COMPONENTS=y
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="mr-canhubk3"
+CONFIG_ARCH_BOARD_MR_CANHUBK3=y
+CONFIG_ARCH_BUTTONS=y
+CONFIG_ARCH_CHIP="s32k3xx"
+CONFIG_ARCH_CHIP_S32K344=y
+CONFIG_ARCH_CHIP_S32K3XX=y
+CONFIG_ARCH_IRQBUTTONS=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=14539
+CONFIG_BUILTIN=y
+CONFIG_CANUTILS_CANDUMP=y
+CONFIG_CANUTILS_CANSEND=y
+CONFIG_EXAMPLES_BUTTONS=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_EXAMPLES_TELNETD=y
+CONFIG_FLEXCAN0_ARBI_BITRATE=500000
+CONFIG_FLEXCAN0_DATA_BITRATE=2000000
+CONFIG_FLEXCAN1_ARBI_BITRATE=500000
+CONFIG_FLEXCAN1_DATA_BITRATE=2000000
+CONFIG_FLEXCAN2_ARBI_BITRATE=500000
+CONFIG_FLEXCAN2_DATA_BITRATE=2000000
+CONFIG_FLEXCAN3_ARBI_BITRATE=500000
+CONFIG_FLEXCAN3_DATA_BITRATE=2000000
+CONFIG_FLEXCAN4_ARBI_BITRATE=500000
+CONFIG_FLEXCAN4_DATA_BITRATE=2000000
+CONFIG_FLEXCAN5_ARBI_BITRATE=500000
+CONFIG_FLEXCAN5_DATA_BITRATE=2000000
+CONFIG_FS_LITTLEFS=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_INPUT=y
+CONFIG_INPUT_BUTTONS=y
+CONFIG_INPUT_BUTTONS_LOWER=y
+CONFIG_LPUART2_SERIAL_CONSOLE=y
+CONFIG_MM_REGIONS=2
+CONFIG_MTD=y
+CONFIG_MTD_MX25RXX=y
+CONFIG_MX25RXX_LXX=y
+CONFIG_NET=y
+CONFIG_NETDEV_IFINDEX=y
+CONFIG_NETDEV_LATEINIT=y
+CONFIG_NETUTILS_PING=y
+CONFIG_NETUTILS_TELNETD=y
+CONFIG_NET_CAN=y
+CONFIG_NET_CAN_EXTID=y
+CONFIG_NET_CAN_NOTIFIER=y
+CONFIG_NET_CAN_SOCK_OPTS=y
+CONFIG_NET_ICMP=y
+CONFIG_NET_TCP=y
+CONFIG_NET_TIMESTAMP=y
+CONFIG_NET_UDP=y
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=272000
+CONFIG_RAM_START=0x20400000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_S32K3XX_DTCM_HEAP=y
+CONFIG_S32K3XX_EIRQINTS=y
+CONFIG_S32K3XX_ENET=y
+CONFIG_S32K3XX_FLEXCAN0=y
+CONFIG_S32K3XX_FLEXCAN1=y
+CONFIG_S32K3XX_FLEXCAN2=y
+CONFIG_S32K3XX_FLEXCAN3=y
+CONFIG_S32K3XX_FLEXCAN4=y
+CONFIG_S32K3XX_FLEXCAN5=y
+CONFIG_S32K3XX_FS26=y
+CONFIG_S32K3XX_GPIOIRQ=y
+CONFIG_S32K3XX_LPI2C0=y
+CONFIG_S32K3XX_LPI2C1=y
+CONFIG_S32K3XX_LPSPI3=y
+CONFIG_S32K3XX_LPSPI3_PINCFG=3
+CONFIG_S32K3XX_LPUART0=y
+CONFIG_S32K3XX_LPUART10=y
+CONFIG_S32K3XX_LPUART13=y
+CONFIG_S32K3XX_LPUART14=y
+CONFIG_S32K3XX_LPUART1=y
+CONFIG_S32K3XX_LPUART2=y
+CONFIG_S32K3XX_LPUART9=y
+CONFIG_S32K3XX_QSPI=y
+CONFIG_S32K3XX_TJA1153=y
+CONFIG_SCHED_LPWORK=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SPI_DRIVER=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2022
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_NSH=y
+CONFIG_TIMER=y
diff --git a/boards/arm/s32k3xx/mr-canhubk3/configs/nsh/defconfig b/boards/arm/s32k3xx/mr-canhubk3/configs/nsh/defconfig
new file mode 100644
index 0000000000..1a4263f711
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/configs/nsh/defconfig
@@ -0,0 +1,52 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_ARCH_FPU is not set
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="arm"
+CONFIG_ARCH_BOARD="mr-canhubk3"
+CONFIG_ARCH_BOARD_MR_CANHUBK3=y
+CONFIG_ARCH_CHIP="s32k3xx"
+CONFIG_ARCH_CHIP_S32K344=y
+CONFIG_ARCH_CHIP_S32K3XX=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARMV7M_DCACHE=y
+CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y
+CONFIG_ARMV7M_DTCM=y
+CONFIG_ARMV7M_ICACHE=y
+CONFIG_BOARD_LOOPSPERMSEC=14539
+CONFIG_BUILTIN=y
+CONFIG_EXAMPLES_HELLO=y
+CONFIG_FS_PROCFS=y
+CONFIG_HAVE_CXX=y
+CONFIG_HAVE_CXXINITIALIZE=y
+CONFIG_INIT_ENTRYPOINT="nsh_main"
+CONFIG_LPUART2_SERIAL_CONSOLE=y
+CONFIG_MM_REGIONS=2
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_PREALLOC_TIMERS=4
+CONFIG_RAM_SIZE=272000
+CONFIG_RAM_START=0x20400000
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_S32K3XX_DTCM_HEAP=y
+CONFIG_S32K3XX_FS26=y
+CONFIG_S32K3XX_LPSPI3=y
+CONFIG_S32K3XX_LPSPI3_PINCFG=3
+CONFIG_S32K3XX_LPUART2=y
+CONFIG_SCHED_WAITPID=y
+CONFIG_SPI_DRIVER=y
+CONFIG_START_DAY=30
+CONFIG_START_MONTH=5
+CONFIG_START_YEAR=2022
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+CONFIG_SYSTEM_NSH=y
diff --git a/boards/arm/s32k3xx/mr-canhubk3/include/board.h b/boards/arm/s32k3xx/mr-canhubk3/include/board.h
new file mode 100644
index 0000000000..0c59590fda
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/include/board.h
@@ -0,0 +1,324 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/include/board.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __BOARDS_ARM_S32K3XX_MR_CANHUBK3_INCLUDE_BOARD_H
+#define __BOARDS_ARM_S32K3XX_MR_CANHUBK3_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Clocking *****************************************************************/
+
+/* The MR-CANHUBK3 is fitted with a 16 MHz crystal */
+
+#define BOARD_XTAL_FREQUENCY 16000000
+
+/* The S32K344 will run at 160 MHz */
+
+#define MR_CANHUBK3_SYSCLK_FREQUENCY 160000000
+
+/* MX25L QuadSPI Flash ******************************************************/
+
+#ifdef CONFIG_S32K3XX_QSPI
+# ifdef CONFIG_MTD_MX25RXX
+# define HAVE_MX25L
+# ifdef CONFIG_FS_LITTLEFS
+# define HAVE_MX25L_LITTLEFS
+# else
+# ifdef CONFIG_FS_NXFFS
+# define HAVE_MX25L_NXFFS
+# else
+# define HAVE_MX25L_CHARDEV
+# endif
+# endif
+# endif
+#endif
+
+#define MX25L_MTD_MINOR 0
+#define MX25L_SMART_MINOR 0
+
+/* LED definitions **********************************************************/
+
+/* The MR-CANHUBK3 has one RGB LED:
+ *
+ * RedLED PTE14 (FXIO D7 / EMIOS0 CH19)
+ * GreenLED PTA27 (FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10)
+ * BlueLED PTE12 (FXIO D8 / EMIOS1 CH5)
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
+ * any way. The following definitions are used to access individual RGB
+ * components.
+ *
+ * The RGB components could, alternatively be controlled through PWM using
+ * the common RGB LED driver.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED_R 0
+#define BOARD_LED_G 1
+#define BOARD_LED_B 2
+#define BOARD_NLEDS 3
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED_R_BIT (1 << BOARD_LED_R)
+#define BOARD_LED_G_BIT (1 << BOARD_LED_G)
+#define BOARD_LED_B_BIT (1 << BOARD_LED_B)
+
+/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LEDs on board
+ * the MR-CANHUBK3. The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ---------------- ----------------------------- -------------------
+ */
+
+#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */
+#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */
+#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */
+#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */
+#define LED_INIRQ 0 /* In an interrupt (No change) */
+#define LED_SIGNAL 0 /* In a signal handler (No change) */
+#define LED_ASSERTION 0 /* An assertion failed (No change) */
+#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */
+#undef LED_IDLE /* S32K344 is in sleep mode (Not used) */
+
+/* Button definitions *******************************************************/
+
+/* The MR-CANHUBK3 supports two buttons:
+ *
+ * SW1 PTD15 (EIRQ31)
+ * SW2 PTA25 (EIRQ5 / WKPU34)
+ */
+
+#define BUTTON_SW1 0
+#define BUTTON_SW2 1
+#define NUM_BUTTONS 2
+
+#define BUTTON_SW1_BIT (1 << BUTTON_SW1)
+#define BUTTON_SW2_BIT (1 << BUTTON_SW2)
+
+/* UART selections **********************************************************/
+
+/* By default, the serial console will be provided on the DCD-LZ UART
+ * (available on the 7-pin DCD-LZ debug connector P6):
+ *
+ * DCD-LZ UART RX PTA8 (LPUART2_RX)
+ * DCD-LZ UART TX PTA9 (LPUART2_TX)
+ */
+
+#define PIN_LPUART2_RX PIN_LPUART2_RX_1 /* PTA8 */
+#define PIN_LPUART2_TX PIN_LPUART2_TX_1 /* PTA9 */
+
+/* LPUART0 P2 UART (with flow control) connector */
+
+#define PIN_LPUART0_CTS PIN_LPUART0_CTS_1 /* PTA0 */
+#define PIN_LPUART0_RTS PIN_LPUART0_RTS_1 /* PTA1 */
+#define PIN_LPUART0_RX PIN_LPUART0_RX_1 /* PTA2 */
+#define PIN_LPUART0_TX PIN_LPUART0_TX_1 /* PTA3 */
+
+/* LPUART1 P5 UART (with flow control) connector */
+
+#define PIN_LPUART1_CTS PIN_LPUART1_CTS_2 /* PTE2 */
+#define PIN_LPUART1_RTS PIN_LPUART1_RTS_2 /* PTE6 */
+#define PIN_LPUART1_RX PIN_LPUART1_RX_3 /* PTC6 */
+#define PIN_LPUART1_TX PIN_LPUART1_TX_3 /* PTC7 */
+
+/* LPUART9 P24 UART connector */
+
+#define PIN_LPUART9_RX PIN_LPUART9_RX_1 /* PTB2 */
+#define PIN_LPUART9_TX PIN_LPUART9_TX_1 /* PTB3 */
+
+/* LPUART10 P24 UART connector */
+
+#define PIN_LPUART10_RX PIN_LPUART10_RX_1 /* PTC12 */
+#define PIN_LPUART10_TX PIN_LPUART10_TX_1 /* PTC13 */
+
+/* LPUART13 P25 UART connector */
+
+#define PIN_LPUART13_RX PIN_LPUART13_RX_1 /* PTB19 */
+#define PIN_LPUART13_TX PIN_LPUART13_TX_1 /* PTB18 */
+
+/* LPUART14 P25 UART connector */
+
+#define PIN_LPUART14_RX PIN_LPUART14_RX_1 /* PTB21 */
+#define PIN_LPUART14_TX PIN_LPUART14_TX_1 /* PTB20 */
+
+/* SPI selections ***********************************************************/
+
+/* LPSPI1 P1A external SPI connector */
+
+#define PIN_LPSPI1_SCK PIN_LPSPI1_SCK_3 /* PTA28 */
+#define PIN_LPSPI1_MISO PIN_LPSPI1_SOUT_2 /* PTA30 */
+#define PIN_LPSPI1_MOSI PIN_LPSPI1_SIN_3 /* PTA29 */
+#define PIN_LPSPI1_PCS0 PIN_LPSPI1_PCS0_2 /* PTA21 */
+#define PIN_LPSPI1_PCS1 PIN_LPSPI1_PCS1_6 /* PTE4 */
+
+#define PIN_LPSPI1_PCS (PIN_PTA21 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE) /* PTA21 */
+
+/* LPSPI2 P1B external SPI connector */
+
+#define PIN_LPSPI2_SCK PIN_LPSPI2_SCK_1 /* PTB29 */
+#define PIN_LPSPI2_MISO PIN_LPSPI2_SOUT_3 /* PTB27 */
+#define PIN_LPSPI2_MOSI PIN_LPSPI2_SIN_2 /* PTB28 */
+#define PIN_LPSPI2_PCS0 PIN_LPSPI2_PCS0_2 /* PTB25 */
+#define PIN_LPSPI2_PCS1 PIN_LPSPI2_PCS1_3 /* PTC19 */
+
+#define PIN_LPSPI2_PCS (PIN_PTB25 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE) /* PTB25 */
+
+/* LPSPI3 FS26 Safety SBC */
+
+#define PIN_LPSPI3_SCK PIN_LPSPI3_SCK_2 /* PTD1 */
+#define PIN_LPSPI3_MISO PIN_LPSPI3_SOUT_2 /* PTD0 */
+#define PIN_LPSPI3_MOSI PIN_LPSPI3_SIN_3 /* PTE10 */
+#define PIN_LPSPI3_PCS PIN_PTD17 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE
+
+/* LPSPI4 P8B I/O connector / P26 external IMU connector */
+
+#define PIN_LPSPI4_SCK PIN_LPSPI4_SCK_1 /* PTB10 */
+#define PIN_LPSPI4_MISO PIN_LPSPI4_SOUT_1 /* PTB9 */
+#define PIN_LPSPI4_MOSI PIN_LPSPI4_SIN_1 /* PTB11 */
+#define PIN_LPSPI4_PCS0 PIN_LPSPI4_PCS0_1 /* PTB8 */
+#define PIN_LPSPI4_PCS3 PIN_LPSPI4_PCS3_1 /* PTA16 */
+
+#define PIN_LPSPI4_PCS (PIN_PTA16 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE) /* PTA16 */
+
+/* LPSPI5 P26 external IMU connector */
+
+#define PIN_LPSPI5_SCK PIN_LPSPI5_SCK_3 /* PTD26 */
+#define PIN_LPSPI5_MISO PIN_LPSPI5_SOUT_2 /* PTD27 */
+#define PIN_LPSPI5_MOSI PIN_LPSPI5_SIN_3 /* PTD28 */
+#define PIN_LPSPI5_PCS1 PIN_LPSPI5_PCS1_1 /* PTA14 */
+
+#define PIN_LPSPI5_PCS (PIN_PTA14 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE) /* PTA14 */
+
+/* PIN_LPSPI5_PCS2 PTD29 */
+
+/* I2C selections ***********************************************************/
+
+/* LPI2C0 P4 LCD header / P26 external IMU connector */
+
+#define PIN_LPI2C0_SCL PIN_LPI2C0_SCL_2 /* PTD14 */
+#define PIN_LPI2C0_SDA PIN_LPI2C0_SDA_2 /* PTD13 */
+
+/* LPI2C1 P3 external I2C connector / SE050 EdgeLock Secure Element */
+
+#define PIN_LPI2C1_SCL PIN_LPI2C1_SCL_4 /* PTD9 */
+#define PIN_LPI2C1_SDA PIN_LPI2C1_SDA_4 /* PTD8 */
+
+/* CAN selections ***********************************************************/
+
+/* CAN0 TJA1443 CAN transceiver */
+
+#define PIN_CAN0_RX PIN_CAN0_RX_1 /* PTA6 */
+#define PIN_CAN0_TX PIN_CAN0_TX_1 /* PTA7 */
+#define PIN_CAN0_STB (PIN_PTC21 | GPIO_OUTPUT)
+#define CAN0_STB_OUT 1
+#define PIN_CAN0_ENABLE (PIN_PTC24 | GPIO_OUTPUT)
+#define CAN0_ENABLE_OUT 1
+#define PIN_CAN0_LED (PIN_PTC18 | GPIO_OUTPUT)
+#define CAN0_LED_OUT 0
+#define PIN_CAN0_ERRN (PIN_PTC20 | GPIO_INPUT)
+
+/* CAN1 TJA1443 CAN transceiver */
+
+#define PIN_CAN1_RX PIN_CAN1_RX_4 /* PTC9 */
+#define PIN_CAN1_TX PIN_CAN1_TX_4 /* PTC8 */
+#define PIN_CAN1_STB (PIN_PTD2 | GPIO_OUTPUT)
+#define CAN1_STB_OUT 1
+#define PIN_CAN1_ENABLE (PIN_PTD23 | GPIO_OUTPUT)
+#define CAN1_ENABLE_OUT 1
+#define PIN_CAN1_LED (PIN_PTE5 | GPIO_OUTPUT)
+#define CAN1_LED_OUT 0
+#define PIN_CAN1_ERRN (PIN_PTD3 | GPIO_INPUT)
+
+/* CAN2 TJA1463 CAN transceiver */
+
+#define PIN_CAN2_RX PIN_CAN2_RX_5 /* PTE25 */
+#define PIN_CAN2_TX PIN_CAN2_TX_5 /* PTE24 */
+#define PIN_CAN2_STB (PIN_PTD22 | GPIO_OUTPUT)
+#define CAN2_STB_OUT 1
+#define PIN_CAN2_ENABLE (PIN_PTD4 | GPIO_OUTPUT)
+#define CAN2_ENABLE_OUT 1
+#define PIN_CAN2_LED (PIN_PTD20 | GPIO_OUTPUT)
+#define CAN2_LED_OUT 0
+#define PIN_CAN2_ERRN (PIN_PTD21 | GPIO_INPUT)
+
+/* CAN3 TJA1463 CAN transceiver */
+
+#define PIN_CAN3_RX PIN_CAN3_RX_2 /* PTC29 */
+#define PIN_CAN3_TX PIN_CAN3_TX_2 /* PTC28 */
+#define PIN_CAN3_STB (PIN_PTB1 | GPIO_OUTPUT)
+#define CAN3_STB_OUT 1
+#define PIN_CAN3_ENABLE (PIN_PTB0 | GPIO_OUTPUT)
+#define CAN3_ENABLE_OUT 1
+#define PIN_CAN3_LED (PIN_PTB24 | GPIO_OUTPUT)
+#define CAN3_LED_OUT 0
+#define PIN_CAN3_ERRN (PIN_PTC27 | GPIO_INPUT)
+
+/* CAN4 TJA1153 CAN transceiver */
+
+#define PIN_CAN4_RX PIN_CAN4_RX_2 /* PTC31 */
+#define PIN_CAN4_TX PIN_CAN4_TX_2 /* PTC30 */
+#define PIN_CAN4_STB (PIN_PTC25 | GPIO_OUTPUT)
+#define CAN4_STB_OUT 0
+#define PIN_CAN4_ENABLE (PIN_PTC26 | GPIO_OUTPUT)
+#define CAN4_ENABLE_OUT 1
+#define PIN_CAN4_LED (PIN_PTB26 | GPIO_OUTPUT)
+#define CAN4_LED_OUT 0
+#define PIN_CAN4_ERRN (PIN_PTC23 | GPIO_INPUT)
+
+/* CAN5 TJA1153 CAN transceiver */
+
+#define PIN_CAN5_RX PIN_CAN5_RX_1 /* PTC11 */
+#define PIN_CAN5_TX PIN_CAN5_TX_1 /* PTC10 */
+#define PIN_CAN5_STB (PIN_PTE17 | GPIO_OUTPUT)
+#define CAN5_STB_OUT 0
+#define PIN_CAN5_ENABLE (PIN_PTD30 | GPIO_OUTPUT)
+#define CAN5_ENABLE_OUT 1
+#define PIN_CAN5_LED (PIN_PTD31 | GPIO_OUTPUT)
+#define CAN5_LED_OUT 0
+#define PIN_CAN5_ERRN (PIN_PTD24 | GPIO_INPUT)
+
+/* ENET selections **********************************************************/
+
+#define PIN_EMAC_MII_RMII_TXD0 PIN_EMAC_MII_RMII_TXD0_1 /* PTB5 */
+#define PIN_EMAC_MII_RMII_TXD1 PIN_EMAC_MII_RMII_TXD1_1 /* PTB4 */
+#define PIN_EMAC_MII_RMII_TX_EN PIN_EMAC_MII_RMII_TX_EN_3 /* PTE9 */
+#define PIN_EMAC_MII_RMII_RXD0 PIN_EMAC_MII_RMII_RXD0_1 /* PTC0 */
+#define PIN_EMAC_MII_RMII_RXD1 PIN_EMAC_MII_RMII_RXD1_2 /* PTC1 */
+#define PIN_EMAC_MII_RMII_RX_DV PIN_EMAC_MII_RMII_RX_DV_1 /* PTC15 */
+#define PIN_EMAC_MII_RMII_RX_ER PIN_EMAC_MII_RMII_RX_ER_1 /* PTC14 */
+#define PIN_EMAC_MII_RMII_MDC PIN_EMAC_MII_RMII_MDC_3 /* PTC8 */
+#define PIN_EMAC_MII_RMII_MDIO PIN_EMAC_MII_RMII_MDIO_2 /* PTD16 */
+#define PIN_EMAC_MII_RMII_TX_CLK PIN_EMAC_MII_RMII_TX_CLK_2 /* PTD6 */
+
+#endif /* __BOARDS_ARM_S32K3XX_MR_CANHUBK3_INCLUDE_BOARD_H */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs b/boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs
new file mode 100644
index 0000000000..4b0b2daaf9
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs
@@ -0,0 +1,49 @@
+############################################################################
+# boards/arm/s32k3xx/mr-canhubk3/scripts/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Copyright 2022 NXP
+
+include $(TOPDIR)/.config
+include $(TOPDIR)/tools/Config.mk
+include $(TOPDIR)/arch/arm/src/armv7-m/Toolchain.defs
+
+ifeq ($(CONFIG_BOOT_RUNFROMFLASH),y)
+ LDSCRIPT = flash.ld
+else ifeq ($(CONFIG_BOOT_RUNFROMISRAM),y)
+ LDSCRIPT = sram.ld
+endif
+
+$(warning, LDSCRIPT is $(LDSCRIPT))
+ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
+$(warning, LDSCRIPT is $(LDSCRIPT))
+$(warning, ARCHSCRIPT is $(ARCHSCRIPT))
+
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
+AFLAGS := $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
diff --git a/boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld b/boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld
new file mode 100644
index 0000000000..3f8c78238c
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld
@@ -0,0 +1,159 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/scripts/flash.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* TO DO: ADD DESCRIPTION
+ *
+ * 0x00400000 - 0x007fffff 4194304 Program Flash (last 64K sBAF)
+ * 0x10000000 - 0x1003ffff 262144 Data Flash (last 32K HSE_NVM)
+ * 0x20400000 - 0x20408000 32768 Standby RAM_0 (32K)
+ * 0x20400000 - 0x20427fff 163840 SRAM_0
+ * 0x20428000 - 0x2044ffff 163840 SRAM_1
+ *
+ * Last 48 KB of SRAM_1 reserved by HSE Firmware
+ * Last 128 KB of CODE_FLASH_3 reserved by HSE Firmware
+ * Last 128 KB of DATA_FLASH reserved by HSE Firmware (not supported in this linker file)
+ *
+ * Note Standby RAM and SRAM overlaps in NuttX since we dont use the Standby functionality
+ *
+ */
+
+MEMORY
+{
+ BOOT_HEADER (R) : ORIGIN = 0x00400000, LENGTH = 0x00001000 /* 0x00400000 - 0x00400fff */
+ flash (rx) : ORIGIN = 0x00401000, LENGTH = 0x003cffff /* 0x00401000 - (0x007fffff - 0x20000 (128 KB) = 0x007dffff) */
+ sram0_stdby (rwx) : ORIGIN = 0x20400000, LENGTH = 32K
+ sram (rwx) : ORIGIN = 0x20400000, LENGTH = 272K
+ itcm (rwx) : ORIGIN = 0x00000000, LENGTH = 64K
+ dtcm (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+EXTERN(boot_header)
+ENTRY(_stext)
+
+SECTIONS
+{
+
+ .boot_header :
+ {
+ KEEP(*(.boot_header))
+ } > BOOT_HEADER
+
+ .text :
+ {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text.__start)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section :
+ {
+ _sinit = ABSOLUTE(.);
+ KEEP(*(.init_array .init_array.*))
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab :
+ {
+ *(.ARM.extab*)
+ } >flash
+
+ .ARM.exidx :
+ {
+ __exidx_start = ABSOLUTE(.);
+ *(.ARM.exidx*)
+ __exidx_end = ABSOLUTE(.);
+ } >flash
+
+ /* Due ECC initialization sequence __data_start__ and __data_end__ should be aligned on 8 bytes */
+ .data :
+ {
+ . = ALIGN(8);
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(8);
+ _edata = ABSOLUTE(.);
+ } > sram AT > flash
+
+ _eronly = LOADADDR(.data);
+
+ .ramfunc ALIGN(8):
+ {
+ _sramfuncs = ABSOLUTE(.);
+ *(.ramfunc .ramfunc.*)
+ _eramfuncs = ABSOLUTE(.);
+ } > sram AT > flash
+
+ _framfuncs = LOADADDR(.ramfunc);
+
+ /* Due ECC initialization sequence __bss_start__ and __bss_end__ should be aligned on 8 bytes */
+ .bss :
+ {
+ . = ALIGN(8);
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(8);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ CM7_0_START_ADDRESS = ORIGIN(flash);
+
+ /* Stabs debugging sections. */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+
+ SRAM_BASE_ADDR = ORIGIN(sram);
+ SRAM_END_ADDR = ORIGIN(sram) + LENGTH(sram);
+ SRAM_STDBY_BASE_ADDR = ORIGIN(sram0_stdby);
+ SRAM_STDBY_END_ADDR = ORIGIN(sram0_stdby) + LENGTH(sram0_stdby);
+ ITCM_BASE_ADDR = ORIGIN(itcm);
+ ITCM_END_ADDR = ORIGIN(itcm) + LENGTH(itcm);
+ DTCM_BASE_ADDR = ORIGIN(dtcm);
+ DTCM_END_ADDR = ORIGIN(dtcm) + LENGTH(dtcm);
+}
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/Makefile b/boards/arm/s32k3xx/mr-canhubk3/src/Makefile
new file mode 100644
index 0000000000..78a95dd706
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/Makefile
@@ -0,0 +1,62 @@
+############################################################################
+# boards/arm/s32k3xx/mr-canhubk3/src/Makefile
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+# Copyright 2022 NXP
+
+include $(TOPDIR)/Make.defs
+
+CSRCS = s32k3xx_boot.c s32k3xx_bringup.c s32k3xx_clockconfig.c
+CSRCS += s32k3xx_periphclocks.c
+
+ifeq ($(CONFIG_ARCH_BUTTONS),y)
+CSRCS += s32k3xx_buttons.c
+endif
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += s32k3xx_autoleds.c
+else
+CSRCS += s32k3xx_userleds.c
+endif
+
+ifeq ($(CONFIG_BOARDCTL),y)
+CSRCS += s32k3xx_appinit.c
+endif
+
+ifeq ($(CONFIG_FAT_DMAMEMORY),y)
+CSRCS += s32k3xx_dma_alloc.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_FLEXCAN),y)
+CSRCS += s32k3xx_tja1153.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPI2C),y)
+CSRCS += s32k3xx_i2c.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_LPSPI),y)
+CSRCS += s32k3xx_spi.c
+endif
+
+ifeq ($(CONFIG_S32K3XX_SELFTEST),y)
+CSRCS += s32k3xx_selftest.c
+endif
+
+include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h b/boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h
new file mode 100644
index 0000000000..bc686ebe39
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h
@@ -0,0 +1,147 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/mr-canhubk3.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+#ifndef __BOARDS_ARM_S32K3XX_MR_CANHUBK3_SRC_MR_CANHUBK3_H
+#define __BOARDS_ARM_S32K3XX_MR_CANHUBK3_SRC_MR_CANHUBK3_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <stdint.h>
+
+#include "hardware/s32k344_pinmux.h"
+#include "s32k3xx_periphclocks.h"
+#include "s32k3xx_pin.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* MR-CANHUBK3 GPIOs ********************************************************/
+
+/* LEDs. The MR-CANHUBK3 has one RGB LED:
+ *
+ * RedLED PTE14 (FXIO D7 / EMIOS0 CH19)
+ * GreenLED PTA27 (FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10)
+ * BlueLED PTE12 (FXIO D8 / EMIOS1 CH5)
+ *
+ * An output of '0' illuminates the LED.
+ */
+
+#define GPIO_LED_R (PIN_PTE14 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE)
+#define GPIO_LED_G (PIN_PTA27 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE)
+#define GPIO_LED_B (PIN_PTE12 | GPIO_LOWDRIVE | GPIO_OUTPUT_ONE)
+
+/* Buttons. The MR-CANHUBK3 supports two buttons:
+ *
+ * SW1 PTD15 (EIRQ31)
+ * SW2 PTA25 (EIRQ5 / WKPU34)
+ */
+
+#define GPIO_SW1 (PIN_EIRQ31_2 | PIN_INT_BOTH) /* PTD15 */
+#define GPIO_SW2 (PIN_EIRQ5_2 | PIN_INT_BOTH) /* PTA25 */
+
+/* Count of peripheral clock user configurations */
+
+#define NUM_OF_PERIPHERAL_CLOCKS_0 26
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* User peripheral configuration structure 0 */
+
+extern const struct peripheral_clock_config_s g_peripheral_clockconfig0[];
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y && CONFIG_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int s32k3xx_bringup(void);
+
+/****************************************************************************
+ * Name: s32k3xx_i2cdev_initialize
+ *
+ * Description:
+ * Initialize I2C driver and register /dev/i2cN devices.
+ *
+ ****************************************************************************/
+
+int s32k3xx_i2cdev_initialize(void);
+
+/****************************************************************************
+ * Name: s32k3xx_spidev_initialize
+ *
+ * Description:
+ * Configure chip select pins, initialize the SPI driver and register
+ * /dev/spiN devices.
+ *
+ ****************************************************************************/
+
+int s32k3xx_spidev_initialize(void);
+
+/****************************************************************************
+ * Name: s32k3xx_tja1153_initialize
+ *
+ * Description:
+ * Initialize a TJA1153 CAN PHY connected to a FlexCAN peripheral (0-5)
+ *
+ ****************************************************************************/
+
+int s32k3xx_tja1153_initialize(int bus);
+
+/****************************************************************************
+ * Name: s32k3xx_selftest
+ *
+ * Description:
+ * Runs basic routines to verify that all board components are up and
+ * running. Results are send to the syslog, it is recommended to
+ * enable all output levels (error, warning and info).
+ *
+ ****************************************************************************/
+
+void s32k3xx_selftest(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __BOARDS_ARM_S32K3XX_MR_CANHUBK3_SRC_MR_CANHUBK3_H */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
new file mode 100644
index 0000000000..4ac3536c4f
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_appinit.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/board.h>
+
+#include <stdint.h>
+
+#include "mr-canhubk3.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef OK
+# define OK 0
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ * Perform application specific initialization. This function is never
+ * called directly from application code, but only indirectly via the
+ * (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ * arg - The boardctl() argument is passed to the board_app_initialize()
+ * implementation without modification. The argument has no meaning
+ * to NuttX; the meaning of the argument is a contract between the
+ * board-specific initialization logic and the matching application
+ * logic. The value could be such things as a mode enumeration
+ * value, a set of DIP switch settings, a pointer to configuration
+ * data read from a file or serial FLASH, or whatever you would like
+ * to do with it. Every implementation should accept zero/NULL as a
+ * default configuration.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; a negated errno value is returned on
+ * any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+ /* Board initialization already performed by board_late_initialize() */
+
+ return OK;
+#else
+ /* Perform board-specific initialization */
+
+ return s32k3xx_bringup();
+#endif
+}
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c
new file mode 100644
index 0000000000..101c85b5f1
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c
@@ -0,0 +1,150 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_autoleds.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* The MR-CANHUBK3 has one RGB LED:
+ *
+ * RedLED PTE14 (FXIO D7 / EMIOS0 CH19)
+ * GreenLED PTA27 (FXIO D5 / EMIOS1 CH10 / EMIOS2 CH10)
+ * BlueLED PTE12 (FXIO D8 / EMIOS1 CH5)
+ *
+ * An output of '0' illuminates the LED.
+ *
+ * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board
+ * the MR-CANHUBK3. The following definitions describe how NuttX controls
+ * the LEDs:
+ *
+ * SYMBOL Meaning LED state
+ * RED GREEN BLUE
+ * ---------------- ------------------------ --------------------
+ * LED_STARTED NuttX has been started OFF OFF OFF
+ * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON
+ * LED_IRQSENABLED Interrupts enabled OFF OFF ON
+ * LED_STACKCREATED Idle stack created OFF ON OFF
+ * LED_INIRQ In an interrupt (No change)
+ * LED_SIGNAL In a signal handler (No change)
+ * LED_ASSERTION An assertion failed (No change)
+ * LED_PANIC The system has crashed FLASH OFF OFF
+ * LED_IDLE S32K344 is in sleep mode (Optional, not used)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include "mr-canhubk3.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Summary of all possible settings */
+
+#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */
+#define LED_OFF_OFF_OFF 1 /* LED_STARTED */
+#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */
+#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */
+#define LED_ON_OFF_OFF 4 /* LED_PANIC */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k3xx_pinconfig(GPIO_LED_R);
+ s32k3xx_pinconfig(GPIO_LED_G);
+ s32k3xx_pinconfig(GPIO_LED_B);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+ if (led != LED_NOCHANGE)
+ {
+ bool redon = false;
+ bool greenon = false;
+ bool blueon = false;
+
+ switch (led)
+ {
+ default:
+ case LED_OFF_OFF_OFF:
+ break;
+
+ case LED_OFF_OFF_ON:
+ blueon = true;
+ break;
+
+ case LED_OFF_ON_OFF:
+ greenon = true;
+ break;
+
+ case LED_ON_OFF_OFF:
+ redon = true;
+ break;
+ }
+
+ /* Invert output, an output of '0' illuminates the LED */
+
+ s32k3xx_gpiowrite(GPIO_LED_R, !redon);
+ s32k3xx_gpiowrite(GPIO_LED_G, !greenon);
+ s32k3xx_gpiowrite(GPIO_LED_B, !blueon);
+ }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+ if (led == LED_ON_OFF_OFF)
+ {
+ /* Invert outputs, an output of '0' illuminates the LED */
+
+ s32k3xx_gpiowrite(GPIO_LED_R, !true);
+ s32k3xx_gpiowrite(GPIO_LED_G, !false);
+ s32k3xx_gpiowrite(GPIO_LED_B, !false);
+ }
+}
+
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c
new file mode 100644
index 0000000000..b4e71a8552
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c
@@ -0,0 +1,82 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_boot.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+#include "mr-canhubk3.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_board_initialize
+ *
+ * Description:
+ * All S32K3XX architectures must provide the following entry point. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured and mapped but before any devices have been
+ * initialized.
+ *
+ ****************************************************************************/
+
+void s32k3xx_board_initialize(void)
+{
+#ifdef CONFIG_SEGGER_SYSVIEW
+ up_perf_init((void *)MR_CANHUBK3_SYSCLK_FREQUENCY);
+#endif
+
+#ifdef CONFIG_ARCH_LEDS
+ /* Configure on-board LEDs if LED support has been selected */
+
+ board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_late_initialize
+ *
+ * Description:
+ * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
+ * initialization call will be performed in the boot-up sequence to a
+ * function called board_late_initialize(). board_late_initialize() will
+ * be called immediately after up_initialize() is called and just before
+ * the initial application is started. This additional initialization
+ * phase may be used, for example, to initialize board-specific device
+ * drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_LATE_INITIALIZE
+void board_late_initialize(void)
+{
+ /* Perform board-specific initialization */
+
+ s32k3xx_bringup();
+}
+#endif
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c
new file mode 100644
index 0000000000..b56ea9e84e
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c
@@ -0,0 +1,320 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_bringup.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <stdint.h>
+#include <sys/types.h>
+
+#ifdef CONFIG_INPUT_BUTTONS
+# include <nuttx/input/buttons.h>
+#endif
+
+#ifdef CONFIG_USERLED
+# include <nuttx/leds/userled.h>
+#endif
+
+#ifdef CONFIG_S32K3XX_FLEXCAN
+# include "s32k3xx_flexcan.h"
+#endif
+
+#ifdef CONFIG_S32K3XX_ENET
+# include "s32k3xx_emac.h"
+#endif
+
+#ifdef CONFIG_S32K3XX_QSPI
+# include <stdio.h>
+# include <nuttx/mtd/mtd.h>
+# include <nuttx/spi/qspi.h>
+# include "s32k3xx_qspi.h"
+#endif
+
+#include <arch/board/board.h>
+#include "mr-canhubk3.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifdef HAVE_MX25L
+struct qspi_dev_s *g_qspi;
+struct mtd_dev_s *g_mtd_fs;
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_bringup
+ *
+ * Description:
+ * Perform architecture-specific initialization
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=y :
+ * Called from board_late_initialize().
+ *
+ * CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
+ * Called from the NSH library
+ *
+ ****************************************************************************/
+
+int s32k3xx_bringup(void)
+{
+ int ret = OK;
+#if defined(CONFIG_BCH) || defined(HAVE_MX25L_LITTLEFS)
+ char blockdev[32];
+# if !defined(HAVE_MX25L_LITTLEFS) && !defined(HAVE_MX25L_NXFFS)
+ char chardev[32];
+# endif /* !HAVE_MX25L_LITTLEFS && !HAVE_MX25L_NXFFS */
+#endif /* CONFIG_BCH || HAVE_MX25L_LITTLEFS */
+
+#ifdef CONFIG_S32K3XX_LPSPI
+ /* Initialize SPI driver */
+
+ ret = s32k3xx_spidev_initialize();
+ if (ret < 0)
+ {
+ _err("s32k3xx_spidev_initialize() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("s32k3xx_spidev_initialize() succesful\n");
+ }
+#endif
+
+#ifdef CONFIG_INPUT_BUTTONS
+ /* Register the BUTTON driver */
+
+ ret = btn_lower_initialize("/dev/buttons");
+ if (ret < 0)
+ {
+ _err("btn_lower_initialize() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("btn_lower_initialize() succesful\n");
+ }
+#endif
+
+#ifdef CONFIG_USERLED
+ /* Register the LED driver */
+
+ ret = userled_lower_initialize("/dev/userleds");
+ if (ret < 0)
+ {
+ _err("userled_lower_initialize() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("userled_lower_initialize() succesful\n");
+ }
+#endif
+
+#ifdef CONFIG_FS_PROCFS
+ /* Mount the procfs file system */
+
+ ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
+ if (ret < 0)
+ {
+ _err("Mounting procfs at /proc failed: %d\n", ret);
+ }
+ else
+ {
+ _info("Mounting procfs at /proc succesful\n");
+ }
+#endif
+
+#ifdef CONFIG_S32K3XX_LPI2C
+ /* Initialize I2C driver */
+
+ ret = s32k3xx_i2cdev_initialize();
+ if (ret < 0)
+ {
+ _err("s32k3xx_i2cdev_initialize() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("s32k3xx_i2cdev_initialize() succesful\n");
+ }
+#endif
+
+#ifdef HAVE_MX25L
+ /* Create an instance of the S32K3XX QSPI device driver */
+
+ g_qspi = s32k3xx_qspi_initialize(0);
+ if (!g_qspi)
+ {
+ _err("s32k3xx_qspi_initialize() failed\n");
+ }
+ else
+ {
+ _info("s32k3xx_qspi_initialize() succesful\n");
+
+ /* Use the QSPI device instance to initialize the MX25 device */
+
+ g_mtd_fs = mx25rxx_initialize(g_qspi, true);
+ if (!g_mtd_fs)
+ {
+ _err("mx25rxx_initialize() failed\n");
+ }
+ else
+ {
+ _info("mx25rxx_initialize() succesful\n");
+
+# ifdef HAVE_MX25L_LITTLEFS
+ /* Configure the device with no partition support */
+
+ snprintf(blockdev, sizeof(blockdev), "/dev/mtdqspi%d",
+ MX25L_MTD_MINOR);
+
+ ret = register_mtddriver(blockdev, g_mtd_fs, 0755, NULL);
+ if (ret != OK)
+ {
+ _err("register_mtddriver() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("register_mtddriver() succesful\n");
+
+ ret = nx_mount(blockdev, "/mnt/qspi", "littlefs", 0, NULL);
+ if (ret < 0)
+ {
+ ret = nx_mount(blockdev, "/mnt/qspi", "littlefs", 0,
+ "forceformat");
+ if (ret < 0)
+ {
+ _err("nx_mount() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("nx_mount() succesful\n");
+ }
+ }
+ }
+
+# elif defined(HAVE_MX25L_NXFFS)
+ /* Initialize to provide NXFFS on the N25QXXX MTD interface */
+
+ ret = nxffs_initialize(g_mtd_fs);
+ if (ret < 0)
+ {
+ _err("nxffs_initialize() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("nxffs_initialize() succesful\n");
+
+ /* Mount the file system at /mnt/qspi */
+
+ ret = nx_mount(NULL, "/mnt/qspi", "nxffs", 0, NULL);
+ if (ret < 0)
+ {
+ _err("nx_mount() failed: %d\n", ret);
+ }
+ else
+ {
+ _info("nx_mount() succesful\n");
+ }
+ }
+
+# else /* if defined(HAVE_MX25L_CHARDEV) */
+ /* Use the FTL layer to wrap the MTD driver as a block driver */
+
+ ret = ftl_initialize(MX25L_MTD_MINOR, g_mtd_fs);
+ if (ret < 0)
+ {
+ _err("ftl_initialize() failed: %d\n", ret);
+ }
+# ifdef CONFIG_BCH
+ else
+ {
+ _info("ftl_initialize() succesful\n");
+
+ /* Use the minor number to create device paths */
+
+ snprintf(blockdev, sizeof(blockdev), "/dev/mtdblock%d",
+ MX25L_MTD_MINOR);
+ snprintf(chardev, sizeof(chardev), "/dev/mtd%d",
+ MX25L_MTD_MINOR);
+
+ /* Now create a character device on the block device */
+
+ ret = bchdev_register(blockdev, chardev, false);
+ if (ret < 0)
+ {
+ _err("bchdev_register %s failed: %d\n", chardev, ret);
+ }
+ else
+ {
+ _info("bchdev_register %s succesful\n", chardev);
+ }
+ }
+# endif /* CONFIG_BCH */
+# endif
+ }
+ }
+#endif
+
+#ifdef CONFIG_S32K3XX_SELFTEST
+ s32k3xx_selftest();
+#endif /* CONFIG_S32K3XX_SELFTEST */
+
+#ifdef CONFIG_NETDEV_LATEINIT
+# ifdef CONFIG_S32K3XX_ENET
+ s32k3xx_netinitialize(0);
+# endif /* CONFIG_S32K3XX_ENET */
+# ifdef CONFIG_S32K3XX_FLEXCAN0
+ s32k3xx_caninitialize(0);
+# endif /* CONFIG_S32K3XX_FLEXCAN0 */
+# ifdef CONFIG_S32K3XX_FLEXCAN1
+ s32k3xx_caninitialize(1);
+# endif /* CONFIG_S32K3XX_FLEXCAN1 */
+# ifdef CONFIG_S32K3XX_FLEXCAN2
+ s32k3xx_caninitialize(2);
+# endif /* CONFIG_S32K3XX_FLEXCAN2 */
+# ifdef CONFIG_S32K3XX_FLEXCAN3
+ s32k3xx_caninitialize(3);
+# endif /* CONFIG_S32K3XX_FLEXCAN3 */
+# ifdef CONFIG_S32K3XX_FLEXCAN4
+ s32k3xx_caninitialize(4);
+# ifdef CONFIG_S32K3XX_TJA1153
+ s32k3xx_tja1153_initialize(4);
+# endif /* CONFIG_S32K3XX_TJA1153 */
+# endif /* CONFIG_S32K3XX_FLEXCAN4 */
+# ifdef CONFIG_S32K3XX_FLEXCAN5
+ s32k3xx_caninitialize(5);
+# ifdef CONFIG_S32K3XX_TJA1153
+ s32k3xx_tja1153_initialize(5);
+# endif /* CONFIG_S32K3XX_TJA1153 */
+# endif /* CONFIG_S32K3XX_FLEXCAN5 */
+#endif /* CONFIG_NETDEV_LATEINIT */
+
+ _info("MR-CANHUBK3 board bringup complete\n");
+
+ return ret;
+}
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c
new file mode 100644
index 0000000000..78b0660150
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c
@@ -0,0 +1,154 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_buttons.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/* The MR-CANHUBK3 supports two buttons:
+ *
+ * SW1 PTD15 (EIRQ31)
+ * SW2 PTA25 (EIRQ5 / WKPU34)
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <errno.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include <arch/board/board.h>
+
+#include "mr-canhubk3.h"
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_button_initialize
+ *
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ ****************************************************************************/
+
+uint32_t board_button_initialize(void)
+{
+ /* Configure the GPIO pins as interrupting inputs */
+
+ s32k3xx_pinconfig(GPIO_SW1);
+ s32k3xx_pinconfig(GPIO_SW2);
+
+ return NUM_BUTTONS;
+}
+
+/****************************************************************************
+ * Name: board_buttons
+ ****************************************************************************/
+
+uint32_t board_buttons(void)
+{
+ uint32_t ret = 0;
+
+ if (s32k3xx_gpioread(GPIO_SW1))
+ {
+ ret |= BUTTON_SW1_BIT;
+ }
+
+ if (s32k3xx_gpioread(GPIO_SW2))
+ {
+ ret |= BUTTON_SW2_BIT;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_ARCH_IRQBUTTONS
+/****************************************************************************
+ * Button support.
+ *
+ * Description:
+ * board_button_initialize() must be called to initialize button resources.
+ * After that, board_buttons() may be called to collect the current state
+ * of all buttons or board_button_irq() may be called to register button
+ * interrupt handlers.
+ *
+ * After board_button_initialize() has been called, board_buttons() may be
+ * called to collect the state of all buttons. board_buttons() returns a
+ * 32-bit bit set with each bit associated with a button. See the
+ * BUTTON_*_BIT definitions in board.h for the meaning of each bit.
+ *
+ * board_button_irq() may be called to register an interrupt handler that
+ * will be called when a button is pressed or released. The ID value is a
+ * button enumeration value that uniquely identifies a button resource.
+ * See the BUTTON_* definitions in board.h for the meaning of enumeration
+ * value.
+ *
+ ****************************************************************************/
+
+int board_button_irq(int id, xcpt_t irqhandler, void *arg)
+{
+ uint32_t pinset;
+ int ret;
+
+ /* Map the button id to the GPIO bit set */
+
+ if (id == BUTTON_SW1)
+ {
+ pinset = GPIO_SW1;
+ }
+ else if (id == BUTTON_SW2)
+ {
+ pinset = GPIO_SW2;
+ }
+ else
+ {
+ return -EINVAL;
+ }
+
+ /* The button has already been configured as an interrupting input (by
+ * board_button_initialize() above).
+ *
+ * Attach the new button handler.
+ */
+
+ ret = s32k3xx_pinirqattach(pinset, irqhandler, NULL);
+ if (ret >= 0)
+ {
+ /* Then make sure that interrupts are enabled on the pin */
+
+ s32k3xx_pinirqenable(pinset);
+ }
+
+ return ret;
+}
+#endif /* CONFIG_ARCH_IRQBUTTONS */
+#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c
new file mode 100644
index 0000000000..64649d30c7
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "s32k3xx_clockconfig.h"
+#include "s32k3xx_start.h"
+
+#include "mr-canhubk3.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K3XX board must provide the following initialized structure.
+ * This is needed to establish the initial board clocking.
+ */
+
+const struct clock_configuration_s g_initial_clkconfig =
+{
+ .cgm =
+ {
+ .sirc =
+ {
+ .range = CGM_FIRC_RANGE_32K, /* Slow IRC is trimmed to 32 kHz */
+ },
+ .firc =
+ {
+ .range = CGM_FIRC_RANGE_HIGH, /* RANGE */
+ .div = CGM_CLOCK_DIV_BY_1, /* FIRCDIV1 */
+ },
+ .scs =
+ {
+ .scs_source = CGM_SCS_SOURCE_PLL_PHI0,
+ .core_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .aips_plat_clk =
+ {
+ .div = CGM_MUX_DIV_BY_2,
+ .trigger = false,
+ },
+ .aips_slow_clk =
+ {
+ .div = CGM_MUX_DIV_SLOW_BY_4,
+ .trigger = false,
+ },
+ .hse_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .dcm_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+ .lbist_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+#ifdef CONFIG_S32K3XX_QSPI
+ .qspi_mem_clk =
+ {
+ .div = CGM_MUX_DIV_BY_1,
+ .trigger = false,
+ },
+#endif
+ .mux_3 =
+ {
+ .source = CGM_CLK_SRC_AIPS_PLAT_CLK,
+ .div = CGM_MUX_DIV_BY_1,
+ },
+ .mux_4 =
+ {
+ .source = CGM_CLK_SRC_AIPS_PLAT_CLK,
+ .div = CGM_MUX_DIV_BY_1,
+ },
+#ifdef CONFIG_S32K3XX_ENET
+ .mux_7_emac_rx =
+ {
+ .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK,
+ .div = CGM_MUX_DIV_BY_2,
+ },
+ .mux_8_emac_tx =
+ {
+ .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK,
+ .div = CGM_MUX_DIV_BY_2,
+ },
+ .mux_9_emac_ts =
+ {
+ .source = CGM_CLK_SRC_EMAC_RMII_TX_CLK,
+ .div = CGM_MUX_DIV_BY_2, /* FIXME check div value */
+ },
+#endif
+#ifdef CONFIG_S32K3XX_QSPI
+ .mux_10_qspi_sfck =
+ {
+ .source = CGM_CLK_SRC_PLL_PHI1_CLK,
+ .div = CGM_MUX_DIV_BY_4,
+ },
+#endif
+ },
+ .pll =
+ {
+ .modul_freq = 0,
+ .modul_depth = 0,
+ .core_pll_power = true,
+ .modulation_type = false,
+ .sigma_delta = CGM_PLL_SIGMA_DELTA,
+ .enable_dither = false,
+ .mode = CGM_PLL_INTEGER_MODE,
+ .prediv = 2,
+ .mult = 120,
+ .postdiv = 2,
+ .phi0 = CGM_PLL_PHI_DIV_BY_3,
+ .phi1 = CGM_PLL_PHI_DIV_BY_3,
+ },
+ .clkout =
+ {
+ .source = CGM_CLK_SRC_AIPS_SLOW_CLK,
+ .div = CGM_CLKOUT_DIV_BY_1,
+ }
+ },
+ .pcc =
+ {
+ .count = NUM_OF_PERIPHERAL_CLOCKS_0, /* Number of peripheral clock configurations */
+ .pclks = g_peripheral_clockconfig0, /* Peripheral clock configurations */
+ },
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c
new file mode 100644
index 0000000000..857a8e6628
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_dma_alloc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <syslog.h>
+#include <stdint.h>
+#include <errno.h>
+#include <nuttx/mm/gran.h>
+
+#if defined(CONFIG_FAT_DMAMEMORY)
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#if !defined(CONFIG_GRAN)
+# error microSD DMA support requires CONFIG_GRAN
+#endif
+
+#define BOARD_DMA_ALLOC_POOL_SIZE (8*512)
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static GRAN_HANDLE dma_allocator;
+
+/* The DMA heap size constrains the total number of things that can be
+ * ready to do DMA at a time.
+ *
+ * For example, FAT DMA depends on one sector-sized buffer per filesystem
+ * plus one sector-sized buffer per file.
+ *
+ * We use a fundamental alignment / granule size of 64B; this is sufficient
+ * to guarantee alignment for the largest STM32 DMA burst
+ * (16 beats x 32bits).
+ */
+
+static
+uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] aligned_data(64);
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_dma_alloc_init
+ *
+ * Description:
+ * All boards may optionally provide this API to instantiate a pool of
+ * memory for uses with FAST FS DMA operations.
+ *
+ ****************************************************************************/
+
+int s32k3xx_dma_alloc_init(void)
+{
+ dma_allocator = gran_initialize(g_dma_heap,
+ sizeof(g_dma_heap),
+ 7, /* 128B granule - must be > alignment (XXX bug?) */
+ 6); /* 64B alignment */
+
+ if (dma_allocator == NULL)
+ {
+ return -ENOMEM;
+ }
+
+ return OK;
+}
+
+/* DMA-aware allocator stubs for the FAT filesystem. */
+
+void *fat_dma_alloc(size_t size)
+{
+ return gran_alloc(dma_allocator, size);
+}
+
+void fat_dma_free(FAR void *memory, size_t size)
+{
+ gran_free(dma_allocator, memory, size);
+}
+
+#endif /* CONFIG_FAT_DMAMEMORY */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c
new file mode 100644
index 0000000000..9d08fedcae
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c
@@ -0,0 +1,105 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_i2c.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/i2c/i2c_master.h>
+
+#include "s32k3xx_lpi2c.h"
+
+#include "mr-canhubk3.h"
+
+#ifdef CONFIG_S32K3XX_LPI2C
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_i2cdev_initialize
+ *
+ * Description:
+ * Initialize I2C driver and register /dev/i2cN devices.
+ *
+ ****************************************************************************/
+
+int weak_function s32k3xx_i2cdev_initialize(void)
+{
+ int ret = OK;
+
+#if defined(CONFIG_S32K3XX_LPI2C0) && defined(CONFIG_I2C_DRIVER)
+ /* LPI2C0 *****************************************************************/
+
+ /* Initialize the I2C driver for LPI2C0 */
+
+ struct i2c_master_s *lpi2c0 = s32k3xx_i2cbus_initialize(0);
+ if (lpi2c0 == NULL)
+ {
+ i2cerr("ERROR: FAILED to initialize LPI2C0\n");
+ return -ENODEV;
+ }
+
+ ret = i2c_register(lpi2c0, 0);
+ if (ret < 0)
+ {
+ i2cerr("ERROR: FAILED to register LPI2C0 driver\n");
+ s32k3xx_i2cbus_uninitialize(lpi2c0);
+ return ret;
+ }
+
+#endif /* CONFIG_S32K3XX_LPI2C0 && CONFIG_I2C_DRIVER */
+
+#if defined(CONFIG_S32K3XX_LPI2C1) && defined(CONFIG_I2C_DRIVER)
+ /* LPI2C1 *****************************************************************/
+
+ /* Initialize the I2C driver for LPI2C1 */
+
+ struct i2c_master_s *lpi2c1 = s32k3xx_i2cbus_initialize(1);
+ if (lpi2c1 == NULL)
+ {
+ i2cerr("ERROR: FAILED to initialize LPI2C1\n");
+ return -ENODEV;
+ }
+
+ ret = i2c_register(lpi2c1, 1);
+ if (ret < 0)
+ {
+ i2cerr("ERROR: FAILED to register LPI2C1 driver\n");
+ s32k3xx_i2cbus_uninitialize(lpi2c1);
+ return ret;
+ }
+#endif /* CONFIG_S32K3XX_LPI2C1 && CONFIG_I2C_DRIVER */
+
+ return ret;
+}
+
+#endif /* CONFIG_S32K3XX_LPI2C */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c
new file mode 100644
index 0000000000..0db0859f02
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c
@@ -0,0 +1,258 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_periphclocks.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+
+#include "s32k3xx_clocknames.h"
+#include "s32k3xx_periphclocks.h"
+
+#include "mr-canhubk3.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* Each S32K3XX board must provide the following initialized structure.
+ * This is needed to establish the initial peripheral clocking.
+ */
+
+const struct peripheral_clock_config_s g_peripheral_clockconfig0[] =
+{
+ {
+ .clkname = FLEXCAN0_CLK,
+#ifdef CONFIG_S32K3XX_FLEXCAN0
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = FLEXCAN1_CLK,
+#ifdef CONFIG_S32K3XX_FLEXCAN1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = FLEXCAN2_CLK,
+#ifdef CONFIG_S32K3XX_FLEXCAN2
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = FLEXCAN3_CLK,
+#ifdef CONFIG_S32K3XX_FLEXCAN3
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = FLEXCAN4_CLK,
+#ifdef CONFIG_S32K3XX_FLEXCAN4
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = FLEXCAN5_CLK,
+#ifdef CONFIG_S32K3XX_FLEXCAN5
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPI2C0_CLK,
+#ifdef CONFIG_S32K3XX_LPI2C0
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPI2C1_CLK,
+#ifdef CONFIG_S32K3XX_LPI2C1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI1_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI2_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI2
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI3_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI3
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI4_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI4
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPSPI5_CLK,
+#ifdef CONFIG_S32K3XX_LPSPI5
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART0_CLK,
+#ifdef CONFIG_S32K3XX_LPUART0
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART1_CLK,
+#ifdef CONFIG_S32K3XX_LPUART1
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART2_CLK,
+#ifdef CONFIG_S32K3XX_LPUART2
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART9_CLK,
+#ifdef CONFIG_S32K3XX_LPUART9
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART10_CLK,
+#ifdef CONFIG_S32K3XX_LPUART10
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART13_CLK,
+#ifdef CONFIG_S32K3XX_LPUART13
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = LPUART14_CLK,
+#ifdef CONFIG_S32K3XX_LPUART14
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = WKPU_CLK,
+#ifdef CONFIG_S32K3XX_WKPUINTS
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = EMAC_CLK,
+#ifdef CONFIG_S32K3XX_ENET
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = QSPI_CLK,
+#ifdef CONFIG_S32K3XX_QSPI
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = EDMA_CLK,
+#ifdef CONFIG_S32K3XX_EDMA
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = DMAMUX0_CLK,
+#ifdef CONFIG_S32K3XX_EDMA
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ },
+ {
+ .clkname = DMAMUX1_CLK,
+#ifdef CONFIG_S32K3XX_EDMA
+ .clkgate = true,
+#else
+ .clkgate = false,
+#endif
+ }
+};
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c
new file mode 100644
index 0000000000..85df009d5b
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c
@@ -0,0 +1,464 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_selftest.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/i2c/i2c_master.h>
+
+#include "s32k3xx_lpi2c.h"
+#include "s32k3xx_pin.h"
+
+#include <arch/board/board.h>
+#include "mr-canhubk3.h"
+
+#ifdef CONFIG_S32K3XX_SELFTEST
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_S32K3XX_LPI2C
+static int s32k3xx_selftest_se050(void);
+#endif /* CONFIG_S32K3XX_LPI2C */
+#ifdef CONFIG_S32K3XX_FLEXCAN
+static int s32k3xx_selftest_can(void);
+# if !defined(CONFIG_S32K3XX_TJA1153)
+static int s32k3xx_selftest_sct(void);
+# endif /* !CONFIG_S32K3XX_TJA1153 */
+#endif /* CONFIG_S32K3XX_FLEXCAN */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_S32K3XX_LPI2C
+/****************************************************************************
+ * Name: s32k3xx_selftest_se050
+ *
+ * Description:
+ * Basic check to see if the SE050 is alive by having it ACK a I2C write.
+ *
+ ****************************************************************************/
+
+static int s32k3xx_selftest_se050(void)
+{
+ struct i2c_master_s *lpi2c1;
+ struct i2c_msg_s se050_msg;
+ uint8_t buf = 0;
+ int ret = 0;
+ bool error = false;
+
+#if !defined(CONFIG_S32K3XX_LPI2C1)
+# error CONFIG_S32K3XX_LPI2C1 needs to be enabled to perform SE050 self-test
+#endif
+
+ /* Initialize LPI2C1 to which the SE050 is connected */
+
+ lpi2c1 = s32k3xx_i2cbus_initialize(1);
+
+ if (lpi2c1 != NULL)
+ {
+ _info("s32k3xx_i2cbus_initialize() succesful\n");
+ }
+ else
+ {
+ error = true;
+ _err("s32k3xx_i2cbus_initialize() failed\n");
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+
+ /* Verify SE050 by checking for ACK on I2C write */
+
+ se050_msg.frequency = I2C_SPEED_STANDARD;
+ se050_msg.addr = 0x48;
+ se050_msg.flags = 0;
+ se050_msg.buffer = &buf;
+ se050_msg.length = 1;
+
+ ret = I2C_TRANSFER(lpi2c1, &se050_msg, 1);
+ if (ret == 0)
+ {
+ _info("SE050 ACK succesful\n");
+ }
+ else
+ {
+ error = true;
+ _err("SE050 ACK failed: %d\n", ret);
+
+ /* Don't return yet, we still need to cleanup */
+ }
+
+ /* Let the LPI2C driver know we won't be using it anymore */
+
+ ret = s32k3xx_i2cbus_uninitialize(lpi2c1);
+
+ if (ret == 0)
+ {
+ _info("s32k3xx_i2cbus_uninitialize() succesful\n");
+
+ /* Return error if we had any earlier, otherwise return result of
+ * s32k3xx_i2cbus_uninitialize()
+ */
+
+ return (error ? -1 : ret);
+ }
+ else
+ {
+ error = true;
+ _err("s32k3xx_i2cbus_uninitialize() failed: %d\n", ret);
+
+ return -1;
+ }
+}
+#endif /* CONFIG_S32K3XX_LPI2C */
+
+#ifdef CONFIG_S32K3XX_FLEXCAN
+/****************************************************************************
+ * Name: s32k3xx_selftest_can
+ *
+ * Description:
+ * Basic check of the local failure flags of the CAN transceivers (0-3).
+ *
+ ****************************************************************************/
+
+static int s32k3xx_selftest_can(void)
+{
+ uint32_t errn_pins[4] =
+ {
+ PIN_CAN0_ERRN,
+ PIN_CAN1_ERRN,
+ PIN_CAN2_ERRN,
+ PIN_CAN3_ERRN
+ };
+
+ uint32_t stbn_pins[4] =
+ {
+ PIN_CAN0_STB,
+ PIN_CAN1_STB,
+ PIN_CAN2_STB,
+ PIN_CAN3_STB
+ };
+
+ uint32_t en_pins[4] =
+ {
+ PIN_CAN0_ENABLE,
+ PIN_CAN1_ENABLE,
+ PIN_CAN2_ENABLE,
+ PIN_CAN3_ENABLE
+ };
+
+ int i;
+ int ret = 0;
+ bool error = false;
+
+#if !defined(CONFIG_S32K3XX_FLEXCAN0) || !defined(CONFIG_S32K3XX_FLEXCAN1) || \
+ !defined(CONFIG_S32K3XX_FLEXCAN2) || !defined(CONFIG_S32K3XX_FLEXCAN3)
+# error CONFIG_S32K3XX_FLEXCAN0-3 need to be enabled to perform CAN self-test
+#endif
+
+ /* Initialize pins, go into normal mode (EN high, STB_N high) to clear Pwon
+ * and Wake flags.
+ */
+
+ for (i = 0; i < 4; i++)
+ {
+ ret = s32k3xx_pinconfig(errn_pins[i]);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d ERR_N pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+
+ ret = s32k3xx_pinconfig(stbn_pins[i] | GPIO_OUTPUT_ONE);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d STB_N pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+
+ ret = s32k3xx_pinconfig(en_pins[i] | GPIO_OUTPUT_ONE);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d EN pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+ }
+
+ /* Wait for the transition to normal mode to finish and previous status
+ * flags to be cleared before switching modes again. This is longer
+ */
+
+ up_udelay(3000);
+
+ /* Go into listen-only mode (EN low, STB_N still high) to read local
+ * failure flags.
+ */
+
+ for (i = 0; i < 4; i++)
+ {
+ s32k3xx_gpiowrite(en_pins[i], 0);
+ }
+
+ /* Wait for transition to listen-only mode to finish */
+
+ up_udelay(200);
+
+ /* Check for local failure flags and then go back to normal mode */
+
+ for (i = 0; i < 4; i++)
+ {
+ if (s32k3xx_gpioread(errn_pins[i]))
+ {
+ _info("CAN%d flag check succesful\n", i);
+ }
+ else
+ {
+ error = true;
+ _err("CAN%d flag check failed\n", i);
+
+ /* Don't return yet, we still need to cleanup */
+ }
+
+ s32k3xx_gpiowrite(en_pins[i], 1);
+ }
+
+ return (error ? -1 : 0);
+}
+
+# if !defined(CONFIG_S32K3XX_TJA1153)
+/****************************************************************************
+ * Name: s32k3xx_selftest_sct
+ *
+ * Description:
+ * Basic check of the SCTs (4-5).
+ *
+ ****************************************************************************/
+
+static int s32k3xx_selftest_sct(void)
+{
+ uint32_t stbn_pins[2] =
+ {
+ PIN_CAN4_STB,
+ PIN_CAN5_STB
+ };
+
+ uint32_t en_pins[2] =
+ {
+ PIN_CAN4_ENABLE,
+ PIN_CAN5_ENABLE
+ };
+
+ uint32_t txd_pins[2] =
+ {
+ PIN_CAN4_TX,
+ PIN_CAN5_TX
+ };
+
+ uint32_t rxd_pins[2] =
+ {
+ PIN_CAN4_RX,
+ PIN_CAN5_RX
+ };
+
+ int i;
+ int ret = 0;
+ bool error = false;
+
+ /* Configure pins and enable CAN PHY. CAN_TXD will be temporarily changed
+ * to a GPIO output to be able to control its logic level.
+ */
+
+ for (i = 4; i < 6; i++)
+ {
+ ret = s32k3xx_pinconfig(stbn_pins[i - 4] | GPIO_OUTPUT_ZERO);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d STB_N pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+
+ ret = s32k3xx_pinconfig(en_pins[i - 4] | GPIO_OUTPUT_ONE);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d EN pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+
+ ret = s32k3xx_pinconfig((txd_pins[i - 4] & (_PIN_PORT_MASK |
+ _PIN_MASK)) | GPIO_OUTPUT | GPIO_OUTPUT_ONE);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d TXD pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+
+ ret = s32k3xx_pinconfig(rxd_pins[i - 4]);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d RXD pin configuration failed\n", i);
+
+ return -1; /* Return immediately, no cleanup needed */
+ }
+ }
+
+ /* Wait for CAN PHY to detect change at TXD pin */
+
+ up_udelay(5000);
+
+ /* Check if CAN_RXD follows the high level of CAN_TXD */
+
+ for (i = 4; i < 6; i++)
+ {
+ if (s32k3xx_gpioread(rxd_pins[i - 4]))
+ {
+ _info("CAN%d RXD high check succesful\n", i);
+ }
+ else
+ {
+ error = true;
+ _err("CAN%d RXD high check failed\n", i);
+
+ /* Don't return yet, we still need to cleanup */
+ }
+ }
+
+ for (i = 4; i < 6; i++)
+ {
+ s32k3xx_gpiowrite(txd_pins[i - 4], 0);
+ }
+
+ /* Wait for CAN PHY to detect change at TXD pin */
+
+ up_udelay(5000);
+
+ /* Check if CAN_RXD follows the low level of CAN_TXD */
+
+ for (i = 4; i < 6; i++)
+ {
+ if (!s32k3xx_gpioread(rxd_pins[i - 4]))
+ {
+ _info("CAN%d RXD low check succesful\n", i);
+ }
+ else
+ {
+ error = true;
+ _err("CAN%d RXD low check failed\n", i);
+
+ /* Don't return yet, we still need to cleanup */
+ }
+ }
+
+ /* Restore CAN_TXD pinconfig */
+
+ for (i = 4; i < 6; i++)
+ {
+ s32k3xx_pinconfig(txd_pins[i - 4]);
+ if (ret != 0)
+ {
+ error = true;
+ _err("CAN%d TXD restoring pin configuration failed\n", i);
+
+ /* Don't return yet, we still need to cleanup */
+ }
+ }
+
+ return (error ? -1 : 0);
+}
+# endif /* !CONFIG_S32K3XX_TJA1153 */
+#endif /* CONFIG_S32K3XX_FLEXCAN */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_selftest
+ *
+ * Description:
+ * Runs basic routines to verify that all board components are up and
+ * running. Results are send to the syslog, it is recommended to
+ * enable all output levels (error, warning and info).
+ *
+ ****************************************************************************/
+
+void s32k3xx_selftest(void)
+{
+ int ret = 0;
+ bool error = false;
+
+#ifdef CONFIG_S32K3XX_LPI2C
+ ret = s32k3xx_selftest_se050();
+ if (ret != 0)
+ {
+ error = true;
+ _err("s32k3xx_selftest_se050() failed\n");
+ }
+#endif
+
+#ifdef CONFIG_S32K3XX_FLEXCAN
+ ret = s32k3xx_selftest_can();
+ if (ret != 0)
+ {
+ error = true;
+ _err("s32k3xx_selftest_can() failed\n");
+ }
+
+# if !defined(CONFIG_S32K3XX_TJA1153)
+ ret = s32k3xx_selftest_sct();
+ if (ret != 0)
+ {
+ error = true;
+ _err("s32k3xx_selftest_sct() failed\n");
+ }
+# endif /* !CONFIG_S32K3XX_TJA1153 */
+#endif
+
+ if (!error)
+ {
+ _info("s32k3xx_selftest() succesful\n");
+ }
+}
+
+#endif /* CONFIG_S32K3XX_SELFTEST */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c
new file mode 100644
index 0000000000..207c944ac4
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c
@@ -0,0 +1,376 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_spi.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/spi/spi.h>
+#include <nuttx/spi/spi_transfer.h>
+
+#include "s32k3xx_pin.h"
+#include "s32k3xx_lpspi.h"
+
+#include <arch/board/board.h>
+
+#include "mr-canhubk3.h"
+
+#ifdef CONFIG_S32K3XX_FS26
+#include "s32k3xx_fs26.h"
+#endif
+
+#if defined(CONFIG_S32K3XX_LPSPI2) && defined(CONFIG_MMCSD)
+#include <nuttx/mmcsd.h>
+#endif
+
+#ifdef CONFIG_S32K3XX_LPSPI
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_spidev_initialize
+ *
+ * Description:
+ * Configure chip select pins, initialize the SPI driver and register
+ * /dev/spiN devices.
+ *
+ ****************************************************************************/
+
+int weak_function s32k3xx_spidev_initialize(void)
+{
+ int ret = OK;
+
+#ifdef CONFIG_S32K3XX_LPSPI3
+ /* LPSPI3 *****************************************************************/
+
+ /* Configure LPSPI3 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI3_PCS);
+
+# ifdef CONFIG_SPI_DRIVER
+ /* Initialize the SPI driver for LPSPI3 */
+
+ struct spi_dev_s *g_lpspi3 = s32k3xx_lpspibus_initialize(3);
+ if (g_lpspi3 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI3\n");
+ return -ENODEV;
+ }
+
+ ret = spi_register(g_lpspi3, 3);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI3 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+
+# ifdef CONFIG_S32K3XX_FS26
+ fs26_initialize(g_lpspi3);
+# endif
+
+#endif /* CONFIG_S32K3XX_LPSPI3 */
+
+#ifdef CONFIG_S32K3XX_LPSPI0
+ /* LPSPI0 *****************************************************************/
+
+ /* Configure LPSPI0 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI0_PCS);
+
+# ifdef CONFIG_SPI_DRIVER
+ /* Initialize the SPI driver for LPSPI0 */
+
+ struct spi_dev_s *g_lpspi0 = s32k3xx_lpspibus_initialize(0);
+ if (g_lpspi0 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI0\n");
+ return -ENODEV;
+ }
+
+ ret = spi_register(g_lpspi0, 0);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI0 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI0 */
+
+#ifdef CONFIG_S32K3XX_LPSPI1
+ /* LPSPI1 *****************************************************************/
+
+ /* Configure LPSPI1 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI1_PCS);
+
+# ifdef CONFIG_SPI_DRIVER
+ /* Initialize the SPI driver for LPSPI1 */
+
+ struct spi_dev_s *g_lpspi1 = s32k3xx_lpspibus_initialize(1);
+ if (g_lpspi1 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI1\n");
+ return -ENODEV;
+ }
+
+ ret = spi_register(g_lpspi1, 1);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI1 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI1 */
+
+#ifdef CONFIG_S32K3XX_LPSPI2
+ /* LPSPI2 *****************************************************************/
+
+ /* Configure LPSPI2 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI2_PCS);
+
+ /* Initialize the SPI driver for LPSPI2 */
+
+ struct spi_dev_s *g_lpspi2 = s32k3xx_lpspibus_initialize(2);
+ if (g_lpspi2 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI2\n");
+ return -ENODEV;
+ }
+
+#if defined(CONFIG_S32K3XX_LPSPI2) && defined(CONFIG_MMCSD)
+
+#if defined(CONFIG_FAT_DMAMEMORY)
+ if (s32k3xx_dma_alloc_init() < 0)
+ {
+ spierr("ERROR: DMA alloc FAILED");
+ }
+#endif
+
+ if (g_lpspi2 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI2\n");
+ }
+
+ ret = mmcsd_spislotinitialize(0, 0, g_lpspi2);
+
+ if (ret < 0)
+ {
+ spierr("ERROR: Failed to bind SPI port %d to SD slot %d\n",
+ 2, 0);
+ }
+# endif
+
+# ifdef CONFIG_SPI_DRIVER
+ ret = spi_register(g_lpspi2, 2);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI2 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+
+#endif /* CONFIG_S32K3XX_LPSPI2 */
+
+#ifdef CONFIG_S32K3XX_LPSPI4
+ /* LPSPI4 *****************************************************************/
+
+ /* Configure LPSPI4 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI4_PCS);
+
+# ifdef CONFIG_SPI_DRIVER
+ /* Initialize the SPI driver for LPSPI4 */
+
+ struct spi_dev_s *g_lpspi4 = s32k3xx_lpspibus_initialize(4);
+ if (g_lpspi4 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI4\n");
+ return -ENODEV;
+ }
+
+ ret = spi_register(g_lpspi4, 4);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI4 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI4 */
+
+#ifdef CONFIG_S32K3XX_LPSPI5
+ /* LPSPI5 *****************************************************************/
+
+ /* Configure LPSPI5 peripheral chip select */
+
+ s32k3xx_pinconfig(PIN_LPSPI5_PCS);
+
+# ifdef CONFIG_SPI_DRIVER
+ /* Initialize the SPI driver for LPSPI5 */
+
+ struct spi_dev_s *g_lpspi5 = s32k3xx_lpspibus_initialize(5);
+ if (g_lpspi5 == NULL)
+ {
+ spierr("ERROR: FAILED to initialize LPSPI5\n");
+ return -ENODEV;
+ }
+
+ ret = spi_register(g_lpspi5, 5);
+ if (ret < 0)
+ {
+ spierr("ERROR: FAILED to register LPSPI5 driver\n");
+ return ret;
+ }
+# endif /* CONFIG_SPI_DRIVER */
+#endif /* CONFIG_S32K3XX_LPSPI5 */
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: s32k3xx_lpspiNselect and s32k3xx_lpspiNstatus
+ *
+ * Description:
+ * The external functions, s32k3xx_lpspiNselect and s32k3xx_lpspiNstatus
+ * must be provided by board-specific logic. They are implementations of
+ * the select and status methods of the SPI interface defined by struct
+ * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including
+ * s32k3xx_lpspibus_initialize()) are provided by common logic. To use
+ * this common SPI logic on your board:
+ *
+ * 1. Provide logic in s32k3xx_boardinitialize() to configure SPI chip
+ * select pins.
+ * 2. Provide s32k3xx_lpspiNselect() and s32k3xx_lpspiNstatus() functions
+ * in your board-specific logic. These functions will perform chip
+ * selection and status operations using GPIOs in the way your board is
+ * configured.
+ * 3. Add a calls to s32k3xx_lpspibus_initialize() in your low level
+ * application initialization logic.
+ * 4. The handle returned by s32k3xx_lpspibus_initialize() may then be used
+ * to bind the SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_S32K3XX_LPSPI1
+/* LPSPI1 *******************************************************************/
+
+void s32k3xx_lpspi1select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI1_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi1status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI1 */
+
+#ifdef CONFIG_S32K3XX_LPSPI2
+/* LPSPI2 *******************************************************************/
+
+void s32k3xx_lpspi2select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI2_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi2status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 1;
+}
+#endif /* CONFIG_S32K3XX_LPSPI2 */
+
+#ifdef CONFIG_S32K3XX_LPSPI3
+/* LPSPI3 *******************************************************************/
+
+void s32k3xx_lpspi3select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI3_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi3status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI3 */
+
+#ifdef CONFIG_S32K3XX_LPSPI4
+/* LPSPI4 *******************************************************************/
+
+void s32k3xx_lpspi4select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI4_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi4status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI4 */
+
+#ifdef CONFIG_S32K3XX_LPSPI5
+/* LPSPI5 *******************************************************************/
+
+void s32k3xx_lpspi5select(struct spi_dev_s *dev, uint32_t devid,
+ bool selected)
+{
+ spiinfo("devid: %" PRId32 ", CS: %s\n", devid,
+ selected ? "assert" : "de-assert");
+
+ s32k3xx_gpiowrite(PIN_LPSPI5_PCS, !selected);
+}
+
+uint8_t s32k3xx_lpspi5status(struct spi_dev_s *dev, uint32_t devid)
+{
+ return 0;
+}
+#endif /* CONFIG_S32K3XX_LPSPI5 */
+#endif /* CONFIG_S32K3XX_LPSPI */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c
new file mode 100644
index 0000000000..738fdb8bfe
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c
@@ -0,0 +1,334 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_tja1153.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP
+ *
+ * This TJA1153 initialization routine is intended for ENGINEERING
+ * DEVELOPMENT OR EVALUATION PURPOSES ONLY. It is provided as an example to
+ * use the TJA1153. Please refer to the datasheets and application hints
+ * provided on NXP.com to implement full functionality.
+ */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+#include <string.h>
+#include <unistd.h>
+#include <net/if.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#include <nuttx/can.h>
+#include <netpacket/can.h>
+#include <nuttx/signal.h>
+
+#include "s32k3xx_pin.h"
+#include <arch/board/board.h>
+#include "mr-canhubk3.h"
+
+#ifdef CONFIG_S32K3XX_TJA1153
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Bitrate must be set to 125, 250 or 500 kbit/s for CAN 2.0 and CAN FD
+ * arbitration phase
+ */
+
+#ifdef CONFIG_S32K3XX_FLEXCAN4
+# if CONFIG_NET_CAN_CANFD
+# if CONFIG_FLEXCAN4_ARBI_BITRATE > 500000
+# error "FLEXCAN4_ARBI_BITRATE > 500000"
+# endif
+# else
+# if CONFIG_FLEXCAN4_BITRATE > 500000
+# error "FLEXCAN4_BITRATE > 500000"
+# endif
+# endif
+#endif
+
+#ifdef CONFIG_S32K3XX_FLEXCAN5
+# if CONFIG_NET_CAN_CANFD
+# if CONFIG_FLEXCAN5_ARBI_BITRATE > 500000
+# error "FLEXCAN5_ARBI_BITRATE > 500000"
+# endif
+# else
+# if CONFIG_FLEXCAN5_BITRATE > 500000
+# error "FLEXCAN5_BITRATE > 500000"
+# endif
+# endif
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: s32k3xx_tja1153_initialize
+ *
+ * Description:
+ * Initialize a TJA1153 CAN PHY connected to a FlexCAN peripheral (0-5)
+ *
+ ****************************************************************************/
+
+int s32k3xx_tja1153_initialize(int bus)
+{
+ int sock;
+ struct sockaddr_can addr;
+ struct can_frame frame_config1;
+ struct can_frame frame_config2;
+ struct can_frame frame_config3;
+ struct can_frame frame_config4;
+ struct can_frame frame_config5;
+ struct ifreq ifr;
+ uint32_t pin_can_txd;
+ uint32_t pin_can_rxd;
+ uint32_t pin_can_enable;
+ uint32_t pin_can_stb_n;
+ int ret = 0;
+
+ /* Select interface and pins */
+
+ switch (bus)
+ {
+#ifdef CONFIG_S32K3XX_FLEXCAN4
+ case 4:
+ {
+ strlcpy(ifr.ifr_name, "can4", IFNAMSIZ);
+
+ pin_can_txd = PIN_CAN4_TX;
+ pin_can_rxd = PIN_CAN4_RX;
+ pin_can_enable = PIN_CAN4_ENABLE;
+ pin_can_stb_n = PIN_CAN4_STB;
+ }
+ break;
+#endif
+#ifdef CONFIG_S32K3XX_FLEXCAN5
+ case 5:
+ {
+ strlcpy(ifr.ifr_name, "can5", IFNAMSIZ);
+
+ pin_can_txd = PIN_CAN5_TX;
+ pin_can_rxd = PIN_CAN5_RX;
+ pin_can_enable = PIN_CAN5_ENABLE;
+ pin_can_stb_n = PIN_CAN5_STB;
+ }
+ break;
+#endif
+ default:
+ {
+ /* This FlexCAN is not supported (yet) */
+
+ return -1;
+ }
+ }
+
+ /* First check if configuration is actually needed */
+
+ s32k3xx_pinconfig((pin_can_txd & (_PIN_PORT_MASK | _PIN_MASK)) |
+ GPIO_OUTPUT | GPIO_OUTPUT_ZERO);
+
+ if (s32k3xx_gpioread(pin_can_rxd))
+ {
+ _info("CAN%d TJA1153 already configured\n", bus);
+
+ s32k3xx_pinconfig(pin_can_txd); /* Restore CAN_TXD pinconfig */
+ return 0;
+ }
+
+ s32k3xx_pinconfig(pin_can_txd); /* Restore CAN_TXD pinconfig */
+
+ /* Find network interface */
+
+ ifr.ifr_ifindex = if_nametoindex(ifr.ifr_name);
+ if (!ifr.ifr_ifindex)
+ {
+ _err("CAN%d TJA1153: if_nametoindex failed\n", bus);
+ return -1;
+ }
+
+ /* Configure pins */
+
+ s32k3xx_pinconfig(pin_can_enable);
+ s32k3xx_pinconfig(pin_can_stb_n);
+
+ s32k3xx_gpiowrite(pin_can_enable, true); /* Enable TJA1153 */
+ s32k3xx_gpiowrite(pin_can_stb_n, false); /* Inverted, so TJA1153 is put in STANDBY */
+
+ /* Init CAN frames, e.g. LEN = 0 */
+
+ memset(&frame_config1, 0, sizeof(frame_config1));
+ memset(&frame_config2, 0, sizeof(frame_config2));
+ memset(&frame_config3, 0, sizeof(frame_config3));
+ memset(&frame_config4, 0, sizeof(frame_config4));
+ memset(&frame_config5, 0, sizeof(frame_config5));
+
+ /* Prepare CAN frames. Refer to the TJA1153 datasheets and application
+ * hints available on NXP.com for details.
+ */
+
+ frame_config1.can_id = 0x555;
+ frame_config1.can_dlc = 0;
+
+ frame_config2.can_id = 0x18da00f1 | CAN_EFF_FLAG;
+ frame_config2.can_dlc = 6;
+ frame_config2.data[0] = 0x10;
+ frame_config2.data[1] = 0x00;
+ frame_config2.data[2] = 0x50;
+ frame_config2.data[3] = 0x00;
+ frame_config2.data[4] = 0x07;
+ frame_config2.data[5] = 0xff;
+
+ frame_config3.can_id = 0x18da00f1 | CAN_EFF_FLAG;
+ frame_config3.can_dlc = 6;
+ frame_config3.data[0] = 0x10;
+ frame_config3.data[1] = 0x01;
+ frame_config3.data[2] = 0x9f;
+ frame_config3.data[3] = 0xff;
+ frame_config3.data[4] = 0xff;
+ frame_config3.data[5] = 0xff;
+
+ frame_config4.can_id = 0x18da00f1 | CAN_EFF_FLAG;
+ frame_config4.can_dlc = 6;
+ frame_config4.data[0] = 0x10;
+ frame_config4.data[1] = 0x02;
+ frame_config4.data[2] = 0xc0;
+ frame_config4.data[3] = 0x00;
+ frame_config4.data[4] = 0x00;
+ frame_config4.data[5] = 0x00;
+
+ frame_config5.can_id = 0x18da00f1 | CAN_EFF_FLAG;
+ frame_config5.can_dlc = 8;
+ frame_config5.data[0] = 0x71;
+ frame_config5.data[1] = 0x02;
+ frame_config5.data[2] = 0x03;
+ frame_config5.data[3] = 0x04;
+ frame_config5.data[4] = 0x05;
+ frame_config5.data[5] = 0x06;
+ frame_config5.data[6] = 0x07;
+ frame_config5.data[7] = 0x08;
+
+ /* Open socket */
+
+ if ((sock = socket(PF_CAN, SOCK_RAW, CAN_RAW)) < 0)
+ {
+ _err("CAN%d TJA1153: Failed to open socket\n", bus);
+ return -1;
+ }
+
+ /* Bring up the interface */
+
+ ifr.ifr_flags = IFF_UP;
+ ret = ioctl(sock, SIOCSIFFLAGS, (unsigned long)&ifr);
+ if (ret < 0)
+ {
+ _err("CAN%d TJA1153: ioctl failed (can't set interface flags)\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ /* Initialize sockaddr struct */
+
+ memset(&addr, 0, sizeof(addr));
+ addr.can_family = AF_CAN;
+ addr.can_ifindex = ifr.ifr_ifindex;
+
+ /* Disable default receive filter on this RAW socket
+ *
+ * This is obsolete as we do not read from the socket at all, but for this
+ * reason we can remove the receive list in the kernel to save a little
+ * (really very little!) CPU usage.
+ */
+
+ setsockopt(sock, SOL_CAN_RAW, CAN_RAW_FILTER, NULL, 0);
+
+ /* Bind socket and send the CAN frames */
+
+ if (bind(sock, (struct sockaddr *)&addr, sizeof(addr)) < 0)
+ {
+ _err("CAN%d TJA1153: Failed to bind socket\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ if (write(sock, &frame_config1, CAN_MTU) != CAN_MTU)
+ {
+ _err("CAN%d TJA1153: Failed to write frame_config1\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ if (write(sock, &frame_config2, CAN_MTU) != CAN_MTU)
+ {
+ _err("CAN%d TJA1153: Failed to write frame_config2\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ if (write(sock, &frame_config3, CAN_MTU) != CAN_MTU)
+ {
+ _err("CAN%d TJA1153: Failed to write frame_config3\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ if (write(sock, &frame_config4, CAN_MTU) != CAN_MTU)
+ {
+ _err("CAN%d TJA1153: Failed to write frame_config4\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ if (write(sock, &frame_config5, CAN_MTU) != CAN_MTU)
+ {
+ _err("CAN%d TJA1153: Failed to write frame_config5\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ /* Sleep for 100 ms to ensure that CAN frames have been transmitted */
+
+ nxsig_usleep(100 * 1000);
+
+ /* TJA1153 must be taken out of STB mode */
+
+ s32k3xx_gpiowrite(pin_can_stb_n, true); /* Inverted, so TJA1153 comes out of STANDBY */
+
+ /* Bring down the interface */
+
+ ifr.ifr_flags = IFF_DOWN;
+ ret = ioctl(sock, SIOCSIFFLAGS, (unsigned long)&ifr);
+ if (ret < 0)
+ {
+ _err("CAN%d TJA1153: ioctl failed (can't set interface flags)\n", bus);
+ close(sock);
+ return -1;
+ }
+
+ close(sock);
+ _info("CAN%d TJA1153 configuration succesful\n", bus);
+ return 0;
+}
+
+#endif /* CONFIG_S32K3XX_TJA1153 */
diff --git a/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
new file mode 100644
index 0000000000..e3dffda672
--- /dev/null
+++ b/boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
@@ -0,0 +1,103 @@
+/****************************************************************************
+ * boards/arm/s32k3xx/mr-canhubk3/src/s32k3xx_userleds.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* Copyright 2022 NXP */
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <nuttx/board.h>
+
+#include "s32k3xx_pin.h"
+
+#include <arch/board/board.h>
+
+#include "mr-canhubk3.h"
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+uint32_t board_userled_initialize(void)
+{
+ /* Configure LED GPIOs for output */
+
+ s32k3xx_pinconfig(GPIO_LED_R);
+ s32k3xx_pinconfig(GPIO_LED_G);
+ s32k3xx_pinconfig(GPIO_LED_B);
+ return BOARD_NLEDS;
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+ uint32_t ledcfg;
+
+ if (led == BOARD_LED_R)
+ {
+ ledcfg = GPIO_LED_R;
+ }
+ else if (led == BOARD_LED_G)
+ {
+ ledcfg = GPIO_LED_G;
+ }
+ else if (led == BOARD_LED_B)
+ {
+ ledcfg = GPIO_LED_B;
+ }
+ else
+ {
+ return;
+ }
+
+ /* Invert output, an output of '0' illuminates the LED */
+
+ s32k3xx_gpiowrite(ledcfg, !ledon);
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint32_t ledset)
+{
+ /* Invert output, an output of '0' illuminates the LED */
+
+ s32k3xx_gpiowrite(GPIO_LED_R, !((ledset & BOARD_LED_R_BIT) != 0));
+ s32k3xx_gpiowrite(GPIO_LED_G, !((ledset & BOARD_LED_G_BIT) != 0));
+ s32k3xx_gpiowrite(GPIO_LED_B, !((ledset & BOARD_LED_B_BIT) != 0));
+}
+
+#endif /* !CONFIG_ARCH_LEDS */
[incubator-nuttx] 09/09: Evaluate n in preprocessor before masking
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 9e7e45df76c124b01066c2ec1f13c148ddc80c3a
Author: Peter van der Perk <pe...@nxp.com>
AuthorDate: Mon Jul 25 13:11:06 2022 +0200
Evaluate n in preprocessor before masking
---
arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h | 30 ++++++++++++++--------------
arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h | 2 +-
2 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
index fab62c1d9e..91aa869cd1 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_qspi.h
@@ -171,11 +171,11 @@
#define QSPICR_IDATSZ_SHIFT (0) /* Bits 0-15: IP data transfer size (IDATSZ) */
#define QSPICR_IDATSZ_MASK (0xffff << QSPICR_IDATSZ_SHIFT)
-#define QSPICR_IDATSZ(n) ((n << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
+#define QSPICR_IDATSZ(n) (((n) << QSPICR_IDATSZ_SHIFT) & QSPICR_IDATSZ_MASK)
/* Bits 16-23: Reserved */
#define QSPICR_SEQID_SHIFT (24) /* Bits 24-27: Points to a sequence in the LUT (SEQID) */
#define QSPICR_SEQID_MASK (0x0f << QSPICR_SEQID_SHIFT)
-#define QSPICR_SEQID(n) ((n << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
+#define QSPICR_SEQID(n) (((n) << QSPICR_SEQID_SHIFT) & QSPICR_SEQID_MASK)
/* Bits 28-31: Reserved */
/* Flash Memory Configuration Register (FLSHCR) */
@@ -185,18 +185,18 @@
#define QSPI_FLSHCR_TCSS(n) (n & QSPI_FLSHCR_TCSS_MASK)
#define QSPI_FLSHCR_TCSH_SHIFT (8) /* Bits 8-11: Serial flash memory CS hold time (TCSH) */
#define QSPI_FLSHCR_TCSH_MASK (0x0f << QSPI_FLSHCR_TCSH_SHIFT)
-#define QSPI_FLSHCR_TCSH(n) ((n << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
+#define QSPI_FLSHCR_TCSH(n) (((n) << QSPI_FLSHCR_TCSH_SHIFT) & QSPI_FLSHCR_TCSH_MASK)
/* Bits 12-31: Reserved */
/* Buffer n Configuration Register (BUFnCR) */
#define QSPI_BUFCR_MSTRID_SHIFT (0) /* Bits 0-3: Master ID (MSTRID) */
#define QSPI_BUFCR_MSTRID_MASK (0x0f << QSPI_BUFCR_MSTRID_SHIFT)
-#define QSPI_BUFCR_MSTRID(n) ((n << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
+#define QSPI_BUFCR_MSTRID(n) (((n) << QSPI_BUFCR_MSTRID_SHIFT) & QSPI_BUFCR_MSTRID_MASK)
/* Bits 4-7: Reserved */
#define QSPI_BUFCR_ADATSZ_SHIFT (8) /* Bits 8-13: AHB data transfer size (ADATSZ) */
#define QSPI_BUFCR_ADATSZ_MASK (0x3f << QSPI_BUFCR_ADATSZ_SHIFT)
-#define QSPI_BUFCR_ADATSZ(n) ((n << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
+#define QSPI_BUFCR_ADATSZ(n) (((n) << QSPI_BUFCR_ADATSZ_SHIFT) & QSPI_BUFCR_ADATSZ_MASK)
/* Bits 14-31: Reserved */
#define QSPI_BUF3CR_ALLMST (1 << 31) /* Bit 31: All master enable (ALLMST) */
@@ -235,10 +235,10 @@
#define QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT (8) /* Bits 8-11: Delay elements in each delay tap (SLV_DLY_COARSE) */
#define QSPI_DLLCRA_SLV_DLY_COARSE_MASK (0x0f << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT)
-#define QSPI_DLLCRA_SLV_DLY_COARSE(n) ((n << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
+#define QSPI_DLLCRA_SLV_DLY_COARSE(n) (((n) << QSPI_DLLCRA_SLV_DLY_COARSE_SHIFT) & QSPI_DLLCRA_SLV_DLY_COARSE_MASK)
#define QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT (12) /* Bits 12-14: T/16 offset delay elements in incoming DQS (SLV_DLY_OFFSET) */
#define QSPI_DLLCRA_SLV_DLY_OFFSET_MASK (0x07 << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT)
-#define QSPI_DLLCRA_SLV_DLY(n) ((n << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
+#define QSPI_DLLCRA_SLV_DLY(n) (((n) << QSPI_DLLCRA_SLV_DLY_OFFSET_SHIFT) & QSPI_DLLCRA_SLV_DLY_OFFSET_MASK)
/* Bit 15: Reserved */
#define QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT (16) /* Bits 16-19: Fine offset delay elements in incoming DQS (SLV_FINE_OFFSET) */
#define QSPI_DLLCRA_SLV_FINE_OFFSET_MASK (0x0f << QSPI_DLLCRA_SLV_FINE_OFFSET_SHIFT)
@@ -259,7 +259,7 @@
/* Bits 7-23: Reserved */
#define QSPI_SMPR_DLLFSMPFA_SHIFT (24) /* Bits 24-26: Selects the nth tap provided by slave delay chain for flash memory A (DLLFSMPFA) */
#define QSPI_SMPR_DLLFSMPFA_MASK (0x07 << QSPI_SMPR_DLLFSMPFA_SHIFT)
-#define QSPI_SMPR_DLLFSMPFA(n) ((n << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
+#define QSPI_SMPR_DLLFSMPFA(n) (((n) << QSPI_SMPR_DLLFSMPFA_SHIFT) & QSPI_SMPR_DLLFSMPFA_MASK)
/* Bits 27-31: Reserved */
/* RX Buffer Status Register (RBSR) */
@@ -274,7 +274,7 @@
#define QSPI_RBCT_WMRK_SHIFT (0) /* Bits 0-6: RX buffer watermark (WMRK) */
#define QSPI_RBCT_WMRK_MASK (0x7f << QSPI_RBCT_WMRK_SHIFT)
-#define QSPI_RBCT_WMRK(n) ((n << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
+#define QSPI_RBCT_WMRK(n) (((n) << QSPI_RBCT_WMRK_SHIFT) & QSPI_RBCT_WMRK_MASK)
/* Bit 7: Reserved */
#define QSPI_RBCT_RXBRD (1 << 8) /* Bit 8: RX buffer readout (RXBRD) */
# define QSPI_RBCT_RXBRD_AHB (0 << 8) /* RX buffer content is read using the AHB bus registers */
@@ -307,7 +307,7 @@
#define QSPI_TBCT_WMRK_SHIFT (0) /* Bits 0-4: Watermark for TX buffer (WMRK) */
#define QSPI_TBCT_WMRK_MASK (0x1f << QSPI_TBCT_WMRK_SHIFT)
-#define QSPI_TBCT_WMRK(n) ((n << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
+#define QSPI_TBCT_WMRK(n) (((n) << QSPI_TBCT_WMRK_SHIFT) & QSPI_TBCT_WMRK_MASK)
/* Bits 5-31: Reserved */
/* Status Register (SR) */
@@ -392,7 +392,7 @@
/* Bits 0-9: Reserved */
#define QSPI_SFAD_TPAD_SHIFT (10) /* Bits 10-31: Top address for serial flash memory An/Bn (TPADAn/TPADBn) */
#define QSPI_SFAD_TPAD_MASK (0x3fffff << QSPI_SFAD_TPAD_SHIFT)
-#define QSPI_SFAD_TPAD(n) ((n << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
+#define QSPI_SFAD_TPAD(n) (((n) << QSPI_SFAD_TPAD_SHIFT) & QSPI_SFAD_TPAD_MASK)
/* RX Buffer Data Register (RBDRn, n=0,...,63) */
@@ -415,7 +415,7 @@
#define QSPI_LUT_OPRND0_SHIFT (0) /* Bits 0-7: Operand for INSTR0 (OPRND0) */
#define QSPI_LUT_OPRND0_MASK (0xff << QSPI_LUT_OPRND0_SHIFT)
-#define QSPI_LUT_OPRND0(n) ((n << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
+#define QSPI_LUT_OPRND0(n) (((n) << QSPI_LUT_OPRND0_SHIFT) & QSPI_LUT_OPRND0_MASK)
#define QSPI_LUT_PAD0_SHIFT (8) /* Bits 8-9: Pad information for INSTR0 (PAD0) */
#define QSPI_LUT_PAD0_MASK (0x03 << QSPI_LUT_PAD0_SHIFT)
# define QSPI_LUT_PAD0_1 (0x00 << QSPI_LUT_PAD0_SHIFT) /* 1 Pad */
@@ -424,11 +424,11 @@
#define QSPI_LUT_INSTR0_SHIFT (10) /* Bits 10-15: Instruction 0 (INSTR0) */
#define QSPI_LUT_INSTR0_MASK (0x3f << QSPI_LUT_INSTR0_SHIFT)
-#define QSPI_LUT_INSTR0(n) ((n << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
+#define QSPI_LUT_INSTR0(n) (((n) << QSPI_LUT_INSTR0_SHIFT) & QSPI_LUT_INSTR0_MASK)
#define QSPI_LUT_OPRND1_SHIFT (16) /* Bits 16-23: Operand for INSTR1 (OPRND1) */
#define QSPI_LUT_OPRND1_MASK (0xff << QSPI_LUT_OPRND1_SHIFT)
-#define QSPI_LUT_OPRND1(n) ((n << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
+#define QSPI_LUT_OPRND1(n) (((n) << QSPI_LUT_OPRND1_SHIFT) & QSPI_LUT_OPRND1_MASK)
#define QSPI_LUT_PAD1_SHIFT (24) /* Bits 24-25: Pad information for INSTR1 (PAD1) */
#define QSPI_LUT_PAD1_MASK (0x03 << QSPI_LUT_PAD1_SHIFT)
# define QSPI_LUT_PAD1_1 (0x00 << QSPI_LUT_PAD1_SHIFT) /* 1 Pad */
@@ -437,7 +437,7 @@
#define QSPI_LUT_INSTR1_SHIFT (26) /* Bits 26-31: Instruction 1 (INSTR1) */
#define QSPI_LUT_INSTR1_MASK (0x3f << QSPI_LUT_INSTR1_SHIFT)
-#define QSPI_LUT_INSTR1(n) ((n << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
+#define QSPI_LUT_INSTR1(n) (((n) << QSPI_LUT_INSTR1_SHIFT) & QSPI_LUT_INSTR1_MASK)
/* External Memory Base Address */
diff --git a/arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h b/arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h
index 17ce4a0812..07b0f68dc3 100644
--- a/arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h
+++ b/arch/arm/src/s32k3xx/hardware/s32k3xx_stm.h
@@ -91,7 +91,7 @@
/* Bits 2-7: Reserved */
#define STM_CR_CPS_SHIFT (8) /* Bits 8-15: Counter Prescaler (CPS) */
#define STM_CR_CPS_MASK (0xff << STM_CR_CPS_SHIFT)
-#define STM_CR_CPS(n) ((n << STM_CR_CPS_SHIFT) & STM_CR_CPS_MASK)
+#define STM_CR_CPS(n) (((n) << STM_CR_CPS_SHIFT) & STM_CR_CPS_MASK)
/* Bits 16-31: Reserved */
/* Count Register (CNT) */