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Posted to commits@nuttx.apache.org by xi...@apache.org on 2023/05/26 19:29:50 UTC
[nuttx] 03/07: procfs：add armv7-a cpuinfo
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 5c5d9420af76070456dc767aa8dc411d2b13b9b8
Author: liaoao <li...@xiaomi.com>
AuthorDate: Sat May 6 15:46:36 2023 +0800
procfs：add armv7-a cpuinfo
Signed-off-by: liaoao <li...@xiaomi.com>
---
arch/arm/Kconfig | 1 +
arch/arm/src/armv7-a/Make.defs | 2 +-
arch/arm/src/armv7-a/arm_cpuinfo.c | 167 +++++++++++++++++++++++++++++++++++++
3 files changed, 169 insertions(+), 1 deletion(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1c9d8a730b..050bb98834 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -772,6 +772,7 @@ config ARCH_CORTEXM7
config ARCH_ARMV7A
bool
default n
+ select ARCH_HAVE_CPUINFO
select ARM_HAVE_WFE_SEV
config ARCH_CORTEXA5
diff --git a/arch/arm/src/armv7-a/Make.defs b/arch/arm/src/armv7-a/Make.defs
index 618699ff0e..ddb629b693 100644
--- a/arch/arm/src/armv7-a/Make.defs
+++ b/arch/arm/src/armv7-a/Make.defs
@@ -41,7 +41,7 @@ CMN_ASRCS += arm_saveusercontext.S
# Common C source files
-CMN_CSRCS += arm_cache.c arm_dataabort.c
+CMN_CSRCS += arm_cache.c arm_cpuinfo.c arm_dataabort.c
CMN_CSRCS += arm_doirq.c arm_gicv2.c arm_gicv2_dump.c
CMN_CSRCS += arm_initialstate.c arm_mmu.c arm_prefetchabort.c
CMN_CSRCS += arm_schedulesigaction.c arm_sigdeliver.c
diff --git a/arch/arm/src/armv7-a/arm_cpuinfo.c b/arch/arm/src/armv7-a/arm_cpuinfo.c
new file mode 100644
index 0000000000..cc1b0e3508
--- /dev/null
+++ b/arch/arm/src/armv7-a/arm_cpuinfo.c
@@ -0,0 +1,167 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_cpuinfo.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/arch.h>
+#include <nuttx/config.h>
+#include <nuttx/fs/procfs.h>
+
+#include "arm_internal.h"
+#include "hwcap.h"
+#include "cp15.h"
+
+#if defined(CONFIG_FS_PROCFS) && !defined(CONFIG_FS_PROCFS_EXCLUDE_CPUINFO)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * name: hwcap_extract_field
+ ****************************************************************************/
+
+static int hwcap_extract_field(uint32_t features, int field)
+{
+ int feature;
+
+ feature = (features >> field) & 0xf;
+ if (feature > 7)
+ {
+ feature -= 16;
+ }
+
+ return feature;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * name: up_show_cpuinfo
+ ****************************************************************************/
+
+ssize_t up_show_cpuinfo(FAR char *buf, size_t buf_size, off_t file_off)
+{
+ int i;
+ uint32_t cpuid;
+
+ for (i = 0; i < CONFIG_SMP_NCPUS; i++)
+ {
+ procfs_sprintf(buf, buf_size, &file_off, "processor\t: %d\n", i);
+ procfs_sprintf(buf, buf_size, &file_off, "BogoMIPS\t: %u.%02u\n",
+ (CONFIG_BOARD_LOOPSPERMSEC / 1000),
+ (CONFIG_BOARD_LOOPSPERMSEC / 10) % 100);
+ procfs_sprintf(buf, buf_size, &file_off, "cpu MHz\t\t: %lu.%02lu\n",
+ up_perf_getfreq() / 1000000,
+ (up_perf_getfreq() / 10000) % 100);
+
+ /* CPU Features */
+
+ procfs_sprintf(buf, buf_size, &file_off, "Features\t:");
+ procfs_sprintf(buf, buf_size, &file_off, " %s %s %s",
+ HWCAP_HALF, HWCAP_FAST_MULT, HWCAP_EDSP);
+
+ /* If the CPU supports LDREX/STREX and LDREXB/STREXB,
+ * avoid advertising SWP; it may not be atomic with
+ * multiprocessing cores.
+ */
+
+ if (hwcap_extract_field(CP15_GET(ID_ISAR3), 12) <= 1 &&
+ hwcap_extract_field(CP15_GET(ID_ISAR4), 20) < 3)
+ {
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_SWP);
+ }
+
+#ifdef CONFIG_ARM_THUMB
+ if (hwcap_extract_field(CP15_GET(ID_ISAR0), 24) >= 1)
+ {
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_IDIVT);
+ }
+
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_THUMB);
+#endif
+ if (hwcap_extract_field(CP15_GET(ID_ISAR0), 24) == 2)
+ {
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_IDIVA);
+ }
+
+#ifdef CONFIG_SCHED_THREAD_LOCAL
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_TLS);
+#endif
+
+ /* LPAE implies atomic ldrd/strd instructions */
+
+ if (hwcap_extract_field(CP15_GET(ID_ISAR2), 0) == 1)
+ {
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_LPAE);
+ }
+
+ /* VFP Features */
+
+#if defined(CONFIG_ARCH_FPU)
+# if defined(CONFIG_ARCH_CORTEXA8) || defined(CONFIG_ARCH_CORTEXA9)
+ procfs_sprintf(buf, buf_size, &file_off, " %s %s %s",
+ HWCAP_VFPV3, HWCAP_FPSP, HWCAP_FPDP);
+# else
+ procfs_sprintf(buf, buf_size, &file_off, " %s %s %s",
+ HWCAP_VFPV4, HWCAP_FPSP, HWCAP_FPDP);
+# endif
+
+# if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA9)
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_FPHP);
+# endif
+
+# ifdef CONFIG_ARM_DPFPU32
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_VFPD32);
+# else
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_VFPV3D16);
+# endif
+
+# ifdef CONFIG_ARM_NEON
+ procfs_sprintf(buf, buf_size, &file_off, " %s", HWCAP_NEON);
+# endif
+#endif
+
+ /* Cpuid info */
+
+ cpuid = CP15_GET(MIDR);
+ procfs_sprintf(buf, buf_size, &file_off,
+ "\nmodel name\t: %s rev %" PRIx32 " (%s)\n"
+ "CPU architecture: %s\n",
+ "ARMv7 Processor", cpuid & 15, "v7", "7");
+
+ procfs_sprintf(buf, buf_size, &file_off,
+ "CPU implementer\t: 0x%02" PRIx32 "\n"
+ "CPU variant\t: 0x%" PRIx32 "\n"
+ "CPU part\t: 0x%03" PRIx32 "\n"
+ "CPU revision\t: %" PRIu32 "\n\n",
+ cpuid >> 24,
+ (cpuid >> 20) & 0xf,
+ (cpuid >> 4) & 0xfff,
+ cpuid & 0xf);
+ }
+
+ return -file_off;
+}
+#endif /* CONFIG_FS_PROCFS && !CONFIG_FS_PROCFS_EXCLUDE_CPUINFO */