[PR] {Bp-13606} armv7/8m: use pendsv to handle context switch [nuttx]

["jerpelea (via GitHub)" <gi...@apache.org>]

jerpelea opened a new pull request, #14395:
URL: https://github.com/apache/nuttx/pull/14395

   armv6/7/8m: use pendsv to handle context switch
   
   This PR support Nested interrupt in armv6/7/8m:
   
   There are two types of nested interrupt model:
   
       Zero latency nested interrupt
   
   Interrupt           Priority            Note
   Data abort          Highest
   SVC                 0x50
   High irq1           0x60             ISR can't access system API
   irq_save()          0x70
   High irq2           0x80             ISR can't access system API
   normal irq3         0xB0
   
   We have already support this mode before this PR
   
       Nested interrupt which interrupt level lower than up_irq_save()
   
   Interrupt           Priority            Note
   Data abort          Highest
   SVC                 0x70
   irq_save()          0x80
   High irq1           0x90              ISR can access system API
   High irq2           0xA0              ISR can access system API
   normal irq3         0xB0
   
   Now, this PR can support this mode
   Impact
   
   arm-m
   Testing
   
   qemu
   
   ./tools/configure.sh mps2-an500:nsh -j8
   
   which described in:
   https://github.com/apache/nuttx-apps/pull/2535


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Re: [PR] {Bp-13606} armv7/8m: use pendsv to handle context switch [nuttx]

["xiaoxiang781216 (via GitHub)" <gi...@apache.org>]

xiaoxiang781216 merged PR #14395:
URL: https://github.com/apache/nuttx/pull/14395


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Re: [PR] {Bp-13606} armv7/8m: use pendsv to handle context switch [nuttx]

["nuttxpr (via GitHub)" <gi...@apache.org>]

nuttxpr commented on PR #14395:
URL: https://github.com/apache/nuttx/pull/14395#issuecomment-2421623809

   [**\[Experimental Bot, please feedback here\]**](https://github.com/search?q=repo%3Aapache%2Fnuttx+13552&type=issues)
   
   
   
   ## NuttX PR Requirements Review
   
   **Summary:** The PR aims to support nested interrupts where the interrupt level is lower than `up_irq_save()` for ARMv6/7/8M architectures. 
   
   **Meets Requirements?** 
   
   * **Summary:** Partially. While the "what" is clear, the "why" and "how" could be elaborated. Explain the benefits of this new nested interrupt model and the technical approach used (e.g., using PendSV for context switching). 
   * **Impact:** 
       * **New Feature:** YES - Nested interrupt support for specific levels.
       * **User Impact:** Potentially YES -  Users utilizing interrupts might be affected.  Specify if any user-level code changes are needed. 
       * **Build Impact:**  Unclear -  Mention if any build system changes are required.
       * **Hardware Impact:** YES - ARMv6/7/8M architectures. 
       * **Documentation Impact:** Likely YES -  Document the new interrupt model and its usage.
       * **Security Impact:**  Potentially YES - Nested interrupts can have security implications. Analyze and document any potential risks or mitigations.
       * **Compatibility Impact:** Potentially YES - Assess if this change affects backward compatibility with existing applications using interrupts. 
   * **Testing:**
       * **Build Host(s):**  Incomplete - Specify the OS, CPU architecture, and compiler used for testing.
       * **Target(s):**  qemu (sim), ARM architecture. Be specific about the board configuration used.
       * **Logs:**  Provide actual testing logs before and after the change.
   
   ## Recommendations
   
   1. **Expand the Summary:** Explain the motivation, benefits, and technical implementation details of using PendSV for context switching.
   2. **Analyze Impact Thoroughly:** Provide specific details on user impact, build changes (if any), and potential security implications.  Address backward compatibility concerns.
   3. **Complete Testing Information:** Specify the build host environment and include actual testing logs demonstrating the change's functionality. 
   4. **Document the Changes:**  Update the documentation to reflect the new interrupt model and guide users on its proper utilization. 
   


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