[GitHub] [nuttx] pussuw commented on pull request #9577: riscv/fpu: Implement correct lazy-FPU functionality (attempt #2)

["pussuw (via GitHub)" <gi...@apache.org>]

pussuw commented on PR #9577:
URL: https://github.com/apache/nuttx/pull/9577#issuecomment-1651802464

   I was able to reproduce the ostest crash on qemu-rv and it should now be fixed. Also, rv-virt:ksmp64 is not crashing any longer either.
   
   ## Changes since last PR round
    
   Moving the MMU change and FPU restore to riscv_internal.h / riscv_restorecontext() works for single core but not for multicore, so they are both moved back into riscv_doirq.c. (and riscv_perform_syscall.c). 
   
   SMP seems to expect this order of execution, I don't know why though.
   
   ## Why does the ostest crash happen ?
   
   The crash is due to mishandling of the floating point control/status register (fcsr). The illegal istruction happes due to incorrect / stale rouding mode, from the risc-v spec:
   
   Floating-point operations use either a static rounding mode encoded in the instruction, or a dynamic
   rounding mode held in frm. Rounding modes are encoded as shown in Table 8.1. A value of 111 in
   the instruction’s rm field selects the dynamic rounding mode held in frm. If frm is set to an invalid
   value (101–111), any subsequent attempt to execute a floating-point operation with a dynamic
   rounding mode will cause an illegal instruction trap. Some instructions that have the rm field are
   nevertheless unaffected by the rounding mode; they should have their rm field set to RNE (000).
   
   So the CPU (FPU status register) status was not updated correctly in the SMP case.


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