You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by ja...@apache.org on 2020/09/10 07:21:03 UTC
[mynewt-core] 02/02: Update NRFX to release 2.3.0
This is an automated email from the ASF dual-hosted git repository.
janc pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 31f44295e3afc0a9eca105694c823100799db07b
Author: Szymon Janc <sz...@codecoup.pl>
AuthorDate: Mon Sep 7 09:16:28 2020 +0200
Update NRFX to release 2.3.0
---
hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md | 52 +
hw/mcu/nordic/src/ext/nrfx/README.md | 4 +-
.../src/ext/nrfx/drivers/include/nrfx_clock.h | 15 +-
.../src/ext/nrfx/drivers/include/nrfx_nfct.h | 6 +
.../src/ext/nrfx/drivers/include/nrfx_nvmc.h | 44 +
.../src/ext/nrfx/drivers/include/nrfx_spim.h | 1 +
.../src/ext/nrfx/drivers/include/nrfx_uarte.h | 19 +
.../nordic/src/ext/nrfx/drivers/src/nrfx_clock.c | 94 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c | 85 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c | 127 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c | 125 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c | 112 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c | 5 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c | 13 +
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c | 12 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c | 20 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c | 4 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c | 30 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c | 72 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c | 15 +
.../nordic/src/ext/nrfx/drivers/src/nrfx_timer.c | 4 +-
.../src/ext/nrfx/drivers/src/nrfx_twi_twim.c | 5 +
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c | 4 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c | 14 +-
.../nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c | 38 +-
hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c | 419 +-
.../src/ext/nrfx/drivers/src/nrfx_usbd_errata.h | 25 +-
.../nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h | 9 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h | 7 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h | 57 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h | 63 +-
.../src/ext/nrfx/{nrfx.h => hal/nrf_common.h} | 36 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h | 40 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h | 7 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h | 106 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h | 79 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h | 4 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h | 33 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h | 19 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h | 4 +
hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h | 21 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h | 94 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h | 18 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h | 13 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h | 22 +
hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h | 59 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h | 61 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h | 77 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h | 52 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h | 13 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h | 33 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h | 33 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h | 21 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h | 21 +-
hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s | 6 +-
.../nordic/src/ext/nrfx/mdk/arm_startup_nrf52805.s | 6 +-
.../nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s | 2 +-
.../nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s | 2 +-
...m_startup_nrf52811.s => arm_startup_nrf52820.s} | 54 +-
.../nordic/src/ext/nrfx/mdk/arm_startup_nrf52833.s | 2 +-
.../nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s | 6 +-
.../ext/nrfx/mdk/arm_startup_nrf5340_application.s | 6 +-
.../src/ext/nrfx/mdk/arm_startup_nrf5340_network.s | 13 +-
.../nordic/src/ext/nrfx/mdk/arm_startup_nrf9160.s | 6 +-
.../nordic/src/ext/nrfx/mdk/compiler_abstraction.h | 58 +-
hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S | 6 +-
hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S | 10 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S | 9 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S | 6 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S | 6 +-
...c_startup_nrf52811.S => gcc_startup_nrf52820.S} | 41 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S | 6 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S | 10 +-
.../ext/nrfx/mdk/gcc_startup_nrf5340_application.S | 10 +-
.../src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S | 19 +-
.../nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s | 2 +-
.../nordic/src/ext/nrfx/mdk/iar_startup_nrf52805.s | 9 +-
.../nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s | 2 +-
.../nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s | 2 +-
...r_startup_nrf52811.s => iar_startup_nrf52820.s} | 57 +-
.../nordic/src/ext/nrfx/mdk/iar_startup_nrf52833.s | 2 +-
.../nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s | 2 +-
.../ext/nrfx/mdk/iar_startup_nrf5340_application.s | 2 +-
.../src/ext/nrfx/mdk/iar_startup_nrf5340_network.s | 9 +-
.../nordic/src/ext/nrfx/mdk/iar_startup_nrf9160.s | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h | 153 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h | 8 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf51422_peripherals.h | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51422_xxaa.ld} | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51422_xxab.ld} | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51422_xxac.ld} | 4 +-
.../nordic/src/ext/nrfx/mdk/nrf51801_peripherals.h | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51801_xxab.ld} | 4 +-
.../nordic/src/ext/nrfx/mdk/nrf51802_peripherals.h | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51802_xxaa.ld} | 4 +-
.../nordic/src/ext/nrfx/mdk/nrf51822_peripherals.h | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51822_xxaa.ld} | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51822_xxab.ld} | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51822_xxac.ld} | 4 +-
.../nordic/src/ext/nrfx/mdk/nrf51824_peripherals.h | 4 +-
.../{nrf5340_xxaa_network.ld => nrf51824_xxaa.ld} | 4 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_bitfields.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_common.ld | 1 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_deprecated.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_erratas.h | 142 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_peripherals.h | 4 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52810.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52840.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.h | 161 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.svd | 4111 ++---
.../nordic/src/ext/nrfx/mdk/nrf52805_bitfields.h | 1139 +-
.../nordic/src/ext/nrfx/mdk/nrf52805_peripherals.h | 14 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.h | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52810.svd | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52810_bitfields.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52810_name_change.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52810_peripherals.h | 4 +-
.../nordic/src/ext/nrfx/mdk/nrf52810_to_nrf52811.h | 7 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52811.h | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52811.svd | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52811_bitfields.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52811_peripherals.h | 4 +-
.../src/ext/nrfx/mdk/{nrf52811.h => nrf52820.h} | 659 +-
.../ext/nrfx/mdk/{nrf52811.svd => nrf52820.svd} | 17152 ++++++++++---------
.../{nrf52811_bitfields.h => nrf52820_bitfields.h} | 3581 ++--
...f52811_peripherals.h => nrf52820_peripherals.h} | 85 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52820_xxaa.ld | 14 +
.../nordic/src/ext/nrfx/mdk/nrf52832_peripherals.h | 17 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52833.h | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52833.svd | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52833_bitfields.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf52833_peripherals.h | 4 +-
.../mdk/{nrf_erratas.h => nrf52833_to_nrf52820.h} | 20 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52840.h | 30 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52840.svd | 114 +-
.../nordic/src/ext/nrfx/mdk/nrf52840_bitfields.h | 57 +-
.../nordic/src/ext/nrfx/mdk/nrf52840_peripherals.h | 4 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52840_xxaa.ld | 1 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_bitfields.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_common.ld | 1 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_erratas.h | 1943 ++-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_name_change.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_to_nrf52810.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_to_nrf52833.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf52_to_nrf52840.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf5340_application.h | 101 +-
.../src/ext/nrfx/mdk/nrf5340_application.svd | 1051 +-
.../ext/nrfx/mdk/nrf5340_application_bitfields.h | 884 +-
.../ext/nrfx/mdk/nrf5340_application_peripherals.h | 8 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_network.h | 196 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_network.svd | 1991 +--
.../src/ext/nrfx/mdk/nrf5340_network_bitfields.h | 1075 +-
.../src/ext/nrfx/mdk/nrf5340_network_peripherals.h | 10 +-
.../src/ext/nrfx/mdk/nrf5340_xxaa_application.ld | 1 +
.../src/ext/nrfx/mdk/nrf5340_xxaa_network.ld | 3 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf53_erratas.h | 2720 ++-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf9160.h | 13 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf9160.svd | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf9160_bitfields.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf9160_name_change.h | 2 +-
.../nordic/src/ext/nrfx/mdk/nrf9160_peripherals.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf91_erratas.h | 104 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf_common.ld | 1 +
hw/mcu/nordic/src/ext/nrfx/mdk/nrf_erratas.h | 5 +-
hw/mcu/nordic/src/ext/nrfx/mdk/nrf_peripherals.h | 63 +-
.../nordic/src/ext/nrfx/mdk/ses_startup_nrf52805.s | 5 +-
...s_startup_nrf52805.s => ses_startup_nrf52820.s} | 61 +-
.../src/ext/nrfx/mdk/ses_startup_nrf5340_network.s | 7 +-
.../src/ext/nrfx/mdk/ses_startup_nrf_common.s | 9 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf.h | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf51.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf51.h | 71 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52.h | 71 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52805.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52805.h | 71 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52810.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52810.h | 71 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52811.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52811.h | 71 +-
.../mdk/{system_nrf52805.c => system_nrf52820.c} | 39 +-
.../nrfx/mdk/{system_nrf.h => system_nrf52820.h} | 10 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52833.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52833.h | 71 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52840.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf52840.h | 71 +-
.../src/ext/nrfx/mdk/system_nrf5340_application.c | 14 +-
.../src/ext/nrfx/mdk/system_nrf5340_application.h | 71 +-
.../src/ext/nrfx/mdk/system_nrf5340_network.c | 2 +-
.../src/ext/nrfx/mdk/system_nrf5340_network.h | 71 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf9160.c | 2 +-
hw/mcu/nordic/src/ext/nrfx/mdk/system_nrf9160.h | 77 +-
hw/mcu/nordic/src/ext/nrfx/nrfx.h | 1 +
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_coredep.h | 6 +-
hw/mcu/nordic/src/ext/nrfx/soc/nrfx_irqs.h | 4 +
.../{nrfx_irqs_nrf52810.h => nrfx_irqs_nrf52805.h} | 17 +-
.../nordic/src/ext/nrfx/soc/nrfx_irqs_nrf52810.h | 6 +-
.../{nrfx_irqs_nrf52810.h => nrfx_irqs_nrf52820.h} | 66 +-
hw/mcu/nordic/src/ext/nrfx/templates/nrfx_config.h | 4 +
.../src/ext/nrfx/templates/nrfx_config_nrf51.h | 15 +
...fx_config_nrf52810.h => nrfx_config_nrf52805.h} | 251 +-
.../src/ext/nrfx/templates/nrfx_config_nrf52810.h | 15 +
.../src/ext/nrfx/templates/nrfx_config_nrf52811.h | 15 +
...fx_config_nrf52811.h => nrfx_config_nrf52820.h} | 404 +-
.../src/ext/nrfx/templates/nrfx_config_nrf52832.h | 15 +
.../src/ext/nrfx/templates/nrfx_config_nrf52833.h | 15 +
.../src/ext/nrfx/templates/nrfx_config_nrf52840.h | 15 +
.../templates/nrfx_config_nrf5340_application.h | 55 +-
.../nrfx/templates/nrfx_config_nrf5340_network.h | 20 +-
.../src/ext/nrfx/templates/nrfx_config_nrf9160.h | 44 +-
hw/mcu/nordic/src/ext/nrfx/templates/nrfx_glue.h | 9 +
228 files changed, 22995 insertions(+), 19464 deletions(-)
diff --git a/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md b/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
index f1fb6c6..d9134fd 100644
--- a/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
+++ b/hw/mcu/nordic/src/ext/nrfx/CHANGELOG.md
@@ -1,6 +1,58 @@
# Changelog
All notable changes to this project are documented in this file.
+## [2.3.0] - 2020-08-19
+### Added
+- Added support for nRF52805.
+- Implemented workaround for nRF52 Series anomaly 197 in the POWER HAL.
+- Implemented workaround for nRF52 Series anomalies 211 and 223 in the USBD driver.
+- Added support for the nRF53 Series in the QSPI HAL.
+- Added function in the GPIO HAL that returns port index.
+- Introduced a QSPI HAL symbol that indicates the availability of the QSPI mode 1.
+- Introduced shortcut functionality in the CCM HAL.
+- Added function in the TIMER HAL for setting the specified shortcuts.
+- Added optional two-stage start procedure of the LFXO in the CLOCK driver.
+
+### Changed
+- Updated MDK to 8.35.0.
+- Divided network and application core-specific functionalities for nRF5340 in the RESET HAL and the reset reason helper.
+
+### Fixed
+- Corrected assertions in the NVMC driver.
+- Corrected return types in the CCM HAL.
+- Fixed setting of program memory access mode for secure code in the NVMC driver.
+- Removed usage of the NRF_UICR symbol on non-secure targets in address validity checks in the NVMC driver.
+- Fixed an error message in the SPIM driver that prevented successful compilation with logging enabled.
+- Fixed unused parameters in the PPI HAL.
+
+## [2.2.0] - 2020-04-28
+### Added
+- Added support for nRF52820.
+- Added possibility to use the nRF52833 DK in development for nRF52820. LEDs and buttons in this DK use GPIOs that are not present in the actual nRF52820 device, so accesses to these need special handling in the GPIO HAL.
+- Added the nrfx_reset_reason helper layer, to facilitate developing generic code that uses the RESETREAS register.
+- Implemented workarounds for nRF52 Series anomalies 170 and 196 in the I2S driver.
+- Added implicit casting of uint32_t to unsigned long in log messages, to prevent compiler warnings.
+- Added missing secure and non-secure peripheral symbol translations for nRF5340 and nRF9160.
+- Added functions in the NVMC driver for reading and writing halfword data from the OTP region of the UICR.
+
+### Changed
+- Updated MDK to 8.32.1.
+- Improved documentation regarding double-buffered reception in the UARTE driver.
+- Unified policy of pin cleanup procedure during uninitialization of the drivers. Now every driver restores utilized pins to default setting.
+- Removed support for revision Engineering A of nRF52840 in the USBD driver.
+- Changed selected while() loops to NRFX_WAIT_FOR() macro in the SPIM, UARTE and CLOCK drivers to improve robustness.
+
+### Fixed
+- Fixed assertions that check write addresses in the NVMC driver. Now the UICR memory region is handled properly.
+- Fixed a race condition in the CLOCK driver when requested clock was stopped during ramp-up from high priority interrupt.
+- Fixed assertions that check pin numbers in the GPIO HAL and GPIOTE driver. Now noncontiguous groups of available pin numbers are handled properly.
+- Fixed assertion that checks correctness of limit setting in the SAADC driver.
+- Fixed spurious callback invocation when the SPIM driver was reinitialized to blocking mode from non-blocking mode.
+- Fixed missing workaround for I2S STOP anomaly for nRF52833.
+- Fixed handling of NRFX_SPIM_FLAG_HOLD_XFER setting in the blocking mode of the SPIM driver.
+- Fixed void pointer cast in the CLOCK HAL, which could cause memory corruption with specific compiler settings.
+- Fixed definition of the NRF_CLOCK_LFCLK_Synth value, to make it available also in builds for nRF5340.
+
## [2.1.0] - 2020-01-24
### Added
- Added HALs for DCNF, OSCILLATORS, USBREG, and VREQCTRL.
diff --git a/hw/mcu/nordic/src/ext/nrfx/README.md b/hw/mcu/nordic/src/ext/nrfx/README.md
index 8864720..0772a3f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/README.md
+++ b/hw/mcu/nordic/src/ext/nrfx/README.md
@@ -13,8 +13,10 @@ SoCs, as well as startup and initialization files for them.
## Supported SoCs
* nRF51 Series
+* nRF52805
* nRF52810
* nRF52811
+* nRF52820
* nRF52832
* nRF52833
* nRF52840
@@ -27,7 +29,7 @@ SoCs, as well as startup and initialization files for them.
.
├── doc # Project documentation files
├── drivers # nrfx driver files
- │ └── include # nrfx driver headers
+ │ ├── include # nrfx driver headers
│ └── src # nrfx driver sources
├── hal # Hardware Access Layer files
├── helpers # nrfx driver helper files
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
index 08cbee1..75109b1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_clock.h
@@ -106,15 +106,16 @@ void nrfx_clock_stop(nrf_clock_domain_t domain);
*
* XTAL source is assumed for domains with multiple sources.
*
- * @param[in] domain Clock domain.
- * @param[out] clk_src Clock source that is running. Set to NULL if not needed.
- * Ignored for HFCLKAUDIO domain. Typecast it to @ref nrf_clock_lfclk_t for
- * LFCLK and @ref nrf_clock_hfclk_t for HFCLK and HFCLK192M.
+ * @param[in] domain Clock domain.
+ * @param[out] p_clk_src Pointer to a clock source that is running. Set to NULL if not needed.
+ * Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src
+ * must be of either @ref nrf_clock_lfclk_t type for LFCLK
+ * or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M.
*
* @retval true The clock domain is running.
* @retval false The clock domain is not running.
*/
-NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src);
+NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src);
#if NRF_CLOCK_HAS_HFCLK_DIV || NRF_CLOCK_HAS_HFCLK_192M
/**
@@ -318,9 +319,9 @@ NRFX_STATIC_INLINE uint32_t nrfx_clock_ppi_event_addr(nrf_clock_event_t event)
return nrf_clock_event_address_get(NRF_CLOCK, event);
}
-NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * clk_src)
+NRFX_STATIC_INLINE bool nrfx_clock_is_running(nrf_clock_domain_t domain, void * p_clk_src)
{
- return nrf_clock_is_running(NRF_CLOCK, domain, clk_src);
+ return nrf_clock_is_running(NRF_CLOCK, domain, p_clk_src);
}
NRFX_STATIC_INLINE bool nrfx_clock_hfclk_is_running(void)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
index 4d8bea0..c1cfe12 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nfct.h
@@ -164,6 +164,9 @@ typedef struct
* @brief Callback descriptor to pass events from the NFCT driver to the upper layer.
*
* @param[in] p_event Pointer to the event descriptor.
+ *
+ * @note @ref NRFX_NFCT_EVT_FIELD_DETECTED and @ref NRFX_NFCT_EVT_FIELD_LOST are generated only on field state transitions,
+ * i.e. there will be no multiple events of the same type (out of the 2 mentioned) coming in a row.
*/
typedef void (*nrfx_nfct_handler_t)(nrfx_nfct_evt_t const * p_event);
@@ -265,6 +268,9 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param);
/**
* @brief Function for getting default bytes for NFCID1.
*
+ * @note This function cannot be used from the non-secure code because it requires access
+ * to FICR registers.
+ *
* @param[in,out] p_nfcid1_buff In: empty buffer for data;
* Out: buffer with the NFCID1 default data. These values
* can be used to fill the Type 2 Tag Internal Bytes.
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h
index cfea373..e5fb974 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_nvmc.h
@@ -155,6 +155,37 @@ bool nrfx_nvmc_byte_writable_check(uint32_t address, uint8_t value);
void nrfx_nvmc_byte_write(uint32_t address, uint8_t value);
/**
+ * @brief Function for checking whether a halfword is writable at the specified address.
+ *
+ * The NVMC is only able to write '0' to bits in the Flash that are erased (set to '1').
+ * It cannot rewrite a bit back to '1'. This function checks if the value currently
+ * residing at the specified address can be transformed to the desired value
+ * without any '0' to '1' transitions.
+ *
+ * @param address Address to be checked. Must be halfword-aligned.
+ * @param value Value to be checked.
+ *
+ * @retval true Halfword can be written at the specified address.
+ * @retval false Halfword cannot be written at the specified address.
+ * Erase page or change address.
+ */
+bool nrfx_nvmc_halfword_writable_check(uint32_t address, uint16_t value);
+
+/**
+ * @brief Function for writing a 16-bit halfword to flash.
+ *
+ * To determine if the flash write has been completed, use @ref nrfx_nvmc_write_done_check().
+ *
+ * @note Depending on the source of the code being executed,
+ * the CPU may be halted during the operation.
+ * Refer to the Product Specification for more information.
+ *
+ * @param address Address to write to. Must be halfword-aligned.
+ * @param value Value to write.
+ */
+void nrfx_nvmc_halfword_write(uint32_t address, uint16_t value);
+
+/**
* @brief Function for checking whether a word is writable at the specified address.
*
* The NVMC is only able to write '0' to bits in the Flash that are erased (set to '1').
@@ -216,6 +247,19 @@ void nrfx_nvmc_bytes_write(uint32_t address, void const * src, uint32_t num_byte
void nrfx_nvmc_words_write(uint32_t address, void const * src, uint32_t num_words);
/**
+ * @brief Function for reading a 16-bit aligned halfword from the OTP (UICR)
+ *
+ * OTP is a region of the UICR present in some chips. This function must be used
+ * to read halfword data from this region since unaligned accesses are not
+ * available on the OTP flash area.
+ *
+ * @param address Address to read from. Must be halfword-aligned.
+ *
+ * @retval The contents at @p address.
+ */
+uint16_t nrfx_nvmc_otp_halfword_read(uint32_t address);
+
+/**
* @brief Function for getting the total flash size in bytes.
*
* @return Flash total size in bytes.
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
index 339ab4c..ba2cdbe 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_spim.h
@@ -285,6 +285,7 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance);
* - @ref NRFX_SPIM_FLAG_HOLD_XFER - Driver is not starting the transfer. Use this
* flag if the transfer is triggered externally by PPI. Use
* @ref nrfx_spim_start_task_get to get the address of the start task.
+ * Chip select must be configured to @ref NRFX_SPIM_PIN_NOT_USED and managed outside the driver.
* - @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER - No user event handler after transfer
* completion. This also means no interrupt at the end of the transfer.
* If @ref NRFX_SPIM_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
index bfba1f8..6346695 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/include/nrfx_uarte.h
@@ -296,6 +296,15 @@ void nrfx_uarte_tx_abort(nrfx_uarte_t const * p_instance);
* to be placed in the Data RAM region. If this condition is not met,
* this function fails with the error code NRFX_ERROR_INVALID_ADDR.
*
+ * @warning When the double-buffering feature is used and the UARTE interrupt
+ * is processed with a delay (for example, due to a higher priority interrupt)
+ * long enough for both buffers to get filled completely,
+ * the event handler will be invoked only once, to notify that
+ * the first buffer has been filled. This is because from hardware perspective it
+ * is impossible to deduce in such case if the second buffer was also filled completely or not.
+ * To prevent this from happening, keep the UARTE interrupt latency low
+ * or use large enough reception buffers.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
* @param[in] p_data Pointer to data.
* @param[in] length Number of bytes to receive. Maximum possible length is
@@ -334,6 +343,16 @@ bool nrfx_uarte_rx_ready(nrfx_uarte_t const * p_instance);
* It will contain number of bytes received until the abort was called. The event
* handler will be called from the UARTE interrupt context.
*
+ * @warning When the double-buffering feature is used and the UARTE interrupt
+ * is processed with a delay (for example, due to a higher priority
+ * interrupt) long enough for the first buffer to be filled completely,
+ * the event handler will be supplied with the pointer to the first
+ * buffer and the number of bytes received in the second buffer.
+ * This is because from hardware perspective it is impossible to deduce
+ * the reception of which buffer has been aborted.
+ * To prevent this from happening, keep the UARTE interrupt latency low
+ * or use large enough reception buffers.
+ *
* @param[in] p_instance Pointer to the driver instance structure.
*/
void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance);
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
index 593201f..2355c18 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_clock.c
@@ -43,11 +43,17 @@
extern bool nrfx_power_irq_enabled;
#endif
+#if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__)
+ #define LF_SRC_RC CLOCK_LFCLKSRC_SRC_RC
+#else
+ #define LF_SRC_RC CLOCK_LFCLKSRC_SRC_LFRC
+#endif
+
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
#if (NRF_CLOCK_HAS_CALIBRATION == 0)
#error "Calibration is not available in the SoC that is used."
#endif
- #if (NRFX_CLOCK_CONFIG_LF_SRC != CLOCK_LFCLKSRC_SRC_RC)
+ #if (NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_RC)
#error "Calibration can be performed only for the RC Oscillator."
#endif
#endif
@@ -79,6 +85,30 @@ extern bool nrfx_power_irq_enabled;
#define USE_WORKAROUND_FOR_ANOMALY_201 1
#endif
+#if defined(CLOCK_LFCLKSRC_SRC_Xtal)
+ #define LF_SRC_LFXO CLOCK_LFCLKSRC_SRC_Xtal
+#else
+ #define LF_SRC_LFXO CLOCK_LFCLKSRC_SRC_LFXO
+#endif
+
+#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES)
+ #define LF_SRC_XTAL_LOW (CLOCK_LFCLKSRC_SRC_Xtal | \
+ (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos))
+ #define LF_SRC_XTAL_FULL (CLOCK_LFCLKSRC_SRC_Xtal | \
+ (CLOCK_LFCLKSRC_BYPASS_Enabled << CLOCK_LFCLKSRC_BYPASS_Pos) | \
+ (CLOCK_LFCLKSRC_EXTERNAL_Enabled << CLOCK_LFCLKSRC_EXTERNAL_Pos))
+#else
+ #define LF_SRC_XTAL_LOW LF_SRC_LFXO
+ #define LF_SRC_XTAL_FULL LF_SRC_LFXO
+#endif
+
+#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED) && \
+ NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_LFXO && \
+ NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_XTAL_LOW && \
+ NRFX_CLOCK_CONFIG_LF_SRC != LF_SRC_XTAL_FULL
+ #error "Two-stage LFXO start procedure enabled but LFCLK source is not set to LFXO!"
+#endif
+
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
typedef enum
{
@@ -173,7 +203,9 @@ void nrfx_clock_enable(void)
{
NRFX_ASSERT(m_clock_cb.module_initialized);
nrfx_power_clock_irq_init();
+#if !NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC);
+#endif
#if NRF_CLOCK_HAS_HFCLKSRC
nrf_clock_hf_src_set(NRF_CLOCK, NRF_CLOCK_HFCLK_HIGH_ACCURACY);
#endif
@@ -233,6 +265,25 @@ void nrfx_clock_start(nrf_clock_domain_t domain)
switch (domain)
{
case NRF_CLOCK_DOMAIN_LFCLK:
+#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
+ {
+ nrf_clock_lfclk_t lfclksrc;
+ if (nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc) &&
+ lfclksrc == NRFX_CLOCK_CONFIG_LF_SRC)
+ {
+ // If the two-stage LFXO procedure has finished already
+ // use the configured LF clock source.
+ nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC);
+ }
+ else
+ {
+ // If the two-stage LFXO procedure hasn't started yet
+ // or the RC stage is in progress,
+ // use the RC oscillator as LF clock source.
+ nrf_clock_lf_src_set(NRF_CLOCK, NRF_CLOCK_LFCLK_RC);
+ }
+ }
+#endif // NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED);
nrf_clock_int_enable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_132)
@@ -271,18 +322,26 @@ void nrfx_clock_stop(nrf_clock_domain_t domain)
switch (domain)
{
case NRF_CLOCK_DOMAIN_LFCLK:
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED);
nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTOP);
break;
case NRF_CLOCK_DOMAIN_HFCLK:
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF_STARTED_MASK);
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKSTARTED);
nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
break;
#if NRF_CLOCK_HAS_HFCLK192M
case NRF_CLOCK_DOMAIN_HFCLK192M:
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HF192M_STARTED_MASK);
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLK192MSTARTED);
nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLK192MSTOP);
break;
#endif
#if NRF_CLOCK_HAS_HFCLKAUDIO
case NRF_CLOCK_DOMAIN_HFCLKAUDIO:
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_HFAUDIO_STARTED_MASK);
+ nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_HFCLKAUDIOSTARTED);
nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKAUDIOSTOP);
break;
#endif
@@ -290,17 +349,24 @@ void nrfx_clock_stop(nrf_clock_domain_t domain)
NRFX_ASSERT(0);
return;
}
+
+ bool stopped;
if (domain == NRF_CLOCK_DOMAIN_HFCLK)
{
nrf_clock_hfclk_t clk_src = NRF_CLOCK_HFCLK_HIGH_ACCURACY;
- while (nrfx_clock_is_running(domain, &clk_src) && (clk_src == NRF_CLOCK_HFCLK_HIGH_ACCURACY))
- {}
+ NRFX_WAIT_FOR((!nrfx_clock_is_running(domain, &clk_src) ||
+ (clk_src != NRF_CLOCK_HFCLK_HIGH_ACCURACY)), 10000, 1, stopped);
}
else
{
- while (nrfx_clock_is_running(domain, NULL))
- {}
+ NRFX_WAIT_FOR(!nrfx_clock_is_running(domain, NULL), 10000, 1, stopped);
+ }
+
+ if (!stopped)
+ {
+ NRFX_LOG_ERROR("Failed to stop clock domain: %d.", domain);
}
+
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_201)
if (domain == NRF_CLOCK_DOMAIN_HFCLK)
{
@@ -465,9 +531,23 @@ void nrfx_clock_irq_handler(void)
{
nrf_clock_event_clear(NRF_CLOCK, NRF_CLOCK_EVENT_LFCLKSTARTED);
NRFX_LOG_DEBUG("Event: NRF_CLOCK_EVENT_LFCLKSTARTED");
- nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
- m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
+#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LFXO_TWO_STAGE_ENABLED)
+ nrf_clock_lfclk_t lfclksrc;
+ (void)nrf_clock_is_running(NRF_CLOCK, NRF_CLOCK_DOMAIN_LFCLK, &lfclksrc);
+ if (lfclksrc == NRF_CLOCK_LFCLK_RC)
+ {
+ // After the LFRC oscillator start switch to external source.
+ nrf_clock_lf_src_set(NRF_CLOCK, (nrf_clock_lfclk_t)NRFX_CLOCK_CONFIG_LF_SRC);
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_LFCLKSTART);
+ }
+ else
+#endif
+ {
+ // After the LF clock external source start invoke user callback.
+ nrf_clock_int_disable(NRF_CLOCK, NRF_CLOCK_INT_LF_STARTED_MASK);
+ m_clock_cb.event_handler(NRFX_CLOCK_EVT_LFCLK_STARTED);
+ }
}
#if NRFX_CHECK(NRFX_CLOCK_CONFIG_LF_CAL_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
index 73f8e44..c14ff09 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_gpiote.c
@@ -39,6 +39,13 @@
#define NRFX_LOG_MODULE GPIOTE
#include <nrfx_log.h>
+#if (GPIO_COUNT == 1)
+#define MAX_PIN_NUMBER 32
+#elif (GPIO_COUNT == 2)
+#define MAX_PIN_NUMBER (32 + P1_PIN_NUM)
+#else
+#error "Not supported."
+#endif
#define FORBIDDEN_HANDLER_ADDRESS ((nrfx_gpiote_evt_handler_t)UINT32_MAX)
#define PIN_NOT_USED (-1)
@@ -48,15 +55,15 @@
#define POLARITY_FIELD_MASK (0xC0)
/* Check if every pin can be encoded on provided number of bits. */
-NRFX_STATIC_ASSERT(NUMBER_OF_PINS <= (1 << POLARITY_FIELD_POS));
+NRFX_STATIC_ASSERT(MAX_PIN_NUMBER <= (1 << POLARITY_FIELD_POS));
/*lint -save -e571*/ /* Suppress "Warning 571: Suspicious cast" */
typedef struct
{
nrfx_gpiote_evt_handler_t handlers[GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS];
- int8_t pin_assignments[NUMBER_OF_PINS];
+ int8_t pin_assignments[MAX_PIN_NUMBER];
int8_t port_handlers_pins[NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS];
- uint8_t configured_pins[((NUMBER_OF_PINS)+7) / 8];
+ uint8_t configured_pins[((MAX_PIN_NUMBER)+7) / 8];
nrfx_drv_state_t state;
} gpiote_control_block_t;
@@ -207,9 +214,12 @@ nrfx_err_t nrfx_gpiote_init(uint8_t interrupt_priority)
uint8_t i;
- for (i = 0; i < NUMBER_OF_PINS; i++)
+ for (i = 0; i < MAX_PIN_NUMBER; i++)
{
- pin_in_use_clear(i);
+ if (nrf_gpio_pin_present_check(i))
+ {
+ pin_in_use_clear(i);
+ }
}
for (i = 0; i < (GPIOTE_CH_NUM + NRFX_GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++)
@@ -243,18 +253,21 @@ void nrfx_gpiote_uninit(void)
uint32_t i;
- for (i = 0; i < NUMBER_OF_PINS; i++)
- {
- if (pin_in_use_as_non_task_out(i))
+ for (i = 0; i < MAX_PIN_NUMBER; i++)
+ {
+ if (nrf_gpio_pin_present_check(i))
{
- nrfx_gpiote_out_uninit(i);
- }
- else if ( pin_in_use_by_gpiote(i))
- {
- /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on
- * so it can be called on all pins used by GPIOTE.
- */
- nrfx_gpiote_in_uninit(i);
+ if (pin_in_use_as_non_task_out(i))
+ {
+ nrfx_gpiote_out_uninit(i);
+ }
+ else if (pin_in_use_by_gpiote(i))
+ {
+ /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on
+ * so it can be called on all pins used by GPIOTE.
+ */
+ nrfx_gpiote_in_uninit(i);
+ }
}
}
m_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
@@ -265,7 +278,7 @@ void nrfx_gpiote_uninit(void)
nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin,
nrfx_gpiote_out_config_t const * p_config)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED);
NRFX_ASSERT(p_config);
@@ -322,7 +335,7 @@ nrfx_err_t nrfx_gpiote_out_init(nrfx_gpiote_pin_t pin,
void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
if (pin_in_use_by_te(pin))
@@ -342,7 +355,7 @@ void nrfx_gpiote_out_uninit(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(!pin_in_use_by_te(pin));
@@ -352,7 +365,7 @@ void nrfx_gpiote_out_set(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(!pin_in_use_by_te(pin));
@@ -362,7 +375,7 @@ void nrfx_gpiote_out_clear(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(!pin_in_use_by_te(pin));
@@ -372,7 +385,7 @@ void nrfx_gpiote_out_toggle(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
@@ -382,7 +395,7 @@ void nrfx_gpiote_out_task_enable(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
@@ -392,7 +405,7 @@ void nrfx_gpiote_out_task_disable(nrfx_gpiote_pin_t pin)
nrf_gpiote_task_t nrfx_gpiote_out_task_get(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
return nrf_gpiote_out_task_get((uint8_t)channel_port_get(pin));
@@ -409,7 +422,7 @@ uint32_t nrfx_gpiote_out_task_addr_get(nrfx_gpiote_pin_t pin)
#if defined(GPIOTE_FEATURE_SET_PRESENT)
nrf_gpiote_task_t nrfx_gpiote_set_task_get(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
return nrf_gpiote_set_task_get((uint8_t)channel_port_get(pin));
@@ -427,7 +440,7 @@ uint32_t nrfx_gpiote_set_task_addr_get(nrfx_gpiote_pin_t pin)
#if defined(GPIOTE_FEATURE_CLR_PRESENT)
nrf_gpiote_task_t nrfx_gpiote_clr_task_get(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
return nrf_gpiote_clr_task_get((uint8_t)channel_port_get(pin));
@@ -444,7 +457,7 @@ uint32_t nrfx_gpiote_clr_task_addr_get(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
@@ -456,7 +469,7 @@ void nrfx_gpiote_out_task_force(nrfx_gpiote_pin_t pin, uint8_t state)
void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
@@ -468,7 +481,7 @@ void nrfx_gpiote_out_task_trigger(nrfx_gpiote_pin_t pin)
#if defined(GPIOTE_FEATURE_SET_PRESENT)
void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
@@ -482,7 +495,7 @@ void nrfx_gpiote_set_task_trigger(nrfx_gpiote_pin_t pin)
#if defined(GPIOTE_FEATURE_CLR_PRESENT)
void nrfx_gpiote_clr_task_trigger(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use(pin));
NRFX_ASSERT(pin_in_use_by_te(pin));
@@ -497,7 +510,7 @@ nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin,
nrfx_gpiote_in_config_t const * p_config,
nrfx_gpiote_evt_handler_t evt_handler)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(m_cb.state == NRFX_DRV_STATE_INITIALIZED);
NRFX_ASSERT(p_config);
@@ -548,7 +561,7 @@ nrfx_err_t nrfx_gpiote_in_init(nrfx_gpiote_pin_t pin,
void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_gpiote(pin));
if (pin_in_use_by_port(pin))
{
@@ -591,7 +604,7 @@ void nrfx_gpiote_in_event_enable(nrfx_gpiote_pin_t pin, bool int_enable)
void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_gpiote(pin));
if (pin_in_use_by_port(pin))
{
@@ -608,7 +621,7 @@ void nrfx_gpiote_in_event_disable(nrfx_gpiote_pin_t pin)
void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_gpiote(pin));
nrfx_gpiote_in_event_disable(pin);
if (pin_in_use_by_te(pin))
@@ -627,14 +640,14 @@ void nrfx_gpiote_in_uninit(nrfx_gpiote_pin_t pin)
bool nrfx_gpiote_in_is_set(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
return nrf_gpio_pin_read(pin) ? true : false;
}
nrf_gpiote_event_t nrfx_gpiote_in_event_get(nrfx_gpiote_pin_t pin)
{
- NRFX_ASSERT(pin < NUMBER_OF_PINS);
+ NRFX_ASSERT(nrf_gpio_pin_present_check(pin));
NRFX_ASSERT(pin_in_use_by_port(pin) || pin_in_use_by_te(pin));
if (pin_in_use_by_te(pin))
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
index 6072083..b58ebb5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_i2s.c
@@ -45,14 +45,26 @@
(event == NRF_I2S_EVENT_STOPPED ? "NRF_I2S_EVENT_STOPPED" : \
"UNKNOWN EVENT")))
-#if !defined(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY) && \
- (defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || defined(NRF52840_XXAA) || \
- defined(NRF9160_XXAA))
-// Enable workaround for nRF52832 and nRF52840 anomaly 194 / nrf9160 anomaly 1
+#if !defined(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY) && \
+ (defined(NRF52_SERIES) || defined(NRF9160_XXAA))
+// Enable workaround for nRF52 Series anomaly 194 / nRF9160 anomaly 1
// (STOP task does not switch off all resources).
#define USE_WORKAROUND_FOR_I2S_STOP_ANOMALY 1
#endif
+#if !defined(USE_WORKAROUND_FOR_ANOMALY_170) && defined(NRF52_SERIES)
+// Enable workaround for nRF52 Series anomaly 170
+// (when reading the value of PSEL registers, the CONNECT field might not
+// return the same value that has been written to it).
+#define USE_WORKAROUND_FOR_ANOMALY_170 1
+#endif
+
+#if !defined(USE_WORKAROUND_FOR_ANOMALY_196) && defined(NRF52_SERIES)
+// Enable workaround for nRF52 Series anomaly 196
+// (PSEL acquires GPIO regardless of ENABLE).
+#define USE_WORKAROUND_FOR_ANOMALY_196 1
+#endif
+
// Control block - driver instance local data.
typedef struct
{
@@ -126,7 +138,7 @@ static void configure_pins(nrfx_i2s_config_t const * p_config)
sdin_pin = NRF_I2S_PIN_NOT_CONNECTED;
}
- nrf_i2s_pins_set(NRF_I2S,
+ nrf_i2s_pins_set(NRF_I2S0,
p_config->sck_pin,
p_config->lrck_pin,
mck_pin,
@@ -134,6 +146,43 @@ static void configure_pins(nrfx_i2s_config_t const * p_config)
sdin_pin);
}
+static void deconfigure_pins(void)
+{
+ uint32_t sck_pin = nrf_i2s_sck_pin_get(NRF_I2S0);
+ uint32_t lrck_pin = nrf_i2s_lrck_pin_get(NRF_I2S0);
+ uint32_t mck_pin = nrf_i2s_mck_pin_get(NRF_I2S0);
+ uint32_t sdout_pin = nrf_i2s_sdout_pin_get(NRF_I2S0);
+ uint32_t sdin_pin = nrf_i2s_sdin_pin_get(NRF_I2S0);
+
+#if USE_WORKAROUND_FOR_ANOMALY_170
+ // Create bitmask for extracting pin number from PSEL register.
+ uint32_t pin_mask = I2S_PSEL_SCK_PIN_Msk;
+#if defined(I2S_PSEL_SCK_PORT_Msk)
+ // If device supports more than one GPIO port, take port number into account as well.
+ pin_mask |= I2S_PSEL_SCK_PORT_Msk;
+#endif
+#else
+ uint32_t pin_mask = 0xFFFFFFFF;
+#endif // USE_WORKAROUND_FOR_ANOMALY_170
+
+ nrf_gpio_cfg_default(sck_pin & pin_mask);
+ nrf_gpio_cfg_default(lrck_pin & pin_mask);
+
+ if (mck_pin != NRF_I2S_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(mck_pin & pin_mask);
+ }
+
+ if (sdout_pin != NRF_I2S_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(sdout_pin & pin_mask);
+ }
+
+ if (sdin_pin != NRF_I2S_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(sdin_pin & pin_mask);
+ }
+}
nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
nrfx_i2s_data_handler_t handler)
@@ -152,7 +201,7 @@ nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
return err_code;
}
- if (!nrf_i2s_configure(NRF_I2S,
+ if (!nrf_i2s_configure(NRF_I2S0,
p_config->mode,
p_config->format,
p_config->alignment,
@@ -169,14 +218,14 @@ nrfx_err_t nrfx_i2s_init(nrfx_i2s_config_t const * p_config,
}
#if NRF_I2S_HAS_CLKCONFIG
- nrf_i2s_clk_configure(NRF_I2S, p_config->clksrc, p_config->enable_bypass);
+ nrf_i2s_clk_configure(NRF_I2S0, p_config->clksrc, p_config->enable_bypass);
#endif
configure_pins(p_config);
m_cb.handler = handler;
- NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_I2S), p_config->irq_priority);
- NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_I2S));
+ NRFX_IRQ_PRIORITY_SET(nrfx_get_irq_number(NRF_I2S0), p_config->irq_priority);
+ NRFX_IRQ_ENABLE(nrfx_get_irq_number(NRF_I2S0));
m_cb.state = NRFX_DRV_STATE_INITIALIZED;
@@ -191,14 +240,22 @@ void nrfx_i2s_uninit(void)
nrfx_i2s_stop();
- NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_I2S));
+ NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_I2S0));
+
+ nrf_i2s_disable(NRF_I2S0);
- nrf_i2s_pins_set(NRF_I2S,
+ deconfigure_pins();
+
+#if USE_WORKAROUND_FOR_ANOMALY_196
+ // Disabling I2S is insufficient to release pins acquired by the peripheral.
+ // Explicit disconnect is needed.
+ nrf_i2s_pins_set(NRF_I2S0,
NRF_I2S_PIN_NOT_CONNECTED,
NRF_I2S_PIN_NOT_CONNECTED,
NRF_I2S_PIN_NOT_CONNECTED,
NRF_I2S_PIN_NOT_CONNECTED,
NRF_I2S_PIN_NOT_CONNECTED);
+#endif
m_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
NRFX_LOG_INFO("Uninitialized.");
@@ -259,22 +316,22 @@ nrfx_err_t nrfx_i2s_start(nrfx_i2s_buffers_t const * p_initial_buffers,
m_cb.current_buffers.p_rx_buffer = NULL;
m_cb.current_buffers.p_tx_buffer = NULL;
- nrf_i2s_transfer_set(NRF_I2S,
+ nrf_i2s_transfer_set(NRF_I2S0,
m_cb.buffer_size,
m_cb.next_buffers.p_rx_buffer,
m_cb.next_buffers.p_tx_buffer);
- nrf_i2s_enable(NRF_I2S);
+ nrf_i2s_enable(NRF_I2S0);
m_cb.state = NRFX_DRV_STATE_POWERED_ON;
- nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD);
- nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD);
- nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_STOPPED);
- nrf_i2s_int_enable(NRF_I2S, (m_cb.use_rx ? NRF_I2S_INT_RXPTRUPD_MASK : 0) |
- (m_cb.use_tx ? NRF_I2S_INT_TXPTRUPD_MASK : 0) |
- NRF_I2S_INT_STOPPED_MASK);
- nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_START);
+ nrf_i2s_event_clear(NRF_I2S0, NRF_I2S_EVENT_RXPTRUPD);
+ nrf_i2s_event_clear(NRF_I2S0, NRF_I2S_EVENT_TXPTRUPD);
+ nrf_i2s_event_clear(NRF_I2S0, NRF_I2S_EVENT_STOPPED);
+ nrf_i2s_int_enable(NRF_I2S0, (m_cb.use_rx ? NRF_I2S_INT_RXPTRUPD_MASK : 0) |
+ (m_cb.use_tx ? NRF_I2S_INT_TXPTRUPD_MASK : 0) |
+ NRF_I2S_INT_STOPPED_MASK);
+ nrf_i2s_task_trigger(NRF_I2S0, NRF_I2S_TASK_START);
NRFX_LOG_INFO("Started.");
return NRFX_SUCCESS;
@@ -319,12 +376,12 @@ nrfx_err_t nrfx_i2s_next_buffers_set(nrfx_i2s_buffers_t const * p_buffers)
if (m_cb.use_tx)
{
NRFX_ASSERT(p_buffers->p_tx_buffer != NULL);
- nrf_i2s_tx_buffer_set(NRF_I2S, p_buffers->p_tx_buffer);
+ nrf_i2s_tx_buffer_set(NRF_I2S0, p_buffers->p_tx_buffer);
}
if (m_cb.use_rx)
{
NRFX_ASSERT(p_buffers->p_rx_buffer != NULL);
- nrf_i2s_rx_buffer_set(NRF_I2S, p_buffers->p_rx_buffer);
+ nrf_i2s_rx_buffer_set(NRF_I2S0, p_buffers->p_rx_buffer);
}
m_cb.next_buffers = *p_buffers;
@@ -342,31 +399,31 @@ void nrfx_i2s_stop(void)
// First disable interrupts, then trigger the STOP task, so no spurious
// RXPTRUPD and TXPTRUPD events (see nRF52 anomaly 55) are processed.
- nrf_i2s_int_disable(NRF_I2S, NRF_I2S_INT_RXPTRUPD_MASK |
- NRF_I2S_INT_TXPTRUPD_MASK);
- nrf_i2s_task_trigger(NRF_I2S, NRF_I2S_TASK_STOP);
+ nrf_i2s_int_disable(NRF_I2S0, NRF_I2S_INT_RXPTRUPD_MASK |
+ NRF_I2S_INT_TXPTRUPD_MASK);
+ nrf_i2s_task_trigger(NRF_I2S0, NRF_I2S_TASK_STOP);
#if NRFX_CHECK(USE_WORKAROUND_FOR_I2S_STOP_ANOMALY)
- *((volatile uint32_t *)(((uint32_t)NRF_I2S) + 0x38)) = 1;
- *((volatile uint32_t *)(((uint32_t)NRF_I2S) + 0x3C)) = 1;
+ *((volatile uint32_t *)(((uint32_t)NRF_I2S0) + 0x38)) = 1;
+ *((volatile uint32_t *)(((uint32_t)NRF_I2S0) + 0x3C)) = 1;
#endif
}
void nrfx_i2s_irq_handler(void)
{
- if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD))
+ if (nrf_i2s_event_check(NRF_I2S0, NRF_I2S_EVENT_TXPTRUPD))
{
- nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_TXPTRUPD);
+ nrf_i2s_event_clear(NRF_I2S0, NRF_I2S_EVENT_TXPTRUPD);
m_cb.tx_ready = true;
if (m_cb.use_tx && m_cb.buffers_needed)
{
m_cb.buffers_reused = true;
}
}
- if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD))
+ if (nrf_i2s_event_check(NRF_I2S0, NRF_I2S_EVENT_RXPTRUPD))
{
- nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_RXPTRUPD);
+ nrf_i2s_event_clear(NRF_I2S0, NRF_I2S_EVENT_RXPTRUPD);
m_cb.rx_ready = true;
if (m_cb.use_rx && m_cb.buffers_needed)
{
@@ -374,11 +431,11 @@ void nrfx_i2s_irq_handler(void)
}
}
- if (nrf_i2s_event_check(NRF_I2S, NRF_I2S_EVENT_STOPPED))
+ if (nrf_i2s_event_check(NRF_I2S0, NRF_I2S_EVENT_STOPPED))
{
- nrf_i2s_event_clear(NRF_I2S, NRF_I2S_EVENT_STOPPED);
- nrf_i2s_int_disable(NRF_I2S, NRF_I2S_INT_STOPPED_MASK);
- nrf_i2s_disable(NRF_I2S);
+ nrf_i2s_event_clear(NRF_I2S0, NRF_I2S_EVENT_STOPPED);
+ nrf_i2s_int_disable(NRF_I2S0, NRF_I2S_INT_STOPPED_MASK);
+ nrf_i2s_disable(NRF_I2S0);
// When stopped, release all buffers, including these scheduled for
// the next part of the transfer, and signal that the transfer has
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
index 952ba64..75e0148 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nfct.c
@@ -63,7 +63,7 @@ typedef struct
bool fieldevents_filter_active; /**< Flag that indicates that the field events are ignored. */
bool is_hfclk_on; /**< HFCLK has started - one of the NFC activation conditions. */
bool is_delayed; /**< Required time delay has passed - one of the NFC activation conditions. */
-#else
+#elif NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
uint32_t field_state_cnt; /**< Counter of the FIELDLOST events. */
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
} nrfx_nfct_timer_workaround_t;
@@ -71,7 +71,7 @@ typedef struct
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
#define NRFX_NFCT_ACTIVATE_DELAY 1000 /**< Minimal delay in us between NFC field detection and activation of NFCT. */
#define NRFX_NFCT_TIMER_PERIOD NRFX_NFCT_ACTIVATE_DELAY
-#else
+#elif NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
#define NRFX_NFCT_FIELDLOST_THR 7
#define NRFX_NFCT_FIELD_TIMER_PERIOD 100 /**< Field polling period in us. */
#define NRFX_NFCT_TIMER_PERIOD NRFX_NFCT_FIELD_TIMER_PERIOD
@@ -83,7 +83,6 @@ static nrfx_nfct_timer_workaround_t m_timer_workaround =
};
#endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
-#define NRFX_NFCT_FWT_MAX_DIFF 1u /**< The maximal difference between the requested FWT and HW-limited FWT settings.*/
#define NFCT_FRAMEDELAYMAX_DEFAULT (0x00001000UL) /**< Default value of the FRAMEDELAYMAX. */
/* Mask of all possible interrupts that are relevant for data reception. */
@@ -153,11 +152,11 @@ static void nrfx_nfct_hw_init_setup(void)
// Use Window Grid frame delay mode.
nrf_nfct_frame_delay_mode_set(NRF_NFCT, NRF_NFCT_FRAME_DELAY_MODE_WINDOWGRID);
- /* Begin: Bugfix for FTPAN-25 (IC-9929) */
+ /* Begin: Workaround for anomaly 25 */
/* Workaround for wrong SENSRES values require using SDD00001, but here SDD00100 is used
because it is required to operate with Windows Phone */
nrf_nfct_sensres_bit_frame_sdd_set(NRF_NFCT, NRF_NFCT_SENSRES_BIT_FRAME_SDD_00100);
- /* End: Bugfix for FTPAN-25 (IC-9929) */
+ /* End: Workaround for anomaly 25 */
}
static void nrfx_nfct_frame_delay_max_set(bool default_delay)
@@ -194,7 +193,9 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
NRFX_NFC_FIELD_STATE_OFF;
}
- /* Field event service */
+ /* Field event service. Only take action on field transition -
+ * based on the value of m_nfct_cb.field_on
+ */
switch (field_state)
{
case NRFX_NFC_FIELD_STATE_ON:
@@ -202,14 +203,12 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
{
#if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
- /* Begin: Bugfix for FTPAN-190 */
m_timer_workaround.is_hfclk_on = false;
m_timer_workaround.is_delayed = false;
m_timer_workaround.fieldevents_filter_active = true;
nrfx_timer_clear(&m_timer_workaround.timer);
nrfx_timer_enable(&m_timer_workaround.timer);
- /* END: Bugfix for FTPAN-190 */
#elif NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
nrfx_timer_clear(&m_timer_workaround.timer);
nrfx_timer_enable(&m_timer_workaround.timer);
@@ -224,14 +223,19 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
break;
case NRFX_NFC_FIELD_STATE_OFF:
- nrfx_nfct_state_force(NRFX_NFCT_STATE_SENSING);
- nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
- m_nfct_cb.field_on = false;
- nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_LOST;
+ if (m_nfct_cb.field_on)
+ {
+ nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_SENSE);
+ nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_RX_INT_MASK | NRFX_NFCT_TX_INT_MASK);
+ m_nfct_cb.field_on = false;
+ nfct_evt.evt_id = NRFX_NFCT_EVT_FIELD_LOST;
- nrfx_nfct_frame_delay_max_set(true);
+ /* Begin: Workaround for anomaly 218 */
+ nrfx_nfct_frame_delay_max_set(true);
+ /* End: Workaround for anomaly 218 */
- NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+ }
break;
default:
@@ -241,7 +245,6 @@ static void nrfx_nfct_field_event_handler(volatile nrfx_nfct_field_state_t field
}
#if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
-
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
static void nrfx_nfct_activate_check(void)
{
@@ -270,6 +273,7 @@ static void nrfx_nfct_activate_check(void)
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
#if NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
+/* Begin: Workaround for anomaly 116 */
static inline void nrfx_nfct_reset(void)
{
uint32_t fdm;
@@ -305,6 +309,7 @@ static inline void nrfx_nfct_reset(void)
NRFX_LOG_INFO("Reinitialize");
}
+/* End: Workaround for anomaly 116 */
static void nrfx_nfct_field_poll(void)
{
@@ -322,10 +327,10 @@ static void nrfx_nfct_field_poll(void)
nrfx_nfct_frame_delay_max_set(true);
- /* Begin: Bugfix for FTPAN-116 */
- // resume the NFCT to initialized state
+ /* Begin: Workaround for anomaly 116 */
+ /* resume the NFCT to initialized state */
nrfx_nfct_reset();
- /* End: Bugfix for FTPAN-116 */
+ /* End: Workaround for anomaly 116 */
NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
}
@@ -350,7 +355,7 @@ static void nrfx_nfct_field_timer_handler(nrf_timer_event_t event_type, void * p
nrfx_timer_disable(&m_timer_workaround.timer);
nrfx_nfct_activate_check();
-#else
+#elif NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
nrfx_nfct_field_poll();
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
}
@@ -382,8 +387,7 @@ static inline nrfx_err_t nrfx_nfct_field_timer_config(void)
true);
return err_code;
}
-
-#endif // NFCT_WORKAROUND_USES_TIMER
+#endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
static inline
nrf_nfct_sensres_nfcid1_size_t nrf_nfct_nfcid1_size_to_sensres_size(uint8_t nfcid1_size)
@@ -430,19 +434,7 @@ nrfx_err_t nrfx_nfct_init(nrfx_nfct_config_t const * p_config)
#if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
/* Initialize Timer module as the workaround for NFCT HW issues. */
err_code = nrfx_nfct_field_timer_config();
-#endif // NFCT_WORKAROUND_USES_TIMER
-
- if (err_code == NRFX_SUCCESS)
- {
- uint8_t default_nfcid1[NRFX_NFCT_NFCID1_DEFAULT_LEN];
- err_code = nrfx_nfct_nfcid1_default_bytes_get(default_nfcid1, sizeof(default_nfcid1));
- NRFX_ASSERT(err_code == NRFX_SUCCESS);
- nrf_nfct_nfcid1_set(NRF_NFCT, default_nfcid1, NRF_NFCT_SENSRES_NFCID1_SIZE_DEFAULT);
- }
- else
- {
- return err_code;
- }
+#endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
m_nfct_cb.state = NRFX_DRV_STATE_INITIALIZED;
m_nfct_cb.frame_delay_max = NFCT_FRAMEDELAYMAX_DEFAULT;
@@ -461,7 +453,7 @@ void nrfx_nfct_uninit(void)
#if NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
/* De-initialize Timer module as the workaround for NFCT HW issues. */
nrfx_timer_uninit(&m_timer_workaround.timer);
-#endif // NFCT_WORKAROUND_USES_TIMER
+#endif // NRFX_CHECK(NFCT_WORKAROUND_USES_TIMER)
m_nfct_cb.state = NRFX_DRV_STATE_UNINITIALIZED;
}
@@ -474,9 +466,9 @@ void nrfx_nfct_enable(void)
nrf_nfct_int_enable(NRF_NFCT, NRF_NFCT_INT_FIELDDETECTED_MASK |
NRF_NFCT_INT_ERROR_MASK |
NRF_NFCT_INT_SELECTED_MASK);
-#if !defined(NRF52832_XXAA) && !defined(NRF52832_XXAB)
+#if !NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
nrf_nfct_int_enable(NRF_NFCT, NRF_NFCT_INT_FIELDLOST_MASK);
-#endif //!defined(NRF52832_XXAA) && !defined(NRF52832_XXAB)
+#endif // !NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_79)
NRFX_LOG_INFO("Start");
}
@@ -496,7 +488,7 @@ bool nrfx_nfct_field_check(void)
if (((field_state & NRF_NFCT_FIELD_STATE_PRESENT_MASK) == 0) &&
((field_state & NRF_NFCT_FIELD_STATE_LOCK_MASK) == 0))
{
- // Field is not active
+ /* Field is not active */
return false;
}
@@ -527,6 +519,7 @@ nrfx_err_t nrfx_nfct_tx(nrfx_nfct_data_desc_t const * p_tx_data,
nrf_nfct_rxtx_buffer_set(NRF_NFCT, (uint8_t *) p_tx_data->p_data, p_tx_data->data_size);
nrf_nfct_tx_bits_set(NRF_NFCT, NRFX_NFCT_BYTES_TO_BITS(p_tx_data->data_size));
nrf_nfct_frame_delay_mode_set(NRF_NFCT, (nrf_nfct_frame_delay_mode_t) delay_mode);
+ nrfx_nfct_frame_delay_max_set(false);
nrfx_nfct_rxtx_int_enable(NRFX_NFCT_TX_INT_MASK);
nrf_nfct_task_trigger(NRF_NFCT, NRF_NFCT_TASK_STARTTX);
@@ -541,7 +534,9 @@ void nrfx_nfct_state_force(nrfx_nfct_state_t state)
if (state == NRFX_NFCT_STATE_ACTIVATED)
{
m_timer_workaround.is_hfclk_on = true;
+ /* NFCT will be activated based on additional conditions */
nrfx_nfct_activate_check();
+ return;
}
#endif // NRFX_CHECK(USE_WORKAROUND_FOR_ANOMALY_190)
nrf_nfct_task_trigger(NRF_NFCT, (nrf_nfct_task_t) state);
@@ -588,14 +583,7 @@ nrfx_err_t nrfx_nfct_parameter_set(nrfx_nfct_param_t const * p_param)
uint32_t delay = p_param->data.fdt;
uint32_t delay_thr = NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk;
- // Delay validation.
- if (delay > (delay_thr + NRFX_NFCT_FWT_MAX_DIFF))
- {
- return NRFX_ERROR_INVALID_PARAM;
- }
-
- delay = (delay > delay_thr) ? delay_thr : delay;
- m_nfct_cb.frame_delay_max = delay;
+ m_nfct_cb.frame_delay_max = (delay > delay_thr) ? delay_thr : delay;
break;
}
@@ -635,7 +623,7 @@ nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
return NRFX_ERROR_INVALID_LENGTH;
}
-#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk)
+#if defined(FICR_NFC_TAGHEADER0_MFGID_Msk) && !defined(NRF_TRUSTZONE_NONSECURE)
uint32_t nfc_tag_header0 = NRF_FICR->NFC.TAGHEADER0;
uint32_t nfc_tag_header1 = NRF_FICR->NFC.TAGHEADER1;
uint32_t nfc_tag_header2 = NRF_FICR->NFC.TAGHEADER2;
@@ -643,8 +631,8 @@ nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
uint32_t nfc_tag_header0 = 0x5F;
uint32_t nfc_tag_header1 = 0;
uint32_t nfc_tag_header2 = 0;
-
#endif
+
p_nfcid1_buff[0] = (uint8_t) (nfc_tag_header0 >> 0);
p_nfcid1_buff[1] = (uint8_t) (nfc_tag_header0 >> 8);
p_nfcid1_buff[2] = (uint8_t) (nfc_tag_header0 >> 16);
@@ -662,14 +650,14 @@ nrfx_err_t nrfx_nfct_nfcid1_default_bytes_get(uint8_t * const p_nfcid1_buff,
p_nfcid1_buff[8] = (uint8_t) (nfc_tag_header2 >> 8);
p_nfcid1_buff[9] = (uint8_t) (nfc_tag_header2 >> 16);
}
- /* Begin: Bugfix for FTPAN-181. */
+ /* Begin: Workaround for anomaly 181. */
/* Workaround for wrong value in NFCID1. Value 0x88 cannot be used as byte 3
of a double-size NFCID1, according to the NFC Forum Digital Protocol specification. */
else if (p_nfcid1_buff[3] == 0x88)
{
p_nfcid1_buff[3] |= 0x11;
}
- /* End: Bugfix for FTPAN-181 */
+ /* End: Workaround for anomaly 181 */
}
return NRFX_SUCCESS;
@@ -751,29 +739,9 @@ void nrfx_nfct_irq_handler(void)
NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
- /* Clear TXFRAMESTART EVENT so it can be checked in hal_nfc_send */
- nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMESTART);
-
NRFX_LOG_DEBUG("Rx fend");
}
- if (NRFX_NFCT_EVT_ACTIVE(TXFRAMEEND))
- {
- nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMEEND);
-
- nrfx_nfct_evt_t nfct_evt =
- {
- .evt_id = NRFX_NFCT_EVT_TX_FRAMEEND
- };
-
- /* Disable TX END event to ignore frame transmission other than READ response */
- nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_TX_INT_MASK);
-
- NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
-
- NRFX_LOG_DEBUG("Tx fend");
- }
-
if (NRFX_NFCT_EVT_ACTIVE(SELECTED))
{
nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_SELECTED);
@@ -845,6 +813,23 @@ void nrfx_nfct_irq_handler(void)
m_nfct_cb.config.cb(&nfct_evt);
}
}
+
+ if (NRFX_NFCT_EVT_ACTIVE(TXFRAMEEND))
+ {
+ nrf_nfct_event_clear(NRF_NFCT, NRF_NFCT_EVENT_TXFRAMEEND);
+
+ nrfx_nfct_evt_t nfct_evt =
+ {
+ .evt_id = NRFX_NFCT_EVT_TX_FRAMEEND
+ };
+
+ /* Ignore any frame transmission until a new TX is scheduled by nrfx_nfct_tx() */
+ nrf_nfct_int_disable(NRF_NFCT, NRFX_NFCT_TX_INT_MASK);
+
+ NRFX_NFCT_CB_HANDLE(m_nfct_cb.config.cb, nfct_evt);
+
+ NRFX_LOG_DEBUG("Tx fend");
+ }
}
#endif // NRFX_CHECK(NRFX_NFCT_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c
index 7eff994..85027d7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_nvmc.c
@@ -80,9 +80,10 @@
*
* This value is used to determine whether the partial erase is still in progress.
*/
-#if defined(NRF52810_XXAA) || defined(NRF52811_XXAA) || defined(NRF52840_XXAA)
+#if defined(NRF52805_XXAA) || defined(NRF52810_XXAA) || \
+ defined(NRF52811_XXAA) || defined(NRF52840_XXAA)
#define NVMC_PAGE_ERASE_DURATION_MS 85
-#elif defined(NRF52833_XXAA) || defined(NRF9160_XXAA) || \
+#elif defined(NRF52820_XXAA) || defined(NRF52833_XXAA) || defined(NRF9160_XXAA) || \
defined(NRF5340_XXAA_APPLICATION) || defined(NRF5340_XXAA_NETWORK)
#define NVMC_PAGE_ERASE_DURATION_MS 87
#else
@@ -141,13 +142,36 @@ static uint32_t flash_total_size_get(void)
return flash_page_size_get() * flash_page_count_get();
}
-
static bool is_page_aligned_check(uint32_t addr)
{
/* If the modulo operation returns '0', then the address is aligned. */
return !(addr % flash_page_size_get());
}
+__STATIC_INLINE bool is_halfword_aligned(uint32_t addr)
+{
+ return ((addr & 0x1u) == 0u);
+}
+
+__STATIC_INLINE bool is_valid_address(uint32_t addr, bool uicr_allowed)
+{
+ if ((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get())
+ {
+ return true;
+ }
+#if !defined(NRF_TRUSTZONE_NONSECURE)
+ if (uicr_allowed &&
+ (addr - (uint32_t)NRF_UICR) < sizeof(NRF_UICR_Type))
+ {
+ return true;
+ }
+#else
+ (void)uicr_allowed;
+#endif
+
+ return false;
+}
+
static uint32_t partial_word_create(uint32_t addr, uint8_t const * bytes, uint32_t bytes_count)
{
uint32_t value32;
@@ -169,27 +193,42 @@ static uint32_t partial_word_create(uint32_t addr, uint8_t const * bytes, uint32
static void nvmc_readonly_mode_set(void)
{
-#if defined(NRF_TRUSTZONE_NONSECURE)
+ /*
+ * For secure code, the access mode needs to be set for both secure and
+ * non-secure regions.
+ */
+#if defined(NVMC_CONFIGNS_WEN_Msk)
nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_READONLY);
-#else
+#endif
+#if !defined(NRF_TRUSTZONE_NONSECURE)
nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_READONLY);
#endif
}
static void nvmc_write_mode_set(void)
{
-#if defined(NRF_TRUSTZONE_NONSECURE)
+ /*
+ * For secure code, the access mode needs to be set for both secure and
+ * non-secure regions.
+ */
+#if defined(NVMC_CONFIGNS_WEN_Msk)
nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_WRITE);
-#else
+#endif
+#if !defined(NRF_TRUSTZONE_NONSECURE)
nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_WRITE);
#endif
}
static void nvmc_erase_mode_set(void)
{
-#if defined(NRF_TRUSTZONE_NONSECURE)
+ /*
+ * For secure code, the access mode needs to be set for both secure and
+ * non-secure regions.
+ */
+#if defined(NVMC_CONFIGNS_WEN_Msk)
nrf_nvmc_nonsecure_mode_set(NRF_NVMC, NRF_NVMC_NS_MODE_ERASE);
-#else
+#endif
+#if !defined(NRF_TRUSTZONE_NONSECURE)
nrf_nvmc_mode_set(NRF_NVMC, NRF_NVMC_MODE_ERASE);
#endif
}
@@ -218,7 +257,7 @@ static void nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words
nrfx_err_t nrfx_nvmc_page_erase(uint32_t addr)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, false));
if (!is_page_aligned_check(addr))
{
@@ -260,7 +299,7 @@ void nrfx_nvmc_all_erase(void)
#if defined(NRF_NVMC_PARTIAL_ERASE_PRESENT)
nrfx_err_t nrfx_nvmc_page_partial_erase_init(uint32_t addr, uint32_t duration_ms)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, false));
if (!is_page_aligned_check(addr))
{
@@ -306,15 +345,33 @@ bool nrfx_nvmc_page_partial_erase_continue(void)
bool nrfx_nvmc_byte_writable_check(uint32_t addr, uint8_t val_to_check)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, true));
uint8_t val_on_addr = *(uint8_t const *)addr;
return (val_to_check & val_on_addr) == val_to_check;
}
+bool nrfx_nvmc_halfword_writable_check(uint32_t addr, uint16_t val_to_check)
+{
+ NRFX_ASSERT(is_valid_address(addr, true));
+ NRFX_ASSERT(is_halfword_aligned(addr));
+
+ uint16_t val_on_addr;
+
+ if ((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get())
+ {
+ val_on_addr = *(uint16_t const *)addr;
+ }
+ else
+ {
+ val_on_addr = nrfx_nvmc_otp_halfword_read(addr);
+ }
+ return (val_to_check & val_on_addr) == val_to_check;
+}
+
bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, true));
NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
uint32_t val_on_addr = *(uint32_t const *)addr;
@@ -323,14 +380,26 @@ bool nrfx_nvmc_word_writable_check(uint32_t addr, uint32_t val_to_check)
void nrfx_nvmc_byte_write(uint32_t addr, uint8_t value)
{
+ NRFX_ASSERT(is_valid_address(addr, true));
+
uint32_t aligned_addr = addr & ~(0x03UL);
nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, &value, 1));
}
+void nrfx_nvmc_halfword_write(uint32_t addr, uint16_t value)
+{
+ NRFX_ASSERT(is_valid_address(addr, true));
+ NRFX_ASSERT(is_halfword_aligned(addr));
+
+ uint32_t aligned_addr = addr & ~(0x03UL);
+
+ nrfx_nvmc_word_write(aligned_addr, partial_word_create(addr, (const uint8_t *)&value, 2));
+}
+
void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, true));
NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
nvmc_write_mode_set();
@@ -342,7 +411,7 @@ void nrfx_nvmc_word_write(uint32_t addr, uint32_t value)
void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, true));
nvmc_write_mode_set();
@@ -404,7 +473,7 @@ void nrfx_nvmc_bytes_write(uint32_t addr, void const * src, uint32_t num_bytes)
void nrfx_nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words)
{
- NRFX_ASSERT((addr - NVMC_FLASH_BASE_ADDRESS) < flash_total_size_get());
+ NRFX_ASSERT(is_valid_address(addr, true));
NRFX_ASSERT(nrfx_is_word_aligned((void const *)addr));
NRFX_ASSERT(nrfx_is_word_aligned(src));
@@ -415,6 +484,17 @@ void nrfx_nvmc_words_write(uint32_t addr, void const * src, uint32_t num_words)
nvmc_readonly_mode_set();
}
+uint16_t nrfx_nvmc_otp_halfword_read(uint32_t addr)
+{
+ NRFX_ASSERT(is_halfword_aligned(addr));
+
+ uint32_t aligned_addr = addr & ~(0x03UL);
+ uint32_t val32 = *(const uint32_t *)aligned_addr;
+
+ return (nrfx_is_word_aligned((void const *)addr) ? (uint16_t)(val32)
+ : (uint16_t)(val32 >> 16));
+}
+
uint32_t nrfx_nvmc_flash_size_get(void)
{
return flash_total_size_get();
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
index 7bd1bce..f571f98 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pdm.c
@@ -234,7 +234,10 @@ nrfx_err_t nrfx_pdm_init(nrfx_pdm_config_t const * p_config,
void nrfx_pdm_uninit(void)
{
nrf_pdm_disable(NRF_PDM0);
- nrf_pdm_psel_disconnect(NRF_PDM0);
+
+ nrf_gpio_cfg_default(nrf_pdm_clk_pin_get(NRF_PDM0));
+ nrf_gpio_cfg_default(nrf_pdm_din_pin_get(NRF_PDM0));
+
m_cb.drv_state = NRFX_DRV_STATE_UNINITIALIZED;
NRFX_LOG_INFO("Uninitialized.");
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
index d89bc7c..a7816c6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_pwm.c
@@ -115,6 +115,17 @@ static void configure_pins(nrfx_pwm_t const * p_instance,
nrf_pwm_pins_set(p_instance->p_registers, out_pins);
}
+static void deconfigure_pins(nrfx_pwm_t const * p_instance)
+{
+ for (uint8_t ch_idx = 0; ch_idx < NRF_PWM_CHANNEL_COUNT; ch_idx++)
+ {
+ uint32_t pin = nrf_pwm_pin_get(p_instance->p_registers, ch_idx);
+ if (pin != NRF_PWM_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(pin);
+ }
+ }
+}
nrfx_err_t nrfx_pwm_init(nrfx_pwm_t const * p_instance,
nrfx_pwm_config_t const * p_config,
@@ -191,6 +202,8 @@ void nrfx_pwm_uninit(nrfx_pwm_t const * p_instance)
nrf_pwm_disable(p_instance->p_registers);
+ deconfigure_pins(p_instance);
+
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
index a83e28c..48c5078 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_qdec.c
@@ -115,7 +115,7 @@ nrfx_err_t nrfx_qdec_init(nrfx_qdec_config_t const * p_config,
nrf_qdec_ledpre_set(NRF_QDEC, p_config->ledpre);
nrf_qdec_ledpol_set(NRF_QDEC, p_config->ledpol);
}
- nrf_qdec_pio_assign(NRF_QDEC, p_config->psela, p_config->pselb, p_config->pselled);
+ nrf_qdec_pins_set(NRF_QDEC, p_config->psela, p_config->pselb, p_config->pselled);
nrf_qdec_shorts_enable(NRF_QDEC, NRF_QDEC_SHORT_REPORTRDY_READCLRACC_MASK);
if (p_config->dbfen)
@@ -156,6 +156,16 @@ void nrfx_qdec_uninit(void)
NRFX_ASSERT(m_state != NRFX_DRV_STATE_UNINITIALIZED);
nrfx_qdec_disable();
NRFX_IRQ_DISABLE(nrfx_get_irq_number(NRF_QDEC));
+
+ nrf_gpio_cfg_default(nrf_qdec_phase_a_pin_get(NRF_QDEC));
+ nrf_gpio_cfg_default(nrf_qdec_phase_b_pin_get(NRF_QDEC));
+
+ uint32_t led_pin = nrf_qdec_led_pin_get(NRF_QDEC);
+ if (led_pin != NRF_QDEC_LED_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(led_pin);
+ }
+
m_state = NRFX_DRV_STATE_UNINITIALIZED;
NRFX_LOG_INFO("Uninitialized.");
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
index 60fe2ae..bd38379 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_rtc.c
@@ -157,7 +157,9 @@ nrfx_err_t nrfx_rtc_cc_disable(nrfx_rtc_t const * p_instance, uint32_t channel)
return err_code;
}
}
- NRFX_LOG_INFO("RTC id: %d, channel disabled: %lu.", p_instance->instance_id, channel);
+ NRFX_LOG_INFO("RTC id: %d, channel disabled: %lu.",
+ p_instance->instance_id,
+ (unsigned long)channel);
err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
@@ -211,8 +213,8 @@ nrfx_err_t nrfx_rtc_cc_set(nrfx_rtc_t const * p_instance,
NRFX_LOG_INFO("RTC id: %d, channel enabled: %lu, compare value: %lu.",
p_instance->instance_id,
- channel,
- val);
+ (unsigned long)channel,
+ (unsigned long)val);
err_code = NRFX_SUCCESS;
NRFX_LOG_INFO("Function: %s, error code: %s.", __func__, NRFX_LOG_ERROR_STRING_GET(err_code));
return err_code;
@@ -290,7 +292,9 @@ static void irq_handler(NRF_RTC_Type * p_reg,
nrf_rtc_event_disable(p_reg, int_mask);
nrf_rtc_int_disable(p_reg, int_mask);
nrf_rtc_event_clear(p_reg, event);
- NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id);
+ NRFX_LOG_DEBUG("Event: %s, instance id: %lu.",
+ EVT_TO_STR(event),
+ (unsigned long)instance_id);
m_handlers[instance_id]((nrfx_rtc_int_type_t)i);
}
int_mask <<= 1;
@@ -301,7 +305,9 @@ static void irq_handler(NRF_RTC_Type * p_reg,
if (nrf_rtc_int_enable_check(p_reg, NRF_RTC_INT_TICK_MASK) && nrf_rtc_event_check(p_reg, event))
{
nrf_rtc_event_clear(p_reg, event);
- NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id);
+ NRFX_LOG_DEBUG("Event: %s, instance id: %lu.",
+ EVT_TO_STR(event),
+ (unsigned long)instance_id);
m_handlers[instance_id](NRFX_RTC_INT_TICK);
}
@@ -310,7 +316,9 @@ static void irq_handler(NRF_RTC_Type * p_reg,
nrf_rtc_event_check(p_reg, event))
{
nrf_rtc_event_clear(p_reg, event);
- NRFX_LOG_DEBUG("Event: %s, instance id: %lu.", EVT_TO_STR(event), instance_id);
+ NRFX_LOG_DEBUG("Event: %s, instance id: %lu.",
+ EVT_TO_STR(event),
+ (unsigned long)instance_id);
m_handlers[instance_id](NRFX_RTC_INT_OVERFLOW);
}
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c
index 4e24409..f9d931b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_saadc.c
@@ -286,7 +286,7 @@ nrfx_err_t nrfx_saadc_channels_config(nrfx_saadc_channel_t const * p_channels,
p_channels[i].channel_index,
&p_channels[i].channel_config);
- NRFX_ASSERT(p_channels[i].pin_p);
+ NRFX_ASSERT(p_channels[i].pin_p != NRF_SAADC_INPUT_DISABLED);
m_cb.channels_pselp[p_channels[i].channel_index] = p_channels[i].pin_p;
m_cb.channels_pseln[p_channels[i].channel_index] = p_channels[i].pin_n;
m_cb.channels_configured |= 1U << p_channels[i].channel_index;
@@ -595,7 +595,7 @@ void nrfx_saadc_abort(void)
nrfx_err_t nrfx_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high)
{
NRFX_ASSERT(m_cb.saadc_state != NRF_SAADC_STATE_UNINITIALIZED);
- NRFX_ASSERT(limit_high <= limit_low);
+ NRFX_ASSERT(limit_high >= limit_low);
if (!m_cb.event_handler)
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
index 1cbed19..836e0c4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spi.c
@@ -57,7 +57,6 @@ typedef struct
// [no need for 'volatile' attribute for the following members, as they
// are not concurrently used in IRQ handlers and main line code]
uint8_t ss_pin;
- uint8_t miso_pin;
uint8_t orc;
size_t bytes_transferred;
@@ -152,7 +151,6 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * p_instance,
{
miso_pin = NRF_SPI_PIN_NOT_CONNECTED;
}
- m_cb[p_instance->drv_inst_idx].miso_pin = p_config->miso_pin;
// - Slave Select (optional) - output with initial value 1 (inactive).
if (p_config->ss_pin != NRFX_SPI_PIN_NOT_USED)
{
@@ -168,11 +166,6 @@ nrfx_err_t nrfx_spi_init(nrfx_spi_t const * p_instance,
m_cb[p_instance->drv_inst_idx].orc = p_config->orc;
- if (p_cb->handler)
- {
- nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
- }
-
nrf_spi_enable(p_spi);
if (p_cb->handler)
@@ -194,23 +187,34 @@ void nrfx_spi_uninit(nrfx_spi_t const * p_instance)
{
spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
+ NRF_SPI_Type * p_spi = p_instance->p_reg;
if (p_cb->handler)
{
NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
+ nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK);
}
- NRF_SPI_Type * p_spi = p_instance->p_reg;
- if (p_cb->handler)
+ nrf_spi_disable(p_spi);
+
+ nrf_gpio_cfg_default(nrf_spi_sck_pin_get(p_spi));
+
+ uint32_t miso_pin = nrf_spi_miso_pin_get(p_spi);
+ if (miso_pin != NRF_SPI_PIN_NOT_CONNECTED)
{
- nrf_spi_int_disable(p_spi, NRF_SPI_ALL_INTS_MASK);
+ nrf_gpio_cfg_default(miso_pin);
}
- if (p_cb->miso_pin != NRFX_SPI_PIN_NOT_USED)
+ uint32_t mosi_pin = nrf_spi_mosi_pin_get(p_spi);
+ if (mosi_pin != NRF_SPI_PIN_NOT_CONNECTED)
{
- nrf_gpio_cfg_default(p_cb->miso_pin);
+ nrf_gpio_cfg_default(mosi_pin);
+ }
+
+ if (p_cb->ss_pin != NRFX_SPI_PIN_NOT_USED)
+ {
+ nrf_gpio_cfg_default(p_cb->ss_pin);
}
- nrf_spi_disable(p_spi);
#if NRFX_CHECK(NRFX_PRS_ENABLED)
nrfx_prs_release(p_instance->p_reg);
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
index 007d177..6414eab 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spim.c
@@ -185,7 +185,6 @@ typedef struct
// are not concurrently used in IRQ handlers and main line code]
bool ss_active_high;
uint8_t ss_pin;
- uint8_t miso_pin;
uint8_t orc;
#if NRFX_CHECK(NRFX_SPIM_NRF52_ANOMALY_109_WORKAROUND_ENABLED)
@@ -236,6 +235,18 @@ static void anomaly_198_disable(void)
}
#endif // NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED)
+static void spim_abort(NRF_SPIM_Type * p_spim, spim_control_block_t * p_cb)
+{
+ nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
+ bool stopped;
+ NRFX_WAIT_FOR(nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED), 100, 1, stopped);
+ if (!stopped)
+ {
+ NRFX_LOG_ERROR("Failed to stop instance with base address: %p.", (void *)p_spim);
+ }
+ p_cb->transfer_in_progress = false;
+}
+
nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance,
nrfx_spim_config_t const * p_config,
nrfx_spim_evt_handler_t handler,
@@ -348,7 +359,6 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance,
{
miso_pin = NRF_SPIM_PIN_NOT_CONNECTED;
}
- p_cb->miso_pin = p_config->miso_pin;
// - Slave Select (optional) - output with initial value 1 (inactive).
// 'p_cb->ss_pin' variable is used during transfers to check if SS pin should be toggled,
@@ -400,11 +410,6 @@ nrfx_err_t nrfx_spim_init(nrfx_spim_t const * p_instance,
nrf_spim_orc_set(p_spim, p_config->orc);
- if (p_cb->handler)
- {
- nrf_spim_int_enable(p_spim, NRF_SPIM_INT_END_MASK);
- }
-
nrf_spim_enable(p_spim);
if (p_cb->handler)
@@ -426,31 +431,47 @@ void nrfx_spim_uninit(nrfx_spim_t const * p_instance)
{
spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
+ NRF_SPIM_Type * p_spim = p_instance->p_reg;
if (p_cb->handler)
{
NRFX_IRQ_DISABLE(nrfx_get_irq_number(p_instance->p_reg));
- }
-
- NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_reg;
- if (p_cb->handler)
- {
nrf_spim_int_disable(p_spim, NRF_SPIM_ALL_INTS_MASK);
if (p_cb->transfer_in_progress)
{
// Ensure that SPI is not performing any transfer.
- nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
- while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED))
- {}
- p_cb->transfer_in_progress = false;
+ spim_abort(p_spim, p_cb);
}
}
- if (p_cb->miso_pin != NRFX_SPIM_PIN_NOT_USED)
+ nrf_spim_disable(p_spim);
+
+ nrf_gpio_cfg_default(nrf_spim_sck_pin_get(p_spim));
+
+ uint32_t miso_pin = nrf_spim_miso_pin_get(p_spim);
+ if (miso_pin != NRF_SPIM_PIN_NOT_CONNECTED)
{
- nrf_gpio_cfg_default(p_cb->miso_pin);
+ nrf_gpio_cfg_default(miso_pin);
+ }
+
+ uint32_t mosi_pin = nrf_spim_mosi_pin_get(p_spim);
+ if (mosi_pin != NRF_SPIM_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(mosi_pin);
+ }
+
+ if (p_cb->ss_pin != NRFX_SPIM_PIN_NOT_USED)
+ {
+ nrf_gpio_cfg_default(p_cb->ss_pin);
}
- nrf_spim_disable(p_spim);
+
+#if NRFX_CHECK(NRFX_SPIM_EXTENDED_ENABLED)
+ uint32_t dcx_pin = nrf_spim_dcx_pin_get(p_spim);
+ if (dcx_pin != NRF_SPIM_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(dcx_pin);
+ }
+#endif
#ifdef USE_WORKAROUND_FOR_ANOMALY_195
if (p_spim == NRF_SPIM3)
@@ -595,7 +616,11 @@ static nrfx_err_t spim_xfer(NRF_SPIM_Type * p_spim,
if (!p_cb->handler)
{
- while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){}
+ if (!(flags & NRFX_SPIM_FLAG_HOLD_XFER))
+ {
+ while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
+ {}
+ }
#if NRFX_CHECK(NRFX_SPIM3_NRF52840_ANOMALY_198_WORKAROUND_ENABLED)
if (p_spim == NRF_SPIM3)
@@ -640,6 +665,8 @@ nrfx_err_t nrfx_spim_xfer(nrfx_spim_t const * p_instance,
NRFX_ASSERT(SPIM_LENGTH_VALIDATE(p_instance->drv_inst_idx,
p_xfer_desc->rx_length,
p_xfer_desc->tx_length));
+ NRFX_ASSERT(!(flags & NRFX_SPIM_FLAG_HOLD_XFER) ||
+ (p_cb->ss_pin == NRFX_SPIM_PIN_NOT_USED));
nrfx_err_t err_code = NRFX_SUCCESS;
@@ -687,10 +714,7 @@ void nrfx_spim_abort(nrfx_spim_t const * p_instance)
spim_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
- nrf_spim_task_trigger(p_instance->p_reg, NRF_SPIM_TASK_STOP);
- while (!nrf_spim_event_check(p_instance->p_reg, NRF_SPIM_EVENT_STOPPED))
- {}
- p_cb->transfer_in_progress = false;
+ spim_abort(p_instance->p_reg, p_cb);
}
uint32_t nrfx_spim_start_task_get(nrfx_spim_t const * p_instance)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
index be30e79..0ca6047 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_spis.c
@@ -303,6 +303,21 @@ void nrfx_spis_uninit(nrfx_spis_t const * p_instance)
nrf_spis_int_disable(p_spis, DISABLE_ALL);
#undef DISABLE_ALL
+ nrf_gpio_cfg_default(nrf_spis_sck_pin_get(p_spis));
+ nrf_gpio_cfg_default(nrf_spis_csn_pin_get(p_spis));
+
+ uint32_t miso_pin = nrf_spis_miso_pin_get(p_spis);
+ if (miso_pin != NRF_SPIS_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(miso_pin);
+ }
+
+ uint32_t mosi_pin = nrf_spis_mosi_pin_get(p_spis);
+ if (mosi_pin != NRF_SPIS_PIN_NOT_CONNECTED)
+ {
+ nrf_gpio_cfg_default(mosi_pin);
+ }
+
#if NRFX_CHECK(NRFX_PRS_ENABLED)
nrfx_prs_release(p_spis);
#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
index d8df49b..347edb1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_timer.c
@@ -226,7 +226,7 @@ void nrfx_timer_compare(nrfx_timer_t const * p_instance,
nrf_timer_cc_set(p_instance->p_reg, cc_channel, cc_value);
NRFX_LOG_INFO("Timer id: %d, capture value set: %lu, channel: %d.",
p_instance->instance_id,
- cc_value,
+ (unsigned long)cc_value,
cc_channel);
}
@@ -248,7 +248,7 @@ void nrfx_timer_extended_compare(nrfx_timer_t const * p_instance,
enable_int);
NRFX_LOG_INFO("Timer id: %d, capture value set: %lu, channel: %d.",
p_instance->instance_id,
- cc_value,
+ (unsigned long)cc_value,
cc_channel);
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c
index 8452ccf..b15f7c6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twi_twim.c
@@ -30,6 +30,9 @@
*/
#include <nrfx_twi_twim.h>
+
+#if NRFX_CHECK(NRFX_TWI_ENABLED) || NRFX_CHECK(NRFX_TWIM_ENABLED)
+
#include <hal/nrf_gpio.h>
#define TWI_TWIM_PIN_CONFIGURE(_pin) nrf_gpio_cfg((_pin), \
@@ -79,3 +82,5 @@ nrfx_err_t nrfx_twi_twim_bus_recover(uint32_t scl_pin, uint32_t sda_pin)
return NRFX_ERROR_INTERNAL;
}
}
+
+#endif // NRFX_CHECK(NRFX_TWI_ENABLED) || NRFX_CHECK(NRFX_TWIM_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
index 8c0085c..64ee394 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twim.c
@@ -312,8 +312,8 @@ void nrfx_twim_uninit(nrfx_twim_t const * p_instance)
if (!p_cb->hold_bus_uninit)
{
- nrf_gpio_cfg_default(p_instance->p_twim->PSEL.SCL);
- nrf_gpio_cfg_default(p_instance->p_twim->PSEL.SDA);
+ nrf_gpio_cfg_default(nrf_twim_scl_pin_get(p_instance->p_twim));
+ nrf_gpio_cfg_default(nrf_twim_sda_pin_get(p_instance->p_twim));
}
p_cb->state = NRFX_DRV_STATE_UNINITIALIZED;
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
index 9298348..10909c0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_twis.c
@@ -557,19 +557,13 @@ void nrfx_twis_uninit(nrfx_twis_t const * p_instance)
twis_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED);
- TWIS_PSEL_Type psel = p_reg->PSEL;
+ uint32_t scl_pin = nrf_twis_scl_pin_get(p_reg);
+ uint32_t sda_pin = nrf_twis_sda_pin_get(p_reg);
nrfx_twis_swreset(p_reg);
- /* Clear pins state if */
- if (!(TWIS_PSEL_SCL_CONNECT_Msk & psel.SCL))
- {
- nrf_gpio_cfg_default(psel.SCL);
- }
- if (!(TWIS_PSEL_SDA_CONNECT_Msk & psel.SDA))
- {
- nrf_gpio_cfg_default(psel.SDA);
- }
+ nrf_gpio_cfg_default(scl_pin);
+ nrf_gpio_cfg_default(sda_pin);
#if NRFX_CHECK(NRFX_PRS_ENABLED)
nrfx_prs_release(p_reg);
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
index 88a06d3..2f626f4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_uarte.c
@@ -96,6 +96,7 @@ typedef struct
size_t rx_buffer_length;
size_t rx_secondary_buffer_length;
nrfx_drv_state_t state;
+ bool rx_aborted;
} uarte_control_block_t;
static uarte_control_block_t m_cb[NRFX_UARTE_ENABLED_COUNT];
@@ -212,8 +213,16 @@ static void apply_workaround_for_enable_anomaly(nrfx_uarte_t const * p_instance)
nrf_uarte_enable(p_instance->p_reg);
nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
- while (*rxenable_reg)
- {}
+ bool workaround_succeded;
+ // The UARTE is able to receive up to four bytes after the STOPRX task has been triggered.
+ // On lowest supported baud rate (1200 baud), with parity bit and two stop bits configured
+ // (resulting in 12 bits per data byte sent), this may take up to 40 ms.
+ NRFX_WAIT_FOR(*rxenable_reg == 0, 40000, 1, workaround_succeded);
+ if (!workaround_succeded)
+ {
+ NRFX_LOG_ERROR("Failed to apply workaround for instance with base address: %p.",
+ (void *)p_instance->p_reg);
+ }
(void)nrf_uarte_errorsrc_get_and_clear(p_instance->p_reg);
nrf_uarte_disable(p_instance->p_reg);
@@ -313,9 +322,18 @@ void nrfx_uarte_uninit(nrfx_uarte_t const * p_instance)
nrf_uarte_task_trigger(p_reg, NRF_UARTE_TASK_STOPTX);
// Wait for TXSTOPPED event and for RXTO event, provided that there was ongoing reception.
- while (!nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_TXSTOPPED) ||
- (p_cb->rx_buffer_length && !nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_RXTO)))
- {}
+ bool stopped;
+
+ // The UARTE is able to receive up to four bytes after the STOPRX task has been triggered.
+ // On lowest supported baud rate (1200 baud), with parity bit and two stop bits configured
+ // (resulting in 12 bits per data byte sent), this may take up to 40 ms.
+ NRFX_WAIT_FOR((nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_TXSTOPPED) &&
+ (!p_cb->rx_buffer_length || nrf_uarte_event_check(p_reg, NRF_UARTE_EVENT_RXTO))),
+ 40000, 1, stopped);
+ if (!stopped)
+ {
+ NRFX_LOG_ERROR("Failed to stop instance with base address: %p.", (void *)p_instance->p_reg);
+ }
nrf_uarte_disable(p_reg);
pins_to_default(p_instance);
@@ -513,6 +531,7 @@ nrfx_err_t nrfx_uarte_rx(nrfx_uarte_t const * p_instance,
}
else
{
+ p_cb->rx_aborted = false;
nrf_uarte_int_enable(p_instance->p_reg, NRF_UARTE_INT_ERROR_MASK |
NRF_UARTE_INT_ENDRX_MASK);
}
@@ -582,6 +601,7 @@ void nrfx_uarte_rx_abort(nrfx_uarte_t const * p_instance)
{
nrf_uarte_shorts_disable(p_instance->p_reg, NRF_UARTE_SHORT_ENDRX_STARTRX);
}
+ p_cb->rx_aborted = true;
nrf_uarte_task_trigger(p_instance->p_reg, NRF_UARTE_TASK_STOPRX);
NRFX_LOG_INFO("RX transaction aborted.");
}
@@ -609,11 +629,11 @@ static void uarte_irq_handler(NRF_UARTE_Type * p_uarte,
else if (nrf_uarte_event_check(p_uarte, NRF_UARTE_EVENT_ENDRX))
{
nrf_uarte_event_clear(p_uarte, NRF_UARTE_EVENT_ENDRX);
- size_t amount = nrf_uarte_rx_amount_get(p_uarte);
- // If the transfer was stopped before completion, amount of transfered bytes
- // will not be equal to the buffer length. Interrupted transfer is ignored.
- if (amount == p_cb->rx_buffer_length)
+
+ // Aborted transfers are handled in RXTO event processing.
+ if (!p_cb->rx_aborted)
{
+ size_t amount = p_cb->rx_buffer_length;
if (p_cb->rx_secondary_buffer_length != 0)
{
uint8_t * p_data = p_cb->p_rx_buffer;
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
index c0598e0..41749e9 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd.c
@@ -35,7 +35,6 @@
#include <nrfx_usbd.h>
#include "nrfx_usbd_errata.h"
-#include <nrfx_systick.h> /* Marker to delete when not required anymore: >> NRFX_USBD_ERRATA_ENABLE << */
#include <string.h>
#define NRFX_LOG_MODULE USBD
@@ -50,16 +49,6 @@
#define NRFX_USBD_EARLY_DMA_PROCESS 1
#endif
-#ifndef NRFX_USBD_PROTO1_FIX_DEBUG
-/* Debug information when events are fixed*/
-#define NRFX_USBD_PROTO1_FIX_DEBUG 1
-#endif
-
-#define NRFX_USBD_LOG_PROTO1_FIX_PRINTF(...) \
- do{ \
- if (NRFX_USBD_PROTO1_FIX_DEBUG){ NRFX_LOG_DEBUG(__VA_ARGS__); }\
- } while (0)
-
#ifndef NRFX_USBD_STARTED_EV_ENABLE
#define NRFX_USBD_STARTED_EV_ENABLE 0
#endif
@@ -67,7 +56,6 @@
#ifndef NRFX_USBD_CONFIG_ISO_IN_ZLP
/*
* Respond to an IN token on ISO IN endpoint with ZLP when no data is ready.
- * NOTE: This option does not work on Engineering A chip.
*/
#define NRFX_USBD_CONFIG_ISO_IN_ZLP 0
#endif
@@ -95,6 +83,11 @@
#define NRFX_USBD_DMAREQ_PROCESS_DEBUG 1
#endif
+#ifndef NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211
+/* Anomaly 211 - Device remains in SUSPEND too long when host resumes
+ a bus activity (sending SOF packets) without a RESUME condition. */
+#define NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211 0
+#endif
/**
* @defgroup nrfx_usbd_int USB Device driver internal part
@@ -269,7 +262,7 @@ static uint32_t m_ep_ready;
* Mask prepared USBD data for transmission.
* It is cleared when no more data to transmit left.
*/
-static uint32_t m_ep_dma_waiting;
+static nrfx_atomic_t m_ep_dma_waiting;
/**
* @brief Current EasyDMA state.
@@ -281,11 +274,9 @@ static uint32_t m_ep_dma_waiting;
static bool m_dma_pending;
/**
- * @brief Simulated data EP status bits required for errata 104.
- *
- * Marker to delete when not required anymore: >> NRFX_USBD_ERRATA_ENABLE <<.
+ * @brief First time enabling after reset. Used in nRF52 errata 223.
*/
-static uint32_t m_simulated_dataepstatus;
+static bool m_first_enable = true;
/**
* @brief The structure that would hold transfer configuration to every endpoint
@@ -1284,13 +1275,6 @@ static void ev_epdata_handler(void)
{
/* Get all endpoints that have acknowledged transfer */
uint32_t dataepstatus = nrf_usbd_epdatastatus_get_and_clear(NRF_USBD);
- if (nrfx_usbd_errata_104())
- {
- dataepstatus |= (m_simulated_dataepstatus &
- ~((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0)));
- m_simulated_dataepstatus &=
- ((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0));
- }
NRFX_LOG_DEBUG("USBD event: EndpointEPStatus: %x", dataepstatus);
/* All finished endpoint have to be marked as busy */
@@ -1447,49 +1431,14 @@ static void usbd_dmareq_process(void)
/* Start transfer to the endpoint buffer */
nrf_usbd_ep_easydma_set(NRF_USBD, ep, transfer.p_data.addr, (uint32_t)transfer.size);
- if (nrfx_usbd_errata_104())
- {
- uint32_t cnt_end = (uint32_t)(-1);
- do
- {
- uint32_t cnt = (uint32_t)(-1);
- do
- {
- nrf_usbd_event_clear(NRF_USBD, NRF_USBD_EVENT_STARTED);
- usbd_dma_start(ep);
- nrfx_systick_delay_us(2);
- ++cnt;
- }while (!nrf_usbd_event_check(NRF_USBD, NRF_USBD_EVENT_STARTED));
- if (cnt)
- {
- NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" DMA restarted: %u times", cnt);
- }
-
- nrfx_systick_delay_us(30);
- while (0 == (0x20 & *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x474))))
- {
- nrfx_systick_delay_us(2);
- }
- nrfx_systick_delay_us(1);
-
- ++cnt_end;
- } while (!nrf_usbd_event_check(NRF_USBD, nrfx_usbd_ep_to_endevent(ep)));
- if (cnt_end)
- {
- NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" DMA fully restarted: %u times", cnt_end);
- }
- }
- else
+ usbd_dma_start(ep);
+ /* There is a lot of USBD registers that cannot be accessed during EasyDMA transfer.
+ * This is quick fix to maintain stability of the stack.
+ * It cost some performance but makes stack stable. */
+ while (!nrf_usbd_event_check(NRF_USBD, nrfx_usbd_ep_to_endevent(ep)) &&
+ !nrf_usbd_event_check(NRF_USBD, NRF_USBD_EVENT_USBRESET))
{
- usbd_dma_start(ep);
- /* There is a lot of USBD registers that cannot be accessed during EasyDMA transfer.
- * This is quick fix to maintain stability of the stack.
- * It cost some performance but makes stack stable. */
- while (!nrf_usbd_event_check(NRF_USBD, nrfx_usbd_ep_to_endevent(ep)) &&
- !nrf_usbd_event_check(NRF_USBD, NRF_USBD_EVENT_USBRESET))
- {
- /* Empty */
- }
+ /* Empty */
}
if (NRFX_USBD_DMAREQ_PROCESS_DEBUG)
@@ -1508,6 +1457,126 @@ static void usbd_dmareq_process(void)
}
}
}
+
+/**
+ * @brief Wait for a specified eventcause and clear it afterwards.
+ */
+static inline void usbd_eventcause_wait_and_clear(nrf_usbd_eventcause_mask_t eventcause)
+{
+ while (0 == (eventcause & nrf_usbd_eventcause_get(NRF_USBD)))
+ {
+ /* Empty loop */
+ }
+ nrf_usbd_eventcause_clear(NRF_USBD, eventcause);
+}
+
+/**
+ * @brief Begin errata 171.
+ */
+static inline void usbd_errata_171_begin(void)
+{
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+}
+
+/**
+ * @brief End errata 171.
+ */
+static inline void usbd_errata_171_end(void)
+{
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+}
+
+/**
+ * @brief Begin erratas 187 and 211.
+ */
+static inline void usbd_errata_187_211_begin(void)
+{
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+}
+
+/**
+ * @brief End erratas 187 and 211.
+ */
+static inline void usbd_errata_187_211_end(void)
+{
+ NRFX_CRITICAL_SECTION_ENTER();
+ if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
+ {
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
+ *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+ }
+ else
+ {
+ *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
+ }
+ NRFX_CRITICAL_SECTION_EXIT();
+}
+
+/**
+ * @brief Enable USBD peripheral.
+ */
+static void usbd_enable(void)
+{
+ if (nrfx_usbd_errata_187())
+ {
+ usbd_errata_187_211_begin();
+ }
+
+ if (nrfx_usbd_errata_171())
+ {
+ usbd_errata_171_begin();
+ }
+
+ /* Enable the peripheral */
+ nrf_usbd_enable(NRF_USBD);
+
+ /* Waiting for peripheral to enable, this should take a few us */
+ usbd_eventcause_wait_and_clear(NRF_USBD_EVENTCAUSE_READY_MASK);
+
+ if (nrfx_usbd_errata_171())
+ {
+ usbd_errata_171_end();
+ }
+
+ if (nrfx_usbd_errata_187())
+ {
+ usbd_errata_187_211_end();
+ }
+}
/** @} */
/**
@@ -1566,97 +1635,6 @@ void nrfx_usbd_irq_handler(void)
to_process &= ~(1UL << event_nr);
}
- if (nrfx_usbd_errata_104())
- {
- /* Event correcting */
- if ((!m_dma_pending) && (0 != (active & (USBD_INTEN_SOF_Msk))))
- {
- uint8_t usbi, uoi, uii;
- /* Testing */
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7A9;
- uii = (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- if (0 != uii)
- {
- uii &= (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- }
-
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AA;
- uoi = (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- if (0 != uoi)
- {
- uoi &= (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- }
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AB;
- usbi = (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- if (0 != usbi)
- {
- usbi &= (uint8_t)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- }
- /* Processing */
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AC;
- uii &= (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
- if (0 != uii)
- {
- uint8_t rb;
- m_simulated_dataepstatus |= ((uint32_t)uii) << NRFX_USBD_EPIN_BITPOS_0;
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7A9;
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = uii;
- rb = (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
- NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" uii: 0x%.2x (0x%.2x)", uii, rb);
- (void)rb;
- }
-
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AD;
- uoi &= (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
- if (0 != uoi)
- {
- uint8_t rb;
- m_simulated_dataepstatus |= ((uint32_t)uoi) << NRFX_USBD_EPOUT_BITPOS_0;
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AA;
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = uoi;
- rb = (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
- NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" uoi: 0x%.2u (0x%.2x)", uoi, rb);
- (void)rb;
- }
-
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AE;
- usbi &= (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
- if (0 != usbi)
- {
- uint8_t rb;
- if (usbi & 0x01)
- {
- active |= USBD_INTEN_EP0SETUP_Msk;
- }
- if (usbi & 0x10)
- {
- active |= USBD_INTEN_USBRESET_Msk;
- }
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7AB;
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = usbi;
- rb = (uint8_t)*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804));
- NRFX_USBD_LOG_PROTO1_FIX_PRINTF(" usbi: 0x%.2u (0x%.2x)", usbi, rb);
- (void)rb;
- }
-
- if (0 != (m_simulated_dataepstatus &
- ~((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0))))
- {
- active |= enabled & NRF_USBD_INT_DATAEP_MASK;
- }
- if (0 != (m_simulated_dataepstatus &
- ((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0))))
- {
- if (0 != (enabled & NRF_USBD_INT_EP0DATADONE_MASK))
- {
- m_simulated_dataepstatus &=
- ~((1U << NRFX_USBD_EPOUT_BITPOS_0) | (1U << NRFX_USBD_EPIN_BITPOS_0));
- active |= NRF_USBD_INT_EP0DATADONE_MASK;
- }
- }
- }
- }
-
/* Process the active interrupts */
bool setup_active = 0 != (active & NRF_USBD_INT_EP0SETUP_MASK);
active &= ~NRF_USBD_INT_EP0SETUP_MASK;
@@ -1724,6 +1702,7 @@ void nrfx_usbd_uninit(void)
return;
}
+
void nrfx_usbd_enable(void)
{
NRFX_ASSERT(m_drv_state == NRFX_DRV_STATE_INITIALIZED);
@@ -1731,62 +1710,24 @@ void nrfx_usbd_enable(void)
/* Prepare for READY event receiving */
nrf_usbd_eventcause_clear(NRF_USBD, NRF_USBD_EVENTCAUSE_READY_MASK);
- if (nrfx_usbd_errata_187())
- {
- NRFX_CRITICAL_SECTION_ENTER();
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
- }
- NRFX_CRITICAL_SECTION_EXIT();
- }
+ usbd_enable();
- if (nrfx_usbd_errata_171())
+ if (nrfx_usbd_errata_223() && m_first_enable)
{
- NRFX_CRITICAL_SECTION_ENTER();
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
- }
- NRFX_CRITICAL_SECTION_EXIT();
- }
+ nrf_usbd_disable(NRF_USBD);
- /* Enable the peripheral */
- nrf_usbd_enable(NRF_USBD);
- /* Waiting for peripheral to enable, this should take a few us */
- while (0 == (NRF_USBD_EVENTCAUSE_READY_MASK & nrf_usbd_eventcause_get(NRF_USBD)))
- {
- /* Empty loop */
+ usbd_enable();
+
+ m_first_enable = false;
}
- nrf_usbd_eventcause_clear(NRF_USBD, NRF_USBD_EVENTCAUSE_READY_MASK);
- if (nrfx_usbd_errata_171())
+#if NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211
+ if (nrfx_usbd_errata_187() || nrfx_usbd_errata_211())
+#else
+ if (nrfx_usbd_errata_187())
+#endif
{
- NRFX_CRITICAL_SECTION_ENTER();
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
- }
-
- NRFX_CRITICAL_SECTION_EXIT();
+ usbd_errata_187_211_begin();
}
if (nrfx_usbd_errata_166())
@@ -1815,20 +1756,13 @@ void nrfx_usbd_enable(void)
m_drv_state = NRFX_DRV_STATE_POWERED_ON;
+#if NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211
+ if (nrfx_usbd_errata_187() && !nrfx_usbd_errata_211())
+#else
if (nrfx_usbd_errata_187())
+#endif
{
- NRFX_CRITICAL_SECTION_ENTER();
- if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000)
- {
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
- *((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
- }
- else
- {
- *((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
- }
- NRFX_CRITICAL_SECTION_EXIT();
+ usbd_errata_187_211_end();
}
}
@@ -1844,6 +1778,13 @@ void nrfx_usbd_disable(void)
nrf_usbd_disable(NRF_USBD);
usbd_dma_pending_clear();
m_drv_state = NRFX_DRV_STATE_INITIALIZED;
+
+#if NRFX_USBD_USE_WORKAROUND_FOR_ANOMALY_211
+ if (nrfx_usbd_errata_211())
+ {
+ usbd_errata_187_211_end();
+ }
+#endif
}
void nrfx_usbd_start(bool enable_sof)
@@ -1861,7 +1802,7 @@ void nrfx_usbd_start(bool enable_sof)
NRF_USBD_INT_EP0SETUP_MASK |
NRF_USBD_INT_DATAEP_MASK;
- if (enable_sof || nrfx_usbd_errata_104())
+ if (enable_sof)
{
ints_to_enable |= NRF_USBD_INT_SOF_MASK;
}
@@ -2297,21 +2238,7 @@ void nrfx_usbd_setup_get(nrfx_usbd_setup_t * p_setup)
void nrfx_usbd_setup_data_clear(void)
{
- if (nrfx_usbd_errata_104())
- {
- /* For this fix to work properly, it must be ensured that the task is
- * executed twice one after another - blocking ISR. This is however a temporary
- * solution to be used only before production version of the chip. */
- uint32_t primask_copy = __get_PRIMASK();
- __disable_irq();
- nrf_usbd_task_trigger(NRF_USBD, NRF_USBD_TASK_EP0RCVOUT);
- nrf_usbd_task_trigger(NRF_USBD, NRF_USBD_TASK_EP0RCVOUT);
- __set_PRIMASK(primask_copy);
- }
- else
- {
- nrf_usbd_task_trigger(NRF_USBD, NRF_USBD_TASK_EP0RCVOUT);
- }
+ nrf_usbd_task_trigger(NRF_USBD, NRF_USBD_TASK_EP0RCVOUT);
}
void nrfx_usbd_setup_clear(void)
@@ -2335,25 +2262,13 @@ void nrfx_usbd_transfer_out_drop(nrfx_usbd_ep_t ep)
{
NRFX_ASSERT(NRF_USBD_EPOUT_CHECK(ep));
- if (nrfx_usbd_errata_200())
- {
- NRFX_CRITICAL_SECTION_ENTER();
- m_ep_ready &= ~(1U << ep2bit(ep));
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7C5 + (2u * NRF_USBD_EP_NR_GET(ep));
- *((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = 0;
- (void)(*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)));
- NRFX_CRITICAL_SECTION_EXIT();
- }
- else
+ NRFX_CRITICAL_SECTION_ENTER();
+ m_ep_ready &= ~(1U << ep2bit(ep));
+ if (!NRF_USBD_EPISO_CHECK(ep))
{
- NRFX_CRITICAL_SECTION_ENTER();
- m_ep_ready &= ~(1U << ep2bit(ep));
- if (!NRF_USBD_EPISO_CHECK(ep))
- {
- nrf_usbd_epout_clear(NRF_USBD, ep);
- }
- NRFX_CRITICAL_SECTION_EXIT();
+ nrf_usbd_epout_clear(NRF_USBD, ep);
}
+ NRFX_CRITICAL_SECTION_EXIT();
}
#endif // NRFX_CHECK(NRFX_USBD_ENABLED)
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
index 76f0c87..2e1512d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/nrfx_usbd_errata.h
@@ -32,7 +32,6 @@
#ifndef NRFX_USBD_ERRATA_H__
#define NRFX_USBD_ERRATA_H__
-#include <stdbool.h>
#include <nrfx.h>
#include <nrf_erratas.h>
@@ -45,18 +44,6 @@
#define NRFX_USBD_ERRATA_ENABLE 1
#endif
-/* Errata: USBD: EPDATA event is not always generated. **/
-static inline bool nrfx_usbd_errata_104(void)
-{
- return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_104();
-}
-
-/* Errata: During setup read/write transfer USBD acknowledges setup stage without SETUP task. **/
-static inline bool nrfx_usbd_errata_154(void)
-{
- return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_154();
-}
-
/* Errata: ISO double buffering not functional. **/
static inline bool nrfx_usbd_errata_166(void)
{
@@ -81,10 +68,16 @@ static inline bool nrfx_usbd_errata_199(void)
return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_199();
}
-/* Errata: SIZE.EPOUT not writable. **/
-static inline bool nrfx_usbd_errata_200(void)
+/* Errata: Device remains in SUSPEND too long. */
+static inline bool nrfx_usbd_errata_211(void)
+{
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_211();
+}
+
+/* Errata: Unexpected behavior after reset. **/
+static inline bool nrfx_usbd_errata_223(void)
{
- return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_200();
+ return NRFX_USBD_ERRATA_ENABLE && nrf52_errata_223();
}
#endif // NRFX_USBD_ERRATA_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
index 2767b54..90e738e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
+++ b/hw/mcu/nordic/src/ext/nrfx/drivers/src/prs/nrfx_prs.h
@@ -51,7 +51,7 @@ extern "C" {
#define NRFX_PRS_BOX_0_ADDR NRF_SPI0
// SPI1, SPIS1, TWI1
#define NRFX_PRS_BOX_1_ADDR NRF_SPI1
-#elif defined(NRF52810_XXAA)
+#elif defined(NRF52805_XXAA) || defined(NRF52810_XXAA)
// TWIM0, TWIS0, TWI0
#define NRFX_PRS_BOX_0_ADDR NRF_TWIM0
// SPIM0, SPIS0, SPI0
@@ -65,6 +65,13 @@ extern "C" {
#define NRFX_PRS_BOX_1_ADDR NRF_SPIM0
// UART0, UARTE0
#define NRFX_PRS_BOX_2_ADDR NRF_UART0
+#elif defined(NRF52820_XXAA)
+ // SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0
+ #define NRFX_PRS_BOX_0_ADDR NRF_SPIM0
+ // SPIM1, SPIS1, TWIM1, TWIS1, SPI1, TWI1
+ #define NRFX_PRS_BOX_1_ADDR NRF_SPIM1
+ // UARTE0, UART0
+ #define NRFX_PRS_BOX_2_ADDR NRF_UARTE0
#elif defined(NRF52832_XXAA) || defined(NRF52832_XXAB) || \
defined(NRF52833_XXAA) || defined(NRF52840_XXAA)
// SPIM0, SPIS0, TWIM0, TWIS0, SPI0, TWI0
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h
index 0b35fae..d42b8d1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_aar.h
@@ -269,10 +269,7 @@ NRF_STATIC_INLINE void nrf_aar_event_clear(NRF_AAR_Type * p_reg,
nrf_aar_event_t aar_event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event)) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)aar_event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)aar_event);
}
NRF_STATIC_INLINE uint32_t nrf_aar_event_address_get(NRF_AAR_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h
index b205a2e..928267f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_acl.h
@@ -33,12 +33,14 @@
#define NRF_ACL_H__
#include <nrfx.h>
+#include <hal/nrf_ficr.h>
#ifdef __cplusplus
extern "C" {
#endif
-#define NRF_ACL_REGION_SIZE_MAX (512 * 1024UL)
+#define NRF_ACL_REGION_SIZE_MAX \
+ (nrf_ficr_codepagesize_get(NRF_FICR) * nrf_ficr_codesize_get(NRF_FICR))
/**
* @defgroup nrf_acl_hal ACL HAL
@@ -113,9 +115,10 @@ NRF_STATIC_INLINE void nrf_acl_region_set(NRF_ACL_Type * p_reg,
nrf_acl_perm_t perm)
{
NRFX_ASSERT(region_id < ACL_REGIONS_COUNT);
- NRFX_ASSERT(address % NRF_FICR->CODEPAGESIZE == 0);
+ NRFX_ASSERT(address % nrf_ficr_codepagesize_get(NRF_FICR) == 0);
NRFX_ASSERT(size <= NRF_ACL_REGION_SIZE_MAX);
NRFX_ASSERT(size != 0);
+ NRFX_ASSERT(size % nrf_ficr_codepagesize_get(NRF_FICR) == 0);
p_reg->ACL[region_id].ADDR = address;
p_reg->ACL[region_id].SIZE = size;
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
index 189eca2..13adfb5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ccm.h
@@ -64,6 +64,12 @@ typedef enum
NRF_CCM_EVENT_ERROR = offsetof(NRF_CCM_Type, EVENTS_ERROR), ///< CCM error event.
} nrf_ccm_event_t;
+/** @brief Types of CCM shorts. */
+typedef enum
+{
+ NRF_CCM_SHORT_ENDKSGEN_CRYPT_MASK = CCM_SHORTS_ENDKSGEN_CRYPT_Msk, ///< Shortcut for starting encryption/decryption when the key-stream generation is complete.
+} nrf_ccm_short_mask_t;
+
/** @brief CCM interrupts. */
typedef enum
{
@@ -167,6 +173,33 @@ NRF_STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg,
nrf_ccm_event_t event);
/**
+ * @brief Function for enabling the specified shortcuts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be enabled.
+ */
+NRF_STATIC_INLINE void nrf_ccm_shorts_enable(NRF_CCM_Type * p_reg,
+ uint32_t mask);
+
+/**
+ * @brief Function for disabling the specified shortcuts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be disabled.
+ */
+NRF_STATIC_INLINE void nrf_ccm_shorts_disable(NRF_CCM_Type * p_reg,
+ uint32_t mask);
+
+/**
+ * @brief Function for setting the specified shortcuts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be set.
+ */
+NRF_STATIC_INLINE void nrf_ccm_shorts_set(NRF_CCM_Type * p_reg,
+ uint32_t mask);
+
+/**
* @brief Function for enabling specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -342,10 +375,7 @@ NRF_STATIC_INLINE void nrf_ccm_event_clear(NRF_CCM_Type * p_reg,
nrf_ccm_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_ccm_event_check(NRF_CCM_Type const * p_reg,
@@ -360,6 +390,25 @@ NRF_STATIC_INLINE uint32_t nrf_ccm_event_address_get(NRF_CCM_Type const * p_reg,
return ((uint32_t)p_reg + (uint32_t)event);
}
+
+NRF_STATIC_INLINE void nrf_ccm_shorts_enable(NRF_CCM_Type * p_reg,
+ uint32_t mask)
+{
+ p_reg->SHORTS |= mask;
+}
+
+NRF_STATIC_INLINE void nrf_ccm_shorts_disable(NRF_CCM_Type * p_reg,
+ uint32_t mask)
+{
+ p_reg->SHORTS &= ~(mask);
+}
+
+NRF_STATIC_INLINE void nrf_ccm_shorts_set(NRF_CCM_Type * p_reg,
+ uint32_t mask)
+{
+ p_reg->SHORTS = mask;
+}
+
NRF_STATIC_INLINE void nrf_ccm_int_enable(NRF_CCM_Type * p_reg, uint32_t mask)
{
p_reg->INTENSET = mask;
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
index 553e19b..3ec013f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_clock.h
@@ -113,23 +113,27 @@ extern "C" {
typedef enum
{
#if defined(CLOCK_LFCLKSRC_SRC_LFULP) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_LFCLK_LFULP = CLOCK_LFCLKSRC_SRC_LFULP, /**< Internal 32 kHz Ultra-low power oscillator. */
+ NRF_CLOCK_LFCLK_LFULP = CLOCK_LFCLKSRC_SRC_LFULP, /**< Internal 32 kHz Ultra-low power oscillator. */
#endif
+
#if defined(CLOCK_LFCLKSRC_SRC_RC) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
+ NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_RC, /**< Internal 32 kHz RC oscillator. */
#else
- NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_LFRC, /**< Internal 32 kHz RC oscillator. */
+ NRF_CLOCK_LFCLK_RC = CLOCK_LFCLKSRC_SRC_LFRC, /**< Internal 32 kHz RC oscillator. */
#endif
#if defined(CLOCK_LFCLKSRC_SRC_Xtal) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
+ NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
#else
- NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_LFXO, /**< External 32 kHz crystal. */
+ NRF_CLOCK_LFCLK_Xtal = CLOCK_LFCLKSRC_SRC_LFXO, /**< External 32 kHz crystal. */
#endif
#if defined(CLOCK_LFCLKSRC_SRC_Synth) || defined(__NRFX_DOXYGEN__)
- NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesizer from HFCLK system clock. */
+ NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth, /**< Internal 32 kHz synthesized from HFCLK system clock. */
+#elif defined(CLOCK_LFCLKSRC_SRC_LFSYNT)
+ NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_LFSYNT, /**< Internal 32 kHz synthesized from HFCLK system clock. */
#endif
+
#if defined(NRF_CLOCK_USE_EXTERNAL_LFCLK_SOURCES) || defined(__NRFX_DOXYGEN__)
/**
* External 32 kHz low swing signal. Used only with the LFCLKSRC register.
@@ -374,18 +378,19 @@ NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,
/**
* @brief Function for retrieving the state of the clock.
*
- * @param[in] p_reg Pointer to the structure of registers of the peripheral.
- * @param[in] domain Clock domain.
- * @param[out] clk_src Clock source that is running. Set to NULL if not needed.
- * Ignored for HFCLKAUDIO domain. Typecast it to @ref nrf_clock_lfclk_t for
- * LFCLK and @ref nrf_clock_hfclk_t for HFCLK and HFCLK192M.
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] domain Clock domain.
+ * @param[out] p_clk_src Pointer to clock source that is running. Set to NULL if not needed.
+ * Ignored for HFCLKAUDIO domain. Variable pointed by @p p_clk_src
+ * must be of either @ref nrf_clock_lfclk_t type for LFCLK
+ * or @ref nrf_clock_hfclk_t type for HFCLK and HFCLK192M.
*
* @retval false The clock is not running.
* @retval true The clock is running.
*/
NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
nrf_clock_domain_t domain,
- void * clk_src);
+ void * p_clk_src);
/**
* @brief Function for changing the low-frequency clock source.
@@ -406,7 +411,7 @@ NRF_STATIC_INLINE void nrf_clock_lf_src_set(NRF_CLOCK_Type * p_reg, nrf_clock_lf
* is the selected source for the low-frequency clock.
* @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
* is the selected source for the low-frequency clock.
- * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesizer from
+ * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from
* the HFCLK is the selected source for the low-frequency clock.
*/
NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const * p_reg);
@@ -422,7 +427,7 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(NRF_CLOCK_Type const *
* is the active source of the low-frequency clock.
* @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
* is the active source of the low-frequency clock.
- * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesizer from
+ * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from
* the HFCLK is the active source of the low-frequency clock.
*/
NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type const * p_reg);
@@ -437,7 +442,7 @@ NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(NRF_CLOCK_Type con
* is running and generating the LFCLK clock.
* @retval NRF_CLOCK_LFCLK_Xtal An external 32 kHz crystal oscillator
* is running and generating the LFCLK clock.
- * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesizer from
+ * @retval NRF_CLOCK_LFCLK_Synth The internal 32 kHz synthesized from
* the HFCLK is running and generating the LFCLK clock.
*/
NRF_STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(NRF_CLOCK_Type const * p_reg);
@@ -738,10 +743,7 @@ NRF_STATIC_INLINE uint32_t nrf_clock_event_address_get(NRF_CLOCK_Type const * p_
NRF_STATIC_INLINE void nrf_clock_event_clear(NRF_CLOCK_Type * p_reg, nrf_clock_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_clock_event_check(NRF_CLOCK_Type const * p_reg, nrf_clock_event_t event)
@@ -778,15 +780,16 @@ NRF_STATIC_INLINE bool nrf_clock_start_task_check(NRF_CLOCK_Type const * p_reg,
NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
nrf_clock_domain_t domain,
- void * clk_src)
+ void * p_clk_src)
{
switch (domain)
{
case NRF_CLOCK_DOMAIN_LFCLK:
- if (clk_src != NULL)
+ if (p_clk_src != NULL)
{
- (*(uint32_t *)clk_src) = ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
- >> CLOCK_LFCLKSTAT_SRC_Pos);
+ (*(nrf_clock_lfclk_t *)p_clk_src) =
+ (nrf_clock_lfclk_t)((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_SRC_Msk)
+ >> CLOCK_LFCLKSTAT_SRC_Pos);
}
if ((p_reg->LFCLKSTAT & CLOCK_LFCLKSTAT_STATE_Msk)
>> CLOCK_LFCLKSTAT_STATE_Pos)
@@ -795,10 +798,11 @@ NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
}
break;
case NRF_CLOCK_DOMAIN_HFCLK:
- if (clk_src != NULL)
+ if (p_clk_src != NULL)
{
- (*(uint32_t *)clk_src) = ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
- >> CLOCK_HFCLKSTAT_SRC_Pos);
+ (*(nrf_clock_hfclk_t *)p_clk_src) =
+ (nrf_clock_hfclk_t)((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_SRC_Msk)
+ >> CLOCK_HFCLKSTAT_SRC_Pos);
}
if ((p_reg->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk)
>> CLOCK_HFCLKSTAT_STATE_Pos)
@@ -808,10 +812,11 @@ NRF_STATIC_INLINE bool nrf_clock_is_running(NRF_CLOCK_Type const * p_reg,
break;
#if NRF_CLOCK_HAS_HFCLK192M
case NRF_CLOCK_DOMAIN_HFCLK192M:
- if (clk_src != NULL)
+ if (p_clk_src != NULL)
{
- (*(uint32_t *)clk_src) = ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
- >> CLOCK_HFCLK192MSTAT_SRC_Pos);
+ (*(nrf_clock_hfclk_t *)p_clk_src) =
+ (nrf_clock_hfclk_t)((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_SRC_Msk)
+ >> CLOCK_HFCLK192MSTAT_SRC_Pos);
}
if ((p_reg->HFCLK192MSTAT & CLOCK_HFCLK192MSTAT_STATE_Msk)
>> CLOCK_HFCLK192MSTAT_STATE_Pos)
diff --git a/hw/mcu/nordic/src/ext/nrfx/nrfx.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_common.h
similarity index 74%
copy from hw/mcu/nordic/src/ext/nrfx/nrfx.h
copy to hw/mcu/nordic/src/ext/nrfx/hal/nrf_common.h
index ac26166..063941c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/nrfx.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_common.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017 - 2020, Nordic Semiconductor ASA
+ * Copyright (c) 2020, Nordic Semiconductor ASA
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@@ -29,12 +29,32 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#ifndef NRFX_H__
-#define NRFX_H__
+#ifndef NRF_COMMON_H__
+#define NRF_COMMON_H__
-#include <nrfx_config.h>
-#include <drivers/nrfx_common.h>
-#include <nrfx_glue.h>
-#include <drivers/nrfx_errors.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
-#endif // NRFX_H__
+#ifndef NRFX_EVENT_READBACK_ENABLED
+#define NRFX_EVENT_READBACK_ENABLED 1
+#endif
+
+#ifndef NRF_DECLARE_ONLY
+
+NRF_STATIC_INLINE void nrf_event_readback(void * p_event_reg)
+{
+#if NRFX_CHECK(NRFX_EVENT_READBACK_ENABLED) && !defined(NRF51)
+ (void)*((volatile uint32_t *)(p_event_reg));
+#else
+ (void)p_event_reg;
+#endif
+}
+
+#endif // NRF_DECLARE_ONLY
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_COMMON_H__
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
index 3a00c48..8a0781e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_comp.h
@@ -48,18 +48,27 @@ extern "C" {
/** @brief COMP analog pin selection. */
typedef enum
{
- NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
- NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
- NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
- NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
- NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
- NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
- NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
+ NRF_COMP_INPUT_0 = COMP_PSEL_PSEL_AnalogInput0, /*!< AIN0 selected as analog input. */
+ NRF_COMP_INPUT_1 = COMP_PSEL_PSEL_AnalogInput1, /*!< AIN1 selected as analog input. */
+ NRF_COMP_INPUT_2 = COMP_PSEL_PSEL_AnalogInput2, /*!< AIN2 selected as analog input. */
+ NRF_COMP_INPUT_3 = COMP_PSEL_PSEL_AnalogInput3, /*!< AIN3 selected as analog input. */
+#if defined (COMP_PSEL_PSEL_AnalogInput4) || defined (__NRFX_DOXYGEN__)
+ NRF_COMP_INPUT_4 = COMP_PSEL_PSEL_AnalogInput4, /*!< AIN4 selected as analog input. */
+#endif
+#if defined (COMP_PSEL_PSEL_AnalogInput5) || defined (__NRFX_DOXYGEN__)
+ NRF_COMP_INPUT_5 = COMP_PSEL_PSEL_AnalogInput5, /*!< AIN5 selected as analog input. */
+#endif
+#if defined (COMP_PSEL_PSEL_AnalogInput6) || defined (__NRFX_DOXYGEN__)
+ NRF_COMP_INPUT_6 = COMP_PSEL_PSEL_AnalogInput6, /*!< AIN6 selected as analog input. */
+#endif
#if defined (COMP_PSEL_PSEL_AnalogInput7) || defined (__NRFX_DOXYGEN__)
- NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
+ NRF_COMP_INPUT_7 = COMP_PSEL_PSEL_AnalogInput7, /*!< AIN7 selected as analog input. */
#endif
#if defined (COMP_PSEL_PSEL_VddDiv2) || defined (__NRFX_DOXYGEN__)
- NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
+ NRF_COMP_VDD_DIV2 = COMP_PSEL_PSEL_VddDiv2, /*!< VDD/2 selected as analog input. */
+#endif
+#if defined (COMP_PSEL_PSEL_VddhDiv5) || defined (__NRFX_DOXYGEN__)
+ NRF_COMP_VDDH_DIV5 = COMP_PSEL_PSEL_VddhDiv5, /*!< VDDH/5 selected as analog input. */
#endif
} nrf_comp_input_t;
@@ -80,10 +89,18 @@ typedef enum
NRF_COMP_EXT_REF_1 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference1, /*!< Use AIN1 as external analog reference. */
NRF_COMP_EXT_REF_2 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference2, /*!< Use AIN2 as external analog reference. */
NRF_COMP_EXT_REF_3 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference3, /*!< Use AIN3 as external analog reference. */
+#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference4) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_4 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference4, /*!< Use AIN4 as external analog reference. */
+#endif
+#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference5) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_5 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference5, /*!< Use AIN5 as external analog reference. */
+#endif
+#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference6) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_6 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference6, /*!< Use AIN6 as external analog reference. */
+#endif
+#if defined (COMP_EXTREFSEL_EXTREFSEL_AnalogReference7) || defined (__NRFX_DOXYGEN__)
NRF_COMP_EXT_REF_7 = COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 /*!< Use AIN7 as external analog reference. */
+#endif
} nrf_comp_ext_ref_t;
/** @brief COMP THDOWN and THUP values that are used to calculate the threshold voltages VDOWN and VUP. */
@@ -463,10 +480,7 @@ NRF_STATIC_INLINE void nrf_comp_task_trigger(NRF_COMP_Type * p_reg, nrf_comp_tas
NRF_STATIC_INLINE void nrf_comp_event_clear(NRF_COMP_Type * p_reg, nrf_comp_event_t event)
{
*( (volatile uint32_t *)( (uint8_t *)p_reg + (uint32_t)event) ) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_comp_event_check(NRF_COMP_Type const * p_reg, nrf_comp_event_t event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
index e734e14..ec4f10d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ecb.h
@@ -178,10 +178,7 @@ NRF_STATIC_INLINE uint32_t nrf_ecb_task_address_get(NRF_ECB_Type const * p_reg,
NRF_STATIC_INLINE void nrf_ecb_event_clear(NRF_ECB_Type * p_reg, nrf_ecb_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_ecb_event_check(NRF_ECB_Type const * p_reg, nrf_ecb_event_t event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
index 8c5cdc2..bdeebea 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_egu.h
@@ -41,7 +41,7 @@ extern "C" {
/**
* @defgroup nrf_egu_hal EGU HAL
* @{
-* @ingroup nrf_swi_egu
+* @ingroup nrf_egu
* @brief Hardware access layer for managing the Event Generator Unit (EGU) peripheral.
*/
@@ -324,10 +324,7 @@ NRF_STATIC_INLINE void nrf_egu_event_clear(NRF_EGU_Type * p_reg, nrf_egu_event_t
{
NRFX_ASSERT(p_reg);
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)egu_event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)egu_event);
}
NRF_STATIC_INLINE uint32_t nrf_egu_event_address_get(NRF_EGU_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
index 6fcf5e6..05edf99 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpio.h
@@ -52,6 +52,10 @@ extern "C" {
#error "Not supported."
#endif
+#if defined(NRF52820_XXAA)
+#include <nrf_erratas.h>
+#endif
+
/**
* @defgroup nrf_gpio_hal GPIO HAL
* @{
@@ -139,9 +143,10 @@ typedef enum
/** @brief Enumerator used for selecting the MCU/Subsystem to control the specified pin. */
typedef enum
{
- NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
- NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
- NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
+ NRF_GPIO_PIN_MCUSEL_APP = GPIO_PIN_CNF_MCUSEL_AppMCU, ///< Pin controlled by Application MCU.
+ NRF_GPIO_PIN_MCUSEL_NETWORK = GPIO_PIN_CNF_MCUSEL_NetworkMCU, ///< Pin controlled by Network MCU.
+ NRF_GPIO_PIN_MCUSEL_PERIPHERAL = GPIO_PIN_CNF_MCUSEL_Peripheral, ///< Pin controlled by dedicated peripheral.
+ NRF_GPIO_PIN_MCUSEL_TND = GPIO_PIN_CNF_MCUSEL_TND, ///< Pin controlled by Trace and Debug Subsystem.
} nrf_gpio_pin_mcusel_t;
#endif
@@ -497,37 +502,57 @@ NRF_STATIC_INLINE void nrf_gpio_pin_latch_clear(uint32_t pin_number);
NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin_mcusel_t mcu);
#endif
+/**
+ * @brief Function for checking if provided pin is present on the MCU.
+ *
+ * @param[in] pin_number Number of the pin to be checked.
+ *
+ * @retval true Pin is present.
+ * @retval false Pin is not present.
+ */
+NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number);
+
+/**
+ * @brief Function for extracting port number and the relative pin number
+ * from the absolute pin number.
+ *
+ * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
+ * that is relative to the port.
+ *
+ * @return Port number.
+*/
+NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin);
+
#ifndef NRF_DECLARE_ONLY
/**
* @brief Function for extracting port and the relative pin number from the absolute pin number.
*
- * @param[in,out] p_pin Pointer to the absolute pin number overriden by the pin number that is relative to the port.
+ * @param[in,out] p_pin Pointer to the absolute pin number overridden by the pin number
+ * that is relative to the port.
*
* @return Pointer to port register set.
*/
NRF_STATIC_INLINE NRF_GPIO_Type * nrf_gpio_pin_port_decode(uint32_t * p_pin)
{
- NRFX_ASSERT(*p_pin < NUMBER_OF_PINS);
-#if (GPIO_COUNT == 1)
- return NRF_P0;
-#else
- if (*p_pin < P0_PIN_NUM)
- {
- return NRF_P0;
- }
- else
+ NRFX_ASSERT(nrf_gpio_pin_present_check(*p_pin));
+
+ switch (nrf_gpio_pin_port_number_extract(p_pin))
{
- *p_pin = *p_pin & (P0_PIN_NUM - 1);
- return NRF_P1;
- }
+ default:
+ NRFX_ASSERT(0);
+#if defined(P0_FEATURE_PINS_PRESENT)
+ case 0: return NRF_P0;
+#endif
+#if defined(P1_FEATURE_PINS_PRESENT)
+ case 1: return NRF_P1;
#endif
+ }
}
NRF_STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
{
- /*lint -e{845} // A zero has been given as right argument to operator '|'" */
for (; pin_range_start <= pin_range_end; pin_range_start++)
{
nrf_gpio_cfg_output(pin_range_start);
@@ -539,7 +564,6 @@ NRF_STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_st
uint32_t pin_range_end,
nrf_gpio_pin_pull_t pull_config)
{
- /*lint -e{845} // A zero has been given as right argument to operator '|'" */
for (; pin_range_start <= pin_range_end; pin_range_start++)
{
nrf_gpio_cfg_input(pin_range_start, pull_config);
@@ -604,7 +628,6 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
{
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
- /*lint -e{845} // A zero has been given as right argument to operator '|'" */
uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
@@ -614,7 +637,6 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
NRF_STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
{
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
- /*lint -e{845} // A zero has been given as right argument to operator '|'" */
uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
reg->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
@@ -639,7 +661,6 @@ NRF_STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number,
nrf_gpio_pin_sense_t sense_config)
{
NRF_GPIO_Type * reg = nrf_gpio_pin_port_decode(&pin_number);
- /*lint -e{845} // A zero has been given as right argument to operator '|'" */
uint32_t cnf = reg->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
reg->PIN_CNF[pin_number] = cnf | (sense_config << GPIO_PIN_CNF_SENSE_Pos);
@@ -884,6 +905,49 @@ NRF_STATIC_INLINE void nrf_gpio_pin_mcu_select(uint32_t pin_number, nrf_gpio_pin
}
#endif
+NRF_STATIC_INLINE bool nrf_gpio_pin_present_check(uint32_t pin_number)
+{
+ uint32_t port = pin_number >> 5;
+ uint32_t mask = 0;
+
+ switch (port)
+ {
+#ifdef P0_FEATURE_PINS_PRESENT
+ case 0:
+ mask = P0_FEATURE_PINS_PRESENT;
+#if defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
+ /* Allow use of the following additional GPIOs that are connected to LEDs and buttons
+ * on the nRF52833 DK:
+ * - P0.11 - Button 1
+ * - P0.12 - Button 2
+ * - P0.13 - LED 1
+ * - P0.24 - Button 3
+ * - P0.25 - Button 4
+ */
+ mask |= 0x03003800;
+#endif // defined(NRF52820_XXAA) && defined(DEVELOP_IN_NRF52833)
+ break;
+#endif
+#ifdef P1_FEATURE_PINS_PRESENT
+ case 1:
+ mask = P1_FEATURE_PINS_PRESENT;
+ break;
+#endif
+ }
+
+ pin_number &= 0x1F;
+
+ return (mask & (1UL << pin_number)) ? true : false;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_gpio_pin_port_number_extract(uint32_t * p_pin)
+{
+ uint32_t pin_number = *p_pin;
+ *p_pin = pin_number & 0x1F;
+
+ return pin_number >> 5;
+}
+
#endif // NRF_DECLARE_ONLY
/** @} */
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
index 8f3321d..2a0d52e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_gpiote.h
@@ -441,10 +441,7 @@ NRF_STATIC_INLINE bool nrf_gpiote_event_check(NRF_GPIOTE_Type const * p_reg,
NRF_STATIC_INLINE void nrf_gpiote_event_clear(NRF_GPIOTE_Type * p_reg, nrf_gpiote_event_t event)
{
*((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event)) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_address_get(p_reg, event));
- (void)dummy;
-#endif
+ nrf_event_readback((void *)nrf_gpiote_event_address_get(p_reg, event));
}
NRF_STATIC_INLINE uint32_t nrf_gpiote_event_address_get(NRF_GPIOTE_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
index da71bc6..7744ebb 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_i2s.h
@@ -38,6 +38,10 @@
extern "C" {
#endif
+#ifndef NRF_I2S0
+#define NRF_I2S0 NRF_I2S
+#endif
+
/**
* @defgroup nrf_i2s_hal I2S HAL
* @{
@@ -360,6 +364,51 @@ NRF_STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
uint32_t sdin_pin);
/**
+ * @brief Function for getting the SCK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SCK pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg);
+
+/**
+ * @brief Function for getting the LRCK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return LRCK pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MCK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MCK pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg);
+
+/**
+ * @brief Function for getting the SDOUT pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SDOUT pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg);
+
+/**
+ * @brief Function for getting the SDIN pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SDIN pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg);
+
+/**
* @brief Function for setting the I2S peripheral configuration.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -476,10 +525,7 @@ NRF_STATIC_INLINE void nrf_i2s_event_clear(NRF_I2S_Type * p_reg,
nrf_i2s_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_i2s_event_check(NRF_I2S_Type const * p_reg,
@@ -563,6 +609,31 @@ NRF_STATIC_INLINE void nrf_i2s_pins_set(NRF_I2S_Type * p_reg,
p_reg->PSEL.SDIN = sdin_pin;
}
+NRF_STATIC_INLINE uint32_t nrf_i2s_sck_pin_get(NRF_I2S_Type const * p_reg)
+{
+ return p_reg->PSEL.SCK;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_i2s_lrck_pin_get(NRF_I2S_Type const * p_reg)
+{
+ return p_reg->PSEL.LRCK;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_i2s_mck_pin_get(NRF_I2S_Type const * p_reg)
+{
+ return p_reg->PSEL.MCK;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_i2s_sdout_pin_get(NRF_I2S_Type const * p_reg)
+{
+ return p_reg->PSEL.SDOUT;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_i2s_sdin_pin_get(NRF_I2S_Type const * p_reg)
+{
+ return p_reg->PSEL.SDIN;
+}
+
NRF_STATIC_INLINE bool nrf_i2s_configure(NRF_I2S_Type * p_reg,
nrf_i2s_mode_t mode,
nrf_i2s_format_t format,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
index 777f6ea..a0e976c 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_lpcomp.h
@@ -406,10 +406,7 @@ NRF_STATIC_INLINE void nrf_lpcomp_task_trigger(NRF_LPCOMP_Type * p_reg, nrf_lpco
NRF_STATIC_INLINE void nrf_lpcomp_event_clear(NRF_LPCOMP_Type * p_reg, nrf_lpcomp_event_t event)
{
*( (volatile uint32_t *)( (uint8_t *)p_reg + (uint32_t)event) ) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_lpcomp_event_check(NRF_LPCOMP_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h
index 4fbf445..b25f1e2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_mwu.h
@@ -287,10 +287,7 @@ NRF_STATIC_INLINE void nrf_mwu_event_clear(NRF_MWU_Type * p_reg,
nrf_mwu_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE uint32_t nrf_mwu_event_address_get(NRF_MWU_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
index f03d01d..2b0f655 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_nfct.h
@@ -407,11 +407,11 @@ NRF_STATIC_INLINE void nrf_nfct_int_disable(NRF_NFCT_Type * p_reg, uint32_t mask
NRF_STATIC_INLINE void nrf_nfct_mod_ctrl_pin_set(NRF_NFCT_Type * p_reg, uint32_t mod_ctrl_pin);
/**
- * @brief Function for getting the modulation control pin.
+ * @brief Function for getting the modulation control pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return Modulation control pin number.
+ * @return Modulation control pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_nfct_mod_ctrl_pin_get(NRF_NFCT_Type const * p_reg);
#endif // defined(NFCT_MODULATIONPSEL_PIN_Msk) || defined(__NRFX_DOXYGEN__)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
index b8545ff..0a36766 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pdm.h
@@ -342,6 +342,24 @@ NRF_STATIC_INLINE void nrf_pdm_psel_connect(NRF_PDM_Type * p_reg,
uint32_t psel_din);
/**
+ * @brief Function for getting the CLK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return CLK pin selection;
+ */
+NRF_STATIC_INLINE uint32_t nrf_pdm_clk_pin_get(NRF_PDM_Type const * p_reg);
+
+/**
+ * @brief Function for getting the DIN pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return DIN pin selection;
+ */
+NRF_STATIC_INLINE uint32_t nrf_pdm_din_pin_get(NRF_PDM_Type const * p_reg);
+
+/**
* @brief Function for disconnecting the PDM pins.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -431,10 +449,7 @@ NRF_STATIC_INLINE bool nrf_pdm_event_check(NRF_PDM_Type const * p_reg, nrf_pdm_e
NRF_STATIC_INLINE void nrf_pdm_event_clear(NRF_PDM_Type * p_reg, nrf_pdm_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE uint32_t nrf_pdm_event_address_get(NRF_PDM_Type const * p_reg,
@@ -537,6 +552,16 @@ NRF_STATIC_INLINE void nrf_pdm_psel_connect(NRF_PDM_Type * p_reg,
p_reg->PSEL.DIN = psel_din;
}
+NRF_STATIC_INLINE uint32_t nrf_pdm_clk_pin_get(NRF_PDM_Type const * p_reg)
+{
+ return p_reg->PSEL.CLK;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_pdm_din_pin_get(NRF_PDM_Type const * p_reg)
+{
+ return p_reg->PSEL.DIN;
+}
+
NRF_STATIC_INLINE void nrf_pdm_psel_disconnect(NRF_PDM_Type * p_reg)
{
p_reg->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
index 830d0b5..d475608 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_power.h
@@ -33,6 +33,7 @@
#define NRF_POWER_H__
#include <nrfx.h>
+#include <nrf_erratas.h>
#ifdef __cplusplus
extern "C" {
@@ -199,8 +200,12 @@ typedef enum
{
NRF_POWER_RAMBLOCK0 = POWER_RAMSTATUS_RAMBLOCK0_Pos,
NRF_POWER_RAMBLOCK1 = POWER_RAMSTATUS_RAMBLOCK1_Pos,
+#if defined(POWER_RAMSTATUS_RAMBLOCK2_Pos) || defined(__NRFX_DOXYGEN__)
NRF_POWER_RAMBLOCK2 = POWER_RAMSTATUS_RAMBLOCK2_Pos,
+#endif
+#if defined(POWER_RAMSTATUS_RAMBLOCK3_Pos) || defined(__NRFX_DOXYGEN__)
NRF_POWER_RAMBLOCK3 = POWER_RAMSTATUS_RAMBLOCK3_Pos
+#endif
} nrf_power_ramblock_t;
/**
@@ -212,8 +217,12 @@ typedef enum
{
NRF_POWER_RAMBLOCK0_MASK = POWER_RAMSTATUS_RAMBLOCK0_Msk,
NRF_POWER_RAMBLOCK1_MASK = POWER_RAMSTATUS_RAMBLOCK1_Msk,
+#if defined(POWER_RAMSTATUS_RAMBLOCK2_Msk) || defined(__NRFX_DOXYGEN__)
NRF_POWER_RAMBLOCK2_MASK = POWER_RAMSTATUS_RAMBLOCK2_Msk,
+#endif
+#if defined(POWER_RAMSTATUS_RAMBLOCK3_Msk) || defined(__NRFX_DOXYGEN__)
NRF_POWER_RAMBLOCK3_MASK = POWER_RAMSTATUS_RAMBLOCK3_Msk
+#endif
} nrf_power_ramblock_mask_t;
#endif // defined(POWER_RAMSTATUS_RAMBLOCK0_Msk) || defined(__NRFX_DOXYGEN__)
@@ -868,10 +877,7 @@ NRF_STATIC_INLINE uint32_t nrf_power_task_address_get(NRF_POWER_Type const * p_r
NRF_STATIC_INLINE void nrf_power_event_clear(NRF_POWER_Type * p_reg, nrf_power_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_power_event_check(NRF_POWER_Type const * p_reg, nrf_power_event_t event)
@@ -1141,6 +1147,11 @@ NRF_STATIC_INLINE uint32_t nrf_power_rampower_mask_get(NRF_POWER_Type const * p_
#if NRF_POWER_HAS_DCDCEN_VDDH
NRF_STATIC_INLINE void nrf_power_dcdcen_vddh_set(NRF_POWER_Type * p_reg, bool enable)
{
+ if (nrf52_errata_197())
+ {
+ // Workaround for anomaly 197 "POWER: DCDC of REG0 not functional".
+ *(volatile uint32_t *)0x40000638ul = 1ul;
+ }
p_reg->DCDCEN0 = (enable ? POWER_DCDCEN0_DCDCEN_Enabled : POWER_DCDCEN0_DCDCEN_Disabled) <<
POWER_DCDCEN0_DCDCEN_Pos;
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
index 85fa32d..2284c35 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_ppi.h
@@ -59,12 +59,14 @@ typedef enum
NRF_PPI_CHANNEL7 = PPI_CHEN_CH7_Pos, /**< Channel 7. */
NRF_PPI_CHANNEL8 = PPI_CHEN_CH8_Pos, /**< Channel 8. */
NRF_PPI_CHANNEL9 = PPI_CHEN_CH9_Pos, /**< Channel 9. */
+#if (PPI_CH_NUM > 10) || defined(__NRFX_DOXYGEN__)
NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
+#endif
#if (PPI_CH_NUM > 16) || defined(__NRFX_DOXYGEN__)
NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
@@ -546,6 +548,7 @@ NRF_STATIC_INLINE uint32_t nrf_ppi_task_group_disable_address_get(NRF_PPI_Type c
NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type const * p_reg,
uint8_t index)
{
+ (void)p_reg;
NRFX_ASSERT(index < PPI_GROUP_NUM);
return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].EN);
}
@@ -553,6 +556,7 @@ NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_enable_task_get(NRF_PPI_Type cons
NRF_STATIC_INLINE nrf_ppi_task_t nrf_ppi_group_disable_task_get(NRF_PPI_Type const * p_reg,
uint8_t index)
{
+ (void)p_reg;
NRFX_ASSERT(index < PPI_GROUP_NUM);
return (nrf_ppi_task_t)NRFX_OFFSETOF(NRF_PPI_Type, TASKS_CHG[index].DIS);
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
index 1f017d1..b9fb052 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_pwm.h
@@ -428,6 +428,16 @@ NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
/**
+ * @brief Function for getting pin selection associated with specified PWM output channel.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] channel PWM output channel.
+ *
+ * @return Pin selection associated with specified PWM output channel.
+ */
+NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel);
+
+/**
* @brief Function for configuring the PWM peripheral.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -542,10 +552,7 @@ NRF_STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_reg,
nrf_pwm_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_reg,
@@ -645,6 +652,12 @@ NRF_STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_reg,
}
}
+NRF_STATIC_INLINE uint32_t nrf_pwm_pin_get(NRF_PWM_Type const * p_reg, uint8_t channel)
+{
+ NRFX_ASSERT(channel < NRF_PWM_CHANNEL_COUNT);
+ return p_reg->PSEL.OUT[channel];
+}
+
NRF_STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_reg,
nrf_pwm_clk_t base_clock,
nrf_pwm_mode_t mode,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
index 8ae72f2..363d122 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qdec.h
@@ -204,8 +204,23 @@ NRF_STATIC_INLINE void nrf_qdec_dbfen_disable(NRF_QDEC_Type * p_reg);
NRF_STATIC_INLINE uint32_t nrf_qdec_dbfen_get(NRF_QDEC_Type const * p_reg);
/**
+ * @brief Function for configuring QDEC pins.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] phase_a_pin Phase A pin number.
+ * @param[in] phase_b_pin Phase B pin number.
+ * @param[in] led_pin LED pin number.
+ */
+NRF_STATIC_INLINE void nrf_qdec_pins_set(NRF_QDEC_Type * p_reg,
+ uint32_t phase_a_pin,
+ uint32_t phase_b_pin,
+ uint32_t led_pin);
+
+/**
* @brief Function for assigning QDEC pins.
*
+ * @note This function is deprecated. Use @ref nrf_qdec_pins_set instead.
+ *
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
* @param[in] psela Pin number.
* @param[in] pselb Pin number.
@@ -217,6 +232,33 @@ NRF_STATIC_INLINE void nrf_qdec_pio_assign(NRF_QDEC_Type * p_reg,
uint32_t pselled);
/**
+ * @brief Function for getting the Phase A pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Phase A pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_qdec_phase_a_pin_get(NRF_QDEC_Type const * p_reg);
+
+/**
+ * @brief Function for getting the Phase B pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return Phase B pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_qdec_phase_b_pin_get(NRF_QDEC_Type const * p_reg);
+
+/**
+ * @brief Function for getting the LED pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return LED pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_qdec_led_pin_get(NRF_QDEC_Type const * p_reg);
+
+/**
* @brief Function for setting the specified QDEC task.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -463,27 +505,62 @@ NRF_STATIC_INLINE uint32_t nrf_qdec_dbfen_get(NRF_QDEC_Type const * p_reg)
return p_reg->DBFEN;
}
+NRF_STATIC_INLINE void nrf_qdec_pins_set(NRF_QDEC_Type * p_reg,
+ uint32_t phase_a_pin,
+ uint32_t phase_b_pin,
+ uint32_t led_pin)
+{
+#if defined(QDEC_PSEL_A_CONNECT_Pos)
+ p_reg->PSEL.A = phase_a_pin;
+#else
+ p_reg->PSELA = phase_a_pin;
+#endif
+
+#if defined(QDEC_PSEL_B_CONNECT_Pos)
+ p_reg->PSEL.B = phase_b_pin;
+#else
+ p_reg->PSELB = phase_b_pin;
+#endif
+
+#if defined(QDEC_PSEL_LED_CONNECT_Pos)
+ p_reg->PSEL.LED = led_pin;
+#else
+ p_reg->PSELLED = led_pin;
+#endif
+}
+
NRF_STATIC_INLINE void nrf_qdec_pio_assign(NRF_QDEC_Type * p_reg,
uint32_t psela,
uint32_t pselb,
uint32_t pselled)
{
+ nrf_qdec_pins_set(p_reg, psela, pselb, pselled);
+}
+
+NRF_STATIC_INLINE uint32_t nrf_qdec_phase_a_pin_get(NRF_QDEC_Type const * p_reg)
+{
#if defined(QDEC_PSEL_A_CONNECT_Pos)
- p_reg->PSEL.A = psela;
+ return p_reg->PSEL.A;
#else
- p_reg->PSELA = psela;
+ return p_reg->PSELA;
#endif
+}
+NRF_STATIC_INLINE uint32_t nrf_qdec_phase_b_pin_get(NRF_QDEC_Type const * p_reg)
+{
#if defined(QDEC_PSEL_B_CONNECT_Pos)
- p_reg->PSEL.B = pselb;
+ return p_reg->PSEL.B;
#else
- p_reg->PSELB = pselb;
+ return p_reg->PSELB;
#endif
+}
+NRF_STATIC_INLINE uint32_t nrf_qdec_led_pin_get(NRF_QDEC_Type const * p_reg)
+{
#if defined(QDEC_PSEL_LED_CONNECT_Pos)
- p_reg->PSEL.LED = pselled;
+ return p_reg->PSEL.LED;
#else
- p_reg->PSELLED = pselled;
+ return p_reg->PSELLED;
#endif
}
@@ -501,10 +578,7 @@ NRF_STATIC_INLINE uint32_t nrf_qdec_task_address_get(NRF_QDEC_Type const * p_reg
NRF_STATIC_INLINE void nrf_qdec_event_clear(NRF_QDEC_Type * p_reg, nrf_qdec_event_t event)
{
*( (volatile uint32_t *)( (uint8_t *)p_reg + (uint32_t)event) ) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_qdec_event_check(NRF_QDEC_Type const * p_reg, nrf_qdec_event_t event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
index 69eca9a..a628334 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_qspi.h
@@ -33,6 +33,7 @@
#define NRF_QSPI_H__
#include <nrfx.h>
+#include <nrf_erratas.h>
#ifdef __cplusplus
extern "C" {
@@ -66,6 +67,13 @@ extern "C" {
#define NRF_QSPI_HAS_DMA_ENC 0
#endif
+#if defined(QSPI_IFCONFIG1_SPIMODE_MODE3) || defined(__NRFX_DOXYGEN__)
+/** @brief Symbol indicating whether support for QSPI mode 1 is present. */
+#define NRF_QSPI_HAS_MODE_1 1
+#else
+#define NRF_QSPI_HAS_MODE_1 0
+#endif
+
#if defined(NRF53_SERIES) || defined(__NRFX_DOXYGEN__)
/** @brief Value representing QSPI base clock frequency. */
#define NRF_QSPI_BASE_CLOCK_FREQ 96000000uL
@@ -177,7 +185,9 @@ typedef enum
typedef enum
{
NRF_QSPI_MODE_0 = QSPI_IFCONFIG1_SPIMODE_MODE0, /**< Mode 0 (CPOL=0, CPHA=0). */
+#if NRF_QSPI_HAS_MODE_1
NRF_QSPI_MODE_1 = QSPI_IFCONFIG1_SPIMODE_MODE3 /**< Mode 1 (CPOL=1, CPHA=1). */
+#endif
} nrf_qspi_spi_mode_t;
/** @brief Addressing configuration mode. */
@@ -665,9 +675,11 @@ NRF_STATIC_INLINE void nrf_qspi_enable(NRF_QSPI_Type * p_reg)
NRF_STATIC_INLINE void nrf_qspi_disable(NRF_QSPI_Type * p_reg)
{
- // Workaround for nRF52840 anomaly 122: Current consumption is too high.
- *(volatile uint32_t *)0x40029054ul = 1ul;
-
+ if (nrf52_errata_122())
+ {
+ // Workaround for anomaly 122: "QSPI: QSPI uses current after being disabled".
+ *(volatile uint32_t *)0x40029054ul = 1ul;
+ }
p_reg->ENABLE = (QSPI_ENABLE_ENABLE_Disabled << QSPI_ENABLE_ENABLE_Pos);
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
index d3e087d..8965d8b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_radio.h
@@ -530,7 +530,9 @@ NRF_STATIC_INLINE uint8_t nrf_radio_dai_get(NRF_RADIO_Type const * p_reg);
* @retval 1 The payload is greater than PCNF1.MAXLEN.
*/
NRF_STATIC_INLINE uint8_t nrf_radio_pdustat_get(NRF_RADIO_Type const * p_reg);
+#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__)
+#if defined(RADIO_PDUSTAT_CISTAT_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for getting status on what rate packet is received with in Long Range.
*
@@ -540,7 +542,7 @@ NRF_STATIC_INLINE uint8_t nrf_radio_pdustat_get(NRF_RADIO_Type const * p_reg);
* @retval 1 The frame is received at 500kbps.
*/
NRF_STATIC_INLINE uint8_t nrf_radio_cistat_get(NRF_RADIO_Type const * p_reg);
-#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk) || defined(__NRFX_DOXYGEN__)
+#endif // defined(RADIO_PDUSTAT_CISTAT_Msk) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for setting packet pointer to given location in memory.
@@ -1051,10 +1053,7 @@ NRF_STATIC_INLINE uint32_t nrf_radio_task_address_get(NRF_RADIO_Type const * p_r
NRF_STATIC_INLINE void nrf_radio_event_clear(NRF_RADIO_Type * p_reg, nrf_radio_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_radio_event_check(NRF_RADIO_Type const * p_reg, nrf_radio_event_t event)
@@ -1129,12 +1128,14 @@ NRF_STATIC_INLINE uint8_t nrf_radio_pdustat_get(NRF_RADIO_Type const * p_reg)
{
return (uint8_t)(p_reg->PDUSTAT & RADIO_PDUSTAT_PDUSTAT_Msk);
}
+#endif
+#if defined(RADIO_PDUSTAT_CISTAT_Msk)
NRF_STATIC_INLINE uint8_t nrf_radio_cistat_get(NRF_RADIO_Type const * p_reg)
{
return (uint8_t)((p_reg->PDUSTAT & RADIO_PDUSTAT_CISTAT_Msk) >> RADIO_PDUSTAT_CISTAT_Pos);
}
-#endif // defined(RADIO_PDUSTAT_PDUSTAT_Msk)
+#endif
NRF_STATIC_INLINE void nrf_radio_packetptr_set(NRF_RADIO_Type * p_reg, void const * p_packet)
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h
index b9292c0..a9e83ac 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_reset.h
@@ -38,6 +38,20 @@
extern "C" {
#endif
+#if defined(NRF5340_XXAA_NETWORK) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of Network core RESET functionality. */
+#define NRF_RESET_HAS_NETWORK 1
+#else
+#define NRF_RESET_HAS_NETWORK 0
+#endif
+
+#if defined(NRF5340_XXAA_APPLICATION) || defined(__NRFX_DOXYGEN__)
+/** @brief Presence of Application core RESET functionality. */
+#define NRF_RESET_HAS_APPLICATION 1
+#else
+#define NRF_RESET_HAS_APPLICATION 0
+#endif
+
/**
* @defgroup nrf_reset_hal RESET HAL
* @{
@@ -56,14 +70,18 @@ typedef enum
NRF_RESET_RESETREAS_OFF_MASK = RESET_RESETREAS_OFF_Msk, ///< Bit mask of OFF field.
NRF_RESET_RESETREAS_LPCOMP_MASK = RESET_RESETREAS_LPCOMP_Msk, ///< Bit mask of LPCOMP field.
NRF_RESET_RESETREAS_DIF_MASK = RESET_RESETREAS_DIF_Msk, ///< Bit mask of DIF field.
+#if NRF_RESET_HAS_NETWORK
NRF_RESET_RESETREAS_LSREQ_MASK = RESET_RESETREAS_LSREQ_Msk, ///< Bit mask of LSREQ field.
NRF_RESET_RESETREAS_LLOCKUP_MASK = RESET_RESETREAS_LLOCKUP_Msk, ///< Bit mask of LLOCKUP field.
NRF_RESET_RESETREAS_LDOG_MASK = RESET_RESETREAS_LDOG_Msk, ///< Bit mask of LDOG field.
NRF_RESET_RESETREAS_MFORCEOFF_MASK = RESET_RESETREAS_MFORCEOFF_Msk, ///< Bit mask of MFORCEOFF field.
+#endif
NRF_RESET_RESETREAS_NFC_MASK = RESET_RESETREAS_NFC_Msk, ///< Bit mask of NFC field.
NRF_RESET_RESETREAS_DOG1_MASK = RESET_RESETREAS_DOG1_Msk, ///< Bit mask of DOG1 field.
NRF_RESET_RESETREAS_VBUS_MASK = RESET_RESETREAS_VBUS_Msk, ///< Bit mask of VBUS field.
+#if NRF_RESET_HAS_NETWORK
NRF_RESET_RESETREAS_LCTRLAP_MASK = RESET_RESETREAS_LCTRLAP_Msk, ///< Bit mask of LCTRLAP field.
+#endif
} nrf_reset_resetreas_mask_t;
/**
@@ -88,6 +106,7 @@ NRF_STATIC_INLINE uint32_t nrf_reset_resetreas_get(NRF_RESET_Type const * p_reg)
*/
NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_t mask);
+#if NRF_RESET_HAS_APPLICATION
/**
* @brief Function for setting the force off signal for the Network core.
*
@@ -98,6 +117,7 @@ NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_
* False if the force off signal is to be released.
*/
NRF_STATIC_INLINE void nrf_reset_network_force_off(NRF_RESET_Type * p_reg, bool hold);
+#endif // NRF_RESET_HAS_APPLICATION
#ifndef NRF_DECLARE_ONLY
@@ -111,11 +131,13 @@ NRF_STATIC_INLINE void nrf_reset_resetreas_clear(NRF_RESET_Type * p_reg, uint32_
p_reg->RESETREAS = mask;
}
+#if NRF_RESET_HAS_APPLICATION
NRF_STATIC_INLINE void nrf_reset_network_force_off(NRF_RESET_Type * p_reg, bool hold)
{
p_reg->NETWORK.FORCEOFF = (hold ? RESET_NETWORK_FORCEOFF_FORCEOFF_Hold :
RESET_NETWORK_FORCEOFF_FORCEOFF_Release);
}
+#endif // NRF_RESET_HAS_APPLICATION
#endif // NRF_DECLARE_ONLY
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
index 26698e0..20c1c9d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rng.h
@@ -227,10 +227,7 @@ NRF_STATIC_INLINE uint32_t nrf_rng_event_address_get(NRF_RNG_Type const * p_reg,
NRF_STATIC_INLINE void nrf_rng_event_clear(NRF_RNG_Type * p_reg, nrf_rng_event_t rng_event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)rng_event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)rng_event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)rng_event);
}
NRF_STATIC_INLINE bool nrf_rng_event_check(NRF_RNG_Type const * p_reg, nrf_rng_event_t rng_event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
index 710b943..ebaf4e6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_rtc.h
@@ -352,10 +352,7 @@ NRF_STATIC_INLINE bool nrf_rtc_event_check(NRF_RTC_Type const * p_reg, nrf_rtc_e
NRF_STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_reg, nrf_rtc_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type const * p_reg)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
index fef39a3..2e662f5 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_saadc.h
@@ -650,10 +650,7 @@ NRF_STATIC_INLINE bool nrf_saadc_event_check(NRF_SAADC_Type const * p_reg, nrf_s
NRF_STATIC_INLINE void nrf_saadc_event_clear(NRF_SAADC_Type * p_reg, nrf_saadc_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE uint32_t nrf_saadc_event_address_get(NRF_SAADC_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
index 95df3d2..fd1871f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spi.h
@@ -188,6 +188,33 @@ NRF_STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
uint32_t miso_pin);
/**
+ * @brief Function for getting the SCK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SCK pin selection;
+ */
+NRF_STATIC_INLINE uint32_t nrf_spi_sck_pin_get(NRF_SPI_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MOSI pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MOSI pin selection;
+ */
+NRF_STATIC_INLINE uint32_t nrf_spi_mosi_pin_get(NRF_SPI_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MISO pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MISO pin selection;
+ */
+NRF_STATIC_INLINE uint32_t nrf_spi_miso_pin_get(NRF_SPI_Type const * p_reg);
+
+/**
* @brief Function for writing data to the SPI transmitter register.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -231,10 +258,7 @@ NRF_STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_reg,
nrf_spi_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type const * p_reg,
@@ -300,6 +324,33 @@ NRF_STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_reg,
#endif
}
+NRF_STATIC_INLINE uint32_t nrf_spi_sck_pin_get(NRF_SPI_Type const * p_reg)
+{
+#if defined(SPI_PSEL_SCK_CONNECT_Pos)
+ return p_reg->PSEL.SCK;
+#else
+ return p_reg->PSELSCK;
+#endif
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spi_mosi_pin_get(NRF_SPI_Type const * p_reg)
+{
+#if defined(SPI_PSEL_MOSI_CONNECT_Pos)
+ return p_reg->PSEL.MOSI;
+#else
+ return p_reg->PSELMOSI;
+#endif
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spi_miso_pin_get(NRF_SPI_Type const * p_reg)
+{
+#if defined(SPI_PSEL_MISO_CONNECT_Pos)
+ return p_reg->PSEL.MISO;
+#else
+ return p_reg->PSELMISO;
+#endif
+}
+
NRF_STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_reg, uint8_t data)
{
p_reg->TXD = data;
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
index a644f3e..c5a6a88 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spim.h
@@ -359,6 +359,33 @@ NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
uint32_t mosi_pin,
uint32_t miso_pin);
+/**
+ * @brief Function for getting the SCK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SCK pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MOSI pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MOSI pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MISO pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MISO pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg);
+
#if (NRF_SPIM_HW_CSN_PRESENT) || defined(__NRFX_DOXYGEN__)
/**
* @brief Function for configuring the SPIM hardware CSN pin.
@@ -393,6 +420,15 @@ NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
uint32_t dcx_pin);
/**
+ * @brief Function for getting the DCX pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return DCX pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg);
+
+/**
* @brief Function for configuring the number of command bytes.
*
* Maximum value available for dividing the transmitted bytes into command
@@ -554,10 +590,7 @@ NRF_STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_reg,
nrf_spim_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type const * p_reg,
@@ -656,6 +689,21 @@ NRF_STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_reg,
p_reg->PSEL.MISO = miso_pin;
}
+NRF_STATIC_INLINE uint32_t nrf_spim_sck_pin_get(NRF_SPIM_Type const * p_reg)
+{
+ return p_reg->PSEL.SCK;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spim_mosi_pin_get(NRF_SPIM_Type const * p_reg)
+{
+ return p_reg->PSEL.MOSI;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spim_miso_pin_get(NRF_SPIM_Type const * p_reg)
+{
+ return p_reg->PSEL.MISO;
+}
+
#if NRF_SPIM_HW_CSN_PRESENT
NRF_STATIC_INLINE void nrf_spim_csn_configure(NRF_SPIM_Type * p_reg,
uint32_t pin,
@@ -675,6 +723,11 @@ NRF_STATIC_INLINE void nrf_spim_dcx_pin_set(NRF_SPIM_Type * p_reg,
p_reg->PSELDCX = dcx_pin;
}
+NRF_STATIC_INLINE uint32_t nrf_spim_dcx_pin_get(NRF_SPIM_Type const * p_reg)
+{
+ return p_reg->PSELDCX;
+}
+
NRF_STATIC_INLINE void nrf_spim_dcx_cnt_set(NRF_SPIM_Type * p_reg,
uint32_t dcx_cnt)
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
index 7819b6b..18b692b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_spis.h
@@ -308,6 +308,42 @@ NRF_STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
uint32_t csn_pin);
/**
+ * @brief Function for getting the SCK pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SCK pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MOSI pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MOSI pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg);
+
+/**
+ * @brief Function for getting the MISO pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return MISO pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg);
+
+/**
+ * @brief Function for getting the CSN pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return CSN pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg);
+
+/**
* @brief Function for setting the transmit buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -430,10 +466,7 @@ NRF_STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_reg,
nrf_spis_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_reg,
@@ -547,6 +580,42 @@ NRF_STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_reg,
#endif
}
+NRF_STATIC_INLINE uint32_t nrf_spis_sck_pin_get(NRF_SPIS_Type const * p_reg)
+{
+#if defined (NRF51)
+ return p_reg->PSELSCK;
+#else
+ return p_reg->PSEL.SCK;
+#endif
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spis_mosi_pin_get(NRF_SPIS_Type const * p_reg)
+{
+#if defined (NRF51)
+ return p_reg->PSELMOSI;
+#else
+ return p_reg->PSEL.MOSI;
+#endif
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spis_miso_pin_get(NRF_SPIS_Type const * p_reg)
+{
+#if defined (NRF51)
+ return p_reg->PSELMISO;
+#else
+ return p_reg->PSEL.MISO;
+#endif
+}
+
+NRF_STATIC_INLINE uint32_t nrf_spis_csn_pin_get(NRF_SPIS_Type const * p_reg)
+{
+#if defined (NRF51)
+ return p_reg->PSELCSN;
+#else
+ return p_reg->PSEL.CSN;
+#endif
+}
+
NRF_STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_reg,
uint8_t const * p_buffer,
size_t length)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
index 56e1d43..e2aad0f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_temp.h
@@ -187,10 +187,7 @@ NRF_STATIC_INLINE uint32_t nrf_temp_event_address_get(NRF_TEMP_Type const * p_re
NRF_STATIC_INLINE void nrf_temp_event_clear(NRF_TEMP_Type * p_reg, nrf_temp_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_temp_event_check(NRF_TEMP_Type const * p_reg, nrf_temp_event_t event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
index d3cc5d6..eda7fe2 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_timer.h
@@ -76,7 +76,6 @@ extern "C" {
(bit_width == NRF_TIMER_BIT_WIDTH_32) : \
false))))
-#if (TIMER_COUNT > 3) || defined(__NRFX_DOXYGEN__)
/**
* @brief Macro for checking correctness of bit width configuration for the specified timer.
*
@@ -86,19 +85,26 @@ extern "C" {
* @retval true Timer instance supports the specified bit width resolution value.
* @retval false Timer instance does not support the specified bit width resolution value.
*/
-#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
- ((p_reg == NRF_TIMER0) && (TIMER_BIT_WIDTH_MAX(0, bit_width))) \
- || ((p_reg == NRF_TIMER1) && (TIMER_BIT_WIDTH_MAX(1, bit_width))) \
- || ((p_reg == NRF_TIMER2) && (TIMER_BIT_WIDTH_MAX(2, bit_width))) \
- || ((p_reg == NRF_TIMER3) && (TIMER_BIT_WIDTH_MAX(3, bit_width))) \
- || ((p_reg == NRF_TIMER4) && (TIMER_BIT_WIDTH_MAX(4, bit_width))) )
-
+#if (TIMER_COUNT == 3) || defined(__NRFX_DOXYGEN__)
+ #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
+ ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
+ || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
+ || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)))
+#elif (TIMER_COUNT == 4)
+ #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
+ ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
+ || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
+ || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) \
+ || ((p_reg == NRF_TIMER3) && TIMER_BIT_WIDTH_MAX(3, bit_width)))
+#elif (TIMER_COUNT == 5)
+ #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
+ ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
+ || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
+ || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) \
+ || ((p_reg == NRF_TIMER3) && TIMER_BIT_WIDTH_MAX(3, bit_width)) \
+ || ((p_reg == NRF_TIMER4) && TIMER_BIT_WIDTH_MAX(4, bit_width)))
#else
-#define NRF_TIMER_IS_BIT_WIDTH_VALID(p_reg, bit_width) ( \
- ((p_reg == NRF_TIMER0) && TIMER_BIT_WIDTH_MAX(0, bit_width)) \
- || ((p_reg == NRF_TIMER1) && TIMER_BIT_WIDTH_MAX(1, bit_width)) \
- || ((p_reg == NRF_TIMER2) && TIMER_BIT_WIDTH_MAX(2, bit_width)) )
-
+ #error "Not supported timer count"
#endif
/**
@@ -318,6 +324,15 @@ NRF_STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
uint32_t mask);
/**
+ * @brief Function for setting the specified shortcuts.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ * @param[in] mask Shortcuts to be set.
+ */
+NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg,
+ uint32_t mask);
+
+/**
* @brief Function for enabling the specified interrupts.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -557,10 +572,7 @@ NRF_STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_reg,
nrf_timer_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type const * p_reg,
@@ -587,6 +599,12 @@ NRF_STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_reg,
p_reg->SHORTS &= ~(mask);
}
+NRF_STATIC_INLINE void nrf_timer_shorts_set(NRF_TIMER_Type * p_reg,
+ uint32_t mask)
+{
+ p_reg->SHORTS = mask;
+}
+
NRF_STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_reg,
uint32_t mask)
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
index 5e37048..107c391 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twi.h
@@ -235,20 +235,20 @@ NRF_STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_reg,
uint32_t sda_pin);
/**
- * @brief Function for retrieving the SCL pin number.
+ * @brief Function for retrieving the SCL pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return SCL pin number.
+ * @return SCL pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_twi_scl_pin_get(NRF_TWI_Type const * p_reg);
/**
- * @brief Function for retrieving the SDA pin number.
+ * @brief Function for retrieving the SDA pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return SDA pin number.
+ * @return SDA pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_twi_sda_pin_get(NRF_TWI_Type const * p_reg);
@@ -324,10 +324,7 @@ NRF_STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_reg,
nrf_twi_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
index 04d7555..c5ed69b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twim.h
@@ -293,6 +293,24 @@ NRF_STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
uint32_t sda_pin);
/**
+ * @brief Function for retrieving the SCL pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SCL pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg);
+
+/**
+ * @brief Function for retrieving the SDA pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SDA pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg);
+
+/**
* @brief Function for setting the TWI master clock frequency.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -426,10 +444,7 @@ NRF_STATIC_INLINE void nrf_twim_event_clear(NRF_TWIM_Type * p_reg,
nrf_twim_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_twim_event_check(NRF_TWIM_Type const * p_reg,
@@ -521,6 +536,16 @@ NRF_STATIC_INLINE void nrf_twim_pins_set(NRF_TWIM_Type * p_reg,
p_reg->PSEL.SDA = sda_pin;
}
+NRF_STATIC_INLINE uint32_t nrf_twim_scl_pin_get(NRF_TWIM_Type const * p_reg)
+{
+ return p_reg->PSEL.SCL;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_twim_sda_pin_get(NRF_TWIM_Type const * p_reg)
+{
+ return p_reg->PSEL.SDA;
+}
+
NRF_STATIC_INLINE void nrf_twim_frequency_set(NRF_TWIM_Type * p_reg,
nrf_twim_frequency_t frequency)
{
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
index 2dffdaf..6b5d5c3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_twis.h
@@ -322,6 +322,24 @@ NRF_STATIC_INLINE void nrf_twis_disable(NRF_TWIS_Type * p_reg);
NRF_STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, uint32_t sda);
/**
+ * @brief Function for retrieving the SCL pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SCL pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_twis_scl_pin_get(NRF_TWIS_Type const * p_reg);
+
+/**
+ * @brief Function for retrieving the SDA pin selection.
+ *
+ * @param[in] p_reg Pointer to the structure of registers of the peripheral.
+ *
+ * @return SDA pin selection.
+ */
+NRF_STATIC_INLINE uint32_t nrf_twis_sda_pin_get(NRF_TWIS_Type const * p_reg);
+
+/**
* @brief Function for setting the receive buffer.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
@@ -547,10 +565,7 @@ NRF_STATIC_INLINE uint32_t nrf_twis_task_address_get(NRF_TWIS_Type const * p_reg
NRF_STATIC_INLINE void nrf_twis_event_clear(NRF_TWIS_Type * p_reg, nrf_twis_event_t event)
{
*(nrf_twis_getRegPtr(p_reg, (uint32_t)event)) = 0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_twis_event_check(NRF_TWIS_Type const * p_reg, nrf_twis_event_t event)
@@ -670,6 +685,16 @@ NRF_STATIC_INLINE void nrf_twis_pins_set(NRF_TWIS_Type * p_reg, uint32_t scl, ui
p_reg->PSEL.SDA = sda;
}
+NRF_STATIC_INLINE uint32_t nrf_twis_scl_pin_get(NRF_TWIS_Type const * p_reg)
+{
+ return p_reg->PSEL.SCL;
+}
+
+NRF_STATIC_INLINE uint32_t nrf_twis_sda_pin_get(NRF_TWIS_Type const * p_reg)
+{
+ return p_reg->PSEL.SDA;
+}
+
NRF_STATIC_INLINE void nrf_twis_rx_buffer_set(NRF_TWIS_Type * p_reg,
uint8_t * p_buf,
size_t length)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
index 2acc9e9..cbafa0a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uart.h
@@ -255,38 +255,38 @@ NRF_STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg,
NRF_STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg);
/**
- * @brief Function for getting TX pin.
+ * @brief Function for getting TX pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return TX pin number.
+ * @return TX pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type const * p_reg);
/**
- * @brief Function for getting RX pin.
+ * @brief Function for getting RX pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return RX pin number.
+ * @return RX pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type const * p_reg);
/**
- * @brief Function for getting RTS pin.
+ * @brief Function for getting RTS pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return RTS pin number.
+ * @return RTS pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type const * p_reg);
/**
- * @brief Function for getting CTS pin.
+ * @brief Function for getting CTS pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return CTS pin number.
+ * @return CTS pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type const * p_reg);
@@ -367,10 +367,7 @@ NRF_STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type * p_reg, nrf_uart_bau
NRF_STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type const * p_reg, nrf_uart_event_t event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
index ba79304..fd1848d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_uarte.h
@@ -335,38 +335,38 @@ NRF_STATIC_INLINE void nrf_uarte_txrx_pins_set(NRF_UARTE_Type * p_reg,
NRF_STATIC_INLINE void nrf_uarte_txrx_pins_disconnect(NRF_UARTE_Type * p_reg);
/**
- * @brief Function for getting TX pin.
+ * @brief Function for getting TX pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return TX pin number.
+ * @return TX pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uarte_tx_pin_get(NRF_UARTE_Type const * p_reg);
/**
- * @brief Function for getting RX pin.
+ * @brief Function for getting RX pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return RX pin number.
+ * @return RX pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uarte_rx_pin_get(NRF_UARTE_Type const * p_reg);
/**
- * @brief Function for getting RTS pin.
+ * @brief Function for getting RTS pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return RTS pin number.
+ * @return RTS pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uarte_rts_pin_get(NRF_UARTE_Type const * p_reg);
/**
- * @brief Function for getting CTS pin.
+ * @brief Function for getting CTS pin selection.
*
* @param[in] p_reg Pointer to the structure of registers of the peripheral.
*
- * @return CTS pin number.
+ * @return CTS pin selection.
*/
NRF_STATIC_INLINE uint32_t nrf_uarte_cts_pin_get(NRF_UARTE_Type const * p_reg);
@@ -469,10 +469,7 @@ NRF_STATIC_INLINE uint32_t nrf_uarte_rx_amount_get(NRF_UARTE_Type const * p_reg)
NRF_STATIC_INLINE void nrf_uarte_event_clear(NRF_UARTE_Type * p_reg, nrf_uarte_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_uarte_event_check(NRF_UARTE_Type const * p_reg,
diff --git a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
index 79f866c..8df6be8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
+++ b/hw/mcu/nordic/src/ext/nrfx/hal/nrf_wdt.h
@@ -317,10 +317,7 @@ NRF_STATIC_INLINE void nrf_wdt_task_trigger(NRF_WDT_Type * p_reg, nrf_wdt_task_t
NRF_STATIC_INLINE void nrf_wdt_event_clear(NRF_WDT_Type * p_reg, nrf_wdt_event_t event)
{
*((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
-#if __CORTEX_M == 0x04
- volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event));
- (void)dummy;
-#endif
+ nrf_event_readback((uint8_t *)p_reg + (uint32_t)event);
}
NRF_STATIC_INLINE bool nrf_wdt_event_check(NRF_WDT_Type const * p_reg, nrf_wdt_event_t event)
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s
index a697f61..12f949a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf51.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s
index 62da860..cf44298 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -30,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 4096
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -48,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 4096
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52805.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52805.s
index 2a5c5ff..bcbbfc4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52805.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52805.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -102,7 +102,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
- DCD 0 ; Reserved
+ DCD QDEC_IRQHandler
DCD 0 ; Reserved
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
@@ -281,6 +281,7 @@ Default_Handler PROC
EXPORT CCM_AAR_IRQHandler [WEAK]
EXPORT WDT_IRQHandler [WEAK]
EXPORT RTC1_IRQHandler [WEAK]
+ EXPORT QDEC_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
EXPORT SWI2_IRQHandler [WEAK]
@@ -304,6 +305,7 @@ ECB_IRQHandler
CCM_AAR_IRQHandler
WDT_IRQHandler
RTC1_IRQHandler
+QDEC_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
SWI2_IRQHandler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s
index 2f0984a..636e870 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52810.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s
index d2baa9c..93ec67f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52820.s
similarity index 91%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s
copy to hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52820.s
index d2baa9c..02d9a3b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52811.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52820.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -87,11 +87,11 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
- DCD TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
- DCD SPIM0_SPIS0_SPI0_IRQHandler
+ DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD 0 ; Reserved
DCD GPIOTE_IRQHandler
- DCD SAADC_IRQHandler
+ DCD 0 ; Reserved
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
@@ -106,14 +106,13 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD COMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
- DCD SWI2_IRQHandler
- DCD SWI3_IRQHandler
- DCD SWI4_IRQHandler
- DCD SWI5_IRQHandler
+ DCD SWI2_EGU2_IRQHandler
+ DCD SWI3_EGU3_IRQHandler
+ DCD SWI4_EGU4_IRQHandler
+ DCD SWI5_EGU5_IRQHandler
+ DCD TIMER3_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD PWM0_IRQHandler
- DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
@@ -124,6 +123,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
+ DCD USBD_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
@@ -267,10 +267,9 @@ Default_Handler PROC
EXPORT POWER_CLOCK_IRQHandler [WEAK]
EXPORT RADIO_IRQHandler [WEAK]
EXPORT UARTE0_UART0_IRQHandler [WEAK]
- EXPORT TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler [WEAK]
- EXPORT SPIM0_SPIS0_SPI0_IRQHandler [WEAK]
+ EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
+ EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
EXPORT GPIOTE_IRQHandler [WEAK]
- EXPORT SAADC_IRQHandler [WEAK]
EXPORT TIMER0_IRQHandler [WEAK]
EXPORT TIMER1_IRQHandler [WEAK]
EXPORT TIMER2_IRQHandler [WEAK]
@@ -285,19 +284,18 @@ Default_Handler PROC
EXPORT COMP_IRQHandler [WEAK]
EXPORT SWI0_EGU0_IRQHandler [WEAK]
EXPORT SWI1_EGU1_IRQHandler [WEAK]
- EXPORT SWI2_IRQHandler [WEAK]
- EXPORT SWI3_IRQHandler [WEAK]
- EXPORT SWI4_IRQHandler [WEAK]
- EXPORT SWI5_IRQHandler [WEAK]
- EXPORT PWM0_IRQHandler [WEAK]
- EXPORT PDM_IRQHandler [WEAK]
+ EXPORT SWI2_EGU2_IRQHandler [WEAK]
+ EXPORT SWI3_EGU3_IRQHandler [WEAK]
+ EXPORT SWI4_EGU4_IRQHandler [WEAK]
+ EXPORT SWI5_EGU5_IRQHandler [WEAK]
+ EXPORT TIMER3_IRQHandler [WEAK]
+ EXPORT USBD_IRQHandler [WEAK]
POWER_CLOCK_IRQHandler
RADIO_IRQHandler
UARTE0_UART0_IRQHandler
-TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
-SPIM0_SPIS0_SPI0_IRQHandler
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
GPIOTE_IRQHandler
-SAADC_IRQHandler
TIMER0_IRQHandler
TIMER1_IRQHandler
TIMER2_IRQHandler
@@ -312,12 +310,12 @@ QDEC_IRQHandler
COMP_IRQHandler
SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
-SWI2_IRQHandler
-SWI3_IRQHandler
-SWI4_IRQHandler
-SWI5_IRQHandler
-PWM0_IRQHandler
-PDM_IRQHandler
+SWI2_EGU2_IRQHandler
+SWI3_EGU3_IRQHandler
+SWI4_EGU4_IRQHandler
+SWI5_EGU5_IRQHandler
+TIMER3_IRQHandler
+USBD_IRQHandler
B .
ENDP
ALIGN
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52833.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52833.s
index a620996..0fa7e06 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52833.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52833.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s
index 1a1662d..c03c46f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf52840.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -30,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 16384
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -48,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 16384
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s
index d9eb6eb..c71ae35 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_application.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -30,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 16384
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -48,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 16384
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_network.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_network.s
index afd0a3c..04a8d0a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_network.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf5340_network.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -30,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 4096
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -48,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 4096
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
@@ -73,7 +73,7 @@ __Vectors DCD __initial_sp ; Top of Stack
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
- DCD SecureFault_Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
@@ -261,11 +261,6 @@ UsageFault_Handler\
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
-SecureFault_Handler\
- PROC
- EXPORT SecureFault_Handler [WEAK]
- B .
- ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf9160.s b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf9160.s
index 356a061..69f1e86 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf9160.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/arm_startup_nrf9160.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -30,7 +30,7 @@ Stack_Size EQU __STARTUP_CONFIG_STACK_SIZE
ELIF :DEF: __STACK_SIZE
Stack_Size EQU __STACK_SIZE
ELSE
-Stack_Size EQU 8192
+Stack_Size EQU 16384
ENDIF
IF :DEF: __STARTUP_CONFIG
@@ -48,7 +48,7 @@ Heap_Size EQU __STARTUP_CONFIG_HEAP_SIZE
ELIF :DEF: __HEAP_SIZE
Heap_Size EQU __HEAP_SIZE
ELSE
-Heap_Size EQU 8192
+Heap_Size EQU 16384
ENDIF
AREA HEAP, NOINIT, READWRITE, ALIGN=3
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/compiler_abstraction.h b/hw/mcu/nordic/src/ext/nrfx/mdk/compiler_abstraction.h
index 2c31bc8..77a495a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/compiler_abstraction.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/compiler_abstraction.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -35,6 +35,18 @@ POSSIBILITY OF SUCH DAMAGE.
/*lint ++flb "Enter library region" */
+#ifndef NRF_STRING_CONCATENATE_IMPL
+ #define NRF_STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
+#endif
+#ifndef NRF_STRING_CONCATENATE
+ #define NRF_STRING_CONCATENATE(lhs, rhs) NRF_STRING_CONCATENATE_IMPL(lhs, rhs)
+#endif
+#if __LINT__ == 1
+ #ifndef NRF_STATIC_ASSERT
+ #define NRF_STATIC_ASSERT(cond, msg)
+ #endif
+#endif
+
#if defined ( __CC_ARM )
#ifndef __ASM
@@ -62,6 +74,11 @@ POSSIBILITY OF SUCH DAMAGE.
#endif
#define GET_SP() __current_sp()
+
+ #ifndef NRF_STATIC_ASSERT
+ #define NRF_STATIC_ASSERT(cond, msg) \
+ ;enum { NRF_STRING_CONCATENATE(static_assert_on_line_, __LINE__) = 1 / (!!(cond)) }
+ #endif
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
@@ -91,6 +108,10 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __current_sp()
+ #ifndef NRF_STATIC_ASSERT
+ #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
+ #endif
+
#elif defined ( __ICCARM__ )
#ifndef __ASM
@@ -120,7 +141,11 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __get_SP()
-#elif defined ( __GNUC__ )
+ #ifndef NRF_STATIC_ASSERT
+ #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
+ #endif
+
+#elif defined ( __GNUC__ ) || defined ( __clang__ )
#ifndef __ASM
#define __ASM __asm
@@ -150,10 +175,15 @@ POSSIBILITY OF SUCH DAMAGE.
static inline unsigned int gcc_current_sp(void)
{
- register unsigned sp __ASM("sp");
- return sp;
+ unsigned int stack_pointer = 0;
+ __asm__ __volatile__ ("mov %0, sp" : "=r"(stack_pointer));
+ return stack_pointer;
}
+ #ifndef NRF_STATIC_ASSERT
+ #define NRF_STATIC_ASSERT(cond, msg) _Static_assert(cond, msg)
+ #endif
+
#elif defined ( __TASKING__ )
#ifndef __ASM
@@ -183,8 +213,28 @@ POSSIBILITY OF SUCH DAMAGE.
#define GET_SP() __get_MSP()
+ #ifndef NRF_STATIC_ASSERT
+ #define NRF_STATIC_ASSERT(cond, msg) static_assert(cond, msg)
+ #endif
+
#endif
+#define NRF_MDK_VERSION_ASSERT_AT_LEAST(major, minor, micro) \
+ NRF_STATIC_ASSERT( \
+ ( \
+ (major < MDK_MAJOR_VERSION) || \
+ (major == MDK_MAJOR_VERSION && minor < MDK_MINOR_VERSION) || \
+ (major == MDK_MAJOR_VERSION && minor == MDK_MINOR_VERSION && micro < MDK_MICRO_VERSION) \
+ ), "MDK version mismatch.")
+
+#define NRF_MDK_VERSION_ASSERT_EXACT(major, minor, micro) \
+ NRF_STATIC_ASSERT( \
+ ( \
+ (major != MDK_MAJOR_VERSION) || \
+ (major != MDK_MAJOR_VERSION) || \
+ (major != MDK_MAJOR_VERSION) \
+ ), "MDK version mismatch.")
+
/*lint --flb "Leave library region" */
#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
index 162db0c..4665eac 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf51.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -156,10 +156,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -174,6 +175,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
index 9e97163..1e9997f 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -39,7 +39,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
.equ Stack_Size, __STACK_SIZE
#else
.align 3
- .equ Stack_Size, 8192
+ .equ Stack_Size, 4096
#endif
.globl __StackTop
.globl __StackLimit
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 4096
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -222,10 +222,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -240,6 +241,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S
index 3e314c7..da82da7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52805.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -108,7 +108,7 @@ __isr_vector:
.long CCM_AAR_IRQHandler
.long WDT_IRQHandler
.long RTC1_IRQHandler
- .long 0 /*Reserved */
+ .long QDEC_IRQHandler
.long 0 /*Reserved */
.long SWI0_EGU0_IRQHandler
.long SWI1_EGU1_IRQHandler
@@ -222,10 +222,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -240,6 +241,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
@@ -380,6 +382,7 @@ Default_Handler:
IRQ CCM_AAR_IRQHandler
IRQ WDT_IRQHandler
IRQ RTC1_IRQHandler
+ IRQ QDEC_IRQHandler
IRQ SWI0_EGU0_IRQHandler
IRQ SWI1_EGU1_IRQHandler
IRQ SWI2_IRQHandler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
index 5bca5cd..dc84105 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52810.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -245,10 +245,11 @@ skip:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -263,6 +264,7 @@ skip:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
index ac7fd29..f6929fc 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -222,10 +222,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -240,6 +241,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52820.S
similarity index 93%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
copy to hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52820.S
index ac7fd29..8e4c2d8 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52811.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52820.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -93,11 +93,11 @@ __isr_vector:
.long POWER_CLOCK_IRQHandler
.long RADIO_IRQHandler
.long UARTE0_UART0_IRQHandler
- .long TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
- .long SPIM0_SPIS0_SPI0_IRQHandler
+ .long SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ .long SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
.long 0 /*Reserved */
.long GPIOTE_IRQHandler
- .long SAADC_IRQHandler
+ .long 0 /*Reserved */
.long TIMER0_IRQHandler
.long TIMER1_IRQHandler
.long TIMER2_IRQHandler
@@ -112,14 +112,13 @@ __isr_vector:
.long COMP_IRQHandler
.long SWI0_EGU0_IRQHandler
.long SWI1_EGU1_IRQHandler
- .long SWI2_IRQHandler
- .long SWI3_IRQHandler
- .long SWI4_IRQHandler
- .long SWI5_IRQHandler
+ .long SWI2_EGU2_IRQHandler
+ .long SWI3_EGU3_IRQHandler
+ .long SWI4_EGU4_IRQHandler
+ .long SWI5_EGU5_IRQHandler
+ .long TIMER3_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
- .long PWM0_IRQHandler
- .long PDM_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
@@ -130,6 +129,7 @@ __isr_vector:
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
+ .long USBD_IRQHandler
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
@@ -222,10 +222,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -240,6 +241,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
@@ -366,10 +368,9 @@ Default_Handler:
IRQ POWER_CLOCK_IRQHandler
IRQ RADIO_IRQHandler
IRQ UARTE0_UART0_IRQHandler
- IRQ TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
- IRQ SPIM0_SPIS0_SPI0_IRQHandler
+ IRQ SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ IRQ SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
IRQ GPIOTE_IRQHandler
- IRQ SAADC_IRQHandler
IRQ TIMER0_IRQHandler
IRQ TIMER1_IRQHandler
IRQ TIMER2_IRQHandler
@@ -384,11 +385,11 @@ Default_Handler:
IRQ COMP_IRQHandler
IRQ SWI0_EGU0_IRQHandler
IRQ SWI1_EGU1_IRQHandler
- IRQ SWI2_IRQHandler
- IRQ SWI3_IRQHandler
- IRQ SWI4_IRQHandler
- IRQ SWI5_IRQHandler
- IRQ PWM0_IRQHandler
- IRQ PDM_IRQHandler
+ IRQ SWI2_EGU2_IRQHandler
+ IRQ SWI3_EGU3_IRQHandler
+ IRQ SWI4_EGU4_IRQHandler
+ IRQ SWI5_EGU5_IRQHandler
+ IRQ TIMER3_IRQHandler
+ IRQ USBD_IRQHandler
.end
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S
index 042b0c3..16030a7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52833.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -222,10 +222,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -240,6 +241,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
index 187a08d..d7f793d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf52840.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -39,7 +39,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
.equ Stack_Size, __STACK_SIZE
#else
.align 3
- .equ Stack_Size, 8192
+ .equ Stack_Size, 16384
#endif
.globl __StackTop
.globl __StackLimit
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 16384
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -222,10 +222,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -240,6 +241,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S
index 1b05d92..a1d7ad0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_application.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -39,7 +39,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
.equ Stack_Size, __STACK_SIZE
#else
.align 3
- .equ Stack_Size, 8192
+ .equ Stack_Size, 16384
#endif
.globl __StackTop
.globl __StackLimit
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 16384
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -350,10 +350,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -368,6 +369,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S
index e8aa81e..fcbd8cd 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf5340_network.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -39,7 +39,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
.equ Stack_Size, __STACK_SIZE
#else
.align 3
- .equ Stack_Size, 8192
+ .equ Stack_Size, 4096
#endif
.globl __StackTop
.globl __StackLimit
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 4096
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -79,7 +79,7 @@ __isr_vector:
.long MemoryManagement_Handler
.long BusFault_Handler
.long UsageFault_Handler
- .long SecureFault_Handler
+ .long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
.long 0 /*Reserved */
@@ -239,10 +239,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -257,6 +258,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
@@ -339,13 +341,6 @@ UsageFault_Handler:
.size UsageFault_Handler, . - UsageFault_Handler
- .weak SecureFault_Handler
- .type SecureFault_Handler, %function
-SecureFault_Handler:
- b .
- .size SecureFault_Handler, . - SecureFault_Handler
-
-
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S
index d8b9893..81b4187 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/gcc_startup_nrf9160.S
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+Copyright (c) 2009-2020 ARM Limited. All rights reserved.
SPDX-License-Identifier: Apache-2.0
@@ -39,7 +39,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
.equ Stack_Size, __STACK_SIZE
#else
.align 3
- .equ Stack_Size, 8192
+ .equ Stack_Size, 16384
#endif
.globl __StackTop
.globl __StackLimit
@@ -56,7 +56,7 @@ __StackTop:
#elif defined(__HEAP_SIZE)
.equ Heap_Size, __HEAP_SIZE
#else
- .equ Heap_Size, 8192
+ .equ Heap_Size, 16384
#endif
.globl __HeapBase
.globl __HeapLimit
@@ -350,10 +350,11 @@ Reset_Handler:
* __etext: LMA of start of the section to copy from. Usually end of text
* __data_start__: VMA of start of the section to copy to.
* __bss_start__: VMA of end of the section to copy to. Normally __data_end__ is used, but by using __bss_start__
- * the user can add their own initialized data section before BSS section with the INTERT AFTER command.
+ * the user can add their own initialized data section before BSS section with the INSERT AFTER command.
*
* All addresses must be aligned to 4 bytes boundary.
*/
+#ifndef __STARTUP_SKIP_ETEXT
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__bss_start__
@@ -368,6 +369,7 @@ Reset_Handler:
bgt .L_loop1
.L_loop1_done:
+#endif
/* This part of work usually is done in C library startup code. Otherwise,
* define __STARTUP_CLEAR_BSS to enable it in this startup. This section
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s
index c3feaee..b4da82b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf51.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s
index d584339..115eb56 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52805.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52805.s
index 4b1200c..6250837 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52805.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52805.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -103,7 +103,7 @@ __vector_table
DCD CCM_AAR_IRQHandler
DCD WDT_IRQHandler
DCD RTC1_IRQHandler
- DCD 0 ; Reserved
+ DCD QDEC_IRQHandler
DCD 0 ; Reserved
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
@@ -351,6 +351,11 @@ WDT_IRQHandler
RTC1_IRQHandler
B .
+ PUBWEAK QDEC_IRQHandler
+ SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+ B .
+
PUBWEAK SWI0_EGU0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
SWI0_EGU0_IRQHandler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s
index 43fe6ec..3f2f25d 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52810.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s
index c447949..69c94b7 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52820.s
similarity index 92%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s
copy to hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52820.s
index c447949..8f5cfb1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52811.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52820.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -88,11 +88,11 @@ __vector_table
DCD POWER_CLOCK_IRQHandler
DCD RADIO_IRQHandler
DCD UARTE0_UART0_IRQHandler
- DCD TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
- DCD SPIM0_SPIS0_SPI0_IRQHandler
+ DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+ DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
DCD 0 ; Reserved
DCD GPIOTE_IRQHandler
- DCD SAADC_IRQHandler
+ DCD 0 ; Reserved
DCD TIMER0_IRQHandler
DCD TIMER1_IRQHandler
DCD TIMER2_IRQHandler
@@ -107,14 +107,13 @@ __vector_table
DCD COMP_IRQHandler
DCD SWI0_EGU0_IRQHandler
DCD SWI1_EGU1_IRQHandler
- DCD SWI2_IRQHandler
- DCD SWI3_IRQHandler
- DCD SWI4_IRQHandler
- DCD SWI5_IRQHandler
+ DCD SWI2_EGU2_IRQHandler
+ DCD SWI3_EGU3_IRQHandler
+ DCD SWI4_EGU4_IRQHandler
+ DCD SWI5_EGU5_IRQHandler
+ DCD TIMER3_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD PWM0_IRQHandler
- DCD PDM_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
@@ -125,6 +124,7 @@ __vector_table
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
+ DCD USBD_IRQHandler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
@@ -281,14 +281,14 @@ RADIO_IRQHandler
UARTE0_UART0_IRQHandler
B .
- PUBWEAK TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
+ PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-TWIM0_TWIS0_TWI0_SPIM1_SPIS1_SPI1_IRQHandler
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
B .
- PUBWEAK SPIM0_SPIS0_SPI0_IRQHandler
+ PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SPIM0_SPIS0_SPI0_IRQHandler
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
B .
PUBWEAK GPIOTE_IRQHandler
@@ -296,11 +296,6 @@ SPIM0_SPIS0_SPI0_IRQHandler
GPIOTE_IRQHandler
B .
- PUBWEAK SAADC_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SAADC_IRQHandler
- B .
-
PUBWEAK TIMER0_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
TIMER0_IRQHandler
@@ -371,34 +366,34 @@ SWI0_EGU0_IRQHandler
SWI1_EGU1_IRQHandler
B .
- PUBWEAK SWI2_IRQHandler
+ PUBWEAK SWI2_EGU2_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SWI2_IRQHandler
+SWI2_EGU2_IRQHandler
B .
- PUBWEAK SWI3_IRQHandler
+ PUBWEAK SWI3_EGU3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SWI3_IRQHandler
+SWI3_EGU3_IRQHandler
B .
- PUBWEAK SWI4_IRQHandler
+ PUBWEAK SWI4_EGU4_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SWI4_IRQHandler
+SWI4_EGU4_IRQHandler
B .
- PUBWEAK SWI5_IRQHandler
+ PUBWEAK SWI5_EGU5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SWI5_IRQHandler
+SWI5_EGU5_IRQHandler
B .
- PUBWEAK PWM0_IRQHandler
+ PUBWEAK TIMER3_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-PWM0_IRQHandler
+TIMER3_IRQHandler
B .
- PUBWEAK PDM_IRQHandler
+ PUBWEAK USBD_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-PDM_IRQHandler
+USBD_IRQHandler
B .
END
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52833.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52833.s
index 417014f..ac85d36 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52833.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52833.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s
index 2ad4502..7a63958 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf52840.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s
index 32106ed..8c66135 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_application.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_network.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_network.s
index 9f67f33..f7d9d2b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_network.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf5340_network.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
@@ -74,7 +74,7 @@ __vector_table
DCD MemoryManagement_Handler
DCD BusFault_Handler
DCD UsageFault_Handler
- DCD SecureFault_Handler
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
@@ -260,11 +260,6 @@ BusFault_Handler
UsageFault_Handler
B .
- PUBWEAK SecureFault_Handler
- SECTION .text:CODE:REORDER:NOROOT(1)
-SecureFault_Handler
- B .
-
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf9160.s b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf9160.s
index b2fc513..d0d370a 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf9160.s
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/iar_startup_nrf9160.s
@@ -1,4 +1,4 @@
-; Copyright (c) 2009-2018 ARM Limited. All rights reserved.
+; Copyright (c) 2009-2020 ARM Limited. All rights reserved.
;
; SPDX-License-Identifier: Apache-2.0
;
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
index f36d5e7..660ddc3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -35,8 +35,8 @@ POSSIBILITY OF SUCH DAMAGE.
/* MDK version */
#define MDK_MAJOR_VERSION 8
-#define MDK_MINOR_VERSION 30
-#define MDK_MICRO_VERSION 2
+#define MDK_MINOR_VERSION 35
+#define MDK_MICRO_VERSION 0
/* Define NRF51_SERIES for common use in nRF51 series devices. Only if not previously defined. */
#if defined (NRF51) ||\
@@ -65,7 +65,7 @@ POSSIBILITY OF SUCH DAMAGE.
#endif
/* Define NRF52_SERIES for common use in nRF52 series devices. Only if not previously defined. */
-#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
+#if defined (NRF52805_XXAA) || defined (NRF52810_XXAA) || defined (NRF52811_XXAA) || defined (NRF52820_XXAA) || defined (NRF52832_XXAA) || defined (NRF52832_XXAB) || defined (NRF52833_XXAA) || defined (NRF52840_XXAA)
#ifndef NRF52_SERIES
#define NRF52_SERIES
#endif
@@ -86,6 +86,11 @@ POSSIBILITY OF SUCH DAMAGE.
#endif
/* Define coprocessor domains */
+#if defined (NRF5340_XXAA_APPLICATION) || defined (NRF5340_XXAA_NETWORK)
+ #ifndef NRF5340_XXAA
+ #define NRF5340_XXAA
+ #endif
+#endif
#if defined (NRF5340_XXAA_APPLICATION)
#ifndef NRF_APPLICATION
#define NRF_APPLICATION
@@ -96,74 +101,86 @@ POSSIBILITY OF SUCH DAMAGE.
#define NRF_NETWORK
#endif
#endif
-
-#if defined(_WIN32)
- /* Do not include nrf specific files when building for PC host */
-#elif defined(__unix)
- /* Do not include nrf specific files when building for PC host */
-#elif defined(__APPLE__)
- /* Do not include nrf specific files when building for PC host */
-#else
- /* Device selection for device includes. */
- #if defined (NRF51)
- #include "nrf51.h"
- #include "nrf51_bitfields.h"
- #include "nrf51_deprecated.h"
-
- #elif defined (NRF52805_XXAA)
- #include "nrf52805.h"
- #include "nrf52805_bitfields.h"
- #include "nrf51_to_nrf52810.h"
- #include "nrf52_to_nrf52810.h"
- #include "nrf52810_to_nrf52811.h"
- #elif defined (NRF52810_XXAA)
- #include "nrf52810.h"
- #include "nrf52810_bitfields.h"
- #include "nrf51_to_nrf52810.h"
- #include "nrf52_to_nrf52810.h"
- #include "nrf52810_name_change.h"
- #elif defined (NRF52811_XXAA)
- #include "nrf52811.h"
- #include "nrf52811_bitfields.h"
- #include "nrf51_to_nrf52810.h"
- #include "nrf52_to_nrf52810.h"
- #include "nrf52810_to_nrf52811.h"
- #elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
- #include "nrf52.h"
- #include "nrf52_bitfields.h"
- #include "nrf51_to_nrf52.h"
- #include "nrf52_name_change.h"
- #elif defined (NRF52833_XXAA)
- #include "nrf52833.h"
- #include "nrf52833_bitfields.h"
- #include "nrf52_to_nrf52833.h"
- #include "nrf51_to_nrf52.h"
- #elif defined (NRF52840_XXAA)
- #include "nrf52840.h"
- #include "nrf52840_bitfields.h"
- #include "nrf51_to_nrf52840.h"
- #include "nrf52_to_nrf52840.h"
-
- #elif defined (NRF5340_XXAA_APPLICATION)
+/* Apply compatibility macros for old nRF5340 macros */
+#if defined(NRF5340_XXAA)
+ #if defined (NRF_APPLICATION)
+ #ifndef NRF5340_XXAA_APPLICATION
+ #define NRF5340_XXAA_APPLICATION
+ #endif
+ #endif
+ #if defined (NRF_NETWORK)
+ #ifndef NRF5340_XXAA_NETWORK
+ #define NRF5340_XXAA_NETWORK
+ #endif
+ #endif
+#endif
+
+/* Device selection for device includes. */
+#if defined (NRF51)
+ #include "nrf51.h"
+ #include "nrf51_bitfields.h"
+ #include "nrf51_deprecated.h"
+
+#elif defined (NRF52805_XXAA)
+ #include "nrf52805.h"
+ #include "nrf52805_bitfields.h"
+ #include "nrf51_to_nrf52810.h"
+ #include "nrf52_to_nrf52810.h"
+ #include "nrf52810_to_nrf52811.h"
+#elif defined (NRF52810_XXAA)
+ #include "nrf52810.h"
+ #include "nrf52810_bitfields.h"
+ #include "nrf51_to_nrf52810.h"
+ #include "nrf52_to_nrf52810.h"
+ #include "nrf52810_name_change.h"
+#elif defined (NRF52811_XXAA)
+ #include "nrf52811.h"
+ #include "nrf52811_bitfields.h"
+ #include "nrf51_to_nrf52810.h"
+ #include "nrf52_to_nrf52810.h"
+ #include "nrf52810_to_nrf52811.h"
+#elif defined (NRF52820_XXAA)
+ #include "nrf52820.h"
+ #include "nrf52820_bitfields.h"
+ #include "nrf51_to_nrf52.h"
+ #include "nrf52_to_nrf52833.h"
+ #include "nrf52833_to_nrf52820.h"
+#elif defined (NRF52832_XXAA) || defined (NRF52832_XXAB)
+ #include "nrf52.h"
+ #include "nrf52_bitfields.h"
+ #include "nrf51_to_nrf52.h"
+ #include "nrf52_name_change.h"
+#elif defined (NRF52833_XXAA)
+ #include "nrf52833.h"
+ #include "nrf52833_bitfields.h"
+ #include "nrf52_to_nrf52833.h"
+ #include "nrf51_to_nrf52.h"
+#elif defined (NRF52840_XXAA)
+ #include "nrf52840.h"
+ #include "nrf52840_bitfields.h"
+ #include "nrf51_to_nrf52840.h"
+ #include "nrf52_to_nrf52840.h"
+
+#elif defined (NRF5340_XXAA)
+ #if defined(NRF_APPLICATION)
#include "nrf5340_application.h"
- #include "nrf5340_application_bitfields.h"
- #elif defined (NRF5340_XXAA_NETWORK)
+ #include "nrf5340_application_bitfields.h"
+ #elif defined (NRF_NETWORK)
#include "nrf5340_network.h"
#include "nrf5340_network_bitfields.h"
-
- #elif defined (NRF9160_XXAA)
- #include "nrf9160.h"
- #include "nrf9160_bitfields.h"
- #include "nrf9160_name_change.h"
-
- #else
- #error "Device must be defined. See nrf.h."
- #endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */
-
- #include "compiler_abstraction.h"
-
-#endif /* _WIN32 || __unix || __APPLE__ */
+ #endif
+
+#elif defined (NRF9160_XXAA)
+ #include "nrf9160.h"
+ #include "nrf9160_bitfields.h"
+ #include "nrf9160_name_change.h"
+
+#else
+ #error "Device must be defined. See nrf.h."
+#endif /* NRF51, NRF52805_XXAA, NRF52810_XXAA, NRF52811_XXAA, NRF52820_XXAA, NRF52832_XXAA, NRF52832_XXAB, NRF52833_XXAA, NRF52840_XXAA, NRF5340_XXAA_APPLICATION, NRF5340_XXAA_NETWORK, NRF9160_XXAA */
+
+#include "compiler_abstraction.h"
#endif /* NRF_H */
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
index 5da3cea..b1ebabf 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,10 +30,10 @@
* @file nrf51.h
* @brief CMSIS HeaderFile
* @version 522
- * @date 17. January 2020
- * @note Generated by SVDConv V3.3.25 on Friday, 17.01.2020 17:08:30
+ * @date 14. August 2020
+ * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:12
* from File 'nrf51.svd',
- * last modified on Friday, 17.01.2020 16:08:22
+ * last modified on Friday, 14.08.2020 13:02:06
*/
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd
index 1b44852..51d0337 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51.svd
@@ -8,7 +8,7 @@
<version>522</version> <!-- Version of this description. It is the run of the automatic generation of SUS. -->
<description>nRF51 reference description for radio MCU with ARM 32-bit Cortex-M0 Microcontroller at 16MHz CPU clock</description>
<licenseText>
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n
\n
Redistribution and use in source and binary forms, with or without\n
modification, are permitted provided that the following conditions are met:\n
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_peripherals.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_peripherals.h
index 2c99e72..790f0b3 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_peripherals.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -71,6 +71,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
+
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxaa.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxaa.ld
index afcc7b6..a36a3c4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxaa.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxab.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxab.ld
index afcc7b6..7bfec18 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxab.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxac.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxac.ld
index afcc7b6..a6e98ba 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51422_xxac.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_peripherals.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_peripherals.h
index a7f49d3..8aa5a3b 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_peripherals.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -71,6 +71,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
+
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_xxab.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_xxab.ld
index afcc7b6..4f27467 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51801_xxab.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x30000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_peripherals.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_peripherals.h
index 917c492..9a685ab 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_peripherals.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -71,6 +71,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
+
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_xxaa.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_xxaa.ld
index afcc7b6..a36a3c4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51802_xxaa.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_peripherals.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_peripherals.h
index 14025de..2c819c6 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_peripherals.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -72,6 +72,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
+
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxaa.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxaa.ld
index afcc7b6..a36a3c4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxaa.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxab.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxab.ld
index afcc7b6..7bfec18 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxab.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x20000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxac.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxac.ld
index afcc7b6..a6e98ba 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51822_xxac.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_peripherals.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_peripherals.h
index 415fc6a..63aff43 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_peripherals.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -72,6 +72,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
+
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_xxaa.ld
similarity index 54%
copy from hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
copy to hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_xxaa.ld
index afcc7b6..a36a3c4 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf5340_xxaa_network.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51824_xxaa.ld
@@ -5,8 +5,8 @@ GROUP(-lgcc -lc -lnosys)
MEMORY
{
- FLASH (rx) : ORIGIN = 0x1000000, LENGTH = 0x40000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x40000
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000
}
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_bitfields.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_bitfields.h
index 7a98d12..ea72479 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_bitfields.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_bitfields.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_common.ld b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_common.ld
index 6f5e4c5..98a1003 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_common.ld
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_common.ld
@@ -89,6 +89,7 @@ SECTIONS
} > FLASH
__exidx_end = .;
+ . = ALIGN(4);
__etext = .;
.data : AT (__etext)
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_deprecated.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_deprecated.h
index 19370d4..4342366 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_deprecated.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_deprecated.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_erratas.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_erratas.h
index 9e6d253..44a0f92 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_erratas.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_erratas.h
@@ -3,7 +3,7 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -158,6 +158,8 @@ static bool nrf51_errata_1(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -207,6 +209,8 @@ static bool nrf51_errata_2(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -256,6 +260,8 @@ static bool nrf51_errata_3(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -323,6 +329,8 @@ static bool nrf51_errata_6(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -372,6 +380,8 @@ static bool nrf51_errata_7(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -421,6 +431,8 @@ static bool nrf51_errata_8(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -470,6 +482,8 @@ static bool nrf51_errata_9(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -519,6 +533,8 @@ static bool nrf51_errata_10(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -568,6 +584,8 @@ static bool nrf51_errata_11(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -617,6 +635,8 @@ static bool nrf51_errata_12(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -666,6 +686,8 @@ static bool nrf51_errata_13(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -715,6 +737,8 @@ static bool nrf51_errata_14(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -764,6 +788,8 @@ static bool nrf51_errata_15(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -813,6 +839,8 @@ static bool nrf51_errata_16(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -862,6 +890,8 @@ static bool nrf51_errata_17(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -911,6 +941,8 @@ static bool nrf51_errata_18(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -960,6 +992,8 @@ static bool nrf51_errata_19(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1009,6 +1043,8 @@ static bool nrf51_errata_20(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1058,6 +1094,8 @@ static bool nrf51_errata_21(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1107,6 +1145,8 @@ static bool nrf51_errata_22(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1156,6 +1196,8 @@ static bool nrf51_errata_23(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1205,6 +1247,8 @@ static bool nrf51_errata_24(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1254,6 +1298,8 @@ static bool nrf51_errata_25(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1303,6 +1349,8 @@ static bool nrf51_errata_26(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1352,6 +1400,8 @@ static bool nrf51_errata_27(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1401,6 +1451,8 @@ static bool nrf51_errata_28(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1450,6 +1502,8 @@ static bool nrf51_errata_29(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1499,6 +1553,8 @@ static bool nrf51_errata_30(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1548,6 +1604,8 @@ static bool nrf51_errata_31(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1597,6 +1655,8 @@ static bool nrf51_errata_32(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1646,6 +1706,8 @@ static bool nrf51_errata_33(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1695,6 +1757,8 @@ static bool nrf51_errata_34(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1744,6 +1808,8 @@ static bool nrf51_errata_35(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1793,6 +1859,8 @@ static bool nrf51_errata_36(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1842,6 +1910,8 @@ static bool nrf51_errata_37(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1891,6 +1961,8 @@ static bool nrf51_errata_38(void)
return true;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -1940,6 +2012,8 @@ static bool nrf51_errata_39(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -1989,6 +2063,8 @@ static bool nrf51_errata_40(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2038,6 +2114,8 @@ static bool nrf51_errata_41(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2087,6 +2165,8 @@ static bool nrf51_errata_42(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2136,6 +2216,8 @@ static bool nrf51_errata_43(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2185,6 +2267,8 @@ static bool nrf51_errata_44(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2234,6 +2318,8 @@ static bool nrf51_errata_45(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2283,6 +2369,8 @@ static bool nrf51_errata_46(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2332,6 +2420,8 @@ static bool nrf51_errata_47(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2381,6 +2471,8 @@ static bool nrf51_errata_48(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2430,6 +2522,8 @@ static bool nrf51_errata_49(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2524,6 +2618,8 @@ static bool nrf51_errata_55(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2573,6 +2669,8 @@ static bool nrf51_errata_56(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2622,6 +2720,8 @@ static bool nrf51_errata_57(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2671,6 +2771,8 @@ static bool nrf51_errata_58(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2720,6 +2822,8 @@ static bool nrf51_errata_59(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2769,6 +2873,8 @@ static bool nrf51_errata_60(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2818,6 +2924,8 @@ static bool nrf51_errata_61(void)
return true;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -2867,6 +2975,8 @@ static bool nrf51_errata_62(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2916,6 +3026,8 @@ static bool nrf51_errata_63(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -2965,6 +3077,8 @@ static bool nrf51_errata_64(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3014,6 +3128,8 @@ static bool nrf51_errata_65(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3063,6 +3179,8 @@ static bool nrf51_errata_66(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3112,6 +3230,8 @@ static bool nrf51_errata_67(void)
return true;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -3161,6 +3281,8 @@ static bool nrf51_errata_68(void)
return false;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3210,6 +3332,8 @@ static bool nrf51_errata_69(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3259,6 +3383,8 @@ static bool nrf51_errata_70(void)
return true;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -3308,6 +3434,8 @@ static bool nrf51_errata_71(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3357,6 +3485,8 @@ static bool nrf51_errata_72(void)
return true;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -3406,6 +3536,8 @@ static bool nrf51_errata_73(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3455,6 +3587,8 @@ static bool nrf51_errata_74(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
@@ -3504,6 +3638,8 @@ static bool nrf51_errata_75(void)
return true;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -3553,6 +3689,8 @@ static bool nrf51_errata_76(void)
return false;
case 0x0Dul:
return true;
+ default:
+ return true;
}
}
#endif
@@ -3611,6 +3749,8 @@ static bool nrf51_errata_78(void)
return true;
case 0x0Dul:
return false;
+ default:
+ return false;
}
}
#endif
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_peripherals.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_peripherals.h
index ff10593..d6457c0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_peripherals.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_peripherals.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
@@ -69,6 +69,8 @@ POSSIBILITY OF SUCH DAMAGE.
#define RADIO_PRESENT
#define RADIO_COUNT 1
+#define RADIO_TXPOWER_TXPOWER_Max RADIO_TXPOWER_TXPOWER_Pos4dBm
+
/* Accelerated Address Resolver */
#define AAR_PRESENT
#define AAR_COUNT 1
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52.h
index 1e13e66..3a6af64 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52810.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52810.h
index b56a891..c4436d1 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52810.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52810.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52840.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52840.h
index eaf68dd..376e0c0 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52840.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf51_to_nrf52840.h
@@ -1,6 +1,6 @@
/*
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h
index 7663eaa..ae44049 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,10 +30,10 @@
* @file nrf52.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2020
- * @note Generated by SVDConv V3.3.25 on Friday, 17.01.2020 17:08:30
+ * @date 14. August 2020
+ * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13
* from File 'nrf52.svd',
- * last modified on Friday, 17.01.2020 16:08:22
+ * last modified on Friday, 14.08.2020 13:02:06
*/
@@ -128,7 +128,7 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
-#define __DSP_PRESENT 0 /*!< DSP present or not */
+#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd
index e2f3a0b..da84887 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52.svd
@@ -8,7 +8,7 @@
<version>1</version>
<description>nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller </description>
<licenseText>
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n
\n
Redistribution and use in source and binary forms, with or without\n
modification, are permitted provided that the following conditions are met:\n
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.h b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.h
index 7ade23c..2a2f781 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.h
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.
+ * Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@@ -30,10 +30,10 @@
* @file nrf52805.h
* @brief CMSIS HeaderFile
* @version 1
- * @date 17. January 2020
- * @note Generated by SVDConv V3.3.25 on Friday, 17.01.2020 17:08:30
+ * @date 14. August 2020
+ * @note Generated by SVDConv V3.3.35 on Friday, 14.08.2020 15:02:13
* from File 'nrf52805.svd',
- * last modified on Friday, 17.01.2020 16:08:22
+ * last modified on Friday, 14.08.2020 13:02:06
*/
@@ -98,6 +98,7 @@ typedef enum {
CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
WDT_IRQn = 16, /*!< 16 WDT */
RTC1_IRQn = 17, /*!< 17 RTC1 */
+ QDEC_IRQn = 18, /*!< 18 QDEC */
SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
SWI2_IRQn = 22, /*!< 22 SWI2 */
@@ -114,7 +115,7 @@ typedef enum {
/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */
#define __CM4_REV 0x0001U /*!< CM4 Core Revision */
-#define __DSP_PRESENT 0 /*!< DSP present or not */
+#define __DSP_PRESENT 1 /*!< DSP present or not */
#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
@@ -452,6 +453,16 @@ typedef struct {
/**
+ * @brief QDEC_PSEL [PSEL] (Unspecified)
+ */
+typedef struct {
+ __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */
+ __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */
+ __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */
+} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */
+
+
+/**
* @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks)
*/
typedef struct {
@@ -464,8 +475,8 @@ typedef struct {
* @brief PPI_CH [CH] (PPI Channel)
*/
typedef struct {
- __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event end-point */
- __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task end-point */
+ __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */
+ __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */
} PPI_CH_Type; /*!< Size = 8 (0x8) */
@@ -473,7 +484,7 @@ typedef struct {
* @brief PPI_FORK [FORK] (Fork)
*/
typedef struct {
- __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task end-point */
+ __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */
} PPI_FORK_Type; /*!< Size = 4 (0x4) */
@@ -667,7 +678,7 @@ typedef struct { /*!< (@ 0x50000000) P0 Structure
__IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that
have met the criteria set in the PIN_CNF[n].SENSE
registers */
- __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behaviour
+ __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior
and LDETECT mode */
__IM uint32_t RESERVED1[118];
__IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO
@@ -717,9 +728,9 @@ typedef struct { /*!< (@ 0x40001000) RADIO Struct
TX path */
__IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started
RX path */
- __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */
- __IM uint32_t RESERVED4[3];
- __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air */
+ __IM uint32_t RESERVED4[4];
+ __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated when last bit is sent on air, or received
+ from air */
__IM uint32_t RESERVED5[36];
__IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
__IM uint32_t RESERVED6[64];
@@ -859,8 +870,8 @@ typedef struct { /*!< (@ 0x40002000) UARTE0 Struc
__IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED9[93];
- __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source Note : this register is read / write
- one to clear. */
+ __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one
+ to clear. */
__IM uint32_t RESERVED10[31];
__IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */
__IM uint32_t RESERVED11;
@@ -955,9 +966,8 @@ typedef struct { /*!< (@ 0x40003000) TWIM0 Struct
__IM uint32_t RESERVED4[7];
__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */
__IM uint32_t RESERVED5[8];
- __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) Last byte has been sent out after the SUSPEND
- task has been issued, TWI traffic is now
- suspended. */
+ __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is
+ now suspended. */
__IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */
__IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */
__IM uint32_t RESERVED6[2];
@@ -1203,7 +1213,7 @@ typedef struct { /*!< (@ 0x40006000) GPIOTE Struc
__IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
__IM uint32_t RESERVED5[129];
__IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n],
- SET[n] and CLR[n] tasks and IN[n] event */
+ SET[n], and CLR[n] tasks and IN[n] event */
} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */
@@ -1354,25 +1364,25 @@ typedef struct { /*!< (@ 0x4000C000) TEMP Structu
__IM uint32_t RESERVED2[127];
__IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */
__IM uint32_t RESERVED3[5];
- __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of 1st piece wise linear function */
- __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of 2nd piece wise linear function */
- __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of 3rd piece wise linear function */
- __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of 4th piece wise linear function */
- __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of 5th piece wise linear function */
- __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of 6th piece wise linear function */
+ __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */
+ __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */
+ __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */
+ __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */
+ __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */
+ __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */
__IM uint32_t RESERVED4[2];
- __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of 1st piece wise linear function */
- __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of 2nd piece wise linear function */
- __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of 3rd piece wise linear function */
- __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of 4th piece wise linear function */
- __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of 5th piece wise linear function */
- __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of 6th piece wise linear function */
+ __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */
+ __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */
+ __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */
+ __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */
+ __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */
+ __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */
__IM uint32_t RESERVED5[2];
- __IOM uint32_t T0; /*!< (@ 0x00000560) End point of 1st piece wise linear function */
- __IOM uint32_t T1; /*!< (@ 0x00000564) End point of 2nd piece wise linear function */
- __IOM uint32_t T2; /*!< (@ 0x00000568) End point of 3rd piece wise linear function */
- __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of 4th piece wise linear function */
- __IOM uint32_t T4; /*!< (@ 0x00000570) End point of 5th piece wise linear function */
+ __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */
+ __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */
+ __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */
+ __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */
+ __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */
} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */
@@ -1473,7 +1483,7 @@ typedef struct { /*!< (@ 0x4000F000) AAR Structur
*/
typedef struct { /*!< (@ 0x4000F000) CCM Structure */
- __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of key-stream. This operation
+ __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation
will stop by itself when completed. */
__OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will
stop by itself when completed. */
@@ -1482,7 +1492,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
the contents of the RATEOVERRIDE register
for any ongoing encryption/decryption */
__IM uint32_t RESERVED[60];
- __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Key-stream generation complete */
+ __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */
__IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */
__IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */
__IM uint32_t RESERVED1[61];
@@ -1500,7 +1510,7 @@ typedef struct { /*!< (@ 0x4000F000) CCM Structur
__IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */
__IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */
__IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */
- __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of key-stream generated when MODE.LENGTH
+ __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH
= Extended. */
__IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */
} NRF_CCM_Type; /*!< Size = 1312 (0x520) */
@@ -1537,12 +1547,61 @@ typedef struct { /*!< (@ 0x40010000) WDT Structur
/* =========================================================================================================================== */
+/* ================ QDEC ================ */
+/* =========================================================================================================================== */
+
+
+/**
+ * @brief Quadrature Decoder (QDEC)
+ */
+
+typedef struct { /*!< (@ 0x40012000) QDEC Structure */
+ __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */
+ __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */
+ __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */
+ __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */
+ __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */
+ __IM uint32_t RESERVED[59];
+ __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value
+ written to the SAMPLE register */
+ __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */
+ __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */
+ __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */
+ __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */
+ __IM uint32_t RESERVED1[59];
+ __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */
+ __IM uint32_t RESERVED2[64];
+ __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */
+ __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */
+ __IM uint32_t RESERVED3[125];
+ __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */
+ __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */
+ __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */
+ __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */
+ __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY
+ and DBLRDY events can be generated */
+ __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */
+ __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the
+ READCLRACC or RDCLRACC task */
+ __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */
+ __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */
+ __IM uint32_t RESERVED4[5];
+ __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */
+ __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected
+ double transitions */
+ __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC
+ or RDCLRDBL task */
+} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */
+
+
+
+/* =========================================================================================================================== */
/* ================ EGU0 ================ */
/* =========================================================================================================================== */
/**
- * @brief Event Generator Unit 0 (EGU0)
+ * @brief Event generator unit 0 (EGU0)
*/
typedef struct { /*!< (@ 0x40014000) EGU0 Structure */
@@ -1581,7 +1640,7 @@ typedef struct { /*!< (@ 0x40014000) SWI0 Structu
/**
- * @brief Non-volatile memory controller (NVMC)
+ * @brief Non Volatile Memory Controller (NVMC)
*/
typedef struct { /*!< (@ 0x4001E000) NVMC Structure */
@@ -1591,16 +1650,16 @@ typedef struct { /*!< (@ 0x4001E000) NVMC Structu
__IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */
union {
- __IOM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */
- __IOM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a
- page in code area. Equivalent to ERASEPAGE. */
+ __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */
+ __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a
+ page in code area, equivalent to ERASEPAGE */
};
- __IOM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
- __IOM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a
- page in code area. Equivalent to ERASEPAGE. */
- __IOM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration
+ __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */
+ __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a
+ page in code area, equivalent to ERASEPAGE */
+ __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration
registers */
- __IOM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code
+ __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code
area */
__IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */
} NRF_NVMC_Type; /*!< Size = 1312 (0x520) */
@@ -1623,8 +1682,8 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
__IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */
__IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */
__IM uint32_t RESERVED1;
- __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */
- __IM uint32_t RESERVED2[148];
+ __IOM PPI_CH_Type CH[10]; /*!< (@ 0x00000510) PPI Channel */
+ __IM uint32_t RESERVED2[168];
__IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */
__IM uint32_t RESERVED3[62];
__IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */
@@ -1671,6 +1730,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
#define NRF_CCM_BASE 0x4000F000UL
#define NRF_WDT_BASE 0x40010000UL
#define NRF_RTC1_BASE 0x40011000UL
+#define NRF_QDEC_BASE 0x40012000UL
#define NRF_EGU0_BASE 0x40014000UL
#define NRF_SWI0_BASE 0x40014000UL
#define NRF_EGU1_BASE 0x40015000UL
@@ -1722,6 +1782,7 @@ typedef struct { /*!< (@ 0x4001F000) PPI Structur
#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE)
#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE)
#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE)
+#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE)
#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE)
#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE)
#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE)
diff --git a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.svd b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.svd
index 6a631c1..bb09b2e 100644
--- a/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.svd
+++ b/hw/mcu/nordic/src/ext/nrfx/mdk/nrf52805.svd
@@ -8,7 +8,7 @@
<version>1</version>
<description>nRF52805 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller </description>
<licenseText>
-Copyright (c) 2010 - 2018, Nordic Semiconductor ASA All rights reserved.\n
+Copyright (c) 2010 - 2020, Nordic Semiconductor ASA All rights reserved.\n
\n
Redistribution and use in source and binary forms, with or without\n
modification, are permitted provided that the following conditions are met:\n
@@ -3898,7 +3898,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -3925,7 +3925,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -3952,7 +3952,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -3979,7 +3979,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4006,7 +4006,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4033,7 +4033,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4060,7 +4060,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4087,7 +4087,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4114,7 +4114,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4141,7 +4141,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4168,7 +4168,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4195,7 +4195,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4222,7 +4222,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4249,7 +4249,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4276,7 +4276,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4303,7 +4303,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4330,7 +4330,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4357,7 +4357,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4384,7 +4384,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4411,7 +4411,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4438,7 +4438,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4465,7 +4465,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4492,7 +4492,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4519,7 +4519,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4546,7 +4546,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4573,7 +4573,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4600,7 +4600,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4627,7 +4627,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4654,7 +4654,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4681,7 +4681,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4708,7 +4708,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4735,7 +4735,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets the pin high; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin high; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4771,7 +4771,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4798,7 +4798,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4825,7 +4825,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4852,7 +4852,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4879,7 +4879,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4906,7 +4906,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4933,7 +4933,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4960,7 +4960,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -4987,7 +4987,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5014,7 +5014,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5041,7 +5041,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5068,7 +5068,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5095,7 +5095,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5122,7 +5122,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5149,7 +5149,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5176,7 +5176,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5203,7 +5203,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5230,7 +5230,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5257,7 +5257,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5284,7 +5284,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5311,7 +5311,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5338,7 +5338,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5365,7 +5365,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5392,7 +5392,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5419,7 +5419,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5446,7 +5446,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5473,7 +5473,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5500,7 +5500,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5527,7 +5527,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5554,7 +5554,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5581,7 +5581,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -5608,7 +5608,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets the pin low; writing a '0' has no effect</description>
+ <description>Write: a '1' sets the pin low; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6812,7 +6812,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6839,7 +6839,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6866,7 +6866,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6893,7 +6893,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6920,7 +6920,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6947,7 +6947,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -6974,7 +6974,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7001,7 +7001,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7028,7 +7028,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7055,7 +7055,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7082,7 +7082,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7109,7 +7109,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7136,7 +7136,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7163,7 +7163,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7190,7 +7190,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7217,7 +7217,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7244,7 +7244,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7271,7 +7271,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7298,7 +7298,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7325,7 +7325,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7352,7 +7352,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7379,7 +7379,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7406,7 +7406,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7433,7 +7433,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7460,7 +7460,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7487,7 +7487,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7514,7 +7514,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7541,7 +7541,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7568,7 +7568,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7595,7 +7595,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7622,7 +7622,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7649,7 +7649,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Set</name>
- <description>Write: writing a '1' sets pin to output; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to output; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7685,7 +7685,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7712,7 +7712,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7739,7 +7739,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7766,7 +7766,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7793,7 +7793,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7820,7 +7820,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7847,7 +7847,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7874,7 +7874,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7901,7 +7901,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7928,7 +7928,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7955,7 +7955,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -7982,7 +7982,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8009,7 +8009,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8036,7 +8036,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8063,7 +8063,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8090,7 +8090,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8117,7 +8117,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8144,7 +8144,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8171,7 +8171,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8198,7 +8198,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8225,7 +8225,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8252,7 +8252,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8279,7 +8279,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8306,7 +8306,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8333,7 +8333,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8360,7 +8360,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8387,7 +8387,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8414,7 +8414,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8441,7 +8441,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8468,7 +8468,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8495,7 +8495,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -8522,7 +8522,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<usage>write</usage>
<enumeratedValue>
<name>Clear</name>
- <description>Write: writing a '1' sets pin to input; writing a '0' has no effect</description>
+ <description>Write: a '1' sets pin to input; a '0' has no effect</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -9115,13 +9115,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>DETECTMODE</name>
- <description>Select between default DETECT signal behaviour and LDETECT mode</description>
+ <description>Select between default DETECT signal behavior and LDETECT mode</description>
<addressOffset>0x524</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>DETECTMODE</name>
- <description>Select between default DETECT signal behaviour and LDETECT mode</description>
+ <description>Select between default DETECT signal behavior and LDETECT mode</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
@@ -9132,7 +9132,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
</enumeratedValue>
<enumeratedValue>
<name>LDETECT</name>
- <description>Use the latched LDETECT behaviour</description>
+ <description>Use the latched LDETECT behavior</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -9826,40 +9826,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</fields>
</register>
<register>
- <name>EVENTS_MHRMATCH</name>
- <description>MAC header match found</description>
- <addressOffset>0x15C</addressOffset>
- <access>read-write</access>
- <fields>
- <field>
- <name>EVENTS_MHRMATCH</name>
- <description>MAC header match found</description>
- <lsb>0</lsb>
- <msb>0</msb>
- <enumeratedValues>
- <enumeratedValue>
- <name>NotGenerated</name>
- <description>Event not generated</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Generated</name>
- <description>Event generated</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- </fields>
- </register>
- <register>
<name>EVENTS_PHYEND</name>
- <description>Generated when last bit is sent on air</description>
+ <description>Generated when last bit is sent on air, or received from air</description>
<addressOffset>0x16C</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>EVENTS_PHYEND</name>
- <description>Generated when last bit is sent on air</description>
+ <description>Generated when last bit is sent on air, or received from air</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
@@ -10459,33 +10433,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
</enumeratedValues>
</field>
<field>
- <name>MHRMATCH</name>
- <description>Write '1' to enable interrupt for event MHRMATCH</description>
- <lsb>23</lsb>
- <msb>23</msb>
- <enumeratedValues>
- <usage>read</usage>
- <enumeratedValue>
- <name>Disabled</name>
- <description>Read: Disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Read: Enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- <enumeratedValues>
- <usage>write</usage>
- <enumeratedValue>
- <name>Set</name>
- <description>Enable</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
<name>PHYEND</name>
<description>Write '1' to enable interrupt for event PHYEND</description>
<lsb>27</lsb>
@@ -10872,33 +10819,6 @@ POSSIBILITY OF SUCH DAMAGE.\n
</enumeratedValues>
</field>
<field>
- <name>MHRMATCH</name>
- <description>Write '1' to disable interrupt for event MHRMATCH</description>
- <lsb>23</lsb>
- <msb>23</msb>
- <enumeratedValues>
- <usage>read</usage>
- <enumeratedValue>
- <name>Disabled</name>
- <description>Read: Disabled</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Read: Enabled</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- <enumeratedValues>
- <usage>write</usage>
- <enumeratedValue>
- <name>Clear</name>
- <description>Disable</description>
- <value>1</value>
- </enumeratedValue>
- </enumeratedValues>
- </field>
- <field>
<name>PHYEND</name>
<description>Write '1' to disable interrupt for event PHYEND</description>
<lsb>27</lsb>
@@ -11051,7 +10971,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
</field>
<field>
<name>MAP</name>
- <description>Channel map selection.</description>
+ <description>Channel map selection</description>
<lsb>8</lsb>
<msb>8</msb>
<enumeratedValues>
@@ -11179,19 +11099,19 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>LFLEN</name>
- <description>Length on air of LENGTH field in number of bits.</description>
+ <description>Length on air of LENGTH field in number of bits</description>
<lsb>0</lsb>
<msb>3</msb>
</field>
<field>
<name>S0LEN</name>
- <description>Length on air of S0 field in number of bytes.</description>
+ <description>Length on air of S0 field in number of bytes</description>
<lsb>8</lsb>
<msb>8</msb>
</field>
<field>
<name>S1LEN</name>
- <description>Length on air of S1 field in number of bits.</description>
+ <description>Length on air of S1 field in number of bits</description>
<lsb>16</lsb>
<msb>19</msb>
</field>
@@ -11579,7 +11499,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>LEN</name>
- <description>CRC length in number of bytes.</description>
+ <description>CRC length in number of bytes</description>
<lsb>0</lsb>
<msb>1</msb>
<enumeratedValues>
@@ -11662,7 +11582,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>TIFS</name>
- <description>Interframe spacing in us</description>
+ <description>Interframe spacing in us.</description>
<lsb>0</lsb>
<msb>9</msb>
</field>
@@ -11676,7 +11596,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>RSSISAMPLE</name>
- <description>RSSI sample</description>
+ <description>RSSI sample.</description>
<lsb>0</lsb>
<msb>6</msb>
</field>
@@ -12024,7 +11944,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
</enumeratedValue>
<enumeratedValue>
<name>Fast</name>
- <description>Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information</description>
+ <description>Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specifications for more information</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -14466,7 +14386,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>ERRORSRC</name>
- <description>Error source Note : this register is read / write one to clear.</description>
+ <description>Error source This register is read/write one to clear.</description>
<addressOffset>0x480</addressOffset>
<access>read-write</access>
<modifiedWriteValues>oneToClear</modifiedWriteValues>
@@ -14814,7 +14734,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
</enumeratedValue>
<enumeratedValue>
<name>Baud1M</name>
- <description>1Mega baud</description>
+ <description>1 megabaud</description>
<value>0x10000000</value>
</enumeratedValue>
</enumeratedValues>
@@ -16064,13 +15984,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>EVENTS_SUSPENDED</name>
- <description>Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.</description>
+ <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
<addressOffset>0x148</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>EVENTS_SUSPENDED</name>
- <description>Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.</description>
+ <description>SUSPEND task has been issued, TWI traffic is now suspended.</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
@@ -18046,7 +17966,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>MATCH</name>
- <description>Which of the addresses in {ADDRESS} matched the incoming address</description>
+ <description>Indication of which address in {ADDRESS} that matched the incoming address</description>
<lsb>0</lsb>
<msb>0</msb>
</field>
@@ -18646,7 +18566,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>TXD</name>
- <description>TX data to send. Double buffered</description>
+ <description>TX data to send. Double buffered.</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -21217,7 +21137,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<dim>0x8</dim>
<dimIncrement>0x4</dimIncrement>
<name>CONFIG[%s]</name>
- <description>Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event</description>
+ <description>Description collection: Configuration for OUT[n], SET[n], and CLR[n] tasks and IN[n] event</description>
<addressOffset>0x510</addressOffset>
<access>read-write</access>
<fields>
@@ -21246,7 +21166,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
</field>
<field>
<name>PSEL</name>
- <description>GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event</description>
+ <description>GPIO number associated with SET[n], CLR[n], and OUT[n] tasks and IN[n] event</description>
<lsb>8</lsb>
<msb>12</msb>
</field>
@@ -25876,14 +25796,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>A0</name>
- <description>Slope of 1st piece wise linear function</description>
+ <description>Slope of first piecewise linear function</description>
<addressOffset>0x520</addressOffset>
<access>read-write</access>
<resetValue>0x00000326</resetValue>
<fields>
<field>
<name>A0</name>
- <description>Slope of 1st piece wise linear function</description>
+ <description>Slope of first piecewise linear function</description>
<lsb>0</lsb>
<msb>11</msb>
</field>
@@ -25891,14 +25811,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>A1</name>
- <description>Slope of 2nd piece wise linear function</description>
+ <description>Slope of second piecewise linear function</description>
<addressOffset>0x524</addressOffset>
<access>read-write</access>
<resetValue>0x00000348</resetValue>
<fields>
<field>
<name>A1</name>
- <description>Slope of 2nd piece wise linear function</description>
+ <description>Slope of second piecewise linear function</description>
<lsb>0</lsb>
<msb>11</msb>
</field>
@@ -25906,14 +25826,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>A2</name>
- <description>Slope of 3rd piece wise linear function</description>
+ <description>Slope of third piecewise linear function</description>
<addressOffset>0x528</addressOffset>
<access>read-write</access>
<resetValue>0x000003AA</resetValue>
<fields>
<field>
<name>A2</name>
- <description>Slope of 3rd piece wise linear function</description>
+ <description>Slope of third piecewise linear function</description>
<lsb>0</lsb>
<msb>11</msb>
</field>
@@ -25921,14 +25841,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>A3</name>
- <description>Slope of 4th piece wise linear function</description>
+ <description>Slope of fourth piecewise linear function</description>
<addressOffset>0x52C</addressOffset>
<access>read-write</access>
<resetValue>0x0000040E</resetValue>
<fields>
<field>
<name>A3</name>
- <description>Slope of 4th piece wise linear function</description>
+ <description>Slope of fourth piecewise linear function</description>
<lsb>0</lsb>
<msb>11</msb>
</field>
@@ -25936,14 +25856,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>A4</name>
- <description>Slope of 5th piece wise linear function</description>
+ <description>Slope of fifth piecewise linear function</description>
<addressOffset>0x530</addressOffset>
<access>read-write</access>
<resetValue>0x000004BD</resetValue>
<fields>
<field>
<name>A4</name>
- <description>Slope of 5th piece wise linear function</description>
+ <description>Slope of fifth piecewise linear function</description>
<lsb>0</lsb>
<msb>11</msb>
</field>
@@ -25951,14 +25871,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>A5</name>
- <description>Slope of 6th piece wise linear function</description>
+ <description>Slope of sixth piecewise linear function</description>
<addressOffset>0x534</addressOffset>
<access>read-write</access>
<resetValue>0x000005A3</resetValue>
<fields>
<field>
<name>A5</name>
- <description>Slope of 6th piece wise linear function</description>
+ <description>Slope of sixth piecewise linear function</description>
<lsb>0</lsb>
<msb>11</msb>
</field>
@@ -25966,14 +25886,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>B0</name>
- <description>y-intercept of 1st piece wise linear function</description>
+ <description>y-intercept of first piecewise linear function</description>
<addressOffset>0x540</addressOffset>
<access>read-write</access>
<resetValue>0x00003FEF</resetValue>
<fields>
<field>
<name>B0</name>
- <description>y-intercept of 1st piece wise linear function</description>
+ <description>y-intercept of first piecewise linear function</description>
<lsb>0</lsb>
<msb>13</msb>
</field>
@@ -25981,14 +25901,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>B1</name>
- <description>y-intercept of 2nd piece wise linear function</description>
+ <description>y-intercept of second piecewise linear function</description>
<addressOffset>0x544</addressOffset>
<access>read-write</access>
<resetValue>0x00003FBE</resetValue>
<fields>
<field>
<name>B1</name>
- <description>y-intercept of 2nd piece wise linear function</description>
+ <description>y-intercept of second piecewise linear function</description>
<lsb>0</lsb>
<msb>13</msb>
</field>
@@ -25996,14 +25916,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>B2</name>
- <description>y-intercept of 3rd piece wise linear function</description>
+ <description>y-intercept of third piecewise linear function</description>
<addressOffset>0x548</addressOffset>
<access>read-write</access>
<resetValue>0x00003FBE</resetValue>
<fields>
<field>
<name>B2</name>
- <description>y-intercept of 3rd piece wise linear function</description>
+ <description>y-intercept of third piecewise linear function</description>
<lsb>0</lsb>
<msb>13</msb>
</field>
@@ -26011,14 +25931,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>B3</name>
- <description>y-intercept of 4th piece wise linear function</description>
+ <description>y-intercept of fourth piecewise linear function</description>
<addressOffset>0x54C</addressOffset>
<access>read-write</access>
<resetValue>0x00000012</resetValue>
<fields>
<field>
<name>B3</name>
- <description>y-intercept of 4th piece wise linear function</description>
+ <description>y-intercept of fourth piecewise linear function</description>
<lsb>0</lsb>
<msb>13</msb>
</field>
@@ -26026,14 +25946,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>B4</name>
- <description>y-intercept of 5th piece wise linear function</description>
+ <description>y-intercept of fifth piecewise linear function</description>
<addressOffset>0x550</addressOffset>
<access>read-write</access>
<resetValue>0x00000124</resetValue>
<fields>
<field>
<name>B4</name>
- <description>y-intercept of 5th piece wise linear function</description>
+ <description>y-intercept of fifth piecewise linear function</description>
<lsb>0</lsb>
<msb>13</msb>
</field>
@@ -26041,14 +25961,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>B5</name>
- <description>y-intercept of 6th piece wise linear function</description>
+ <description>y-intercept of sixth piecewise linear function</description>
<addressOffset>0x554</addressOffset>
<access>read-write</access>
<resetValue>0x0000027C</resetValue>
<fields>
<field>
<name>B5</name>
- <description>y-intercept of 6th piece wise linear function</description>
+ <description>y-intercept of sixth piecewise linear function</description>
<lsb>0</lsb>
<msb>13</msb>
</field>
@@ -26056,14 +25976,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>T0</name>
- <description>End point of 1st piece wise linear function</description>
+ <description>End point of first piecewise linear function</description>
<addressOffset>0x560</addressOffset>
<access>read-write</access>
<resetValue>0x000000E2</resetValue>
<fields>
<field>
<name>T0</name>
- <description>End point of 1st piece wise linear function</description>
+ <description>End point of first piecewise linear function</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -26071,14 +25991,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>T1</name>
- <description>End point of 2nd piece wise linear function</description>
+ <description>End point of second piecewise linear function</description>
<addressOffset>0x564</addressOffset>
<access>read-write</access>
<resetValue>0x00000000</resetValue>
<fields>
<field>
<name>T1</name>
- <description>End point of 2nd piece wise linear function</description>
+ <description>End point of second piecewise linear function</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -26086,14 +26006,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>T2</name>
- <description>End point of 3rd piece wise linear function</description>
+ <description>End point of third piecewise linear function</description>
<addressOffset>0x568</addressOffset>
<access>read-write</access>
<resetValue>0x00000019</resetValue>
<fields>
<field>
<name>T2</name>
- <description>End point of 3rd piece wise linear function</description>
+ <description>End point of third piecewise linear function</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -26101,14 +26021,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>T3</name>
- <description>End point of 4th piece wise linear function</description>
+ <description>End point of fourth piecewise linear function</description>
<addressOffset>0x56C</addressOffset>
<access>read-write</access>
<resetValue>0x0000003C</resetValue>
<fields>
<field>
<name>T3</name>
- <description>End point of 4th piece wise linear function</description>
+ <description>End point of fourth piecewise linear function</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -26116,14 +26036,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>T4</name>
- <description>End point of 5th piece wise linear function</description>
+ <description>End point of fifth piecewise linear function</description>
<addressOffset>0x570</addressOffset>
<access>read-write</access>
<resetValue>0x00000050</resetValue>
<fields>
<field>
<name>T4</name>
- <description>End point of 5th piece wise linear function</description>
+ <description>End point of fifth piecewise linear function</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -27035,13 +26955,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
<registers>
<register>
<name>TASKS_KSGEN</name>
- <description>Start generation of key-stream. This operation will stop by itself when completed.</description>
+ <description>Start generation of keystream. This operation will stop by itself when completed.</description>
<addressOffset>0x000</addressOffset>
<access>write-only</access>
<fields>
<field>
<name>TASKS_KSGEN</name>
- <description>Start generation of key-stream. This operation will stop by itself when completed.</description>
+ <description>Start generation of keystream. This operation will stop by itself when completed.</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
@@ -27119,13 +27039,13 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>EVENTS_ENDKSGEN</name>
- <description>Key-stream generation complete</description>
+ <description>Keystream generation complete</description>
<addressOffset>0x100</addressOffset>
<access>read-write</access>
<fields>
<field>
<name>EVENTS_ENDKSGEN</name>
- <description>Key-stream generation complete</description>
+ <description>Keystream generation complete</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
@@ -27512,12 +27432,12 @@ POSSIBILITY OF SUCH DAMAGE.\n
<enumeratedValues>
<enumeratedValue>
<name>Default</name>
- <description>Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.</description>
+ <description>Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A keystream for packet payloads up to 27 bytes will be generated.</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
<name>Extended</name>
- <description>Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.</description>
+ <description>Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A keystream for packet payloads up to MAXPACKETSIZE bytes will be generated.</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -27574,7 +27494,7 @@ POSSIBILITY OF SUCH DAMAGE.\n
<fields>
<field>
<name>SCRATCHPTR</name>
- <description>Pointer to a scratch data area used for temporary storage during key-stream generation,
+ <description>Pointer to a scratch data area used for temporary storage during keystream generation,
MIC generation and encryption/decryption.</description>
<lsb>0</lsb>
<msb>31</msb>
@@ -27583,14 +27503,14 @@ POSSIBILITY OF SUCH DAMAGE.\n
</register>
<register>
<name>MAXPACKETSIZE</name>
- <description>Length of key-stream generated when MODE.LENGTH = Extended.</description>
+ <description>Length of keystream generated when MODE.LENGTH = Extended.</description>
<addressOffset>0x518</addressOffset>
<access>read-write</access>
<resetValue>0x000000FB</resetValue>
<fields>
<field>
<name>MAXPACKETSIZE</name>
- <description>Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.</description>
+ <description>Length of keystream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.</description>
<lsb>0</lsb>
<msb>7</msb>
</field>
@@ -28195,33 +28115,30 @@ POSSIBILITY OF SUCH DAMAGE.\n
</interrupt>
</peripheral>
<peripheral>
- <name>EGU0</name>
- <description>Event Generator Unit 0</description>
- <baseAddress>0x40014000</baseAddress>
- <headerStructName>EGU</headerStructName>
+ <name>QDEC</name>
+ <description>Quadrature Decoder</description>
+ <baseAddress>0x40012000</baseAddress>
<addressBlock>
<offset>0</offset>
<size>0x1000</size>
<usage>registers</usage>
</addressBlock>
<interrupt>
- <name>SWI0_EGU0</name>
- <value>20</value>
+ <name>QDEC</name>
+ <value>18</value>
</interrupt>
- <groupName>EGU</groupName>
+ <groupName>QDEC</groupName>
<size>0x20</size>
<registers>
<register>
- <dim>0x10</dim>
- <dimIncrement>0x4</dimIncrement>
- <name>TASKS_TRIGGER[%s]</name>
- <description>Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event</description>
+ <name>TASKS_START</name>
+ <description>Task starting the quadrature decoder</description>
<addressOffset>0x000</addressOffset>
<access>write-only</access>
<fields>
<field>
- <name>TASKS_TRIGGER</name>
- <description>Trigger n for triggering the corresponding TRIGGERED[n] event</description>
+ <name>TASKS_START</name>
+ <description>Task starting the quadrature decoder</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
@@ -28235,27 +28152,20 @@ POSSIBILITY OF SUCH DAMAGE.\n
</fields>
</register>
<register>
- <dim>0x10</dim>
- <dimIncrement>0x4</dimIncrement>
- <name>EVENTS_TRIGGERED[%s]</name>
- <description>Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task</description>
- <addressOffset>0x100</addressOffset>
- <access>read-write</access>
+ <name>TASKS_STOP</name>
+ <description>Task stopping the quadrature decoder</description>
+ <addressOffset>0x004</addressOffset>
+ <access>write-only</access>
<fields>
<field>
- <name>EVENTS_TRIGGERED</name>
- <description>Event number n generated by triggering the corresponding TRIGGER[n] task</description>
+ <name>TASKS_STOP</name>
+ <description>Task stopping the quadrature decoder</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>NotGenerated</name>
- <description>Event not generated</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Generated</name>
- <description>Event generated</description>
+ <name>Trigger</name>
+ <description>Trigger task</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
@@ -28263,295 +28173,326 @@ POSSIBILITY OF SUCH DAMAGE.\n
</fields>
</register>
<register>
- <name>INTEN</name>
- <description>Enable or disable interrupt</description>
- <addressOffset>0x300</addressOffset>
- <access>read-write</access>
+ <name>TASKS_READCLRACC</name>
+ <description>Read and clear ACC and ACCDBL</description>
+ <addressOffset>0x008</addressOffset>
+ <access>write-only</access>
<fields>
<field>
- <name>TRIGGERED0</name>
- <description>Enable or disable interrupt for event TRIGGERED[0]</description>
+ <name>TASKS_READCLRACC</name>
+ <description>Read and clear ACC and ACCDBL</description>
<lsb>0</lsb>
<msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>Disabled</name>
- <description>Disable</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Enable</description>
+ <name>Trigger</name>
+ <description>Trigger task</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>TASKS_RDCLRACC</name>
+ <description>Read and clear ACC</description>
+ <addressOffset>0x00C</addressOffset>
+ <access>write-only</access>
+ <fields>
<field>
- <name>TRIGGERED1</name>
- <description>Enable or disable interrupt for event TRIGGERED[1]</description>
- <lsb>1</lsb>
- <msb>1</msb>
+ <name>TASKS_RDCLRACC</name>
+ <description>Read and clear ACC</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>Disabled</name>
- <description>Disable</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Enable</description>
+ <name>Trigger</name>
+ <description>Trigger task</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>TASKS_RDCLRDBL</name>
+ <description>Read and clear ACCDBL</description>
+ <addressOffset>0x010</addressOffset>
+ <access>write-only</access>
+ <fields>
<field>
- <name>TRIGGERED2</name>
- <description>Enable or disable interrupt for event TRIGGERED[2]</description>
- <lsb>2</lsb>
- <msb>2</msb>
+ <name>TASKS_RDCLRDBL</name>
+ <description>Read and clear ACCDBL</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>Disabled</name>
- <description>Disable</description>
- <value>0</value>
- </enumeratedValue>
- <enumeratedValue>
- <name>Enabled</name>
- <description>Enable</description>
+ <name>Trigger</name>
+ <description>Trigger task</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>EVENTS_SAMPLERDY</name>
+ <description>Event being generated for every new sample value written to the SAMPLE register</description>
+ <addressOffset>0x100</addressOffset>
+ <access>read-write</access>
+ <fields>
<field>
- <name>TRIGGERED3</name>
- <description>Enable or disable interrupt for event TRIGGERED[3]</description>
- <lsb>3</lsb>
- <msb>3</msb>
+ <name>EVENTS_SAMPLERDY</name>
+ <description>Event being generated for every new sample value written to the SAMPLE register</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>Disabled</name>
- <description>Disable</description>
+ <name>NotGenerated</name>
+ <description>Event not generated</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
- <name>Enabled</name>
- <description>Enable</description>
+ <name>Generated</name>
+ <description>Event generated</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>EVENTS_REPORTRDY</name>
+ <description>Non-null report ready</description>
+ <addressOffset>0x104</addressOffset>
+ <access>read-write</access>
+ <fields>
<field>
- <name>TRIGGERED4</name>
- <description>Enable or disable interrupt for event TRIGGERED[4]</description>
- <lsb>4</lsb>
- <msb>4</msb>
+ <name>EVENTS_REPORTRDY</name>
+ <description>Non-null report ready</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>Disabled</name>
- <description>Disable</description>
+ <name>NotGenerated</name>
+ <description>Event not generated</description>
<value>0</value>
</enumeratedValue>
<enumeratedValue>
- <name>Enabled</name>
- <description>Enable</description>
+ <name>Generated</name>
+ <description>Event generated</description>
<value>1</value>
</enumeratedValue>
</enumeratedValues>
</field>
+ </fields>
+ </register>
+ <register>
+ <name>EVENTS_ACCOF</name>
+ <description>ACC or ACCDBL register overflow</description>
+ <addressOffset>0x108</addressOffset>
+ <access>read-write</access>
+ <fields>
<field>
- <name>TRIGGERED5</name>
- <description>Enable or disable interrupt for event TRIGGERED[5]</description>
- <lsb>5</lsb>
- <msb>5</msb>
+ <name>EVENTS_ACCOF</name>
+ <description>ACC or ACCDBL register overflow</description>
+ <lsb>0</lsb>
+ <msb>0</msb>
<enumeratedValues>
<enumeratedValue>
- <name>Disabled</name>
- <description>Disable</description>
... 65323 lines suppressed ...