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Posted to commits@nuttx.apache.org by xi...@apache.org on 2026/10/15 11:27:39 UTC
(nuttx) 02/05: arch/arm/stm32h7: Fix FDCAN register field masks.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang781216 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit ba4016bb9e79a8ee7fa3016e1fbc23027c2533b3
Author: raiden00pl <ra...@railab.me>
AuthorDate: Mon Oct 12 17:52:13 2026 +0200
arch/arm/stm32h7: Fix FDCAN register field masks.
RXF1C.F1SA and TXEFC.EFSA start addresses are 14 bits (15:2) and
DBTP.DTSEG1 is 5 bits, as in the reference manual and the M_CAN
headers of other chips. The masks truncated them, so an RX FIFO1
placed above 0xFC would overlap other message RAM sections.
The SocketCAN driver does not use these masks. Tested on
stm32h735g-dk with the FDCAN character driver using RX FIFO1.
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: raiden00pl <ra...@railab.me>
---
arch/arm/src/stm32h7/hardware/stm32_fdcan.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
index 0af9a42fcca..f8b1dc57e01 100644
--- a/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
+++ b/arch/arm/src/stm32h7/hardware/stm32_fdcan.h
@@ -214,7 +214,7 @@
#define FDCAN_DBTP_DTSEG2_MASK (0xFU << FDCAN_DBTP_DTSEG2_SHIFT) /* 0x000000F0 */
#define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_MASK /* Data time segment after sample point */
#define FDCAN_DBTP_DTSEG1_SHIFT (8U)
-#define FDCAN_DBTP_DTSEG1_MASK (0xFU << FDCAN_DBTP_DTSEG1_SHIFT) /* 0x00000F00 */
+#define FDCAN_DBTP_DTSEG1_MASK (0x1FU << FDCAN_DBTP_DTSEG1_SHIFT) /* 0x00001F00 */
#define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_MASK /* Data time segment before sample point */
#define FDCAN_DBTP_DBRP_SHIFT (16U)
#define FDCAN_DBTP_DBRP_MASK (0x1FU << FDCAN_DBTP_DBRP_SHIFT) /* 0x001F0000 */
@@ -963,7 +963,7 @@
/* *************** Bit definition for FDCAN_RXF1C register ****************/
#define FDCAN_RXF1C_F1SA_SHIFT (2U)
-#define FDCAN_RXF1C_F1SA_MASK (0x3FU << FDCAN_RXF1C_F1SA_SHIFT) /* 0x000000FC */
+#define FDCAN_RXF1C_F1SA_MASK (0x3FFFU << FDCAN_RXF1C_F1SA_SHIFT) /* 0x0000FFFC */
#define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_MASK /* Rx FIFO 1 Start Address */
#define FDCAN_RXF1C_F1S_SHIFT (16U)
#define FDCAN_RXF1C_F1S_MASK (0x7FU << FDCAN_RXF1C_F1S_SHIFT) /* 0x007F0000 */
@@ -1078,7 +1078,7 @@
/* *************** Bit definition for FDCAN_TXEFC register ****************/
#define FDCAN_TXEFC_EFSA_SHIFT (2U)
-#define FDCAN_TXEFC_EFSA_MASK (0x3FU << FDCAN_TXEFC_EFSA_SHIFT) /* 0x000000FC */
+#define FDCAN_TXEFC_EFSA_MASK (0x3FFFU << FDCAN_TXEFC_EFSA_SHIFT) /* 0x0000FFFC */
#define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_MASK /* Event FIFO Start Address */
#define FDCAN_TXEFC_EFS_SHIFT (8U)
#define FDCAN_TXEFC_EFS_MASK (0x3FU << FDCAN_TXEFC_EFS_SHIFT) /* 0x00003F00 */