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Posted to commits@nuttx.apache.org by ag...@apache.org on 2020/07/17 12:32:33 UTC
[incubator-nuttx] branch master updated: implement system reset on
SAMA5D27
This is an automated email from the ASF dual-hosted git repository.
aguettouche pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new 8581195 implement system reset on SAMA5D27
8581195 is described below
commit 85811957c999bae0f00b7fc07a27a49c74341f50
Author: Adam Feuer <ad...@starcat.io>
AuthorDate: Thu Jul 16 16:43:42 2020 -0700
implement system reset on SAMA5D27
- makes nsh reboot command work
Squashed commit of the following:
commit 5193f6ae9623bfb4d3bed4ecf3d0fb9ae1bfb6e8
Author: Adam Feuer <ad...@starcat.io>
Date: Thu Jul 16 16:41:54 2020 -0700
removed conflict tag that was missed
- result of an incorrectly fixed bad merge
commit 731108ea7495655e96e516448887ca8c9ab354d1
Author: Adam Feuer <ad...@starcat.io>
Date: Thu Jul 16 16:12:30 2020 -0700
implement system reset to make nsh reboot work
Squashed commit of the following:
commit 245d155cc58d31af412f2b832877736b2088b896
Author: Adam Feuer <ad...@starcat.io>
Date: Thu Jul 16 16:10:10 2020 -0700
add Kconfig setting for system reset
commit e7d5def8151821bf359c55c05ba1f59421b2371a
Author: Adam Feuer <ad...@starcat.io>
Date: Thu Jul 16 15:51:35 2020 -0700
implement system reset to make nsh reboot work
---
arch/arm/src/sama5/Make.defs | 4 +
arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h | 12 +--
arch/arm/src/sama5/hardware/sam_rstc.h | 95 +++++++++++++++++++++++
arch/arm/src/sama5/sam_systemreset.c | 75 ++++++++++++++++++
boards/arm/sama5/sama5d2-xult/Kconfig | 4 +
boards/arm/sama5/sama5d2-xult/src/Makefile | 4 +
boards/arm/sama5/sama5d2-xult/src/sam_reset.c | 62 +++++++++++++++
7 files changed, 250 insertions(+), 6 deletions(-)
diff --git a/arch/arm/src/sama5/Make.defs b/arch/arm/src/sama5/Make.defs
index b5f9e5b..940cf4a 100644
--- a/arch/arm/src/sama5/Make.defs
+++ b/arch/arm/src/sama5/Make.defs
@@ -128,6 +128,10 @@ ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += sam_timerisr.c
endif
+ifeq ($(CONFIG_SAMA5_SYSTEMRESET),y)
+CHIP_CSRCS += sam_systemreset.c
+endif
+
ifeq ($(CONFIG_SAMA5_DMAC0),y)
CHIP_CSRCS += sam_dmac.c
else
diff --git a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
index 81924b8..827850d 100644
--- a/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
+++ b/arch/arm/src/sama5/hardware/_sama5d2x_memorymap.h
@@ -376,12 +376,12 @@
# define SAM_EBICS3_MMUFLAGS MMU_ROMFLAGS
#endif
-#define SAM_QSPI0AES MMU_IOFLAGS
-#define SAM_QSPI1AES MMU_IOFLAGS
-#define SAM_SDMMC0 MMU_IOFLAGS
-#define SAM_SDMMC1 MMU_IOFLAGS
-#define SAM_QSPI0 MMU_IOFLAGS
-#define SAM_QSPI1 MMU_IOFLAGS
+#define SAM_QSPI0AES_MMUFLAGS MMU_IOFLAGS
+#define SAM_QSPI1AES_MMUFLAGS MMU_IOFLAGS
+#define SAM_SDMMC0_MMUFLAGS MMU_IOFLAGS
+#define SAM_SDMMC1_MMUFLAGS MMU_IOFLAGS
+#define SAM_QSPI0_MMUFLAGS MMU_IOFLAGS
+#define SAM_QSPI1_MMUFLAGS MMU_IOFLAGS
#define SAM_NFCCR_MMUFLAGS MMU_IOFLAGS
#define SAM_PERIPHA_MMUFLAGS MMU_IOFLAGS
diff --git a/arch/arm/src/sama5/hardware/sam_rstc.h b/arch/arm/src/sama5/hardware/sam_rstc.h
new file mode 100644
index 0000000..ed894e3
--- /dev/null
+++ b/arch/arm/src/sama5/hardware/sam_rstc.h
@@ -0,0 +1,95 @@
+/****************************************************************************
+ * arch/arm/src/sama5/hardware/sam_rstc.h
+ * Reset Controller (RSTC) definitions for the SAMA5
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RSTC_H
+#define __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RSTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <arch/sama5/chip.h>
+#include "hardware/sam_memorymap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* RSTC register offsets ****************************************************/
+
+#define SAM_RSTC_CR_OFFSET 0x00 /* Control Register */
+#define SAM_RSTC_SR_OFFSET 0x04 /* Status Register */
+#define SAM_RSTC_MR_OFFSET 0x08 /* Mode Register */
+
+/* RSTC register addresses **************************************************/
+
+#define SAM_RSTC_CR (SAM_RSTC_VBASE+SAM_RSTC_CR_OFFSET)
+#define SAM_RSTC_SR (SAM_RSTC_VBASE+SAM_RSTC_SR_OFFSET)
+#define SAM_RSTC_MR (SAM_RSTC_VBASE+SAM_RSTC_MR_OFFSET)
+
+/* RSTC register bit definitions ********************************************/
+
+/* Reset Controller Control Register */
+
+#define RSTC_CR_PROCRST (1 << 0) /* Bit 0: Processor Reset */
+#define RSTC_CR_EXTRST (1 << 3) /* Bit 3: External Reset */
+#define RSTC_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
+#define RSTC_CR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
+# define RSTC_CR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
+
+/* Reset Controller Status Register */
+
+#define RSTC_SR_URSTS (1 << 0) /* Bit 0: User Reset Status */
+#define RSTC_SR_RSTTYP_SHIFT (8) /* Bits 8-10: Reset Type */
+#define RSTC_SR_RSTTYP_MASK (7 << RSTC_SR_RSTTYP_SHIFT)
+# define RSTC_SR_RSTTYP_PWRUP (0 << RSTC_SR_RSTTYP_SHIFT) /* General Reset */
+# define RSTC_SR_RSTTYP_BACKUP (1 << RSTC_SR_RSTTYP_SHIFT) /* Backup Reset */
+# define RSTC_SR_RSTTYP_WDOG (2 << RSTC_SR_RSTTYP_SHIFT) /* Watchdog Reset */
+# define RSTC_SR_RSTTYP_SWRST (3 << RSTC_SR_RSTTYP_SHIFT) /* Software Reset */
+# define RSTC_SR_RSTTYP_NRST (4 << RSTC_SR_RSTTYP_SHIFT) /* User Reset NRST pin */
+#define RSTC_SR_NRSTL (1 << 16) /* Bit 16: NRST Pin Level */
+#define RSTC_SR_SRCMP (1 << 17) /* Bit 17: Software Reset Command in Progress */
+
+/* Reset Controller Mode Register */
+
+#define RSTC_MR_URSTEN (1 << 0) /* Bit 0: User Reset Enable */
+#define RSTC_MR_URSTIEN (1 << 4) /* Bit 4: User Reset Interrupt Enable */
+#define RSTC_MR_ERSTL_SHIFT (8) /* Bits 8-11: External Reset Length */
+#define RSTC_MR_ERSTL_MASK (15 << RSTC_MR_ERSTL_SHIFT)
+# define RSTC_MR_ERSTL(n) ((uint32_t)(n) << RSTC_MR_ERSTL_SHIFT)
+#define RSTC_MR_KEY_SHIFT (24) /* Bits 24-31: Password */
+#define RSTC_MR_KEY_MASK (0xff << RSTC_CR_KEY_SHIFT)
+# define RSTC_MR_KEY (0xa5 << RSTC_CR_KEY_SHIFT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_SAMA5_HARDWARE_SAM_RSTC_H */
diff --git a/arch/arm/src/sama5/sam_systemreset.c b/arch/arm/src/sama5/sam_systemreset.c
new file mode 100644
index 0000000..3fa8299
--- /dev/null
+++ b/arch/arm/src/sama5/sam_systemreset.c
@@ -0,0 +1,75 @@
+/****************************************************************************
+ * arch/arm/src/sama5/sam_systemreset.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/sama5/chip.h>
+
+#include "arm_arch.h"
+#include "hardware/sam_rstc.h"
+
+#ifdef CONFIG_SAMA5_SYSTEMRESET
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_systemreset
+ *
+ * Description:
+ * Internal reset logic.
+ *
+ ****************************************************************************/
+
+void up_systemreset(void)
+{
+ uint32_t rstcr;
+#if defined(CONFIG_SAMA5_EXTRESET_ERST) && CONFIG_SAMA5_EXTRESET_ERST != 0
+ uint32_t rstmr;
+#endif
+
+ rstcr = (RSTC_CR_PROCRST | RSTC_CR_KEY);
+
+#if defined(CONFIG_SAMA5_EXTRESET_ERST) && CONFIG_SAMA5_EXTRESET_ERST != 0
+ rstcr |= RSTC_CR_EXTRST;
+
+ rstmr = getreg32(SAM_RSTC_MR);
+ rstmr &= ~RSTC_MR_ERSTL_MASK;
+ rstmr &= RSTC_MR_ERSTL(CONFIG_SAMA5_EXTRESET_ERST - 1) | RSTC_MR_KEY;
+ putreg32(rstmr, SAM_RSTC_MR);
+#endif
+
+ putreg32(rstcr, SAM_RSTC_CR);
+
+ /* Wait for the reset */
+
+ for (; ; );
+}
+#endif /* CONFIG_SAMA5_SYSTEMRESET */
diff --git a/boards/arm/sama5/sama5d2-xult/Kconfig b/boards/arm/sama5/sama5d2-xult/Kconfig
index 5ce561f..b63d62e 100644
--- a/boards/arm/sama5/sama5d2-xult/Kconfig
+++ b/boards/arm/sama5/sama5d2-xult/Kconfig
@@ -128,4 +128,8 @@ config SAMA5_SDMMC1_WIDTH_D1_D4
default y
depends on SAMA5_SDMMC1
+config SAMA5_SYSTEMRESET
+ bool "Enable system reset - this will enable the nsh reboot command"
+ select BOARDCTL_RESET
+
endif # ARCH_BOARD_SAMA5D2_XULT
diff --git a/boards/arm/sama5/sama5d2-xult/src/Makefile b/boards/arm/sama5/sama5d2-xult/src/Makefile
index 8ed19b5..8c54857 100644
--- a/boards/arm/sama5/sama5d2-xult/src/Makefile
+++ b/boards/arm/sama5/sama5d2-xult/src/Makefile
@@ -139,4 +139,8 @@ ifeq ($(CONFIG_ARCH_BUTTONS),y)
CSRCS += sam_buttons.c
endif
+ifeq ($(CONFIG_BOARDCTL_RESET),y)
+CSRCS += sam_reset.c
+endif
+
include $(TOPDIR)/boards/Board.mk
diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_reset.c b/boards/arm/sama5/sama5d2-xult/src/sam_reset.c
new file mode 100644
index 0000000..5cbb062
--- /dev/null
+++ b/boards/arm/sama5/sama5d2-xult/src/sam_reset.c
@@ -0,0 +1,62 @@
+/****************************************************************************
+ * boards/arm/sama5/sama5d2-xult/src/sam_reset.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#ifdef CONFIG_BOARDCTL_RESET
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_reset
+ *
+ * Description:
+ * Reset board. Support for this function is required by board-level
+ * logic if CONFIG_BOARDCTL_RESET is selected.
+ *
+ * Input Parameters:
+ * status - Status information provided with the reset event. This
+ * meaning of this status information is board-specific. If not
+ * used by a board, the value zero may be provided in calls to
+ * board_reset().
+ *
+ * Returned Value:
+ * If this function returns, then it was not possible to power-off the
+ * board due to some constraints. The return value int this case is a
+ * board-specific reason for the failure to shutdown.
+ *
+ ****************************************************************************/
+
+int board_reset(int status)
+{
+ up_systemreset();
+ return 0;
+}
+
+#endif /* CONFIG_BOARDCTL_RESET */