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Posted to commits@mynewt.apache.org by ma...@apache.org on 2016/10/11 16:25:32 UTC
[13/45] incubator-mynewt-core git commit: add Kinetis SDK 2.0 built
for FRDM-K64F
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_port.h
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diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_port.h b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_port.h
new file mode 100644
index 0000000..790518c
--- /dev/null
+++ b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_port.h
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_PORT_H_
+#define _FSL_PORT_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup port_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! Version 2.0.1. */
+#define FSL_PORT_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief Internal resistor pull feature selection */
+enum _port_pull
+{
+ kPORT_PullDisable = 0U, /*!< internal pull-up/down resistor is disabled. */
+ kPORT_PullDown = 2U, /*!< internal pull-down resistor is enabled. */
+ kPORT_PullUp = 3U, /*!< internal pull-up resistor is enabled. */
+};
+
+/*! @brief Slew rate selection */
+enum _port_slew_rate
+{
+ kPORT_FastSlewRate = 0U, /*!< fast slew rate is configured. */
+ kPORT_SlowSlewRate = 1U, /*!< slow slew rate is configured. */
+};
+
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+/*! @brief Internal resistor pull feature enable/disable */
+enum _port_open_drain_enable
+{
+ kPORT_OpenDrainDisable = 0U, /*!< internal pull-down resistor is disabled. */
+ kPORT_OpenDrainEnable = 1U, /*!< internal pull-up resistor is enabled. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+
+/*! @brief Passive filter feature enable/disable */
+enum _port_passive_filter_enable
+{
+ kPORT_PassiveFilterDisable = 0U, /*!< fast slew rate is configured. */
+ kPORT_PassiveFilterEnable = 1U, /*!< slow slew rate is configured. */
+};
+
+/*! @brief Configures the drive strength. */
+enum _port_drive_strength
+{
+ kPORT_LowDriveStrength = 0U, /*!< low drive strength is configured. */
+ kPORT_HighDriveStrength = 1U, /*!< high drive strength is configured. */
+};
+
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+/*! @brief Unlock/lock the pin control register field[15:0] */
+enum _port_lock_register
+{
+ kPORT_UnlockRegister = 0U, /*!< Pin Control Register fields [15:0] are not locked. */
+ kPORT_LockRegister = 1U, /*!< Pin Control Register fields [15:0] are locked. */
+};
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+
+/*! @brief Pin mux selection */
+typedef enum _port_mux
+{
+ kPORT_PinDisabledOrAnalog = 0U, /*!< corresponding pin is disabled, but is used as an analog pin. */
+ kPORT_MuxAsGpio = 1U, /*!< corresponding pin is configured as GPIO. */
+ kPORT_MuxAlt2 = 2U, /*!< chip-specific */
+ kPORT_MuxAlt3 = 3U, /*!< chip-specific */
+ kPORT_MuxAlt4 = 4U, /*!< chip-specific */
+ kPORT_MuxAlt5 = 5U, /*!< chip-specific */
+ kPORT_MuxAlt6 = 6U, /*!< chip-specific */
+ kPORT_MuxAlt7 = 7U, /*!< chip-specific */
+} port_mux_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef enum _port_interrupt
+{
+ kPORT_InterruptOrDMADisabled = 0x0U, /*!< Interrupt/DMA request is disabled. */
+#if defined(FSL_FEATURE_PORT_HAS_DMA_REQUEST) && FSL_FEATURE_PORT_HAS_DMA_REQUEST
+ kPORT_DMARisingEdge = 0x1U, /*!< DMA request on rising edge. */
+ kPORT_DMAFallingEdge = 0x2U, /*!< DMA request on falling edge. */
+ kPORT_DMAEitherEdge = 0x3U, /*!< DMA request on either edge. */
+#endif
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_FLAG) && FSL_FEATURE_PORT_HAS_IRQC_FLAG
+ kPORT_FlagRisingEdge = 0x05U, /*!< Flag sets on rising edge. */
+ kPORT_FlagFallingEdge = 0x06U, /*!< Flag sets on falling edge. */
+ kPORT_FlagEitherEdge = 0x07U, /*!< Flag sets on either edge. */
+#endif
+ kPORT_InterruptLogicZero = 0x8U, /*!< Interrupt when logic zero. */
+ kPORT_InterruptRisingEdge = 0x9U, /*!< Interrupt on rising edge. */
+ kPORT_InterruptFallingEdge = 0xAU, /*!< Interrupt on falling edge. */
+ kPORT_InterruptEitherEdge = 0xBU, /*!< Interrupt on either edge. */
+ kPORT_InterruptLogicOne = 0xCU, /*!< Interrupt when logic one. */
+#if defined(FSL_FEATURE_PORT_HAS_IRQC_TRIGGER) && FSL_FEATURE_PORT_HAS_IRQC_TRIGGER
+ kPORT_ActiveHighTriggerOutputEnable = 0xDU, /*!< Enable active high trigger output. */
+ kPORT_ActiveLowTriggerOutputEnable = 0xEU, /*!< Enable active low trigger output. */
+#endif
+} port_interrupt_t;
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+/*! @brief Digital filter clock source selection */
+typedef enum _port_digital_filter_clock_source
+{
+ kPORT_BusClock = 0U, /*!< Digital filters are clocked by the bus clock. */
+ kPORT_LpoClock = 1U, /*!< Digital filters are clocked by the 1 kHz LPO clock. */
+} port_digital_filter_clock_source_t;
+
+/*! @brief PORT digital filter feature configuration definition */
+typedef struct _port_digital_filter_config
+{
+ uint32_t digitalFilterWidth; /*!< Set digital filter width */
+ port_digital_filter_clock_source_t clockSource; /*!< Set digital filter clockSource */
+} port_digital_filter_config_t;
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*! @brief PORT pin config structure */
+typedef struct _port_pin_config
+{
+ uint16_t pullSelect : 2; /*!< no-pull/pull-down/pull-up select */
+ uint16_t slewRate : 1; /*!< fast/slow slew rate Configure */
+ uint16_t : 1;
+ uint16_t passiveFilterEnable : 1; /*!< passive filter enable/disable */
+#if defined(FSL_FEATURE_PORT_HAS_OPEN_DRAIN) && FSL_FEATURE_PORT_HAS_OPEN_DRAIN
+ uint16_t openDrainEnable : 1; /*!< open drain enable/disable */
+#else
+ uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_OPEN_DRAIN */
+ uint16_t driveStrength : 1; /*!< fast/slow drive strength configure */
+ uint16_t : 1;
+ uint16_t mux : 3; /*!< pin mux Configure */
+ uint16_t : 4;
+#if defined(FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK) && FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK
+ uint16_t lockRegister : 1; /*!< lock/unlock the pcr field[15:0] */
+#else
+ uint16_t : 1;
+#endif /* FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK */
+} port_pin_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name Configuration */
+/*@{*/
+
+/*!
+ * @brief Sets the port PCR register.
+ *
+ * This is an example to define an input pin or output pin PCR configuration:
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ * kPORT_PullUp,
+ * kPORT_FastSlewRate,
+ * kPORT_PassiveFilterDisable,
+ * kPORT_OpenDrainDisable,
+ * kPORT_LowDriveStrength,
+ * kPORT_MuxAsGpio,
+ * kPORT_UnLockRegister,
+ * };
+ * @endcode
+ *
+ * @param base PORT peripheral base pointer.
+ * @param pin PORT pin number.
+ * @param config PORT PCR register configure structure.
+ */
+static inline void PORT_SetPinConfig(PORT_Type *base, uint32_t pin, const port_pin_config_t *config)
+{
+ assert(config);
+ uint32_t addr = (uint32_t)&base->PCR[pin];
+ *(volatile uint16_t *)(addr) = *((const uint16_t *)config);
+}
+
+/*!
+ * @brief Sets the port PCR register for multiple pins.
+ *
+ * This is an example to define input pins or output pins PCR configuration:
+ * @code
+ * // Define a digital input pin PCR configuration
+ * port_pin_config_t config = {
+ * kPORT_PullUp ,
+ * kPORT_PullEnable,
+ * kPORT_FastSlewRate,
+ * kPORT_PassiveFilterDisable,
+ * kPORT_OpenDrainDisable,
+ * kPORT_LowDriveStrength,
+ * kPORT_MuxAsGpio,
+ * kPORT_UnlockRegister,
+ * };
+ * @endcode
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pins' numbers macro.
+ * @param config PORT PCR register configure structure.
+ */
+static inline void PORT_SetMultiplePinsConfig(PORT_Type *base, uint32_t mask, const port_pin_config_t *config)
+{
+ assert(config);
+
+ uint16_t pcrl = *((const uint16_t *)config);
+
+ if (mask & 0xffffU)
+ {
+ base->GPCLR = ((mask & 0xffffU) << 16) | pcrl;
+ }
+ if (mask >> 16)
+ {
+ base->GPCHR = (mask & 0xffff0000U) | pcrl;
+ }
+}
+
+/*!
+ * @brief Configures the pin muxing.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param pin PORT pin number.
+ * @param mux pin muxing slot selection.
+ * - #kPORT_PinDisabledOrAnalog: Pin disabled or work in analog function.
+ * - #kPORT_MuxAsGpio : Set as GPIO.
+ * - #kPORT_MuxAlt2 : chip-specific.
+ * - #kPORT_MuxAlt3 : chip-specific.
+ * - #kPORT_MuxAlt4 : chip-specific.
+ * - #kPORT_MuxAlt5 : chip-specific.
+ * - #kPORT_MuxAlt6 : chip-specific.
+ * - #kPORT_MuxAlt7 : chip-specific.
+ * @Note : This function is NOT recommended to use together with the PORT_SetPinsConfig, because
+ * the PORT_SetPinsConfig need to configure the pin mux anyway (Otherwise the pin mux will
+ * be reset to zero : kPORT_PinDisabledOrAnalog).
+ * This function is recommended to use in the case you just need to reset the pin mux
+ *
+ */
+static inline void PORT_SetPinMux(PORT_Type *base, uint32_t pin, port_mux_t mux)
+{
+ base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_MUX_MASK) | PORT_PCR_MUX(mux);
+}
+
+#if defined(FSL_FEATURE_PORT_HAS_DIGITAL_FILTER) && FSL_FEATURE_PORT_HAS_DIGITAL_FILTER
+
+/*!
+ * @brief Enables the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pins' numbers macro.
+ */
+static inline void PORT_EnablePinsDigitalFilter(PORT_Type *base, uint32_t mask, bool enable)
+{
+ if (enable == true)
+ {
+ base->DFER |= mask;
+ }
+ else
+ {
+ base->DFER &= ~mask;
+ }
+}
+
+/*!
+ * @brief Sets the digital filter in one port, each bit of the 32-bit register represents one pin.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param config PORT digital filter configuration structure.
+ */
+static inline void PORT_SetDigitalFilterConfig(PORT_Type *base, const port_digital_filter_config_t *config)
+{
+ assert(config);
+
+ base->DFCR = PORT_DFCR_CS(config->clockSource);
+ base->DFWR = PORT_DFWR_FILT(config->digitalFilterWidth);
+}
+
+#endif /* FSL_FEATURE_PORT_HAS_DIGITAL_FILTER */
+
+/*@}*/
+
+/*! @name Interrupt */
+/*@{*/
+
+/*!
+ * @brief Configures the port pin interrupt/DMA request.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param pin PORT pin number.
+ * @param config PORT pin interrupt configuration.
+ * - #kPORT_InterruptOrDMADisabled: Interrupt/DMA request disabled.
+ * - #kPORT_DMARisingEdge : DMA request on rising edge(if the DMA requests exit).
+ * - #kPORT_DMAFallingEdge: DMA request on falling edge(if the DMA requests exit).
+ * - #kPORT_DMAEitherEdge : DMA request on either edge(if the DMA requests exit).
+ * - #kPORT_FlagRisingEdge : Flag sets on rising edge(if the Flag states exit).
+ * - #kPORT_FlagFallingEdge : Flag sets on falling edge(if the Flag states exit).
+ * - #kPORT_FlagEitherEdge : Flag sets on either edge(if the Flag states exit).
+ * - #kPORT_InterruptLogicZero : Interrupt when logic zero.
+ * - #kPORT_InterruptRisingEdge : Interrupt on rising edge.
+ * - #kPORT_InterruptFallingEdge: Interrupt on falling edge.
+ * - #kPORT_InterruptEitherEdge : Interrupt on either edge.
+ * - #kPORT_InterruptLogicOne : Interrupt when logic one.
+ * - #kPORT_ActiveHighTriggerOutputEnable : Enable active high trigger output(if the trigger states exit).
+ * - #kPORT_ActiveLowTriggerOutputEnable : Enable active low trigger output(if the trigger states exit).
+ */
+static inline void PORT_SetPinInterruptConfig(PORT_Type *base, uint32_t pin, port_interrupt_t config)
+{
+ base->PCR[pin] = (base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | PORT_PCR_IRQC(config);
+}
+
+/*!
+ * @brief Reads the whole port status flag.
+ *
+ * If a pin is configured to generate the DMA request, the corresponding flag
+ * is cleared automatically at the completion of the requested DMA transfer.
+ * Otherwise, the flag remains set until a logic one is written to that flag.
+ * If configured for a level sensitive interrupt that remains asserted, the flag
+ * is set again immediately.
+ *
+ * @param base PORT peripheral base pointer.
+ * @return Current port interrupt status flags, for example, 0x00010001 means the
+ * pin 0 and 17 have the interrupt.
+ */
+static inline uint32_t PORT_GetPinsInterruptFlags(PORT_Type *base)
+{
+ return base->ISFR;
+}
+
+/*!
+ * @brief Clears the multiple pins' interrupt status flag.
+ *
+ * @param base PORT peripheral base pointer.
+ * @param mask PORT pins' numbers macro.
+ */
+static inline void PORT_ClearPinsInterruptFlags(PORT_Type *base, uint32_t mask)
+{
+ base->ISFR = mask;
+}
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_PORT_H_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.c
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diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.c b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.c
new file mode 100644
index 0000000..538f687
--- /dev/null
+++ b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rcm.h"
+
+void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+ uint32_t reg;
+
+ reg = (((uint32_t)config->enableFilterInStop << RCM_RPC_RSTFLTSS_SHIFT) | (uint32_t)config->filterInRunWait);
+ if (config->filterInRunWait == kRCM_FilterBusClock)
+ {
+ reg |= ((uint32_t)config->busClockFilterCount << RCM_RPC_RSTFLTSEL_SHIFT);
+ }
+ base->RPC = reg;
+#else
+ base->RPFC = ((uint8_t)(config->enableFilterInStop << RCM_RPFC_RSTFLTSS_SHIFT) | (uint8_t)config->filterInRunWait);
+ if (config->filterInRunWait == kRCM_FilterBusClock)
+ {
+ base->RPFW = config->busClockFilterCount;
+ }
+#endif /* FSL_FEATURE_RCM_REG_WIDTH */
+}
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config)
+{
+ uint32_t reg;
+
+ reg = base->FM;
+ reg &= ~RCM_FM_FORCEROM_MASK;
+ reg |= ((uint32_t)config << RCM_FM_FORCEROM_SHIFT);
+ base->FM = reg;
+}
+#endif /* #if FSL_FEATURE_RCM_HAS_BOOTROM */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.h
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diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.h b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.h
new file mode 100644
index 0000000..81e2555
--- /dev/null
+++ b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rcm.h
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RCM_H_
+#define _FSL_RCM_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup rcm */
+/*! @{*/
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief RCM driver version 2.0.0. */
+#define FSL_RCM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*!
+ * @brief System Reset Source Name definitions
+ */
+typedef enum _rcm_reset_source
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+/* RCM register bit width is 32. */
+#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
+ kRCM_SourceWakeup = RCM_SRS_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
+#endif
+ kRCM_SourceLvd = RCM_SRS_LVD_MASK, /*!< low voltage detect reset */
+#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
+ kRCM_SourceLoc = RCM_SRS_LOC_MASK, /*!< Loss of clock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOC */
+#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
+ kRCM_SourceLol = RCM_SRS_LOL_MASK, /*!< Loss of lock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOL */
+ kRCM_SourceWdog = RCM_SRS_WDOG_MASK, /*!< Watchdog reset */
+ kRCM_SourcePin = RCM_SRS_PIN_MASK, /*!< External pin reset */
+ kRCM_SourcePor = RCM_SRS_POR_MASK, /*!< Power on reset */
+#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
+ kRCM_SourceJtag = RCM_SRS_JTAG_MASK, /*!< JTAG generated reset */
+#endif /* FSL_FEATURE_RCM_HAS_JTAG */
+ kRCM_SourceLockup = RCM_SRS_LOCKUP_MASK, /*!< Core lock up reset */
+ kRCM_SourceSw = RCM_SRS_SW_MASK, /*!< Software reset */
+#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
+ kRCM_SourceMdmap = RCM_SRS_MDM_AP_MASK, /*!< MDM-AP system reset */
+#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
+#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
+ kRCM_SourceEzpt = RCM_SRS_EZPT_MASK, /*!< EzPort reset */
+#endif /* FSL_FEATURE_RCM_HAS_EZPORT */
+ kRCM_SourceSackerr = RCM_SRS_SACKERR_MASK, /*!< Parameter could get all reset flags */
+
+#else /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+/* RCM register bit width is 8. */
+#if (defined(FSL_FEATURE_RCM_HAS_WAKEUP) && FSL_FEATURE_RCM_HAS_WAKEUP)
+ kRCM_SourceWakeup = RCM_SRS0_WAKEUP_MASK, /*!< Low-leakage wakeup reset */
+#endif
+ kRCM_SourceLvd = RCM_SRS0_LVD_MASK, /*!< low voltage detect reset */
+#if (defined(FSL_FEATURE_RCM_HAS_LOC) && FSL_FEATURE_RCM_HAS_LOC)
+ kRCM_SourceLoc = RCM_SRS0_LOC_MASK, /*!< Loss of clock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOC */
+#if (defined(FSL_FEATURE_RCM_HAS_LOL) && FSL_FEATURE_RCM_HAS_LOL)
+ kRCM_SourceLol = RCM_SRS0_LOL_MASK, /*!< Loss of lock reset */
+#endif /* FSL_FEATURE_RCM_HAS_LOL */
+ kRCM_SourceWdog = RCM_SRS0_WDOG_MASK, /*!< Watchdog reset */
+ kRCM_SourcePin = RCM_SRS0_PIN_MASK, /*!< External pin reset */
+ kRCM_SourcePor = RCM_SRS0_POR_MASK, /*!< Power on reset */
+#if (defined(FSL_FEATURE_RCM_HAS_JTAG) && FSL_FEATURE_RCM_HAS_JTAG)
+ kRCM_SourceJtag = RCM_SRS1_JTAG_MASK << 8U, /*!< JTAG generated reset */
+#endif /* FSL_FEATURE_RCM_HAS_JTAG */
+ kRCM_SourceLockup = RCM_SRS1_LOCKUP_MASK << 8U, /*!< Core lock up reset */
+ kRCM_SourceSw = RCM_SRS1_SW_MASK, /*!< Software reset */
+#if (defined(FSL_FEATURE_RCM_HAS_MDM_AP) && FSL_FEATURE_RCM_HAS_MDM_AP)
+ kRCM_SourceMdmap = RCM_SRS1_MDM_AP_MASK << 8U, /*!< MDM-AP system reset */
+#endif /* FSL_FEATURE_RCM_HAS_MDM_AP */
+#if (defined(FSL_FEATURE_RCM_HAS_EZPORT) && FSL_FEATURE_RCM_HAS_EZPORT)
+ kRCM_SourceEzpt = RCM_SRS1_EZPT_MASK << 8U, /*!< EzPort reset */
+#endif /* FSL_FEATURE_RCM_HAS_EZPORT */
+ kRCM_SourceSackerr = RCM_SRS1_SACKERR_MASK << 8U, /*!< Parameter could get all reset flags */
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+ kRCM_SourceAll = 0xffffffffU,
+} rcm_reset_source_t;
+
+/*!
+ * @brief Reset pin filter select in Run and Wait modes
+ */
+typedef enum _rcm_run_wait_filter_mode
+{
+ kRCM_FilterDisable = 0U, /*!< All filtering disabled */
+ kRCM_FilterBusClock = 1U, /*!< Bus clock filter enabled */
+ kRCM_FilterLpoClock = 2U /*!< LPO clock filter enabled */
+} rcm_run_wait_filter_mode_t;
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * @brief Boot from ROM configuration.
+ */
+typedef enum _rcm_boot_rom_config
+{
+ kRCM_BootFlash = 0U, /*!< Boot from flash */
+ kRCM_BootRomCfg0 = 1U, /*!< Boot from boot ROM due to BOOTCFG0 */
+ kRCM_BootRomFopt = 2U, /*!< Boot from boot ROM due to FOPT[7] */
+ kRCM_BootRomBoth = 3U /*!< Boot from boot ROM due to both BOOTCFG0 and FOPT[7] */
+} rcm_boot_rom_config_t;
+#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
+
+#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
+/*!
+ * @brief Max delay time from interrupt asserts to system reset.
+ */
+typedef enum _rcm_reset_delay
+{
+ kRCM_ResetDelay8Lpo = 0U, /*!< Delay 8 LPO cycles. */
+ kRCM_ResetDelay32Lpo = 1U, /*!< Delay 32 LPO cycles. */
+ kRCM_ResetDelay128Lpo = 2U, /*!< Delay 128 LPO cycles. */
+ kRCM_ResetDelay512Lpo = 3U /*!< Delay 512 LPO cycles. */
+} rcm_reset_delay_t;
+
+/*!
+ * @brief System reset interrupt enable bit definitions.
+ */
+typedef enum _rcm_interrupt_enable
+{
+ kRCM_IntNone = 0U, /*!< No interrupt enabled. */
+ kRCM_IntLossOfClk = RCM_SRIE_LOC_MASK, /*!< Loss of clock interrupt. */
+ kRCM_IntLossOfLock = RCM_SRIE_LOL_MASK, /*!< Loss of lock interrupt. */
+ kRCM_IntWatchDog = RCM_SRIE_WDOG_MASK, /*!< Watch dog interrupt. */
+ kRCM_IntExternalPin = RCM_SRIE_PIN_MASK, /*!< External pin interrupt. */
+ kRCM_IntGlobal = RCM_SRIE_GIE_MASK, /*!< Global interrupts. */
+ kRCM_IntCoreLockup = RCM_SRIE_LOCKUP_MASK, /*!< Core lock up interrupt */
+ kRCM_IntSoftware = RCM_SRIE_SW_MASK, /*!< software interrupt */
+ kRCM_IntStopModeAckErr = RCM_SRIE_SACKERR_MASK, /*!< Stop mode ACK error interrupt. */
+#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
+ kRCM_IntCore1 = RCM_SRIE_CORE1_MASK, /*!< Core 1 interrupt. */
+#endif
+ kRCM_IntAll = RCM_SRIE_LOC_MASK /*!< Enable all interrupts. */
+ |
+ RCM_SRIE_LOL_MASK | RCM_SRIE_WDOG_MASK | RCM_SRIE_PIN_MASK | RCM_SRIE_GIE_MASK |
+ RCM_SRIE_LOCKUP_MASK | RCM_SRIE_SW_MASK | RCM_SRIE_SACKERR_MASK
+#if (defined(FSL_FEATURE_RCM_HAS_CORE1) && FSL_FEATURE_RCM_HAS_CORE1)
+ |
+ RCM_SRIE_CORE1_MASK
+#endif
+} rcm_interrupt_enable_t;
+#endif /* FSL_FEATURE_RCM_HAS_SRIE */
+
+#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
+/*!
+ * @brief IP version ID definition.
+ */
+typedef struct _rcm_version_id
+{
+ uint16_t feature; /*!< Feature Specification Number. */
+ uint8_t minor; /*!< Minor version number. */
+ uint8_t major; /*!< Major version number. */
+} rcm_version_id_t;
+#endif
+
+/*!
+ * @brief Reset pin filter configuration
+ */
+typedef struct _rcm_reset_pin_filter_config
+{
+ bool enableFilterInStop; /*!< Reset pin filter select in stop mode. */
+ rcm_run_wait_filter_mode_t filterInRunWait; /*!< Reset pin filter in run/wait mode. */
+ uint8_t busClockFilterCount; /*!< Reset pin bus clock filter width. */
+} rcm_reset_pin_filter_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*! @name Reset Control Module APIs*/
+/*@{*/
+
+#if (defined(FSL_FEATURE_RCM_HAS_VERID) && FSL_FEATURE_RCM_HAS_VERID)
+/*!
+ * @brief Gets the RCM version ID.
+ *
+ * This function gets the RCM version ID including the major version number,
+ * the minor version number, and the feature specification number.
+ *
+ * @param base RCM peripheral base address.
+ * @param versionId Pointer to version ID structure.
+ */
+static inline void RCM_GetVersionId(RCM_Type *base, rcm_version_id_t *versionId)
+{
+ *((uint32_t *)versionId) = base->VERID;
+}
+#endif
+
+#if (defined(FSL_FEATURE_RCM_HAS_PARAM) && FSL_FEATURE_RCM_HAS_PARAM)
+/*!
+ * @brief Gets the reset source implemented status.
+ *
+ * This function gets the RCM parameter that indicates whether the corresponding reset source is implemented.
+ * Use source masks defined in the rcm_reset_source_t to get the desired source status.
+ *
+ * Example:
+ @code
+ uint32_t status;
+
+ // To test whether the MCU is reset using Watchdog.
+ status = RCM_GetResetSourceImplementedStatus(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+ @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source implemented status bit map.
+ */
+static inline uint32_t RCM_GetResetSourceImplementedStatus(RCM_Type *base)
+{
+ return base->PARAM;
+}
+#endif /* FSL_FEATURE_RCM_HAS_PARAM */
+
+/*!
+ * @brief Gets the reset source status which caused a previous reset.
+ *
+ * This function gets the current reset source status. Use source masks
+ * defined in the rcm_reset_source_t to get the desired source status.
+ *
+ * Example:
+ @code
+ uint32_t resetStatus;
+
+ // To get all reset source statuses.
+ resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceAll;
+
+ // To test whether the MCU is reset using Watchdog.
+ resetStatus = RCM_GetPreviousResetSources(RCM) & kRCM_SourceWdog;
+
+ // To test multiple reset sources.
+ resetStatus = RCM_GetPreviousResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+ @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t RCM_GetPreviousResetSources(RCM_Type *base)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+ return base->SRS;
+#else
+ return (uint32_t)((uint32_t)base->SRS0 | ((uint32_t)base->SRS1 << 8U));
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+
+#if (defined(FSL_FEATURE_RCM_HAS_SSRS) && FSL_FEATURE_RCM_HAS_SSRS)
+/*!
+ * @brief Gets the sticky reset source status.
+ *
+ * This function gets the current reset source status that has not been cleared
+ * by software for some specific source.
+ *
+ * Example:
+ @code
+ uint32_t resetStatus;
+
+ // To get all reset source statuses.
+ resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceAll;
+
+ // To test whether the MCU is reset using Watchdog.
+ resetStatus = RCM_GetStickyResetSources(RCM) & kRCM_SourceWdog;
+
+ // To test multiple reset sources.
+ resetStatus = RCM_GetStickyResetSources(RCM) & (kRCM_SourceWdog | kRCM_SourcePin);
+ @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @return All reset source status bit map.
+ */
+static inline uint32_t RCM_GetStickyResetSources(RCM_Type *base)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+ return base->SSRS;
+#else
+ return (base->SSRS0 | ((uint32_t)base->SSRS1 << 8U));
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+
+/*!
+ * @brief Clears the sticky reset source status.
+ *
+ * This function clears the sticky system reset flags indicated by source masks.
+ *
+ * Example:
+ @code
+ // Clears multiple reset sources.
+ RCM_ClearStickyResetSources(kRCM_SourceWdog | kRCM_SourcePin);
+ @endcode
+ *
+ * @param base RCM peripheral base address.
+ * @param sourceMasks reset source status bit map
+ */
+static inline void RCM_ClearStickyResetSources(RCM_Type *base, uint32_t sourceMasks)
+{
+#if (defined(FSL_FEATURE_RCM_REG_WIDTH) && (FSL_FEATURE_RCM_REG_WIDTH == 32))
+ base->SSRS = sourceMasks;
+#else
+ base->SSRS0 = (sourceMasks & 0xffU);
+ base->SSRS1 = ((sourceMasks >> 8U) & 0xffU);
+#endif /* (FSL_FEATURE_RCM_REG_WIDTH == 32) */
+}
+#endif /* FSL_FEATURE_RCM_HAS_SSRS */
+
+/*!
+ * @brief Configures the reset pin filter.
+ *
+ * This function sets the reset pin filter including the filter source, filter
+ * width, and so on.
+ *
+ * @param base RCM peripheral base address.
+ * @param config Pointer to the configuration structure.
+ */
+void RCM_ConfigureResetPinFilter(RCM_Type *base, const rcm_reset_pin_filter_config_t *config);
+
+#if (defined(FSL_FEATURE_RCM_HAS_EZPMS) && FSL_FEATURE_RCM_HAS_EZPMS)
+/*!
+ * @brief Gets the EZP_MS_B pin assert status.
+ *
+ * This function gets the easy port mode status (EZP_MS_B) pin assert status.
+ *
+ * @param base RCM peripheral base address.
+ * @return status true - asserted, false - reasserted
+ */
+static inline bool RCM_GetEasyPortModePinStatus(RCM_Type *base)
+{
+ return (bool)(base->MR & RCM_MR_EZP_MS_MASK);
+}
+#endif /* FSL_FEATURE_RCM_HAS_EZPMS */
+
+#if (defined(FSL_FEATURE_RCM_HAS_BOOTROM) && FSL_FEATURE_RCM_HAS_BOOTROM)
+/*!
+ * @brief Gets the ROM boot source.
+ *
+ * This function gets the ROM boot source during the last chip reset.
+ *
+ * @param base RCM peripheral base address.
+ * @return The ROM boot source.
+ */
+static inline rcm_boot_rom_config_t RCM_GetBootRomSource(RCM_Type *base)
+{
+ return (rcm_boot_rom_config_t)((base->MR & RCM_MR_BOOTROM_MASK) >> RCM_MR_BOOTROM_SHIFT);
+}
+
+/*!
+ * @brief Clears the ROM boot source flag.
+ *
+ * This function clears the ROM boot source flag.
+ *
+ * @param base Register base address of RCM
+ */
+static inline void RCM_ClearBootRomSource(RCM_Type *base)
+{
+ base->MR |= RCM_MR_BOOTROM_MASK;
+}
+
+/*!
+ * @brief Forces the boot from ROM.
+ *
+ * This function forces booting from ROM during all subsequent system resets.
+ *
+ * @param base RCM peripheral base address.
+ * @param config Boot configuration.
+ */
+void RCM_SetForceBootRomSource(RCM_Type *base, rcm_boot_rom_config_t config);
+#endif /* FSL_FEATURE_RCM_HAS_BOOTROM */
+
+#if (defined(FSL_FEATURE_RCM_HAS_SRIE) && FSL_FEATURE_RCM_HAS_SRIE)
+/*!
+ * @brief Sets the system reset interrupt configuration.
+ *
+ * For graceful shutdown, the RCM supports delaying the assertion of the system
+ * reset for a period of time when the reset interrupt is generated. This function
+ * can be used to enable the interrupt and the delay period. The interrupts
+ * are passed in as bit mask. See rcm_int_t for details. For example, to
+ * delay a reset for 512 LPO cycles after the WDOG timeout or loss-of-clock occurs,
+ * configure as follows:
+ * RCM_SetSystemResetInterruptConfig(kRCM_IntWatchDog | kRCM_IntLossOfClk, kRCM_ResetDelay512Lpo);
+ *
+ * @param base RCM peripheral base address.
+ * @param intMask Bit mask of the system reset interrupts to enable. See
+ * rcm_interrupt_enable_t for details.
+ * @param Delay Bit mask of the system reset interrupts to enable.
+ */
+static inline void RCM_SetSystemResetInterruptConfig(RCM_Type *base, uint32_t intMask, rcm_reset_delay_t delay)
+{
+ base->SRIE = (intMask | delay);
+}
+#endif /* FSL_FEATURE_RCM_HAS_SRIE */
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*! @}*/
+
+#endif /* _FSL_RCM_H_ */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.c b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.c
new file mode 100644
index 0000000..9be2749
--- /dev/null
+++ b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rnga.h"
+
+#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*******************************************************************************
+ * RNG_CR - RNGA Control Register
+ ******************************************************************************/
+/*!
+ * @brief RNG_CR - RNGA Control Register (RW)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Controls the operation of RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_CR register
+ */
+/*@{*/
+#define RNG_CR_REG(base) ((base)->CR)
+#define RNG_RD_CR(base) (RNG_CR_REG(base))
+#define RNG_WR_CR(base, value) (RNG_CR_REG(base) = (value))
+#define RNG_RMW_CR(base, mask, value) (RNG_WR_CR(base, (RNG_RD_CR(base) & ~(mask)) | (value)))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field GO[0] (RW)
+ *
+ * Specifies whether random-data generation and loading (into OR[RANDOUT]) is
+ * enabled.This field is sticky. You must reset RNGA to stop RNGA from loading
+ * OR[RANDOUT] with data.
+ *
+ * Values:
+ * - 0b0 - Disabled
+ * - 0b1 - Enabled
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_GO field. */
+#define RNG_RD_CR_GO(base) ((RNG_CR_REG(base) & RNG_CR_GO_MASK) >> RNG_CR_GO_SHIFT)
+
+/*! @brief Set the GO field to a new value. */
+#define RNG_WR_CR_GO(base, value) (RNG_RMW_CR(base, RNG_CR_GO_MASK, RNG_CR_GO(value)))
+/*@}*/
+
+/*!
+ * @name Register RNG_CR, field SLP[4] (RW)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_CR_SLP field. */
+#define RNG_RD_CR_SLP(base) ((RNG_CR_REG(base) & RNG_CR_SLP_MASK) >> RNG_CR_SLP_SHIFT)
+
+/*! @brief Set the SLP field to a new value. */
+#define RNG_WR_CR_SLP(base, value) (RNG_RMW_CR(base, RNG_CR_SLP_MASK, RNG_CR_SLP(value)))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_SR - RNGA Status Register
+ ******************************************************************************/
+#define RNG_SR_REG(base) ((base)->SR)
+
+/*!
+ * @name Register RNG_SR, field OREG_LVL[15:8] (RO)
+ *
+ * Indicates the number of random-data words that are in OR[RANDOUT], which
+ * indicates whether OR[RANDOUT] is valid.If you read OR[RANDOUT] when SR[OREG_LVL]
+ * is not 0, then the contents of a random number contained in OR[RANDOUT] are
+ * returned, and RNGA writes 0 to both OR[RANDOUT] and SR[OREG_LVL].
+ *
+ * Values:
+ * - 0b00000000 - No words (empty)
+ * - 0b00000001 - One word (valid)
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_OREG_LVL field. */
+#define RNG_RD_SR_OREG_LVL(base) ((RNG_SR_REG(base) & RNG_SR_OREG_LVL_MASK) >> RNG_SR_OREG_LVL_SHIFT)
+/*@}*/
+
+/*!
+ * @name Register RNG_SR, field SLP[4] (RO)
+ *
+ * Specifies whether RNGA is in Sleep or Normal mode. You can also enter Sleep
+ * mode by asserting the DOZE signal.
+ *
+ * Values:
+ * - 0b0 - Normal mode
+ * - 0b1 - Sleep (low-power) mode
+ */
+/*@{*/
+/*! @brief Read current value of the RNG_SR_SLP field. */
+#define RNG_RD_SR_SLP(base) ((RNG_SR_REG(base) & RNG_SR_SLP_MASK) >> RNG_SR_SLP_SHIFT)
+/*@}*/
+
+/*******************************************************************************
+ * RNG_OR - RNGA Output Register
+ ******************************************************************************/
+/*!
+ * @brief RNG_OR - RNGA Output Register (RO)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Stores a random-data word generated by RNGA.
+ */
+/*!
+ * @name Constants and macros for entire RNG_OR register
+ */
+/*@{*/
+#define RNG_OR_REG(base) ((base)->OR)
+#define RNG_RD_OR(base) (RNG_OR_REG(base))
+/*@}*/
+
+/*******************************************************************************
+ * RNG_ER - RNGA Entropy Register
+ ******************************************************************************/
+/*!
+ * @brief RNG_ER - RNGA Entropy Register (WORZ)
+ *
+ * Reset value: 0x00000000U
+ *
+ * Specifies an entropy value that RNGA uses in addition to its ring oscillators
+ * to seed its pseudorandom algorithm. This is a write-only register; reads
+ * return all zeros.
+ */
+/*!
+ * @name Constants and macros for entire RNG_ER register
+ */
+/*@{*/
+#define RNG_ER_REG(base) ((base)->ER)
+#define RNG_RD_ER(base) (RNG_ER_REG(base))
+#define RNG_WR_ER(base, value) (RNG_ER_REG(base) = (value))
+/*@}*/
+
+/*******************************************************************************
+ * Prototypes
+ *******************************************************************************/
+
+static uint32_t rnga_ReadEntropy(RNG_Type *base);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+void RNGA_Init(RNG_Type *base)
+{
+ /* Enable the clock gate. */
+ CLOCK_EnableClock(kCLOCK_Rnga0);
+ CLOCK_DisableClock(kCLOCK_Rnga0); /* To solve the release version on twrkm43z75m */
+ CLOCK_EnableClock(kCLOCK_Rnga0);
+
+ /* Reset the registers for RNGA module to reset state. */
+ RNG_WR_CR(base, 0);
+ /* Enables the RNGA random data generation and loading.*/
+ RNG_WR_CR_GO(base, 1);
+}
+
+void RNGA_Deinit(RNG_Type *base)
+{
+ /* Disable the clock for RNGA module.*/
+ CLOCK_DisableClock(kCLOCK_Rnga0);
+}
+
+/*!
+ * @brief Get a random data from RNGA.
+ *
+ * @param base RNGA base address
+ */
+static uint32_t rnga_ReadEntropy(RNG_Type *base)
+{
+ uint32_t data = 0;
+ if (RNGA_GetMode(base) == kRNGA_ModeNormal) /* Is in normal mode.*/
+ {
+ /* Wait for valid random-data.*/
+ while (RNG_RD_SR_OREG_LVL(base) == 0)
+ {
+ }
+ data = RNG_RD_OR(base);
+ }
+ /* Get random-data word generated by RNGA.*/
+ return data;
+}
+
+status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size)
+{
+ status_t result = kStatus_Success;
+ uint32_t random_32;
+ uint8_t *random_p;
+ uint32_t random_size;
+ uint8_t *data_p = (uint8_t *)data;
+ uint32_t i;
+
+ /* Check input parameters.*/
+ if (base && data && data_size)
+ {
+ do
+ {
+ /* Read Entropy.*/
+ random_32 = rnga_ReadEntropy(base);
+
+ random_p = (uint8_t *)&random_32;
+
+ if (data_size < sizeof(random_32))
+ {
+ random_size = data_size;
+ }
+ else
+ {
+ random_size = sizeof(random_32);
+ }
+
+ for (i = 0; i < random_size; i++)
+ {
+ *data_p++ = *random_p++;
+ }
+
+ data_size -= random_size;
+ } while (data_size > 0);
+ }
+ else
+ {
+ result = kStatus_InvalidArgument;
+ }
+
+ return result;
+}
+
+void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode)
+{
+ RNG_WR_CR_SLP(base, (uint32_t)mode);
+}
+
+rnga_mode_t RNGA_GetMode(RNG_Type *base)
+{
+ return (rnga_mode_t)RNG_RD_SR_SLP(base);
+}
+
+void RNGA_Seed(RNG_Type *base, uint32_t seed)
+{
+ /* Write to RNGA Entropy Register.*/
+ RNG_WR_ER(base, seed);
+}
+
+#endif /* FSL_FEATURE_SOC_RNG_COUNT */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.h b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rnga.h
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@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RNGA_DRIVER_H_
+#define _FSL_RNGA_DRIVER_H_
+
+#include "fsl_common.h"
+
+#if defined(FSL_FEATURE_SOC_RNG_COUNT) && FSL_FEATURE_SOC_RNG_COUNT
+/*!
+ * @addtogroup rnga_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief RNGA driver version 2.0.1. */
+#define FSL_RNGA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*! @brief RNGA working mode */
+typedef enum _rnga_mode
+{
+ kRNGA_ModeNormal = 0U, /*!< Normal Mode. The ring-oscillator clocks are active; RNGA generates entropy
+ (randomness) from the clocks and stores it in shift registers.*/
+ kRNGA_ModeSleep = 1U, /*!< Sleep Mode. The ring-oscillator clocks are inactive; RNGA does not generate entropy.*/
+} rnga_mode_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Initializes the RNGA.
+ *
+ * This function initializes the RNGA.
+ * When called, the RNGA entropy generation starts immediately.
+ *
+ * @param base RNGA base address
+ */
+void RNGA_Init(RNG_Type *base);
+
+/*!
+ * @brief Shuts down the RNGA.
+ *
+ * This function shuts down the RNGA.
+ *
+ * @param base RNGA base address
+ */
+void RNGA_Deinit(RNG_Type *base);
+
+/*!
+ * @brief Gets random data.
+ *
+ * This function gets random data from the RNGA.
+ *
+ * @param base RNGA base address
+ * @param data pointer to user buffer to be filled by random data
+ * @param data_size size of data in bytes
+ * @return RNGA status
+ */
+status_t RNGA_GetRandomData(RNG_Type *base, void *data, size_t data_size);
+
+/*!
+ * @brief Feeds the RNGA module.
+ *
+ * This function inputs an entropy value that the RNGA uses to seed its
+ * pseudo-random algorithm.
+ *
+ * @param base RNGA base address
+ * @param seed input seed value
+ */
+void RNGA_Seed(RNG_Type *base, uint32_t seed);
+
+/*!
+ * @brief Sets the RNGA in normal mode or sleep mode.
+ *
+ * This function sets the RNGA in sleep mode or normal mode.
+ *
+ * @param base RNGA base address
+ * @param mode normal mode or sleep mode
+ */
+void RNGA_SetMode(RNG_Type *base, rnga_mode_t mode);
+
+/*!
+ * @brief Gets the RNGA working mode.
+ *
+ * This function gets the RNGA working mode.
+ *
+ * @param base RNGA base address
+ * @return normal mode or sleep mode
+ */
+rnga_mode_t RNGA_GetMode(RNG_Type *base);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_SOC_RNG_COUNT */
+#endif /* _FSL_RNGA_H_*/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rtc.c
----------------------------------------------------------------------
diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rtc.c b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rtc.c
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@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_rtc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define SECONDS_IN_A_DAY (86400U)
+#define SECONDS_IN_A_HOUR (3600U)
+#define SECONDS_IN_A_MINUTE (60U)
+#define DAYS_IN_A_YEAR (365U)
+#define YEAR_RANGE_START (1970U)
+#define YEAR_RANGE_END (2099U)
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Checks whether the date and time passed in is valid
+ *
+ * @param datetime Pointer to structure where the date and time details are stored
+ *
+ * @return Returns false if the date & time details are out of range; true if in range
+ */
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from datetime to seconds
+ *
+ * @param datetime Pointer to datetime structure where the date and time details are stored
+ *
+ * @return The result of the conversion in seconds
+ */
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Converts time data from seconds to a datetime structure
+ *
+ * @param seconds Seconds value that needs to be converted to datetime format
+ * @param datetime Pointer to the datetime structure where the result of the conversion is stored
+ */
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime);
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+static bool RTC_CheckDatetimeFormat(const rtc_datetime_t *datetime)
+{
+ /* Table of days in a month for a non leap year. First entry in the table is not used,
+ * valid months start from 1
+ */
+ uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+ /* Check year, month, hour, minute, seconds */
+ if ((datetime->year < YEAR_RANGE_START) || (datetime->year > YEAR_RANGE_END) || (datetime->month > 12U) ||
+ (datetime->month < 1U) || (datetime->hour >= 24U) || (datetime->minute >= 60U) || (datetime->second >= 60U))
+ {
+ /* If not correct then error*/
+ return false;
+ }
+
+ /* Adjust the days in February for a leap year */
+ if (!(datetime->year & 3U))
+ {
+ daysPerMonth[2] = 29U;
+ }
+
+ /* Check the validity of the day */
+ if (datetime->day > daysPerMonth[datetime->month])
+ {
+ return false;
+ }
+
+ return true;
+}
+
+static uint32_t RTC_ConvertDatetimeToSeconds(const rtc_datetime_t *datetime)
+{
+ /* Number of days from begin of the non Leap-year*/
+ uint16_t monthDays[] = {0U, 0U, 31U, 59U, 90U, 120U, 151U, 181U, 212U, 243U, 273U, 304U, 334U};
+ uint32_t seconds;
+
+ /* Compute number of days from 1970 till given year*/
+ seconds = (datetime->year - 1970U) * DAYS_IN_A_YEAR;
+ /* Add leap year days */
+ seconds += ((datetime->year / 4) - (1970U / 4));
+ /* Add number of days till given month*/
+ seconds += monthDays[datetime->month];
+ /* Add days in given month. We subtract the current day as it is
+ * represented in the hours, minutes and seconds field*/
+ seconds += (datetime->day - 1);
+ /* For leap year if month less than or equal to Febraury, decrement day counter*/
+ if ((!(datetime->year & 3U)) && (datetime->month <= 2U))
+ {
+ seconds--;
+ }
+
+ seconds = (seconds * SECONDS_IN_A_DAY) + (datetime->hour * SECONDS_IN_A_HOUR) +
+ (datetime->minute * SECONDS_IN_A_MINUTE) + datetime->second;
+
+ return seconds;
+}
+
+static void RTC_ConvertSecondsToDatetime(uint32_t seconds, rtc_datetime_t *datetime)
+{
+ uint32_t x;
+ uint32_t secondsRemaining, days;
+ uint16_t daysInYear;
+ /* Table of days in a month for a non leap year. First entry in the table is not used,
+ * valid months start from 1
+ */
+ uint8_t daysPerMonth[] = {0U, 31U, 28U, 31U, 30U, 31U, 30U, 31U, 31U, 30U, 31U, 30U, 31U};
+
+ /* Start with the seconds value that is passed in to be converted to date time format */
+ secondsRemaining = seconds;
+
+ /* Calcuate the number of days, we add 1 for the current day which is represented in the
+ * hours and seconds field
+ */
+ days = secondsRemaining / SECONDS_IN_A_DAY + 1;
+
+ /* Update seconds left*/
+ secondsRemaining = secondsRemaining % SECONDS_IN_A_DAY;
+
+ /* Calculate the datetime hour, minute and second fields */
+ datetime->hour = secondsRemaining / SECONDS_IN_A_HOUR;
+ secondsRemaining = secondsRemaining % SECONDS_IN_A_HOUR;
+ datetime->minute = secondsRemaining / 60U;
+ datetime->second = secondsRemaining % SECONDS_IN_A_MINUTE;
+
+ /* Calculate year */
+ daysInYear = DAYS_IN_A_YEAR;
+ datetime->year = YEAR_RANGE_START;
+ while (days > daysInYear)
+ {
+ /* Decrease day count by a year and increment year by 1 */
+ days -= daysInYear;
+ datetime->year++;
+
+ /* Adjust the number of days for a leap year */
+ if (datetime->year & 3U)
+ {
+ daysInYear = DAYS_IN_A_YEAR;
+ }
+ else
+ {
+ daysInYear = DAYS_IN_A_YEAR + 1;
+ }
+ }
+
+ /* Adjust the days in February for a leap year */
+ if (!(datetime->year & 3U))
+ {
+ daysPerMonth[2] = 29U;
+ }
+
+ for (x = 1U; x <= 12U; x++)
+ {
+ if (days <= daysPerMonth[x])
+ {
+ datetime->month = x;
+ break;
+ }
+ else
+ {
+ days -= daysPerMonth[x];
+ }
+ }
+
+ datetime->day = days;
+}
+
+void RTC_Init(RTC_Type *base, const rtc_config_t *config)
+{
+ assert(config);
+
+ uint32_t reg;
+
+ CLOCK_EnableClock(kCLOCK_Rtc0);
+
+ /* Issue a software reset if timer is invalid */
+ if (RTC_GetStatusFlags(RTC) & kRTC_TimeInvalidFlag)
+ {
+ RTC_Reset(RTC);
+ }
+
+ reg = base->CR;
+ /* Setup the update mode and supervisor access mode */
+ reg &= ~(RTC_CR_UM_MASK | RTC_CR_SUP_MASK);
+ reg |= RTC_CR_UM(config->updateMode) | RTC_CR_SUP(config->supervisorAccess);
+#if defined(FSL_FEATURE_RTC_HAS_WAKEUP_PIN) && FSL_FEATURE_RTC_HAS_WAKEUP_PIN
+ /* Setup the wakeup pin select */
+ reg &= ~(RTC_CR_WPS_MASK);
+ reg |= RTC_CR_WPS(config->wakeupSelect);
+#endif /* FSL_FEATURE_RTC_HAS_WAKEUP_PIN */
+ base->CR = reg;
+
+ /* Configure the RTC time compensation register */
+ base->TCR = (RTC_TCR_CIR(config->compensationInterval) | RTC_TCR_TCR(config->compensationTime));
+}
+
+void RTC_GetDefaultConfig(rtc_config_t *config)
+{
+ assert(config);
+
+ /* Wakeup pin will assert if the RTC interrupt asserts or if the wakeup pin is turned on */
+ config->wakeupSelect = false;
+ /* Registers cannot be written when locked */
+ config->updateMode = false;
+ /* Non-supervisor mode write accesses are not supported and will generate a bus error */
+ config->supervisorAccess = false;
+ /* Compensation interval used by the crystal compensation logic */
+ config->compensationInterval = 0;
+ /* Compensation time used by the crystal compensation logic */
+ config->compensationTime = 0;
+}
+
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
+{
+ assert(datetime);
+
+ /* Return error if the time provided is not valid */
+ if (!(RTC_CheckDatetimeFormat(datetime)))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ /* Set time in seconds */
+ base->TSR = RTC_ConvertDatetimeToSeconds(datetime);
+
+ return kStatus_Success;
+}
+
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime)
+{
+ assert(datetime);
+
+ uint32_t seconds = 0;
+
+ seconds = base->TSR;
+ RTC_ConvertSecondsToDatetime(seconds, datetime);
+}
+
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime)
+{
+ assert(alarmTime);
+
+ uint32_t alarmSeconds = 0;
+ uint32_t currSeconds = 0;
+
+ /* Return error if the alarm time provided is not valid */
+ if (!(RTC_CheckDatetimeFormat(alarmTime)))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ alarmSeconds = RTC_ConvertDatetimeToSeconds(alarmTime);
+
+ /* Get the current time */
+ currSeconds = base->TSR;
+
+ /* Return error if the alarm time has passed */
+ if (alarmSeconds < currSeconds)
+ {
+ return kStatus_Fail;
+ }
+
+ /* Set alarm in seconds*/
+ base->TAR = alarmSeconds;
+
+ return kStatus_Success;
+}
+
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime)
+{
+ assert(datetime);
+
+ uint32_t alarmSeconds = 0;
+
+ /* Get alarm in seconds */
+ alarmSeconds = base->TAR;
+
+ RTC_ConvertSecondsToDatetime(alarmSeconds, datetime);
+}
+
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask)
+{
+ /* The alarm flag is cleared by writing to the TAR register */
+ if (mask & kRTC_AlarmFlag)
+ {
+ base->TAR = 0U;
+ }
+
+ /* The timer overflow flag is cleared by initializing the TSR register.
+ * The time counter should be disabled for this write to be successful
+ */
+ if (mask & kRTC_TimeOverflowFlag)
+ {
+ base->TSR = 1U;
+ }
+
+ /* The timer overflow flag is cleared by initializing the TSR register.
+ * The time counter should be disabled for this write to be successful
+ */
+ if (mask & kRTC_TimeInvalidFlag)
+ {
+ base->TSR = 1U;
+ }
+}
+
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+
+void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter)
+{
+ *counter = (((uint64_t)base->MCHR << 32) | ((uint64_t)base->MCLR));
+}
+
+void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter)
+{
+ /* Prepare to initialize the register with the new value written */
+ base->MER &= ~RTC_MER_MCE_MASK;
+
+ base->MCHR = (uint32_t)((counter) >> 32);
+ base->MCLR = (uint32_t)(counter);
+}
+
+status_t RTC_IncrementMonotonicCounter(RTC_Type *base)
+{
+ if (base->SR & (RTC_SR_MOF_MASK | RTC_SR_TIF_MASK))
+ {
+ return kStatus_Fail;
+ }
+
+ /* Prepare to switch to increment mode */
+ base->MER |= RTC_MER_MCE_MASK;
+ /* Write anything so the counter increments*/
+ base->MCLR = 1U;
+
+ return kStatus_Success;
+}
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/f8f2ebbf/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rtc.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rtc.h b/hw/mcu/nxp/src/ext/sdk-2.0-frdm-k64f_b160321/devices/MK64F12/drivers/fsl_rtc.h
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index 0000000..063d1d4
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@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_RTC_H_
+#define _FSL_RTC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup rtc_driver
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+#define FSL_RTC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
+/*@}*/
+
+/*! @brief List of RTC interrupts */
+typedef enum _rtc_interrupt_enable
+{
+ kRTC_TimeInvalidInterruptEnable = RTC_IER_TIIE_MASK, /*!< Time invalid interrupt.*/
+ kRTC_TimeOverflowInterruptEnable = RTC_IER_TOIE_MASK, /*!< Time overflow interrupt.*/
+ kRTC_AlarmInterruptEnable = RTC_IER_TAIE_MASK, /*!< Alarm interrupt.*/
+ kRTC_SecondsInterruptEnable = RTC_IER_TSIE_MASK /*!< Seconds interrupt.*/
+} rtc_interrupt_enable_t;
+
+/*! @brief List of RTC flags */
+typedef enum _rtc_status_flags
+{
+ kRTC_TimeInvalidFlag = RTC_SR_TIF_MASK, /*!< Time invalid flag */
+ kRTC_TimeOverflowFlag = RTC_SR_TOF_MASK, /*!< Time overflow flag */
+ kRTC_AlarmFlag = RTC_SR_TAF_MASK /*!< Alarm flag*/
+} rtc_status_flags_t;
+
+/*! @brief List of RTC Oscillator capacitor load settings */
+typedef enum _rtc_osc_cap_load
+{
+ kRTC_Capacitor_2p = RTC_CR_SC2P_MASK, /*!< 2pF capacitor load */
+ kRTC_Capacitor_4p = RTC_CR_SC4P_MASK, /*!< 4pF capacitor load */
+ kRTC_Capacitor_8p = RTC_CR_SC8P_MASK, /*!< 8pF capacitor load */
+ kRTC_Capacitor_16p = RTC_CR_SC16P_MASK /*!< 16pF capacitor load */
+} rtc_osc_cap_load_t;
+
+/*! @brief Structure is used to hold the date and time */
+typedef struct _rtc_datetime
+{
+ uint16_t year; /*!< Range from 1970 to 2099.*/
+ uint8_t month; /*!< Range from 1 to 12.*/
+ uint8_t day; /*!< Range from 1 to 31 (depending on month).*/
+ uint8_t hour; /*!< Range from 0 to 23.*/
+ uint8_t minute; /*!< Range from 0 to 59.*/
+ uint8_t second; /*!< Range from 0 to 59.*/
+} rtc_datetime_t;
+
+/*!
+ * @brief RTC config structure
+ *
+ * This structure holds the configuration settings for the RTC peripheral. To initialize this
+ * structure to reasonable defaults, call the RTC_GetDefaultConfig() function and pass a
+ * pointer to your config structure instance.
+ *
+ * The config struct can be made const so it resides in flash
+ */
+typedef struct _rtc_config
+{
+ bool wakeupSelect; /*!< true: Wakeup pin outputs the 32KHz clock;
+ false:Wakeup pin used to wakeup the chip */
+ bool updateMode; /*!< true: Registers can be written even when locked under certain
+ conditions, false: No writes allowed when registers are locked */
+ bool supervisorAccess; /*!< true: Non-supervisor accesses are allowed;
+ false: Non-supervisor accesses are not supported */
+ uint32_t compensationInterval; /*!< Compensation interval that is written to the CIR field in RTC TCR Register */
+ uint32_t compensationTime; /*!< Compensation time that is written to the TCR field in RTC TCR Register */
+} rtc_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Ungates the RTC clock and configures the peripheral for basic operation.
+ *
+ * This function will issue a software reset if the timer invalid flag is set.
+ *
+ * @note This API should be called at the beginning of the application using the RTC driver.
+ *
+ * @param base RTC peripheral base address
+ * @param config Pointer to user's RTC config structure.
+ */
+void RTC_Init(RTC_Type *base, const rtc_config_t *config);
+
+/*!
+ * @brief Stop the timer and gate the RTC clock
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Deinit(RTC_Type *base)
+{
+ /* Stop the RTC timer */
+ base->SR &= ~RTC_SR_TCE_MASK;
+
+ /* Gate the module clock */
+ CLOCK_DisableClock(kCLOCK_Rtc0);
+}
+
+/*!
+ * @brief Fill in the RTC config struct with the default settings
+ *
+ * The default values are:
+ * @code
+ * config->wakeupSelect = false;
+ * config->updateMode = false;
+ * config->supervisorAccess = false;
+ * config->compensationInterval = 0;
+ * config->compensationTime = 0;
+ * @endcode
+ * @param config Pointer to user's RTC config structure.
+ */
+void RTC_GetDefaultConfig(rtc_config_t *config);
+
+/*! @}*/
+
+/*!
+ * @name Current Time & Alarm
+ * @{
+ */
+
+/*!
+ * @brief Sets the RTC date and time according to the given time structure.
+ *
+ * The RTC counter must be stopped prior to calling this function as writes to the RTC
+ * seconds register will fail if the RTC counter is running.
+ *
+ * @param base RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details to set are stored
+ *
+ * @return kStatus_Success: Success in setting the time and starting the RTC
+ * kStatus_InvalidArgument: Error because the datetime format is incorrect
+ */
+status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime);
+
+/*!
+ * @brief Gets the RTC time and stores it in the given time structure.
+ *
+ * @param base RTC peripheral base address
+ * @param datetime Pointer to structure where the date and time details are stored.
+ */
+void RTC_GetDatetime(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*!
+ * @brief Sets the RTC alarm time
+ *
+ * The function checks whether the specified alarm time is greater than the present
+ * time. If not, the function does not set the alarm and returns an error.
+ *
+ * @param base RTC peripheral base address
+ * @param alarmTime Pointer to structure where the alarm time is stored.
+ *
+ * @return kStatus_Success: success in setting the RTC alarm
+ * kStatus_InvalidArgument: Error because the alarm datetime format is incorrect
+ * kStatus_Fail: Error because the alarm time has already passed
+ */
+status_t RTC_SetAlarm(RTC_Type *base, const rtc_datetime_t *alarmTime);
+
+/*!
+ * @brief Returns the RTC alarm time.
+ *
+ * @param base RTC peripheral base address
+ * @param datetime Pointer to structure where the alarm date and time details are stored.
+ */
+void RTC_GetAlarm(RTC_Type *base, rtc_datetime_t *datetime);
+
+/*! @}*/
+
+/*!
+ * @name Interrupt Interface
+ * @{
+ */
+
+/*!
+ * @brief Enables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_EnableInterrupts(RTC_Type *base, uint32_t mask)
+{
+ base->IER |= mask;
+}
+
+/*!
+ * @brief Disables the selected RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The interrupts to enable. This is a logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+static inline void RTC_DisableInterrupts(RTC_Type *base, uint32_t mask)
+{
+ base->IER &= ~mask;
+}
+
+/*!
+ * @brief Gets the enabled RTC interrupts.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The enabled interrupts. This is the logical OR of members of the
+ * enumeration ::rtc_interrupt_enable_t
+ */
+static inline uint32_t RTC_GetEnabledInterrupts(RTC_Type *base)
+{
+ return (base->IER & (RTC_IER_TIIE_MASK | RTC_IER_TOIE_MASK | RTC_IER_TAIE_MASK | RTC_IER_TSIE_MASK));
+}
+
+/*! @}*/
+
+/*!
+ * @name Status Interface
+ * @{
+ */
+
+/*!
+ * @brief Gets the RTC status flags
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return The status flags. This is the logical OR of members of the
+ * enumeration ::rtc_status_flags_t
+ */
+static inline uint32_t RTC_GetStatusFlags(RTC_Type *base)
+{
+ return (base->SR & (RTC_SR_TIF_MASK | RTC_SR_TOF_MASK | RTC_SR_TAF_MASK));
+}
+
+/*!
+ * @brief Clears the RTC status flags.
+ *
+ * @param base RTC peripheral base address
+ * @param mask The status flags to clear. This is a logical OR of members of the
+ * enumeration ::rtc_status_flags_t
+ */
+void RTC_ClearStatusFlags(RTC_Type *base, uint32_t mask);
+
+/*! @}*/
+
+/*!
+ * @name Timer Start and Stop
+ * @{
+ */
+
+/*!
+ * @brief Starts the RTC time counter.
+ *
+ * After calling this function, the timer counter increments once a second provided SR[TOF] or
+ * SR[TIF] are not set.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StartTimer(RTC_Type *base)
+{
+ base->SR |= RTC_SR_TCE_MASK;
+}
+
+/*!
+ * @brief Stops the RTC time counter.
+ *
+ * RTC's seconds register can be written to only when the timer is stopped.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_StopTimer(RTC_Type *base)
+{
+ base->SR &= ~RTC_SR_TCE_MASK;
+}
+
+/*! @}*/
+
+/*!
+ * @brief This function sets the specified capacitor configuration for the RTC oscillator.
+ *
+ * @param base RTC peripheral base address
+ * @param capLoad Oscillator loads to enable. This is a logical OR of members of the
+ * enumeration ::rtc_osc_cap_load_t
+ */
+static inline void RTC_SetOscCapLoad(RTC_Type *base, uint32_t capLoad)
+{
+ uint32_t reg = base->CR;
+
+ reg &= ~(RTC_CR_SC2P_MASK | RTC_CR_SC4P_MASK | RTC_CR_SC8P_MASK | RTC_CR_SC16P_MASK);
+ reg |= capLoad;
+
+ base->CR = reg;
+}
+
+/*!
+ * @brief Performs a software reset on the RTC module.
+ *
+ * This resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR
+ * registers. The SWR bit is cleared by software explicitly clearing it.
+ *
+ * @param base RTC peripheral base address
+ */
+static inline void RTC_Reset(RTC_Type *base)
+{
+ base->CR |= RTC_CR_SWR_MASK;
+ base->CR &= ~RTC_CR_SWR_MASK;
+
+ /* Set TSR register to 0x1 to avoid the timer invalid (TIF) bit being set in the SR register */
+ base->TSR = 1U;
+}
+
+#if defined(FSL_FEATURE_RTC_HAS_MONOTONIC) && (FSL_FEATURE_RTC_HAS_MONOTONIC)
+
+/*!
+ * @name Monotonic counter functions
+ * @{
+ */
+
+/*!
+ * @brief Reads the values of the Monotonic Counter High and Monotonic Counter Low and returns
+ * them as a single value.
+ *
+ * @param base RTC peripheral base address
+ * @param counter Pointer to variable where the value is stored.
+ */
+void RTC_GetMonotonicCounter(RTC_Type *base, uint64_t *counter);
+
+/*!
+ * @brief Writes values Monotonic Counter High and Monotonic Counter Low by decomposing
+ * the given single value.
+ *
+ * @param base RTC peripheral base address
+ * @param counter Counter value
+ */
+void RTC_SetMonotonicCounter(RTC_Type *base, uint64_t counter);
+
+/*!
+ * @brief Increments the Monotonic Counter by one.
+ *
+ * Increments the Monotonic Counter (registers RTC_MCLR and RTC_MCHR accordingly) by setting
+ * the monotonic counter enable (MER[MCE]) and then writing to the RTC_MCLR register. A write to the
+ * monotonic counter low that causes it to overflow also increments the monotonic counter high.
+ *
+ * @param base RTC peripheral base address
+ *
+ * @return kStatus_Success: success
+ * kStatus_Fail: error occurred, either time invalid or monotonic overflow flag was found
+ */
+status_t RTC_IncrementMonotonicCounter(RTC_Type *base);
+
+/*! @}*/
+
+#endif /* FSL_FEATURE_RTC_HAS_MONOTONIC */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_RTC_H_ */