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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2022/04/26 10:42:43 UTC

[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a diff in pull request #6151: RISC-V: workaround for the RV64 SoC which does not has mem mapped MTI…

xiaoxiang781216 commented on code in PR #6151:
URL: https://github.com/apache/incubator-nuttx/pull/6151#discussion_r858563130


##########
arch/risc-v/src/common/riscv_mtimer.c:
##########
@@ -84,7 +84,13 @@ static const struct oneshot_operations_s g_riscv_mtimer_ops =
 static uint64_t riscv_mtimer_get_mtime(struct riscv_mtimer_lowerhalf_s *priv)
 {
 #ifdef CONFIG_ARCH_RV64
-  return getreg64(priv->mtime);

Review Comment:
   should we modify 32bit version too?



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