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Posted to commits@tvm.apache.org by GitBox <gi...@apache.org> on 2021/06/29 10:25:32 UTC
[GitHub] [tvm] HerrLieber opened a new issue #8365: When I run make under /home/libo/tvm-vta-main/apps/tsim_example I get an error
HerrLieber opened a new issue #8365:
URL: https://github.com/apache/tvm/issues/8365
I followed ../tvm-vta-main/apps/tsim_example/READ.md step by step
When I go to this step
Test Verilog backend
Go to <vta-hw-root>/apps/tsim_example
Run make
After running "make", the following error always appears.
(tvm-build) libo@ubuntu:~/tvm-vta-main/apps/tsim_example$ make
make -C hardware/verilog
make[1]: 进入目录“/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog”
g++ -O2 -Wall -fPIC -shared -fvisibility=hidden -std=c++11 -DVL_TSIM_NAME=VTestAccel -DVL_PRINTF=printf -DVL_USER_FINISH -DVM_COVERAGE=0 -DVM_SC=0 -Wno-sign-compare -include VTestAccel.h -I/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -I/home/libo/tvm-vta-main/include -I/home/include -I/home/3rdparty/dlpack/include -DVM_TRACE=0 /usr/share/verilator/include/verilated.cpp /usr/share/verilator/include/verilated_dpi.cpp /home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp /home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Slow.cpp /home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Syms.cpp /home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Dpi.cpp /home/libo/tvm-vta-main/hardware/dpi/tsim_device.cc -o /home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/libhw.so
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp: In static member function ‘static void VTestAccel::_sequent__TOP__1(VTestAccel__Syms*)’:
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp:488:13: warning: ‘__Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v15’ may be used uninitialized in this function [-Wmaybe-uninitialized]
487 | vlTOPp->TestAccel__DOT__accel__DOT__rf__DOT__rf[6U]
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
488 | = __Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v15;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp:481:13: warning: ‘__Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v13’ may be used uninitialized in this function [-Wmaybe-uninitialized]
480 | vlTOPp->TestAccel__DOT__accel__DOT__rf__DOT__rf[5U]
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
481 | = __Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v13;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp:474:13: warning: ‘__Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v11’ may be used uninitialized in this function [-Wmaybe-uninitialized]
473 | vlTOPp->TestAccel__DOT__accel__DOT__rf__DOT__rf[4U]
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
474 | = __Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v11;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp:154:19: warning: ‘__Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v9’ may be used uninitialized in this function [-Wmaybe-uninitialized]
154 | IData/*31:0*/ __Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v9;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel.cpp:460:13: warning: ‘__Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v7’ may be used uninitialized in this function [-Wmaybe-uninitialized]
459 | vlTOPp->TestAccel__DOT__accel__DOT__rf__DOT__rf[2U]
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
460 | = __Vdlyvval__TestAccel__DOT__accel__DOT__rf__DOT__rf__v7;
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Slow.cpp: In constructor ‘VTestAccel::VTestAccel(const char*)’:
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Slow.cpp:13:89: warning: ‘new’ of type ‘VTestAccel__Syms’ with extended alignment 64 [-Waligned-new=]
13 | trict vlSymsp = __VlSymsp = new VTestAccel__Syms(this, name());
| ^
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Slow.cpp:13:89: note: uses ‘void* operator new(long unsigned int)’, which does not have an alignment parameter
/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/VTestAccel__Slow.cpp:13:89: note: use ‘-faligned-new’ to enable C++17 over-aligned new support
In file included from /home/libo/tvm-vta-main/hardware/dpi/tsim_device.cc:22:
/home/libo/tvm-vta-main/include/vta/dpi/tsim.h:23:10: fatal error: tvm/runtime/c_runtime_api.h: 没有那个文件或目录
23 | #include <tvm/runtime/c_runtime_api.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [Makefile:97：/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog/build/libhw.so] 错误 1
make[1]: 离开目录“/home/libo/tvm-vta-main/apps/tsim_example/hardware/verilog”
make: *** [Makefile:38：verilog] 错误 2
The error is that this file does not exist(tvm/runtime/c_runtime_api.h). I searched through the entire folder and couldn't find this file. What should I do?
I want to simulate the FPGA with TSIM to get the running time of each layer.
Thanks for your Attention.
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[GitHub] [tvm] HerrLieber commented on issue #8365: When I run make under /home/libo/tvm-vta-main/apps/tsim_example I get an error
Posted by GitBox <gi...@apache.org>.
HerrLieber commented on issue #8365:
URL: https://github.com/apache/tvm/issues/8365#issuecomment-874189618
> You need to clone apache/tvm repo and set up tvm path.
Thanks for your reply.
But there is no tsim_example folder in apache/tvm/apps.
If I want to simulate the FPGA with TSIM to get the running time of each layer, what could I do?
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[GitHub] [tvm] HerrLieber commented on issue #8365: When I run make under /home/libo/tvm-vta-main/apps/tsim_example I get an error
Posted by GitBox <gi...@apache.org>.
HerrLieber commented on issue #8365:
URL: https://github.com/apache/tvm/issues/8365#issuecomment-874189618
> You need to clone apache/tvm repo and set up tvm path.
Thanks for your reply.
But there is no tsim_example folder in apache/tvm/apps.
If I want to simulate the FPGA with TSIM to get the running time of each layer, what could I do?
--
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[GitHub] [tvm] vinx13 commented on issue #8365: When I run make under /home/libo/tvm-vta-main/apps/tsim_example I get an error
Posted by GitBox <gi...@apache.org>.
vinx13 commented on issue #8365:
URL: https://github.com/apache/tvm/issues/8365#issuecomment-872442776
You need to clone apache/tvm repo and set up tvm path.
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[GitHub] [tvm] vinx13 closed issue #8365: When I run make under /home/libo/tvm-vta-main/apps/tsim_example I get an error
Posted by GitBox <gi...@apache.org>.
vinx13 closed issue #8365:
URL: https://github.com/apache/tvm/issues/8365
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