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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2020/12/03 22:49:07 UTC
[GitHub] [incubator-nuttx] hartmannathan opened a new pull request #2473: [DRAFT] Stm32g4 add adc
hartmannathan opened a new pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473
## Summary
STM32G4xx family: Add register mappings and bitfield definitions for ADC peripheral.
## Impact
One step toward supporting the ADC on this family.
## Testing
nxstyle
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[GitHub] [incubator-nuttx] raiden00pl merged pull request #2473: STM32 - Add ADC register definitions for STM32G4 family
Posted by GitBox <gi...@apache.org>.
raiden00pl merged pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #2473: [DRAFT] Stm32g4 add adc
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473#issuecomment-743371393
@davids5 , @raiden00pl , Thank you for your input. I've finished this up and it's ready for review.
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[GitHub] [incubator-nuttx] hartmannathan commented on pull request #2473: [DRAFT] Stm32g4 add adc
Posted by GitBox <gi...@apache.org>.
hartmannathan commented on pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473#issuecomment-738410736
@davids5 , @raiden00pl -
Suggestions/thoughts wanted:
The STM32G4xx family has a slightly newer IP version of the ADC. It resembles stm32_adc_v2 but has enough differences that I think adding more ifdef to stm32_adc_v2 will create a maintenance nightmare.
Which do you think is best?
- Call this file stm32_adc_v3?
- Call this file stm32_adc_v2g4?
- Merge this file into stm32_adc_v2 with additional ifdef?
Here is a summary of the differences between stm32_adc_v2 and this new file for STM32G4xx family:
- Addition of ADC5
- Common ADC345 instead of ADC34
- Addition of GCOMP register
- CR register: ADVREGEN field is only 1 bit wide instead of 2, but there is a new field, DEEPPWD.
- CFGR register: EXTSEL is 5 bits instead of 4; ALIGN at bit 15 instead of bit 5; addition of JQDIS bit.
- SMPR1, SMPR2 registers: All sample time options are different: instead of 1.5, 2.5, 4.5, 7.5, 19.5, 61.5, 181.5, or 601.5 cycles, STM32G4 provides these options: 2.5, 6.5, 12.5, 24.5, 47.5, 92.5, 247.5, and 640.5 cycles.
- Addition of Channel 0, i.e., SMPR1_SMP0.
- TR1 register: addition of AWDFILT field.
- JSQR register: JSQ2, JSQ3, and JSQ4 bitfields are at different positions: instead of at bits 14, 20, 26, they are at bits 15, 21, 27.
- OFR1 thru OFR4 registers: Addition of OFR_OFFSETPOS and OFR_SATEN bits.
- AWD2CR, AWD3CR, and DIFSEL registers: Additional bit for Channel 0.
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[GitHub] [incubator-nuttx] davids5 commented on pull request #2473: [DRAFT] Stm32g4 add adc
Posted by GitBox <gi...@apache.org>.
davids5 commented on pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473#issuecomment-738757339
@hartmannathan.
Here is what I would do. I would have a look at some of the new chips ref manuals and see if the the IP is used there as well. (this was the case with the PLLs on the F7 etc) If so, I would call the file stm32_adc_v3. If not and it is a G4 only thing, I would call this file stm32_adc_v2g4 if it is a G4 family (do a survey of the family) then name it stm32_adc_v2g4xxx with the x masking the common family element.
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[GitHub] [incubator-nuttx] raiden00pl commented on pull request #2473: [DRAFT] Stm32g4 add adc
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on pull request #2473:
URL: https://github.com/apache/incubator-nuttx/pull/2473#issuecomment-738791558
@hartmannathan
I think this is a similar situation to the STM32L1 case where we are dealing with a modified version of ADCv1.
In the case of STM32G4 we have a modified version of ADCv2 so the name stm32_adc_v2g4 should be appropriate.
It's probably also a good time to separate the ADCv1 code from the ADCv2 code.
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