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Posted to commits@mynewt.apache.org by ut...@apache.org on 2019/09/24 15:36:43 UTC
[mynewt-core] 02/05: [STM32F4] Turn off BSP's HSI
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit d2fe35ed7db904cc067aceffa65db9995accfdcc
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Fri Aug 30 09:05:10 2019 -0300
[STM32F4] Turn off BSP's HSI
---
hw/bsp/black_vet6/syscfg.yml | 1 +
hw/bsp/nucleo-f401re/syscfg.yml | 1 +
hw/bsp/nucleo-f413zh/syscfg.yml | 1 +
hw/bsp/nucleo-f439zi/syscfg.yml | 1 +
hw/bsp/olimex_stm32-e407_devboard/syscfg.yml | 1 +
hw/bsp/stm32f429discovery/syscfg.yml | 1 +
hw/bsp/stm32f4discovery/syscfg.yml | 1 +
7 files changed, 7 insertions(+)
diff --git a/hw/bsp/black_vet6/syscfg.yml b/hw/bsp/black_vet6/syscfg.yml
index 7a9ec7b..d1c2d3d 100644
--- a/hw/bsp/black_vet6/syscfg.yml
+++ b/hw/bsp/black_vet6/syscfg.yml
@@ -125,6 +125,7 @@ syscfg.vals:
HARDFLOAT: 1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_PLL_PLLM: 8
STM32_CLOCK_PLL_PLLN: 336
diff --git a/hw/bsp/nucleo-f401re/syscfg.yml b/hw/bsp/nucleo-f401re/syscfg.yml
index 53d0dd8..503ba8f 100644
--- a/hw/bsp/nucleo-f401re/syscfg.yml
+++ b/hw/bsp/nucleo-f401re/syscfg.yml
@@ -40,6 +40,7 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE2'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 1
STM32_CLOCK_PLL_PLLM: 8
diff --git a/hw/bsp/nucleo-f413zh/syscfg.yml b/hw/bsp/nucleo-f413zh/syscfg.yml
index db3c285..be59dd3 100644
--- a/hw/bsp/nucleo-f413zh/syscfg.yml
+++ b/hw/bsp/nucleo-f413zh/syscfg.yml
@@ -39,6 +39,7 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 1
STM32_CLOCK_PLL_PLLM: 8
diff --git a/hw/bsp/nucleo-f439zi/syscfg.yml b/hw/bsp/nucleo-f439zi/syscfg.yml
index a9cadd3..883485f 100644
--- a/hw/bsp/nucleo-f439zi/syscfg.yml
+++ b/hw/bsp/nucleo-f439zi/syscfg.yml
@@ -39,6 +39,7 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 1
STM32_CLOCK_PLL_PLLM: 8
diff --git a/hw/bsp/olimex_stm32-e407_devboard/syscfg.yml b/hw/bsp/olimex_stm32-e407_devboard/syscfg.yml
index ff7cfb8..e762aba 100644
--- a/hw/bsp/olimex_stm32-e407_devboard/syscfg.yml
+++ b/hw/bsp/olimex_stm32-e407_devboard/syscfg.yml
@@ -53,6 +53,7 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 0
STM32_CLOCK_PLL_PLLM: 12
diff --git a/hw/bsp/stm32f429discovery/syscfg.yml b/hw/bsp/stm32f429discovery/syscfg.yml
index 0a97c16..6fb516b 100644
--- a/hw/bsp/stm32f429discovery/syscfg.yml
+++ b/hw/bsp/stm32f429discovery/syscfg.yml
@@ -46,6 +46,7 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 1
STM32_CLOCK_PLL_PLLM: 8
diff --git a/hw/bsp/stm32f4discovery/syscfg.yml b/hw/bsp/stm32f4discovery/syscfg.yml
index 58233c8..464f9b4 100644
--- a/hw/bsp/stm32f4discovery/syscfg.yml
+++ b/hw/bsp/stm32f4discovery/syscfg.yml
@@ -46,6 +46,7 @@ syscfg.vals:
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
STM32_CLOCK_VOLTAGESCALING_CONFIG: 'PWR_REGULATOR_VOLTAGE_SCALE1'
+ STM32_CLOCK_HSI: 0
STM32_CLOCK_HSE: 1
STM32_CLOCK_HSE_BYPASS: 0
STM32_CLOCK_PLL_PLLM: 8