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Posted to commits@mynewt.apache.org by we...@apache.org on 2016/11/05 00:01:30 UTC
[2/4] incubator-mynewt-core git commit: MYNEWT-475: BSP Cleanup
MYNEWT-475: BSP Cleanup
Remove os_bsp.c by adding all its functionaltiy to hal_bsp.c
Project: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/repo
Commit: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/commit/60c1d227
Tree: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/tree/60c1d227
Diff: http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/diff/60c1d227
Branch: refs/heads/develop
Commit: 60c1d227d9a1681dff65f88650775275da238a14
Parents: 849c1e9
Author: William San Filippo <wi...@runtime.io>
Authored: Fri Nov 4 17:00:10 2016 -0700
Committer: William San Filippo <wi...@runtime.io>
Committed: Fri Nov 4 17:01:16 2016 -0700
----------------------------------------------------------------------
hw/bsp/arduino_primo_nrf52/src/hal_bsp.c | 152 ++++++++-
hw/bsp/arduino_primo_nrf52/src/os_bsp.c | 174 ----------
hw/bsp/bmd300eval/src/hal_bsp.c | 152 ++++++++-
hw/bsp/bmd300eval/src/os_bsp.c | 171 ----------
hw/bsp/frdm-k64f/src/hal_bsp.c | 93 +++++-
hw/bsp/frdm-k64f/src/os_bsp.c | 111 -------
hw/bsp/native/src/hal_bsp.c | 19 +-
hw/bsp/native/src/os_bsp.c | 38 ---
hw/bsp/nrf51-arduino_101/src/hal_bsp.c | 159 +++++++++
hw/bsp/nrf51-arduino_101/src/os_bsp.c | 184 -----------
hw/bsp/nrf51-blenano/src/hal_bsp.c | 104 ++++++
hw/bsp/nrf51-blenano/src/os_bsp.c | 126 -------
hw/bsp/nrf51dk-16kbram/src/hal_bsp.c | 114 +++++++
hw/bsp/nrf51dk-16kbram/src/os_bsp.c | 138 --------
hw/bsp/nrf51dk/src/hal_bsp.c | 115 +++++++
hw/bsp/nrf51dk/src/os_bsp.c | 141 --------
hw/bsp/nrf52dk/src/hal_bsp.c | 166 +++++++++-
hw/bsp/nrf52dk/src/os_bsp.c | 185 -----------
hw/bsp/olimex_stm32-e407_devboard/src/hal_bsp.c | 301 ++++++++++++++++-
hw/bsp/olimex_stm32-e407_devboard/src/os_bsp.c | 329 -------------------
hw/bsp/rb-nano2/src/hal_bsp.c | 124 ++++++-
hw/bsp/rb-nano2/src/os_bsp.c | 129 --------
22 files changed, 1477 insertions(+), 1748 deletions(-)
----------------------------------------------------------------------
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c b/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
index c7e7db4..9472119 100644
--- a/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
+++ b/hw/bsp/arduino_primo_nrf52/src/hal_bsp.c
@@ -19,14 +19,100 @@
#include <stdint.h>
#include <stddef.h>
#include <assert.h>
-
#include "bsp/bsp.h"
#include <nrf52.h>
-#include <hal/hal_bsp.h>
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_watchdog.h"
#include "mcu/nrf52_hal.h"
-
#include <os/os_dev.h>
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "flash_map/flash_map.h"
+#include "uart/uart.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_0_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#if MYNEWT_VAL(UART_0)
+#include "uart_hal/uart_hal.h"
+#endif
+#if MYNEWT_VAL(UART_1)
+#include "uart_bitbang/uart_bitbang.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "nrf.h"
+#include "app_error.h"
+#include "nrf_drv_saadc.h"
+#if MYNEWT_VAL(ADC_0)
+#include "adc_nrf52/adc_nrf52.h"
+#endif
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_bitbang_uart1;
+static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
+ .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
+ .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
+ .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
+};
+#endif
+#if MYNEWT_VAL(ADC_0)
+static struct adc_dev os_bsp_adc0;
+static struct nrf52_adc_dev_cfg os_bsp_adc0_config = {
+ .nadc_refmv = 2800
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 24,
+ .mosi_pin = 23,
+ .miso_pin = 22,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi0s_cfg = {
+ .sck_pin = 24,
+ .mosi_pin = 23,
+ .miso_pin = 22,
+ .csn_pin = 19,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
/*
* What memory to include in coredump.
@@ -87,3 +173,63 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
}
return cfg_pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ rc = hal_timer_init(3, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ rc = hal_timer_init(4, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_adc0, "adc0",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ nrf52_adc_dev_init, &os_bsp_adc0_config);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/arduino_primo_nrf52/src/os_bsp.c b/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
deleted file mode 100644
index 448a021..0000000
--- a/hw/bsp/arduino_primo_nrf52/src/os_bsp.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stdint.h>
-#include "os/os_cputime.h"
-#include "syscfg/syscfg.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_bsp.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_spi.h"
-#include "hal/hal_watchdog.h"
-#include "mcu/nrf52_hal.h"
-#include "uart/uart.h"
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_0_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#if MYNEWT_VAL(UART_0)
-#include "uart_hal/uart_hal.h"
-#endif
-#if MYNEWT_VAL(UART_1)
-#include "uart_bitbang/uart_bitbang.h"
-#endif
-#include "nrf_drv_config.h"
-#include "app_util_platform.h"
-#include "nrf.h"
-#include "app_error.h"
-#include "nrf_drv_saadc.h"
-
-#if MYNEWT_VAL(ADC_0)
-#include "adc_nrf52/adc_nrf52.h"
-#endif
-
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(UART_1)
-static struct uart_dev os_bsp_bitbang_uart1;
-static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
- .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
- .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
- .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
-};
-#endif
-
-#if MYNEWT_VAL(ADC_0)
-static struct adc_dev os_bsp_adc0;
-static struct nrf52_adc_dev_cfg os_bsp_adc0_config = {
- .nadc_refmv = 2800
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 24,
- .mosi_pin = 23,
- .miso_pin = 22,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi0s_cfg = {
- .sck_pin = 24,
- .mosi_pin = 23,
- .miso_pin = 22,
- .csn_pin = 19,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_3)
- rc = hal_timer_init(3, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_4)
- rc = hal_timer_init(4, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_0_SLAVE)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_1)
- rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
- OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(ADC_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_adc0, "adc0",
- OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
- nrf52_adc_dev_init, &os_bsp_adc0_config);
- assert(rc == 0);
-#endif
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/bmd300eval/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/src/hal_bsp.c b/hw/bsp/bmd300eval/src/hal_bsp.c
index b54e44f..d545611 100644
--- a/hw/bsp/bmd300eval/src/hal_bsp.c
+++ b/hw/bsp/bmd300eval/src/hal_bsp.c
@@ -16,13 +16,99 @@
* specific language governing permissions and limitations
* under the License.
*/
+
#include <stdint.h>
#include <stddef.h>
-
-#include "bsp/bsp.h"
-#include <hal/hal_bsp.h>
#include <nrf52.h>
+#include <assert.h>
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
#include "mcu/nrf52_hal.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+#include "os/os_dev.h"
+#include "bsp.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_0_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "nrf.h"
+#include "app_error.h"
+#include "nrf_drv_saadc.h"
+
+#if MYNEWT_VAL(ADC_0)
+#include "adc_nrf52/adc_nrf52.h"
+#endif
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_bitbang_uart1;
+static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
+ .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
+ .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
+ .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
+};
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+static struct adc_dev os_bsp_adc0;
+static struct nrf52_adc_dev_cfg os_bsp_adc0_config = {
+ .nadc_refmv = 2800
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 23,
+ .mosi_pin = 24,
+ .miso_pin = 25,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi0s_cfg = {
+ .sck_pin = 23,
+ .mosi_pin = 24,
+ .miso_pin = 25,
+ .csn_pin = 22,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
/*
* What memory to include in coredump.
@@ -83,3 +169,63 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
}
return cfg_pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ rc = hal_timer_init(3, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ rc = hal_timer_init(4, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_adc0, "adc0",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ nrf52_adc_dev_init, &os_bsp_adc0_config);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/bmd300eval/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/bmd300eval/src/os_bsp.c b/hw/bsp/bmd300eval/src/os_bsp.c
deleted file mode 100644
index 822f1a5..0000000
--- a/hw/bsp/bmd300eval/src/os_bsp.c
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stdint.h>
-#include "os/os_cputime.h"
-#include "syscfg/syscfg.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_bsp.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_spi.h"
-#include "mcu/nrf52_hal.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-#include "os/os_dev.h"
-#include "bsp.h"
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_0_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#include "nrf_drv_config.h"
-#include "app_util_platform.h"
-#include "nrf.h"
-#include "app_error.h"
-#include "nrf_drv_saadc.h"
-
-#if MYNEWT_VAL(ADC_0)
-#include "adc_nrf52/adc_nrf52.h"
-#endif
-
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(UART_1)
-static struct uart_dev os_bsp_bitbang_uart1;
-static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
- .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
- .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
- .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
-};
-#endif
-
-#if MYNEWT_VAL(ADC_0)
-static struct adc_dev os_bsp_adc0;
-static struct nrf52_adc_dev_cfg os_bsp_adc0_config = {
- .nadc_refmv = 2800
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .csn_pin = 22,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_3)
- rc = hal_timer_init(3, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_4)
- rc = hal_timer_init(4, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_0_SLAVE)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_1)
- rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
- OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(ADC_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_adc0, "adc0",
- OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
- nrf52_adc_dev_init, &os_bsp_adc0_config);
- assert(rc == 0);
-#endif
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/frdm-k64f/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/frdm-k64f/src/hal_bsp.c b/hw/bsp/frdm-k64f/src/hal_bsp.c
index a0bd707..0dd820f 100644
--- a/hw/bsp/frdm-k64f/src/hal_bsp.c
+++ b/hw/bsp/frdm-k64f/src/hal_bsp.c
@@ -16,18 +16,48 @@
* specific language governing permissions and limitations
* under the License.
*/
+
#include <stddef.h>
#include <stdint.h>
-#include <stdio.h>
#include <errno.h>
-
+#include <sys/types.h>
+#include <stdio.h>
+#include "os/os_dev.h"
+#include "syscfg/syscfg.h"
#include "bsp/bsp.h"
-#include "flash_map/flash_map.h"
-
#include "hal/hal_bsp.h"
#include "hal/hal_flash_int.h"
-
+#include "flash_map/flash_map.h"
+#include "hal/hal_flash.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+#include "hal/hal_uart.h"
+#include "bsp/cmsis_nvic.h"
#include "mcu/frdm-k64f_hal.h"
+#include "fsl_device_registers.h"
+#include "fsl_common.h"
+#include "fsl_clock.h"
+#include "fsl_port.h"
+#include "clock_config.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+#endif
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_uart1;
+#endif
+#if MYNEWT_VAL(UART_2)
+static struct uart_dev os_bsp_uart2;
+#endif
+#if MYNEWT_VAL(UART_3)
+static struct uart_dev os_bsp_uart3;
+#endif
+#if MYNEWT_VAL(UART_4)
+static struct uart_dev os_bsp_uart4;
+#endif
+#if MYNEWT_VAL(UART_5)
+static struct uart_dev os_bsp_uart5;
+#endif
/*
* What memory to include in coredump.
@@ -39,6 +69,18 @@ static const struct hal_bsp_mem_dump dump_cfg[] = {
}
};
+static void init_hardware(void)
+{
+ // Disable the MPU otherwise USB cannot access the bus
+ MPU->CESR = 0;
+
+ // Enable all the ports
+ SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
+ SIM_SCGC5_PORTE_MASK);
+}
+
+extern void BOARD_BootClockRUN(void);
+
const struct hal_flash *
hal_bsp_flash_dev(uint8_t id)
{
@@ -110,3 +152,44 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
/* Add any interrupt priorities configured by the bsp here */
return pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc = 0;
+
+ // Init pinmux and other hardware setup.
+ init_hardware();
+ BOARD_BootClockRUN();
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_2)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart2, "uart2",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_3)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart3, "uart3",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_4)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart4, "uart4",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(UART_5)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart5, "uart5",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/frdm-k64f/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/frdm-k64f/src/os_bsp.c b/hw/bsp/frdm-k64f/src/os_bsp.c
deleted file mode 100644
index 4b9582d..0000000
--- a/hw/bsp/frdm-k64f/src/os_bsp.c
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include <sys/types.h>
-#include <stdio.h>
-
-#include "os/os_dev.h"
-#include "syscfg/syscfg.h"
-
-#include "flash_map/flash_map.h"
-#include "hal/hal_flash.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-#include "hal/hal_uart.h"
-
-#include "bsp/cmsis_nvic.h"
-
-#include "mcu/frdm-k64f_hal.h"
-#include "fsl_device_registers.h"
-#include "fsl_common.h"
-#include "fsl_clock.h"
-#include "fsl_port.h"
-
-#include "clock_config.h"
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-#endif
-#if MYNEWT_VAL(UART_1)
-static struct uart_dev os_bsp_uart1;
-#endif
-#if MYNEWT_VAL(UART_2)
-static struct uart_dev os_bsp_uart2;
-#endif
-#if MYNEWT_VAL(UART_3)
-static struct uart_dev os_bsp_uart3;
-#endif
-#if MYNEWT_VAL(UART_4)
-static struct uart_dev os_bsp_uart4;
-#endif
-#if MYNEWT_VAL(UART_5)
-static struct uart_dev os_bsp_uart5;
-#endif
-
-static void init_hardware(void)
-{
- // Disable the MPU otherwise USB cannot access the bus
- MPU->CESR = 0;
-
- // Enable all the ports
- SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK | SIM_SCGC5_PORTD_MASK |
- SIM_SCGC5_PORTE_MASK);
-}
-
-extern void BOARD_BootClockRUN(void);
-
-void
-hal_bsp_init(void)
-{
- int rc = 0;
-
- // Init pinmux and other hardware setup.
- init_hardware();
- BOARD_BootClockRUN();
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(UART_1)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart1, "uart1",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(UART_2)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart2, "uart2",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(UART_3)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart3, "uart3",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(UART_4)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart4, "uart4",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(UART_5)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart5, "uart5",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, NULL);
- assert(rc == 0);
-#endif
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/native/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/native/src/hal_bsp.c b/hw/bsp/native/src/hal_bsp.c
index e7d8400..5f14e1e 100644
--- a/hw/bsp/native/src/hal_bsp.c
+++ b/hw/bsp/native/src/hal_bsp.c
@@ -21,10 +21,17 @@
#include <assert.h>
#include <string.h>
#include <inttypes.h>
+#include <bsp/bsp.h>
+#include "sysflash/sysflash.h"
+#include "os/os.h"
#include "hal/hal_flash_int.h"
+#include "flash_map/flash_map.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
#include "mcu/native_bsp.h"
#include "mcu/mcu_hal.h"
-#include <bsp/bsp.h>
+
+static struct uart_dev os_bsp_uart0;
const struct hal_flash *
hal_bsp_flash_dev(uint8_t id)
@@ -43,3 +50,13 @@ hal_bsp_power_state(int state)
{
return (0);
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *) NULL);
+ assert(rc == 0);
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/native/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/native/src/os_bsp.c b/hw/bsp/native/src/os_bsp.c
deleted file mode 100644
index 2ac78f1..0000000
--- a/hw/bsp/native/src/os_bsp.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include <assert.h>
-
-#include "sysflash/sysflash.h"
-#include "os/os.h"
-#include "flash_map/flash_map.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-#include "mcu/native_bsp.h"
-
-static struct uart_dev os_bsp_uart0;
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *) NULL);
- assert(rc == 0);
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c b/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
index 437d2a6..97336ec 100644
--- a/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
+++ b/hw/bsp/nrf51-arduino_101/src/hal_bsp.c
@@ -19,10 +19,73 @@
#include <stdint.h>
#include <stddef.h>
+#include <assert.h>
#include <nrf51.h>
#include <mcu/nrf51_hal.h>
#include <hal/hal_bsp.h>
#include "bsp/bsp.h"
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_flash.h"
+#include "bsp/cmsis_nvic.h"
+#include "nrf51_bitfields.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_1_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "hal/hal_spi.h"
+#include "os/os_dev.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .csn_pin = 24,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
/*
* What memory to include in coredump.
@@ -83,3 +146,99 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
}
return cfg_pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+ rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+}
+
+extern void timer_handler(void);
+static void
+rtc0_timer_handler(void)
+{
+ if (NRF_RTC0->EVENTS_TICK) {
+ NRF_RTC0->EVENTS_TICK = 0;
+ timer_handler();
+ }
+}
+
+void
+os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio)
+{
+ uint32_t ctx;
+ uint32_t mask;
+ uint32_t pre_scaler;
+
+ /* Turn on the LFCLK */
+ NRF_CLOCK->XTALFREQ = CLOCK_XTALFREQ_XTALFREQ_16MHz;
+ NRF_CLOCK->TASKS_LFCLKSTOP = 1;
+ NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+ NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_Xtal;
+ NRF_CLOCK->TASKS_LFCLKSTART = 1;
+
+ /* Wait here till started! */
+ mask = CLOCK_LFCLKSTAT_STATE_Msk | CLOCK_LFCLKSTAT_SRC_Xtal;
+ while (1) {
+ if (NRF_CLOCK->EVENTS_LFCLKSTARTED) {
+ if ((NRF_CLOCK->LFCLKSTAT & mask) == mask) {
+ break;
+ }
+ }
+ }
+
+ /* Is this exact frequency obtainable? */
+ pre_scaler = (32768 / os_ticks_per_sec) - 1;
+
+ /* disable interrupts */
+ __HAL_DISABLE_INTERRUPTS(ctx);
+
+ NRF_RTC0->TASKS_STOP = 1;
+ NRF_RTC0->EVENTS_TICK = 0;
+ NRF_RTC0->PRESCALER = pre_scaler;
+ NRF_RTC0->INTENCLR = 0xffffffff;
+ NRF_RTC0->TASKS_CLEAR = 1;
+
+ /* Set isr in vector table and enable interrupt */
+ NVIC_SetPriority(RTC0_IRQn, prio);
+ NVIC_SetVector(RTC0_IRQn, (uint32_t)rtc0_timer_handler);
+ NVIC_EnableIRQ(RTC0_IRQn);
+
+ NRF_RTC0->INTENSET = RTC_INTENSET_TICK_Msk;
+ NRF_RTC0->TASKS_START = 1;
+
+ __HAL_ENABLE_INTERRUPTS(ctx);
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51-arduino_101/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-arduino_101/src/os_bsp.c b/hw/bsp/nrf51-arduino_101/src/os_bsp.c
deleted file mode 100644
index 4be5682..0000000
--- a/hw/bsp/nrf51-arduino_101/src/os_bsp.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include <assert.h>
-#include <stdint.h>
-#include "os/os_cputime.h"
-#include "syscfg/syscfg.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_bsp.h"
-#include "bsp/cmsis_nvic.h"
-#include "nrf51.h"
-#include "nrf51_bitfields.h"
-#include "mcu/nrf51_hal.h"
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_1_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#include "hal/hal_spi.h"
-#include "os/os_dev.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-
-#define BSP_LOWEST_PRIO ((1 << __NVIC_PRIO_BITS) - 1)
-
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .csn_pin = 24,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
- rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-}
-
-extern void timer_handler(void);
-static void
-rtc0_timer_handler(void)
-{
- if (NRF_RTC0->EVENTS_TICK) {
- NRF_RTC0->EVENTS_TICK = 0;
- timer_handler();
- }
-}
-
-void
-os_bsp_systick_init(uint32_t os_ticks_per_sec, int prio)
-{
- uint32_t ctx;
- uint32_t mask;
- uint32_t pre_scaler;
-
- /* Turn on the LFCLK */
- NRF_CLOCK->XTALFREQ = CLOCK_XTALFREQ_XTALFREQ_16MHz;
- NRF_CLOCK->TASKS_LFCLKSTOP = 1;
- NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
- NRF_CLOCK->LFCLKSRC = CLOCK_LFCLKSRC_SRC_Xtal;
- NRF_CLOCK->TASKS_LFCLKSTART = 1;
-
- /* Wait here till started! */
- mask = CLOCK_LFCLKSTAT_STATE_Msk | CLOCK_LFCLKSTAT_SRC_Xtal;
- while (1) {
- if (NRF_CLOCK->EVENTS_LFCLKSTARTED) {
- if ((NRF_CLOCK->LFCLKSTAT & mask) == mask) {
- break;
- }
- }
- }
-
- /* Is this exact frequency obtainable? */
- pre_scaler = (32768 / os_ticks_per_sec) - 1;
-
- /* disable interrupts */
- __HAL_DISABLE_INTERRUPTS(ctx);
-
- NRF_RTC0->TASKS_STOP = 1;
- NRF_RTC0->EVENTS_TICK = 0;
- NRF_RTC0->PRESCALER = pre_scaler;
- NRF_RTC0->INTENCLR = 0xffffffff;
- NRF_RTC0->TASKS_CLEAR = 1;
-
- /* Set isr in vector table and enable interrupt */
- NVIC_SetPriority(RTC0_IRQn, prio);
- NVIC_SetVector(RTC0_IRQn, (uint32_t)rtc0_timer_handler);
- NVIC_EnableIRQ(RTC0_IRQn);
-
- NRF_RTC0->INTENSET = RTC_INTENSET_TICK_Msk;
- NRF_RTC0->TASKS_START = 1;
-
- __HAL_ENABLE_INTERRUPTS(ctx);
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51-blenano/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/src/hal_bsp.c b/hw/bsp/nrf51-blenano/src/hal_bsp.c
index 74762f4..8bc8f22 100644
--- a/hw/bsp/nrf51-blenano/src/hal_bsp.c
+++ b/hw/bsp/nrf51-blenano/src/hal_bsp.c
@@ -19,9 +19,72 @@
#include <stdint.h>
#include <stddef.h>
+#include <assert.h>
#include <nrf51.h>
#include "mcu/nrf51_hal.h"
#include "hal/hal_bsp.h"
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_1_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "os/os_dev.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .csn_pin = 24,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
const struct hal_flash *
hal_bsp_flash_dev(uint8_t id)
@@ -65,3 +128,44 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
}
return cfg_pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+ rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51-blenano/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51-blenano/src/os_bsp.c b/hw/bsp/nrf51-blenano/src/os_bsp.c
deleted file mode 100644
index 566a153..0000000
--- a/hw/bsp/nrf51-blenano/src/os_bsp.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include <assert.h>
-#include <stdint.h>
-#include "os/os_cputime.h"
-#include "syscfg/syscfg.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_bsp.h"
-#include "hal/hal_spi.h"
-#include "mcu/nrf51_hal.h"
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_1_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#include "nrf_drv_config.h"
-#include "app_util_platform.h"
-#include "os/os_dev.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .csn_pin = 24,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
- (void)rc;
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
- rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c b/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
index 2d2c9c6..fbe9e9d 100644
--- a/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
+++ b/hw/bsp/nrf51dk-16kbram/src/hal_bsp.c
@@ -20,12 +20,74 @@
#include <stdint.h>
#include <stddef.h>
#include <assert.h>
+#include "syscfg/syscfg.h"
#include "hal/hal_bsp.h"
#include "mcu/nrf51_hal.h"
#include "bsp/bsp.h"
#include "nrf_adc.h"
#include "nrf_drv_adc.h"
#include "os/os_dev.h"
+#include "os/os_cputime.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_i2c.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_1_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .csn_pin = 24,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
/*
* What memory to include in coredump.
@@ -86,3 +148,55 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
}
return cfg_pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+#if MYNEWT_VAL(I2C_0)
+ struct nrf51_hal_i2c_cfg hal_i2c_cfg;
+#endif
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+ rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+ hal_i2c_cfg.scl_pin = TWI0_CONFIG_SCL;
+ hal_i2c_cfg.sda_pin = TWI0_CONFIG_SDA;
+ hal_i2c_cfg.i2c_frequency = 100; /* 100 kHz */
+ rc = hal_i2c_init(0, &hal_i2c_cfg);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk-16kbram/src/os_bsp.c b/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
deleted file mode 100644
index 0a11713..0000000
--- a/hw/bsp/nrf51dk-16kbram/src/os_bsp.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include <assert.h>
-#include <stdint.h>
-#include "os/os_cputime.h"
-#include "syscfg/syscfg.h"
-#include "bsp.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_bsp.h"
-#include "hal/hal_spi.h"
-#include "hal/hal_i2c.h"
-#include "mcu/nrf51_hal.h"
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_1_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#include "nrf_drv_config.h"
-#include "app_util_platform.h"
-#include "os/os_dev.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .csn_pin = 24,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-#if MYNEWT_VAL(I2C_0)
- struct nrf51_hal_i2c_cfg hal_i2c_cfg;
-#endif
-
- (void)rc;
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
- rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(I2C_0)
- hal_i2c_cfg.scl_pin = TWI0_CONFIG_SCL;
- hal_i2c_cfg.sda_pin = TWI0_CONFIG_SDA;
- hal_i2c_cfg.i2c_frequency = 100; /* 100 kHz */
- rc = hal_i2c_init(0, &hal_i2c_cfg);
- assert(rc == 0);
-#endif
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51dk/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk/src/hal_bsp.c b/hw/bsp/nrf51dk/src/hal_bsp.c
index 7669ebf..7a9a3c5 100644
--- a/hw/bsp/nrf51dk/src/hal_bsp.c
+++ b/hw/bsp/nrf51dk/src/hal_bsp.c
@@ -20,12 +20,74 @@
#include <stdint.h>
#include <stddef.h>
#include <assert.h>
+#include "syscfg/syscfg.h"
#include "hal/hal_bsp.h"
#include "mcu/nrf51_hal.h"
#include "bsp/bsp.h"
#include "nrf_adc.h"
#include "nrf_drv_adc.h"
#include "os/os_dev.h"
+#include "os/os_cputime.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_i2c.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_1_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
+ .sck_pin = 29,
+ .mosi_pin = 25,
+ .miso_pin = 28,
+ .csn_pin = 24,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
/*
* What memory to include in coredump.
@@ -87,3 +149,56 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
return cfg_pri;
}
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(I2C_0)
+ struct nrf51_hal_i2c_cfg hal_i2c_cfg;
+#endif
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_1_SLAVE)
+ rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+ hal_i2c_cfg.scl_pin = TWI0_CONFIG_SCL;
+ hal_i2c_cfg.sda_pin = TWI0_CONFIG_SDA;
+ hal_i2c_cfg.i2c_frequency = 100; /* 100 kHz */
+ rc = hal_i2c_init(0, &hal_i2c_cfg);
+ assert(rc == 0);
+#endif
+
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf51dk/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf51dk/src/os_bsp.c b/hw/bsp/nrf51dk/src/os_bsp.c
deleted file mode 100644
index d2b9f22..0000000
--- a/hw/bsp/nrf51dk/src/os_bsp.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-#include <assert.h>
-#include <stdint.h>
-#include "syscfg/syscfg.h"
-#include "os/os_cputime.h"
-#include "bsp.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_bsp.h"
-#include "hal/hal_spi.h"
-#include "hal/hal_i2c.h"
-#include "mcu/nrf51_hal.h"
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_1_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#include "nrf_drv_config.h"
-#include "app_util_platform.h"
-#include "os/os_dev.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf51_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi1s_cfg = {
- .sck_pin = 29,
- .mosi_pin = 25,
- .miso_pin = 28,
- .csn_pin = 24,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
-#if MYNEWT_VAL(I2C_0)
- struct nrf51_hal_i2c_cfg hal_i2c_cfg;
-#endif
-
- (void)rc;
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_1_SLAVE)
- rc = hal_spi_init(1, (void *)&os_bsp_spi1s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(I2C_0)
- hal_i2c_cfg.scl_pin = TWI0_CONFIG_SCL;
- hal_i2c_cfg.sda_pin = TWI0_CONFIG_SDA;
- hal_i2c_cfg.i2c_frequency = 100; /* 100 kHz */
- rc = hal_i2c_init(0, &hal_i2c_cfg);
- assert(rc == 0);
-#endif
-
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf52dk/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52dk/src/hal_bsp.c b/hw/bsp/nrf52dk/src/hal_bsp.c
index b54e44f..dc9f697 100644
--- a/hw/bsp/nrf52dk/src/hal_bsp.c
+++ b/hw/bsp/nrf52dk/src/hal_bsp.c
@@ -16,13 +16,101 @@
* specific language governing permissions and limitations
* under the License.
*/
+
#include <stdint.h>
#include <stddef.h>
-
-#include "bsp/bsp.h"
-#include <hal/hal_bsp.h>
+#include <assert.h>
#include <nrf52.h>
+#include "os/os_cputime.h"
+#include "syscfg/syscfg.h"
+#include "sysflash/sysflash.h"
+#include "flash_map/flash_map.h"
+#include "hal/hal_bsp.h"
+#include "hal/hal_flash.h"
+#include "hal/hal_spi.h"
+#include "hal/hal_watchdog.h"
+#include "hal/hal_i2c.h"
#include "mcu/nrf52_hal.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+#include "os/os_dev.h"
+#include "bsp.h"
+#if MYNEWT_VAL(SPI_0_MASTER)
+#include "nrf_drv_spi.h"
+#endif
+#if MYNEWT_VAL(SPI_0_SLAVE)
+#include "nrf_drv_spis.h"
+#endif
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "nrf.h"
+#include "app_error.h"
+#include "nrf_drv_saadc.h"
+#if MYNEWT_VAL(ADC_0)
+#include "adc_nrf52/adc_nrf52.h"
+#endif
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev os_bsp_uart0;
+static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
+ .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+#endif
+
+#if MYNEWT_VAL(UART_1)
+static struct uart_dev os_bsp_bitbang_uart1;
+static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
+ .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
+ .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
+ .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
+};
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+static struct adc_dev os_bsp_adc0;
+static struct nrf52_adc_dev_cfg os_bsp_adc0_config = {
+ .nadc_refmv = 2800
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+/*
+ * NOTE: do not set the ss pin here! This would cause the nordic SDK
+ * to start using the SS pin when configured as a master and this is
+ * not what our HAL expects. Our HAL expects that the SS pin, if used,
+ * is treated as a gpio line and is handled outside the SPI routines.
+ */
+static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
+ .sck_pin = 23,
+ .mosi_pin = 24,
+ .miso_pin = 25,
+ .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
+ .orc = 0xFF,
+ .frequency = NRF_DRV_SPI_FREQ_4M,
+ .mode = NRF_DRV_SPI_MODE_0,
+ .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+static const nrf_drv_spis_config_t os_bsp_spi0s_cfg = {
+ .sck_pin = 23,
+ .mosi_pin = 24,
+ .miso_pin = 25,
+ .csn_pin = 22,
+ .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
+ .csn_pullup = NRF_GPIO_PIN_PULLUP,
+ .orc = NRF_DRV_SPIS_DEFAULT_ORC,
+ .def = NRF_DRV_SPIS_DEFAULT_DEF,
+ .mode = NRF_DRV_SPIS_MODE_0,
+ .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
+ .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
+};
+#endif
/*
* What memory to include in coredump.
@@ -83,3 +171,75 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
}
return cfg_pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(I2C_0)
+ struct nrf52_hal_i2c_cfg hal_i2c_cfg;
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ rc = hal_timer_init(0, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_1)
+ rc = hal_timer_init(1, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_2)
+ rc = hal_timer_init(2, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_3)
+ rc = hal_timer_init(3, NULL);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(TIMER_4)
+ rc = hal_timer_init(4, NULL);
+ assert(rc == 0);
+#endif
+
+ /* Set cputime to count at 1 usec increments */
+ rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(I2C_0)
+ hal_i2c_cfg.scl_pin = TWI0_CONFIG_SCL;
+ hal_i2c_cfg.sda_pin = TWI0_CONFIG_SDA;
+ hal_i2c_cfg.i2c_frequency = 100; /* 100 kHz */
+ rc = hal_i2c_init(0, &hal_i2c_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(UART_1)
+ rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
+ OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(ADC_0)
+ rc = os_dev_create((struct os_dev *) &os_bsp_adc0, "adc0",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ nrf52_adc_dev_init, &os_bsp_adc0_config);
+ assert(rc == 0);
+#endif
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/nrf52dk/src/os_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/nrf52dk/src/os_bsp.c b/hw/bsp/nrf52dk/src/os_bsp.c
deleted file mode 100644
index 6b62233..0000000
--- a/hw/bsp/nrf52dk/src/os_bsp.c
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <stdint.h>
-#include "os/os_cputime.h"
-#include "syscfg/syscfg.h"
-#include "sysflash/sysflash.h"
-#include "flash_map/flash_map.h"
-#include "hal/hal_bsp.h"
-#include "hal/hal_flash.h"
-#include "hal/hal_spi.h"
-#include "hal/hal_watchdog.h"
-#include "hal/hal_i2c.h"
-#include "mcu/nrf52_hal.h"
-#include "uart/uart.h"
-#include "uart_hal/uart_hal.h"
-#include "os/os_dev.h"
-#include "bsp.h"
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-#include "nrf_drv_spi.h"
-#endif
-#if MYNEWT_VAL(SPI_0_SLAVE)
-#include "nrf_drv_spis.h"
-#endif
-#include "nrf_drv_config.h"
-#include "app_util_platform.h"
-#include "nrf.h"
-#include "app_error.h"
-#include "nrf_drv_saadc.h"
-
-#if MYNEWT_VAL(ADC_0)
-#include "adc_nrf52/adc_nrf52.h"
-#endif
-
-#if MYNEWT_VAL(UART_0)
-static struct uart_dev os_bsp_uart0;
-static const struct nrf52_uart_cfg os_bsp_uart0_cfg = {
- .suc_pin_tx = MYNEWT_VAL(UART_0_PIN_TX),
- .suc_pin_rx = MYNEWT_VAL(UART_0_PIN_RX),
- .suc_pin_rts = MYNEWT_VAL(UART_0_PIN_RTS),
- .suc_pin_cts = MYNEWT_VAL(UART_0_PIN_CTS),
-};
-#endif
-
-#if MYNEWT_VAL(UART_1)
-static struct uart_dev os_bsp_bitbang_uart1;
-static const struct uart_bitbang_conf os_bsp_uart1_cfg = {
- .ubc_rxpin = MYNEWT_VAL(UART_1_PIN_TX),
- .ubc_txpin = MYNEWT_VAL(UART_1_PIN_RX),
- .ubc_cputimer_freq = MYNEWT_VAL(CLOCK_FREQ),
-};
-#endif
-
-#if MYNEWT_VAL(ADC_0)
-static struct adc_dev os_bsp_adc0;
-static struct nrf52_adc_dev_cfg os_bsp_adc0_config = {
- .nadc_refmv = 2800
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
-/*
- * NOTE: do not set the ss pin here! This would cause the nordic SDK
- * to start using the SS pin when configured as a master and this is
- * not what our HAL expects. Our HAL expects that the SS pin, if used,
- * is treated as a gpio line and is handled outside the SPI routines.
- */
-static const nrf_drv_spi_config_t os_bsp_spi0m_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .ss_pin = NRF_DRV_SPI_PIN_NOT_USED,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1,
- .orc = 0xFF,
- .frequency = NRF_DRV_SPI_FREQ_4M,
- .mode = NRF_DRV_SPI_MODE_0,
- .bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST
-};
-#endif
-
-#if MYNEWT_VAL(SPI_0_SLAVE)
-static const nrf_drv_spis_config_t os_bsp_spi0s_cfg = {
- .sck_pin = 23,
- .mosi_pin = 24,
- .miso_pin = 25,
- .csn_pin = 22,
- .miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,
- .csn_pullup = NRF_GPIO_PIN_PULLUP,
- .orc = NRF_DRV_SPIS_DEFAULT_ORC,
- .def = NRF_DRV_SPIS_DEFAULT_DEF,
- .mode = NRF_DRV_SPIS_MODE_0,
- .bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,
- .irq_priority = (1 << __NVIC_PRIO_BITS) - 1
-};
-#endif
-
-void
-hal_bsp_init(void)
-{
- int rc;
-
-#if MYNEWT_VAL(I2C_0)
- struct nrf52_hal_i2c_cfg hal_i2c_cfg;
-#endif
-
-#if MYNEWT_VAL(TIMER_0)
- rc = hal_timer_init(0, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_1)
- rc = hal_timer_init(1, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_2)
- rc = hal_timer_init(2, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_3)
- rc = hal_timer_init(3, NULL);
- assert(rc == 0);
-#endif
-#if MYNEWT_VAL(TIMER_4)
- rc = hal_timer_init(4, NULL);
- assert(rc == 0);
-#endif
-
- /* Set cputime to count at 1 usec increments */
- rc = os_cputime_init(MYNEWT_VAL(CLOCK_FREQ));
- assert(rc == 0);
-
-#if MYNEWT_VAL(I2C_0)
- hal_i2c_cfg.scl_pin = TWI0_CONFIG_SCL;
- hal_i2c_cfg.sda_pin = TWI0_CONFIG_SDA;
- hal_i2c_cfg.i2c_frequency = 100; /* 100 kHz */
- rc = hal_i2c_init(0, &hal_i2c_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_0_MASTER)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0m_cfg, HAL_SPI_TYPE_MASTER);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(SPI_0_SLAVE)
- rc = hal_spi_init(0, (void *)&os_bsp_spi0s_cfg, HAL_SPI_TYPE_SLAVE);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_uart0, "uart0",
- OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&os_bsp_uart0_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(UART_1)
- rc = os_dev_create((struct os_dev *) &os_bsp_bitbang_uart1, "uart1",
- OS_DEV_INIT_PRIMARY, 0, uart_bitbang_init, (void *)&os_bsp_uart1_cfg);
- assert(rc == 0);
-#endif
-
-#if MYNEWT_VAL(ADC_0)
- rc = os_dev_create((struct os_dev *) &os_bsp_adc0, "adc0",
- OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
- nrf52_adc_dev_init, &os_bsp_adc0_config);
- assert(rc == 0);
-#endif
-}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/60c1d227/hw/bsp/olimex_stm32-e407_devboard/src/hal_bsp.c
----------------------------------------------------------------------
diff --git a/hw/bsp/olimex_stm32-e407_devboard/src/hal_bsp.c b/hw/bsp/olimex_stm32-e407_devboard/src/hal_bsp.c
index 5ff50a0..9d50e8c 100644
--- a/hw/bsp/olimex_stm32-e407_devboard/src/hal_bsp.c
+++ b/hw/bsp/olimex_stm32-e407_devboard/src/hal_bsp.c
@@ -16,14 +16,259 @@
* specific language governing permissions and limitations
* under the License.
*/
+
+#include <assert.h>
+#include "syscfg/syscfg.h"
+#include "bsp/bsp.h"
+#include "stm32f407xx.h"
+#include "stm32f4xx_hal_gpio_ex.h"
+#include "stm32f4xx_hal_dma.h"
+#include "stm32f4xx_hal_adc.h"
+#include "flash_map/flash_map.h"
+#include "os/os_dev.h"
+#include "uart/uart.h"
+#include "uart_hal/uart_hal.h"
+#include "adc_stm32f4/adc_stm32f4.h"
+#include "hal/hal_i2c.h"
+#include "hal/hal_timer.h"
#include "hal/hal_bsp.h"
#include "hal/hal_gpio.h"
#include "hal/hal_flash_int.h"
-#include "stm32f407xx.h"
-#include "stm32f4xx_hal_gpio_ex.h"
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+#include "hal/hal_spi.h"
+#endif
#include "mcu/stm32f4_bsp.h"
-#include "bsp/bsp.h"
-#include <assert.h>
+#include "mcu/stm32f4xx_mynewt_hal.h"
+
+static struct uart_dev hal_uart0;
+
+/* XXX should not be here */
+
+#if MYNEWT_VAL(ADC_1)
+struct adc_dev my_dev_adc1;
+#endif
+#if MYNEWT_VAL(ADC_2)
+struct adc_dev my_dev_adc2;
+#endif
+#if MYNEWT_VAL(ADC_3)
+struct adc_dev my_dev_adc3;
+#endif
+
+struct stm32f4_uart_cfg;
+
+#if MYNEWT_VAL(ADC_1)
+/*
+ * adc_handle is defined earlier because the DMA handle's
+ * parent needs to be pointing to the adc_handle
+ */
+extern ADC_HandleTypeDef adc1_handle;
+
+#define STM32F4_DEFAULT_DMA00_HANDLE {\
+ .Instance = DMA2_Stream0,\
+ .Init.Channel = DMA_CHANNEL_0,\
+ .Init.Direction = DMA_PERIPH_TO_MEMORY,\
+ .Init.PeriphInc = DMA_PINC_DISABLE,\
+ .Init.MemInc = DMA_MINC_ENABLE,\
+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD,\
+ .Init.MemDataAlignment = DMA_MDATAALIGN_WORD,\
+ .Init.Mode = DMA_CIRCULAR,\
+ .Init.Priority = DMA_PRIORITY_HIGH,\
+ .Init.FIFOMode = DMA_FIFOMODE_DISABLE,\
+ .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\
+ .Init.MemBurst = DMA_MBURST_SINGLE,\
+ .Init.PeriphBurst = DMA_PBURST_SINGLE,\
+ .Parent = &adc1_handle,\
+}
+
+DMA_HandleTypeDef adc1_dma00_handle = STM32F4_DEFAULT_DMA00_HANDLE;
+#endif
+
+#if MYNEWT_VAL(ADC_2)
+
+extern ADC_HandleTypeDef adc2_handle;
+
+#define STM32F4_DEFAULT_DMA21_HANDLE {\
+ .Instance = DMA2_Stream2,\
+ .Init.Channel = DMA_CHANNEL_1,\
+ .Init.Direction = DMA_PERIPH_TO_MEMORY,\
+ .Init.PeriphInc = DMA_PINC_DISABLE,\
+ .Init.MemInc = DMA_MINC_ENABLE,\
+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD,\
+ .Init.MemDataAlignment = DMA_MDATAALIGN_WORD,\
+ .Init.Mode = DMA_CIRCULAR,\
+ .Init.Priority = DMA_PRIORITY_HIGH,\
+ .Init.FIFOMode = DMA_FIFOMODE_DISABLE,\
+ .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\
+ .Init.MemBurst = DMA_MBURST_SINGLE,\
+ .Init.PeriphBurst = DMA_PBURST_SINGLE,\
+ .Parent = &adc2_handle,\
+}
+
+DMA_HandleTypeDef adc2_dma21_handle = STM32F4_DEFAULT_DMA21_HANDLE;
+#endif
+
+
+#if MYNEWT_VAL(ADC_3)
+
+extern ADC_HandleTypeDef adc3_handle;
+
+#define STM32F4_DEFAULT_DMA12_HANDLE {\
+ .Instance = DMA2_Stream1,\
+ .Init.Channel = DMA_CHANNEL_2,\
+ .Init.Direction = DMA_PERIPH_TO_MEMORY,\
+ .Init.PeriphInc = DMA_PINC_DISABLE,\
+ .Init.MemInc = DMA_MINC_ENABLE,\
+ .Init.PeriphDataAlignment = DMA_PDATAALIGN_WORD,\
+ .Init.MemDataAlignment = DMA_MDATAALIGN_WORD,\
+ .Init.Mode = DMA_CIRCULAR,\
+ .Init.Priority = DMA_PRIORITY_HIGH,\
+ .Init.FIFOMode = DMA_FIFOMODE_DISABLE,\
+ .Init.FIFOThreshold = DMA_FIFO_THRESHOLD_HALFFULL,\
+ .Init.MemBurst = DMA_MBURST_SINGLE,\
+ .Init.PeriphBurst = DMA_PBURST_SINGLE,\
+ .Parent = &adc3_handle,\
+}
+
+DMA_HandleTypeDef adc3_dma12_handle = STM32F4_DEFAULT_DMA12_HANDLE;
+#endif
+
+#define STM32F4_ADC_DEFAULT_INIT_TD {\
+ .ClockPrescaler = ADC_CLOCKPRESCALER_PCLK_DIV2,\
+ .Resolution = ADC_RESOLUTION12b,\
+ .DataAlign = ADC_DATAALIGN_RIGHT,\
+ .ScanConvMode = DISABLE,\
+ .EOCSelection = DISABLE,\
+ .ContinuousConvMode = ENABLE,\
+ .NbrOfConversion = 1,\
+ .DiscontinuousConvMode = DISABLE,\
+ .NbrOfDiscConversion = 0,\
+ .ExternalTrigConv = ADC_SOFTWARE_START,\
+ .ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE,\
+ .DMAContinuousRequests = ENABLE\
+}
+
+#if MYNEWT_VAL(ADC_1)
+
+/*****************ADC1 Config ***************/
+#define STM32F4_DEFAULT_ADC1_HANDLE {\
+ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\
+ .Instance = ADC1,\
+ .NbrOfCurrentConversionRank = 0,\
+ .DMA_Handle = &adc1_dma00_handle,\
+ .Lock = HAL_UNLOCKED,\
+ .State = 0,\
+ .ErrorCode = 0\
+}
+
+ADC_HandleTypeDef adc1_handle = STM32F4_DEFAULT_ADC1_HANDLE;
+
+#define STM32F4_ADC1_DEFAULT_SAC {\
+ .c_refmv = 3300,\
+ .c_res = 12,\
+ .c_configured = 1,\
+ .c_cnum = ADC_CHANNEL_10\
+}
+
+struct adc_chan_config adc1_chan10_config = STM32F4_ADC1_DEFAULT_SAC;
+
+#define STM32F4_ADC1_DEFAULT_CONFIG {\
+ .sac_chan_count = 16,\
+ .sac_chans = (struct adc_chan_config [16]){{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},STM32F4_ADC1_DEFAULT_SAC},\
+ .sac_adc_handle = &adc1_handle,\
+}
+
+struct stm32f4_adc_dev_cfg adc1_config = STM32F4_ADC1_DEFAULT_CONFIG;
+/*********************************************/
+#endif
+
+#if MYNEWT_VAL(ADC_2)
+
+/*****************ADC2 Config ***************/
+#define STM32F4_DEFAULT_ADC2_HANDLE {\
+ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\
+ .Instance = ADC2,\
+ .NbrOfCurrentConversionRank = 0,\
+ .DMA_Handle = &adc2_dma21_handle,\
+ .Lock = HAL_UNLOCKED,\
+ .State = 0,\
+ .ErrorCode = 0\
+}
+
+ADC_HandleTypeDef adc2_handle = STM32F4_DEFAULT_ADC2_HANDLE;
+
+#define STM32F4_ADC2_DEFAULT_SAC {\
+ .c_refmv = 3300,\
+ .c_res = 12,\
+ .c_configured = 1,\
+ .c_cnum = ADC_CHANNEL_1\
+}
+
+struct adc_chan_config adc2_chan1_config = STM32F4_ADC2_DEFAULT_SAC;
+
+#define STM32F4_ADC2_DEFAULT_CONFIG {\
+ .sac_chan_count = 16,\
+ .sac_chans = (struct adc_chan_config [16]){{0},STM32F4_ADC1_DEFAULT_SAC}\
+ .sac_adc_handle = &adc2_handle,\
+}
+
+struct stm32f4_adc_dev_cfg adc2_config = STM32F4_ADC2_DEFAULT_CONFIG;
+/*********************************************/
+#endif
+
+#if MYNEWT_VAL(ADC_3)
+
+#define STM32F4_DEFAULT_ADC3_HANDLE {\
+ .Init = STM32F4_ADC_DEFAULT_INIT_TD,\
+ .Instance = ADC3,\
+ .NbrOfCurrentConversionRank = 0,\
+ .DMA_Handle = &adc3_dma12_handle,\
+ .Lock = HAL_UNLOCKED,\
+ .State = 0,\
+ .ErrorCode = 0\
+}
+
+ADC_HandleTypeDef adc3_handle = STM32F4_DEFAULT_ADC3_HANDLE;
+
+#define STM32F4_ADC3_DEFAULT_SAC {\
+ .c_refmv = 3300,\
+ .c_res = 12,\
+ .c_configured = 1,\
+ .c_cnum = ADC_CHANNEL_4\
+}
+
+struct adc_chan_config adc3_chan4_config = STM32F4_ADC3_DEFAULT_SAC;
+
+#define STM32F4_ADC3_DEFAULT_CONFIG {\
+ .sac_chan_count = 16,\
+ .sac_chans = (struct adc_chan_config [16]){{0},{0},{0},{0},STM32F4_ADC3_DEFAULT_SAC},\
+ .sac_adc_handle = &adc3_handle,\
+}
+
+struct stm32f4_adc_dev_cfg adc3_config = STM32F4_ADC3_DEFAULT_CONFIG;
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+static struct stm32f4_hal_i2c_cfg i2c_cfg0 = {
+ .hic_i2c = I2C1,
+ .hic_rcc_reg = &RCC->APB1ENR,
+ .hic_rcc_dev = RCC_APB1ENR_I2C1EN,
+ .hic_pin_sda = MCU_GPIO_PORTB(9), /* PB9 */
+ .hic_pin_scl = MCU_GPIO_PORTB(8), /* PB8 */
+ .hic_pin_af = GPIO_AF4_I2C1,
+ .hic_10bit = 0,
+ .hic_speed = 100000 /* 100kHz */
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_0_MASTER)
+struct stm32f4_hal_spi_cfg spi0_cfg = {
+ .ss_pin = MCU_GPIO_PORTA(4), /* PA4 */
+ .sck_pin = MCU_GPIO_PORTA(5), /* PA5 */
+ .miso_pin = MCU_GPIO_PORTA(6), /* PA6 */
+ .mosi_pin = MCU_GPIO_PORTB(5), /* PB5 */
+ .irq_prio = 2
+};
+#endif
static const struct stm32f4_uart_cfg uart_cfg[UART_CNT] = {
[0] = {
@@ -97,3 +342,51 @@ hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
/* Add any interrupt priorities configured by the bsp here */
return pri;
}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, &spi0_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, &spi0_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+ rc = os_dev_create((struct os_dev *) &hal_uart0, CONSOLE_UART,
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)bsp_uart_config(0));
+ assert(rc == 0);
+
+#if MYNEWT_VAL(ADC_1)
+ rc = os_dev_create((struct os_dev *) &my_dev_adc1, "adc1",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ stm32f4_adc_dev_init, &adc1_config);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(ADC_2)
+ rc = os_dev_create((struct os_dev *) &my_dev_adc2, "adc2",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ stm32f4_adc_dev_init, &adc2_config);
+ assert(rc == 0);
+#endif
+#if MYNEWT_VAL(ADC_3)
+ rc = os_dev_create((struct os_dev *) &my_dev_adc3, "adc3",
+ OS_DEV_INIT_KERNEL, OS_DEV_INIT_PRIO_DEFAULT,
+ stm32f4_adc_dev_init, &adc3_config);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+ rc = hal_i2c_init(0, &i2c_cfg0);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_init(0, TIM9);
+#endif
+}