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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/10/14 09:58:20 UTC
(nuttx) 01/02: arch/armv8-a: new config to set SPIs Configuration to edge-triggered
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 83c483c1b456a9a2fe62f45b972baea7f6743a3b
Author: chao an <an...@lixiang.com>
AuthorDate: Mon Oct 14 12:27:22 2024 +0800
arch/armv8-a: new config to set SPIs Configuration to edge-triggered
Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default
Signed-off-by: chao an <an...@lixiang.com>
---
arch/arm64/Kconfig | 10 ++++++++++
arch/arm64/src/common/arm64_gicv3.c | 8 ++++++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 3cea820589..8aa8681902 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -353,6 +353,16 @@ config ARM64_GICV2_LEGACY_IRQ0
endif
+if ARM64_GIC_VERSION = 3
+
+config ARM64_GICV3_SPI_EDGE
+ bool "Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default"
+ default n
+ ---help---
+ Configure all SPIs(Shared Peripheral Interrupts) as edge-triggered by default.
+
+endif
+
config ARM64_SEMIHOSTING_HOSTFS
bool "Semihosting HostFS"
depends on FS_HOSTFS
diff --git a/arch/arm64/src/common/arm64_gicv3.c b/arch/arm64/src/common/arm64_gicv3.c
index 9a8b77b4c6..9b0d2985fb 100644
--- a/arch/arm64/src/common/arm64_gicv3.c
+++ b/arch/arm64/src/common/arm64_gicv3.c
@@ -607,7 +607,15 @@ static void gicv3_dist_init(void)
intid += GIC_NUM_CFG_PER_REG)
{
idx = intid / GIC_NUM_CFG_PER_REG;
+#ifdef CONFIG_ARM64_GICV3_SPI_EDGE
+ /* Configure all SPIs as edge-triggered by default */
+
+ putreg32(0xaaaaaaaa, ICFGR(base, idx));
+#else
+ /* Configure all SPIs as level-sensitive by default */
+
putreg32(0, ICFGR(base, idx));
+#endif
}
/* TODO: Some arrch64 Cortex-A core maybe without security state