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Posted to commits@nuttx.apache.org by gu...@apache.org on 2022/04/27 11:57:59 UTC
[incubator-nuttx] branch master updated (54b770d46a -> 98d8d2a1ff)
This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from 54b770d46a driver/ioexpander: remove response about irq_handler
new 541eabb535 xtensa_int_handlers.S: Refactor the calls to ps_setup.
new 98d8d2a1ff arch/xtensa: Group all the macros in one file.
The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/xtensa/src/common/xtensa_int_handlers.S | 122 ++++-----------------
.../common/{xtensa_loadstore.S => xtensa_macros.S} | 80 ++++++++------
arch/xtensa/src/common/xtensa_panic.S | 31 +-----
arch/xtensa/src/common/xtensa_user_handler.S | 67 +----------
4 files changed, 75 insertions(+), 225 deletions(-)
copy arch/xtensa/src/common/{xtensa_loadstore.S => xtensa_macros.S} (55%)
[incubator-nuttx] 02/02: arch/xtensa: Group all the macros in one file.
Posted by gu...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 98d8d2a1ff4e60514e7c18a7b1607430c1310d06
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Mon Apr 25 15:31:24 2022 +0200
arch/xtensa: Group all the macros in one file.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/common/xtensa_int_handlers.S | 67 ++------------------
arch/xtensa/src/common/xtensa_macros.S | 94 ++++++++++++++++++++++++++++
arch/xtensa/src/common/xtensa_panic.S | 31 +--------
arch/xtensa/src/common/xtensa_user_handler.S | 67 +-------------------
4 files changed, 105 insertions(+), 154 deletions(-)
diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S
index 5f405aa8c0..bc5d141b49 100644
--- a/arch/xtensa/src/common/xtensa_int_handlers.S
+++ b/arch/xtensa/src/common/xtensa_int_handlers.S
@@ -64,10 +64,16 @@
#include <arch/xtensa/xtensa_abi.h>
#include <arch/xtensa/xtensa_specregs.h>
+#include "xtensa_macros.S"
+
#include "chip.h"
#include "xtensa.h"
#include "xtensa_timer.h"
+/****************************************************************************
+ * Public Symbols
+ ****************************************************************************/
+
#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
.data
.align 16
@@ -104,67 +110,6 @@ g_intstacktop:
addi \aout, \aout, 1 /* Return aout + 1 */
.endm
-/****************************************************************************
- * Name: setintstack
- *
- * Description:
- * Set the current stack pointer to the "top" the interrupt stack.
- * Single CPU case.
- * Must be provided by MCU-specific logic in the SMP case.
- *
- ****************************************************************************/
-
-#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
- .macro setintstack tmp1 tmp2
- movi a1, g_intstacktop
- .endm
-#endif
-
-/****************************************************************************
- * Macro: ps_setup
- *
- * Description:
- * Set up PS for C, enable interrupts above this level and clear EXCM.
- *
- * Entry Conditions:
- * level - interrupt level
- * tmp - scratch register
- *
- * Side Effects:
- * PS and scratch register modified
- *
- * Assumptions:
- * - PS.EXCM = 1, C calling disabled
- *
- ****************************************************************************/
-
- .macro ps_setup level tmp
-
-#if 0 /* Nested interrupts no yet supported */
-# ifdef __XTENSA_CALL0_ABI__
- /* Disable interrupts at level and below */
-
- movi \tmp, PS_INTLEVEL(\level) | PS_UM
-# else
- movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
-# endif
-#else
-# ifdef __XTENSA_CALL0_ABI__
- /* Disable all low- and medium-priority interrupts. Nested are not yet
- * supported.
- */
-
- movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-# else
- movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-# endif
-#endif
-
- wsr \tmp, PS
- rsync
-
- .endm
-
/****************************************************************************
* Macro dispatch_c_isr level mask tmp
*
diff --git a/arch/xtensa/src/common/xtensa_macros.S b/arch/xtensa/src/common/xtensa_macros.S
new file mode 100644
index 0000000000..cb57846d1c
--- /dev/null
+++ b/arch/xtensa/src/common/xtensa_macros.S
@@ -0,0 +1,94 @@
+/****************************************************************************
+ * arch/xtensa/src/common/xtensa_macros.S
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+.file "xtensa_macros.S"
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+#include <arch/chip/core-isa.h>
+#include <arch/xtensa/xtensa_abi.h>
+#include <arch/xtensa/xtensa_specregs.h>
+
+/****************************************************************************
+ * Name: setintstack
+ *
+ * Description:
+ * Set the current stack pointer to the "top" the interrupt stack.
+ * Single CPU case.
+ * Must be provided by MCU-specific logic in the SMP case.
+ *
+ ****************************************************************************/
+
+#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
+ .macro setintstack tmp1 tmp2
+ movi a1, g_intstacktop
+ .endm
+#endif
+
+/****************************************************************************
+ * Macro: ps_setup
+ *
+ * Description:
+ * Set up PS for C, enable interrupts above this level and clear EXCM.
+ *
+ * Entry Conditions:
+ * level - interrupt level
+ * tmp - scratch register
+ *
+ * Side Effects:
+ * PS and scratch register modified
+ *
+ * Assumptions:
+ * - PS.EXCM = 1, C calling disabled
+ *
+ ****************************************************************************/
+
+ .macro ps_setup level tmp
+
+#if 0 /* Nested interrupts no yet supported */
+# ifdef __XTENSA_CALL0_ABI__
+ /* Disable interrupts at level and below */
+
+ movi \tmp, PS_INTLEVEL(\level) | PS_UM
+# else
+ movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
+# endif
+#else
+# ifdef __XTENSA_CALL0_ABI__
+ /* Disable all low- and medium-priority interrupts. Nested are not yet
+ * supported.
+ */
+
+ movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+# else
+ movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+# endif
+#endif
+
+ wsr \tmp, PS
+ rsync
+
+ .endm
+
diff --git a/arch/xtensa/src/common/xtensa_panic.S b/arch/xtensa/src/common/xtensa_panic.S
index f5ebd53801..dbd2ce7099 100644
--- a/arch/xtensa/src/common/xtensa_panic.S
+++ b/arch/xtensa/src/common/xtensa_panic.S
@@ -64,27 +64,9 @@
#include <arch/xtensa/core.h>
#include <arch/xtensa/xtensa_specregs.h>
-#include "chip.h"
-
-/****************************************************************************
- * Assembly Language Macros
- ****************************************************************************/
-
-/****************************************************************************
- * Name: setintstack
- *
- * Description:
- * Set the current stack pointer to the "top" the interrupt stack.
- * Single CPU case.
- * Must be provided by MCU-specific logic in the SMP case.
- *
- ****************************************************************************/
+#include "xtensa_macros.S"
-#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
- .macro setintstack tmp1 tmp2
- movi a1, g_intstacktop
- .endm
-#endif
+#include "chip.h"
/****************************************************************************
* Public Functions
@@ -147,14 +129,7 @@ _xtensa_panic:
/* Set up PS for C, re-enable hi-pri interrupts, and clear EXCM. */
-#ifdef __XTENSA_CALL0_ABI__
- movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-#else
- movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-#endif
-
- wsr a0, PS
- rsync
+ ps_setup XCHAL_EXCM_LEVEL a0
/* Call C panic handler: Arg1 (A2) = Exception code; Arg 2 (A3) = start
* of the register save area.
diff --git a/arch/xtensa/src/common/xtensa_user_handler.S b/arch/xtensa/src/common/xtensa_user_handler.S
index 61ef9c1742..10b787d6e4 100644
--- a/arch/xtensa/src/common/xtensa_user_handler.S
+++ b/arch/xtensa/src/common/xtensa_user_handler.S
@@ -64,72 +64,9 @@
#include <arch/xtensa/core.h>
#include <arch/xtensa/xtensa_specregs.h>
-#include "chip.h"
-
-/****************************************************************************
- * Assembly Language Macros
- ****************************************************************************/
-
-/****************************************************************************
- * Name: setintstack
- *
- * Description:
- * Set the current stack pointer to the "top" the interrupt stack.
- * Single CPU case.
- * Must be provided by MCU-specific logic in the SMP case.
- *
- ****************************************************************************/
-
-#if !defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15
- .macro setintstack tmp1 tmp2
- movi a1, g_intstacktop
- .endm
-#endif
+#include "xtensa_macros.S"
-/****************************************************************************
- * Macro: ps_setup
- *
- * Description:
- * Set up PS for C, enable interrupts above this level and clear EXCM.
- *
- * Entry Conditions:
- * level - interrupt level
- * tmp - scratch register
- *
- * Side Effects:
- * PS and scratch register modified
- *
- * Assumptions:
- * - PS.EXCM = 1, C calling disabled
- *
- ****************************************************************************/
-
- .macro ps_setup level tmp
-
-#if 0 /* Nested interrupts no yet supported */
-# ifdef __XTENSA_CALL0_ABI__
- /* Disable interrupts at level and below */
-
- movi \tmp, PS_INTLEVEL(\level) | PS_UM
-# else
- movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
-# endif
-#else
-# ifdef __XTENSA_CALL0_ABI__
- /* Disable all low- and medium-priority interrupts. Nested are not yet
- * supported.
- */
-
- movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-# else
- movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-# endif
-#endif
-
- wsr \tmp, PS
- rsync
-
- .endm
+#include "chip.h"
/****************************************************************************
* Waypoints
[incubator-nuttx] 01/02: xtensa_int_handlers.S: Refactor the calls to ps_setup.
Posted by gu...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
gustavonihei pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 541eabb535144214faf9dd64777c407ae502bc10
Author: Abdelatif Guettouche <ab...@espressif.com>
AuthorDate: Mon Apr 25 13:43:34 2022 +0200
xtensa_int_handlers.S: Refactor the calls to ps_setup.
Signed-off-by: Abdelatif Guettouche <ab...@espressif.com>
---
arch/xtensa/src/common/xtensa_int_handlers.S | 143 +++++++++++----------------
1 file changed, 59 insertions(+), 84 deletions(-)
diff --git a/arch/xtensa/src/common/xtensa_int_handlers.S b/arch/xtensa/src/common/xtensa_int_handlers.S
index 0b40e4e3ab..5f405aa8c0 100644
--- a/arch/xtensa/src/common/xtensa_int_handlers.S
+++ b/arch/xtensa/src/common/xtensa_int_handlers.S
@@ -121,18 +121,58 @@ g_intstacktop:
#endif
/****************************************************************************
- * Macro dispatch_c_isr level mask
+ * Macro: ps_setup
*
* Description:
+ * Set up PS for C, enable interrupts above this level and clear EXCM.
*
- * This will dispatch to user handlers (if any) that are registered in the
- * XTOS dispatch table (_xtos_interrupt_table). These handlers would have
- * been registered by calling _xtos_set_interrupt_handler(). There is one
- * exception - the timer interrupt used by the OS will not be dispatched
- * to a user handler - this must be handled by the caller of this macro.
+ * Entry Conditions:
+ * level - interrupt level
+ * tmp - scratch register
*
- * Level triggered and software interrupts are automatically deasserted by
- * this code.
+ * Side Effects:
+ * PS and scratch register modified
+ *
+ * Assumptions:
+ * - PS.EXCM = 1, C calling disabled
+ *
+ ****************************************************************************/
+
+ .macro ps_setup level tmp
+
+#if 0 /* Nested interrupts no yet supported */
+# ifdef __XTENSA_CALL0_ABI__
+ /* Disable interrupts at level and below */
+
+ movi \tmp, PS_INTLEVEL(\level) | PS_UM
+# else
+ movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
+# endif
+#else
+# ifdef __XTENSA_CALL0_ABI__
+ /* Disable all low- and medium-priority interrupts. Nested are not yet
+ * supported.
+ */
+
+ movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+# else
+ movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+# endif
+#endif
+
+ wsr \tmp, PS
+ rsync
+
+ .endm
+
+/****************************************************************************
+ * Macro dispatch_c_isr level mask tmp
+ *
+ * Description:
+ *
+ * This macro will dispatch the set of pending and enabled interrupts to
+ * their handlers. It just does the necessary configuration and ends up
+ * calling xtensa_int_decode.
*
* Assumptions:
* - PS.INTLEVEL is set to "level" at entry
@@ -150,7 +190,11 @@ g_intstacktop:
*
****************************************************************************/
- .macro dispatch_c_isr level mask
+ .macro dispatch_c_isr level mask tmp
+
+ /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+
+ ps_setup \level \tmp
#ifdef __XTENSA_CALL0_ABI__
/* Get mask of pending, enabled interrupts at this level into a2. */
@@ -233,51 +277,6 @@ g_intstacktop:
1:
.endm
-/****************************************************************************
- * Macro: ps_setup
- *
- * Description:
- * Set up PS for C, enable interrupts above this level and clear EXCM.
- *
- * Entry Conditions:
- * level - interrupt level
- * tmp - scratch register
- *
- * Side Effects:
- * PS and scratch register modified
- *
- * Assumptions:
- * - PS.EXCM = 1, C calling disabled
- *
- ****************************************************************************/
-
- .macro ps_setup level tmp
-
-#if 0 /* Nested interrupts no yet supported */
-# ifdef __XTENSA_CALL0_ABI__
- /* Disable interrupts at level and below */
-
- movi \tmp, PS_INTLEVEL(\level) | PS_UM
-# else
- movi \tmp, PS_INTLEVEL(\level) | PS_UM | PS_WOE
-# endif
-#else
-# ifdef __XTENSA_CALL0_ABI__
- /* Disable all low- and medium-priority interrupts. Nested are not yet
- * supported.
- */
-
- movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-# else
- movi \tmp, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-# endif
-#endif
-
- wsr \tmp, PS
- rsync
-
- .endm
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -322,10 +321,6 @@ _xtensa_level1_handler:
setintstack a13 a14
#endif
- /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-
- ps_setup 1 a0
-
/* Decode and dispatch the interrupt. In the event of an interrupt
* level context dispatch_c_isr() will (1) switch stacks to the new
* thread's and (2) provide the address of the register state save
@@ -333,7 +328,7 @@ _xtensa_level1_handler:
* in the new thread's stack.
*/
- dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
+ dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK a0
/* Restore registers in preparation to return from interrupt */
@@ -420,10 +415,6 @@ _xtensa_level2_handler:
setintstack a13 a14
#endif
- /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-
- ps_setup 2 a0
-
/* Decode and dispatch the interrupt. In the event of an interrupt
* level context dispatch_c_isr() will (1) switch stacks to the new
* thread's and (2) provide the address of the register state save
@@ -431,7 +422,7 @@ _xtensa_level2_handler:
* in the new thread's stack.
*/
- dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
+ dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK a0
/* Restore registers in preparation to return from interrupt */
@@ -493,10 +484,6 @@ _xtensa_level3_handler:
setintstack a13 a14
#endif
- /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-
- ps_setup 3 a0
-
/* Decode and dispatch the interrupt. In the event of an interrupt
* level context dispatch_c_isr() will (1) switch stacks to the new
* thread's and (2) provide the address of the register state save
@@ -504,7 +491,7 @@ _xtensa_level3_handler:
* in the new thread's stack.
*/
- dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
+ dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK a0
/* Restore registers in preparation to return from interrupt */
@@ -566,10 +553,6 @@ _xtensa_level4_handler:
setintstack a13 a14
#endif
- /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-
- ps_setup 4 a0
-
/* Decode and dispatch the interrupt. In the event of an interrupt
* level context dispatch_c_isr() will (1) switch stacks to the new
* thread's and (2) provide the address of the register state save
@@ -577,7 +560,7 @@ _xtensa_level4_handler:
* in the new thread's stack.
*/
- dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
+ dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK a0
/* Restore registers in preparation to return from interrupt */
@@ -639,10 +622,6 @@ _xtensa_level5_handler:
setintstack a13 a14
#endif
- /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-
- ps_setup 5 a0
-
/* Decode and dispatch the interrupt. In the event of an interrupt
* level context dispatch_c_isr() will (1) switch stacks to the new
* thread's and (2) provide the address of the register state save
@@ -650,7 +629,7 @@ _xtensa_level5_handler:
* in the new thread's stack.
*/
- dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
+ dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK a0
/* Restore registers in preparation to return from interrupt */
@@ -712,10 +691,6 @@ _xtensa_level6_handler:
setintstack a13 a14
#endif
- /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-
- ps_setup 6 a0
-
/* Decode and dispatch the interrupt. In the event of an interrupt
* level context dispatch_c_isr() will (1) switch stacks to the new
* thread's and (2) provide the address of the register state save
@@ -723,7 +698,7 @@ _xtensa_level6_handler:
* in the new thread's stack.
*/
- dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
+ dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK a0
/* Restore registers in preparation to return from interrupt */