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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2018/07/26 07:56:51 UTC
[GitHub] mkiiskila closed pull request #1259: TSL2591 driver w/sim stubs
mkiiskila closed pull request #1259: TSL2591 driver w/sim stubs
URL: https://github.com/apache/mynewt-core/pull/1259
This is a PR merged from a forked repository.
As GitHub hides the original diff on merge, it is displayed below for
the sake of provenance:
As this is a foreign pull request (from a fork), the diff is supplied
below (as it won't show otherwise due to GitHub magic):
diff --git a/.gitignore b/.gitignore
index 94f54b44a4..86f93128e2 100644
--- a/.gitignore
+++ b/.gitignore
@@ -35,8 +35,15 @@ docs/html
docs/latex
cscope.*
*.tags
-stlink.log
+stlink.log
+openocd.log
+*.pem
# Prevent accidental checkins of personal targets. If you need to commit a
# target, specify the -f option for "git add".
targets
+
+# Generated directories - pubkey sources, coverity data, etc
+/keys/
+/repos/
+/cov-int/
diff --git a/apps/blecent/pkg.yml b/apps/blecent/pkg.yml
index 29dae6394b..2d14558745 100644
--- a/apps/blecent/pkg.yml
+++ b/apps/blecent/pkg.yml
@@ -23,14 +23,15 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/util
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/util"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
diff --git a/apps/blecent/src/blecent.h b/apps/blecent/src/blecent.h
index 2d598644cd..cce13954c7 100644
--- a/apps/blecent/src/blecent.h
+++ b/apps/blecent/src/blecent.h
@@ -21,7 +21,7 @@
#define H_BLECENT_
#include "os/mynewt.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -32,15 +32,6 @@ struct ble_hs_cfg;
union ble_store_value;
union ble_store_key;
-extern struct log blecent_log;
-
-/* blecent uses the first "peruser" log module. */
-#define BLECENT_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the blecent module. */
-#define BLECENT_LOG(lvl, ...) \
- LOG_ ## lvl(&blecent_log, BLECENT_LOG_MODULE, __VA_ARGS__)
-
#define BLECENT_SVC_ALERT_UUID 0x1811
#define BLECENT_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
#define BLECENT_CHR_NEW_ALERT 0x2A46
diff --git a/apps/blecent/src/main.c b/apps/blecent/src/main.c
index ff44fbf955..f14da346af 100644
--- a/apps/blecent/src/main.c
+++ b/apps/blecent/src/main.c
@@ -38,9 +38,6 @@
/* Application-specified header. */
#include "blecent.h"
-/** Log data. */
-struct log blecent_log;
-
static int blecent_gap_event(struct ble_gap_event *event, void *arg);
/**
@@ -53,13 +50,13 @@ blecent_on_read(uint16_t conn_handle,
struct ble_gatt_attr *attr,
void *arg)
{
- BLECENT_LOG(INFO, "Read complete; status=%d conn_handle=%d", error->status,
+ MODLOG_DFLT(INFO, "Read complete; status=%d conn_handle=%d", error->status,
conn_handle);
if (error->status == 0) {
- BLECENT_LOG(INFO, " attr_handle=%d value=", attr->handle);
+ MODLOG_DFLT(INFO, " attr_handle=%d value=", attr->handle);
print_mbuf(attr->om);
}
- BLECENT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
}
@@ -74,8 +71,8 @@ blecent_on_write(uint16_t conn_handle,
struct ble_gatt_attr *attr,
void *arg)
{
- BLECENT_LOG(INFO, "Write complete; status=%d conn_handle=%d "
- "attr_handle=%d\n",
+ MODLOG_DFLT(INFO,
+ "Write complete; status=%d conn_handle=%d attr_handle=%d\n",
error->status, conn_handle, attr->handle);
return 0;
@@ -91,7 +88,7 @@ blecent_on_subscribe(uint16_t conn_handle,
struct ble_gatt_attr *attr,
void *arg)
{
- BLECENT_LOG(INFO, "Subscribe complete; status=%d conn_handle=%d "
+ MODLOG_DFLT(INFO, "Subscribe complete; status=%d conn_handle=%d "
"attr_handle=%d\n",
error->status, conn_handle, attr->handle);
@@ -123,7 +120,7 @@ blecent_read_write_subscribe(const struct peer *peer)
BLE_UUID16_DECLARE(BLECENT_SVC_ALERT_UUID),
BLE_UUID16_DECLARE(BLECENT_CHR_SUP_NEW_ALERT_CAT_UUID));
if (chr == NULL) {
- BLECENT_LOG(ERROR, "Error: Peer doesn't support the Supported New "
+ MODLOG_DFLT(ERROR, "Error: Peer doesn't support the Supported New "
"Alert Category characteristic\n");
goto err;
}
@@ -131,7 +128,7 @@ blecent_read_write_subscribe(const struct peer *peer)
rc = ble_gattc_read(peer->conn_handle, chr->chr.val_handle,
blecent_on_read, NULL);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Error: Failed to read characteristic; rc=%d\n",
+ MODLOG_DFLT(ERROR, "Error: Failed to read characteristic; rc=%d\n",
rc);
goto err;
}
@@ -143,7 +140,7 @@ blecent_read_write_subscribe(const struct peer *peer)
BLE_UUID16_DECLARE(BLECENT_SVC_ALERT_UUID),
BLE_UUID16_DECLARE(BLECENT_CHR_ALERT_NOT_CTRL_PT));
if (chr == NULL) {
- BLECENT_LOG(ERROR, "Error: Peer doesn't support the Alert "
+ MODLOG_DFLT(ERROR, "Error: Peer doesn't support the Alert "
"Notification Control Point characteristic\n");
goto err;
}
@@ -153,7 +150,7 @@ blecent_read_write_subscribe(const struct peer *peer)
rc = ble_gattc_write_flat(peer->conn_handle, chr->chr.val_handle,
value, sizeof value, blecent_on_write, NULL);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Error: Failed to write characteristic; rc=%d\n",
+ MODLOG_DFLT(ERROR, "Error: Failed to write characteristic; rc=%d\n",
rc);
}
@@ -166,7 +163,7 @@ blecent_read_write_subscribe(const struct peer *peer)
BLE_UUID16_DECLARE(BLECENT_CHR_UNR_ALERT_STAT_UUID),
BLE_UUID16_DECLARE(BLE_GATT_DSC_CLT_CFG_UUID16));
if (dsc == NULL) {
- BLECENT_LOG(ERROR, "Error: Peer lacks a CCCD for the Unread Alert "
+ MODLOG_DFLT(ERROR, "Error: Peer lacks a CCCD for the Unread Alert "
"Status characteristic\n");
goto err;
}
@@ -176,7 +173,7 @@ blecent_read_write_subscribe(const struct peer *peer)
rc = ble_gattc_write_flat(peer->conn_handle, dsc->dsc.handle,
value, sizeof value, blecent_on_subscribe, NULL);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Error: Failed to subscribe to characteristic; "
+ MODLOG_DFLT(ERROR, "Error: Failed to subscribe to characteristic; "
"rc=%d\n", rc);
goto err;
}
@@ -197,7 +194,7 @@ blecent_on_disc_complete(const struct peer *peer, int status, void *arg)
if (status != 0) {
/* Service discovery failed. Terminate the connection. */
- BLECENT_LOG(ERROR, "Error: Service discovery failed; status=%d "
+ MODLOG_DFLT(ERROR, "Error: Service discovery failed; status=%d "
"conn_handle=%d\n", status, peer->conn_handle);
ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM);
return;
@@ -207,7 +204,7 @@ blecent_on_disc_complete(const struct peer *peer, int status, void *arg)
* list of services, characteristics, and descriptors that the peer
* supports.
*/
- BLECENT_LOG(ERROR, "Service discovery complete; status=%d "
+ MODLOG_DFLT(ERROR, "Service discovery complete; status=%d "
"conn_handle=%d\n", status, peer->conn_handle);
/* Now perform three concurrent GATT procedures against the peer: read,
@@ -229,7 +226,7 @@ blecent_scan(void)
/* Figure out address to use while advertising (no privacy for now) */
rc = ble_hs_id_infer_auto(0, &own_addr_type);
if (rc != 0) {
- BLECENT_LOG(ERROR, "error determining address type; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc);
return;
}
@@ -253,7 +250,7 @@ blecent_scan(void)
rc = ble_gap_disc(own_addr_type, BLE_HS_FOREVER, &disc_params,
blecent_gap_event, NULL);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Error initiating GAP discovery procedure; rc=%d\n",
+ MODLOG_DFLT(ERROR, "Error initiating GAP discovery procedure; rc=%d\n",
rc);
}
}
@@ -312,7 +309,7 @@ blecent_connect_if_interesting(const struct ble_gap_disc_desc *disc)
/* Scanning must be stopped before a connection can be initiated. */
rc = ble_gap_disc_cancel();
if (rc != 0) {
- BLECENT_LOG(DEBUG, "Failed to cancel scan; rc=%d\n", rc);
+ MODLOG_DFLT(DEBUG, "Failed to cancel scan; rc=%d\n", rc);
return;
}
@@ -322,9 +319,9 @@ blecent_connect_if_interesting(const struct ble_gap_disc_desc *disc)
rc = ble_gap_connect(BLE_OWN_ADDR_PUBLIC, &disc->addr, 30000, NULL,
blecent_gap_event, NULL);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Error: Failed to connect to device; addr_type=%d "
- "addr=%s\n", disc->addr.type,
- addr_str(disc->addr.val));
+ MODLOG_DFLT(ERROR, "Error: Failed to connect to device; addr_type=%d "
+ "addr=%s\n",
+ disc->addr.type, addr_str(disc->addr.val));
return;
}
}
@@ -369,17 +366,17 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
/* A new connection was established or a connection attempt failed. */
if (event->connect.status == 0) {
/* Connection successfully established. */
- BLECENT_LOG(INFO, "Connection established ");
+ MODLOG_DFLT(INFO, "Connection established ");
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
print_conn_desc(&desc);
- BLECENT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Remember peer. */
rc = peer_add(event->connect.conn_handle);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Failed to add peer; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Failed to add peer; rc=%d\n", rc);
return 0;
}
@@ -387,12 +384,12 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
rc = peer_disc_all(event->connect.conn_handle,
blecent_on_disc_complete, NULL);
if (rc != 0) {
- BLECENT_LOG(ERROR, "Failed to discover services; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc);
return 0;
}
} else {
/* Connection attempt failed; resume scanning. */
- BLECENT_LOG(ERROR, "Error: Connection failed; status=%d\n",
+ MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n",
event->connect.status);
blecent_scan();
}
@@ -401,9 +398,9 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_DISCONNECT:
/* Connection terminated. */
- BLECENT_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
print_conn_desc(&event->disconnect.conn);
- BLECENT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Forget about peer. */
peer_delete(event->disconnect.conn.conn_handle);
@@ -413,13 +410,13 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISC_COMPLETE:
- BLECENT_LOG(INFO, "discovery complete; reason=%d\n",
+ MODLOG_DFLT(INFO, "discovery complete; reason=%d\n",
event->disc_complete.reason);
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BLECENT_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc);
assert(rc == 0);
@@ -428,7 +425,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_NOTIFY_RX:
/* Peer sent us a notification or indication. */
- BLECENT_LOG(INFO, "received %s; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "received %s; conn_handle=%d attr_handle=%d "
"attr_len=%d\n",
event->notify_rx.indication ?
"indication" :
@@ -441,7 +438,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BLECENT_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -471,7 +468,7 @@ blecent_gap_event(struct ble_gap_event *event, void *arg)
static void
blecent_on_reset(int reason)
{
- BLECENT_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -502,13 +499,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the blecent log. */
- log_register("blecent", &blecent_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Configure the host. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = blecent_on_reset;
ble_hs_cfg.sync_cb = blecent_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/blecent/src/misc.c b/apps/blecent/src/misc.c
index eb4af0cc18..6813a12264 100644
--- a/apps/blecent/src/misc.c
+++ b/apps/blecent/src/misc.c
@@ -33,7 +33,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BLECENT_LOG(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -45,7 +45,7 @@ print_mbuf(const struct os_mbuf *om)
colon = 0;
while (om != NULL) {
if (colon) {
- BLECENT_LOG(DEBUG, ":");
+ MODLOG_DFLT(DEBUG, ":");
} else {
colon = 1;
}
@@ -72,7 +72,7 @@ print_uuid(const ble_uuid_t *uuid)
{
char buf[BLE_UUID_STR_LEN];
- BLECENT_LOG(DEBUG, "%s", ble_uuid_to_str(uuid, buf));
+ MODLOG_DFLT(DEBUG, "%s", ble_uuid_to_str(uuid, buf));
}
/**
@@ -81,16 +81,16 @@ print_uuid(const ble_uuid_t *uuid)
void
print_conn_desc(const struct ble_gap_conn_desc *desc)
{
- BLECENT_LOG(DEBUG, "handle=%d our_ota_addr_type=%d our_ota_addr=%s ",
+ MODLOG_DFLT(DEBUG, "handle=%d our_ota_addr_type=%d our_ota_addr=%s ",
desc->conn_handle, desc->our_ota_addr.type,
addr_str(desc->our_ota_addr.val));
- BLECENT_LOG(DEBUG, "our_id_addr_type=%d our_id_addr=%s ",
+ MODLOG_DFLT(DEBUG, "our_id_addr_type=%d our_id_addr=%s ",
desc->our_id_addr.type, addr_str(desc->our_id_addr.val));
- BLECENT_LOG(DEBUG, "peer_ota_addr_type=%d peer_ota_addr=%s ",
+ MODLOG_DFLT(DEBUG, "peer_ota_addr_type=%d peer_ota_addr=%s ",
desc->peer_ota_addr.type, addr_str(desc->peer_ota_addr.val));
- BLECENT_LOG(DEBUG, "peer_id_addr_type=%d peer_id_addr=%s ",
+ MODLOG_DFLT(DEBUG, "peer_id_addr_type=%d peer_id_addr=%s ",
desc->peer_id_addr.type, addr_str(desc->peer_id_addr.val));
- BLECENT_LOG(DEBUG, "conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ MODLOG_DFLT(DEBUG, "conn_itvl=%d conn_latency=%d supervision_timeout=%d "
"encrypted=%d authenticated=%d bonded=%d",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
@@ -108,102 +108,102 @@ print_adv_fields(const struct ble_hs_adv_fields *fields)
int i;
if (fields->flags != 0) {
- BLECENT_LOG(DEBUG, " flags=0x%02x\n", fields->flags);
+ MODLOG_DFLT(DEBUG, " flags=0x%02x\n", fields->flags);
}
if (fields->uuids16 != NULL) {
- BLECENT_LOG(DEBUG, " uuids16(%scomplete)=",
+ MODLOG_DFLT(DEBUG, " uuids16(%scomplete)=",
fields->uuids16_is_complete ? "" : "in");
for (i = 0; i < fields->num_uuids16; i++) {
print_uuid(&fields->uuids16[i].u);
- BLECENT_LOG(DEBUG, " ");
+ MODLOG_DFLT(DEBUG, " ");
}
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->uuids32 != NULL) {
- BLECENT_LOG(DEBUG, " uuids32(%scomplete)=",
+ MODLOG_DFLT(DEBUG, " uuids32(%scomplete)=",
fields->uuids32_is_complete ? "" : "in");
for (i = 0; i < fields->num_uuids32; i++) {
print_uuid(&fields->uuids32[i].u);
- BLECENT_LOG(DEBUG, " ");
+ MODLOG_DFLT(DEBUG, " ");
}
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->uuids128 != NULL) {
- BLECENT_LOG(DEBUG, " uuids128(%scomplete)=",
+ MODLOG_DFLT(DEBUG, " uuids128(%scomplete)=",
fields->uuids128_is_complete ? "" : "in");
for (i = 0; i < fields->num_uuids128; i++) {
print_uuid(&fields->uuids128[i].u);
- BLECENT_LOG(DEBUG, " ");
+ MODLOG_DFLT(DEBUG, " ");
}
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->name != NULL) {
assert(fields->name_len < sizeof s - 1);
memcpy(s, fields->name, fields->name_len);
s[fields->name_len] = '\0';
- BLECENT_LOG(DEBUG, " name(%scomplete)=%s\n",
+ MODLOG_DFLT(DEBUG, " name(%scomplete)=%s\n",
fields->name_is_complete ? "" : "in", s);
}
if (fields->tx_pwr_lvl_is_present) {
- BLECENT_LOG(DEBUG, " tx_pwr_lvl=%d\n", fields->tx_pwr_lvl);
+ MODLOG_DFLT(DEBUG, " tx_pwr_lvl=%d\n", fields->tx_pwr_lvl);
}
if (fields->slave_itvl_range != NULL) {
- BLECENT_LOG(DEBUG, " slave_itvl_range=");
+ MODLOG_DFLT(DEBUG, " slave_itvl_range=");
print_bytes(fields->slave_itvl_range, BLE_HS_ADV_SLAVE_ITVL_RANGE_LEN);
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->svc_data_uuid16 != NULL) {
- BLECENT_LOG(DEBUG, " svc_data_uuid16=");
+ MODLOG_DFLT(DEBUG, " svc_data_uuid16=");
print_bytes(fields->svc_data_uuid16, fields->svc_data_uuid16_len);
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->public_tgt_addr != NULL) {
- BLECENT_LOG(DEBUG, " public_tgt_addr=");
+ MODLOG_DFLT(DEBUG, " public_tgt_addr=");
u8p = fields->public_tgt_addr;
for (i = 0; i < fields->num_public_tgt_addrs; i++) {
- BLECENT_LOG(DEBUG, "public_tgt_addr=%s ", addr_str(u8p));
+ MODLOG_DFLT(DEBUG, "public_tgt_addr=%s ", addr_str(u8p));
u8p += BLE_HS_ADV_PUBLIC_TGT_ADDR_ENTRY_LEN;
}
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->appearance_is_present) {
- BLECENT_LOG(DEBUG, " appearance=0x%04x\n", fields->appearance);
+ MODLOG_DFLT(DEBUG, " appearance=0x%04x\n", fields->appearance);
}
if (fields->adv_itvl_is_present) {
- BLECENT_LOG(DEBUG, " adv_itvl=0x%04x\n", fields->adv_itvl);
+ MODLOG_DFLT(DEBUG, " adv_itvl=0x%04x\n", fields->adv_itvl);
}
if (fields->svc_data_uuid32 != NULL) {
- BLECENT_LOG(DEBUG, " svc_data_uuid32=");
+ MODLOG_DFLT(DEBUG, " svc_data_uuid32=");
print_bytes(fields->svc_data_uuid32, fields->svc_data_uuid32_len);
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->svc_data_uuid128 != NULL) {
- BLECENT_LOG(DEBUG, " svc_data_uuid128=");
+ MODLOG_DFLT(DEBUG, " svc_data_uuid128=");
print_bytes(fields->svc_data_uuid128, fields->svc_data_uuid128_len);
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->uri != NULL) {
- BLECENT_LOG(DEBUG, " uri=");
+ MODLOG_DFLT(DEBUG, " uri=");
print_bytes(fields->uri, fields->uri_len);
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->mfg_data != NULL) {
- BLECENT_LOG(DEBUG, " mfg_data=");
+ MODLOG_DFLT(DEBUG, " mfg_data=");
print_bytes(fields->mfg_data, fields->mfg_data_len);
- BLECENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
}
diff --git a/apps/blecsc/pkg.yml b/apps/blecsc/pkg.yml
index 860ec4a34f..c9ea3e2317 100644
--- a/apps/blecsc/pkg.yml
+++ b/apps/blecsc/pkg.yml
@@ -25,16 +25,17 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/config
- - net/nimble/transport
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/sysinit
- - sys/id
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/config"
+ - "@apache-mynewt-core/net/nimble/transport"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/sysinit"
+ - "@apache-mynewt-core/sys/id"
diff --git a/apps/blecsc/src/blecsc_sens.h b/apps/blecsc/src/blecsc_sens.h
index a73a3b8be0..a06af831af 100644
--- a/apps/blecsc/src/blecsc_sens.h
+++ b/apps/blecsc/src/blecsc_sens.h
@@ -20,22 +20,13 @@
#ifndef H_BLECSC_SENSOR_
#define H_BLECSC_SENSOR_
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "nimble/ble.h"
#ifdef __cplusplus
extern "C" {
#endif
-extern struct log blecsc_log;
-
-/* blecsc uses the first "peruser" log module */
-#define BLECSC_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the blerh module */
-#define BLECSC_LOG(lvl, ...) \
- LOG_ ## lvl(&blecsc_log, BLECSC_LOG_MODULE, __VA_ARGS__)
-
/* Cycling Speed and Cadence configuration */
#define GATT_CSC_UUID 0x1816
#define GATT_CSC_MEASUREMENT_UUID 0x2A5B
diff --git a/apps/blecsc/src/gatt_svr.c b/apps/blecsc/src/gatt_svr.c
index e17a38ed2d..3c81d74592 100644
--- a/apps/blecsc/src/gatt_svr.c
+++ b/apps/blecsc/src/gatt_svr.c
@@ -178,8 +178,8 @@ gatt_svr_chr_access_sc_control_point(uint16_t conn_handle,
assert(ctxt->op == BLE_GATT_ACCESS_OP_WRITE_CHR);
if (!csc_cp_indication_status) {
- BLECSC_LOG(INFO, "SC Control Point; CCC descriptor "
- "improperly configured");
+ MODLOG_DFLT(INFO, "SC Control Point; CCC descriptor "
+ "improperly configured");
return CSC_ERR_CCC_DESC_IMPROPERLY_CONFIGURED;
}
@@ -188,7 +188,7 @@ gatt_svr_chr_access_sc_control_point(uint16_t conn_handle,
if (rc != 0){
return BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN;
}
- BLECSC_LOG(INFO, "SC Control Point; opcode=%d\n", op_code);
+ MODLOG_DFLT(INFO, "SC Control Point; opcode=%d\n", op_code);
/* Allocate response buffer */
om_indication = ble_hs_mbuf_att_pkt();
@@ -207,8 +207,8 @@ gatt_svr_chr_access_sc_control_point(uint16_t conn_handle,
measurement_state->cumulative_wheel_rev =
get_le32(new_cumulative_wheel_rev_arr);
- BLECSC_LOG(INFO, "SC Control Point; Set cumulative value = %d\n",
- measurement_state->cumulative_wheel_rev);
+ MODLOG_DFLT(INFO, "SC Control Point; Set cumulative value = %d\n",
+ measurement_state->cumulative_wheel_rev);
response = SC_CP_RESPONSE_SUCCESS;
break;
@@ -222,8 +222,8 @@ gatt_svr_chr_access_sc_control_point(uint16_t conn_handle,
return BLE_ATT_ERR_INVALID_ATTR_VALUE_LEN;
}
- BLECSC_LOG(INFO, "SC Control Point; Sensor location update = %d\n",
- new_sensor_location);
+ MODLOG_DFLT(INFO, "SC Control Point; Sensor location update = %d\n",
+ new_sensor_location);
/* Verify if requested new location is on supported locations list */
response = SC_CP_RESPONSE_INVALID_PARAM;
@@ -338,13 +338,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BLECSC_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BLECSC_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -352,7 +352,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BLECSC_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/blecsc/src/main.c b/apps/blecsc/src/main.c
index de9c260039..1b1e9c33c2 100644
--- a/apps/blecsc/src/main.c
+++ b/apps/blecsc/src/main.c
@@ -41,9 +41,6 @@
/* Simulated speed upper limit */
#define CSC_SIM_SPEED_KPH_MAX 35
-/* Log data */
-struct log blecsc_log;
-
/* Noticication status */
static bool notify_state = false;
@@ -118,7 +115,7 @@ blecsc_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BLECSC_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -129,7 +126,7 @@ blecsc_advertise(void)
rc = ble_gap_adv_start(blecsc_addr_type, NULL, BLE_HS_FOREVER,
&adv_params, blecsc_gap_event, NULL);
if (rc != 0) {
- BLECSC_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -180,8 +177,8 @@ blecsc_simulate_speed_and_cadence()
csc_measurement_state.last_crank_evt_time += crank_rev_period;
}
- BLECSC_LOG(INFO, "CSC simulated values: speed = %d kph, cadence = %d \n",
- csc_sim_speed_kph, csc_sim_crank_rpm);
+ MODLOG_DFLT(INFO, "CSC simulated values: speed = %d kph, cadence = %d \n",
+ csc_sim_speed_kph, csc_sim_crank_rpm);
}
/* Run CSC measurement simulation and notify it to the client */
@@ -207,7 +204,7 @@ blecsc_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed */
- BLECSC_LOG(INFO, "connection %s; status=%d\n",
+ MODLOG_DFLT(INFO, "connection %s; status=%d\n",
event->connect.status == 0 ? "established" : "failed",
event->connect.status);
@@ -222,34 +219,34 @@ blecsc_gap_event(struct ble_gap_event *event, void *arg)
break;
case BLE_GAP_EVENT_DISCONNECT:
- BLECSC_LOG(INFO, "disconnect; reason=%d\n", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d\n", event->disconnect.reason);
conn_handle = 0;
/* Connection terminated; resume advertising */
blecsc_advertise();
break;
case BLE_GAP_EVENT_ADV_COMPLETE:
- BLECSC_LOG(INFO, "adv complete\n");
+ MODLOG_DFLT(INFO, "adv complete\n");
break;
case BLE_GAP_EVENT_SUBSCRIBE:
- BLECSC_LOG(INFO, "subscribe event attr_handle=%d\n",
- event->subscribe.attr_handle);
+ MODLOG_DFLT(INFO, "subscribe event attr_handle=%d\n",
+ event->subscribe.attr_handle);
if (event->subscribe.attr_handle == csc_measurement_handle) {
notify_state = event->subscribe.cur_notify;
- BLECSC_LOG(INFO, "csc measurement notify state = %d\n",
- notify_state);
+ MODLOG_DFLT(INFO, "csc measurement notify state = %d\n",
+ notify_state);
}
else if (event->subscribe.attr_handle == csc_control_point_handle) {
gatt_svr_set_cp_indicate(event->subscribe.cur_indicate);
- BLECSC_LOG(INFO, "csc control point indicate state = %d\n",
- event->subscribe.cur_indicate);
+ MODLOG_DFLT(INFO, "csc control point indicate state = %d\n",
+ event->subscribe.cur_indicate);
}
break;
case BLE_GAP_EVENT_MTU:
- BLECSC_LOG(INFO, "mtu update event; conn_handle=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.value);
break;
@@ -288,13 +285,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the blecsc log */
- log_register("blecsc_sens_log", &blecsc_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration */
- log_register("blecsc_sens", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.sync_cb = blecsc_on_sync;
/* Initialize measurement and notification timer */
diff --git a/apps/blehci/pkg.yml b/apps/blehci/pkg.yml
index 18ee5dcbd6..2eceeb7c6f 100644
--- a/apps/blehci/pkg.yml
+++ b/apps/blehci/pkg.yml
@@ -23,8 +23,8 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - sys/console/stub
- - sys/stats/full
- - kernel/os
- - net/nimble/controller
- - net/nimble/transport/uart
+ - "@apache-mynewt-core/sys/console/stub"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/transport/uart"
diff --git a/apps/blehr/pkg.yml b/apps/blehr/pkg.yml
index 6c67270e8a..826961b363 100644
--- a/apps/blehr/pkg.yml
+++ b/apps/blehr/pkg.yml
@@ -25,16 +25,17 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/config
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/sysinit
- - sys/id
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/config"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/sysinit"
+ - "@apache-mynewt-core/sys/id"
diff --git a/apps/blehr/src/blehr_sens.h b/apps/blehr/src/blehr_sens.h
index 2eec9ddf45..a3f59ca94f 100644
--- a/apps/blehr/src/blehr_sens.h
+++ b/apps/blehr/src/blehr_sens.h
@@ -20,22 +20,13 @@
#ifndef H_BLEHR_SENSOR_
#define H_BLEHR_SENSOR_
-#include "log/log.h"
#include "nimble/ble.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
-extern struct log blehr_log;
-
-/* blehr uses the first "peruser" log module */
-#define BLEHR_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the blerh module */
-#define BLEHR_LOG(lvl, ...) \
- LOG_ ## lvl(&blehr_log, BLEHR_LOG_MODULE, __VA_ARGS__)
-
/* Heart-rate configuration */
#define GATT_HRS_UUID 0x180D
#define GATT_HRS_MEASUREMENT_UUID 0x2A37
diff --git a/apps/blehr/src/gatt_svr.c b/apps/blehr/src/gatt_svr.c
index eac843e8ab..b2e9b4e0af 100644
--- a/apps/blehr/src/gatt_svr.c
+++ b/apps/blehr/src/gatt_svr.c
@@ -132,13 +132,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BLEHR_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BLEHR_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -146,7 +146,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BLEHR_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/blehr/src/main.c b/apps/blehr/src/main.c
index e538beeb76..217c2b126d 100644
--- a/apps/blehr/src/main.c
+++ b/apps/blehr/src/main.c
@@ -30,9 +30,6 @@
#include "services/gap/ble_svc_gap.h"
#include "blehr_sens.h"
-/* Log data */
-struct log blehr_log;
-
static bool notify_state;
static const char *device_name = "blehr_sensor";
@@ -89,7 +86,7 @@ blehr_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BLEHR_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -100,7 +97,7 @@ blehr_advertise(void)
rc = ble_gap_adv_start(blehr_addr_type, NULL, BLE_HS_FOREVER,
&adv_params, blehr_gap_event, NULL);
if (rc != 0) {
- BLEHR_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -158,7 +155,7 @@ blehr_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed */
- BLEHR_LOG(INFO, "connection %s; status=%d\n",
+ MODLOG_DFLT(INFO, "connection %s; status=%d\n",
event->connect.status == 0 ? "established" : "failed",
event->connect.status);
@@ -169,22 +166,21 @@ blehr_gap_event(struct ble_gap_event *event, void *arg)
break;
case BLE_GAP_EVENT_DISCONNECT:
- BLEHR_LOG(INFO, "disconnect; reason=%d\n", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d\n", event->disconnect.reason);
/* Connection terminated; resume advertising */
blehr_advertise();
break;
case BLE_GAP_EVENT_ADV_COMPLETE:
- BLEHR_LOG(INFO, "adv complete\n");
+ MODLOG_DFLT(INFO, "adv complete\n");
blehr_advertise();
break;
case BLE_GAP_EVENT_SUBSCRIBE:
- BLEHR_LOG(INFO, "subscribe event; cur_notify=%d\n value handle; "
- "val_handle=%d\n",
- event->subscribe.cur_notify,
- hrs_hrm_handle);
+ MODLOG_DFLT(INFO, "subscribe event; cur_notify=%d\n value handle; "
+ "val_handle=%d\n",
+ event->subscribe.cur_notify, hrs_hrm_handle);
if (event->subscribe.attr_handle == hrs_hrm_handle) {
notify_state = event->subscribe.cur_notify;
blehr_tx_hrate_reset();
@@ -195,7 +191,7 @@ blehr_gap_event(struct ble_gap_event *event, void *arg)
break;
case BLE_GAP_EVENT_MTU:
- BLEHR_LOG(INFO, "mtu update event; conn_handle=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.value);
break;
@@ -234,13 +230,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the blehr log */
- log_register("blehr_sens_log", &blehr_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration */
- log_register("blehr_sens", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.sync_cb = blehr_on_sync;
os_callout_init(&blehr_tx_timer, os_eventq_dflt_get(),
diff --git a/apps/blemesh/pkg.yml b/apps/blemesh/pkg.yml
index 50ec78e577..3e80bed3d1 100644
--- a/apps/blemesh/pkg.yml
+++ b/apps/blemesh/pkg.yml
@@ -23,14 +23,15 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/shell
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/shell"
diff --git a/apps/blemesh/src/main.c b/apps/blemesh/src/main.c
index 105ec6f9b2..e0c2ebb890 100644
--- a/apps/blemesh/src/main.c
+++ b/apps/blemesh/src/main.c
@@ -419,8 +419,6 @@ main(int argc, char **argv)
sysinit();
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = blemesh_on_reset;
ble_hs_cfg.sync_cb = blemesh_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/blemesh_light/pkg.yml b/apps/blemesh_light/pkg.yml
index 642cbba9fc..fc4a3a1006 100644
--- a/apps/blemesh_light/pkg.yml
+++ b/apps/blemesh_light/pkg.yml
@@ -23,14 +23,15 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/shell
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/shell"
diff --git a/apps/blemesh_light/src/main.c b/apps/blemesh_light/src/main.c
index 4bab1ed38b..009dd6481a 100755
--- a/apps/blemesh_light/src/main.c
+++ b/apps/blemesh_light/src/main.c
@@ -109,8 +109,6 @@ main(void)
sysinit();
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = blemesh_on_reset;
ble_hs_cfg.sync_cb = blemesh_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/blemesh_shell/pkg.yml b/apps/blemesh_shell/pkg.yml
index 7febc36917..e21cbfddfb 100644
--- a/apps/blemesh_shell/pkg.yml
+++ b/apps/blemesh_shell/pkg.yml
@@ -23,14 +23,15 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/shell
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/shell"
diff --git a/apps/blemesh_shell/src/main.c b/apps/blemesh_shell/src/main.c
index 32aa28ad7b..eb1dfb52a2 100644
--- a/apps/blemesh_shell/src/main.c
+++ b/apps/blemesh_shell/src/main.c
@@ -99,8 +99,6 @@ main(void)
sysinit();
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = blemesh_on_reset;
ble_hs_cfg.sync_cb = blemesh_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/bleprph/pkg.yml b/apps/bleprph/pkg.yml
index 9288db901a..eecbe7649e 100644
--- a/apps/bleprph/pkg.yml
+++ b/apps/bleprph/pkg.yml
@@ -23,21 +23,22 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/split
- - boot/bootutil
- - kernel/os
- - mgmt/imgmgr
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/ble
- - net/nimble/host
- - net/nimble/host/services/ans
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/config
- - net/nimble/host/util
- - net/nimble/transport
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/sysinit
- - sys/id
+ - "@apache-mynewt-core/boot/split"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/ble"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/ans"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/config"
+ - "@apache-mynewt-core/net/nimble/host/util"
+ - "@apache-mynewt-core/net/nimble/transport"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/sysinit"
+ - "@apache-mynewt-core/sys/id"
diff --git a/apps/bleprph/src/bleprph.h b/apps/bleprph/src/bleprph.h
index ec14445946..7d2c80a8f8 100644
--- a/apps/bleprph/src/bleprph.h
+++ b/apps/bleprph/src/bleprph.h
@@ -21,8 +21,8 @@
#define H_BLEPRPH_
#include <stdbool.h>
-#include "log/log.h"
#include "nimble/ble.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -30,15 +30,6 @@ extern "C" {
struct ble_hs_cfg;
struct ble_gatt_register_ctxt;
-extern struct log bleprph_log;
-
-/* bleprph uses the first "peruser" log module. */
-#define BLEPRPH_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the bleprph module. */
-#define BLEPRPH_LOG(lvl, ...) \
- LOG_ ## lvl(&bleprph_log, BLEPRPH_LOG_MODULE, __VA_ARGS__)
-
/** GATT server. */
#define GATT_SVR_SVC_ALERT_UUID 0x1811
#define GATT_SVR_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
diff --git a/apps/bleprph/src/gatt_svr.c b/apps/bleprph/src/gatt_svr.c
index 7025aaf354..632ef4fb01 100644
--- a/apps/bleprph/src/gatt_svr.c
+++ b/apps/bleprph/src/gatt_svr.c
@@ -160,13 +160,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BLEPRPH_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BLEPRPH_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -174,7 +174,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BLEPRPH_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/bleprph/src/main.c b/apps/bleprph/src/main.c
index 29296cc2d9..cae7c2faba 100644
--- a/apps/bleprph/src/main.c
+++ b/apps/bleprph/src/main.c
@@ -38,9 +38,6 @@
/* Application-specified header. */
#include "bleprph.h"
-/** Log data. */
-struct log bleprph_log;
-
static int bleprph_gap_event(struct ble_gap_event *event, void *arg);
/**
@@ -49,19 +46,19 @@ static int bleprph_gap_event(struct ble_gap_event *event, void *arg);
static void
bleprph_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- BLEPRPH_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
print_addr(desc->our_ota_addr.val);
- BLEPRPH_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
print_addr(desc->our_id_addr.val);
- BLEPRPH_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
print_addr(desc->peer_ota_addr.val);
- BLEPRPH_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
print_addr(desc->peer_id_addr.val);
- BLEPRPH_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
"encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
@@ -87,7 +84,7 @@ bleprph_advertise(void)
/* Figure out address to use while advertising (no privacy for now) */
rc = ble_hs_id_infer_auto(0, &own_addr_type);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error determining address type; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc);
return;
}
@@ -128,7 +125,7 @@ bleprph_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -139,7 +136,7 @@ bleprph_advertise(void)
rc = ble_gap_adv_start(own_addr_type, NULL, BLE_HS_FOREVER,
&adv_params, bleprph_gap_event, NULL);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -168,9 +165,9 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- BLEPRPH_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
@@ -180,7 +177,7 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
phy_conn_changed(event->connect.conn_handle);
#endif
}
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -189,9 +186,9 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISCONNECT:
- BLEPRPH_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
bleprph_print_conn_desc(&event->disconnect.conn);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
#if MYNEWT_VAL(BLEPRPH_LE_PHY_SUPPORT)
phy_conn_changed(CONN_HANDLE_INVALID);
@@ -203,32 +200,32 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- BLEPRPH_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bleprph_print_conn_desc(&desc);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_ADV_COMPLETE:
- BLEPRPH_LOG(INFO, "advertise complete; reason=%d",
+ MODLOG_DFLT(INFO, "advertise complete; reason=%d",
event->adv_complete.reason);
bleprph_advertise();
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BLEPRPH_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bleprph_print_conn_desc(&desc);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- BLEPRPH_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -240,7 +237,7 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BLEPRPH_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -276,7 +273,7 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
static void
bleprph_on_reset(int reason)
{
- BLEPRPH_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -308,13 +305,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the bleprph log. */
- log_register("bleprph", &bleprph_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = bleprph_on_reset;
ble_hs_cfg.sync_cb = bleprph_on_sync;
ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb;
diff --git a/apps/bleprph/src/misc.c b/apps/bleprph/src/misc.c
index 8ec785e511..640b7ff8b6 100644
--- a/apps/bleprph/src/misc.c
+++ b/apps/bleprph/src/misc.c
@@ -28,7 +28,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BLEPRPH_LOG(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -38,6 +38,6 @@ print_addr(const void *addr)
const uint8_t *u8p;
u8p = addr;
- BLEPRPH_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
diff --git a/apps/bleprph_oic/pkg.yml b/apps/bleprph_oic/pkg.yml
index ebfc50609c..bd7470ff17 100644
--- a/apps/bleprph_oic/pkg.yml
+++ b/apps/bleprph_oic/pkg.yml
@@ -23,18 +23,19 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - mgmt/oicmgr
- - sys/sysinit
- - sys/shell
- - sys/id
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/mgmt/oicmgr"
+ - "@apache-mynewt-core/sys/sysinit"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/id"
diff --git a/apps/bleprph_oic/src/bleprph.h b/apps/bleprph_oic/src/bleprph.h
index 2e3f024737..d14b53a97a 100644
--- a/apps/bleprph_oic/src/bleprph.h
+++ b/apps/bleprph_oic/src/bleprph.h
@@ -20,7 +20,8 @@
#ifndef H_BLEPRPH_
#define H_BLEPRPH_
-#include "log/log.h"
+#include "os/mynewt.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -30,13 +31,6 @@ struct ble_gatt_register_ctxt;
extern struct log bleprph_log;
-/* bleprph uses the first "peruser" log module. */
-#define BLEPRPH_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the bleprph module. */
-#define BLEPRPH_LOG(lvl, ...) \
- LOG_ ## lvl(&bleprph_log, BLEPRPH_LOG_MODULE, __VA_ARGS__)
-
/** GATT server. */
#define GATT_SVR_SVC_ALERT_UUID 0x1811
#define GATT_SVR_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
diff --git a/apps/bleprph_oic/src/gatt_svr.c b/apps/bleprph_oic/src/gatt_svr.c
index c0670768ad..03791d3eba 100644
--- a/apps/bleprph_oic/src/gatt_svr.c
+++ b/apps/bleprph_oic/src/gatt_svr.c
@@ -31,13 +31,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BLEPRPH_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BLEPRPH_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -45,7 +45,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BLEPRPH_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/bleprph_oic/src/main.c b/apps/bleprph_oic/src/main.c
index e8a1fe3ce1..fa6268459a 100644
--- a/apps/bleprph_oic/src/main.c
+++ b/apps/bleprph_oic/src/main.c
@@ -29,7 +29,6 @@
#include <oic/oc_api.h>
#include <oic/oc_gatt.h>
-#include <oic/oc_log.h>
#include <cborattr/cborattr.h>
/* BLE */
@@ -40,10 +39,6 @@
/* Application-specified header. */
#include "bleprph.h"
-
-/** Log data. */
-struct log bleprph_log;
-
static int bleprph_gap_event(struct ble_gap_event *event, void *arg);
/**
@@ -52,19 +47,19 @@ static int bleprph_gap_event(struct ble_gap_event *event, void *arg);
static void
bleprph_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- BLEPRPH_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
print_addr(desc->our_ota_addr.val);
- BLEPRPH_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
print_addr(desc->our_id_addr.val);
- BLEPRPH_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
print_addr(desc->peer_ota_addr.val);
- BLEPRPH_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
print_addr(desc->peer_id_addr.val);
- BLEPRPH_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
"encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
@@ -133,7 +128,7 @@ bleprph_advertise(void)
#endif
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -144,7 +139,7 @@ bleprph_advertise(void)
rc = ble_gap_adv_start(BLE_OWN_ADDR_PUBLIC, NULL, BLE_HS_FOREVER,
&adv_params, bleprph_gap_event, NULL);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -173,15 +168,15 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- BLEPRPH_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bleprph_print_conn_desc(&desc);
}
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -192,9 +187,9 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISCONNECT:
- BLEPRPH_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
bleprph_print_conn_desc(&event->disconnect.conn);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
oc_ble_coap_conn_del(event->disconnect.conn.conn_handle);
@@ -204,32 +199,32 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- BLEPRPH_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bleprph_print_conn_desc(&desc);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_ADV_COMPLETE:
- BLEPRPH_LOG(INFO, "advertise complete; reason=%d\n",
+ MODLOG_DFLT(INFO, "advertise complete; reason=%d\n",
event->adv_complete.reason);
bleprph_advertise();
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BLEPRPH_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bleprph_print_conn_desc(&desc);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- BLEPRPH_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -241,7 +236,7 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BLEPRPH_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -270,7 +265,7 @@ bleprph_gap_event(struct ble_gap_event *event, void *arg)
static void
bleprph_on_reset(int reason)
{
- BLEPRPH_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -377,16 +372,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the bleprph log. */
- log_register("bleprph", &bleprph_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
- /* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the OIC */
- log_register("oic", &oc_log, &log_console_handler, NULL, LOG_SYSLEVEL);
oc_main_init((oc_handler_t *)&omgr_oc_handler);
oc_ble_coap_gatt_srv_init();
diff --git a/apps/bleprph_oic/src/misc.c b/apps/bleprph_oic/src/misc.c
index 8ec785e511..6ed205ec84 100644
--- a/apps/bleprph_oic/src/misc.c
+++ b/apps/bleprph_oic/src/misc.c
@@ -28,7 +28,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BLEPRPH_LOG(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -38,6 +38,6 @@ print_addr(const void *addr)
const uint8_t *u8p;
u8p = addr;
- BLEPRPH_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
- u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
diff --git a/apps/blesplit/pkg.yml b/apps/blesplit/pkg.yml
index f82c59f999..5e93ab089f 100644
--- a/apps/blesplit/pkg.yml
+++ b/apps/blesplit/pkg.yml
@@ -25,21 +25,23 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/split
- - boot/split_app
- - kernel/os
- - mgmt/imgmgr
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/ble
- - net/nimble/host
- - net/nimble/host/util
- - net/nimble/host/services/ans
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/id
- - sys/log/full
- - sys/shell
- - sys/stats/full
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/boot/split"
+ - "@apache-mynewt-core/boot/split_app"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/ble"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/util"
+ - "@apache-mynewt-core/net/nimble/host/services/ans"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/id"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/stats/full"
diff --git a/apps/blesplit/src/blesplit.h b/apps/blesplit/src/blesplit.h
index 8a04e3eda7..6b17c9beec 100644
--- a/apps/blesplit/src/blesplit.h
+++ b/apps/blesplit/src/blesplit.h
@@ -20,7 +20,8 @@
#ifndef H_BLESPLIT_
#define H_BLESPLIT_
-#include "log/log.h"
+#include "os/mynewt.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -28,15 +29,6 @@ extern "C" {
struct ble_hs_cfg;
struct ble_gatt_register_ctxt;
-extern struct log blesplit_log;
-
-/* blesplit uses the first "peruser" log module. */
-#define BLESPLIT_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the blesplit module. */
-#define BLESPLIT_LOG(lvl, ...) \
- LOG_ ## lvl(&blesplit_log, BLESPLIT_LOG_MODULE, __VA_ARGS__)
-
/** GATT server. */
#define GATT_SVR_SVC_ALERT_UUID 0x1811
#define GATT_SVR_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
diff --git a/apps/blesplit/src/main.c b/apps/blesplit/src/main.c
index eda8352a4d..b4d8caa355 100644
--- a/apps/blesplit/src/main.c
+++ b/apps/blesplit/src/main.c
@@ -38,9 +38,6 @@
/* Application-specified header. */
#include "blesplit.h"
-/** Log data. */
-struct log blesplit_log;
-
static int blesplit_gap_event(struct ble_gap_event *event, void *arg);
/**
@@ -49,19 +46,19 @@ static int blesplit_gap_event(struct ble_gap_event *event, void *arg);
static void
blesplit_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- BLESPLIT_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
print_addr(desc->our_ota_addr.val);
- BLESPLIT_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
print_addr(desc->our_id_addr.val);
- BLESPLIT_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
print_addr(desc->peer_ota_addr.val);
- BLESPLIT_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
print_addr(desc->peer_id_addr.val);
- BLESPLIT_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
"encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
@@ -87,7 +84,7 @@ blesplit_advertise(void)
/* Figure out address to use while advertising (no privacy for now) */
rc = ble_hs_id_infer_auto(0, &own_addr_type);
if (rc != 0) {
- BLESPLIT_LOG(ERROR, "error determining address type; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error determining address type; rc=%d\n", rc);
return;
}
@@ -128,7 +125,7 @@ blesplit_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BLESPLIT_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -139,7 +136,7 @@ blesplit_advertise(void)
rc = ble_gap_adv_start(own_addr_type, NULL, BLE_HS_FOREVER,
&adv_params, blesplit_gap_event, NULL);
if (rc != 0) {
- BLESPLIT_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -168,15 +165,15 @@ blesplit_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- BLESPLIT_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
blesplit_print_conn_desc(&desc);
}
- BLESPLIT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -185,9 +182,9 @@ blesplit_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISCONNECT:
- BLESPLIT_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
blesplit_print_conn_desc(&event->disconnect.conn);
- BLESPLIT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Connection terminated; resume advertising. */
blesplit_advertise();
@@ -195,33 +192,33 @@ blesplit_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- BLESPLIT_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
blesplit_print_conn_desc(&desc);
- BLESPLIT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_ADV_COMPLETE:
- BLESPLIT_LOG(INFO, "advertise complete; reason=%d\n",
- event->adv_complete.reason);
+ MODLOG_DFLT(INFO, "advertise complete; reason=%d\n",
+ event->adv_complete.reason);
blesplit_advertise();
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BLESPLIT_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
blesplit_print_conn_desc(&desc);
- BLESPLIT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- BLESPLIT_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -233,7 +230,7 @@ blesplit_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BLESPLIT_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -262,7 +259,7 @@ blesplit_gap_event(struct ble_gap_event *event, void *arg)
static void
blesplit_on_reset(int reason)
{
- BLESPLIT_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -294,13 +291,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the blesplit log. */
- log_register("blesplit", &blesplit_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = blesplit_on_reset;
ble_hs_cfg.sync_cb = blesplit_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/blesplit/src/misc.c b/apps/blesplit/src/misc.c
index 43f62ae6bd..3c11d916ff 100644
--- a/apps/blesplit/src/misc.c
+++ b/apps/blesplit/src/misc.c
@@ -28,7 +28,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BLESPLIT_LOG(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -38,6 +38,6 @@ print_addr(const void *addr)
const uint8_t *u8p;
u8p = addr;
- BLESPLIT_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
- u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
diff --git a/apps/bletest/pkg.yml b/apps/bletest/pkg.yml
index 54d87985f3..5ef77e5654 100644
--- a/apps/bletest/pkg.yml
+++ b/apps/bletest/pkg.yml
@@ -25,13 +25,14 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/transport/ram
- - kernel/os
- - sys/console/full
- - sys/shell
- - sys/config
- - sys/log/full
- - sys/stats/full
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
pkg.cflags: -DBLETEST
diff --git a/apps/bletest/src/main.c b/apps/bletest/src/main.c
index da76e8b29b..8a5367a9b0 100644
--- a/apps/bletest/src/main.c
+++ b/apps/bletest/src/main.c
@@ -1299,9 +1299,6 @@ main(void)
g_bletest_cur_peer_addr[5] = 0x08;
#endif
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Set the led pin as an output */
g_led_pin = LED_BLINK_PIN;
hal_gpio_init_out(g_led_pin, 1);
diff --git a/apps/bleuart/pkg.yml b/apps/bleuart/pkg.yml
index f8a6d7daa8..7aa0ad9354 100644
--- a/apps/bleuart/pkg.yml
+++ b/apps/bleuart/pkg.yml
@@ -23,18 +23,19 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - libc/baselibc
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/ble
- - net/nimble/host/services/bleuart
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/libc/baselibc"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/ble"
+ - "@apache-mynewt-core/net/nimble/host/services/bleuart"
diff --git a/apps/bleuart/src/main.c b/apps/bleuart/src/main.c
index 6817f02ba4..d9b5d88f3b 100644
--- a/apps/bleuart/src/main.c
+++ b/apps/bleuart/src/main.c
@@ -208,8 +208,6 @@ main(void)
sysinit();
/* Initialize the BLE host. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.sync_cb = bleuart_on_sync;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/boot/pkg.yml b/apps/boot/pkg.yml
index 30e45ea721..7d07516162 100644
--- a/apps/boot/pkg.yml
+++ b/apps/boot/pkg.yml
@@ -26,9 +26,9 @@ pkg.keywords:
- loader
pkg.deps:
- - boot/bootutil
- - kernel/os
- - sys/console/stub
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/console/stub"
pkg.deps.BOOT_SERIAL:
- - boot/boot_serial
+ - "@apache-mynewt-core/boot/boot_serial"
diff --git a/apps/bsncent/pkg.yml b/apps/bsncent/pkg.yml
index 6ce9462d96..bfa57ebc2d 100644
--- a/apps/bsncent/pkg.yml
+++ b/apps/bsncent/pkg.yml
@@ -23,13 +23,14 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
diff --git a/apps/bsncent/src/bsncent.h b/apps/bsncent/src/bsncent.h
index 5aa742d5af..8363f5e849 100644
--- a/apps/bsncent/src/bsncent.h
+++ b/apps/bsncent/src/bsncent.h
@@ -21,7 +21,7 @@
#define H_BSNCENT_
#include "os/mynewt.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -32,15 +32,6 @@ struct ble_hs_cfg;
union ble_store_value;
union ble_store_key;
-extern struct log bsncent_log;
-
-/* bsncent uses the first "peruser" log module. */
-#define BSNCENT_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the bsncent module. */
-#define BSNCENT_LOG(lvl, ...) \
- LOG_ ## lvl(&bsncent_log, BSNCENT_LOG_MODULE, __VA_ARGS__)
-
#define BSNCENT_SVC_GENDATA 0x1811
#define BSNCENT_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
#define BSNCENT_CHR_NEW_ALERT 0x2A46
diff --git a/apps/bsncent/src/main.c b/apps/bsncent/src/main.c
index 029eebca36..bb9d4bdc71 100644
--- a/apps/bsncent/src/main.c
+++ b/apps/bsncent/src/main.c
@@ -21,6 +21,7 @@
#include <string.h>
#include "os/mynewt.h"
#include "bsp/bsp.h"
+#include "console/console.h"
/* BLE */
#include "nimble/ble.h"
@@ -39,8 +40,6 @@
#define BSNCENT_PRINT_RATE (OS_TICKS_PER_SEC * 10)
-struct log bsncent_log;
-
static uint32_t num_notify_pkts_rx;
static uint32_t num_notify_bytes_rx;
@@ -94,7 +93,7 @@ bsncent_on_subscribe(uint16_t conn_handle,
struct ble_gatt_attr *attr,
void *arg)
{
- BSNCENT_LOG(INFO, "Subscribe complete; status=%d conn_handle=%d "
+ MODLOG_DFLT(INFO, "Subscribe complete; status=%d conn_handle=%d "
"attr_handle=%d\n",
error->status, conn_handle, attr->handle);
@@ -130,7 +129,7 @@ bsncent_subscribe(const struct peer *peer)
&bsncent_chr_gendata_uuid.u,
BLE_UUID16_DECLARE(BLE_GATT_DSC_CLT_CFG_UUID16));
if (dsc == NULL) {
- BSNCENT_LOG(ERROR, "Error: Peer lacks a CCCD for the generic data "
+ MODLOG_DFLT(ERROR, "Error: Peer lacks a CCCD for the generic data "
"characteristic\n");
goto err;
}
@@ -140,7 +139,7 @@ bsncent_subscribe(const struct peer *peer)
rc = ble_gattc_write_flat(peer->conn_handle, dsc->dsc.handle,
value, sizeof value, bsncent_on_subscribe, NULL);
if (rc != 0) {
- BSNCENT_LOG(ERROR, "Error: Failed to subscribe to characteristic; "
+ MODLOG_DFLT(ERROR, "Error: Failed to subscribe to characteristic; "
"rc=%d\n", rc);
goto err;
}
@@ -161,7 +160,7 @@ bsncent_on_disc_complete(const struct peer *peer, int status, void *arg)
if (status != 0) {
/* Service discovery failed. Terminate the connection. */
- BSNCENT_LOG(ERROR, "Error: Service discovery failed; status=%d "
+ MODLOG_DFLT(ERROR, "Error: Service discovery failed; status=%d "
"conn_handle=%d\n", status, peer->conn_handle);
ble_gap_terminate(peer->conn_handle, BLE_ERR_REM_USER_CONN_TERM);
return;
@@ -171,7 +170,7 @@ bsncent_on_disc_complete(const struct peer *peer, int status, void *arg)
* list of services, characteristics, and descriptors that the peer
* supports.
*/
- BSNCENT_LOG(ERROR, "Service discovery complete; status=%d "
+ MODLOG_DFLT(ERROR, "Service discovery complete; status=%d "
"conn_handle=%d\n", status, peer->conn_handle);
/* Now subscribe to the gendata characterustic. */
@@ -187,7 +186,7 @@ bsncent_on_mtu_exchanged(uint16_t conn_handle,
int rc;
if (error->status != 0) {
- BSNCENT_LOG(ERROR, "MTU exchange failed; rc=%d\n", error->status);
+ MODLOG_DFLT(ERROR, "MTU exchange failed; rc=%d\n", error->status);
ble_gap_terminate(conn_handle, BLE_ERR_REM_USER_CONN_TERM);
return 0;
}
@@ -195,7 +194,7 @@ bsncent_on_mtu_exchanged(uint16_t conn_handle,
/* Perform service discovery. */
rc = peer_disc_all(conn_handle, bsncent_on_disc_complete, NULL);
if (rc != 0) {
- BSNCENT_LOG(ERROR, "Failed to discover services; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Failed to discover services; rc=%d\n", rc);
ble_gap_terminate(conn_handle, BLE_ERR_REM_USER_CONN_TERM);
return 0;
}
@@ -211,7 +210,7 @@ bsncent_connect(void)
rc = ble_gap_connect(BLE_OWN_ADDR_PUBLIC, NULL, BLE_HS_FOREVER,
&ble_gap_conn_params_bsn, bsncent_gap_event, NULL);
if (rc != 0) {
- BSNCENT_LOG(ERROR, "Error connecting; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Error connecting; rc=%d\n", rc);
if (!((rc == BLE_HS_EALREADY) || (rc == BLE_HS_EBUSY))) {
/* Only assert if we are not already trying */
assert(0);
@@ -226,7 +225,7 @@ bsncent_fill_wl(void)
rc = ble_gap_wl_set(bsncent_peer_addrs, bsncent_num_peer_addrs);
if (rc != 0) {
- BSNCENT_LOG(ERROR, "Error setting white list; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Error setting white list; rc=%d\n", rc);
assert(0);
}
}
@@ -303,17 +302,17 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
/* A new connection was established or a connection attempt failed. */
if (event->connect.status == 0) {
/* Connection successfully established. */
- BSNCENT_LOG(INFO, "Connection established ");
+ MODLOG_DFLT(INFO, "Connection established ");
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
print_conn_desc(&desc);
- BSNCENT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Remember peer. */
rc = peer_add(event->connect.conn_handle);
if (rc != 0) {
- BSNCENT_LOG(ERROR, "Failed to add peer; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Failed to add peer; rc=%d\n", rc);
assert(0);
}
@@ -326,12 +325,12 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
rc = ble_gattc_exchange_mtu(event->connect.conn_handle,
bsncent_on_mtu_exchanged, NULL);
if (rc != 0) {
- BSNCENT_LOG(ERROR, "Failed to exchange MTU; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "Failed to exchange MTU; rc=%d\n", rc);
return 0;
}
} else {
/* Connection attempt failed; resume connecting. */
- BSNCENT_LOG(ERROR, "Error: Connection failed; status=%d\n",
+ MODLOG_DFLT(ERROR, "Error: Connection failed; status=%d\n",
event->connect.status);
bsncent_connect();
}
@@ -340,9 +339,9 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_DISCONNECT:
/* Connection terminated. */
- BSNCENT_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
print_conn_desc(&event->disconnect.conn);
- BSNCENT_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Forget about peer. */
peer_delete(event->disconnect.conn.conn_handle);
@@ -353,7 +352,7 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BSNCENT_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->enc_change.conn_handle, &desc);
assert(rc == 0);
@@ -362,7 +361,7 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_NOTIFY_RX:
/* Peer sent us a notification or indication. */
- BSNCENT_LOG(DEBUG, "received %s; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(DEBUG, "received %s; conn_handle=%d attr_handle=%d "
"attr_len=%d\n",
event->notify_rx.indication ?
"indication" :
@@ -378,7 +377,7 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BSNCENT_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -392,7 +391,7 @@ bsncent_gap_event(struct ble_gap_event *event, void *arg)
static void
bsncent_on_reset(int reason)
{
- BSNCENT_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -426,13 +425,7 @@ main(void)
/* Initialize OS */
sysinit();
- /* Initialize the bsncent log. */
- log_register("bsncent", &bsncent_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Configure the host. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = bsncent_on_reset;
ble_hs_cfg.sync_cb = bsncent_on_sync;
diff --git a/apps/bsncent/src/misc.c b/apps/bsncent/src/misc.c
index 910a3046da..7b00273270 100644
--- a/apps/bsncent/src/misc.c
+++ b/apps/bsncent/src/misc.c
@@ -33,7 +33,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BSNCENT_LOG(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(DEBUG, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -45,7 +45,7 @@ print_mbuf(const struct os_mbuf *om)
colon = 0;
while (om != NULL) {
if (colon) {
- BSNCENT_LOG(DEBUG, ":");
+ MODLOG_DFLT(DEBUG, ":");
} else {
colon = 1;
}
@@ -72,7 +72,7 @@ print_uuid(const ble_uuid_t *uuid)
{
char buf[BLE_UUID_STR_LEN];
- BSNCENT_LOG(DEBUG, "%s", ble_uuid_to_str(uuid, buf));
+ MODLOG_DFLT(DEBUG, "%s", ble_uuid_to_str(uuid, buf));
}
/**
@@ -81,16 +81,16 @@ print_uuid(const ble_uuid_t *uuid)
void
print_conn_desc(const struct ble_gap_conn_desc *desc)
{
- BSNCENT_LOG(DEBUG, "handle=%d our_ota_addr_type=%d our_ota_addr=%s ",
+ MODLOG_DFLT(DEBUG, "handle=%d our_ota_addr_type=%d our_ota_addr=%s ",
desc->conn_handle, desc->our_ota_addr.type,
addr_str(desc->our_ota_addr.val));
- BSNCENT_LOG(DEBUG, "our_id_addr_type=%d our_id_addr=%s ",
+ MODLOG_DFLT(DEBUG, "our_id_addr_type=%d our_id_addr=%s ",
desc->our_id_addr.type, addr_str(desc->our_id_addr.val));
- BSNCENT_LOG(DEBUG, "peer_ota_addr_type=%d peer_ota_addr=%s ",
+ MODLOG_DFLT(DEBUG, "peer_ota_addr_type=%d peer_ota_addr=%s ",
desc->peer_ota_addr.type, addr_str(desc->peer_ota_addr.val));
- BSNCENT_LOG(DEBUG, "peer_id_addr_type=%d peer_id_addr=%s ",
+ MODLOG_DFLT(DEBUG, "peer_id_addr_type=%d peer_id_addr=%s ",
desc->peer_id_addr.type, addr_str(desc->peer_id_addr.val));
- BSNCENT_LOG(DEBUG, "conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ MODLOG_DFLT(DEBUG, "conn_itvl=%d conn_latency=%d supervision_timeout=%d "
"encrypted=%d authenticated=%d bonded=%d",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
@@ -108,102 +108,102 @@ print_adv_fields(const struct ble_hs_adv_fields *fields)
int i;
if (fields->flags != 0) {
- BSNCENT_LOG(DEBUG, " flags=0x%02x\n", fields->flags);
+ MODLOG_DFLT(DEBUG, " flags=0x%02x\n", fields->flags);
}
if (fields->uuids16 != NULL) {
- BSNCENT_LOG(DEBUG, " uuids16(%scomplete)=",
+ MODLOG_DFLT(DEBUG, " uuids16(%scomplete)=",
fields->uuids16_is_complete ? "" : "in");
for (i = 0; i < fields->num_uuids16; i++) {
print_uuid(&fields->uuids16[i].u);
- BSNCENT_LOG(DEBUG, " ");
+ MODLOG_DFLT(DEBUG, " ");
}
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->uuids32 != NULL) {
- BSNCENT_LOG(DEBUG, " uuids32(%scomplete)=",
+ MODLOG_DFLT(DEBUG, " uuids32(%scomplete)=",
fields->uuids32_is_complete ? "" : "in");
for (i = 0; i < fields->num_uuids32; i++) {
print_uuid(&fields->uuids32[i].u);
- BSNCENT_LOG(DEBUG, " ");
+ MODLOG_DFLT(DEBUG, " ");
}
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->uuids128 != NULL) {
- BSNCENT_LOG(DEBUG, " uuids128(%scomplete)=",
+ MODLOG_DFLT(DEBUG, " uuids128(%scomplete)=",
fields->uuids128_is_complete ? "" : "in");
for (i = 0; i < fields->num_uuids128; i++) {
print_uuid(&fields->uuids128[i].u);
- BSNCENT_LOG(DEBUG, " ");
+ MODLOG_DFLT(DEBUG, " ");
}
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->name != NULL) {
assert(fields->name_len < sizeof s - 1);
memcpy(s, fields->name, fields->name_len);
s[fields->name_len] = '\0';
- BSNCENT_LOG(DEBUG, " name(%scomplete)=%s\n",
+ MODLOG_DFLT(DEBUG, " name(%scomplete)=%s\n",
fields->name_is_complete ? "" : "in", s);
}
if (fields->tx_pwr_lvl_is_present) {
- BSNCENT_LOG(DEBUG, " tx_pwr_lvl=%d\n", fields->tx_pwr_lvl);
+ MODLOG_DFLT(DEBUG, " tx_pwr_lvl=%d\n", fields->tx_pwr_lvl);
}
if (fields->slave_itvl_range != NULL) {
- BSNCENT_LOG(DEBUG, " slave_itvl_range=");
+ MODLOG_DFLT(DEBUG, " slave_itvl_range=");
print_bytes(fields->slave_itvl_range, BLE_HS_ADV_SLAVE_ITVL_RANGE_LEN);
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->svc_data_uuid16 != NULL) {
- BSNCENT_LOG(DEBUG, " svc_data_uuid16=");
+ MODLOG_DFLT(DEBUG, " svc_data_uuid16=");
print_bytes(fields->svc_data_uuid16, fields->svc_data_uuid16_len);
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->public_tgt_addr != NULL) {
- BSNCENT_LOG(DEBUG, " public_tgt_addr=");
+ MODLOG_DFLT(DEBUG, " public_tgt_addr=");
u8p = fields->public_tgt_addr;
for (i = 0; i < fields->num_public_tgt_addrs; i++) {
- BSNCENT_LOG(DEBUG, "public_tgt_addr=%s ", addr_str(u8p));
+ MODLOG_DFLT(DEBUG, "public_tgt_addr=%s ", addr_str(u8p));
u8p += BLE_HS_ADV_PUBLIC_TGT_ADDR_ENTRY_LEN;
}
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->appearance_is_present) {
- BSNCENT_LOG(DEBUG, " appearance=0x%04x\n", fields->appearance);
+ MODLOG_DFLT(DEBUG, " appearance=0x%04x\n", fields->appearance);
}
if (fields->adv_itvl_is_present) {
- BSNCENT_LOG(DEBUG, " adv_itvl=0x%04x\n", fields->adv_itvl);
+ MODLOG_DFLT(DEBUG, " adv_itvl=0x%04x\n", fields->adv_itvl);
}
if (fields->svc_data_uuid32 != NULL) {
- BSNCENT_LOG(DEBUG, " svc_data_uuid32=");
+ MODLOG_DFLT(DEBUG, " svc_data_uuid32=");
print_bytes(fields->svc_data_uuid32, fields->svc_data_uuid32_len);
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->svc_data_uuid128 != NULL) {
- BSNCENT_LOG(DEBUG, " svc_data_uuid128=");
+ MODLOG_DFLT(DEBUG, " svc_data_uuid128=");
print_bytes(fields->svc_data_uuid128, fields->svc_data_uuid128_len);
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->uri != NULL) {
- BSNCENT_LOG(DEBUG, " uri=");
+ MODLOG_DFLT(DEBUG, " uri=");
print_bytes(fields->uri, fields->uri_len);
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
if (fields->mfg_data != NULL) {
- BSNCENT_LOG(DEBUG, " mfg_data=");
+ MODLOG_DFLT(DEBUG, " mfg_data=");
print_bytes(fields->mfg_data, fields->mfg_data_len);
- BSNCENT_LOG(DEBUG, "\n");
+ MODLOG_DFLT(DEBUG, "\n");
}
}
diff --git a/apps/bsnprph/pkg.yml b/apps/bsnprph/pkg.yml
index c0002ceffe..b4dbc1e0ea 100644
--- a/apps/bsnprph/pkg.yml
+++ b/apps/bsnprph/pkg.yml
@@ -23,21 +23,22 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - boot/split
- - kernel/os
- - mgmt/imgmgr
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/ble
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/ans
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - sys/sysinit
- - sys/id
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/boot/split"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/ble"
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/ans"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/sysinit"
+ - "@apache-mynewt-core/sys/id"
diff --git a/apps/bsnprph/src/bleprph.h b/apps/bsnprph/src/bleprph.h
deleted file mode 100644
index afcbb72e22..0000000000
--- a/apps/bsnprph/src/bleprph.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#ifndef H_BLEPRPH_
-#define H_BLEPRPH_
-
-#include "log/log.h"
-#include "nimble/ble.h"
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct ble_hs_cfg;
-struct ble_gatt_register_ctxt;
-
-extern struct log bleprph_log;
-
-/* bleprph uses the first "peruser" log module. */
-#define BLEPRPH_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the bleprph module. */
-#define BLEPRPH_LOG(lvl, ...) \
- LOG_ ## lvl(&bleprph_log, BLEPRPH_LOG_MODULE, __VA_ARGS__)
-
-/** GATT server. */
-#define GATT_SVR_SVC_ALERT_UUID 0x1811
-#define GATT_SVR_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
-#define GATT_SVR_CHR_NEW_ALERT 0x2A46
-#define GATT_SVR_CHR_SUP_UNR_ALERT_CAT_UUID 0x2A48
-#define GATT_SVR_CHR_UNR_ALERT_STAT_UUID 0x2A45
-#define GATT_SVR_CHR_ALERT_NOT_CTRL_PT 0x2A44
-
-void gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg);
-int gatt_svr_init(void);
-
-/** Misc. */
-void print_bytes(const uint8_t *bytes, int len);
-void print_addr(const void *addr);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/apps/bsnprph/src/bsnprph.h b/apps/bsnprph/src/bsnprph.h
index d8e814f245..e305ac70d2 100644
--- a/apps/bsnprph/src/bsnprph.h
+++ b/apps/bsnprph/src/bsnprph.h
@@ -20,7 +20,8 @@
#ifndef H_BSNPRPH_
#define H_BSNPRPH_
-#include "log/log.h"
+#include "os/mynewt.h"
+#include "modlog/modlog.h"
#include "nimble/ble.h"
#ifdef __cplusplus
extern "C" {
@@ -29,15 +30,6 @@ extern "C" {
struct ble_hs_cfg;
struct ble_gatt_register_ctxt;
-extern struct log bsnprph_log;
-
-/* bsnprph uses the first "peruser" log module. */
-#define BSNPRPH_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the bsnprph module. */
-#define BSNPRPH_LOG(lvl, ...) \
- LOG_ ## lvl(&bsnprph_log, BSNPRPH_LOG_MODULE, __VA_ARGS__)
-
/** GATT server. */
#define GATT_SVR_SVC_ALERT_UUID 0x1811
#define GATT_SVR_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
diff --git a/apps/bsnprph/src/gatt_svr.c b/apps/bsnprph/src/gatt_svr.c
index f8c2af9dba..eefb57bba5 100644
--- a/apps/bsnprph/src/gatt_svr.c
+++ b/apps/bsnprph/src/gatt_svr.c
@@ -87,13 +87,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BSNPRPH_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BSNPRPH_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -101,7 +101,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BSNPRPH_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/bsnprph/src/main.c b/apps/bsnprph/src/main.c
index a47722b6e7..64c6526ec9 100644
--- a/apps/bsnprph/src/main.c
+++ b/apps/bsnprph/src/main.c
@@ -49,8 +49,6 @@ static const ble_addr_t bsnprph_central_addr = {
{ 0x0a, 0x0b, 0x09, 0x09, 0x09, 0x00 },
};
-struct log bsnprph_log;
-
/* Sends data to central at 60 Hz. */
static struct os_callout bsnprph_tx_timer;
@@ -65,19 +63,19 @@ static int bsnprph_gap_event(struct ble_gap_event *event, void *arg);
static void
bsnprph_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- BSNPRPH_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
print_addr(desc->our_ota_addr.val);
- BSNPRPH_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
print_addr(desc->our_id_addr.val);
- BSNPRPH_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
print_addr(desc->peer_ota_addr.val);
- BSNPRPH_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
print_addr(desc->peer_id_addr.val);
- BSNPRPH_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
"encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
@@ -136,7 +134,7 @@ bsnprph_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BSNPRPH_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -149,7 +147,7 @@ bsnprph_advertise(void)
BLE_HS_FOREVER, &adv_params,
bsnprph_gap_event, NULL);
if (rc != 0) {
- BSNPRPH_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -216,9 +214,9 @@ bsnprph_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- BSNPRPH_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
@@ -226,7 +224,7 @@ bsnprph_gap_event(struct ble_gap_event *event, void *arg)
bsnprph_conn_handle = event->connect.conn_handle;
}
- BSNPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -237,9 +235,9 @@ bsnprph_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_DISCONNECT:
os_callout_stop(&bsnprph_tx_timer);
- BSNPRPH_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
bsnprph_print_conn_desc(&event->disconnect.conn);
- BSNPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Connection terminated; resume advertising. */
bsnprph_advertise();
@@ -247,32 +245,32 @@ bsnprph_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_ADV_COMPLETE:
os_callout_stop(&bsnprph_tx_timer);
- BSNPRPH_LOG(INFO, "adv complete\n");
+ MODLOG_DFLT(INFO, "adv complete\n");
bsnprph_advertise();
return 0;
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- BSNPRPH_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bsnprph_print_conn_desc(&desc);
- BSNPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BSNPRPH_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
bsnprph_print_conn_desc(&desc);
- BSNPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- BSNPRPH_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -288,7 +286,7 @@ bsnprph_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BSNPRPH_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -301,7 +299,7 @@ bsnprph_gap_event(struct ble_gap_event *event, void *arg)
static void
bsnprph_on_reset(int reason)
{
- BSNPRPH_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -330,13 +328,7 @@ main(void)
/* Set initial BLE device address. */
memcpy(g_dev_addr, bsnprph_prph_public_addr, 6);
- /* Initialize the bsnprph log. */
- log_register("bsnprph", &bsnprph_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = bsnprph_on_reset;
ble_hs_cfg.sync_cb = bsnprph_on_sync;
ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb;
diff --git a/apps/bsnprph/src/misc.c b/apps/bsnprph/src/misc.c
index 72dc813a7c..6b2e58432c 100644
--- a/apps/bsnprph/src/misc.c
+++ b/apps/bsnprph/src/misc.c
@@ -28,7 +28,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BSNPRPH_LOG(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -38,6 +38,6 @@ print_addr(const void *addr)
const uint8_t *u8p;
u8p = addr;
- BSNPRPH_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
- u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
diff --git a/apps/btshell/pkg.yml b/apps/btshell/pkg.yml
index 2e1084ce6c..b2c2987765 100644
--- a/apps/btshell/pkg.yml
+++ b/apps/btshell/pkg.yml
@@ -23,16 +23,17 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport
- - sys/log/full
- - sys/stats/full
- - sys/console/full
- - sys/shell
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/shell"
pkg.deps.BTSHELL_ANS:
- - net/nimble/host/services/ans
+ - "@apache-mynewt-core/net/nimble/host/services/ans"
diff --git a/apps/btshell/src/btshell.h b/apps/btshell/src/btshell.h
index 8b181f22d6..0d3a50aa23 100644
--- a/apps/btshell/src/btshell.h
+++ b/apps/btshell/src/btshell.h
@@ -24,7 +24,7 @@
#include "os/mynewt.h"
#include "nimble/ble.h"
#include "nimble/nimble_opt.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "host/ble_gatt.h"
#include "host/ble_gap.h"
@@ -89,7 +89,6 @@ struct btshell_scan_opts {
extern struct btshell_conn btshell_conns[MYNEWT_VAL(BLE_MAX_CONNECTIONS)];
extern int btshell_num_conns;
-extern struct log btshell_log;
int btshell_exchange_mtu(uint16_t conn_handle);
int btshell_disc_svcs(uint16_t conn_handle);
int btshell_disc_svc_by_uuid(uint16_t conn_handle, const ble_uuid_t *uuid);
@@ -165,9 +164,6 @@ int btshell_l2cap_create_srv(uint16_t psm, int accept_response);
int btshell_l2cap_connect(uint16_t conn, uint16_t psm);
int btshell_l2cap_disconnect(uint16_t conn, uint16_t idx);
int btshell_l2cap_send(uint16_t conn, uint16_t idx, uint16_t bytes);
-#define BTSHELL_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-#define BTSHELL_LOG(lvl, ...) \
- LOG_ ## lvl(&btshell_log, BTSHELL_LOG_MODULE, __VA_ARGS__)
/** GATT server. */
#define GATT_SVR_SVC_ALERT_UUID 0x1811
diff --git a/apps/btshell/src/gatt_svr.c b/apps/btshell/src/gatt_svr.c
index 792a41772c..ba52158581 100644
--- a/apps/btshell/src/gatt_svr.c
+++ b/apps/btshell/src/gatt_svr.c
@@ -545,13 +545,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BTSHELL_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BTSHELL_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -559,7 +559,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BTSHELL_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/btshell/src/main.c b/apps/btshell/src/main.c
index 103668270a..a794fb87a5 100644
--- a/apps/btshell/src/main.c
+++ b/apps/btshell/src/main.c
@@ -74,8 +74,6 @@
#define PTR_TO_INT(x) (int) ((intptr_t)(x))
#endif
-struct log btshell_log;
-
bssnz_t struct btshell_conn btshell_conns[MYNEWT_VAL(BLE_MAX_CONNECTIONS)];
int btshell_num_conns;
@@ -390,7 +388,7 @@ btshell_svc_add(uint16_t conn_handle, const struct ble_gatt_svc *gatt_svc)
conn = btshell_conn_find(conn_handle);
if (conn == NULL) {
- BTSHELL_LOG(DEBUG, "RECEIVED SERVICE FOR UNKNOWN CONNECTION; "
+ MODLOG_DFLT(DEBUG, "RECEIVED SERVICE FOR UNKNOWN CONNECTION; "
"HANDLE=%d\n",
conn_handle);
return NULL;
@@ -404,7 +402,7 @@ btshell_svc_add(uint16_t conn_handle, const struct ble_gatt_svc *gatt_svc)
svc = os_memblock_get(&btshell_svc_pool);
if (svc == NULL) {
- BTSHELL_LOG(DEBUG, "OOM WHILE DISCOVERING SERVICE\n");
+ MODLOG_DFLT(DEBUG, "OOM WHILE DISCOVERING SERVICE\n");
return NULL;
}
memset(svc, 0, sizeof *svc);
@@ -474,7 +472,7 @@ btshell_chr_add(uint16_t conn_handle, uint16_t svc_start_handle,
conn = btshell_conn_find(conn_handle);
if (conn == NULL) {
- BTSHELL_LOG(DEBUG, "RECEIVED SERVICE FOR UNKNOWN CONNECTION; "
+ MODLOG_DFLT(DEBUG, "RECEIVED SERVICE FOR UNKNOWN CONNECTION; "
"HANDLE=%d\n",
conn_handle);
return NULL;
@@ -482,7 +480,7 @@ btshell_chr_add(uint16_t conn_handle, uint16_t svc_start_handle,
svc = btshell_svc_find(conn, svc_start_handle, NULL);
if (svc == NULL) {
- BTSHELL_LOG(DEBUG, "CAN'T FIND SERVICE FOR DISCOVERED CHR; HANDLE=%d\n",
+ MODLOG_DFLT(DEBUG, "CAN'T FIND SERVICE FOR DISCOVERED CHR; HANDLE=%d\n",
conn_handle);
return NULL;
}
@@ -495,7 +493,7 @@ btshell_chr_add(uint16_t conn_handle, uint16_t svc_start_handle,
chr = os_memblock_get(&btshell_chr_pool);
if (chr == NULL) {
- BTSHELL_LOG(DEBUG, "OOM WHILE DISCOVERING CHARACTERISTIC\n");
+ MODLOG_DFLT(DEBUG, "OOM WHILE DISCOVERING CHARACTERISTIC\n");
return NULL;
}
memset(chr, 0, sizeof *chr);
@@ -565,7 +563,7 @@ btshell_dsc_add(uint16_t conn_handle, uint16_t chr_val_handle,
conn = btshell_conn_find(conn_handle);
if (conn == NULL) {
- BTSHELL_LOG(DEBUG, "RECEIVED SERVICE FOR UNKNOWN CONNECTION; "
+ MODLOG_DFLT(DEBUG, "RECEIVED SERVICE FOR UNKNOWN CONNECTION; "
"HANDLE=%d\n",
conn_handle);
return NULL;
@@ -573,14 +571,14 @@ btshell_dsc_add(uint16_t conn_handle, uint16_t chr_val_handle,
svc = btshell_svc_find_range(conn, chr_val_handle);
if (svc == NULL) {
- BTSHELL_LOG(DEBUG, "CAN'T FIND SERVICE FOR DISCOVERED DSC; HANDLE=%d\n",
+ MODLOG_DFLT(DEBUG, "CAN'T FIND SERVICE FOR DISCOVERED DSC; HANDLE=%d\n",
conn_handle);
return NULL;
}
chr = btshell_chr_find(svc, chr_val_handle, NULL);
if (chr == NULL) {
- BTSHELL_LOG(DEBUG, "CAN'T FIND CHARACTERISTIC FOR DISCOVERED DSC; "
+ MODLOG_DFLT(DEBUG, "CAN'T FIND CHARACTERISTIC FOR DISCOVERED DSC; "
"HANDLE=%d\n",
conn_handle);
return NULL;
@@ -689,7 +687,7 @@ btshell_disc_full_dscs(uint16_t conn_handle)
conn = btshell_conn_find(conn_handle);
if (conn == NULL) {
- BTSHELL_LOG(DEBUG, "Failed to discover descriptors for conn=%d; "
+ MODLOG_DFLT(DEBUG, "Failed to discover descriptors for conn=%d; "
"not connected\n", conn_handle);
btshell_full_disc_complete(BLE_HS_ENOTCONN);
return;
@@ -727,7 +725,7 @@ btshell_disc_full_chrs(uint16_t conn_handle)
conn = btshell_conn_find(conn_handle);
if (conn == NULL) {
- BTSHELL_LOG(DEBUG, "Failed to discover characteristics for conn=%d; "
+ MODLOG_DFLT(DEBUG, "Failed to discover characteristics for conn=%d; "
"not connected\n", conn_handle);
btshell_full_disc_complete(BLE_HS_ENOTCONN);
return;
@@ -2080,13 +2078,7 @@ main(int argc, char **argv)
assert(rc == 0);
#endif
- /* Initialize the logging system. */
- log_register("btshell", &btshell_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = btshell_on_reset;
ble_hs_cfg.gatts_register_cb = gatt_svr_register_cb;
ble_hs_cfg.store_status_cb = ble_store_util_status_rr;
diff --git a/apps/ffs2native/pkg.yml b/apps/ffs2native/pkg.yml
index 4af4e70ecc..3345cdce01 100644
--- a/apps/ffs2native/pkg.yml
+++ b/apps/ffs2native/pkg.yml
@@ -25,9 +25,9 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - fs/nffs
- - hw/hal
- - sys/console/full
- - sys/log/full
- - sys/stats/stub
- - kernel/os
+ - "@apache-mynewt-core/fs/nffs"
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/stats/stub"
+ - "@apache-mynewt-core/kernel/os"
diff --git a/apps/iptest/pkg.yml b/apps/iptest/pkg.yml
index 529ef4e717..311887f313 100644
--- a/apps/iptest/pkg.yml
+++ b/apps/iptest/pkg.yml
@@ -25,22 +25,22 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - boot/bootutil
- - sys/shell
- - sys/config
- - sys/console/full
- - sys/id
- - sys/log/full
- - sys/stats/full
- - net/ip/inet_def_service
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/id"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/net/ip/inet_def_service"
pkg.deps.CONFIG_NFFS:
- - fs/nffs
+ - "@apache-mynewt-core/fs/nffs"
pkg.deps.CONFIG_FCB:
- - fs/fcb
+ - "@apache-mynewt-core/fs/fcb"
pkg.deps.BUILD_WITH_OIC:
- - net/oic
- - encoding/cborattr
+ - "@apache-mynewt-core/net/oic"
+ - "@apache-mynewt-core/encoding/cborattr"
diff --git a/apps/iptest/src/main.c b/apps/iptest/src/main.c
index 3210b496ef..f56fe5e28b 100644
--- a/apps/iptest/src/main.c
+++ b/apps/iptest/src/main.c
@@ -24,7 +24,6 @@
#include <hal/hal_flash.h>
#include <console/console.h>
-#include <log/log.h>
#include <config/config.h>
#include <hal/hal_system.h>
@@ -41,7 +40,6 @@
#if MYNEWT_VAL(BUILD_WITH_OIC)
#include <oic/oc_api.h>
-#include <oic/oc_log.h>
#include <cborattr/cborattr.h>
#endif
@@ -49,13 +47,6 @@
#include <mcu/mcu_sim.h>
#endif
-static struct log my_log;
-
-#define MAX_CBMEM_BUF 2048
-
-static uint32_t cbmem_buf[MAX_CBMEM_BUF];
-static struct cbmem cbmem;
-
static int net_cli(int argc, char **argv);
struct shell_cmd net_test_cmd = {
.sc_cmd = "net",
@@ -421,9 +412,6 @@ main(int argc, char **argv)
console_printf("iptest\n");
- cbmem_init(&cbmem, cbmem_buf, MAX_CBMEM_BUF);
- log_register("log", &my_log, &log_cbmem_handler, &cbmem, LOG_SYSLEVEL);
-
shell_cmd_register(&net_test_cmd);
/*
diff --git a/apps/lora_app_shell/pkg.yml b/apps/lora_app_shell/pkg.yml
index 749e706d16..0bed1ebc06 100644
--- a/apps/lora_app_shell/pkg.yml
+++ b/apps/lora_app_shell/pkg.yml
@@ -32,5 +32,5 @@ pkg.deps:
- "@apache-mynewt-core/sys/shell"
- "@apache-mynewt-core/sys/stats/full"
- "@apache-mynewt-core/util/parse"
- - "mgmt/oicmgr"
- - "mgmt/newtmgr/nmgr_os"
+ - "@apache-mynewt-core/mgmt/oicmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/nmgr_os"
diff --git a/apps/loraping/pkg.yml b/apps/loraping/pkg.yml
index 972cafa2a5..bc6f0634c5 100644
--- a/apps/loraping/pkg.yml
+++ b/apps/loraping/pkg.yml
@@ -40,7 +40,7 @@ pkg.deps:
- "@apache-mynewt-core/test/flash_test"
pkg.deps.CONFIG_NFFS:
- - fs/nffs
+ - "@apache-mynewt-core/fs/nffs"
pkg.deps.CONFIG_FCB:
- - fs/fcb
+ - "@apache-mynewt-core/fs/fcb"
diff --git a/apps/ocf_sample/pkg.yml b/apps/ocf_sample/pkg.yml
index f43e7afde9..e8882052a7 100644
--- a/apps/ocf_sample/pkg.yml
+++ b/apps/ocf_sample/pkg.yml
@@ -25,18 +25,19 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - net/oic
- - encoding/cborattr
- - sys/console/full
- - sys/log/full
- - sys/stats/full
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/net/oic"
+ - "@apache-mynewt-core/encoding/cborattr"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
pkg.deps.OC_TRANSPORT_SERIAL:
- - sys/shell
+ - "@apache-mynewt-core/sys/shell"
pkg.deps.OC_TRANSPORT_GATT:
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
diff --git a/apps/ocf_sample/src/ocf_ble.c b/apps/ocf_sample/src/ocf_ble.c
index 1a4ed9c955..2e6b23b1e0 100644
--- a/apps/ocf_sample/src/ocf_ble.c
+++ b/apps/ocf_sample/src/ocf_ble.c
@@ -24,7 +24,7 @@
#include <assert.h>
#include <string.h>
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "oic/oc_gatt.h"
@@ -33,15 +33,6 @@
#include "host/ble_hs.h"
#include "services/gap/ble_svc_gap.h"
-struct log ocf_ble_log;
-
-/* ocf_ble uses the first "peruser" log module. */
-#define OCF_BLE_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the ocf_ble module. */
-#define OCF_BLE_LOG(lvl, ...) \
- LOG_ ## lvl(&ocf_ble_log, OCF_BLE_LOG_MODULE, __VA_ARGS__)
-
static int ocf_ble_gap_event(struct ble_gap_event *event, void *arg);
/**
@@ -53,7 +44,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- OCF_BLE_LOG(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -63,7 +54,7 @@ print_addr(const void *addr)
const uint8_t *u8p;
u8p = addr;
- OCF_BLE_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
@@ -73,20 +64,20 @@ print_addr(const void *addr)
static void
ocf_ble_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- OCF_BLE_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
print_addr(desc->our_ota_addr.val);
- OCF_BLE_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
print_addr(desc->our_id_addr.val);
- OCF_BLE_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
print_addr(desc->peer_ota_addr.val);
- OCF_BLE_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
print_addr(desc->peer_id_addr.val);
- OCF_BLE_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
- "encrypted=%d authenticated=%d bonded=%d\n",
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ "encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
desc->sec_state.encrypted,
@@ -137,7 +128,7 @@ ocf_ble_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- OCF_BLE_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -148,7 +139,7 @@ ocf_ble_advertise(void)
rc = ble_gap_adv_start(BLE_OWN_ADDR_PUBLIC, NULL, BLE_HS_FOREVER,
&adv_params, ocf_ble_gap_event, NULL);
if (rc != 0) {
- OCF_BLE_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -184,15 +175,15 @@ ocf_ble_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- OCF_BLE_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
ocf_ble_print_conn_desc(&desc);
}
- OCF_BLE_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -201,9 +192,9 @@ ocf_ble_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISCONNECT:
- OCF_BLE_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
ocf_ble_print_conn_desc(&event->disconnect.conn);
- OCF_BLE_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Connection terminated; resume advertising. */
ocf_ble_advertise();
@@ -211,32 +202,32 @@ ocf_ble_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- OCF_BLE_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
ocf_ble_print_conn_desc(&desc);
- OCF_BLE_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_ADV_COMPLETE:
- OCF_BLE_LOG(INFO, "advertise complete; reason=%d\n",
+ MODLOG_DFLT(INFO, "advertise complete; reason=%d\n",
event->adv_complete.reason);
ocf_ble_advertise();
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- OCF_BLE_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
ocf_ble_print_conn_desc(&desc);
- OCF_BLE_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- OCF_BLE_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -248,7 +239,7 @@ ocf_ble_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- OCF_BLE_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -263,16 +254,9 @@ static const uint8_t ocf_ble_addr[6] = {1,2,3,4,5,6};
void
ocf_ble_init(void)
{
- /* Initialize the ocf_ble log. */
- log_register("ocf_ble", &ocf_ble_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
memcpy(g_dev_addr, ocf_ble_addr, sizeof(g_dev_addr));
/* Initialize the BLE host. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
ble_hs_cfg.sync_cb = ocf_ble_on_sync;
}
diff --git a/apps/pwm_test/pkg.yml b/apps/pwm_test/pkg.yml
index 44d6f32efb..a5e73f30b9 100644
--- a/apps/pwm_test/pkg.yml
+++ b/apps/pwm_test/pkg.yml
@@ -25,7 +25,7 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - sys/console/full
- - hw/drivers/pwm
- - util/easing
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/hw/drivers/pwm"
+ - "@apache-mynewt-core/util/easing"
diff --git a/apps/sensors_test/pkg.yml b/apps/sensors_test/pkg.yml
index d4815200f7..ebc8028125 100644
--- a/apps/sensors_test/pkg.yml
+++ b/apps/sensors_test/pkg.yml
@@ -25,33 +25,34 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - hw/sensor
- - boot/bootutil
- - sys/console/full
- - sys/log/full
- - sys/stats/full
- - hw/sensor/creator
- - sys/reboot
- - mgmt/newtmgr/transport/ble
- - sys/id
- - mgmt/imgmgr
- - test/flash_test
- - test/i2c_scan
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/hw/sensor/creator"
+ - "@apache-mynewt-core/sys/reboot"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/ble"
+ - "@apache-mynewt-core/sys/id"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/test/flash_test"
+ - "@apache-mynewt-core/test/i2c_scan"
pkg.deps.SENSOR_OIC:
#- mgmt/oicmgr
pkg.deps.SENSOR_BLE:
- - net/nimble/controller
- - net/nimble/host
- - net/nimble/host/services/gap
- - net/nimble/host/services/gatt
- - net/nimble/host/store/ram
- - net/nimble/transport/ram
+ - "@apache-mynewt-core/net/nimble/controller"
+ - "@apache-mynewt-core/net/nimble/host"
+ - "@apache-mynewt-core/net/nimble/host/services/gap"
+ - "@apache-mynewt-core/net/nimble/host/services/gatt"
+ - "@apache-mynewt-core/net/nimble/host/store/ram"
+ - "@apache-mynewt-core/net/nimble/transport/ram"
pkg.deps.CONFIG_NFFS:
- - fs/nffs
+ - "@apache-mynewt-core/fs/nffs"
pkg.deps.CONFIG_FCB:
- - fs/fcb
+ - "@apache-mynewt-core/fs/fcb"
diff --git a/apps/sensors_test/src/bleprph.h b/apps/sensors_test/src/bleprph.h
index 2e3f024737..cacca932df 100644
--- a/apps/sensors_test/src/bleprph.h
+++ b/apps/sensors_test/src/bleprph.h
@@ -20,7 +20,7 @@
#ifndef H_BLEPRPH_
#define H_BLEPRPH_
-#include "log/log.h"
+#include "modlog/modlog.h"
#ifdef __cplusplus
extern "C" {
#endif
@@ -28,15 +28,6 @@ extern "C" {
struct ble_hs_cfg;
struct ble_gatt_register_ctxt;
-extern struct log bleprph_log;
-
-/* bleprph uses the first "peruser" log module. */
-#define BLEPRPH_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the bleprph module. */
-#define BLEPRPH_LOG(lvl, ...) \
- LOG_ ## lvl(&bleprph_log, BLEPRPH_LOG_MODULE, __VA_ARGS__)
-
/** GATT server. */
#define GATT_SVR_SVC_ALERT_UUID 0x1811
#define GATT_SVR_CHR_SUP_NEW_ALERT_CAT_UUID 0x2A47
diff --git a/apps/sensors_test/src/gatt_svr.c b/apps/sensors_test/src/gatt_svr.c
index db6e61b0be..130e4df59a 100644
--- a/apps/sensors_test/src/gatt_svr.c
+++ b/apps/sensors_test/src/gatt_svr.c
@@ -35,13 +35,13 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
switch (ctxt->op) {
case BLE_GATT_REGISTER_OP_SVC:
- BLEPRPH_LOG(DEBUG, "registered service %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registered service %s with handle=%d\n",
ble_uuid_to_str(ctxt->svc.svc_def->uuid, buf),
ctxt->svc.handle);
break;
case BLE_GATT_REGISTER_OP_CHR:
- BLEPRPH_LOG(DEBUG, "registering characteristic %s with "
+ MODLOG_DFLT(DEBUG, "registering characteristic %s with "
"def_handle=%d val_handle=%d\n",
ble_uuid_to_str(ctxt->chr.chr_def->uuid, buf),
ctxt->chr.def_handle,
@@ -49,7 +49,7 @@ gatt_svr_register_cb(struct ble_gatt_register_ctxt *ctxt, void *arg)
break;
case BLE_GATT_REGISTER_OP_DSC:
- BLEPRPH_LOG(DEBUG, "registering descriptor %s with handle=%d\n",
+ MODLOG_DFLT(DEBUG, "registering descriptor %s with handle=%d\n",
ble_uuid_to_str(ctxt->dsc.dsc_def->uuid, buf),
ctxt->dsc.handle);
break;
diff --git a/apps/sensors_test/src/main.c b/apps/sensors_test/src/main.c
index 1080c75e06..7783d7472d 100644
--- a/apps/sensors_test/src/main.c
+++ b/apps/sensors_test/src/main.c
@@ -91,9 +91,6 @@ static const oc_handler_t sensor_oic_handler = {
static int sensor_oic_gap_event(struct ble_gap_event *event, void *arg);
#endif
-/** Log data. */
-struct log bleprph_log;
-
#endif
#ifdef ARCH_sim
@@ -127,20 +124,20 @@ static int g_led_pin;
static void
sensor_oic_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- BLEPRPH_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
print_addr(desc->our_ota_addr.val);
- BLEPRPH_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
print_addr(desc->our_id_addr.val);
- BLEPRPH_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
print_addr(desc->peer_ota_addr.val);
- BLEPRPH_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
print_addr(desc->peer_id_addr.val);
- BLEPRPH_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
- "encrypted=%d authenticated=%d bonded=%d\n",
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ "encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
desc->sec_state.encrypted,
@@ -200,7 +197,7 @@ sensor_oic_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -211,7 +208,7 @@ sensor_oic_advertise(void)
rc = ble_gap_adv_start(BLE_OWN_ADDR_PUBLIC, NULL, BLE_HS_FOREVER,
&adv_params, sensor_oic_gap_event, NULL);
if (rc != 0) {
- BLEPRPH_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -220,7 +217,7 @@ sensor_oic_advertise(void)
static void
sensor_oic_on_reset(int reason)
{
- BLEPRPH_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -254,15 +251,15 @@ sensor_oic_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- BLEPRPH_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
sensor_oic_print_conn_desc(&desc);
}
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -273,9 +270,9 @@ sensor_oic_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISCONNECT:
- BLEPRPH_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
sensor_oic_print_conn_desc(&event->disconnect.conn);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
oc_ble_coap_conn_del(event->disconnect.conn.conn_handle);
@@ -285,38 +282,38 @@ sensor_oic_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- BLEPRPH_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
sensor_oic_print_conn_desc(&desc);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_DISC_COMPLETE:
- BLEPRPH_LOG(INFO, "discovery complete; reason=%d\n",
+ MODLOG_DFLT(INFO, "discovery complete; reason=%d\n",
event->disc_complete.reason);
return 0;
case BLE_GAP_EVENT_ADV_COMPLETE:
- BLEPRPH_LOG(INFO, "advertise complete; reason=%d\n",
+ MODLOG_DFLT(INFO, "advertise complete; reason=%d\n",
event->adv_complete.reason);
sensor_oic_advertise();
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- BLEPRPH_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
sensor_oic_print_conn_desc(&desc);
- BLEPRPH_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- BLEPRPH_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -328,7 +325,7 @@ sensor_oic_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- BLEPRPH_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -487,25 +484,6 @@ sensor_ble_oic_server_init(void)
#endif
}
-static void
-ble_oic_log_init(void)
-{
-#if MYNEWT_VAL(SENSOR_BLE)
- /* Initialize the bleprph log. */
- log_register("bleprph", &bleprph_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
- /* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-#endif
-
-#if MYNEWT_VAL(SENSOR_OIC)
- /* Initialize the OIC */
- log_register("oic", &oc_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-#endif
-}
-
/**
* main
*
@@ -525,9 +503,6 @@ main(int argc, char **argv)
/* Initialize OS */
sysinit();
- /* Initialize BLE and OIC logs */
- ble_oic_log_init();
-
/* Initialize tasks */
init_tasks();
diff --git a/apps/sensors_test/src/misc.c b/apps/sensors_test/src/misc.c
index 8ec785e511..6ed205ec84 100644
--- a/apps/sensors_test/src/misc.c
+++ b/apps/sensors_test/src/misc.c
@@ -28,7 +28,7 @@ print_bytes(const uint8_t *bytes, int len)
int i;
for (i = 0; i < len; i++) {
- BLEPRPH_LOG(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
+ MODLOG_DFLT(INFO, "%s0x%02x", i != 0 ? ":" : "", bytes[i]);
}
}
@@ -38,6 +38,6 @@ print_addr(const void *addr)
const uint8_t *u8p;
u8p = addr;
- BLEPRPH_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
- u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
diff --git a/apps/slinky/pkg.yml b/apps/slinky/pkg.yml
index 4e4c7d8914..ee25b7b101 100644
--- a/apps/slinky/pkg.yml
+++ b/apps/slinky/pkg.yml
@@ -25,26 +25,27 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - test/flash_test
- - mgmt/imgmgr
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/nmgr_shell
- - kernel/os
- - boot/bootutil
- - sys/shell
- - sys/config
- - sys/console/full
- - sys/id
- - sys/log/full
- - sys/stats/full
- - boot/split
+ - "@apache-mynewt-core/test/flash_test"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/nmgr_shell"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/id"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/boot/split"
pkg.deps.I2C_0: test/i2c_scan
pkg.deps.I2C_1: test/i2c_scan
pkg.deps.I2C_2: test/i2c_scan
pkg.deps.CONFIG_NFFS:
- - fs/nffs
+ - "@apache-mynewt-core/fs/nffs"
pkg.deps.CONFIG_FCB:
- - fs/fcb
+ - "@apache-mynewt-core/fs/fcb"
diff --git a/apps/slinky/src/main.c b/apps/slinky/src/main.c
index a33cafc560..3cf9716ca2 100644
--- a/apps/slinky/src/main.c
+++ b/apps/slinky/src/main.c
@@ -39,6 +39,7 @@
#include <string.h>
#include <reboot/log_reboot.h>
#include <id/id.h>
+#include "modlog/modlog.h"
#ifdef ARCH_sim
#include <mcu/mcu_sim.h>
@@ -172,8 +173,8 @@ task1_handler(void *arg)
/* Toggle the LED */
prev_pin_state = hal_gpio_read(g_led_pin);
curr_pin_state = hal_gpio_toggle(g_led_pin);
- LOG_INFO(&my_log, LOG_MODULE_DEFAULT, "GPIO toggle from %u to %u",
- prev_pin_state, curr_pin_state);
+ MODLOG_DFLT(INFO, "GPIO toggle from %u to %u",
+ prev_pin_state, curr_pin_state);
STATS_INC(g_stats_gpio_toggle, toggles);
/* Release semaphore to task 2 */
@@ -254,6 +255,10 @@ main(int argc, char **argv)
cbmem_init(&cbmem, cbmem_buf, MAX_CBMEM_BUF);
log_register("log", &my_log, &log_cbmem_handler, &cbmem, LOG_SYSLEVEL);
+ /* Point the default module at the cbmem log just registered. */
+ rc = modlog_register(LOG_MODULE_DEFAULT, &my_log, LOG_LEVEL_DEBUG, NULL);
+ assert(rc == 0);
+
stats_init(STATS_HDR(g_stats_gpio_toggle),
STATS_SIZE_INIT_PARMS(g_stats_gpio_toggle, STATS_SIZE_32),
STATS_NAME_INIT_PARMS(gpio_stats));
diff --git a/apps/slinky/syscfg.yml b/apps/slinky/syscfg.yml
index 7438a81790..5661efee41 100644
--- a/apps/slinky/syscfg.yml
+++ b/apps/slinky/syscfg.yml
@@ -17,6 +17,10 @@
#
# Package: apps/slinky
+syscfg.defs:
+ SLINKY_LOG_MODULE_GPIO:
+ description: The log module to use for slinky GPIO messages.
+ value: 64
syscfg.vals:
# Enable the shell task.
diff --git a/apps/slinky_oic/pkg.yml b/apps/slinky_oic/pkg.yml
index 74364c4fd2..7442e6900d 100644
--- a/apps/slinky_oic/pkg.yml
+++ b/apps/slinky_oic/pkg.yml
@@ -25,20 +25,21 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - mgmt/imgmgr
- - mgmt/oicmgr
- - kernel/os
- - boot/bootutil
- - sys/shell
- - sys/config
- - sys/console/full
- - sys/id
- - sys/log/full
- - sys/stats/full
- - boot/split
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/oicmgr"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/id"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/stats/full"
+ - "@apache-mynewt-core/boot/split"
pkg.deps.CONFIG_NFFS:
- - fs/nffs
+ - "@apache-mynewt-core/fs/nffs"
pkg.deps.CONFIG_FCB:
- - fs/fcb
+ - "@apache-mynewt-core/fs/fcb"
diff --git a/apps/slinky_oic/src/main.c b/apps/slinky_oic/src/main.c
index c5854a1569..25d621429f 100644
--- a/apps/slinky_oic/src/main.c
+++ b/apps/slinky_oic/src/main.c
@@ -168,8 +168,8 @@ task1_handler(void *arg)
/* Toggle the LED */
prev_pin_state = hal_gpio_read(g_led_pin);
curr_pin_state = hal_gpio_toggle(g_led_pin);
- LOG_INFO(&my_log, LOG_MODULE_DEFAULT, "GPIO toggle from %u to %u",
- prev_pin_state, curr_pin_state);
+ MODLOG_DFLT(INFO, "GPIO toggle from %u to %u",
+ prev_pin_state, curr_pin_state);
STATS_INC(g_stats_gpio_toggle, toggles);
/* Release semaphore to task 2 */
@@ -268,8 +268,9 @@ main(int argc, char **argv)
cbmem_init(&cbmem, cbmem_buf, MAX_CBMEM_BUF);
log_register("log", &my_log, &log_cbmem_handler, &cbmem, LOG_SYSLEVEL);
- /* Initialize the OIC */
- log_register("oic", &oc_log, &log_console_handler, NULL, LOG_SYSLEVEL);
+ /* Point the default module at the cbmem log just registered. */
+ rc = modlog_register(LOG_MODULE_DEFAULT, &my_log, LOG_LEVEL_DEBUG, NULL);
+ assert(rc == 0);
stats_init(STATS_HDR(g_stats_gpio_toggle),
STATS_SIZE_INIT_PARMS(g_stats_gpio_toggle, STATS_SIZE_32),
diff --git a/apps/spitest/pkg.yml b/apps/spitest/pkg.yml
index f7bca85d25..a59f5cc894 100644
--- a/apps/spitest/pkg.yml
+++ b/apps/spitest/pkg.yml
@@ -25,9 +25,9 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - sys/console/full
- - kernel/os
- - sys/shell
- - sys/config
- - sys/log/full
- - sys/stats/full
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/stats/full"
diff --git a/apps/splitty/pkg.yml b/apps/splitty/pkg.yml
index 68e4e1e71c..06602f29c2 100644
--- a/apps/splitty/pkg.yml
+++ b/apps/splitty/pkg.yml
@@ -25,16 +25,17 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - boot/split
- - boot/split_app
- - kernel/os
- - mgmt/imgmgr
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/nmgr_shell
- - sys/config
- - sys/console/full
- - sys/id
- - sys/log/full
- - sys/shell
- - sys/stats/full
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/boot/split"
+ - "@apache-mynewt-core/boot/split_app"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/nmgr_shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/sys/id"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/stats/full"
diff --git a/apps/splitty/src/main.c b/apps/splitty/src/main.c
index 674787b613..04eab297e4 100644
--- a/apps/splitty/src/main.c
+++ b/apps/splitty/src/main.c
@@ -25,7 +25,7 @@
#include <hal/hal_flash.h>
#include <console/console.h>
#include <shell/shell.h>
-#include <log/log.h>
+#include <modlog/modlog.h>
#include <stats/stats.h>
#include <config/config.h>
#include <flash_map/flash_map.h>
@@ -107,8 +107,8 @@ task1_handler(void *arg)
/* Toggle the LED */
prev_pin_state = hal_gpio_read(g_led_pin);
curr_pin_state = hal_gpio_toggle(g_led_pin);
- LOG_INFO(&my_log, LOG_MODULE_DEFAULT, "GPIO toggle from %u to %u",
- prev_pin_state, curr_pin_state);
+ MODLOG_INFO(LOG_MODULE_DEFAULT, "GPIO toggle from %u to %u",
+ prev_pin_state, curr_pin_state);
STATS_INC(g_stats_gpio_toggle, toggles);
/* Release semaphore to task 2 */
@@ -187,6 +187,9 @@ main(int argc, char **argv)
cbmem_init(&cbmem, cbmem_buf, MAX_CBMEM_BUF);
log_register("log", &my_log, &log_cbmem_handler, &cbmem, LOG_SYSLEVEL);
+ rc = modlog_register(LOG_MODULE_DEFAULT, &my_log, LOG_LEVEL_DEBUG, NULL);
+ assert(rc == 0);
+
stats_init(STATS_HDR(g_stats_gpio_toggle),
STATS_SIZE_INIT_PARMS(g_stats_gpio_toggle, STATS_SIZE_32),
STATS_NAME_INIT_PARMS(gpio_stats));
diff --git a/apps/splitty/syscfg.yml b/apps/splitty/syscfg.yml
index 7ff1dfb6a6..cd2ece79be 100644
--- a/apps/splitty/syscfg.yml
+++ b/apps/splitty/syscfg.yml
@@ -26,4 +26,5 @@ syscfg.vals:
STATS_NAMES: 1
# Log reboot messages to a flash circular buffer.
+ LOG_FCB: 1
REBOOT_LOG_FCB: 1
diff --git a/apps/testbench/pkg.yml b/apps/testbench/pkg.yml
index db39cde2e8..9810c42745 100644
--- a/apps/testbench/pkg.yml
+++ b/apps/testbench/pkg.yml
@@ -38,6 +38,7 @@ pkg.deps:
- "@apache-mynewt-core/sys/flash_map/test"
- "@apache-mynewt-core/sys/id"
- "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/log/modlog"
- "@apache-mynewt-core/sys/stats/full"
- "@apache-mynewt-core/test/crash_test"
- "@apache-mynewt-core/test/runtest"
diff --git a/apps/testbench/src/tbb.c b/apps/testbench/src/tbb.c
index aa3279c1af..a0633aadef 100644
--- a/apps/testbench/src/tbb.c
+++ b/apps/testbench/src/tbb.c
@@ -34,6 +34,7 @@
#include "hal/hal_system.h"
#include "config/config.h"
#include "split/split.h"
+#include "modlog/modlog.h"
/* BLE */
#include "nimble/ble.h"
@@ -46,23 +47,14 @@
static int tbb_gap_event(struct ble_gap_event *event, void *arg);
-static struct log tbb_log;
-
-/* tbb uses the first "peruser" log module. */
-#define TBB_LOG_MODULE (LOG_MODULE_PERUSER + 0)
-
-/* Convenience macro for logging to the tbb module. */
-#define TBB_LOG(lvl, ...) \
- LOG_ ## lvl(&tbb_log, TBB_LOG_MODULE, __VA_ARGS__)
-
void
tbb_print_addr(const void *addr)
{
const uint8_t *u8p;
u8p = addr;
- TBB_LOG(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
- u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
+ MODLOG_DFLT(INFO, "%02x:%02x:%02x:%02x:%02x:%02x",
+ u8p[5], u8p[4], u8p[3], u8p[2], u8p[1], u8p[0]);
}
/**
@@ -71,20 +63,20 @@ tbb_print_addr(const void *addr)
static void
tbb_print_conn_desc(struct ble_gap_conn_desc *desc)
{
- TBB_LOG(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
+ MODLOG_DFLT(INFO, "handle=%d our_ota_addr_type=%d our_ota_addr=",
desc->conn_handle, desc->our_ota_addr.type);
tbb_print_addr(desc->our_ota_addr.val);
- TBB_LOG(INFO, " our_id_addr_type=%d our_id_addr=",
+ MODLOG_DFLT(INFO, " our_id_addr_type=%d our_id_addr=",
desc->our_id_addr.type);
tbb_print_addr(desc->our_id_addr.val);
- TBB_LOG(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
+ MODLOG_DFLT(INFO, " peer_ota_addr_type=%d peer_ota_addr=",
desc->peer_ota_addr.type);
tbb_print_addr(desc->peer_ota_addr.val);
- TBB_LOG(INFO, " peer_id_addr_type=%d peer_id_addr=",
+ MODLOG_DFLT(INFO, " peer_id_addr_type=%d peer_id_addr=",
desc->peer_id_addr.type);
tbb_print_addr(desc->peer_id_addr.val);
- TBB_LOG(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
- "encrypted=%d authenticated=%d bonded=%d\n",
+ MODLOG_DFLT(INFO, " conn_itvl=%d conn_latency=%d supervision_timeout=%d "
+ "encrypted=%d authenticated=%d bonded=%d\n",
desc->conn_itvl, desc->conn_latency,
desc->supervision_timeout,
desc->sec_state.encrypted,
@@ -142,7 +134,7 @@ tbb_advertise(void)
rc = ble_gap_adv_set_fields(&fields);
if (rc != 0) {
- TBB_LOG(ERROR, "error setting advertisement data; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error setting advertisement data; rc=%d\n", rc);
return;
}
@@ -153,7 +145,7 @@ tbb_advertise(void)
rc = ble_gap_adv_start(BLE_OWN_ADDR_PUBLIC, NULL, BLE_HS_FOREVER,
&adv_params, tbb_gap_event, NULL);
if (rc != 0) {
- TBB_LOG(ERROR, "error enabling advertisement; rc=%d\n", rc);
+ MODLOG_DFLT(ERROR, "error enabling advertisement; rc=%d\n", rc);
return;
}
}
@@ -182,15 +174,15 @@ tbb_gap_event(struct ble_gap_event *event, void *arg)
switch (event->type) {
case BLE_GAP_EVENT_CONNECT:
/* A new connection was established or a connection attempt failed. */
- TBB_LOG(INFO, "connection %s; status=%d ",
- event->connect.status == 0 ? "established" : "failed",
- event->connect.status);
+ MODLOG_DFLT(INFO, "connection %s; status=%d ",
+ event->connect.status == 0 ? "established" : "failed",
+ event->connect.status);
if (event->connect.status == 0) {
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
tbb_print_conn_desc(&desc);
}
- TBB_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
if (event->connect.status != 0) {
/* Connection failed; resume advertising. */
@@ -199,9 +191,9 @@ tbb_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_DISCONNECT:
- TBB_LOG(INFO, "disconnect; reason=%d ", event->disconnect.reason);
+ MODLOG_DFLT(INFO, "disconnect; reason=%d ", event->disconnect.reason);
tbb_print_conn_desc(&event->disconnect.conn);
- TBB_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
/* Connection terminated; resume advertising. */
tbb_advertise();
@@ -209,32 +201,32 @@ tbb_gap_event(struct ble_gap_event *event, void *arg)
case BLE_GAP_EVENT_CONN_UPDATE:
/* The central has updated the connection parameters. */
- TBB_LOG(INFO, "connection updated; status=%d ",
+ MODLOG_DFLT(INFO, "connection updated; status=%d ",
event->conn_update.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
tbb_print_conn_desc(&desc);
- TBB_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_ADV_COMPLETE:
- TBB_LOG(INFO, "advertise complete; reason=%d\n",
- event->adv_complete.reason);
+ MODLOG_DFLT(INFO, "advertise complete; reason=%d\n",
+ event->adv_complete.reason);
tbb_advertise();
return 0;
case BLE_GAP_EVENT_ENC_CHANGE:
/* Encryption has been enabled or disabled for this connection. */
- TBB_LOG(INFO, "encryption change event; status=%d ",
+ MODLOG_DFLT(INFO, "encryption change event; status=%d ",
event->enc_change.status);
rc = ble_gap_conn_find(event->connect.conn_handle, &desc);
assert(rc == 0);
tbb_print_conn_desc(&desc);
- TBB_LOG(INFO, "\n");
+ MODLOG_DFLT(INFO, "\n");
return 0;
case BLE_GAP_EVENT_SUBSCRIBE:
- TBB_LOG(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
+ MODLOG_DFLT(INFO, "subscribe event; conn_handle=%d attr_handle=%d "
"reason=%d prevn=%d curn=%d previ=%d curi=%d\n",
event->subscribe.conn_handle,
event->subscribe.attr_handle,
@@ -246,7 +238,7 @@ tbb_gap_event(struct ble_gap_event *event, void *arg)
return 0;
case BLE_GAP_EVENT_MTU:
- TBB_LOG(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
+ MODLOG_DFLT(INFO, "mtu update event; conn_handle=%d cid=%d mtu=%d\n",
event->mtu.conn_handle,
event->mtu.channel_id,
event->mtu.value);
@@ -259,7 +251,7 @@ tbb_gap_event(struct ble_gap_event *event, void *arg)
static void
tbb_on_reset(int reason)
{
- TBB_LOG(ERROR, "Resetting state; reason=%d\n", reason);
+ MODLOG_DFLT(ERROR, "Resetting state; reason=%d\n", reason);
}
static void
@@ -274,13 +266,7 @@ tbb_init(void)
{
int rc;
- /* Initialize the tbb log. */
- log_register("tbb", &tbb_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialize the NimBLE host configuration. */
- log_register("ble_hs", &ble_hs_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
ble_hs_cfg.reset_cb = tbb_on_reset;
ble_hs_cfg.sync_cb = tbb_on_sync;
diff --git a/apps/testbench/src/testbench.c b/apps/testbench/src/testbench.c
index 108301a0d7..895e61fa1a 100644
--- a/apps/testbench/src/testbench.c
+++ b/apps/testbench/src/testbench.c
@@ -26,6 +26,7 @@
#include <shell/shell.h>
#endif
#include <log/log.h>
+#include <modlog/modlog.h>
#include <stats/stats.h>
#include <config/config.h>
#include "flash_map/flash_map.h"
@@ -170,9 +171,10 @@ testbench_ts_result(char *msg, void *arg, bool passed)
total_fails++;
}
- LOG_INFO(&testlog, LOG_MODULE_TEST,
- "{\"k\":\"%s\",\"n\":\"%s\",\"s\":\"%s\",\"m\":\"%s\",\"r\":%d}",
- runtest_token, n, s, m, passed);
+ MODLOG_INFO(
+ LOG_MODULE_TEST,
+ "{\"k\":\"%s\",\"n\":\"%s\",\"s\":\"%s\",\"m\":\"%s\",\"r\":%d}",
+ runtest_token, n, s, m, passed);
}
void
@@ -260,16 +262,15 @@ testbench_runtests(struct os_event *ev)
static void
testbench_test_complete(void)
{
- LOG_INFO(&testlog, LOG_MODULE_TEST, "%s Done", runtest_token);
- LOG_INFO(&testlog, LOG_MODULE_TEST,
- "%s TESTBENCH TEST %s - Tests run:%d pass:%d fail:%d %s",
- buildID,
- (total_fails ? "FAILED" : "PASSED"),
- total_tests,
- (total_tests-total_fails),
- total_fails,
- runtest_token);
- return;
+ MODLOG_INFO(LOG_MODULE_TEST, "%s Done", runtest_token);
+ MODLOG_INFO(LOG_MODULE_TEST,
+ "%s TESTBENCH TEST %s - Tests run:%d pass:%d fail:%d %s",
+ buildID,
+ (total_fails ? "FAILED" : "PASSED"),
+ total_tests,
+ (total_tests-total_fails),
+ total_fails,
+ runtest_token);
}
/*
@@ -388,8 +389,10 @@ main(int argc, char **argv)
cbmem_init(&cbmem, cbmem_buf, MAX_CBMEM_BUF);
log_register("testlog", &testlog, &log_cbmem_handler, &cbmem, LOG_SYSLEVEL);
+ rc = modlog_register(LOG_MODULE_TEST, &testlog, LOG_LEVEL_DEBUG, NULL);
+ assert(rc == 0);
+
/* Initialize the OIC */
- log_register("oic", &oc_log, &log_console_handler, NULL, LOG_SYSLEVEL);
oc_main_init((oc_handler_t *)&omgr_oc_handler);
#if MYNEWT_VAL(TESTBENCH_BLE)
@@ -418,7 +421,7 @@ main(int argc, char **argv)
*/
run_evcb_set((os_event_fn*) testbench_runtests);
- LOG_INFO(&testlog, LOG_MODULE_TEST, "testbench app initialized");
+ MODLOG_INFO(LOG_MODULE_TEST, "testbench app initialized");
while (1) {
os_eventq_run(os_eventq_dflt_get());
diff --git a/apps/testbench/src/testbench.h b/apps/testbench/src/testbench.h
index 815c061d50..869725230a 100644
--- a/apps/testbench/src/testbench.h
+++ b/apps/testbench/src/testbench.h
@@ -63,7 +63,7 @@
#include "mbedtls/mbedtls_test.h"
#ifdef __cplusplus
-#extern "C" {
+extern "C" {
#endif
#ifndef IMGMGR_HASH_LEN
@@ -81,7 +81,6 @@ int g_led_pin;
*/
int testbench_nffs();
extern struct nffs_area_desc *nffs_current_area_descs;
-extern struct log nffs_log; /* defined in the OS module */
#endif
/*
diff --git a/apps/testbench/src/testbench_json.c b/apps/testbench/src/testbench_json.c
index b225b164e3..58fa7a5c91 100644
--- a/apps/testbench/src/testbench_json.c
+++ b/apps/testbench/src/testbench_json.c
@@ -19,6 +19,7 @@
#include <stdio.h>
#include <string.h>
#include "os/mynewt.h"
+#include "modlog/modlog.h"
#include "testutil/testutil.h"
#include "testbench.h"
@@ -31,12 +32,7 @@ extern char *bigbuf;
void
testbench_json_init(void *arg)
{
- /*
- * Lorem ipsum dolor sit amet, consectetur adipiscing elit,
- * sed do eiusmod tempor incididunt ut labore et dolore magna aliqua.
- */
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s testbench json_init", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench json_init", buildID);
bigbuf = os_malloc(JSON_BIGBUF_SIZE);
@@ -55,7 +51,7 @@ TEST_CASE_DECL(test_json_simple_decode);
TEST_SUITE(testbench_json_suite)
{
- LOG_DEBUG(&testlog, LOG_MODULE_TEST, "%s testbench_json", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench_json", buildID);
tu_suite_set_init_cb(testbench_json_init, NULL);
tu_suite_set_complete_cb(testbench_json_complete, NULL);
@@ -69,7 +65,7 @@ testbench_json()
{
tu_suite_set_init_cb(testbench_json_init, NULL);
tu_suite_set_complete_cb(testbench_json_complete, NULL);
- LOG_DEBUG(&testlog, LOG_MODULE_TEST, "%s testbench_json", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench_json", buildID);
testbench_json_suite();
return tu_any_failed;
diff --git a/apps/testbench/src/testbench_mempool.c b/apps/testbench/src/testbench_mempool.c
index 89a6cbe6d7..d44ecae250 100644
--- a/apps/testbench/src/testbench_mempool.c
+++ b/apps/testbench/src/testbench_mempool.c
@@ -16,9 +16,11 @@
* specific language governing permissions and limitations
* under the License.
*/
+
#include <stdio.h>
#include <string.h>
#include "os/mynewt.h"
+#include "modlog/modlog.h"
#include "testutil/testutil.h"
#include "testbench.h"
@@ -47,12 +49,7 @@ void *block_array[MEMPOOL_TEST_MAX_BLOCKS];
void
testbench_mempool_init(void *arg)
{
- /*
- * Lorem ipsum dolor sit amet, consectetur adipiscing elit,
- * sed do eiusmod tempor incididunt ut labore et dolore magna aliqua.
- */
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s testbench mempool_init", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench mempool_init", buildID);
TstMembufSz = (sizeof(os_membuf_t) *
OS_MEMPOOL_SIZE(NUM_MEM_BLOCKS, MEM_BLOCK_SIZE));
@@ -72,7 +69,7 @@ TEST_CASE_DECL(os_mempool_test_case)
TEST_SUITE(testbench_mempool_suite)
{
- LOG_DEBUG(&testlog, LOG_MODULE_TEST, "%s testbench_mempool", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench_mempool", buildID);
tu_suite_set_init_cb(testbench_mempool_init, NULL);
tu_suite_set_complete_cb(testbench_mempool_complete, NULL);
@@ -85,7 +82,7 @@ testbench_mempool()
{
tu_suite_set_init_cb(testbench_mempool_init, NULL);
tu_suite_set_complete_cb(testbench_mempool_complete, NULL);
- LOG_DEBUG(&testlog, LOG_MODULE_TEST, "%s testbench_mempool", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench_mempool", buildID);
testbench_mempool_suite();
return tu_any_failed;
diff --git a/apps/testbench/src/testbench_mutex.c b/apps/testbench/src/testbench_mutex.c
index 9343c38507..bbff8e3526 100644
--- a/apps/testbench/src/testbench_mutex.c
+++ b/apps/testbench/src/testbench_mutex.c
@@ -16,13 +16,14 @@
* specific language governing permissions and limitations
* under the License.
*/
+
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <sys/time.h>
#include "os/mynewt.h"
+#include "modlog/modlog.h"
#include "testutil/testutil.h"
-
#include "testbench.h"
#ifdef ARCH_sim
@@ -39,8 +40,7 @@ volatile int g_mutex_test;
void
testbench_mutex_ts_init(void *arg)
{
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s starting %s", buildID, tu_case_name);
+ MODLOG_DFLT(DEBUG, "%s starting %s", buildID, tu_case_name);
}
/*
@@ -112,8 +112,7 @@ testbench_mutex_init(void *arg)
tu_case_idx = 0;
tu_case_failed = 0;
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s testbench test_init", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench test_init", buildID);
tu_suite_set_pass_cb(testbench_ts_pass, NULL);
tu_suite_set_fail_cb(testbench_ts_fail, NULL);
@@ -127,8 +126,7 @@ TEST_SUITE(testbench_mutex_suite)
{
int taskcount;
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s mutex_suite start", buildID);
+ MODLOG_DFLT(DEBUG, "%s mutex_suite start", buildID);
taskcount = 1;
tu_case_set_post_cb(testbench_mutex_tc_posttest, (void*)taskcount);
diff --git a/apps/testbench/src/testbench_sem.c b/apps/testbench/src/testbench_sem.c
index 4f6e67a9e8..89b02ff8c6 100644
--- a/apps/testbench/src/testbench_sem.c
+++ b/apps/testbench/src/testbench_sem.c
@@ -20,8 +20,8 @@
#include <stdio.h>
#include <string.h>
#include "os/mynewt.h"
+#include "modlog/modlog.h"
#include "testutil/testutil.h"
-
#include "testbench.h"
#define SEM_TEST_STACK_SIZE 256
@@ -31,8 +31,7 @@ struct os_sem g_sem1;
void
testbench_sem_ts_init(void *arg)
{
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s starting %s", buildID, tu_case_name);
+ MODLOG_DFLT(DEBUG, "%s starting %s", buildID, tu_case_name);
}
void sem_test_basic_handler(void* arg);
@@ -72,8 +71,8 @@ testbench_sem_init(void *arg)
tu_case_idx = 0;
tu_case_failed = 0;
- LOG_DEBUG(&testlog, LOG_MODULE_TEST, "%s testbench_sem suite init",
- buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench_sem suite init",
+ buildID);
tu_suite_set_pass_cb(testbench_ts_pass, NULL);
tu_suite_set_fail_cb(testbench_ts_fail, NULL);
@@ -133,8 +132,7 @@ testbench_sem()
tu_suite_set_init_cb(testbench_sem_init, NULL);
testbench_sem_suite();
- LOG_DEBUG(&testlog, LOG_MODULE_TEST,
- "%s testbench_sem suite complete", buildID);
+ MODLOG_DFLT(DEBUG, "%s testbench_sem suite complete", buildID);
return;
}
diff --git a/apps/timtest/pkg.yml b/apps/timtest/pkg.yml
index b2c6d17a6c..706343b4cd 100644
--- a/apps/timtest/pkg.yml
+++ b/apps/timtest/pkg.yml
@@ -25,9 +25,9 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - sys/console/full
- - kernel/os
- - sys/shell
- - sys/config
- - sys/log/full
- - sys/stats/full
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/config"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/stats/full"
diff --git a/apps/trng_test/pkg.yml b/apps/trng_test/pkg.yml
index 61b8e9246c..3da3f2b7b4 100644
--- a/apps/trng_test/pkg.yml
+++ b/apps/trng_test/pkg.yml
@@ -23,6 +23,6 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
- - sys/console/full
- - hw/drivers/trng
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/console/full"
+ - "@apache-mynewt-core/hw/drivers/trng"
diff --git a/boot/boot_serial/pkg.yml b/boot/boot_serial/pkg.yml
index a0b04e9d4b..8211eb41af 100644
--- a/boot/boot_serial/pkg.yml
+++ b/boot/boot_serial/pkg.yml
@@ -26,12 +26,12 @@ pkg.keywords:
- bootloader
pkg.deps:
- - hw/hal
- - kernel/os
- - encoding/tinycbor
- - encoding/base64
- - sys/flash_map
- - util/crc
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/encoding/tinycbor"
+ - "@apache-mynewt-core/encoding/base64"
+ - "@apache-mynewt-core/sys/flash_map"
+ - "@apache-mynewt-core/util/crc"
pkg.req_apis:
- bootloader
diff --git a/boot/boot_serial/test/pkg.yml b/boot/boot_serial/test/pkg.yml
index b023a4675e..74440e7145 100644
--- a/boot/boot_serial/test/pkg.yml
+++ b/boot/boot_serial/test/pkg.yml
@@ -23,9 +23,9 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/boot_serial
- - boot/bootutil
- - test/testutil
+ - "@apache-mynewt-core/boot/boot_serial"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/test/testutil"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/boot/bootutil/pkg.yml b/boot/bootutil/pkg.yml
index 96703a05ab..ef94c035d5 100644
--- a/boot/bootutil/pkg.yml
+++ b/boot/bootutil/pkg.yml
@@ -29,11 +29,11 @@ pkg.apis:
- bootloader
pkg.deps:
- - hw/hal
- - crypto/mbedtls
- - kernel/os
- - sys/defs
- - sys/flash_map
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/crypto/mbedtls"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/defs"
+ - "@apache-mynewt-core/sys/flash_map"
pkg.deps.BOOTUTIL_SIGN_EC256:
- - crypto/tinycrypt
+ - "@apache-mynewt-core/crypto/tinycrypt"
diff --git a/boot/bootutil/test/pkg.yml b/boot/bootutil/test/pkg.yml
index d13d67a6d8..a02601f129 100644
--- a/boot/bootutil/test/pkg.yml
+++ b/boot/bootutil/test/pkg.yml
@@ -23,8 +23,8 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - boot/bootutil
- - test/testutil
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/test/testutil"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/boot/split/pkg.yml b/boot/split/pkg.yml
index b2537c15bd..b42bc6f53f 100644
--- a/boot/split/pkg.yml
+++ b/boot/split/pkg.yml
@@ -25,7 +25,7 @@ pkg.keywords:
- split
pkg.deps:
- - sys/config
+ - "@apache-mynewt-core/sys/config"
pkg.req_apis:
- bootloader
diff --git a/boot/split_app/pkg.yml b/boot/split_app/pkg.yml
index 77ea11783f..fff542507d 100644
--- a/boot/split_app/pkg.yml
+++ b/boot/split_app/pkg.yml
@@ -22,8 +22,8 @@ pkg.description: Required by the application half of a split image. The split i
pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
pkg.homepage: "http://mynewt.apache.org/"
pkg.deps:
- - kernel/os
+ - "@apache-mynewt-core/kernel/os"
pkg.keywords:
- - split
- - boot
- - image
+ - "@apache-mynewt-core/split"
+ - "@apache-mynewt-core/boot"
+ - "@apache-mynewt-core/image"
diff --git a/compiler/xc32/pkg.yml b/compiler/xc32/pkg.yml
index c14af6ec3c..26593073bf 100644
--- a/compiler/xc32/pkg.yml
+++ b/compiler/xc32/pkg.yml
@@ -27,4 +27,4 @@ pkg.keywords:
- compiler
pkg.deps:
- - libc/baselibc
+ - "@apache-mynewt-core/libc/baselibc"
diff --git a/crypto/mbedtls/test/pkg.yml b/crypto/mbedtls/test/pkg.yml
index c4d2481a10..845beeb89b 100644
--- a/crypto/mbedtls/test/pkg.yml
+++ b/crypto/mbedtls/test/pkg.yml
@@ -23,8 +23,8 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - crypto/mbedtls
- - test/testutil
+ - "@apache-mynewt-core/crypto/mbedtls"
+ - "@apache-mynewt-core/test/testutil"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/crypto/tinycrypt/pkg.yml b/crypto/tinycrypt/pkg.yml
index 55c1fcd118..c336ca5d88 100644
--- a/crypto/tinycrypt/pkg.yml
+++ b/crypto/tinycrypt/pkg.yml
@@ -27,7 +27,7 @@ pkg.cflags:
- "-std=c99"
pkg.deps.TINYCRYPT_UECC_RNG_USE_TRNG:
- - hw/drivers/trng
+ - "@apache-mynewt-core/hw/drivers/trng"
pkg.init.TINYCRYPT_UECC_RNG_USE_TRNG:
mynewt_tinycrypt_pkg_init: 200
diff --git a/docs/os/modules/console/console.rst b/docs/os/modules/console/console.rst
index 731a96308c..57098c51fe 100644
--- a/docs/os/modules/console/console.rst
+++ b/docs/os/modules/console/console.rst
@@ -60,10 +60,10 @@ file:
pkg.name: sys/shell
pkg.deps:
- - kernel/os
- - encoding/base64
- - time/datetime
- - util/crc
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/encoding/base64"
+ - "@apache-mynewt-core/time/datetime"
+ - "@apache-mynewt-core/util/crc"
pkg.req_apis:
- console
@@ -83,16 +83,16 @@ capability and has the following ``pkg.yml`` file:
pkg.name: apps/slinky
pkg.deps:
- - test/flash_test
- - mgmt/imgmgr
- - mgmt/newtmgr
- - mgmt/newtmgr/transport/nmgr_shell
- - kernel/os
- - boot/bootutil
- - sys/shell
- - sys/console/full
+ - "@apache-mynewt-core/test/flash_test"
+ - "@apache-mynewt-core/mgmt/imgmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr"
+ - "@apache-mynewt-core/mgmt/newtmgr/transport/nmgr_shell"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/sys/console/full"
...
- - sys/id
+ - "@apache-mynewt-core/sys/id"
Using the Stub Console Package
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -127,9 +127,9 @@ project boot pkg looks like the following:
pkg.name: apps/boot
pkg.deps:
- - boot/bootutil
- - kernel/os
- - sys/console/stub
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/console/stub"
Using the Minimal Console Package
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -151,13 +151,13 @@ has the following ``pkg.yml`` file:
- loader
pkg.deps:
- - boot/bootutil
- - kernel/os
- - sys/console/stub
+ - "@apache-mynewt-core/boot/bootutil"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/sys/console/stub"
pkg.deps.BOOT_SERIAL.OVERWRITE:
- - sys/console/minimal
- - boot/boot_serial
+ - "@apache-mynewt-core/sys/console/minimal"
+ - "@apache-mynewt-core/boot/boot_serial"
Output to the Console
^^^^^^^^^^^^^^^^^^^^^
diff --git a/docs/os/modules/drivers/flash.rst b/docs/os/modules/drivers/flash.rst
index c9d84653c5..79d9e71e52 100644
--- a/docs/os/modules/drivers/flash.rst
+++ b/docs/os/modules/drivers/flash.rst
@@ -70,7 +70,7 @@ dependency in your pkg.yml:
::
pkg.deps:
- - hw/drivers/flash/at45db
+ - "@apache-mynewt-core/hw/drivers/flash/at45db"
Header file
^^^^^^^^^^^
diff --git a/docs/os/modules/drivers/mmc.rst b/docs/os/modules/drivers/mmc.rst
index 664406ecbf..9efc99bec9 100644
--- a/docs/os/modules/drivers/mmc.rst
+++ b/docs/os/modules/drivers/mmc.rst
@@ -28,7 +28,7 @@ dependency in your pkg.yml:
::
pkg.deps:
- - hw/drivers/mmc
+ - "@apache-mynewt-core/hw/drivers/mmc"
Returned values
^^^^^^^^^^^^^^^
diff --git a/docs/os/modules/fs/fatfs.rst b/docs/os/modules/fs/fatfs.rst
index c81e335d18..8c76d8230f 100644
--- a/docs/os/modules/fs/fatfs.rst
+++ b/docs/os/modules/fs/fatfs.rst
@@ -40,7 +40,7 @@ your project:
::
pkg.deps:
- - fs/fatfs
+ - "@apache-mynewt-core/fs/fatfs"
It can now be used through the standard file system abstraction
functions as described in `FS API </os/modules/fs/fs/fs#API>`__.
diff --git a/docs/os/modules/fs/fs.rst b/docs/os/modules/fs/fs.rst
index da7a63d068..150f75d1c2 100644
--- a/docs/os/modules/fs/fs.rst
+++ b/docs/os/modules/fs/fs.rst
@@ -40,8 +40,8 @@ used.
pkg.name: repos/apache-mynewt-core/apps/slinky
pkg.deps:
- - fs/fs # include the file operations interfaces
- - fs/nffs # include the NFFS filesystem implementation
+ - "@apache-mynewt-core/fs/fs" # include the file operations interfaces
+ - "@apache-mynewt-core/fs/nffs" # include the NFFS filesystem implementation
::
@@ -70,7 +70,7 @@ package.
# repos/apache-mynewt-core/libs/imgmgr/pkg.yml
pkg.name: libs/imgmgr
pkg.deps:
- - fs/fs
+ - "@apache-mynewt-core/fs/fs"
# [...]
diff --git a/docs/os/modules/fs/otherfs.rst b/docs/os/modules/fs/otherfs.rst
index 970f92dd01..e54082969f 100644
--- a/docs/os/modules/fs/otherfs.rst
+++ b/docs/os/modules/fs/otherfs.rst
@@ -19,11 +19,11 @@ the first item in the ``pkg.deps`` list.
pkg.name: fs/nffs
pkg.deps:
- - fs/fs
- - hw/hal
- - libs/os
- - libs/testutil
- - sys/log
+ - "@apache-mynewt-core/fs/fs"
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/libs/os"
+ - "@apache-mynewt-core/libs/testutil"
+ - "@apache-mynewt-core/sys/log"
2. Register your package's API with the ``fs/fs`` interface.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/os/modules/logs/logs.rst b/docs/os/modules/logs/logs.rst
index 7da70de106..22c7ee15c9 100644
--- a/docs/os/modules/logs/logs.rst
+++ b/docs/os/modules/logs/logs.rst
@@ -36,7 +36,7 @@ file:
.. code-block:: console
pkg.deps:
- - sys/log/full
+ - "@apache-mynewt-core/sys/log/full"
You can use the ``sys/log/stub`` package if you want to build your
application without logging to reduce code size.
diff --git a/docs/os/modules/sensor_framework/sensor_create.rst b/docs/os/modules/sensor_framework/sensor_create.rst
index 5fbd545fe4..777ffb2be1 100644
--- a/docs/os/modules/sensor_framework/sensor_create.rst
+++ b/docs/os/modules/sensor_framework/sensor_create.rst
@@ -149,7 +149,7 @@ For example:
pkg.deps.LIS2DH12_ONB:
- - hw/drivers/sensors/lis2dh12
+ - "@apache-mynewt-core/hw/drivers/sensors/lis2dh12"
pkg.init:
config_lis2dh12_sensor: 400
@@ -225,7 +225,7 @@ For example:
pkg.deps.BNO055_OFB:
- - hw/drivers/sensors/bno055
+ - "@apache-mynewt-core/hw/drivers/sensors/bno055"
Reconfiguring A Sensor Device by an Application
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
diff --git a/docs/os/modules/shell/shell.rst b/docs/os/modules/shell/shell.rst
index e701b58342..c471a5b33f 100644
--- a/docs/os/modules/shell/shell.rst
+++ b/docs/os/modules/shell/shell.rst
@@ -49,7 +49,7 @@ setting to enable the log command in the shell:
# sys/log/full pkg.yml
pkg.deps.LOG_CLI:
- - sys/shell
+ - "@apache-mynewt-core/sys/shell"
Description
-----------
diff --git a/docs/os/modules/sysinitconfig/sysinitconfig.rst b/docs/os/modules/sysinitconfig/sysinitconfig.rst
index 8a3f4d9a3b..ae70886f4f 100644
--- a/docs/os/modules/sysinitconfig/sysinitconfig.rst
+++ b/docs/os/modules/sysinitconfig/sysinitconfig.rst
@@ -660,11 +660,11 @@ value is non-zero. Here is an example from the ``libs/os`` package
.. code-block:: yaml
pkg.deps:
- - sys/sysinit
- - util/mem
+ - "@apache-mynewt-core/sys/sysinit"
+ - "@apache-mynewt-core/util/mem"
pkg.deps.OS_CLI
- - sys/shell
+ - "@apache-mynewt-core/sys/shell"
This example specifies that the ``os`` package depends on the
``sysinit`` and ``mem`` packages, and also depends on the ``shell``
diff --git a/encoding/base64/test/pkg.yml b/encoding/base64/test/pkg.yml
index 129ffd5d0d..6d6438cacd 100644
--- a/encoding/base64/test/pkg.yml
+++ b/encoding/base64/test/pkg.yml
@@ -23,8 +23,8 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - test/testutil
- - encoding/base64
+ - "@apache-mynewt-core/test/testutil"
+ - "@apache-mynewt-core/encoding/base64"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/encoding/cborattr/pkg.yml b/encoding/cborattr/pkg.yml
index 0f62824b4d..c139b7d85a 100644
--- a/encoding/cborattr/pkg.yml
+++ b/encoding/cborattr/pkg.yml
@@ -24,6 +24,6 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - "encoding/tinycbor"
+ - "@apache-mynewt-core/encoding/tinycbor"
pkg.cflags.FLOAT_USER: -DFLOAT_SUPPORT
diff --git a/encoding/cborattr/test/pkg.yml b/encoding/cborattr/test/pkg.yml
index 941a9853a2..945cb66efa 100644
--- a/encoding/cborattr/test/pkg.yml
+++ b/encoding/cborattr/test/pkg.yml
@@ -23,9 +23,9 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - encoding/tinycbor
- - encoding/cborattr
- - test/testutil
+ - "@apache-mynewt-core/encoding/tinycbor"
+ - "@apache-mynewt-core/encoding/cborattr"
+ - "@apache-mynewt-core/test/testutil"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/encoding/json/test/pkg.yml b/encoding/json/test/pkg.yml
index ba4e95209b..3062b4af43 100644
--- a/encoding/json/test/pkg.yml
+++ b/encoding/json/test/pkg.yml
@@ -23,8 +23,8 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - encoding/json
- - test/testutil
+ - "@apache-mynewt-core/encoding/json"
+ - "@apache-mynewt-core/test/testutil"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/encoding/tinycbor/include/tinycbor/cbor.h b/encoding/tinycbor/include/tinycbor/cbor.h
index 528f666cba..ce45d5b22d 100644
--- a/encoding/tinycbor/include/tinycbor/cbor.h
+++ b/encoding/tinycbor/include/tinycbor/cbor.h
@@ -166,10 +166,13 @@ typedef struct cbor_encoder_writer {
int bytes_written;
} cbor_encoder_writer;
+struct cbor_iovec {
+ void *iov_base;
+ size_t iov_len;
+};
/* Encoder API */
-struct CborEncoder
-{
+struct CborEncoder {
cbor_encoder_writer *writer;
void *writer_arg;
size_t added;
@@ -190,6 +193,9 @@ CBOR_API CborError cbor_encode_text_string(CborEncoder *encoder, const char *str
CBOR_INLINE_API CborError cbor_encode_text_stringz(CborEncoder *encoder, const char *string)
{ return cbor_encode_text_string(encoder, string, strlen(string)); }
CBOR_API CborError cbor_encode_byte_string(CborEncoder *encoder, const uint8_t *string, size_t length);
+CBOR_API CborError cbor_encode_byte_iovec(CborEncoder *encoder,
+ const struct cbor_iovec iov[],
+ int iov_len);
CBOR_API CborError cbor_encode_floating_point(CborEncoder *encoder, CborType fpType, const void *value);
CBOR_INLINE_API CborError cbor_encode_bytes_written(CborEncoder *encoder)
{ return encoder->writer->bytes_written; }
diff --git a/encoding/tinycbor/src/cborencoder.c b/encoding/tinycbor/src/cborencoder.c
index e523ffb0e5..ab19b54bd6 100644
--- a/encoding/tinycbor/src/cborencoder.c
+++ b/encoding/tinycbor/src/cborencoder.c
@@ -410,6 +410,36 @@ CborError cbor_encode_byte_string(CborEncoder *encoder, const uint8_t *string, s
return encode_string(encoder, length, ByteStringType << MajorTypeShift, string);
}
+/**
+ * Appends the byte string passed as \a iov and \a iov_len to the CBOR
+ * stream provided by \a encoder. CBOR byte strings are arbitrary raw data.
+ *
+ * \sa CborError cbor_encode_text_stringz, cbor_encode_byte_string
+ */
+CborError cbor_encode_byte_iovec(CborEncoder *encoder,
+ const struct cbor_iovec iov[], int iov_len)
+{
+ CborError err;
+ size_t length;
+ int i;
+
+ length = 0;
+ for (i = 0; i < iov_len; i++) {
+ length += iov[i].iov_len;
+ }
+ err = encode_number(encoder, length, ByteStringType << MajorTypeShift);
+ if (err && !isOomError(err)) {
+ return err;
+ }
+ for (i = 0; i < iov_len; i++) {
+ err = append_to_buffer(encoder, iov[i].iov_base, iov[i].iov_len);
+ if (err && !isOomError(err)) {
+ return err;
+ }
+ }
+ return 0;
+}
+
/**
* Appends the byte string \a string of length \a length to the CBOR stream
* provided by \a encoder. CBOR byte strings are arbitrary raw data.
diff --git a/fs/disk/pkg.yml b/fs/disk/pkg.yml
index 0b65bd4106..623b46bf30 100644
--- a/fs/disk/pkg.yml
+++ b/fs/disk/pkg.yml
@@ -24,4 +24,4 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - kernel/os
+ - "@apache-mynewt-core/kernel/os"
diff --git a/fs/fatfs/pkg.yml b/fs/fatfs/pkg.yml
index 8a9297eb59..e1d63077df 100644
--- a/fs/fatfs/pkg.yml
+++ b/fs/fatfs/pkg.yml
@@ -26,12 +26,12 @@ pkg.keywords:
- filesystem
pkg.deps:
- - fs/fs
- - util/crc
- - hw/hal
- - kernel/os
- - test/testutil
- - sys/flash_map
+ - "@apache-mynewt-core/fs/fs"
+ - "@apache-mynewt-core/util/crc"
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/test/testutil"
+ - "@apache-mynewt-core/sys/flash_map"
pkg.req_apis:
- log
- stats
diff --git a/fs/fcb/pkg.yml b/fs/fcb/pkg.yml
index 8e7ab4820a..c4f795e205 100644
--- a/fs/fcb/pkg.yml
+++ b/fs/fcb/pkg.yml
@@ -25,6 +25,6 @@ pkg.keywords:
- log
pkg.deps:
- - kernel/os
- - util/crc
- - sys/flash_map
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/util/crc"
+ - "@apache-mynewt-core/sys/flash_map"
diff --git a/fs/fcb/test/pkg.yml b/fs/fcb/test/pkg.yml
index cc7c93cf3f..555bde1b25 100644
--- a/fs/fcb/test/pkg.yml
+++ b/fs/fcb/test/pkg.yml
@@ -23,8 +23,8 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - test/testutil
- - fs/fcb
+ - "@apache-mynewt-core/test/testutil"
+ - "@apache-mynewt-core/fs/fcb"
pkg.deps.SELFTEST:
- - sys/console/stub
+ - "@apache-mynewt-core/sys/console/stub"
diff --git a/fs/fs/pkg.yml b/fs/fs/pkg.yml
index 4091540ae9..e73b200cd4 100644
--- a/fs/fs/pkg.yml
+++ b/fs/fs/pkg.yml
@@ -27,7 +27,7 @@ pkg.keywords:
- ffs
pkg.deps:
- - fs/disk
+ - "@apache-mynewt-core/fs/disk"
pkg.deps.FS_CLI:
- - sys/shell
+ - "@apache-mynewt-core/sys/shell"
diff --git a/fs/nffs/pkg.yml b/fs/nffs/pkg.yml
index 276f4565b9..dcab5a29d7 100644
--- a/fs/nffs/pkg.yml
+++ b/fs/nffs/pkg.yml
@@ -27,14 +27,15 @@ pkg.keywords:
- ffs
pkg.deps:
- - fs/fs
- - util/crc
- - hw/hal
- - kernel/os
- - test/testutil
- - sys/flash_map
+ - "@apache-mynewt-core/fs/fs"
+ - "@apache-mynewt-core/util/crc"
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/test/testutil"
+ - "@apache-mynewt-core/sys/flash_map"
+ - "@apache-mynewt-core/sys/log/modlog"
+
pkg.req_apis:
- - log
- stats
pkg.init:
diff --git a/fs/nffs/src/nffs.c b/fs/nffs/src/nffs.c
index cd48e4302e..7359a694de 100644
--- a/fs/nffs/src/nffs.c
+++ b/fs/nffs/src/nffs.c
@@ -57,8 +57,6 @@ struct nffs_inode_entry *nffs_lost_found_dir;
static struct os_mutex nffs_mutex;
-struct log nffs_log;
-
static int nffs_open(const char *path, uint8_t access_flags,
struct fs_file **out_file);
static int nffs_close(struct fs_file *fs_file);
diff --git a/fs/nffs/src/nffs_priv.h b/fs/nffs/src/nffs_priv.h
index 2ca3b9c02b..2203b47004 100644
--- a/fs/nffs/src/nffs_priv.h
+++ b/fs/nffs/src/nffs_priv.h
@@ -21,8 +21,8 @@
#define H_NFFS_PRIV_
#include <inttypes.h>
-#include "log/log.h"
#include "os/mynewt.h"
+#include "modlog/modlog.h"
#include "nffs/nffs.h"
#include "fs/fs.h"
#include "crc/crc16.h"
@@ -299,8 +299,6 @@ extern struct nffs_hash_list *nffs_hash;
extern struct nffs_inode_entry *nffs_root_dir;
extern struct nffs_inode_entry *nffs_lost_found_dir;
-extern struct log nffs_log;
-
/* @area */
int nffs_area_magic_is_set(const struct nffs_disk_area *disk_area);
int nffs_area_is_scratch(const struct nffs_disk_area *disk_area);
@@ -512,19 +510,8 @@ int nffs_write_to_file(struct nffs_file *file, const void *data, int len);
#define NFFS_FLASH_LOC_NONE nffs_flash_loc(NFFS_AREA_ID_NONE, 0)
-#if 0
-#ifdef ARCH_sim
-#include <stdio.h>
-#define NFFS_LOG(lvl, ...) \
- printf(__VA_ARGS__)
-#else
-#define NFFS_LOG(lvl, ...) \
- LOG_ ## lvl(&nffs_log, LOG_MODULE_NFFS, __VA_ARGS__)
-#endif
-#endif /* 0 */
-
#define NFFS_LOG(lvl, ...) \
- LOG_ ## lvl(&nffs_log, LOG_MODULE_NFFS, __VA_ARGS__)
+ MODLOG_ ## lvl(LOG_MODULE_NFFS, __VA_ARGS__)
#ifdef __cplusplus
}
diff --git a/fs/nffs/test/pkg.yml b/fs/nffs/test/pkg.yml
index 9e64e71816..7487417cb8 100644
--- a/fs/nffs/test/pkg.yml
+++ b/fs/nffs/test/pkg.yml
@@ -23,10 +23,10 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - fs/nffs
- - test/testutil
+ - "@apache-mynewt-core/fs/nffs"
+ - "@apache-mynewt-core/test/testutil"
pkg.deps.SELFTEST:
- - sys/console/stub
- - sys/log/full
- - sys/stats/stub
+ - "@apache-mynewt-core/sys/console/stub"
+ - "@apache-mynewt-core/sys/log/full"
+ - "@apache-mynewt-core/sys/stats/stub"
diff --git a/hw/battery/include/battery/battery_adc.h b/hw/battery/include/battery/battery_adc.h
index 520fa3951f..b61a44572c 100644
--- a/hw/battery/include/battery/battery_adc.h
+++ b/hw/battery/include/battery/battery_adc.h
@@ -45,6 +45,12 @@ struct battery_adc_cfg
int mul;
/* divider for ADC reading */
int div;
+ /* GPIO pin to activate for measurement */
+ int activation_pin;
+ /* GPIO activation needed for measurement */
+ uint8_t activation_pin_needed:1;
+ /* GPIO value needed for measurement */
+ uint8_t activation_pin_level:1;
};
/* battery_adc device */
diff --git a/hw/battery/pkg.yml b/hw/battery/pkg.yml
index eed0b0fb88..1bb14bda87 100644
--- a/hw/battery/pkg.yml
+++ b/hw/battery/pkg.yml
@@ -22,7 +22,7 @@ pkg.description: Battery/Fuel Gauge Controller IC Interface
pkg.keywords:
pkg.deps:
- - kernel/os
+ - "@apache-mynewt-core/kernel/os"
pkg.req_apis:
- console
diff --git a/hw/battery/src/battery_adc.c b/hw/battery/src/battery_adc.c
index af9f74acba..80093b7b15 100644
--- a/hw/battery/src/battery_adc.c
+++ b/hw/battery/src/battery_adc.c
@@ -23,6 +23,7 @@
#include <battery/battery_drv.h>
#include <battery/battery_adc.h>
#include <adc/adc.h>
+#include <hal/hal_gpio.h>
/* Battery manager interface functions */
@@ -34,11 +35,26 @@ battery_adc_property_get(struct battery_driver *driver,
struct battery_adc *bat_adc = (struct battery_adc *)driver->bd_driver_data;
int val;
- /* Only one property is supported, voltate */
+ /* Only one property is supported, voltage */
if (property->bp_type == BATTERY_PROP_VOLTAGE_NOW &&
property->bp_flags == 0) {
+
+ /* Activate GPIO if it was configured */
+ if (bat_adc->cfg.activation_pin_needed &&
+ bat_adc->cfg.activation_pin != -1) {
+ hal_gpio_write(bat_adc->cfg.activation_pin,
+ bat_adc->cfg.activation_pin_level);
+ }
/* Blocking read of voltage */
rc = adc_read_channel(bat_adc->adc_dev, bat_adc->cfg.channel, &val);
+
+ /* Deactivate GPIO if it was configured */
+ if (bat_adc->cfg.activation_pin_needed &&
+ bat_adc->cfg.activation_pin != -1) {
+ hal_gpio_write(bat_adc->cfg.activation_pin,
+ bat_adc->cfg.activation_pin_level ? 0 : 1);
+ }
+
if (rc == 0) {
property->bp_valid = 1;
/* Convert value to according to reference voltage and multiplier
@@ -104,6 +120,13 @@ battery_adc_open(struct os_dev *dev, uint32_t timeout, void *arg)
/* Setup channel configuration to use for battery voltage */
adc_chan_config(bat_adc->adc_dev, bat_adc->cfg.channel,
bat_adc->cfg.adc_channel_cfg);
+
+ /* Additional GPIO needed before measurement ? */
+ if (bat_adc->cfg.activation_pin_needed &&
+ bat_adc->cfg.activation_pin != -1) {
+ hal_gpio_init_out(bat_adc->cfg.activation_pin,
+ bat_adc->cfg.activation_pin_level ? 0 : 1);
+ }
rc = 0;
}
return rc;
diff --git a/hw/bsp/ada_feather_nrf52/bsp.yml b/hw/bsp/ada_feather_nrf52/bsp.yml
index 3721c2b710..13e2961a8e 100644
--- a/hw/bsp/ada_feather_nrf52/bsp.yml
+++ b/hw/bsp/ada_feather_nrf52/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/ada_feather_nrf52/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/ada_feather_nrf52/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/ada_feather_nrf52/split_ada_feather_nrf52.ld"
bsp.downloadscript: "hw/bsp/ada_feather_nrf52/ada_feather_nrf52_download.sh"
bsp.debugscript: "hw/bsp/ada_feather_nrf52/ada_feather_nrf52_debug.sh"
diff --git a/hw/bsp/ada_feather_nrf52/pkg.yml b/hw/bsp/ada_feather_nrf52/pkg.yml
index c9e9d5f6bc..1ab138eb55 100644
--- a/hw/bsp/ada_feather_nrf52/pkg.yml
+++ b/hw/bsp/ada_feather_nrf52/pkg.yml
@@ -34,29 +34,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/apollo2_evb/bsp.yml b/hw/bsp/apollo2_evb/bsp.yml
index c3ca996d27..b10edc63aa 100644
--- a/hw/bsp/apollo2_evb/bsp.yml
+++ b/hw/bsp/apollo2_evb/bsp.yml
@@ -23,10 +23,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/apollo2_evb/apollo2.ld"
- - "hw/mcu/ambiq/apollo2/apollo2.ld"
+ - "@apache-mynewt-core/hw/mcu/ambiq/apollo2/apollo2.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/apollo2_evb/boot-apollo2.ld"
- - "hw/mcu/ambiq/apollo2/apollo2.ld"
+ - "@apache-mynewt-core/hw/mcu/ambiq/apollo2/apollo2.ld"
bsp.downloadscript: "hw/bsp/apollo2_evb/apollo2_evb_download.sh"
bsp.debugscript: "hw/bsp/apollo2_evb/apollo2_evb_debug.sh"
diff --git a/hw/bsp/apollo2_evb/pkg.yml b/hw/bsp/apollo2_evb/pkg.yml
index 67693b3417..54ffe8cff6 100644
--- a/hw/bsp/apollo2_evb/pkg.yml
+++ b/hw/bsp/apollo2_evb/pkg.yml
@@ -31,8 +31,8 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/ambiq/apollo2
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/ambiq/apollo2"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/arduino_primo_nrf52/bsp.yml b/hw/bsp/arduino_primo_nrf52/bsp.yml
index 15928c7ef2..da5dcf52ad 100644
--- a/hw/bsp/arduino_primo_nrf52/bsp.yml
+++ b/hw/bsp/arduino_primo_nrf52/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/arduino_primo_nrf52/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/arduino_primo_nrf52/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/arduino_primo_nrf52/split-primo.ld"
bsp.downloadscript: "hw/bsp/arduino_primo_nrf52/primo_download.sh"
bsp.debugscript: "hw/bsp/arduino_primo_nrf52/primo_debug.sh"
diff --git a/hw/bsp/arduino_primo_nrf52/pkg.yml b/hw/bsp/arduino_primo_nrf52/pkg.yml
index c19aef1020..82a16a8d39 100644
--- a/hw/bsp/arduino_primo_nrf52/pkg.yml
+++ b/hw/bsp/arduino_primo_nrf52/pkg.yml
@@ -34,29 +34,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/bbc_microbit/bsp.yml b/hw/bsp/bbc_microbit/bsp.yml
index 7a7063cda2..c63b62cfbc 100644
--- a/hw/bsp/bbc_microbit/bsp.yml
+++ b/hw/bsp/bbc_microbit/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/bbc_microbit/nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/bbc_microbit/boot-nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/bbc_microbit/split-microbit.ld"
bsp.downloadscript: hw/bsp/bbc_microbit/microbit_download.sh
bsp.debugscript: hw/bsp/bbc_microbit/microbit_debug.sh
diff --git a/hw/bsp/bbc_microbit/pkg.yml b/hw/bsp/bbc_microbit/pkg.yml
index 92276f8f33..20f60657f5 100644
--- a/hw/bsp/bbc_microbit/pkg.yml
+++ b/hw/bsp/bbc_microbit/pkg.yml
@@ -30,14 +30,14 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/ble400/bsp.yml b/hw/bsp/ble400/bsp.yml
index d724bba5fc..051a7a553a 100644
--- a/hw/bsp/ble400/bsp.yml
+++ b/hw/bsp/ble400/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/ble400/nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/ble400/boot-nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/ble400/split-ble400.ld"
bsp.downloadscript: "hw/bsp/ble400/ble400_download.sh"
bsp.debugscript: "hw/bsp/ble400/ble400_debug.sh"
diff --git a/hw/bsp/ble400/pkg.yml b/hw/bsp/ble400/pkg.yml
index 9b251a02b1..744cb9397c 100644
--- a/hw/bsp/ble400/pkg.yml
+++ b/hw/bsp/ble400/pkg.yml
@@ -31,17 +31,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/bmd200/bsp.yml b/hw/bsp/bmd200/bsp.yml
index 388966d707..6d661e8585 100644
--- a/hw/bsp/bmd200/bsp.yml
+++ b/hw/bsp/bmd200/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/bmd200/nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/bmd200/boot-nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/bmd200/split-nrf51dk.ld"
bsp.downloadscript: "hw/bsp/bmd200/nrf51dk_download.sh"
bsp.debugscript: "hw/bsp/bmd200/nrf51dk_debug.sh"
diff --git a/hw/bsp/bmd200/pkg.yml b/hw/bsp/bmd200/pkg.yml
index 6863f66009..af863a8f35 100644
--- a/hw/bsp/bmd200/pkg.yml
+++ b/hw/bsp/bmd200/pkg.yml
@@ -31,17 +31,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/bmd300eval/bsp.yml b/hw/bsp/bmd300eval/bsp.yml
index 68920b3e04..d1b22627b5 100644
--- a/hw/bsp/bmd300eval/bsp.yml
+++ b/hw/bsp/bmd300eval/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/bmd300eval/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/bmd300eval/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/bmd300eval/split-bmd300eval.ld"
bsp.downloadscript: "hw/bsp/bmd300eval/bmd300eval_download.sh"
bsp.debugscript: "hw/bsp/bmd300eval/bmd300eval_debug.sh"
diff --git a/hw/bsp/bmd300eval/pkg.yml b/hw/bsp/bmd300eval/pkg.yml
index 7343d4fabf..73f304270f 100644
--- a/hw/bsp/bmd300eval/pkg.yml
+++ b/hw/bsp/bmd300eval/pkg.yml
@@ -34,29 +34,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/calliope_mini/bsp.yml b/hw/bsp/calliope_mini/bsp.yml
index 7d2327c1b7..1d02833393 100644
--- a/hw/bsp/calliope_mini/bsp.yml
+++ b/hw/bsp/calliope_mini/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: "@apache-mynewt-core/compiler/arm-none-eabi-m0"
bsp.linkerscript:
- hw/bsp/calliope_mini/nrf51xxac.ld
- - hw/mcu/nordic/nrf51xxx/nrf51.ld
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- hw/bsp/calliope_mini/boot-nrf51xxac.ld
- - hw/mcu/nordic/nrf51xxx/nrf51.ld
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: hw/bsp/calliope_mini/split-calliope_mini.ld
bsp.downloadscript: hw/bsp/calliope_mini/calliope_mini_download.sh
bsp.debugscript: hw/bsp/calliope_mini/calliope_mini_debug.sh
diff --git a/hw/bsp/calliope_mini/pkg.yml b/hw/bsp/calliope_mini/pkg.yml
index 1be932fc01..ec1ba37268 100644
--- a/hw/bsp/calliope_mini/pkg.yml
+++ b/hw/bsp/calliope_mini/pkg.yml
@@ -30,14 +30,14 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/calliope_mini/syscfg.yml b/hw/bsp/calliope_mini/syscfg.yml
index 2fcf32e32f..34077c9c44 100644
--- a/hw/bsp/calliope_mini/syscfg.yml
+++ b/hw/bsp/calliope_mini/syscfg.yml
@@ -66,6 +66,10 @@ syscfg.defs:
I2C_0_FREQ_KHZ:
description: 'Frequency in khz for I2C_0 bus'
value: 100
+ I2C_0_FREQ:
+ description: 'Use I2C_0_FREQ_KHZ instead'
+ defunct: 1
+ value: 100
I2C_1_PIN_SCL:
description: 'SCL pin for I2C_1'
diff --git a/hw/bsp/ci40/pkg.yml b/hw/bsp/ci40/pkg.yml
index 218a35df29..3701f438b8 100644
--- a/hw/bsp/ci40/pkg.yml
+++ b/hw/bsp/ci40/pkg.yml
@@ -30,14 +30,14 @@ pkg.keywords:
pkg.cflags:
pkg.deps:
- - hw/mcu/mips/danube
- - libc/baselibc
- - hw/mips-hal
+ - "@apache-mynewt-core/hw/mcu/mips/danube"
+ - "@apache-mynewt-core/libc/baselibc"
+ - "@apache-mynewt-core/hw/mips-hal"
pkg.arch: mips
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/dwm1001-dev/bsp.yml b/hw/bsp/dwm1001-dev/bsp.yml
index 989f0df8a0..61aca50444 100644
--- a/hw/bsp/dwm1001-dev/bsp.yml
+++ b/hw/bsp/dwm1001-dev/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/dwm1001-dev/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/dwm1001-dev/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/dwm1001-dev/split-dwm1001-dev.ld"
bsp.downloadscript: "hw/bsp/dwm1001-dev/dwm1001-dev_download.sh"
bsp.debugscript: "hw/bsp/dwm1001-dev/dwm1001-dev_debug.sh"
diff --git a/hw/bsp/dwm1001-dev/pkg.yml b/hw/bsp/dwm1001-dev/pkg.yml
index e528f583fe..70bfcd5666 100644
--- a/hw/bsp/dwm1001-dev/pkg.yml
+++ b/hw/bsp/dwm1001-dev/pkg.yml
@@ -33,29 +33,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/embarc_emsk/pkg.yml b/hw/bsp/embarc_emsk/pkg.yml
index 1529fb5207..8faf2566e5 100644
--- a/hw/bsp/embarc_emsk/pkg.yml
+++ b/hw/bsp/embarc_emsk/pkg.yml
@@ -27,7 +27,7 @@ pkg.keywords:
- embarc_emsk
pkg.deps:
- - hw/mcu/arc/snps
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/arc/snps"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.cflags: -mcpu=em4_dmips -mlittle-endian -mcode-density -mdiv-rem -mswap -mbarrel-shifter
diff --git a/hw/bsp/frdm-k64f/pkg.yml b/hw/bsp/frdm-k64f/pkg.yml
index a8dd57389e..86cb0f92d8 100644
--- a/hw/bsp/frdm-k64f/pkg.yml
+++ b/hw/bsp/frdm-k64f/pkg.yml
@@ -42,23 +42,23 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nxp/MK64F12
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nxp/MK64F12"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_2:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_3:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_4:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_5:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/hifive1/pkg.yml b/hw/bsp/hifive1/pkg.yml
index dd901faf81..af2091c439 100644
--- a/hw/bsp/hifive1/pkg.yml
+++ b/hw/bsp/hifive1/pkg.yml
@@ -27,11 +27,11 @@ pkg.keywords:
- riscv
pkg.deps:
- - hw/mcu/sifive/fe310
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/sifive/fe310"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.cflags: -march=rv32imac -mabi=ilp32
diff --git a/hw/bsp/native-armv7/pkg.yml b/hw/bsp/native-armv7/pkg.yml
index b6e19f52ac..47465926fc 100644
--- a/hw/bsp/native-armv7/pkg.yml
+++ b/hw/bsp/native-armv7/pkg.yml
@@ -27,9 +27,9 @@ pkg.keywords:
- bsp
pkg.deps:
- - hw/mcu/native
- - hw/drivers/uart/uart_hal
- - net/ip/native_sockets
+ - "@apache-mynewt-core/hw/mcu/native"
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+ - "@apache-mynewt-core/net/ip/native_sockets"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/native
+ - "@apache-mynewt-core/hw/drivers/nimble/native"
diff --git a/hw/bsp/native-mips/pkg.yml b/hw/bsp/native-mips/pkg.yml
index b9288da2a0..ee90c379f4 100644
--- a/hw/bsp/native-mips/pkg.yml
+++ b/hw/bsp/native-mips/pkg.yml
@@ -27,9 +27,9 @@ pkg.keywords:
- bsp
pkg.deps:
- - hw/mcu/native
- - hw/drivers/uart/uart_hal
- - net/ip/native_sockets
+ - "@apache-mynewt-core/hw/mcu/native"
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+ - "@apache-mynewt-core/net/ip/native_sockets"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/native
+ - "@apache-mynewt-core/hw/drivers/nimble/native"
diff --git a/hw/bsp/native/pkg.yml b/hw/bsp/native/pkg.yml
index 52d9b56b80..abef00e080 100644
--- a/hw/bsp/native/pkg.yml
+++ b/hw/bsp/native/pkg.yml
@@ -27,9 +27,9 @@ pkg.keywords:
- bsp
pkg.deps:
- - hw/mcu/native
- - hw/drivers/uart/uart_hal
- - net/ip/native_sockets
+ - "@apache-mynewt-core/hw/mcu/native"
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+ - "@apache-mynewt-core/net/ip/native_sockets"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/native
+ - "@apache-mynewt-core/hw/drivers/nimble/native"
diff --git a/hw/bsp/nina-b1/bsp.yml b/hw/bsp/nina-b1/bsp.yml
index 6ee297a5f9..6abadb8169 100644
--- a/hw/bsp/nina-b1/bsp.yml
+++ b/hw/bsp/nina-b1/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nina-b1/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nina-b1/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/nina-b1/split-nrf52dk.ld"
bsp.downloadscript: "hw/bsp/nina-b1/nrf52dk_download.sh"
bsp.debugscript: "hw/bsp/nina-b1/nrf52dk_debug.sh"
diff --git a/hw/bsp/nina-b1/pkg.yml b/hw/bsp/nina-b1/pkg.yml
index e2789e2476..7991e6a9a8 100644
--- a/hw/bsp/nina-b1/pkg.yml
+++ b/hw/bsp/nina-b1/pkg.yml
@@ -33,35 +33,35 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/nrf51-arduino_101/bsp.yml b/hw/bsp/nrf51-arduino_101/bsp.yml
index 1b2cf94865..6f1f667ab1 100644
--- a/hw/bsp/nrf51-arduino_101/bsp.yml
+++ b/hw/bsp/nrf51-arduino_101/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/nrf51-arduino_101/nrf51xxaa.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf51-arduino_101/boot-nrf51xxaa.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.downloadscript: "hw/bsp/nrf51-arduino_101/nrf51dk-16kbram_download.sh"
bsp.debugscript: "hw/bsp/nrf51-arduino_101/nrf51dk-16kbram_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nrf51-arduino_101/nrf51dk-16kbram_download.cmd"
diff --git a/hw/bsp/nrf51-arduino_101/pkg.yml b/hw/bsp/nrf51-arduino_101/pkg.yml
index 46431b067e..bee1aaa9aa 100644
--- a/hw/bsp/nrf51-arduino_101/pkg.yml
+++ b/hw/bsp/nrf51-arduino_101/pkg.yml
@@ -30,17 +30,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/nrf51-blenano/bsp.yml b/hw/bsp/nrf51-blenano/bsp.yml
index c72efecb22..5214a2c7ef 100644
--- a/hw/bsp/nrf51-blenano/bsp.yml
+++ b/hw/bsp/nrf51-blenano/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/nrf51-blenano/nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf51-blenano/boot-nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/nrf51-blenano/split-nrf51dk.ld"
bsp.downloadscript: "hw/bsp/nrf51-blenano/nrf51dk_download.sh"
bsp.debugscript: "hw/bsp/nrf51-blenano/nrf51dk_debug.sh"
diff --git a/hw/bsp/nrf51-blenano/pkg.yml b/hw/bsp/nrf51-blenano/pkg.yml
index 535bf3cd07..38e8a21544 100644
--- a/hw/bsp/nrf51-blenano/pkg.yml
+++ b/hw/bsp/nrf51-blenano/pkg.yml
@@ -31,17 +31,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/nrf51-blenano/syscfg.yml b/hw/bsp/nrf51-blenano/syscfg.yml
index dd3dcfe4c5..59a70cbd4a 100644
--- a/hw/bsp/nrf51-blenano/syscfg.yml
+++ b/hw/bsp/nrf51-blenano/syscfg.yml
@@ -49,6 +49,18 @@ syscfg.defs:
I2C_0_FREQ_KHZ:
description: 'Frequency in khz for I2C_0 bus'
value: 100
+ I2C_0_FREQUENCY:
+ description: 'Use I2C_0_FREQ_KHZ instead'
+ defunct: 1
+ value: 100
+ I2C_0_SDA_PIN:
+ description: 'Use I2C_0_PIN_SDA instead'
+ defunct: 1
+ value: 6
+ I2C_0_SCL_PIN:
+ description: 'Use I2C_0_PIN_SCL instead'
+ defunct: 1
+ value: 7
I2C_1_PIN_SCL:
description: 'SCL pin for I2C_1'
@@ -59,6 +71,19 @@ syscfg.defs:
I2C_1_FREQ_KHZ:
description: 'Frequency in khz for I2C_1 bus'
value: 100
+ I2C_1_FREQUENCY:
+ description: 'Use I2C_1_FREQ_KHZ instead'
+ defunct: 1
+ value: 100
+ I2C_1_SDA_PIN:
+ description: 'Use I2C_1_PIN_SDA instead'
+ defunct: 1
+ value: 28
+ I2C_1_SCL_PIN:
+ description: 'Use I2C_1_PIN_SCL instead'
+ defunct: 1
+ value: 29
+
TIMER_0:
description: 'NRF51 Timer 0'
diff --git a/hw/bsp/nrf51dk-16kbram/bsp.yml b/hw/bsp/nrf51dk-16kbram/bsp.yml
index 6aaaee4c5b..84eacd9894 100644
--- a/hw/bsp/nrf51dk-16kbram/bsp.yml
+++ b/hw/bsp/nrf51dk-16kbram/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/nrf51dk-16kbram/nrf51xxaa.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf51dk-16kbram/boot-nrf51xxaa.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/nrf51dk-16kbram/split-nrf51dk-16kbram.ld"
bsp.downloadscript: "hw/bsp/nrf51dk-16kbram/nrf51dk-16kbram_download.sh"
bsp.debugscript: "hw/bsp/nrf51dk-16kbram/nrf51dk-16kbram_debug.sh"
diff --git a/hw/bsp/nrf51dk-16kbram/pkg.yml b/hw/bsp/nrf51dk-16kbram/pkg.yml
index a055799294..c05ac24afe 100644
--- a/hw/bsp/nrf51dk-16kbram/pkg.yml
+++ b/hw/bsp/nrf51dk-16kbram/pkg.yml
@@ -30,17 +30,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/nrf51dk-16kbram/syscfg.yml b/hw/bsp/nrf51dk-16kbram/syscfg.yml
index f339cd2f5c..50a8738f4f 100644
--- a/hw/bsp/nrf51dk-16kbram/syscfg.yml
+++ b/hw/bsp/nrf51dk-16kbram/syscfg.yml
@@ -72,6 +72,18 @@ syscfg.defs:
I2C_0_FREQ_KHZ:
description: 'Frequency in khz for I2C_0 bus'
value: 100
+ I2C_0_FREQUENCY:
+ description: 'Use I2C_0_FREQ_KHZ instead'
+ defunct: 1
+ value: 100
+ I2C_0_SDA_PIN:
+ description: 'Use I2C_0_PIN_SDA instead'
+ defunct: 1
+ value: 30
+ I2C_0_SCL_PIN:
+ description: 'Use I2C_0_PIN_SCL instead'
+ defunct: 1
+ value: 7
I2C_1_PIN_SCL:
description: 'SCL pin for I2C_1'
diff --git a/hw/bsp/nrf51dk/bsp.yml b/hw/bsp/nrf51dk/bsp.yml
index 9382824508..f223d4d9da 100644
--- a/hw/bsp/nrf51dk/bsp.yml
+++ b/hw/bsp/nrf51dk/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/nrf51dk/nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf51dk/boot-nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/nrf51dk/split-nrf51dk.ld"
bsp.downloadscript: "hw/bsp/nrf51dk/nrf51dk_download.sh"
bsp.debugscript: "hw/bsp/nrf51dk/nrf51dk_debug.sh"
diff --git a/hw/bsp/nrf51dk/pkg.yml b/hw/bsp/nrf51dk/pkg.yml
index 0165cc61e5..ddb199c96c 100644
--- a/hw/bsp/nrf51dk/pkg.yml
+++ b/hw/bsp/nrf51dk/pkg.yml
@@ -30,17 +30,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/nrf51dk/syscfg.yml b/hw/bsp/nrf51dk/syscfg.yml
index e67737479f..6ef52fc777 100644
--- a/hw/bsp/nrf51dk/syscfg.yml
+++ b/hw/bsp/nrf51dk/syscfg.yml
@@ -72,6 +72,18 @@ syscfg.defs:
I2C_0_FREQ_KHZ:
description: 'Frequency in khz for I2C_0 bus'
value: 100
+ I2C_0_FREQUENCY:
+ description: 'Use I2C_0_FREQ_KHZ instead'
+ defunct: 1
+ value: 100
+ I2C_0_SDA_PIN:
+ description: 'Use I2C_0_PIN_SDA instead'
+ defunct: 1
+ value: 30
+ I2C_0_SCL_PIN:
+ description: 'Use I2C_0_PIN_SCL instead'
+ defunct: 1
+ value: 7
I2C_1_PIN_SCL:
description: 'SCL pin for I2C_1'
diff --git a/hw/bsp/nrf52-thingy/bsp.yml b/hw/bsp/nrf52-thingy/bsp.yml
index 610ceddee1..c5a8ded8b2 100644
--- a/hw/bsp/nrf52-thingy/bsp.yml
+++ b/hw/bsp/nrf52-thingy/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nrf52-thingy/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf52-thingy/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/nrf52-thingy/split-nrf52-thingy.ld"
bsp.downloadscript: "hw/bsp/nrf52-thingy/nrf52-thingy_download.sh"
bsp.debugscript: "hw/bsp/nrf52-thingy/nrf52-thingy_debug.sh"
diff --git a/hw/bsp/nrf52-thingy/pkg.yml b/hw/bsp/nrf52-thingy/pkg.yml
index 4cd7b112df..f613b052d5 100644
--- a/hw/bsp/nrf52-thingy/pkg.yml
+++ b/hw/bsp/nrf52-thingy/pkg.yml
@@ -34,35 +34,35 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
pkg.deps.LIS2DH12_ONB:
- - hw/drivers/sensors/lis2dh12
+ - "@apache-mynewt-core/hw/drivers/sensors/lis2dh12"
pkg.init:
config_lis2dh12_sensor: 400
diff --git a/hw/bsp/nrf52840pdk/bsp.yml b/hw/bsp/nrf52840pdk/bsp.yml
index 950c399f3d..43c572175d 100644
--- a/hw/bsp/nrf52840pdk/bsp.yml
+++ b/hw/bsp/nrf52840pdk/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nrf52840pdk/nrf52840aa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf52840pdk/boot-nrf52840aa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/nrf52840pdk/split-nrf52840pdk.ld"
bsp.downloadscript: "hw/bsp/nrf52840pdk/nrf52840pdk_download.sh"
bsp.debugscript: "hw/bsp/nrf52840pdk/nrf52840pdk_debug.sh"
diff --git a/hw/bsp/nrf52840pdk/pkg.yml b/hw/bsp/nrf52840pdk/pkg.yml
index 09268619fc..6ad0a4e1a8 100644
--- a/hw/bsp/nrf52840pdk/pkg.yml
+++ b/hw/bsp/nrf52840pdk/pkg.yml
@@ -33,36 +33,36 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
- - sys/flash_map
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
+ - "@apache-mynewt-core/sys/flash_map"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.TRNG:
- - hw/drivers/trng/trng_nrf52
+ - "@apache-mynewt-core/hw/drivers/trng/trng_nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_3:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/nrf52dk/bsp.yml b/hw/bsp/nrf52dk/bsp.yml
index 76e154df8f..240b60388a 100644
--- a/hw/bsp/nrf52dk/bsp.yml
+++ b/hw/bsp/nrf52dk/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nrf52dk/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nrf52dk/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/nrf52dk/split-nrf52dk.ld"
bsp.downloadscript: "hw/bsp/nrf52dk/nrf52dk_download.sh"
bsp.debugscript: "hw/bsp/nrf52dk/nrf52dk_debug.sh"
diff --git a/hw/bsp/nrf52dk/pkg.yml b/hw/bsp/nrf52dk/pkg.yml
index c810bfdca9..3f19f9478d 100644
--- a/hw/bsp/nrf52dk/pkg.yml
+++ b/hw/bsp/nrf52dk/pkg.yml
@@ -33,29 +33,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/nucleo-f303k8/bsp.yml b/hw/bsp/nucleo-f303k8/bsp.yml
index 930dde2225..8fe04e6fe0 100644
--- a/hw/bsp/nucleo-f303k8/bsp.yml
+++ b/hw/bsp/nucleo-f303k8/bsp.yml
@@ -21,7 +21,7 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nucleo-f303k8/nucleo-f303k8.ld"
- - "hw/mcu/stm/stm32f3xx/stm32f303.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx/stm32f303.ld"
bsp.downloadscript: "hw/bsp/nucleo-f303k8/nucleo-f303k8_download.sh"
bsp.debugscript: "hw/bsp/nucleo-f303k8/nucleo-f303k8_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-f303k8/nucleo-f303k8_download.cmd"
diff --git a/hw/bsp/nucleo-f303k8/pkg.yml b/hw/bsp/nucleo-f303k8/pkg.yml
index 3be47b4b4e..f4f2669635 100644
--- a/hw/bsp/nucleo-f303k8/pkg.yml
+++ b/hw/bsp/nucleo-f303k8/pkg.yml
@@ -33,21 +33,21 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f3xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
diff --git a/hw/bsp/nucleo-f303re/bsp.yml b/hw/bsp/nucleo-f303re/bsp.yml
index ea60495c05..e0471f0e01 100644
--- a/hw/bsp/nucleo-f303re/bsp.yml
+++ b/hw/bsp/nucleo-f303re/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nucleo-f303re/nucleo-f303re.ld"
- - "hw/mcu/stm/stm32f3xx/stm32f303.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx/stm32f303.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nucleo-f303re/boot-nucleo-f303re.ld"
- - "hw/mcu/stm/stm32f3xx/stm32f303.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx/stm32f303.ld"
bsp.downloadscript: "hw/bsp/nucleo-f303re/nucleo-f303re_download.sh"
bsp.debugscript: "hw/bsp/nucleo-f303re/nucleo-f303re_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-f303re/nucleo-f303re_download.cmd"
diff --git a/hw/bsp/nucleo-f303re/pkg.yml b/hw/bsp/nucleo-f303re/pkg.yml
index ca6f7ea014..9d7aa5f166 100644
--- a/hw/bsp/nucleo-f303re/pkg.yml
+++ b/hw/bsp/nucleo-f303re/pkg.yml
@@ -33,20 +33,20 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f3xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
diff --git a/hw/bsp/nucleo-f401re/bsp.yml b/hw/bsp/nucleo-f401re/bsp.yml
index 4fdd6ce55b..6a08263075 100644
--- a/hw/bsp/nucleo-f401re/bsp.yml
+++ b/hw/bsp/nucleo-f401re/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nucleo-f401re/nucleo-f401re.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f401.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f401.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nucleo-f401re/boot-nucleo-f401re.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f401.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f401.ld"
bsp.downloadscript: "hw/bsp/nucleo-f401re/nucleo-f401re_download.sh"
bsp.debugscript: "hw/bsp/nucleo-f401re/nucleo-f401re_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-f401re/nucleo-f401re_download.cmd"
diff --git a/hw/bsp/nucleo-f401re/pkg.yml b/hw/bsp/nucleo-f401re/pkg.yml
index 4370762deb..11a3f21003 100644
--- a/hw/bsp/nucleo-f401re/pkg.yml
+++ b/hw/bsp/nucleo-f401re/pkg.yml
@@ -34,10 +34,10 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f4xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/nucleo-f413zh/bsp.yml b/hw/bsp/nucleo-f413zh/bsp.yml
index a47c933098..ad779591ba 100644
--- a/hw/bsp/nucleo-f413zh/bsp.yml
+++ b/hw/bsp/nucleo-f413zh/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/nucleo-f413zh/nucleo-f413zh.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f413.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f413.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nucleo-f413zh/boot-nucleo-f413zh.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f413.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f413.ld"
bsp.downloadscript: "hw/bsp/nucleo-f413zh/nucleo-f413zh_download.sh"
bsp.debugscript: "hw/bsp/nucleo-f413zh/nucleo-f413zh_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-f413zh/nucleo-f413zh_download.cmd"
diff --git a/hw/bsp/nucleo-f413zh/pkg.yml b/hw/bsp/nucleo-f413zh/pkg.yml
index e9b959b6fb..5a5b8716d7 100644
--- a/hw/bsp/nucleo-f413zh/pkg.yml
+++ b/hw/bsp/nucleo-f413zh/pkg.yml
@@ -35,8 +35,8 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f4xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/nucleo-f746zg/bsp.yml b/hw/bsp/nucleo-f746zg/bsp.yml
index 2db89b6dec..a1ff9ae950 100644
--- a/hw/bsp/nucleo-f746zg/bsp.yml
+++ b/hw/bsp/nucleo-f746zg/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m7
bsp.compiler: compiler/arm-none-eabi-m7
bsp.linkerscript:
- "hw/bsp/nucleo-f746zg/nucleo-f746zg.ld"
- - "hw/mcu/stm/stm32f7xx/stm32f746.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx/stm32f746.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nucleo-f746zg/boot-nucleo-f746zg.ld"
- - "hw/mcu/stm/stm32f7xx/stm32f746.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx/stm32f746.ld"
bsp.downloadscript: "hw/bsp/nucleo-f746zg/nucleo-f746zg_download.sh"
bsp.debugscript: "hw/bsp/nucleo-f746zg/nucleo-f746zg_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-f746zg/nucleo-f746zg_download.cmd"
diff --git a/hw/bsp/nucleo-f746zg/pkg.yml b/hw/bsp/nucleo-f746zg/pkg.yml
index f204c9e285..627c765b49 100644
--- a/hw/bsp/nucleo-f746zg/pkg.yml
+++ b/hw/bsp/nucleo-f746zg/pkg.yml
@@ -33,20 +33,20 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f7xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.ETH_0:
- - hw/drivers/lwip/stm32_eth
+ - "@apache-mynewt-core/hw/drivers/lwip/stm32_eth"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
diff --git a/hw/bsp/nucleo-f767zi/bsp.yml b/hw/bsp/nucleo-f767zi/bsp.yml
index 65766c94aa..771fbe9ed0 100644
--- a/hw/bsp/nucleo-f767zi/bsp.yml
+++ b/hw/bsp/nucleo-f767zi/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m7
bsp.compiler: compiler/arm-none-eabi-m7
bsp.linkerscript:
- "hw/bsp/nucleo-f767zi/nucleo-f767zi.ld"
- - "hw/mcu/stm/stm32f7xx/stm32f767.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx/stm32f767.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/nucleo-f767zi/boot-nucleo-f767zi.ld"
- - "hw/mcu/stm/stm32f7xx/stm32f767.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx/stm32f767.ld"
bsp.downloadscript: "hw/bsp/nucleo-f767zi/nucleo-f767zi_download.sh"
bsp.debugscript: "hw/bsp/nucleo-f767zi/nucleo-f767zi_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-f767zi/nucleo-f767zi_download.cmd"
diff --git a/hw/bsp/nucleo-f767zi/pkg.yml b/hw/bsp/nucleo-f767zi/pkg.yml
index 71fc4e1c11..339f40bc25 100644
--- a/hw/bsp/nucleo-f767zi/pkg.yml
+++ b/hw/bsp/nucleo-f767zi/pkg.yml
@@ -33,20 +33,20 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f7xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.ETH_0:
- - hw/drivers/lwip/stm32_eth
+ - "@apache-mynewt-core/hw/drivers/lwip/stm32_eth"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
diff --git a/hw/bsp/nucleo-l476rg/boot-nucleo-l476rg.ld b/hw/bsp/nucleo-l476rg/boot-nucleo-l476rg.ld
new file mode 100644
index 0000000000..8e59d8a2f6
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/boot-nucleo-l476rg.ld
@@ -0,0 +1,28 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 16K
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* The bootloader does not contain an image header */
+_imghdr_size = 0x0;
diff --git a/hw/bsp/nucleo-l476rg/bsp.yml b/hw/bsp/nucleo-l476rg/bsp.yml
new file mode 100644
index 0000000000..7552409a4e
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/bsp.yml
@@ -0,0 +1,63 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+bsp.arch: cortex_m4
+bsp.compiler: compiler/arm-none-eabi-m4
+bsp.linkerscript:
+ - "hw/bsp/nucleo-l476rg/nucleo-l476rg.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32l4xx/stm32l476.ld"
+bsp.linkerscript.BOOT_LOADER.OVERWRITE:
+ - "hw/bsp/nucleo-l476rg/boot-nucleo-l476rg.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32l4xx/stm32l476.ld"
+bsp.downloadscript: "hw/bsp/nucleo-l476rg/nucleo-l476rg_download.sh"
+bsp.debugscript: "hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.sh"
+bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-l476rg/nucleo-l476rg_download.cmd"
+bsp.debugscript.WINDOWS.OVERWRITE: "hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.cmd"
+
+bsp.flash_map:
+ areas:
+ # System areas.
+ FLASH_AREA_BOOTLOADER:
+ device: 0
+ offset: 0x08000000
+ size: 16kB
+ FLASH_AREA_IMAGE_0:
+ device: 0
+ offset: 0x08010000
+ size: 464kB
+ FLASH_AREA_IMAGE_1:
+ device: 0
+ offset: 0x08084000
+ size: 464kB
+ FLASH_AREA_IMAGE_SCRATCH:
+ device: 0
+ offset: 0x080f8000
+ size: 32kB
+
+ # User areas.
+ FLASH_AREA_REBOOT_LOG:
+ user_id: 0
+ device: 0
+ offset: 0x08004000
+ size: 32kB
+ FLASH_AREA_NFFS:
+ user_id: 1
+ device: 0
+ offset: 0x0800c000
+ size: 16kB
diff --git a/hw/bsp/nucleo-l476rg/include/bsp/bsp.h b/hw/bsp/nucleo-l476rg/include/bsp/bsp.h
new file mode 100644
index 0000000000..93b3ba0eaf
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/include/bsp/bsp.h
@@ -0,0 +1,51 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_BSP_H
+#define H_BSP_H
+
+#include <inttypes.h>
+#include <mcu/mcu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Define special stack sections */
+#define sec_data_core __attribute__((section(".data.core")))
+#define sec_bss_core __attribute__((section(".bss.core")))
+#define sec_bss_nz_core __attribute__((section(".bss.core.nz")))
+
+/* More convenient section placement macros. */
+#define bssnz_t sec_bss_nz_core
+
+extern uint8_t _ram_start;
+
+#define RAM_SIZE (96 * 1024)
+
+/* LED pins */
+#define LED_BLINK_PIN MCU_GPIO_PORTA(5)
+
+/* UART */
+#define UART_CNT 1
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* H_BSP_H */
diff --git a/hw/bsp/nucleo-l476rg/include/bsp/stm32l4xx_hal_conf.h b/hw/bsp/nucleo-l476rg/include/bsp/stm32l4xx_hal_conf.h
new file mode 100644
index 0000000000..c7134949e3
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/include/bsp/stm32l4xx_hal_conf.h
@@ -0,0 +1,388 @@
+/**
+ ******************************************************************************
+ * @file stm32l4xx_hal_conf.h
+ * @author MCD Application Team
+ * @brief HAL configuration template file.
+ * This file should be copied to the application folder and renamed
+ * to stm32l4xx_hal_conf.h.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32L4xx_HAL_CONF_H
+#define __STM32L4xx_HAL_CONF_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* ########################## Module Selection ############################## */
+/**
+ * @brief This is the list of modules to be used in the HAL driver
+ */
+#if 0
+#define HAL_ADC_MODULE_ENABLED
+#define HAL_CAN_MODULE_ENABLED
+/* #define HAL_CAN_LEGACY_MODULE_ENABLED */
+#define HAL_COMP_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_CRC_MODULE_ENABLED
+#define HAL_CRYP_MODULE_ENABLED
+#define HAL_DAC_MODULE_ENABLED
+#define HAL_DFSDM_MODULE_ENABLED
+#define HAL_FIREWALL_MODULE_ENABLED
+#define HAL_HCD_MODULE_ENABLED
+#define HAL_NAND_MODULE_ENABLED
+#define HAL_NOR_MODULE_ENABLED
+#define HAL_SRAM_MODULE_ENABLED
+#define HAL_IRDA_MODULE_ENABLED
+#define HAL_LCD_MODULE_ENABLED
+#define HAL_LPTIM_MODULE_ENABLED
+#define HAL_OPAMP_MODULE_ENABLED
+#define HAL_PCD_MODULE_ENABLED
+#define HAL_QSPI_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_RNG_MODULE_ENABLED
+#define HAL_RTC_MODULE_ENABLED
+#define HAL_SAI_MODULE_ENABLED
+#define HAL_SD_MODULE_ENABLED
+#define HAL_SMARTCARD_MODULE_ENABLED
+#define HAL_SMBUS_MODULE_ENABLED
+#define HAL_SWPMI_MODULE_ENABLED
+#define HAL_TSC_MODULE_ENABLED
+#define HAL_UART_MODULE_ENABLED
+#define HAL_USART_MODULE_ENABLED
+#define HAL_WWDG_MODULE_ENABLED
+#endif
+
+#define HAL_MODULE_ENABLED
+#define HAL_CORTEX_MODULE_ENABLED
+#define HAL_GPIO_MODULE_ENABLED
+#define HAL_RCC_MODULE_ENABLED
+#define HAL_PWR_MODULE_ENABLED
+#define HAL_FLASH_MODULE_ENABLED
+#define HAL_IWDG_MODULE_ENABLED
+#define HAL_DMA_MODULE_ENABLED
+#define HAL_I2C_MODULE_ENABLED
+#define HAL_SPI_MODULE_ENABLED
+#define HAL_TIM_MODULE_ENABLED
+
+/* ########################## Oscillator Values adaptation ####################*/
+/**
+ * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSE is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (HSE_STARTUP_TIMEOUT)
+ #define HSE_STARTUP_TIMEOUT 100U /*!< Time out for HSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief Internal Multiple Speed oscillator (MSI) default value.
+ * This value is the default MSI range value after Reset.
+ */
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+/**
+ * @brief Internal High Speed oscillator (HSI) value.
+ * This value is used by the RCC HAL module to compute the system frequency
+ * (when HSI is used as system clock source, directly or through the PLL).
+ */
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @brief Internal Low Speed oscillator (LSI) value.
+ */
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE 32000U /*!< LSI Typical Value in Hz*/
+#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
+ The real value may vary depending on the variations
+ in voltage and temperature.*/
+/**
+ * @brief External Low Speed oscillator (LSE) value.
+ * This value is used by the UART, RTC HAL module to compute the system frequency
+ */
+#if !defined (LSE_VALUE)
+ #define LSE_VALUE 32768U /*!< Value of the External oscillator in Hz*/
+#endif /* LSE_VALUE */
+
+#if !defined (LSE_STARTUP_TIMEOUT)
+ #define LSE_STARTUP_TIMEOUT 5000U /*!< Time out for LSE start up, in ms */
+#endif /* HSE_STARTUP_TIMEOUT */
+
+/**
+ * @brief External clock source for SAI1 peripheral
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_SAI1_CLOCK_VALUE)
+ #define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1 External clock source in Hz*/
+#endif /* EXTERNAL_SAI1_CLOCK_VALUE */
+
+/**
+ * @brief External clock source for SAI2 peripheral
+ * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source
+ * frequency.
+ */
+#if !defined (EXTERNAL_SAI2_CLOCK_VALUE)
+ #define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2 External clock source in Hz*/
+#endif /* EXTERNAL_SAI2_CLOCK_VALUE */
+
+/* Tip: To avoid modifying this file each time you need to use different HSE,
+ === you can define the HSE value in your toolchain compiler preprocessor. */
+
+/* ########################### System Configuration ######################### */
+/**
+ * @brief This is the HAL system configuration section
+ */
+#define VDD_VALUE 3300U /*!< Value of VDD in mv */
+#define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */
+#define USE_RTOS 0U
+#define PREFETCH_ENABLE 0U
+#define INSTRUCTION_CACHE_ENABLE 1U
+#define DATA_CACHE_ENABLE 1U
+
+/* ########################## Assert Selection ############################## */
+/**
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * HAL drivers code
+ */
+/* #define USE_FULL_ASSERT 1U */
+
+/* ################## SPI peripheral configuration ########################## */
+
+/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver
+ * Activated: CRC code is present inside driver
+ * Deactivated: CRC code cleaned from driver
+ */
+
+#define USE_SPI_CRC 1U
+
+/* Includes ------------------------------------------------------------------*/
+/**
+ * @brief Include module's header file
+ */
+
+#ifdef HAL_RCC_MODULE_ENABLED
+ #include "stm32l4xx_hal_rcc.h"
+#endif /* HAL_RCC_MODULE_ENABLED */
+
+#ifdef HAL_GPIO_MODULE_ENABLED
+ #include "stm32l4xx_hal_gpio.h"
+#endif /* HAL_GPIO_MODULE_ENABLED */
+
+#ifdef HAL_DMA_MODULE_ENABLED
+ #include "stm32l4xx_hal_dma.h"
+#endif /* HAL_DMA_MODULE_ENABLED */
+
+#ifdef HAL_DFSDM_MODULE_ENABLED
+ #include "stm32l4xx_hal_dfsdm.h"
+#endif /* HAL_DFSDM_MODULE_ENABLED */
+
+#ifdef HAL_CORTEX_MODULE_ENABLED
+ #include "stm32l4xx_hal_cortex.h"
+#endif /* HAL_CORTEX_MODULE_ENABLED */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+ #include "stm32l4xx_hal_adc.h"
+#endif /* HAL_ADC_MODULE_ENABLED */
+
+#ifdef HAL_CAN_MODULE_ENABLED
+ #include "stm32l4xx_hal_can.h"
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #include "Legacy/stm32l4xx_hal_can_legacy.h"
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+ #include "stm32l4xx_hal_comp.h"
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+#ifdef HAL_CRC_MODULE_ENABLED
+ #include "stm32l4xx_hal_crc.h"
+#endif /* HAL_CRC_MODULE_ENABLED */
+
+#ifdef HAL_CRYP_MODULE_ENABLED
+ #include "stm32l4xx_hal_cryp.h"
+#endif /* HAL_CRYP_MODULE_ENABLED */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+ #include "stm32l4xx_hal_dac.h"
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+#ifdef HAL_FIREWALL_MODULE_ENABLED
+ #include "stm32l4xx_hal_firewall.h"
+#endif /* HAL_FIREWALL_MODULE_ENABLED */
+
+#ifdef HAL_FLASH_MODULE_ENABLED
+ #include "stm32l4xx_hal_flash.h"
+#endif /* HAL_FLASH_MODULE_ENABLED */
+
+#ifdef HAL_SRAM_MODULE_ENABLED
+ #include "stm32l4xx_hal_sram.h"
+#endif /* HAL_SRAM_MODULE_ENABLED */
+
+#ifdef HAL_NOR_MODULE_ENABLED
+ #include "stm32l4xx_hal_nor.h"
+#endif /* HAL_NOR_MODULE_ENABLED */
+
+#ifdef HAL_NAND_MODULE_ENABLED
+ #include "stm32l4xx_hal_nand.h"
+#endif /* HAL_NAND_MODULE_ENABLED */
+
+#ifdef HAL_I2C_MODULE_ENABLED
+ #include "stm32l4xx_hal_i2c.h"
+#endif /* HAL_I2C_MODULE_ENABLED */
+
+#ifdef HAL_IWDG_MODULE_ENABLED
+ #include "stm32l4xx_hal_iwdg.h"
+#endif /* HAL_IWDG_MODULE_ENABLED */
+
+#ifdef HAL_LCD_MODULE_ENABLED
+ #include "stm32l4xx_hal_lcd.h"
+#endif /* HAL_LCD_MODULE_ENABLED */
+
+#ifdef HAL_LPTIM_MODULE_ENABLED
+#include "stm32l4xx_hal_lptim.h"
+#endif /* HAL_LPTIM_MODULE_ENABLED */
+
+#ifdef HAL_OPAMP_MODULE_ENABLED
+#include "stm32l4xx_hal_opamp.h"
+#endif /* HAL_OPAMP_MODULE_ENABLED */
+
+#ifdef HAL_PWR_MODULE_ENABLED
+ #include "stm32l4xx_hal_pwr.h"
+#endif /* HAL_PWR_MODULE_ENABLED */
+
+#ifdef HAL_QSPI_MODULE_ENABLED
+ #include "stm32l4xx_hal_qspi.h"
+#endif /* HAL_QSPI_MODULE_ENABLED */
+
+#ifdef HAL_RNG_MODULE_ENABLED
+ #include "stm32l4xx_hal_rng.h"
+#endif /* HAL_RNG_MODULE_ENABLED */
+
+#ifdef HAL_RTC_MODULE_ENABLED
+ #include "stm32l4xx_hal_rtc.h"
+#endif /* HAL_RTC_MODULE_ENABLED */
+
+#ifdef HAL_SAI_MODULE_ENABLED
+ #include "stm32l4xx_hal_sai.h"
+#endif /* HAL_SAI_MODULE_ENABLED */
+
+#ifdef HAL_SD_MODULE_ENABLED
+ #include "stm32l4xx_hal_sd.h"
+#endif /* HAL_SD_MODULE_ENABLED */
+
+#ifdef HAL_SMBUS_MODULE_ENABLED
+ #include "stm32l4xx_hal_smbus.h"
+#endif /* HAL_SMBUS_MODULE_ENABLED */
+
+#ifdef HAL_SPI_MODULE_ENABLED
+ #include "stm32l4xx_hal_spi.h"
+#endif /* HAL_SPI_MODULE_ENABLED */
+
+#ifdef HAL_SWPMI_MODULE_ENABLED
+ #include "stm32l4xx_hal_swpmi.h"
+#endif /* HAL_SWPMI_MODULE_ENABLED */
+
+#ifdef HAL_TIM_MODULE_ENABLED
+ #include "stm32l4xx_hal_tim.h"
+#endif /* HAL_TIM_MODULE_ENABLED */
+
+#ifdef HAL_TSC_MODULE_ENABLED
+ #include "stm32l4xx_hal_tsc.h"
+#endif /* HAL_TSC_MODULE_ENABLED */
+
+#ifdef HAL_UART_MODULE_ENABLED
+ #include "stm32l4xx_hal_uart.h"
+#endif /* HAL_UART_MODULE_ENABLED */
+
+#ifdef HAL_USART_MODULE_ENABLED
+ #include "stm32l4xx_hal_usart.h"
+#endif /* HAL_USART_MODULE_ENABLED */
+
+#ifdef HAL_IRDA_MODULE_ENABLED
+ #include "stm32l4xx_hal_irda.h"
+#endif /* HAL_IRDA_MODULE_ENABLED */
+
+#ifdef HAL_SMARTCARD_MODULE_ENABLED
+ #include "stm32l4xx_hal_smartcard.h"
+#endif /* HAL_SMARTCARD_MODULE_ENABLED */
+
+#ifdef HAL_WWDG_MODULE_ENABLED
+ #include "stm32l4xx_hal_wwdg.h"
+#endif /* HAL_WWDG_MODULE_ENABLED */
+
+#ifdef HAL_PCD_MODULE_ENABLED
+ #include "stm32l4xx_hal_pcd.h"
+#endif /* HAL_PCD_MODULE_ENABLED */
+
+#ifdef HAL_HCD_MODULE_ENABLED
+ #include "stm32l4xx_hal_hcd.h"
+#endif /* HAL_HCD_MODULE_ENABLED */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef USE_FULL_ASSERT
+/**
+ * @brief The assert_param macro is used for function's parameters check.
+ * @param expr: If expr is false, it calls assert_failed function
+ * which reports the name of the source file and the source
+ * line number of the call that failed.
+ * If expr is true, it returns no value.
+ * @retval None
+ */
+ #define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+ void assert_failed(char *file, uint32_t line);
+#else
+ #define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32L4xx_HAL_CONF_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-l476rg/nucleo-l476rg.ld b/hw/bsp/nucleo-l476rg/nucleo-l476rg.ld
new file mode 100644
index 0000000000..512d498844
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/nucleo-l476rg.ld
@@ -0,0 +1,28 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* Linker script to configure memory regions. */
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 464K /* First image slot. */
+ RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
+}
+
+/* This linker script is used for images and thus contains an image header */
+_imghdr_size = 0x20;
diff --git a/hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.cmd b/hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.cmd
new file mode 100755
index 0000000000..96f0b26050
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.cmd
@@ -0,0 +1,22 @@
+@rem
+@rem Licensed to the Apache Software Foundation (ASF) under one
+@rem or more contributor license agreements. See the NOTICE file
+@rem distributed with this work for additional information
+@rem regarding copyright ownership. The ASF licenses this file
+@rem to you under the Apache License, Version 2.0 (the
+@rem "License"); you may not use this file except in compliance
+@rem with the License. You may obtain a copy of the License at
+@rem
+@rem http://www.apache.org/licenses/LICENSE-2.0
+@rem
+@rem Unless required by applicable law or agreed to in writing,
+@rem software distributed under the License is distributed on an
+@rem "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+@rem KIND, either express or implied. See the License for the
+@rem specific language governing permissions and limitations
+@rem under the License.
+@rem
+
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"
diff --git a/hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.sh b/hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.sh
new file mode 100755
index 0000000000..f51452334a
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/nucleo-l476rg_debug.sh
@@ -0,0 +1,37 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - RESET set if target should be reset when attaching
+# - NO_GDB set if we should not start gdb to debug
+#
+. $CORE_PATH/hw/scripts/openocd.sh
+
+FILE_NAME=$BIN_BASENAME.elf
+CFG="-f board/st_nucleo_l4.cfg"
+# Exit openocd when gdb detaches.
+EXTRA_JTAG_CMD="$EXTRA_JTAG_CMD; stm32l4x.cpu configure -event gdb-detach {if {[stm32l4x.cpu curstate] eq \"halted\"} resume;shutdown}"
+
+openocd_debug
diff --git a/hw/bsp/nucleo-l476rg/nucleo-l476rg_download.cmd b/hw/bsp/nucleo-l476rg/nucleo-l476rg_download.cmd
new file mode 100755
index 0000000000..96f0b26050
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/nucleo-l476rg_download.cmd
@@ -0,0 +1,22 @@
+@rem
+@rem Licensed to the Apache Software Foundation (ASF) under one
+@rem or more contributor license agreements. See the NOTICE file
+@rem distributed with this work for additional information
+@rem regarding copyright ownership. The ASF licenses this file
+@rem to you under the Apache License, Version 2.0 (the
+@rem "License"); you may not use this file except in compliance
+@rem with the License. You may obtain a copy of the License at
+@rem
+@rem http://www.apache.org/licenses/LICENSE-2.0
+@rem
+@rem Unless required by applicable law or agreed to in writing,
+@rem software distributed under the License is distributed on an
+@rem "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+@rem KIND, either express or implied. See the License for the
+@rem specific language governing permissions and limitations
+@rem under the License.
+@rem
+
+@rem Execute a shell with a script of the same name and .sh extension
+
+@bash "%~dp0%~n0.sh"
diff --git a/hw/bsp/nucleo-l476rg/nucleo-l476rg_download.sh b/hw/bsp/nucleo-l476rg/nucleo-l476rg_download.sh
new file mode 100755
index 0000000000..820c90be37
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/nucleo-l476rg_download.sh
@@ -0,0 +1,42 @@
+#!/bin/sh
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+# Called with following variables set:
+# - CORE_PATH is absolute path to @apache-mynewt-core
+# - BSP_PATH is absolute path to hw/bsp/bsp_name
+# - BIN_BASENAME is the path to prefix to target binary,
+# .elf appended to name is the ELF file
+# - IMAGE_SLOT is the image slot to download to (for non-mfg-image, non-boot)
+# - FEATURES holds the target features string
+# - EXTRA_JTAG_CMD holds extra parameters to pass to jtag software
+# - MFG_IMAGE is "1" if this is a manufacturing image
+# - FLASH_OFFSET contains the flash offset to download to
+# - BOOT_LOADER is set if downloading a bootloader
+
+. $CORE_PATH/hw/scripts/openocd.sh
+
+CFG="-f board/st_nucleo_l4.cfg"
+
+if [ "$MFG_IMAGE" ]; then
+ FLASH_OFFSET=0x08000000
+fi
+
+common_file_to_load
+openocd_load
+openocd_reset_run
diff --git a/hw/bsp/nucleo-l476rg/pkg.yml b/hw/bsp/nucleo-l476rg/pkg.yml
new file mode 100644
index 0000000000..42e6795bbd
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/pkg.yml
@@ -0,0 +1,43 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/nucleo-l476rg
+pkg.type: bsp
+pkg.description: BSP definition for the Nucleo stm32l476rg board
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - stm32
+ - stm32l4
+ - nucleo
+
+pkg.cflags:
+ - -DSTM32L476xx
+
+pkg.cflags.HARDFLOAT:
+ - -mfloat-abi=hard -mfpu=fpv4-sp-d16
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/mcu/stm/stm32l4xx"
+ - "@apache-mynewt-core/libc/baselibc"
+
+pkg.deps.UART_0:
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
+pkg.deps.UART_1:
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/nucleo-l476rg/src/arch/cortex_m4/startup_stm32l476xx.s b/hw/bsp/nucleo-l476rg/src/arch/cortex_m4/startup_stm32l476xx.s
new file mode 100644
index 0000000000..f37f643614
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/src/arch/cortex_m4/startup_stm32l476xx.s
@@ -0,0 +1,538 @@
+/**
+ ******************************************************************************
+ * @file startup_stm32l476xx.s
+ * @author MCD Application Team
+ * @brief STM32L476xx devices vector table GCC toolchain.
+ * This module performs:
+ * - Set the initial SP
+ * - Set the initial PC == Reset_Handler,
+ * - Set the vector table entries with the exceptions ISR address,
+ * - Configure the clock system
+ * - Branches to main in the C library (which eventually
+ * calls main()).
+ * After Reset the Cortex-M4 processor is in Thread mode,
+ * priority is Privileged, and the Stack is set to Main.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+ .syntax unified
+ .cpu cortex-m4
+ .fpu softvfp
+ .thumb
+
+.global g_pfnVectors
+.global Default_Handler
+
+/* start address for the initialization values of the .data section.
+defined in linker script */
+.word _sidata
+/* start address for the .data section. defined in linker script */
+.word _sdata
+/* end address for the .data section. defined in linker script */
+.word _edata
+/* start address for the .bss section. defined in linker script */
+.word _sbss
+/* end address for the .bss section. defined in linker script */
+.word _ebss
+
+.equ BootRAM, 0xF1E0F85F
+/**
+ * @brief This is the code that gets called when the processor first
+ * starts execution following a reset event. Only the absolutely
+ * necessary set is performed, after which the application
+ * supplied main() routine is called.
+ * @param None
+ * @retval : None
+*/
+
+ .section .text.Reset_Handler
+ .weak Reset_Handler
+ .type Reset_Handler, %function
+Reset_Handler:
+ ldr sp, =_estack /* Atollic update: set stack pointer */
+
+/* Copy the data segment initializers from flash to SRAM */
+ movs r1, #0
+ b LoopCopyDataInit
+
+CopyDataInit:
+ ldr r3, =_sidata
+ ldr r3, [r3, r1]
+ str r3, [r0, r1]
+ adds r1, r1, #4
+
+LoopCopyDataInit:
+ ldr r0, =_sdata
+ ldr r3, =_edata
+ adds r2, r0, r1
+ cmp r2, r3
+ bcc CopyDataInit
+
+ ldr r2, =_sbss
+ b LoopFillZerobss
+
+/* Zero fill the bss segment. */
+FillZerobss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZerobss:
+ ldr r3, = _ebss
+ cmp r2, r3
+ bcc FillZerobss
+
+/*
+ * mynewt specific corebss clearing.
+ */
+ ldr r2, =__corebss_start__
+ b LoopFillZeroCoreBss
+
+/* Zero fill the bss segment. */
+FillZeroCoreBss:
+ movs r3, #0
+ str r3, [r2], #4
+
+LoopFillZeroCoreBss:
+ ldr r3, =__corebss_end__
+ cmp r2, r3
+ bcc FillZeroCoreBss
+
+/* Call the clock system initialization function.*/
+ bl SystemInit
+/* Call the libc entry point.*/
+ bl _start
+.size Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief This is the code that gets called when the processor receives an
+ * unexpected interrupt. This simply enters an infinite loop, preserving
+ * the system state for examination by a debugger.
+ *
+ * @param None
+ * @retval : None
+*/
+ .section .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+ b Infinite_Loop
+ .size Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex-M4. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+*
+******************************************************************************/
+ .section .isr_vector,"a",%progbits
+ .type g_pfnVectors, %object
+ .size g_pfnVectors, .-g_pfnVectors
+
+
+g_pfnVectors:
+ .globl __isr_vector
+__isr_vector:
+ .word _estack
+ .word Reset_Handler
+ .word NMI_Handler
+ .word HardFault_Handler
+ .word MemManage_Handler
+ .word BusFault_Handler
+ .word UsageFault_Handler
+ .word 0
+ .word 0
+ .word 0
+ .word 0
+ .word SVC_Handler
+ .word DebugMon_Handler
+ .word 0
+ .word PendSV_Handler
+ .word SysTick_Handler
+ .word WWDG_IRQHandler
+ .word PVD_PVM_IRQHandler
+ .word TAMP_STAMP_IRQHandler
+ .word RTC_WKUP_IRQHandler
+ .word FLASH_IRQHandler
+ .word RCC_IRQHandler
+ .word EXTI0_IRQHandler
+ .word EXTI1_IRQHandler
+ .word EXTI2_IRQHandler
+ .word EXTI3_IRQHandler
+ .word EXTI4_IRQHandler
+ .word DMA1_Channel1_IRQHandler
+ .word DMA1_Channel2_IRQHandler
+ .word DMA1_Channel3_IRQHandler
+ .word DMA1_Channel4_IRQHandler
+ .word DMA1_Channel5_IRQHandler
+ .word DMA1_Channel6_IRQHandler
+ .word DMA1_Channel7_IRQHandler
+ .word ADC1_2_IRQHandler
+ .word CAN1_TX_IRQHandler
+ .word CAN1_RX0_IRQHandler
+ .word CAN1_RX1_IRQHandler
+ .word CAN1_SCE_IRQHandler
+ .word EXTI9_5_IRQHandler
+ .word TIM1_BRK_TIM15_IRQHandler
+ .word TIM1_UP_TIM16_IRQHandler
+ .word TIM1_TRG_COM_TIM17_IRQHandler
+ .word TIM1_CC_IRQHandler
+ .word TIM2_IRQHandler
+ .word TIM3_IRQHandler
+ .word TIM4_IRQHandler
+ .word I2C1_EV_IRQHandler
+ .word I2C1_ER_IRQHandler
+ .word I2C2_EV_IRQHandler
+ .word I2C2_ER_IRQHandler
+ .word SPI1_IRQHandler
+ .word SPI2_IRQHandler
+ .word USART1_IRQHandler
+ .word USART2_IRQHandler
+ .word USART3_IRQHandler
+ .word EXTI15_10_IRQHandler
+ .word RTC_Alarm_IRQHandler
+ .word DFSDM1_FLT3_IRQHandler
+ .word TIM8_BRK_IRQHandler
+ .word TIM8_UP_IRQHandler
+ .word TIM8_TRG_COM_IRQHandler
+ .word TIM8_CC_IRQHandler
+ .word ADC3_IRQHandler
+ .word FMC_IRQHandler
+ .word SDMMC1_IRQHandler
+ .word TIM5_IRQHandler
+ .word SPI3_IRQHandler
+ .word UART4_IRQHandler
+ .word UART5_IRQHandler
+ .word TIM6_DAC_IRQHandler
+ .word TIM7_IRQHandler
+ .word DMA2_Channel1_IRQHandler
+ .word DMA2_Channel2_IRQHandler
+ .word DMA2_Channel3_IRQHandler
+ .word DMA2_Channel4_IRQHandler
+ .word DMA2_Channel5_IRQHandler
+ .word DFSDM1_FLT0_IRQHandler
+ .word DFSDM1_FLT1_IRQHandler
+ .word DFSDM1_FLT2_IRQHandler
+ .word COMP_IRQHandler
+ .word LPTIM1_IRQHandler
+ .word LPTIM2_IRQHandler
+ .word OTG_FS_IRQHandler
+ .word DMA2_Channel6_IRQHandler
+ .word DMA2_Channel7_IRQHandler
+ .word LPUART1_IRQHandler
+ .word QUADSPI_IRQHandler
+ .word I2C3_EV_IRQHandler
+ .word I2C3_ER_IRQHandler
+ .word SAI1_IRQHandler
+ .word SAI2_IRQHandler
+ .word SWPMI1_IRQHandler
+ .word TSC_IRQHandler
+ .word LCD_IRQHandler
+ .word 0
+ .word RNG_IRQHandler
+ .word FPU_IRQHandler
+
+
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler.
+* As they are weak aliases, any function with the same name will override
+* this definition.
+*
+*******************************************************************************/
+
+ .weak NMI_Handler
+ .thumb_set NMI_Handler,Default_Handler
+
+ .weak HardFault_Handler
+ .thumb_set HardFault_Handler,Default_Handler
+
+ .weak MemManage_Handler
+ .thumb_set MemManage_Handler,Default_Handler
+
+ .weak BusFault_Handler
+ .thumb_set BusFault_Handler,Default_Handler
+
+ .weak UsageFault_Handler
+ .thumb_set UsageFault_Handler,Default_Handler
+
+ .weak SVC_Handler
+ .thumb_set SVC_Handler,Default_Handler
+
+ .weak DebugMon_Handler
+ .thumb_set DebugMon_Handler,Default_Handler
+
+ .weak PendSV_Handler
+ .thumb_set PendSV_Handler,Default_Handler
+
+ .weak SysTick_Handler
+ .thumb_set SysTick_Handler,Default_Handler
+
+ .weak WWDG_IRQHandler
+ .thumb_set WWDG_IRQHandler,Default_Handler
+
+ .weak PVD_PVM_IRQHandler
+ .thumb_set PVD_PVM_IRQHandler,Default_Handler
+
+ .weak TAMP_STAMP_IRQHandler
+ .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+
+ .weak RTC_WKUP_IRQHandler
+ .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+
+ .weak FLASH_IRQHandler
+ .thumb_set FLASH_IRQHandler,Default_Handler
+
+ .weak RCC_IRQHandler
+ .thumb_set RCC_IRQHandler,Default_Handler
+
+ .weak EXTI0_IRQHandler
+ .thumb_set EXTI0_IRQHandler,Default_Handler
+
+ .weak EXTI1_IRQHandler
+ .thumb_set EXTI1_IRQHandler,Default_Handler
+
+ .weak EXTI2_IRQHandler
+ .thumb_set EXTI2_IRQHandler,Default_Handler
+
+ .weak EXTI3_IRQHandler
+ .thumb_set EXTI3_IRQHandler,Default_Handler
+
+ .weak EXTI4_IRQHandler
+ .thumb_set EXTI4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel1_IRQHandler
+ .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel2_IRQHandler
+ .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel3_IRQHandler
+ .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel4_IRQHandler
+ .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel5_IRQHandler
+ .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel6_IRQHandler
+ .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA1_Channel7_IRQHandler
+ .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
+
+ .weak ADC1_2_IRQHandler
+ .thumb_set ADC1_2_IRQHandler,Default_Handler
+
+ .weak CAN1_TX_IRQHandler
+ .thumb_set CAN1_TX_IRQHandler,Default_Handler
+
+ .weak CAN1_RX0_IRQHandler
+ .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+
+ .weak CAN1_RX1_IRQHandler
+ .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+
+ .weak CAN1_SCE_IRQHandler
+ .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+
+ .weak EXTI9_5_IRQHandler
+ .thumb_set EXTI9_5_IRQHandler,Default_Handler
+
+ .weak TIM1_BRK_TIM15_IRQHandler
+ .thumb_set TIM1_BRK_TIM15_IRQHandler,Default_Handler
+
+ .weak TIM1_UP_TIM16_IRQHandler
+ .thumb_set TIM1_UP_TIM16_IRQHandler,Default_Handler
+
+ .weak TIM1_TRG_COM_TIM17_IRQHandler
+ .thumb_set TIM1_TRG_COM_TIM17_IRQHandler,Default_Handler
+
+ .weak TIM1_CC_IRQHandler
+ .thumb_set TIM1_CC_IRQHandler,Default_Handler
+
+ .weak TIM2_IRQHandler
+ .thumb_set TIM2_IRQHandler,Default_Handler
+
+ .weak TIM3_IRQHandler
+ .thumb_set TIM3_IRQHandler,Default_Handler
+
+ .weak TIM4_IRQHandler
+ .thumb_set TIM4_IRQHandler,Default_Handler
+
+ .weak I2C1_EV_IRQHandler
+ .thumb_set I2C1_EV_IRQHandler,Default_Handler
+
+ .weak I2C1_ER_IRQHandler
+ .thumb_set I2C1_ER_IRQHandler,Default_Handler
+
+ .weak I2C2_EV_IRQHandler
+ .thumb_set I2C2_EV_IRQHandler,Default_Handler
+
+ .weak I2C2_ER_IRQHandler
+ .thumb_set I2C2_ER_IRQHandler,Default_Handler
+
+ .weak SPI1_IRQHandler
+ .thumb_set SPI1_IRQHandler,Default_Handler
+
+ .weak SPI2_IRQHandler
+ .thumb_set SPI2_IRQHandler,Default_Handler
+
+ .weak USART1_IRQHandler
+ .thumb_set USART1_IRQHandler,Default_Handler
+
+ .weak USART2_IRQHandler
+ .thumb_set USART2_IRQHandler,Default_Handler
+
+ .weak USART3_IRQHandler
+ .thumb_set USART3_IRQHandler,Default_Handler
+
+ .weak EXTI15_10_IRQHandler
+ .thumb_set EXTI15_10_IRQHandler,Default_Handler
+
+ .weak RTC_Alarm_IRQHandler
+ .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT3_IRQHandler
+ .thumb_set DFSDM1_FLT3_IRQHandler,Default_Handler
+
+ .weak TIM8_BRK_IRQHandler
+ .thumb_set TIM8_BRK_IRQHandler,Default_Handler
+
+ .weak TIM8_UP_IRQHandler
+ .thumb_set TIM8_UP_IRQHandler,Default_Handler
+
+ .weak TIM8_TRG_COM_IRQHandler
+ .thumb_set TIM8_TRG_COM_IRQHandler,Default_Handler
+
+ .weak TIM8_CC_IRQHandler
+ .thumb_set TIM8_CC_IRQHandler,Default_Handler
+
+ .weak ADC3_IRQHandler
+ .thumb_set ADC3_IRQHandler,Default_Handler
+
+ .weak FMC_IRQHandler
+ .thumb_set FMC_IRQHandler,Default_Handler
+
+ .weak SDMMC1_IRQHandler
+ .thumb_set SDMMC1_IRQHandler,Default_Handler
+
+ .weak TIM5_IRQHandler
+ .thumb_set TIM5_IRQHandler,Default_Handler
+
+ .weak SPI3_IRQHandler
+ .thumb_set SPI3_IRQHandler,Default_Handler
+
+ .weak UART4_IRQHandler
+ .thumb_set UART4_IRQHandler,Default_Handler
+
+ .weak UART5_IRQHandler
+ .thumb_set UART5_IRQHandler,Default_Handler
+
+ .weak TIM6_DAC_IRQHandler
+ .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+
+ .weak TIM7_IRQHandler
+ .thumb_set TIM7_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel1_IRQHandler
+ .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel2_IRQHandler
+ .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel3_IRQHandler
+ .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel4_IRQHandler
+ .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel5_IRQHandler
+ .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT0_IRQHandler
+ .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT1_IRQHandler
+ .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler
+
+ .weak DFSDM1_FLT2_IRQHandler
+ .thumb_set DFSDM1_FLT2_IRQHandler,Default_Handler
+
+ .weak COMP_IRQHandler
+ .thumb_set COMP_IRQHandler,Default_Handler
+
+ .weak LPTIM1_IRQHandler
+ .thumb_set LPTIM1_IRQHandler,Default_Handler
+
+ .weak LPTIM2_IRQHandler
+ .thumb_set LPTIM2_IRQHandler,Default_Handler
+
+ .weak OTG_FS_IRQHandler
+ .thumb_set OTG_FS_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel6_IRQHandler
+ .thumb_set DMA2_Channel6_IRQHandler,Default_Handler
+
+ .weak DMA2_Channel7_IRQHandler
+ .thumb_set DMA2_Channel7_IRQHandler,Default_Handler
+
+ .weak LPUART1_IRQHandler
+ .thumb_set LPUART1_IRQHandler,Default_Handler
+
+ .weak QUADSPI_IRQHandler
+ .thumb_set QUADSPI_IRQHandler,Default_Handler
+
+ .weak I2C3_EV_IRQHandler
+ .thumb_set I2C3_EV_IRQHandler,Default_Handler
+
+ .weak I2C3_ER_IRQHandler
+ .thumb_set I2C3_ER_IRQHandler,Default_Handler
+
+ .weak SAI1_IRQHandler
+ .thumb_set SAI1_IRQHandler,Default_Handler
+
+ .weak SAI2_IRQHandler
+ .thumb_set SAI2_IRQHandler,Default_Handler
+
+ .weak SWPMI1_IRQHandler
+ .thumb_set SWPMI1_IRQHandler,Default_Handler
+
+ .weak TSC_IRQHandler
+ .thumb_set TSC_IRQHandler,Default_Handler
+
+ .weak LCD_IRQHandler
+ .thumb_set LCD_IRQHandler,Default_Handler
+
+ .weak RNG_IRQHandler
+ .thumb_set RNG_IRQHandler,Default_Handler
+
+ .weak FPU_IRQHandler
+ .thumb_set FPU_IRQHandler,Default_Handler
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-l476rg/src/hal_bsp.c b/hw/bsp/nucleo-l476rg/src/hal_bsp.c
new file mode 100644
index 0000000000..c90aed1481
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/src/hal_bsp.c
@@ -0,0 +1,177 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#if MYNEWT_VAL(UART_0)
+#include <uart/uart.h>
+#include <uart_hal/uart_hal.h>
+#endif
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_flash_int.h>
+#include <hal/hal_timer.h>
+
+#if MYNEWT_VAL(SPI_0_MASTER) || MYNEWT_VAL(SPI_0_SLAVE)
+#include <hal/hal_spi.h>
+#endif
+
+#include <stm32l476xx.h>
+#include <stm32l4xx_hal_rcc.h>
+#include <stm32l4xx_hal_pwr.h>
+#include <stm32l4xx_hal_flash.h>
+#include <stm32l4xx_hal_gpio_ex.h>
+#include <mcu/stm32l4_bsp.h>
+#include "mcu/stm32l4xx_mynewt_hal.h"
+#include "mcu/stm32_hal.h"
+#include "hal/hal_i2c.h"
+
+#include "bsp/bsp.h"
+
+#if MYNEWT_VAL(UART_0)
+static struct uart_dev hal_uart0;
+
+static const struct stm32_uart_cfg uart_cfg[UART_CNT] = {
+ [0] = {
+ .suc_uart = USART2,
+ .suc_rcc_reg = &RCC->APB1ENR1,
+ .suc_rcc_dev = RCC_APB1ENR1_USART2EN,
+ .suc_pin_tx = MCU_GPIO_PORTA(2),
+ .suc_pin_rx = MCU_GPIO_PORTA(3),
+ .suc_pin_rts = -1,
+ .suc_pin_cts = -1,
+ .suc_pin_af = GPIO_AF7_USART2,
+ .suc_irqn = USART2_IRQn
+ }
+};
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+/*
+ * NOTE: The PB8 and PB9 pins are connected through jumpers in the board to
+ * both AIN and I2C pins. To enable I2C functionality SB51/SB56 need to
+ * be removed (they are the default connections) and SB46/SB52 need to
+ * be added.
+ */
+static struct stm32_hal_i2c_cfg i2c_cfg0 = {
+ .hic_i2c = I2C1,
+ .hic_rcc_reg = &RCC->APB1ENR1,
+ .hic_rcc_dev = RCC_APB1ENR1_I2C1EN,
+ .hic_pin_sda = MCU_GPIO_PORTB(9), /* PB9 - D14 on CN5 */
+ .hic_pin_scl = MCU_GPIO_PORTB(8), /* PB8 - D15 on CN5 */
+ .hic_pin_af = GPIO_AF4_I2C1,
+ .hic_10bit = 0,
+ .hic_timingr = 0x10420F13, /* 100KHz at 8MHz of SysCoreClock */
+};
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE) || MYNEWT_VAL(SPI_0_MASTER)
+struct stm32_hal_spi_cfg spi0_cfg = {
+ .ss_pin = MCU_GPIO_PORTA(4),
+ .sck_pin = MCU_GPIO_PORTA(5),
+ .miso_pin = MCU_GPIO_PORTA(6),
+ .mosi_pin = MCU_GPIO_PORTB(5),
+ .irq_prio = 2,
+};
+#endif
+
+static const struct hal_bsp_mem_dump dump_cfg[] = {
+ [0] = {
+ .hbmd_start = &_ram_start,
+ .hbmd_size = RAM_SIZE
+ },
+};
+
+const struct hal_flash *
+hal_bsp_flash_dev(uint8_t id)
+{
+ /*
+ * Internal flash mapped to id 0.
+ */
+ if (id != 0) {
+ return NULL;
+ }
+ return &stm32l4_flash_dev;
+}
+
+const struct hal_bsp_mem_dump *
+hal_bsp_core_dump(int *area_cnt)
+{
+ *area_cnt = sizeof(dump_cfg) / sizeof(dump_cfg[0]);
+ return dump_cfg;
+}
+
+void
+hal_bsp_init(void)
+{
+ int rc;
+
+ (void)rc;
+
+#if MYNEWT_VAL(UART_0)
+ rc = os_dev_create((struct os_dev *) &hal_uart0, "uart0",
+ OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(TIMER_0)
+ hal_timer_init(0, TIM2);
+#endif
+
+#if MYNEWT_VAL(TIMER_1)
+ hal_timer_init(1, TIM3);
+#endif
+
+#if MYNEWT_VAL(TIMER_2)
+ hal_timer_init(2, TIM4);
+#endif
+
+#if MYNEWT_VAL(SPI_0_MASTER)
+ rc = hal_spi_init(0, &spi0_cfg, HAL_SPI_TYPE_MASTER);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(SPI_0_SLAVE)
+ rc = hal_spi_init(0, &spi0_cfg, HAL_SPI_TYPE_SLAVE);
+ assert(rc == 0);
+#endif
+
+#if MYNEWT_VAL(I2C_0)
+ rc = hal_i2c_init(0, &i2c_cfg0);
+ assert(rc == 0);
+#endif
+}
+
+/**
+ * Returns the configured priority for the given interrupt. If no priority
+ * configured, return the priority passed in
+ *
+ * @param irq_num
+ * @param pri
+ *
+ * @return uint32_t
+ */
+uint32_t
+hal_bsp_get_nvic_priority(int irq_num, uint32_t pri)
+{
+ /* Add any interrupt priorities configured by the bsp here */
+ return pri;
+}
diff --git a/hw/bsp/nucleo-l476rg/src/system_stm32l4xx.c b/hw/bsp/nucleo-l476rg/src/system_stm32l4xx.c
new file mode 100644
index 0000000000..2caad67475
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/src/system_stm32l4xx.c
@@ -0,0 +1,349 @@
+/**
+ ******************************************************************************
+ * @file system_stm32l4xx.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File
+ *
+ * This file provides two functions and one global variable to be called from
+ * user application:
+ * - SystemInit(): This function is called at startup just after reset and
+ * before branch to main program. This call is made inside
+ * the "startup_stm32l4xx.s" file.
+ *
+ * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+ * by the user application to setup the SysTick
+ * timer or configure other parameters.
+ *
+ * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+ * be called whenever the core clock is changed
+ * during program execution.
+ *
+ * After each device reset the MSI (4 MHz) is used as system clock source.
+ * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to
+ * configure the system clock before to branch to main program.
+ *
+ * This file configures the system clock as follows:
+ *=============================================================================
+ *-----------------------------------------------------------------------------
+ * System Clock source | MSI
+ *-----------------------------------------------------------------------------
+ * SYSCLK(Hz) | 4000000
+ *-----------------------------------------------------------------------------
+ * HCLK(Hz) | 4000000
+ *-----------------------------------------------------------------------------
+ * AHB Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB1 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * APB2 Prescaler | 1
+ *-----------------------------------------------------------------------------
+ * PLL_M | 1
+ *-----------------------------------------------------------------------------
+ * PLL_N | 8
+ *-----------------------------------------------------------------------------
+ * PLL_P | 7
+ *-----------------------------------------------------------------------------
+ * PLL_Q | 2
+ *-----------------------------------------------------------------------------
+ * PLL_R | 2
+ *-----------------------------------------------------------------------------
+ * PLLSAI1_P | NA
+ *-----------------------------------------------------------------------------
+ * PLLSAI1_Q | NA
+ *-----------------------------------------------------------------------------
+ * PLLSAI1_R | NA
+ *-----------------------------------------------------------------------------
+ * PLLSAI2_P | NA
+ *-----------------------------------------------------------------------------
+ * PLLSAI2_Q | NA
+ *-----------------------------------------------------------------------------
+ * PLLSAI2_R | NA
+ *-----------------------------------------------------------------------------
+ * Require 48MHz for USB OTG FS, | Disabled
+ * SDIO and RNG clock |
+ *-----------------------------------------------------------------------------
+ *=============================================================================
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS
+ * @{
+ */
+
+/** @addtogroup stm32l4xx_system
+ * @{
+ */
+
+/** @addtogroup STM32L4xx_System_Private_Includes
+ * @{
+ */
+
+#include "stm32l4xx.h"
+#include "mcu/cmsis_nvic.h"
+
+#if !defined (HSE_VALUE)
+ #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+#if !defined (MSI_VALUE)
+ #define MSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* MSI_VALUE */
+
+#if !defined (HSI_VALUE)
+ #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Private_TypesDefinitions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Private_Defines
+ * @{
+ */
+
+/************************* Miscellaneous Configuration ************************/
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+/******************************************************************************/
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Private_Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Private_Variables
+ * @{
+ */
+ /* The SystemCoreClock variable is updated in three ways:
+ 1) by calling CMSIS function SystemCoreClockUpdate()
+ 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+ Note: If you use this function to configure the system clock; then there
+ is no need to call the 2 first functions listed above, since SystemCoreClock
+ variable is updated automatically.
+ */
+ uint32_t SystemCoreClock = 4000000;
+
+ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+ const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
+ const uint32_t MSIRangeTable[12] = {100000, 200000, 400000, 800000, 1000000, 2000000, \
+ 4000000, 8000000, 16000000, 24000000, 32000000, 48000000};
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/** @addtogroup STM32L4xx_System_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Setup the microcontroller system.
+ * @param None
+ * @retval None
+ */
+
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+ #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+ #endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set MSION bit */
+ RCC->CR |= RCC_CR_MSION;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON , HSION, and PLLON bits */
+ RCC->CR &= (uint32_t)0xEAF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x00001000;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIER = 0x00000000;
+
+ /* Relocate the vector table */
+ NVIC_Relocate();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
+ * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+ * 4 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+ * 16 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate(void)
+{
+ uint32_t tmp = 0, msirange = 0, pllvco = 0, pllr = 2, pllsource = 0, pllm = 2;
+
+ /* Get MSI Range frequency--------------------------------------------------*/
+ if((RCC->CR & RCC_CR_MSIRGSEL) == RESET)
+ { /* MSISRANGE from RCC_CSR applies */
+ msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8;
+ }
+ else
+ { /* MSIRANGE from RCC_CR applies */
+ msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4;
+ }
+ /*MSI frequency range in HZ*/
+ msirange = MSIRangeTable[msirange];
+
+ /* Get SYSCLK source -------------------------------------------------------*/
+ switch (RCC->CFGR & RCC_CFGR_SWS)
+ {
+ case 0x00: /* MSI used as system clock source */
+ SystemCoreClock = msirange;
+ break;
+
+ case 0x04: /* HSI used as system clock source */
+ SystemCoreClock = HSI_VALUE;
+ break;
+
+ case 0x08: /* HSE used as system clock source */
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ case 0x0C: /* PLL used as system clock source */
+ /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
+ SYSCLK = PLL_VCO / PLLR
+ */
+ pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
+ pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4) + 1 ;
+
+ switch (pllsource)
+ {
+ case 0x02: /* HSI used as PLL clock source */
+ pllvco = (HSI_VALUE / pllm);
+ break;
+
+ case 0x03: /* HSE used as PLL clock source */
+ pllvco = (HSE_VALUE / pllm);
+ break;
+
+ default: /* MSI used as PLL clock source */
+ pllvco = (msirange / pllm);
+ break;
+ }
+ pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8);
+ pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25) + 1) * 2;
+ SystemCoreClock = pllvco/pllr;
+ break;
+
+ default:
+ SystemCoreClock = msirange;
+ break;
+ }
+ /* Compute HCLK clock frequency --------------------------------------------*/
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-l476rg/syscfg.yml b/hw/bsp/nucleo-l476rg/syscfg.yml
new file mode 100644
index 0000000000..e69c957cdd
--- /dev/null
+++ b/hw/bsp/nucleo-l476rg/syscfg.yml
@@ -0,0 +1,41 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ UART_0:
+ description: 'Whether to enable UART0'
+ value: 1
+
+ TIMER_0:
+ description: 'Whether to enable TIMER_0'
+ value: 0
+
+ TIMER_1:
+ description: 'Whether to enable TIMER_1'
+ value: 0
+
+ TIMER_2:
+ description: 'Whether to enable TIMER_2'
+ value: 0
+
+syscfg.vals:
+ REBOOT_LOG_FLASH_AREA: FLASH_AREA_REBOOT_LOG
+ CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
+ NFFS_FLASH_AREA: FLASH_AREA_NFFS
+ COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
diff --git a/hw/bsp/olimex-p103/bsp.yml b/hw/bsp/olimex-p103/bsp.yml
index 9f91e661f3..a5933fea9e 100644
--- a/hw/bsp/olimex-p103/bsp.yml
+++ b/hw/bsp/olimex-p103/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m3
bsp.compiler: compiler/arm-none-eabi-m3
bsp.linkerscript:
- "hw/bsp/olimex-p103/olimex_p103.ld"
- - "hw/mcu/stm/stm32f1xx/stm32f103.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f1xx/stm32f103.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/olimex-p103/boot-olimex_p103.ld"
- - "hw/mcu/stm/stm32f1xx/stm32f103.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f1xx/stm32f103.ld"
bsp.downloadscript: "hw/bsp/olimex-p103/olimex_p103_download.sh"
bsp.debugscript: "hw/bsp/olimex-p103/olimex_p103_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/olimex-p103/olimex_p103_download.cmd"
diff --git a/hw/bsp/olimex-p103/pkg.yml b/hw/bsp/olimex-p103/pkg.yml
index adb3a0d530..bbfe4d8521 100644
--- a/hw/bsp/olimex-p103/pkg.yml
+++ b/hw/bsp/olimex-p103/pkg.yml
@@ -29,8 +29,8 @@ pkg.keywords:
pkg.cflags: -DSTM32F103xB
pkg.deps:
- - hw/mcu/stm/stm32f1xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f1xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/olimex_stm32-e407_devboard/bsp.yml b/hw/bsp/olimex_stm32-e407_devboard/bsp.yml
index fdddd4b554..f87d146b8d 100644
--- a/hw/bsp/olimex_stm32-e407_devboard/bsp.yml
+++ b/hw/bsp/olimex_stm32-e407_devboard/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f407.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/olimex_stm32-e407_devboard/boot-olimex_stm32-e407_devboard.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f407.ld"
bsp.downloadscript: "hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard_download.sh"
bsp.debugscript: "hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/olimex_stm32-e407_devboard/olimex_stm32-e407_devboard_download.cmd"
diff --git a/hw/bsp/olimex_stm32-e407_devboard/pkg.yml b/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
index 7708c67687..37a2c75899 100644
--- a/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
+++ b/hw/bsp/olimex_stm32-e407_devboard/pkg.yml
@@ -35,18 +35,18 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f4xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.ADC_1:
- - hw/drivers/adc/adc_stm32f4
+ - "@apache-mynewt-core/hw/drivers/adc/adc_stm32f4"
pkg.deps.ADC_2:
- - hw/drivers/adc/adc_stm32f4
+ - "@apache-mynewt-core/hw/drivers/adc/adc_stm32f4"
pkg.deps.ADC_3:
- - hw/drivers/adc/adc_stm32f4
+ - "@apache-mynewt-core/hw/drivers/adc/adc_stm32f4"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.ETH_0:
- - hw/drivers/lwip/stm32_eth
+ - "@apache-mynewt-core/hw/drivers/lwip/stm32_eth"
diff --git a/hw/bsp/pic32mx470_6lp_clicker/pkg.yml b/hw/bsp/pic32mx470_6lp_clicker/pkg.yml
index 1f104e9a6e..7d87ca3700 100644
--- a/hw/bsp/pic32mx470_6lp_clicker/pkg.yml
+++ b/hw/bsp/pic32mx470_6lp_clicker/pkg.yml
@@ -33,17 +33,17 @@ pkg.lflags:
- -Wl,--defsym=_min_heap_size=0x400
pkg.deps:
- - hw/mcu/microchip/pic32mx470f512h
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/microchip/pic32mx470f512h"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_2:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_3:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/pic32mz2048_wi-fire/pkg.yml b/hw/bsp/pic32mz2048_wi-fire/pkg.yml
index 75d39dc349..d1fb059504 100644
--- a/hw/bsp/pic32mz2048_wi-fire/pkg.yml
+++ b/hw/bsp/pic32mz2048_wi-fire/pkg.yml
@@ -33,23 +33,23 @@ pkg.lflags:
- -Wl,--defsym=_min_heap_size=0x400
pkg.deps:
- - hw/mcu/microchip/pic32mz2048efg100
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/microchip/pic32mz2048efg100"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_2:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_3:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_4:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_5:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/puckjs/bsp.yml b/hw/bsp/puckjs/bsp.yml
index a312fbc770..2913debe9e 100644
--- a/hw/bsp/puckjs/bsp.yml
+++ b/hw/bsp/puckjs/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/puckjs/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/puckjs/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/puckjs/split_puckjs.ld"
bsp.downloadscript: "hw/bsp/puckjs/puckjs_download.sh"
bsp.debugscript: "hw/bsp/puckjs/puckjs_debug.sh"
diff --git a/hw/bsp/puckjs/pkg.yml b/hw/bsp/puckjs/pkg.yml
index 02bde6c63d..031a18c6b4 100644
--- a/hw/bsp/puckjs/pkg.yml
+++ b/hw/bsp/puckjs/pkg.yml
@@ -34,29 +34,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/rb-blend2/bsp.yml b/hw/bsp/rb-blend2/bsp.yml
index 0c0c9f34d3..4e8f8fadfa 100644
--- a/hw/bsp/rb-blend2/bsp.yml
+++ b/hw/bsp/rb-blend2/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/rb-blend2/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/rb-blend2/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/rb-blend2/split-rb-blend2.ld"
bsp.downloadscript: "hw/bsp/rb-blend2/rb-blend2_download.sh"
bsp.debugscript: "hw/bsp/rb-blend2/rb-blend2_debug.sh"
diff --git a/hw/bsp/rb-blend2/pkg.yml b/hw/bsp/rb-blend2/pkg.yml
index be67bd1942..12a5b5d8fe 100644
--- a/hw/bsp/rb-blend2/pkg.yml
+++ b/hw/bsp/rb-blend2/pkg.yml
@@ -34,29 +34,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/rb-nano2/bsp.yml b/hw/bsp/rb-nano2/bsp.yml
index 7e04c46a1d..de5b056b12 100644
--- a/hw/bsp/rb-nano2/bsp.yml
+++ b/hw/bsp/rb-nano2/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/rb-nano2/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/rb-nano2/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/rb-nano2/split-rb-nano2.ld"
bsp.downloadscript: "hw/bsp/rb-nano2/rb-nano2_download.sh"
bsp.debugscript: "hw/bsp/rb-nano2/rb-nano2_debug.sh"
diff --git a/hw/bsp/rb-nano2/pkg.yml b/hw/bsp/rb-nano2/pkg.yml
index 0499ba0bee..15c4a46f85 100644
--- a/hw/bsp/rb-nano2/pkg.yml
+++ b/hw/bsp/rb-nano2/pkg.yml
@@ -34,29 +34,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/ruuvi_tag_revb2/bsp.yml b/hw/bsp/ruuvi_tag_revb2/bsp.yml
index 918392c6ee..27fc1ff3d4 100644
--- a/hw/bsp/ruuvi_tag_revb2/bsp.yml
+++ b/hw/bsp/ruuvi_tag_revb2/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/ruuvi_tag_revb2/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/ruuvi_tag_revb2/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/ruuvi_tag_revb2/split-nrf52dk.ld"
bsp.downloadscript: "hw/bsp/ruuvi_tag_revb2/nrf52dk_download.sh"
bsp.debugscript: "hw/bsp/ruuvi_tag_revb2/nrf52dk_debug.sh"
diff --git a/hw/bsp/ruuvi_tag_revb2/pkg.yml b/hw/bsp/ruuvi_tag_revb2/pkg.yml
index 28e6f1d17e..86509533af 100644
--- a/hw/bsp/ruuvi_tag_revb2/pkg.yml
+++ b/hw/bsp/ruuvi_tag_revb2/pkg.yml
@@ -35,38 +35,38 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
pkg.deps.BME280_ONB:
- - hw/drivers/sensors/bme280
+ - "@apache-mynewt-core/hw/drivers/sensors/bme280"
pkg.deps.LIS2DH12_ONB:
- - hw/drivers/sensors/lis2dh12
+ - "@apache-mynewt-core/hw/drivers/sensors/lis2dh12"
pkg.init:
config_lis2dh12_sensor: 400
diff --git a/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c b/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c
index 960bdbc921..899618708c 100644
--- a/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c
+++ b/hw/bsp/ruuvi_tag_revb2/src/hal_bsp.c
@@ -232,15 +232,15 @@ config_bme280_sensor(void)
memset(&bmecfg, 0, sizeof(bmecfg));
- bmecfg.bc_mode = BME280_MODE_NORMAL;
- bmecfg.bc_iir = BME280_FILTER_X16;
+ bmecfg.bc_mode = BME280_MODE_FORCED;
+ bmecfg.bc_iir = BME280_FILTER_OFF;
bmecfg.bc_sby_dur = BME280_STANDBY_MS_0_5;
bmecfg.bc_boc[0].boc_type = SENSOR_TYPE_RELATIVE_HUMIDITY;
bmecfg.bc_boc[1].boc_type = SENSOR_TYPE_PRESSURE;
bmecfg.bc_boc[2].boc_type = SENSOR_TYPE_AMBIENT_TEMPERATURE;
bmecfg.bc_boc[0].boc_oversample = BME280_SAMPLING_X1;
- bmecfg.bc_boc[1].boc_oversample = BME280_SAMPLING_X16;
- bmecfg.bc_boc[2].boc_oversample = BME280_SAMPLING_X2;
+ bmecfg.bc_boc[1].boc_oversample = BME280_SAMPLING_X1;
+ bmecfg.bc_boc[2].boc_oversample = BME280_SAMPLING_X1;
bmecfg.bc_s_mask = SENSOR_TYPE_AMBIENT_TEMPERATURE|
SENSOR_TYPE_PRESSURE|
SENSOR_TYPE_RELATIVE_HUMIDITY;
diff --git a/hw/bsp/sensorhub/bsp.yml b/hw/bsp/sensorhub/bsp.yml
index f19e0e884b..ce475e3f50 100644
--- a/hw/bsp/sensorhub/bsp.yml
+++ b/hw/bsp/sensorhub/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/sensorhub/sensorhub.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f427.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f427.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/sensorhub/boot-sensorhub.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f427.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f427.ld"
bsp.downloadscript: "hw/bsp/sensorhub/sensorhub_download.sh"
bsp.debugscript: "hw/bsp/sensorhub/sensorhub_debug.sh"
bsp.downloadscript.WINDOWS.OVERRIDE: "hw/bsp/sensorhub/sensorhub_download.cmd"
diff --git a/hw/bsp/sensorhub/pkg.yml b/hw/bsp/sensorhub/pkg.yml
index 26ad6f26ad..04261dddd6 100644
--- a/hw/bsp/sensorhub/pkg.yml
+++ b/hw/bsp/sensorhub/pkg.yml
@@ -33,8 +33,8 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f4xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/stm32f3discovery/bsp.yml b/hw/bsp/stm32f3discovery/bsp.yml
index 5cc58b2472..cc5a9a2ca6 100644
--- a/hw/bsp/stm32f3discovery/bsp.yml
+++ b/hw/bsp/stm32f3discovery/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/stm32f3discovery/stm32f3discovery.ld"
- - "hw/mcu/stm/stm32f3xx/stm32f303.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx/stm32f303.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/stm32f3discovery/boot-stm32f3discovery.ld"
- - "hw/mcu/stm/stm32f3xx/stm32f303.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx/stm32f303.ld"
bsp.downloadscript: "hw/bsp/stm32f3discovery/stm32f3discovery_download.sh"
bsp.debugscript: "hw/bsp/stm32f3discovery/stm32f3discovery_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/stm32f3discovery/stm32f3discovery_download.cmd"
diff --git a/hw/bsp/stm32f3discovery/pkg.yml b/hw/bsp/stm32f3discovery/pkg.yml
index 403a8ae426..3edf273ac1 100644
--- a/hw/bsp/stm32f3discovery/pkg.yml
+++ b/hw/bsp/stm32f3discovery/pkg.yml
@@ -33,11 +33,11 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f3xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/stm32f429discovery/bsp.yml b/hw/bsp/stm32f429discovery/bsp.yml
index 5b6c28b2e5..f1e13da5f8 100644
--- a/hw/bsp/stm32f429discovery/bsp.yml
+++ b/hw/bsp/stm32f429discovery/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/stm32f429discovery/stm32f429discovery.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f429.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f429.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/stm32f429discovery/boot-stm32f429discovery.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f429.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f429.ld"
bsp.downloadscript: "hw/bsp/stm32f429discovery/stm32f429discovery_download.sh"
bsp.debugscript: "hw/bsp/stm32f429discovery/stm32f429discovery_debug.sh"
diff --git a/hw/bsp/stm32f429discovery/pkg.yml b/hw/bsp/stm32f429discovery/pkg.yml
index bdda1ba5d4..9fd73f539b 100644
--- a/hw/bsp/stm32f429discovery/pkg.yml
+++ b/hw/bsp/stm32f429discovery/pkg.yml
@@ -33,8 +33,8 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f4xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/stm32f4discovery/bsp.yml b/hw/bsp/stm32f4discovery/bsp.yml
index 6c4a1a5e4d..ddda5ddca6 100644
--- a/hw/bsp/stm32f4discovery/bsp.yml
+++ b/hw/bsp/stm32f4discovery/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/stm32f4discovery/stm32f4discovery.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f407.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/stm32f4discovery/boot-stm32f4discovery.ld"
- - "hw/mcu/stm/stm32f4xx/stm32f407.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx/stm32f407.ld"
bsp.downloadscript: "hw/bsp/stm32f4discovery/stm32f4discovery_download.sh"
bsp.debugscript: "hw/bsp/stm32f4discovery/stm32f4discovery_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/stm32f4discovery/stm32f4discovery_download.cmd"
diff --git a/hw/bsp/stm32f4discovery/pkg.yml b/hw/bsp/stm32f4discovery/pkg.yml
index 55183e738d..b6840da43b 100644
--- a/hw/bsp/stm32f4discovery/pkg.yml
+++ b/hw/bsp/stm32f4discovery/pkg.yml
@@ -33,8 +33,8 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f4xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/stm32f7discovery/bsp.yml b/hw/bsp/stm32f7discovery/bsp.yml
index 7a0ebf7f26..95e6a26e78 100644
--- a/hw/bsp/stm32f7discovery/bsp.yml
+++ b/hw/bsp/stm32f7discovery/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m7
bsp.compiler: compiler/arm-none-eabi-m7
bsp.linkerscript:
- "hw/bsp/stm32f7discovery/stm32f7discovery.ld"
- - "hw/mcu/stm/stm32f7xx/stm32f746.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx/stm32f746.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/stm32f7discovery/boot-stm32f7discovery.ld"
- - "hw/mcu/stm/stm32f7xx/stm32f746.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx/stm32f746.ld"
bsp.downloadscript: "hw/bsp/stm32f7discovery/stm32f7discovery_download.sh"
bsp.debugscript: "hw/bsp/stm32f7discovery/stm32f7discovery_debug.sh"
diff --git a/hw/bsp/stm32f7discovery/pkg.yml b/hw/bsp/stm32f7discovery/pkg.yml
index a880e3cc38..784de0a00c 100644
--- a/hw/bsp/stm32f7discovery/pkg.yml
+++ b/hw/bsp/stm32f7discovery/pkg.yml
@@ -33,20 +33,20 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/stm/stm32f7xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.ETH_0:
- - hw/drivers/lwip/stm32_eth
+ - "@apache-mynewt-core/hw/drivers/lwip/stm32_eth"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_stm32
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_stm32"
diff --git a/hw/bsp/stm32l152discovery/bsp.yml b/hw/bsp/stm32l152discovery/bsp.yml
index e737a3f593..06ae773ad4 100644
--- a/hw/bsp/stm32l152discovery/bsp.yml
+++ b/hw/bsp/stm32l152discovery/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m3
bsp.compiler: compiler/arm-none-eabi-m3
bsp.linkerscript:
- "hw/bsp/stm32l152discovery/stm32l152discovery.ld"
- - "hw/mcu/stm/stm32l1xx/stm32l152.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32l1xx/stm32l152.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/stm32l152discovery/boot-stm32l152discovery.ld"
- - "hw/mcu/stm/stm32l1xx/stm32l152.ld"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32l1xx/stm32l152.ld"
bsp.downloadscript: "hw/bsp/stm32l152discovery/stm32l152discovery_download.sh"
bsp.debugscript: "hw/bsp/stm32l152discovery/stm32l152discovery_debug.sh"
bsp.downloadscript.WINDOWS.OVERWRITE: "hw/bsp/stm32l152discovery/stm32l152discovery_download.cmd"
diff --git a/hw/bsp/stm32l152discovery/pkg.yml b/hw/bsp/stm32l152discovery/pkg.yml
index a4d0e4beb9..ca7eff61b6 100644
--- a/hw/bsp/stm32l152discovery/pkg.yml
+++ b/hw/bsp/stm32l152discovery/pkg.yml
@@ -30,8 +30,8 @@ pkg.keywords:
pkg.cflags: -DSTM32L152xC
pkg.deps:
- - hw/mcu/stm/stm32l1xx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/stm/stm32l1xx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/bsp/telee02/bsp.yml b/hw/bsp/telee02/bsp.yml
index ffc3928cdc..200d77c3a5 100644
--- a/hw/bsp/telee02/bsp.yml
+++ b/hw/bsp/telee02/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/telee02/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/telee02/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/telee02/split-telee02.ld"
bsp.downloadscript: "hw/bsp/telee02/telee02_download.sh"
bsp.debugscript: "hw/bsp/telee02/telee02_debug.sh"
diff --git a/hw/bsp/telee02/pkg.yml b/hw/bsp/telee02/pkg.yml
index 81cfb05c5c..83d1ba1ab2 100644
--- a/hw/bsp/telee02/pkg.yml
+++ b/hw/bsp/telee02/pkg.yml
@@ -34,32 +34,32 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.LORA_NODE:
- - hw/drivers/lora/sx1276
+ - "@apache-mynewt-core/hw/drivers/lora/sx1276"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/bsp/usbmkw41z/pkg.yml b/hw/bsp/usbmkw41z/pkg.yml
index 9c19a6f04a..a5e89adda2 100644
--- a/hw/bsp/usbmkw41z/pkg.yml
+++ b/hw/bsp/usbmkw41z/pkg.yml
@@ -29,7 +29,7 @@ pkg.keywords:
# NOTE: boot/bootutil and sys/flash_map were here. Seeing if they can be removed
pkg.deps:
- - hw/mcu/nxp/mkw41z
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nxp/mkw41z"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.cflags: -DCPU_MKW41Z512VHT4
diff --git a/hw/bsp/vbluno51/bsp.yml b/hw/bsp/vbluno51/bsp.yml
index ec18373cba..af2d715500 100644
--- a/hw/bsp/vbluno51/bsp.yml
+++ b/hw/bsp/vbluno51/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m0
bsp.compiler: compiler/arm-none-eabi-m0
bsp.linkerscript:
- "hw/bsp/vbluno51/nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/vbluno51/boot-nrf51xxac.ld"
- - "hw/mcu/nordic/nrf51xxx/nrf51.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx/nrf51.ld"
bsp.part2linkerscript: "hw/bsp/vbluno51/split-vbluno51.ld"
bsp.downloadscript: "hw/bsp/vbluno51/vbluno51_download.sh"
bsp.debugscript: "hw/bsp/vbluno51/vbluno51_debug.sh"
diff --git a/hw/bsp/vbluno51/pkg.yml b/hw/bsp/vbluno51/pkg.yml
index 2dec3de14d..eb4f4b2375 100644
--- a/hw/bsp/vbluno51/pkg.yml
+++ b/hw/bsp/vbluno51/pkg.yml
@@ -30,17 +30,17 @@ pkg.cflags:
- '-DNRF51'
pkg.deps:
- - hw/mcu/nordic/nrf51xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf51xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf51
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf51"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf51
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf51"
diff --git a/hw/bsp/vbluno52/bsp.yml b/hw/bsp/vbluno52/bsp.yml
index c66a5cd92a..276cfed57a 100644
--- a/hw/bsp/vbluno52/bsp.yml
+++ b/hw/bsp/vbluno52/bsp.yml
@@ -21,10 +21,10 @@ bsp.arch: cortex_m4
bsp.compiler: compiler/arm-none-eabi-m4
bsp.linkerscript:
- "hw/bsp/vbluno52/nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.linkerscript.BOOT_LOADER.OVERWRITE:
- "hw/bsp/vbluno52/boot-nrf52xxaa.ld"
- - "hw/mcu/nordic/nrf52xxx/nrf52.ld"
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx/nrf52.ld"
bsp.part2linkerscript: "hw/bsp/vbluno52/split-vbluno52.ld"
bsp.downloadscript: "hw/bsp/vbluno52/vbluno52_download.sh"
bsp.debugscript: "hw/bsp/vbluno52/vbluno52_debug.sh"
diff --git a/hw/bsp/vbluno52/pkg.yml b/hw/bsp/vbluno52/pkg.yml
index 9c07107f0c..83cd6ee85f 100644
--- a/hw/bsp/vbluno52/pkg.yml
+++ b/hw/bsp/vbluno52/pkg.yml
@@ -33,29 +33,29 @@ pkg.cflags.HARDFLOAT:
- -mfloat-abi=hard -mfpu=fpv4-sp-d16
pkg.deps:
- - hw/mcu/nordic/nrf52xxx
- - libc/baselibc
+ - "@apache-mynewt-core/hw/mcu/nordic/nrf52xxx"
+ - "@apache-mynewt-core/libc/baselibc"
pkg.deps.BLE_DEVICE:
- - hw/drivers/nimble/nrf52
+ - "@apache-mynewt-core/hw/drivers/nimble/nrf52"
pkg.deps.UART_0:
- - hw/drivers/uart/uart_hal
+ - "@apache-mynewt-core/hw/drivers/uart/uart_hal"
pkg.deps.UART_1:
- - hw/drivers/uart/uart_bitbang
+ - "@apache-mynewt-core/hw/drivers/uart/uart_bitbang"
pkg.deps.ADC_0:
- - hw/drivers/adc/adc_nrf52
+ - "@apache-mynewt-core/hw/drivers/adc/adc_nrf52"
pkg.deps.PWM_0:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_1:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.PWM_2:
- - hw/drivers/pwm/pwm_nrf52
+ - "@apache-mynewt-core/hw/drivers/pwm/pwm_nrf52"
pkg.deps.SOFT_PWM:
- - hw/drivers/pwm/soft_pwm
+ - "@apache-mynewt-core/hw/drivers/pwm/soft_pwm"
diff --git a/hw/charge-control/include/charge-control/charge_control.h b/hw/charge-control/include/charge-control/charge_control.h
index fb9ec26520..c3b1b72b0e 100644
--- a/hw/charge-control/include/charge-control/charge_control.h
+++ b/hw/charge-control/include/charge-control/charge_control.h
@@ -178,6 +178,9 @@ struct charge_control_itf {
/* Charge control interface address (for I2C interface type) */
uint16_t cci_addr;
+
+ /* OS lock for shared access */
+ struct os_mutex *cci_lock;
};
// ---------------------- LISTENER ---------------------------------
diff --git a/hw/charge-control/pkg.yml b/hw/charge-control/pkg.yml
index 355de704db..6b28caae8f 100644
--- a/hw/charge-control/pkg.yml
+++ b/hw/charge-control/pkg.yml
@@ -22,11 +22,11 @@ pkg.description: Battery Charge Controller IC Interface
pkg.keywords:
pkg.deps:
- - kernel/os
+ - "@apache-mynewt-core/kernel/os"
pkg.deps.CHARGE_CONTROL_CLI:
- - sys/shell
- - util/parse
+ - "@apache-mynewt-core/sys/shell"
+ - "@apache-mynewt-core/util/parse"
pkg.req_apis:
- console
diff --git a/hw/drivers/adc/adc_nrf51/pkg.yml b/hw/drivers/adc/adc_nrf51/pkg.yml
index 1f40d16ac6..c640429e5e 100644
--- a/hw/drivers/adc/adc_nrf51/pkg.yml
+++ b/hw/drivers/adc/adc_nrf51/pkg.yml
@@ -25,5 +25,5 @@ pkg.keywords:
pkg.apis:
- ADC_HW_IMPL
pkg.deps:
- - hw/drivers/adc
- - hw/mcu/nordic
+ - "@apache-mynewt-core/hw/drivers/adc"
+ - "@apache-mynewt-core/hw/mcu/nordic"
diff --git a/hw/drivers/adc/adc_nrf52/pkg.yml b/hw/drivers/adc/adc_nrf52/pkg.yml
index 71c4d75fd1..f1e98a4e99 100644
--- a/hw/drivers/adc/adc_nrf52/pkg.yml
+++ b/hw/drivers/adc/adc_nrf52/pkg.yml
@@ -25,5 +25,5 @@ pkg.keywords:
pkg.apis:
- ADC_HW_IMPL
pkg.deps:
- - hw/drivers/adc
- - hw/mcu/nordic
+ - "@apache-mynewt-core/hw/drivers/adc"
+ - "@apache-mynewt-core/hw/mcu/nordic"
diff --git a/hw/drivers/adc/adc_stm32f4/pkg.yml b/hw/drivers/adc/adc_stm32f4/pkg.yml
index 8ed81a98b2..171e5309ec 100644
--- a/hw/drivers/adc/adc_stm32f4/pkg.yml
+++ b/hw/drivers/adc/adc_stm32f4/pkg.yml
@@ -27,8 +27,8 @@ pkg.features:
pkg.apis:
- ADC_HW_IMPL
pkg.deps:
- - hw/drivers/adc
+ - "@apache-mynewt-core/hw/drivers/adc"
pkg.deps.TEST:
- - hw/hal
- - hw/mcu/stm/stm32f4xx
- - test/testutil
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
+ - "@apache-mynewt-core/test/testutil"
diff --git a/hw/drivers/bq27z561/include/bq27z561/bq27z561.h b/hw/drivers/bq27z561/include/bq27z561/bq27z561.h
index b92e0ce082..82a4072600 100644
--- a/hw/drivers/bq27z561/include/bq27z561/bq27z561.h
+++ b/hw/drivers/bq27z561/include/bq27z561/bq27z561.h
@@ -545,6 +545,8 @@ bq27z561_err_t bq27x561_rd_flash(struct bq27z561 *dev, uint16_t addr,
bq27z561_err_t bq27x561_rd_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd,
uint8_t *val, int val_len);
+bq27z561_err_t bq27x561_wr_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd,
+ uint8_t *buf, int len);
/**
* bq27z561 rd std reg word
*
diff --git a/hw/drivers/bq27z561/pkg.yml b/hw/drivers/bq27z561/pkg.yml
index 532c9875e1..45e5d52280 100644
--- a/hw/drivers/bq27z561/pkg.yml
+++ b/hw/drivers/bq27z561/pkg.yml
@@ -28,13 +28,13 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/battery"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.BQ27Z561_CLI:
- "@apache-mynewt-core/util/parse"
pkg.init:
- bq27z561_pkg_init: 500
\ No newline at end of file
+ bq27z561_pkg_init: 500
diff --git a/hw/drivers/bq27z561/src/bq27z561.c b/hw/drivers/bq27z561/src/bq27z561.c
index 3cacfb8f17..860bd0b02d 100644
--- a/hw/drivers/bq27z561/src/bq27z561.c
+++ b/hw/drivers/bq27z561/src/bq27z561.c
@@ -29,17 +29,15 @@
#include "battery/battery_prop.h"
#if MYNEWT_VAL(BQ27Z561_LOG)
-#include "log/log.h"
+#include "modlog/modlog.h"
#endif
#if MYNEWT_VAL(BQ27Z561_LOG)
-static struct log bq27z561_log;
-#define LOG_MODULE_BQ27Z561 (253)
-#define BQ27Z561_ERROR(...) LOG_ERROR(&bq27z561_log, LOG_MODULE_BQ27Z561, __VA_ARGS__)
-#define BQ27Z561_INFO(...) LOG_INFO(&bq27z561_log, LOG_MODULE_BQ27Z561, __VA_ARGS__)
+
+#define BQ27Z561_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(BQ27Z561_LOG_MODULE), __VA_ARGS__)
#else
-#define BQ27Z561_ERROR(...)
-#define BQ27Z561_INFO(...)
+#define BQ27Z561_LOG(lvl_, ...)
#endif
static uint8_t
@@ -140,7 +138,7 @@ bq27z561_rd_std_reg_byte(struct bq27z561 *dev, uint8_t reg, uint8_t *val)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 0);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
return rc;
}
@@ -148,7 +146,7 @@ bq27z561_rd_std_reg_byte(struct bq27z561 *dev, uint8_t reg, uint8_t *val)
i2c.buffer = (uint8_t *)val;
rc = hal_i2c_master_read(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (rd) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (rd) failed 0x%02X\n", reg);
return rc;
}
@@ -172,7 +170,7 @@ bq27z561_rd_std_reg_word(struct bq27z561 *dev, uint8_t reg, uint16_t *val)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 0);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
goto err;
}
@@ -180,7 +178,7 @@ bq27z561_rd_std_reg_word(struct bq27z561 *dev, uint8_t reg, uint16_t *val)
i2c.buffer = (uint8_t *)val;
rc = hal_i2c_master_read(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (rd) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (rd) failed 0x%02X\n", reg);
goto err;
}
@@ -208,7 +206,7 @@ bq27z561_wr_std_reg_byte(struct bq27z561 *dev, uint8_t reg, uint8_t val)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg write 0x%02X failed\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg write 0x%02X failed\n", reg);
return rc;
}
@@ -237,7 +235,7 @@ bq27z561_wr_std_reg_word(struct bq27z561 *dev, uint8_t reg, uint16_t val)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg write 0x%02X failed\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg write 0x%02X failed\n", reg);
goto err;
}
@@ -284,7 +282,7 @@ bq27x561_wr_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd, uint8_t *buf,
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
}
@@ -323,7 +321,7 @@ bq27x561_rd_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd, uint8_t *val,
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
bq27z561_itf_unlock(&dev->bq27_itf);
goto err;
@@ -335,7 +333,7 @@ bq27x561_rd_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd, uint8_t *val,
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 0);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
bq27z561_itf_unlock(&dev->bq27_itf);
goto err;
@@ -345,7 +343,7 @@ bq27x561_rd_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd, uint8_t *val,
i2c.buffer = tmpbuf;
rc = hal_i2c_master_read(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (rd) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (rd) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
bq27z561_itf_unlock(&dev->bq27_itf);
goto err;
@@ -357,7 +355,7 @@ bq27x561_rd_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd, uint8_t *val,
cmd_read = tmpbuf[0];
cmd_read |= ((uint16_t)tmpbuf[1]) << 8;
if (cmd_read != cmd) {
- BQ27Z561_ERROR("cmd mismatch (cmd=%x cmd_ret=%x\n", cmd, cmd_read);
+ BQ27Z561_LOG(ERROR, "cmd mismatch (cmd=%x cmd_ret=%x\n", cmd, cmd_read);
rc = BQ27Z561_ERR_CMD_MISMATCH;
goto err;
}
@@ -377,7 +375,7 @@ bq27x561_rd_alt_mfg_cmd(struct bq27z561 *dev, uint16_t cmd, uint8_t *val,
len -= 2;
chksum = bq27z561_calc_chksum(tmpbuf, len);
if (chksum != tmpbuf[34]) {
- BQ27Z561_ERROR("chksum failure for cmd %u (calc=%u read=%u)", cmd,
+ BQ27Z561_LOG(ERROR, "chksum failure for cmd %u (calc=%u read=%u)", cmd,
chksum, tmpbuf[34]);
rc = BQ27Z561_ERR_CHKSUM_FAIL;
}
@@ -426,7 +424,7 @@ bq27x561_rd_flash(struct bq27z561 *dev, uint16_t addr, uint8_t *buf, int buflen)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
bq27z561_itf_unlock(&dev->bq27_itf);
goto err;
@@ -438,7 +436,7 @@ bq27x561_rd_flash(struct bq27z561 *dev, uint16_t addr, uint8_t *buf, int buflen)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 0);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
bq27z561_itf_unlock(&dev->bq27_itf);
goto err;
@@ -448,7 +446,7 @@ bq27x561_rd_flash(struct bq27z561 *dev, uint16_t addr, uint8_t *buf, int buflen)
i2c.buffer = tmpbuf;
rc = hal_i2c_master_read(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (rd) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (rd) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
bq27z561_itf_unlock(&dev->bq27_itf);
goto err;
@@ -460,7 +458,7 @@ bq27x561_rd_flash(struct bq27z561 *dev, uint16_t addr, uint8_t *buf, int buflen)
addr_read = tmpbuf[0];
addr_read |= ((uint16_t)tmpbuf[1]) << 8;
if (addr_read != addr) {
- BQ27Z561_ERROR("addr mismatch (addr_read=%x addr_ret=%x\n", cmd,
+ BQ27Z561_LOG(ERROR, "addr mismatch (addr_read=%x addr_ret=%x\n", cmd,
cmd_read);
rc = BQ27Z561_ERR_FLASH_ADDR_MISMATCH;
goto err;
@@ -507,7 +505,7 @@ bq27x561_wr_flash(struct bq27z561 *dev, uint16_t addr, uint8_t *buf, int buflen)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
goto err;
}
@@ -524,7 +522,7 @@ bq27x561_wr_flash(struct bq27z561 *dev, uint16_t addr, uint8_t *buf, int buflen)
rc = hal_i2c_master_write(dev->bq27_itf.itf_num, &i2c, OS_TICKS_PER_SEC, 1);
if (rc != 0) {
- BQ27Z561_ERROR("I2C reg read (wr) failed 0x%02X\n", reg);
+ BQ27Z561_LOG(ERROR, "I2C reg read (wr) failed 0x%02X\n", reg);
rc = BQ27Z561_ERR_I2C_ERR;
}
diff --git a/hw/drivers/bq27z561/syscfg.yml b/hw/drivers/bq27z561/syscfg.yml
index 8458e09e4e..edf4474dfd 100644
--- a/hw/drivers/bq27z561/syscfg.yml
+++ b/hw/drivers/bq27z561/syscfg.yml
@@ -27,6 +27,9 @@ syscfg.defs:
BQ27Z561_LOG:
description: 'Enable BQ27Z561 logging'
value: 0
+ BQ27Z561_LOG_MODULE:
+ description: 'Numeric module ID to use for BQ27Z561 log messages'
+ value: 111
BQ27Z561_SHELL_DEV_NAME:
description: 'BQ27Z561 Shell device name'
value: "\"bq27z561_0\""
diff --git a/hw/drivers/chg_ctrl/adp5061/src/adp5061.c b/hw/drivers/chg_ctrl/adp5061/src/adp5061.c
index de52fae0c5..3d936df75d 100644
--- a/hw/drivers/chg_ctrl/adp5061/src/adp5061.c
+++ b/hw/drivers/chg_ctrl/adp5061/src/adp5061.c
@@ -139,6 +139,54 @@ adp5061_set_config(struct adp5061_dev *dev,
return rc;
}
+/**
+ * Lock access to the charge_control_itf specified by cci. Blocks until lock acquired.
+ *
+ * @param The charge_ctrl_itf to lock
+ * @param The timeout
+ *
+ * @return 0 on success, non-zero on failure.
+ */
+static int
+ad5061_itf_lock(struct charge_control_itf *cci, uint32_t timeout)
+{
+ int rc;
+ os_time_t ticks;
+
+ if (!cci->cci_lock) {
+ return 0;
+ }
+
+ rc = os_time_ms_to_ticks(timeout, &ticks);
+ if (rc) {
+ return rc;
+ }
+
+ rc = os_mutex_pend(cci->cci_lock, ticks);
+ if (rc == 0 || rc == OS_NOT_STARTED) {
+ return (0);
+ }
+
+ return (rc);
+}
+
+/**
+ * Unlock access to the charge_control_itf specified by bi.
+ *
+ * @param The charge_control_itf to unlock access to
+ *
+ * @return 0 on success, non-zero on failure.
+ */
+static void
+adp5061_itf_unlock(struct charge_control_itf *cci)
+{
+ if (!cci->cci_lock) {
+ return;
+ }
+
+ os_mutex_release(cci->cci_lock);
+}
+
int
adp5061_get_reg(struct adp5061_dev *dev, uint8_t addr, uint8_t *value)
{
@@ -149,6 +197,12 @@ adp5061_get_reg(struct adp5061_dev *dev, uint8_t addr, uint8_t *value)
.len = 1,
.buffer = &payload
};
+
+ rc = ad5061_itf_lock(&dev->a_chg_ctrl.cc_itf, OS_TIMEOUT_NEVER);
+ if (rc) {
+ return rc;
+ }
+
/* Register write */
payload = addr;
rc = hal_i2c_master_write(dev->a_chg_ctrl.cc_itf.cci_num, &data_struct,
@@ -156,13 +210,17 @@ adp5061_get_reg(struct adp5061_dev *dev, uint8_t addr, uint8_t *value)
if (rc) {
goto err;
}
+
/* Read one byte back */
payload = addr;
rc = hal_i2c_master_read(dev->a_chg_ctrl.cc_itf.cci_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
*value = payload;
+
err:
+ adp5061_itf_unlock(&dev->a_chg_ctrl.cc_itf);
+
return rc;
}
@@ -177,9 +235,16 @@ adp5061_set_reg(struct adp5061_dev *dev, uint8_t addr, uint8_t value)
.buffer = payload
};
+ rc = ad5061_itf_lock(&dev->a_chg_ctrl.cc_itf, OS_TIMEOUT_NEVER);
+ if (rc) {
+ return rc;
+ }
+
rc = hal_i2c_master_write(dev->a_chg_ctrl.cc_itf.cci_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
+ adp5061_itf_unlock(&dev->a_chg_ctrl.cc_itf);
+
return rc;
}
@@ -201,9 +266,16 @@ adp5061_set_regs(struct adp5061_dev *dev, uint8_t addr,
payload[i + 1] = values[i];
}
+ rc = ad5061_itf_lock(&dev->a_chg_ctrl.cc_itf, OS_TIMEOUT_NEVER);
+ if (rc) {
+ return rc;
+ }
+
rc = hal_i2c_master_write(dev->a_chg_ctrl.cc_itf.cci_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
+ adp5061_itf_unlock(&dev->a_chg_ctrl.cc_itf);
+
return rc;
}
@@ -514,6 +586,7 @@ adp5061_init(struct os_dev *dev, void *arg)
{
struct adp5061_dev *adp5061 = (struct adp5061_dev *)dev;
struct charge_control *cc;
+ struct charge_control_itf *cci;
const struct adp5061_config *cfg;
uint8_t device_id;
int rc;
@@ -525,13 +598,14 @@ adp5061_init(struct os_dev *dev, void *arg)
cc = &adp5061->a_chg_ctrl;
+ cci = (struct charge_control_itf *)arg;
+
rc = charge_control_init(cc, dev);
if (rc) {
goto err;
}
- cc->cc_itf.cci_addr = ADP5061_ADDR;
- cc->cc_itf.cci_num = MYNEWT_VAL(ADP5061_I2C_NUM);
- cc->cc_itf.cci_type = CHARGE_CONTROL_ITF_I2C;
+
+ charge_control_set_interface(cc, cci);
/* Add the driver with all the supported types */
rc = charge_control_set_driver(cc, CHARGE_CONTROL_TYPE_STATUS,
@@ -542,11 +616,8 @@ adp5061_init(struct os_dev *dev, void *arg)
charge_control_set_type_mask(cc,
CHARGE_CONTROL_TYPE_STATUS | CHARGE_CONTROL_TYPE_FAULT);
- if (arg) {
- cfg = (struct adp5061_config *)(arg);
- } else {
- cfg = &default_config;
- }
+
+ cfg = &default_config;
rc = adp5061_get_device_id(adp5061, &device_id);
if (rc) {
diff --git a/hw/drivers/debounce/pkg.yml b/hw/drivers/debounce/pkg.yml
index bc76875d7d..f35d722313 100644
--- a/hw/drivers/debounce/pkg.yml
+++ b/hw/drivers/debounce/pkg.yml
@@ -23,4 +23,4 @@ pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - "hw/hal"
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/drivers/drv2605/pkg.yml b/hw/drivers/drv2605/pkg.yml
index 8561f2b52b..38dfa91bfd 100644
--- a/hw/drivers/drv2605/pkg.yml
+++ b/hw/drivers/drv2605/pkg.yml
@@ -32,6 +32,7 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.deps.DRV2605_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/drv2605/src/drv2605.c b/hw/drivers/drv2605/src/drv2605.c
index f36c2b82ce..d3efc13da1 100644
--- a/hw/drivers/drv2605/src/drv2605.c
+++ b/hw/drivers/drv2605/src/drv2605.c
@@ -28,7 +28,7 @@
#include "drv2605_priv.h"
#if MYNEWT_VAL(DRV2605_LOG)
-#include "log/log.h"
+#include "modlog/modlog.h"
#endif
#if MYNEWT_VAL(DRV2605_STATS)
@@ -51,16 +51,12 @@ STATS_SECT_DECL(drv2605_stat_section) g_drv2605stats;
#endif
#if MYNEWT_VAL(DRV2605_LOG)
-#define LOG_MODULE_DRV2605 (306)
-#define DRV2605_INFO(...) LOG_INFO(&_log, LOG_MODULE_DRV2605, __VA_ARGS__)
-#define DRV2605_ERR(...) LOG_ERROR(&_log, LOG_MODULE_DRV2605, __VA_ARGS__)
-static struct log _log;
+#define DRV2605_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(DRV2605_LOG_MODULE), __VA_ARGS__)
#else
-#define DRV2605_INFO(...)
-#define DRV2605_ERR(...)
+#define DRV2605_LOG(lvl_, ...)
#endif
-
/**
* Writes a single byte to the specified register
*
@@ -84,8 +80,9 @@ drv2605_write8(struct sensor_itf *itf, uint8_t reg, uint8_t value)
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC, 1);
if (rc) {
- DRV2605_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
- data_struct.address, reg, value);
+ DRV2605_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
+ data_struct.address, reg, value);
#if MYNEWT_VAL(DRV2605_STATS)
STATS_INC(g_drv2605stats, errors);
#endif
@@ -126,7 +123,8 @@ drv2605_writelen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- DRV2605_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ DRV2605_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
#if MYNEWT_VAL(DRV2605_STATS)
STATS_INC(g_drv2605stats, errors);
#endif
@@ -163,8 +161,9 @@ drv2605_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
payload = reg;
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- DRV2605_ERR("I2C register write failed at address 0x%02X:0x%02X\n",
- data_struct.address, reg);
+ DRV2605_LOG(ERROR,
+ "I2C register write failed at address 0x%02X:0x%02X\n",
+ data_struct.address, reg);
#if MYNEWT_VAL(DRV2605_STATS)
STATS_INC(g_drv2605stats, errors);
#endif
@@ -176,7 +175,8 @@ drv2605_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
*value = payload;
if (rc) {
- DRV2605_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ DRV2605_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
#if MYNEWT_VAL(DRV2605_STATS)
STATS_INC(g_drv2605stats, errors);
#endif
@@ -217,7 +217,8 @@ drv2605_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- DRV2605_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ DRV2605_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
#if MYNEWT_VAL(DRV2605_STATS)
STATS_INC(g_drv2605stats, errors);
#endif
@@ -229,7 +230,8 @@ drv2605_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- DRV2605_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ DRV2605_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
#if MYNEWT_VAL(DRV2605_STATS)
STATS_INC(g_drv2605stats, errors);
#endif
@@ -282,10 +284,6 @@ drv2605_init(struct os_dev *dev, void *arg)
drv2605 = (struct drv2605 *) dev;
-#if MYNEWT_VAL(DRV2605_LOG)
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-#endif
-
sensor = &drv2605->sensor;
#if MYNEWT_VAL(DRV2605_STATS)
@@ -314,7 +312,7 @@ drv2605_init(struct os_dev *dev, void *arg)
/* Check if we can read the chip address */
rc = drv2605_get_chip_id(arg, &id);
if (rc) {
- DRV2605_ERR("unable to get chip id [1]: %d\n", rc);
+ DRV2605_LOG(ERROR, "unable to get chip id [1]: %d\n", rc);
goto err;
}
@@ -323,21 +321,23 @@ drv2605_init(struct os_dev *dev, void *arg)
rc = drv2605_get_chip_id(arg, &id);
if (rc) {
- DRV2605_ERR("unable to get chip id [2]: %d\n", rc);
+ DRV2605_LOG(ERROR, "unable to get chip id [2]: %d\n", rc);
goto err;
}
if (id != DRV2605_STATUS_DEVICE_ID_2605 && id != DRV2605_STATUS_DEVICE_ID_2605L) {
rc = SYS_EINVAL;
- DRV2605_ERR("id not as expected: got: %d, expected %d or %d\n", id,
- DRV2605_STATUS_DEVICE_ID_2605, DRV2605_STATUS_DEVICE_ID_2605L);
+ DRV2605_LOG(ERROR,
+ "id not as expected: got: %d, expected %d or %d\n", id,
+ DRV2605_STATUS_DEVICE_ID_2605,
+ DRV2605_STATUS_DEVICE_ID_2605L);
goto err;
}
}
return (0);
err:
- DRV2605_ERR("Error initializing DRV2605: %d\n", rc);
+ DRV2605_LOG(ERROR, "Error initializing DRV2605: %d\n", rc);
return (rc);
}
diff --git a/hw/drivers/drv2605/syscfg.yml b/hw/drivers/drv2605/syscfg.yml
index 5946ea9bc5..70a14bee0a 100644
--- a/hw/drivers/drv2605/syscfg.yml
+++ b/hw/drivers/drv2605/syscfg.yml
@@ -24,6 +24,9 @@ syscfg.defs:
DRV2605_LOG:
description: 'Enable DRV2605 logging'
value: 0
+ DRV2605_LOG_MODULE:
+ description: 'Numeric module ID to use for DRV2605 log messages'
+ value: 205
DRV2605_STATS:
description: 'Enable DRV2605 statistics'
value: 0
diff --git a/hw/drivers/flash/at45db/pkg.yml b/hw/drivers/flash/at45db/pkg.yml
index fd1d6d1a8c..35d22a1a7a 100644
--- a/hw/drivers/flash/at45db/pkg.yml
+++ b/hw/drivers/flash/at45db/pkg.yml
@@ -24,4 +24,4 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/drivers/flash/spiflash/pkg.yml b/hw/drivers/flash/spiflash/pkg.yml
index 4b575bbd00..406a430a7a 100644
--- a/hw/drivers/flash/spiflash/pkg.yml
+++ b/hw/drivers/flash/spiflash/pkg.yml
@@ -24,4 +24,4 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/drivers/led/lp5523/pkg.yml b/hw/drivers/led/lp5523/pkg.yml
index 51126a1610..ae78f2ca66 100644
--- a/hw/drivers/led/lp5523/pkg.yml
+++ b/hw/drivers/led/lp5523/pkg.yml
@@ -30,10 +30,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/drivers/led"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.deps.LP5523_CLI:
- "@apache-mynewt-core/util/parse"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/led/lp5523/src/lp5523.c b/hw/drivers/led/lp5523/src/lp5523.c
index a0720f0aa1..6ca603b79d 100644
--- a/hw/drivers/led/lp5523/src/lp5523.c
+++ b/hw/drivers/led/lp5523/src/lp5523.c
@@ -19,7 +19,7 @@
#include "os/mynewt.h"
#include <hal/hal_i2c.h>
-#include <log/log.h>
+#include <modlog/modlog.h>
#include <stats/stats.h>
#include <string.h>
@@ -45,10 +45,8 @@ STATS_NAME_END(lp5523_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(lp5523_stat_section) g_lp5523stats;
-#define LOG_MODULE_LP5523 (5523)
-#define LP5523_INFO(...) LOG_INFO(&_log, LOG_MODULE_LP5523, __VA_ARGS__)
-#define LP5523_ERR(...) LOG_ERROR(&_log, LOG_MODULE_LP5523, __VA_ARGS__)
-static struct log _log;
+#define LP5523_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(LP5523_LOG_MODULE), __VA_ARGS__)
int
lp5523_set_reg(struct led_itf *itf, enum lp5523_registers addr,
@@ -72,8 +70,9 @@ lp5523_set_reg(struct led_itf *itf, enum lp5523_registers addr,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LP5523_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
- itf->li_addr, addr, value);
+ LP5523_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
+ itf->li_addr, addr, value);
STATS_INC(g_lp5523stats, read_errors);
}
@@ -103,7 +102,8 @@ lp5523_get_reg(struct led_itf *itf, enum lp5523_registers addr,
rc = hal_i2c_master_write(itf->li_num, &data_struct,
OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- LP5523_ERR("I2C access failed at address 0x%02X\n", itf->li_addr);
+ LP5523_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->li_addr);
STATS_INC(g_lp5523stats, write_errors);
goto err;
}
@@ -114,7 +114,8 @@ lp5523_get_reg(struct led_itf *itf, enum lp5523_registers addr,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LP5523_ERR("Failed to read from 0x%02X:0x%02X\n", itf->li_addr, addr);
+ LP5523_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->li_addr, addr);
STATS_INC(g_lp5523stats, read_errors);
}
@@ -150,7 +151,8 @@ lp5523_set_n_regs(struct led_itf *itf, enum lp5523_registers addr,
(OS_TICKS_PER_SEC / 5), 1);
if (rc) {
- LP5523_ERR("Failed to write to 0x%02X:0x%02X\n", itf->li_addr, regs[0]);
+ LP5523_LOG(ERROR, "Failed to write to 0x%02X:0x%02X\n", itf->li_addr,
+ regs[0]);
STATS_INC(g_lp5523stats, read_errors);
}
@@ -182,7 +184,8 @@ lp5523_get_n_regs(struct led_itf *itf, enum lp5523_registers addr,
(OS_TICKS_PER_SEC / 10), 0);
if (rc) {
- LP5523_ERR("Failed to write to 0x%02X:0x%02X\n", itf->li_addr, addr_b);
+ LP5523_LOG(ERROR, "Failed to write to 0x%02X:0x%02X\n", itf->li_addr,
+ addr_b);
STATS_INC(g_lp5523stats, read_errors);
goto err;
}
@@ -193,8 +196,8 @@ lp5523_get_n_regs(struct led_itf *itf, enum lp5523_registers addr,
OS_TICKS_PER_SEC / 5, 1);
if (rc) {
- LP5523_ERR("Failed to read from 0x%02X:0x%02X\n", itf->li_addr,
- addr_b);
+ LP5523_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n", itf->li_addr,
+ addr_b);
STATS_INC(g_lp5523stats, read_errors);
}
@@ -931,9 +934,6 @@ lp5523_init(struct os_dev *dev, void *arg)
return SYS_ENODEV;
}
- log_register(dev->od_name, &_log, &log_console_handler, NULL,
- LOG_SYSLEVEL);
-
/* Initialise the stats entry */
rc = stats_init(
STATS_HDR(g_lp5523stats),
diff --git a/hw/drivers/led/lp5523/syscfg.yml b/hw/drivers/led/lp5523/syscfg.yml
index 45db86a98f..c61e642756 100644
--- a/hw/drivers/led/lp5523/syscfg.yml
+++ b/hw/drivers/led/lp5523/syscfg.yml
@@ -36,3 +36,6 @@ syscfg.defs:
LP5523_ITF_LOCK_TMO:
description: 'LP5523 interface lock timeout in milliseconds'
value: 1000
+ LP5523_LOG_MODULE:
+ description: 'Numeric module ID to use for LP5523 log messages'
+ value: 105
diff --git a/hw/drivers/lwip/stm32_eth/pkg.yml b/hw/drivers/lwip/stm32_eth/pkg.yml
index 56e8890297..4b26020c7f 100644
--- a/hw/drivers/lwip/stm32_eth/pkg.yml
+++ b/hw/drivers/lwip/stm32_eth/pkg.yml
@@ -26,14 +26,14 @@ pkg.keywords:
- lwip
- ethernet
pkg.deps:
- - hw/hal
- - net/ip/lwip_base
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/net/ip/lwip_base"
pkg.deps.MCU_STM32F4:
- - hw/mcu/stm/stm32f4xx
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f4xx"
pkg.deps.MCU_STM32F7:
- - hw/mcu/stm/stm32f7xx
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx"
pkg.req_apis:
diff --git a/hw/drivers/mmc/pkg.yml b/hw/drivers/mmc/pkg.yml
index 4101718437..e29902f5d3 100644
--- a/hw/drivers/mmc/pkg.yml
+++ b/hw/drivers/mmc/pkg.yml
@@ -24,4 +24,4 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/drivers/pwm/pwm_nrf52/pkg.yml b/hw/drivers/pwm/pwm_nrf52/pkg.yml
index bf5385e2c8..1a67fa9893 100644
--- a/hw/drivers/pwm/pwm_nrf52/pkg.yml
+++ b/hw/drivers/pwm/pwm_nrf52/pkg.yml
@@ -26,5 +26,5 @@ pkg.keywords:
pkg.apis:
- PWM_HW_IMPL
pkg.deps:
- - hw/drivers/pwm
- - hw/mcu/nordic
+ - "@apache-mynewt-core/hw/drivers/pwm"
+ - "@apache-mynewt-core/hw/mcu/nordic"
diff --git a/hw/drivers/pwm/pwm_stm32/pkg.yml b/hw/drivers/pwm/pwm_stm32/pkg.yml
index 85544ad9da..64193cad6f 100644
--- a/hw/drivers/pwm/pwm_stm32/pkg.yml
+++ b/hw/drivers/pwm/pwm_stm32/pkg.yml
@@ -27,10 +27,10 @@ pkg.apis:
- PWM_HW_IMPL
pkg.deps:
- - hw/drivers/pwm
+ - "@apache-mynewt-core/hw/drivers/pwm"
pkg.deps.MCU_STM32F3:
- - hw/mcu/stm/stm32f3xx
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f3xx"
pkg.deps.MCU_STM32F7:
- - hw/mcu/stm/stm32f7xx
+ - "@apache-mynewt-core/hw/mcu/stm/stm32f7xx"
diff --git a/hw/drivers/rtt/syscfg.yml b/hw/drivers/rtt/syscfg.yml
index 08f410a9cb..db77c6f015 100644
--- a/hw/drivers/rtt/syscfg.yml
+++ b/hw/drivers/rtt/syscfg.yml
@@ -52,8 +52,10 @@ syscfg.defs:
# Values below are deprecated and only used for backwards compatibility.
# Please use new values instead.
RTT_BUFFER_SIZE_UP:
- description: 'Size of the output buffer'
+ description: 'Use RTT_TERMINAL_BUFFER_SIZE_UP instead'
+ deprecated: 1
value: 1024
RTT_BUFFER_SIZE_DOWN:
- description: 'Size of the input buffer'
+ description: 'Use RTT_TERMINAL_BUFFER_SIZE_DOWN instead'
+ deprecated: 1
value: 16
diff --git a/hw/drivers/sensors/adxl345/pkg.yml b/hw/drivers/sensors/adxl345/pkg.yml
index 8b2ac91da8..c54e8baf60 100644
--- a/hw/drivers/sensors/adxl345/pkg.yml
+++ b/hw/drivers/sensors/adxl345/pkg.yml
@@ -31,10 +31,10 @@ pkg.deps:
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.ADXL345_CLI:
- - "@apache-mynewt-core/util/parse"
\ No newline at end of file
+ - "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/adxl345/src/adxl345.c b/hw/drivers/sensors/adxl345/src/adxl345.c
index 92e2ba13bd..813c12d5fb 100644
--- a/hw/drivers/sensors/adxl345/src/adxl345.c
+++ b/hw/drivers/sensors/adxl345/src/adxl345.c
@@ -30,7 +30,7 @@
#include "sensor/accel.h"
#include "adxl345/adxl345.h"
#include "adxl345_priv.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -57,10 +57,8 @@ STATS_NAME_END(adxl345_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(adxl345_stat_section) g_adxl345stats;
-#define LOG_MODULE_ADXL345 (345)
-#define ADXL345_INFO(...) LOG_INFO(&_log, LOG_MODULE_ADXL345, __VA_ARGS__)
-#define ADXL345_ERR(...) LOG_ERROR(&_log, LOG_MODULE_ADXL345, __VA_ARGS__)
-static struct log _log;
+#define ADXL345_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(ADXL345_LOG_MODULE), __VA_ARGS__)
#define ADXL345_NOTIFY_MASK 0x01
#define ADXL345_READ_MASK 0x02
@@ -128,7 +126,8 @@ adxl345_i2c_write8(struct sensor_itf *itf, uint8_t reg, uint8_t value)
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- ADXL345_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
+ ADXL345_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
itf->si_addr, reg, value);
STATS_INC(g_adxl345stats, read_errors);
}
@@ -160,7 +159,9 @@ adxl345_i2c_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- ADXL345_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ ADXL345_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr)
+
STATS_INC(g_adxl345stats, write_errors);
return rc;
}
@@ -171,7 +172,8 @@ adxl345_i2c_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- ADXL345_ERR("Failed to read from 0x%02X:0x%02X - %02X\n", itf->si_addr, reg, rc);
+ ADXL345_LOG(ERROR, "Failed to read from 0x%02X:0x%02X - %02X\n",
+ itf->si_addr, reg, rc);
STATS_INC(g_adxl345stats, read_errors);
}
return rc;
@@ -202,7 +204,8 @@ adxl345_i2c_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8_
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- ADXL345_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ ADXL345_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr);
STATS_INC(g_adxl345stats, write_errors);
return rc;
}
@@ -214,7 +217,8 @@ adxl345_i2c_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8_
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- ADXL345_ERR("Failed to read from 0x%02X:0x%02X\n", itf->si_addr, reg);
+ ADXL345_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->si_addr, reg);
STATS_INC(g_adxl345stats, read_errors);
}
@@ -242,8 +246,8 @@ adxl345_spi_write8(struct sensor_itf *itf, uint8_t reg, uint8_t value)
rc = hal_spi_tx_val(itf->si_num, reg & ~ADXL345_SPI_READ_CMD_BIT);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- ADXL345_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ ADXL345_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_adxl345stats, write_errors);
goto err;
}
@@ -252,8 +256,8 @@ adxl345_spi_write8(struct sensor_itf *itf, uint8_t reg, uint8_t value)
rc = hal_spi_tx_val(itf->si_num, value);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- ADXL345_ERR("SPI_%u write failed addr:0x%02X\n",
- itf->si_num, reg);
+ ADXL345_LOG(ERROR, "SPI_%u write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_adxl345stats, write_errors);
goto err;
}
@@ -291,8 +295,8 @@ adxl345_spi_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- ADXL345_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ ADXL345_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_adxl345stats, read_errors);
goto err;
}
@@ -301,8 +305,8 @@ adxl345_spi_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- ADXL345_ERR("SPI_%u read failed addr:0x%02X\n",
- itf->si_num, reg);
+ ADXL345_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_adxl345stats, read_errors);
goto err;
}
@@ -342,8 +346,8 @@ adxl345_spi_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- ADXL345_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ ADXL345_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_adxl345stats, read_errors);
goto err;
}
@@ -353,8 +357,8 @@ adxl345_spi_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- ADXL345_ERR("SPI_%u read failed addr:0x%02X\n",
- itf->si_num, reg);
+ ADXL345_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_adxl345stats, read_errors);
goto err;
}
@@ -859,7 +863,7 @@ adxl345_set_act_inact_enables(struct sensor_itf *itf, struct adxl345_act_inact_e
reg |= cfg.act_x ? (1 << 6) : 0;
reg |= cfg.act_ac_dc ? (1 << 7) : 0;
- ADXL345_ERR("act_inact = 0x%x\n", reg);
+ ADXL345_LOG(ERROR, "act_inact = 0x%x\n", reg);
return adxl345_write8(itf, ADXL345_ACT_INACT_CTL, reg);
@@ -1379,7 +1383,7 @@ init_intpin(struct adxl345 * adxl345, hal_gpio_irq_handler_t handler,
}
if (pin < 0) {
- ADXL345_ERR("Interrupt pin not configured\n");
+ ADXL345_LOG(ERROR, "Interrupt pin not configured\n");
return SYS_EINVAL;
}
@@ -1395,7 +1399,7 @@ init_intpin(struct adxl345 * adxl345, hal_gpio_irq_handler_t handler,
} else if (adxl345->sensor.s_itf.si_ints[pdd->int_num].device_pin == 2) {
pdd->int_route = 0xFF;
} else {
- ADXL345_ERR("Route not configured\n");
+ ADXL345_LOG(ERROR, "Route not configured\n");
return SYS_EINVAL;
}
@@ -1405,7 +1409,7 @@ init_intpin(struct adxl345 * adxl345, hal_gpio_irq_handler_t handler,
trig,
HAL_GPIO_PULL_NONE);
if (rc != 0) {
- ADXL345_ERR("Failed to initialise interrupt pin %d\n", pin);
+ ADXL345_LOG(ERROR, "Failed to initialise interrupt pin %d\n", pin);
return rc;
}
@@ -1508,7 +1512,7 @@ adxl345_sensor_handle_interrupt(struct sensor * sensor)
rc = adxl345_clear_interrupts(itf, &int_status);
if (rc != 0) {
- ADXL345_ERR("Cound not read int status err=0x%02x\n", rc);
+ ADXL345_LOG(ERROR, "Cound not read int status err=0x%02x\n", rc);
return rc;
}
@@ -1525,7 +1529,7 @@ adxl345_sensor_handle_interrupt(struct sensor * sensor)
if ((pdd->registered_mask & ADXL345_READ_MASK) &&
((int_status & ADXL345_INT_ACTIVITY_BIT) ||
(int_status & ADXL345_INT_INACTIVITY_BIT))) {
- ADXL345_ERR("READ EVT 0x%02x\n", int_status);
+ ADXL345_LOG(ERROR, "READ EVT 0x%02x\n", int_status);
sensor_mgr_put_read_evt(&pdd->read_ctx);
}
@@ -1737,7 +1741,7 @@ adxl345_sensor_set_notification(struct sensor * sensor,
struct adxl345_private_driver_data *pdd;
int rc;
- ADXL345_ERR("Enabling notifications\n");
+ ADXL345_LOG(ERROR, "Enabling notifications\n");
if ((sensor_event_type & ~(SENSOR_EVENT_TYPE_DOUBLE_TAP |
SENSOR_EVENT_TYPE_SINGLE_TAP)) != 0) {
@@ -1773,7 +1777,7 @@ adxl345_sensor_set_notification(struct sensor * sensor,
pdd->notify_ctx.snec_evtype |= sensor_event_type;
pdd->registered_mask |= ADXL345_NOTIFY_MASK;
- ADXL345_ERR("Enabled notifications\n");
+ ADXL345_LOG(ERROR, "Enabled notifications\n");
return 0;
#else
diff --git a/hw/drivers/sensors/adxl345/syscfg.yml b/hw/drivers/sensors/adxl345/syscfg.yml
index 46585013f9..85971c2e0d 100644
--- a/hw/drivers/sensors/adxl345/syscfg.yml
+++ b/hw/drivers/sensors/adxl345/syscfg.yml
@@ -50,3 +50,6 @@ syscfg.defs:
ADXL345_ITF_LOCK_TMO:
description: 'ADXL345 interface lock timeout in milliseconds'
value: 1000
+ ADXL345_LOG_MODULE:
+ description: 'Numeric module ID to use for ADXL345 log messages'
+ value: 75
diff --git a/hw/drivers/sensors/bma253/pkg.yml b/hw/drivers/sensors/bma253/pkg.yml
index d1c7a2a713..871402583b 100644
--- a/hw/drivers/sensors/bma253/pkg.yml
+++ b/hw/drivers/sensors/bma253/pkg.yml
@@ -28,10 +28,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.BMA253_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/bma253/src/bma253.c b/hw/drivers/sensors/bma253/src/bma253.c
index 80e08bcfac..e99523fedd 100644
--- a/hw/drivers/sensors/bma253/src/bma253.c
+++ b/hw/drivers/sensors/bma253/src/bma253.c
@@ -29,17 +29,15 @@
#include <syscfg/syscfg.h>
#if MYNEWT_VAL(BMA253_LOG)
-#include "log/log.h"
+#include "modlog/modlog.h"
#endif
#if MYNEWT_VAL(BMA253_LOG)
-static struct log bma253_log;
-#define LOG_MODULE_BMA253 (253)
-#define BMA253_ERROR(...) LOG_ERROR(&bma253_log, LOG_MODULE_BMA253, __VA_ARGS__)
-#define BMA253_INFO(...) LOG_INFO(&bma253_log, LOG_MODULE_BMA253, __VA_ARGS__)
+
+#define BMA253_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(BMA253_LOG_MODULE), __VA_ARGS__)
#else
-#define BMA253_ERROR(...)
-#define BMA253_INFO(...)
+#define BMA253_LOG(lvl_, ...)
#endif
#define BMA253_NOTIFY_MASK 0x01
@@ -168,7 +166,7 @@ get_register(struct bma253 * bma253,
rc = hal_i2c_master_write(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA253_ERROR("I2C access failed at address 0x%02X\n", addr);
+ BMA253_LOG(ERROR, "I2C access failed at address 0x%02X\n", addr);
goto err;
}
@@ -179,8 +177,8 @@ get_register(struct bma253 * bma253,
rc = hal_i2c_master_read(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA253_ERROR("I2C read failed at address 0x%02X single byte\n",
- addr);
+ BMA253_LOG(ERROR, "I2C read failed at address 0x%02X single byte\n",
+ addr);
}
err:
@@ -213,8 +211,8 @@ get_registers(struct bma253 * bma253,
rc = hal_i2c_master_write(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA253_ERROR("I2C access failed at address 0x%02X\n",
- addr);
+ BMA253_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ addr);
goto err;
}
@@ -225,8 +223,8 @@ get_registers(struct bma253 * bma253,
rc = hal_i2c_master_read(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA253_ERROR("I2C read failed at address 0x%02X length %u\n",
- addr, size);
+ BMA253_LOG(ERROR, "I2C read failed at address 0x%02X length %u\n",
+ addr, size);
}
err:
@@ -262,8 +260,8 @@ set_register(struct bma253 * bma253,
rc = hal_i2c_master_write(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA253_ERROR("I2C write failed at address 0x%02X single byte\n",
- addr);
+ BMA253_LOG(ERROR, "I2C write failed at address 0x%02X single byte\n",
+ addr);
}
switch (bma253->power) {
@@ -380,8 +378,8 @@ quad_to_axis_trigger(struct axis_trigger * axis_trigger,
axis_trigger->sign = (quad_bits >> 3) & 0x01;
switch (quad_bits & 0x07) {
default:
- BMA253_ERROR("unknown %s quad bits 0x%02X\n",
- name_bits, quad_bits);
+ BMA253_LOG(ERROR, "unknown %s quad bits 0x%02X\n",
+ name_bits, quad_bits);
case 0x00:
axis_trigger->axis = -1;
axis_trigger->axis_known = false;
@@ -471,7 +469,7 @@ bma253_get_g_range(const struct bma253 * bma253,
switch (data & 0x0F) {
default:
- BMA253_ERROR("unknown PMU_RANGE reg value 0x%02X\n", data);
+ BMA253_LOG(ERROR, "unknown PMU_RANGE reg value 0x%02X\n", data);
*g_range = BMA253_G_RANGE_16;
break;
case 0x03:
@@ -612,7 +610,7 @@ bma253_get_power_settings(const struct bma253 * bma253,
switch ((data[0] >> 5) & 0x07) {
default:
- BMA253_ERROR("unknown PMU_LPW reg value 0x%02X\n", data[0]);
+ BMA253_LOG(ERROR, "unknown PMU_LPW reg value 0x%02X\n", data[0]);
power_settings->power_mode = BMA253_POWER_MODE_NORMAL;
break;
case 0x00:
@@ -2624,7 +2622,7 @@ bma253_get_fifo_cfg(const struct bma253 * bma253,
switch ((data >> 6) & 0x03) {
case 0x03:
- BMA253_ERROR("unknown FIFO_CONFIG_1 reg value 0x%02X\n", data);
+ BMA253_LOG(ERROR, "unknown FIFO_CONFIG_1 reg value 0x%02X\n", data);
case 0x00:
fifo_cfg->fifo_mode = FIFO_MODE_BYPASS;
break;
@@ -3071,7 +3069,7 @@ init_intpin(struct bma253 * bma253,
}
if (pin < 0) {
- BMA253_ERROR("Interrupt pin not configured\n");
+ BMA253_LOG(ERROR, "Interrupt pin not configured\n");
return SYS_EINVAL;
}
@@ -3087,7 +3085,7 @@ init_intpin(struct bma253 * bma253,
} else if (bma253->sensor.s_itf.si_ints[pdd->int_num].device_pin == 2) {
pdd->int_route = INT_ROUTE_PIN_2;
} else {
- BMA253_ERROR("Route not configured\n");
+ BMA253_LOG(ERROR, "Route not configured\n");
return SYS_EINVAL;
}
@@ -3371,7 +3369,7 @@ axis_offset_compensation(const struct bma253 * bma253,
}
if (!ready) {
- BMA253_ERROR("offset compensation already in progress\n");
+ BMA253_LOG(ERROR, "offset compensation already in progress\n");
return SYS_ETIMEOUT;
}
@@ -3396,7 +3394,7 @@ axis_offset_compensation(const struct bma253 * bma253,
}
if (count == 0) {
- BMA253_ERROR("offset compensation did not complete\n");
+ BMA253_LOG(ERROR, "offset compensation did not complete\n");
return SYS_ETIMEOUT;
}
@@ -3515,15 +3513,15 @@ bma253_query_offsets(struct bma253 * bma253,
mismatch = false;
if (cfg->offset_x_g != val_offset_x_g) {
- BMA253_ERROR("X compensation offset value mismatch\n");
+ BMA253_LOG(ERROR, "X compensation offset value mismatch\n");
mismatch = true;
}
if (cfg->offset_y_g != val_offset_y_g) {
- BMA253_ERROR("Y compensation offset value mismatch\n");
+ BMA253_LOG(ERROR, "Y compensation offset value mismatch\n");
mismatch = true;
}
if (cfg->offset_z_g != val_offset_z_g) {
- BMA253_ERROR("Z compensation offset value mismatch\n");
+ BMA253_LOG(ERROR, "Z compensation offset value mismatch\n");
mismatch = true;
}
@@ -3837,7 +3835,7 @@ bma253_wait_for_orient(struct bma253 * bma253,
pdd = &bma253->pdd;
if (pdd->interrupt) {
- BMA253_ERROR("Interrupt used\n");
+ BMA253_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -3914,7 +3912,7 @@ bma253_wait_for_high_g(struct bma253 * bma253)
pdd = &bma253->pdd;
if (pdd->interrupt) {
- BMA253_ERROR("Interrupt used\n");
+ BMA253_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -3986,7 +3984,7 @@ bma253_wait_for_low_g(struct bma253 * bma253)
pdd = &bma253->pdd;
if (pdd->interrupt) {
- BMA253_ERROR("Interrupt used\n");
+ BMA253_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -4089,7 +4087,7 @@ bma253_wait_for_tap(struct bma253 * bma253,
}
if (pdd->interrupt) {
- BMA253_ERROR("Interrupt used\n");
+ BMA253_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -4633,7 +4631,7 @@ sensor_driver_handle_interrupt(struct sensor * sensor)
rc = bma253_get_int_status(bma253, &int_status);
if (rc != 0) {
- BMA253_ERROR("Cound not read int status err=0x%02x\n", rc);
+ BMA253_LOG(ERROR, "Cound not read int status err=0x%02x\n", rc);
return rc;
}
@@ -4684,7 +4682,7 @@ bma253_config(struct bma253 * bma253, struct bma253_cfg * cfg)
return rc;
}
if (chip_id != REG_VALUE_CHIP_ID) {
- BMA253_ERROR("received incorrect chip ID 0x%02X\n", chip_id);
+ BMA253_LOG(ERROR, "received incorrect chip ID 0x%02X\n", chip_id);
return SYS_EINVAL;
}
@@ -4720,17 +4718,6 @@ bma253_init(struct os_dev * dev, void * arg)
return SYS_ENODEV;
}
-#if MYNEWT_VAL(BMA253_LOG)
- rc = log_register(dev->od_name,
- &bma253_log,
- &log_console_handler,
- NULL,
- LOG_SYSLEVEL);
- if (rc != 0) {
- return rc;
- }
-#endif
-
bma253 = (struct bma253 *)dev;
sensor = &bma253->sensor;
diff --git a/hw/drivers/sensors/bma253/syscfg.yml b/hw/drivers/sensors/bma253/syscfg.yml
index 16c725d1dc..2bcb66e78b 100644
--- a/hw/drivers/sensors/bma253/syscfg.yml
+++ b/hw/drivers/sensors/bma253/syscfg.yml
@@ -48,6 +48,9 @@ syscfg.defs:
BMA253_LOG:
description: 'Enable BMA253 logging'
value: 0
+ BMA253_LOG_MODULE:
+ description: 'Numeric module ID to use for BMA253 log messages'
+ value: 253
BMA253_SHELL_DEV_NAME:
description: 'BMA253 Shell device name'
value: "\"bma253_0\""
diff --git a/hw/drivers/sensors/bma2xx/pkg.yml b/hw/drivers/sensors/bma2xx/pkg.yml
index aaf26ad385..537137a5d3 100644
--- a/hw/drivers/sensors/bma2xx/pkg.yml
+++ b/hw/drivers/sensors/bma2xx/pkg.yml
@@ -29,10 +29,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.BMA2XX_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/bma2xx/src/bma2xx.c b/hw/drivers/sensors/bma2xx/src/bma2xx.c
index 624bd38667..173e46032c 100644
--- a/hw/drivers/sensors/bma2xx/src/bma2xx.c
+++ b/hw/drivers/sensors/bma2xx/src/bma2xx.c
@@ -32,17 +32,13 @@
#include <syscfg/syscfg.h>
#if MYNEWT_VAL(BMA2XX_LOG)
-#include "log/log.h"
+#include "modlog/modlog.h"
#endif
-#if MYNEWT_VAL(BMA2XX_LOG)
-static struct log bma2xx_log;
-#define LOG_MODULE_BMA2XX (200)
-#define BMA2XX_ERROR(...) LOG_ERROR(&bma2xx_log, LOG_MODULE_BMA2XX, __VA_ARGS__)
-#define BMA2XX_INFO(...) LOG_INFO(&bma2xx_log, LOG_MODULE_BMA2XX, __VA_ARGS__)
+#define BMA2XX_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(BMA2XX_LOG_MODULE), __VA_ARGS__)
#else
-#define BMA2XX_ERROR(...)
-#define BMA2XX_INFO(...)
+#define BMA2XX_LOG(lvl_, ...)
#endif
#define BMA2XX_NOTIFY_MASK 0x01
@@ -183,8 +179,8 @@ spi_readlen(struct sensor_itf * itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, addr | BMA2XX_SPI_READ_CMD_BIT);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- BMA2XX_ERROR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, addr);
+ BMA2XX_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, addr);
goto err;
}
@@ -193,8 +189,8 @@ spi_readlen(struct sensor_itf * itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- BMA2XX_ERROR("SPI_%u read failed addr:0x%02X\n",
- itf->si_num, addr);
+ BMA2XX_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
+ itf->si_num, addr);
goto err;
}
payload[i] = retval;
@@ -232,8 +228,8 @@ spi_writereg(struct sensor_itf * itf, uint8_t addr, uint8_t payload,
rc = hal_spi_tx_val(itf->si_num, addr);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- BMA2XX_ERROR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, addr);
+ BMA2XX_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, addr);
goto err;
}
@@ -242,8 +238,8 @@ spi_writereg(struct sensor_itf * itf, uint8_t addr, uint8_t payload,
rc = hal_spi_tx_val(itf->si_num, payload);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- BMA2XX_ERROR("SPI_%u write failed addr:0x%02X:0x%02X\n",
- itf->si_num, addr);
+ BMA2XX_LOG(ERROR, "SPI_%u write failed addr:0x%02X:0x%02X\n",
+ itf->si_num, addr);
goto err;
}
}
@@ -274,8 +270,7 @@ i2c_readlen(struct sensor_itf * itf, uint8_t addr, uint8_t *payload,
rc = hal_i2c_master_write(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA2XX_ERROR("I2C access failed at address 0x%02X\n",
- addr);
+ BMA2XX_LOG(ERROR, "I2C access failed at address 0x%02X\n", addr);
return rc;
}
@@ -286,8 +281,8 @@ i2c_readlen(struct sensor_itf * itf, uint8_t addr, uint8_t *payload,
rc = hal_i2c_master_read(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA2XX_ERROR("I2C read failed at address 0x%02X length %u\n",
- addr, len);
+ BMA2XX_LOG(ERROR, "I2C read failed at address 0x%02X length %u\n",
+ addr, len);
return rc;
}
@@ -311,8 +306,8 @@ i2c_writereg(struct sensor_itf * itf, uint8_t addr, uint8_t data)
rc = hal_i2c_master_write(itf->si_num, &oper,
OS_TICKS_PER_SEC / 10, 1);
if (rc != 0) {
- BMA2XX_ERROR("I2C write failed at address 0x%02X single byte\n",
- addr);
+ BMA2XX_LOG(ERROR, "I2C write failed at address 0x%02X single byte\n",
+ addr);
return rc;
}
@@ -572,8 +567,8 @@ quad_to_axis_trigger(struct axis_trigger * axis_trigger,
axis_trigger->sign = (quad_bits >> 3) & 0x01;
switch (quad_bits & 0x07) {
default:
- BMA2XX_ERROR("unknown %s quad bits 0x%02X\n",
- name_bits, quad_bits);
+ BMA2XX_LOG(ERROR, "unknown %s quad bits 0x%02X\n",
+ name_bits, quad_bits);
case 0x00:
axis_trigger->axis = -1;
axis_trigger->axis_known = false;
@@ -663,7 +658,7 @@ bma2xx_get_g_range(struct bma2xx *bma2xx,
switch (data & 0x0F) {
default:
- BMA2XX_ERROR("unknown PMU_RANGE reg value 0x%02X\n", data);
+ BMA2XX_LOG(ERROR, "unknown PMU_RANGE reg value 0x%02X\n", data);
*g_range = BMA2XX_G_RANGE_16;
break;
case 0x03:
@@ -823,7 +818,7 @@ bma2xx_get_power_settings(struct bma2xx *bma2xx,
switch ((data[0] >> 5) & 0x07) {
default:
- BMA2XX_ERROR("unknown PMU_LPW reg value 0x%02X\n", data[0]);
+ BMA2XX_LOG(ERROR, "unknown PMU_LPW reg value 0x%02X\n", data[0]);
power_settings->power_mode = BMA2XX_POWER_MODE_NORMAL;
break;
case 0x00:
@@ -2835,7 +2830,7 @@ bma2xx_get_fifo_cfg(struct bma2xx *bma2xx,
switch ((data >> 6) & 0x03) {
case 0x03:
- BMA2XX_ERROR("unknown FIFO_CONFIG_1 reg value 0x%02X\n", data);
+ BMA2XX_LOG(ERROR, "unknown FIFO_CONFIG_1 reg value 0x%02X\n", data);
case 0x00:
fifo_cfg->fifo_mode = FIFO_MODE_BYPASS;
break;
@@ -3271,7 +3266,7 @@ init_intpin(struct bma2xx *bma2xx,
}
if (pin < 0) {
- BMA2XX_ERROR("Interrupt pin not configured\n");
+ BMA2XX_LOG(ERROR, "Interrupt pin not configured\n");
return SYS_EINVAL;
}
@@ -3287,7 +3282,7 @@ init_intpin(struct bma2xx *bma2xx,
} else if (bma2xx->sensor.s_itf.si_ints[pdd->int_num].device_pin == 2) {
pdd->int_route = INT_ROUTE_PIN_2;
} else {
- BMA2XX_ERROR("Route not configured\n");
+ BMA2XX_LOG(ERROR, "Route not configured\n");
return SYS_EINVAL;
}
@@ -3571,7 +3566,7 @@ axis_offset_compensation(struct bma2xx *bma2xx,
}
if (!ready) {
- BMA2XX_ERROR("offset compensation already in progress\n");
+ BMA2XX_LOG(ERROR, "offset compensation already in progress\n");
return SYS_ETIMEOUT;
}
@@ -3596,7 +3591,7 @@ axis_offset_compensation(struct bma2xx *bma2xx,
}
if (count == 0) {
- BMA2XX_ERROR("offset compensation did not complete\n");
+ BMA2XX_LOG(ERROR, "offset compensation did not complete\n");
return SYS_ETIMEOUT;
}
@@ -3715,15 +3710,15 @@ bma2xx_query_offsets(struct bma2xx *bma2xx,
mismatch = false;
if (cfg->offset_x_g != val_offset_x_g) {
- BMA2XX_ERROR("X compensation offset value mismatch\n");
+ BMA2XX_LOG(ERROR, "X compensation offset value mismatch\n");
mismatch = true;
}
if (cfg->offset_y_g != val_offset_y_g) {
- BMA2XX_ERROR("Y compensation offset value mismatch\n");
+ BMA2XX_LOG(ERROR, "Y compensation offset value mismatch\n");
mismatch = true;
}
if (cfg->offset_z_g != val_offset_z_g) {
- BMA2XX_ERROR("Z compensation offset value mismatch\n");
+ BMA2XX_LOG(ERROR, "Z compensation offset value mismatch\n");
mismatch = true;
}
@@ -4029,7 +4024,7 @@ bma2xx_wait_for_orient(struct bma2xx *bma2xx,
pdd = &bma2xx->pdd;
if (pdd->interrupt) {
- BMA2XX_ERROR("Interrupt used\n");
+ BMA2XX_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -4106,7 +4101,7 @@ bma2xx_wait_for_high_g(struct bma2xx *bma2xx)
pdd = &bma2xx->pdd;
if (pdd->interrupt) {
- BMA2XX_ERROR("Interrupt used\n");
+ BMA2XX_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -4178,7 +4173,7 @@ bma2xx_wait_for_low_g(struct bma2xx *bma2xx)
pdd = &bma2xx->pdd;
if (pdd->interrupt) {
- BMA2XX_ERROR("Interrupt used\n");
+ BMA2XX_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -4281,7 +4276,7 @@ bma2xx_wait_for_tap(struct bma2xx *bma2xx,
}
if (pdd->interrupt) {
- BMA2XX_ERROR("Interrupt used\n");
+ BMA2XX_LOG(ERROR, "Interrupt used\n");
return SYS_EINVAL;
}
@@ -4791,7 +4786,7 @@ sensor_driver_handle_interrupt(struct sensor * sensor)
rc = bma2xx_get_int_status(bma2xx, &int_status);
if (rc != 0) {
- BMA2XX_ERROR("Cound not read int status err=0x%02x\n", rc);
+ BMA2XX_LOG(ERROR, "Cound not read int status err=0x%02x\n", rc);
return rc;
}
@@ -4853,7 +4848,7 @@ bma2xx_config(struct bma2xx *bma2xx, struct bma2xx_cfg *cfg)
}
if (chip_id != model_chip_id) {
- BMA2XX_ERROR("received incorrect chip ID 0x%02X\n", chip_id);
+ BMA2XX_LOG(ERROR, "received incorrect chip ID 0x%02X\n", chip_id);
return SYS_EINVAL;
}
@@ -4889,17 +4884,6 @@ bma2xx_init(struct os_dev * dev, void * arg)
return SYS_ENODEV;
}
-#if MYNEWT_VAL(BMA2XX_LOG)
- rc = log_register(dev->od_name,
- &bma2xx_log,
- &log_console_handler,
- NULL,
- LOG_SYSLEVEL);
- if (rc != 0) {
- return rc;
- }
-#endif
-
bma2xx = (struct bma2xx *)dev;
sensor = &bma2xx->sensor;
diff --git a/hw/drivers/sensors/bma2xx/syscfg.yml b/hw/drivers/sensors/bma2xx/syscfg.yml
index 3b45c848e0..1d0195f655 100644
--- a/hw/drivers/sensors/bma2xx/syscfg.yml
+++ b/hw/drivers/sensors/bma2xx/syscfg.yml
@@ -42,6 +42,9 @@ syscfg.defs:
BMA2XX_LOG:
description: 'Enable BMA2XX logging'
value: 0
+ BMA2XX_LOG_MODULE:
+ description: 'Numeric module ID to use for BMA2XX log messages'
+ value: 200
BMA2XX_SHELL_DEV_NAME:
description: 'BMA2XX Shell device name'
value: "\"bma2xx_0\""
diff --git a/hw/drivers/sensors/bme280/pkg.yml b/hw/drivers/sensors/bme280/pkg.yml
index bf98f70c4d..22a0a6b710 100644
--- a/hw/drivers/sensors/bme280/pkg.yml
+++ b/hw/drivers/sensors/bme280/pkg.yml
@@ -31,10 +31,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.BME280_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/bme280/src/bme280.c b/hw/drivers/sensors/bme280/src/bme280.c
index 53c23b485a..67a0adee0a 100644
--- a/hw/drivers/sensors/bme280/src/bme280.c
+++ b/hw/drivers/sensors/bme280/src/bme280.c
@@ -31,7 +31,7 @@
#include "sensor/pressure.h"
#include "bme280_priv.h"
#include "hal/hal_gpio.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#ifndef MATHLIB_SUPPORT
@@ -62,10 +62,8 @@ STATS_NAME_END(bme280_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(bme280_stat_section) g_bme280stats;
-#define LOG_MODULE_BME280 (280)
-#define BME280_INFO(...) LOG_INFO(&_log, LOG_MODULE_BME280, __VA_ARGS__)
-#define BME280_ERR(...) LOG_ERROR(&_log, LOG_MODULE_BME280, __VA_ARGS__)
-static struct log _log;
+#define BME280_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(BME280_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int bme280_sensor_read(struct sensor *, sensor_type_t,
@@ -122,8 +120,6 @@ bme280_init(struct os_dev *dev, void *arg)
goto err;
}
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &bme280->sensor;
/* Initialise the stats entry */
@@ -200,7 +196,7 @@ bme280_compensate_temperature(int32_t rawtemp, struct bme280_pdd *pdd)
double var1, var2, comptemp;
if (rawtemp == 0x800000) {
- BME280_ERR("Invalid temp data\n");
+ BME280_LOG(ERROR, "Invalid temp data\n");
STATS_INC(g_bme280stats, invalid_data_errors);
return NAN;
}
@@ -235,7 +231,7 @@ bme280_compensate_pressure(struct sensor_itf *itf, int32_t rawpress,
int32_t temp;
if (rawpress == 0x800000) {
- BME280_ERR("Invalid press data\n");
+ BME280_LOG(ERROR, "Invalid press data\n");
STATS_INC(g_bme280stats, invalid_data_errors);
return NAN;
}
@@ -286,7 +282,7 @@ bme280_compensate_humidity(struct sensor_itf *itf, int32_t rawhumid,
int32_t temp;
if (rawhumid == 0x8000) {
- BME280_ERR("Invalid humidity data\n");
+ BME280_LOG(ERROR, "Invalid humidity data\n");
STATS_INC(g_bme280stats, invalid_data_errors);
return NAN;
}
@@ -330,7 +326,7 @@ bme280_compensate_temperature(int32_t rawtemp, struct bme280_pdd *pdd)
int32_t var1, var2, comptemp;
if (rawtemp == 0x800000) {
- BME280_ERR("Invalid temp data\n");
+ BME280_LOG(ERROR, "Invalid temp data\n");
STATS_INC(g_bme280stats, invalid_data_errors);
return NAN;
}
@@ -367,7 +363,7 @@ bme280_compensate_pressure(struct sensor_itf *itf, int32_t rawpress,
int32_t temp;
if (rawpress == 0x800000) {
- BME280_ERR("Invalid pressure data\n");
+ BME280_LOG(ERROR, "Invalid pressure data\n");
STATS_INC(g_bme280stats, invalid_data_errors);
return NAN;
}
@@ -420,7 +416,7 @@ bme280_compensate_humidity(struct sensor_itf *itf, uint32_t rawhumid,
int32_t tmp32;
if (rawhumid == 0x8000) {
- BME280_ERR("Invalid humidity data\n");
+ BME280_LOG(ERROR, "Invalid humidity data\n");
STATS_INC(g_bme280stats, invalid_data_errors);
return NAN;
}
@@ -843,7 +839,7 @@ bme280_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, addr | BME280_SPI_READ_CMD_BIT);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- BME280_ERR("SPI_%u register write failed addr:0x%02X\n",
+ BME280_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bme280stats, read_errors);
goto err;
@@ -854,7 +850,7 @@ bme280_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- BME280_ERR("SPI_%u read failed addr:0x%02X\n",
+ BME280_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bme280stats, read_errors);
goto err;
@@ -894,7 +890,7 @@ bme280_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, addr & ~BME280_SPI_READ_CMD_BIT);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- BME280_ERR("SPI_%u register write failed addr:0x%02X\n",
+ BME280_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bme280stats, write_errors);
goto err;
@@ -905,7 +901,7 @@ bme280_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, payload[i]);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- BME280_ERR("SPI_%u write failed addr:0x%02X:0x%02X\n",
+ BME280_LOG(ERROR, "SPI_%u write failed addr:0x%02X:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bme280stats, write_errors);
goto err;
diff --git a/hw/drivers/sensors/bme280/syscfg.yml b/hw/drivers/sensors/bme280/syscfg.yml
index 6fd65c63d9..f26087e854 100644
--- a/hw/drivers/sensors/bme280/syscfg.yml
+++ b/hw/drivers/sensors/bme280/syscfg.yml
@@ -36,3 +36,6 @@ syscfg.defs:
BME280_SPEC_CALC:
description: 'BME280 Spec calculation insetad of built in one'
value : 1
+ BME280_LOG_MODULE:
+ description: 'Numeric module ID to use for BME280 log messages'
+ value: 208
diff --git a/hw/drivers/sensors/bmp280/pkg.yml b/hw/drivers/sensors/bmp280/pkg.yml
index beff0a4060..ed184b7c20 100644
--- a/hw/drivers/sensors/bmp280/pkg.yml
+++ b/hw/drivers/sensors/bmp280/pkg.yml
@@ -32,10 +32,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.BMP280_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/bmp280/src/bmp280.c b/hw/drivers/sensors/bmp280/src/bmp280.c
index c3f4907e68..5670a72380 100644
--- a/hw/drivers/sensors/bmp280/src/bmp280.c
+++ b/hw/drivers/sensors/bmp280/src/bmp280.c
@@ -31,7 +31,7 @@
#include "sensor/pressure.h"
#include "bmp280_priv.h"
#include "hal/hal_gpio.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -63,10 +63,8 @@ STATS_NAME_END(bmp280_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(bmp280_stat_section) g_bmp280stats;
-#define LOG_MODULE_BMP280 (2801)
-#define BMP280_INFO(...) LOG_INFO(&_log, LOG_MODULE_BMP280, __VA_ARGS__)
-#define BMP280_ERR(...) LOG_ERROR(&_log, LOG_MODULE_BMP280, __VA_ARGS__)
-static struct log _log;
+#define BMP280_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(BMP280_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int bmp280_sensor_read(struct sensor *, sensor_type_t,
@@ -123,8 +121,6 @@ bmp280_init(struct os_dev *dev, void *arg)
goto err;
}
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &bmp280->sensor;
/* Initialise the stats entry */
@@ -202,7 +198,7 @@ bmp280_compensate_temperature(int32_t rawtemp, struct bmp280_pdd *pdd)
double var1, var2, comptemp;
if (rawtemp == 0x800000) {
- BMP280_ERR("Invalid temp data\n");
+ BMP280_LOG(ERROR, "Invalid temp data\n");
STATS_INC(g_bmp280stats, invalid_data_errors);
return NAN;
}
@@ -237,7 +233,7 @@ bmp280_compensate_pressure(struct sensor_itf *itf, int32_t rawpress,
int32_t temp;
if (rawpress == 0x800000) {
- BMP280_ERR("Invalid press data\n");
+ BMP280_LOG(ERROR, "Invalid press data\n");
STATS_INC(g_bmp280stats, invalid_data_errors);
return NAN;
}
@@ -288,7 +284,7 @@ bmp280_compensate_temperature(int32_t rawtemp, struct bmp280_pdd *pdd)
int32_t var1, var2, comptemp;
if (rawtemp == 0x800000) {
- BMP280_ERR("Invalid temp data\n");
+ BMP280_LOG(ERROR, "Invalid temp data\n");
STATS_INC(g_bmp280stats, invalid_data_errors);
return NAN;
}
@@ -326,7 +322,7 @@ bmp280_compensate_pressure(struct sensor_itf *itf, int32_t rawpress,
int32_t temp;
if (rawpress == 0x800000) {
- BMP280_ERR("Invalid pressure data\n");
+ BMP280_LOG(ERROR, "Invalid pressure data\n");
STATS_INC(g_bmp280stats, invalid_data_errors);
return NAN;
}
@@ -710,7 +706,7 @@ bmp280_i2c_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- BMP280_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ BMP280_LOG(ERROR, "I2C access failed at address 0x%02X\n", data_struct.address);
STATS_INC(g_bmp280stats, write_errors);
goto err;
}
@@ -720,7 +716,7 @@ bmp280_i2c_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- BMP280_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, addr);
+ BMP280_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n", data_struct.address, addr);
STATS_INC(g_bmp280stats, read_errors);
goto err;
}
@@ -759,7 +755,7 @@ bmp280_spi_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, addr | BMP280_SPI_READ_CMD_BIT);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- BMP280_ERR("SPI_%u register write failed addr:0x%02X\n",
+ BMP280_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bmp280stats, read_errors);
goto err;
@@ -770,7 +766,7 @@ bmp280_spi_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- BMP280_ERR("SPI_%u read failed addr:0x%02X\n",
+ BMP280_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bmp280stats, read_errors);
goto err;
@@ -820,7 +816,7 @@ bmp280_i2c_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- BMP280_ERR("Failed to write 0x%02X:0x%02X\n", data_struct.address, addr);
+ BMP280_LOG(ERROR, "Failed to write 0x%02X:0x%02X\n", data_struct.address, addr);
STATS_INC(g_bmp280stats, write_errors);
goto err;
}
@@ -856,7 +852,7 @@ bmp280_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, addr & ~BMP280_SPI_READ_CMD_BIT);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- BMP280_ERR("SPI_%u register write failed addr:0x%02X\n",
+ BMP280_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bmp280stats, write_errors);
goto err;
@@ -867,7 +863,7 @@ bmp280_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, payload[i]);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- BMP280_ERR("SPI_%u write failed addr:0x%02X\n",
+ BMP280_LOG(ERROR, "SPI_%u write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_bmp280stats, write_errors);
goto err;
diff --git a/hw/drivers/sensors/bmp280/syscfg.yml b/hw/drivers/sensors/bmp280/syscfg.yml
index f48b07ea84..2b2828163a 100644
--- a/hw/drivers/sensors/bmp280/syscfg.yml
+++ b/hw/drivers/sensors/bmp280/syscfg.yml
@@ -42,3 +42,6 @@ syscfg.defs:
BMP280_ITF_LOCK_TMO:
description: 'BMP280 interface lock timeout in milliseconds'
value: 1000
+ BMP280_LOG_MODULE:
+ description: 'Numeric module ID to use for BMP280 log messages'
+ value: 209
diff --git a/hw/drivers/sensors/bno055/pkg.yml b/hw/drivers/sensors/bno055/pkg.yml
index fdb455595d..1c9e441d86 100644
--- a/hw/drivers/sensors/bno055/pkg.yml
+++ b/hw/drivers/sensors/bno055/pkg.yml
@@ -30,10 +30,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.BNO055_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/bno055/src/bno055.c b/hw/drivers/sensors/bno055/src/bno055.c
index aeed53ec79..66fed6a3aa 100644
--- a/hw/drivers/sensors/bno055/src/bno055.c
+++ b/hw/drivers/sensors/bno055/src/bno055.c
@@ -32,7 +32,7 @@
#include "sensor/temperature.h"
#include "bno055/bno055.h"
#include "bno055_priv.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -49,10 +49,8 @@ STATS_NAME_END(bno055_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(bno055_stat_section) g_bno055stats;
-#define LOG_MODULE_BNO055 (305)
-#define BNO055_INFO(...) LOG_INFO(&_log, LOG_MODULE_BNO055, __VA_ARGS__)
-#define BNO055_ERR(...) LOG_ERROR(&_log, LOG_MODULE_BNO055, __VA_ARGS__)
-static struct log _log;
+#define BNO055_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(BNO055_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API.*/
static int bno055_sensor_read(struct sensor *, sensor_type_t,
@@ -88,8 +86,9 @@ bno055_write8(struct sensor_itf *itf, uint8_t reg, uint8_t value)
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC, 1);
if (rc) {
- BNO055_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
- data_struct.address, reg, value);
+ BNO055_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
+ data_struct.address, reg, value);
STATS_INC(g_bno055stats, errors);
}
@@ -134,7 +133,8 @@ bno055_writelen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- BNO055_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ BNO055_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_bno055stats, errors);
goto err;
}
@@ -143,7 +143,8 @@ bno055_writelen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, len);
if (rc) {
- BNO055_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ BNO055_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
STATS_INC(g_bno055stats, errors);;
}
@@ -183,7 +184,8 @@ bno055_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
payload = reg;
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- BNO055_ERR("I2C register write failed at address 0x%02X:0x%02X\n",
+ BNO055_LOG(ERROR,
+ "I2C register write failed at address 0x%02X:0x%02X\n",
data_struct.address, reg);
STATS_INC(g_bno055stats, errors);
goto err;
@@ -194,7 +196,8 @@ bno055_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
*value = payload;
if (rc) {
- BNO055_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ BNO055_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
STATS_INC(g_bno055stats, errors);
}
@@ -240,7 +243,8 @@ bno055_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- BNO055_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ BNO055_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_bno055stats, errors);
goto err;
}
@@ -250,7 +254,8 @@ bno055_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- BNO055_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ BNO055_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
STATS_INC(g_bno055stats, errors);
}
@@ -469,8 +474,6 @@ bno055_init(struct os_dev *dev, void *arg)
goto err;
}
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &bno055->sensor;
/* Initialise the stats entry */
@@ -638,7 +641,7 @@ bno055_placement_cfg(struct sensor_itf *itf, uint8_t placement)
remap_sign = BNO055_REMAP_SIGN_P7;
break;
default:
- BNO055_ERR("Invalid Axis config, Assuming P1(default) \n");
+ BNO055_LOG(ERROR, "Invalid Axis config, Assuming P1(default) \n");
rc = SYS_EINVAL;
goto err;
}
@@ -806,7 +809,7 @@ bno055_config(struct bno055 *bno055, struct bno055_cfg *cfg)
}
if (cfg->bc_opr_mode != mode) {
- BNO055_ERR("Config mode and read mode do not match.\n");
+ BNO055_LOG(ERROR, "Config mode and read mode do not match.\n");
rc = SYS_EINVAL;
goto err;
}
@@ -906,7 +909,7 @@ bno055_find_reg(sensor_type_t type, uint8_t *reg)
*reg = BNO055_GRAVITY_DATA_X_LSB_ADDR;
break;
default:
- BNO055_ERR("Not supported sensor type: %d\n", (int)type);
+ BNO055_LOG(ERROR, "Not supported sensor type: %d\n", (int)type);
rc = SYS_EINVAL;
break;
}
@@ -1018,7 +1021,7 @@ bno055_get_vector_data(struct sensor_itf *itf, void *datastruct, int type)
sad->sad_z_is_valid = 1;
break;
default:
- BNO055_ERR("Not supported sensor type: %d\n", type);
+ BNO055_LOG(ERROR, "Not supported sensor type: %d\n", type);
rc = SYS_EINVAL;
goto err;
}
diff --git a/hw/drivers/sensors/bno055/syscfg.yml b/hw/drivers/sensors/bno055/syscfg.yml
index 4bae5d55a1..39a3609f30 100644
--- a/hw/drivers/sensors/bno055/syscfg.yml
+++ b/hw/drivers/sensors/bno055/syscfg.yml
@@ -33,3 +33,6 @@ syscfg.defs:
BNO055_ITF_LOCK_TMO:
description: 'BNO055 interface lock timeout in milliseconds'
value: 1000
+ BNO055_LOG_MODULE:
+ description: 'Numeric module ID to use for BNO055 log messages'
+ value: 85
diff --git a/hw/drivers/sensors/lis2dh12/pkg.yml b/hw/drivers/sensors/lis2dh12/pkg.yml
index 77ae8d68ae..782c9407e1 100644
--- a/hw/drivers/sensors/lis2dh12/pkg.yml
+++ b/hw/drivers/sensors/lis2dh12/pkg.yml
@@ -28,7 +28,7 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/lis2dh12/src/lis2dh12.c b/hw/drivers/sensors/lis2dh12/src/lis2dh12.c
index a46be3a8f9..709b920bab 100644
--- a/hw/drivers/sensors/lis2dh12/src/lis2dh12.c
+++ b/hw/drivers/sensors/lis2dh12/src/lis2dh12.c
@@ -30,7 +30,7 @@
#include "lis2dh12/lis2dh12.h"
#include "lis2dh12_priv.h"
#include "hal/hal_gpio.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -56,10 +56,8 @@ STATS_NAME_END(lis2dh12_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(lis2dh12_stat_section) g_lis2dh12stats;
-#define LOG_MODULE_LIS2DH12 (212)
-#define LIS2DH12_INFO(...) LOG_INFO(&_log, LOG_MODULE_LIS2DH12, __VA_ARGS__)
-#define LIS2DH12_ERR(...) LOG_ERROR(&_log, LOG_MODULE_LIS2DH12, __VA_ARGS__)
-static struct log _log;
+#define LIS2DH12_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(LIS2DH12_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int lis2dh12_sensor_read(struct sensor *, sensor_type_t,
@@ -115,7 +113,8 @@ lis2dh12_i2c_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DH12_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ LIS2DH12_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_lis2dh12stats, read_errors);
goto err;
}
@@ -125,7 +124,8 @@ lis2dh12_i2c_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DH12_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, addr);
+ LIS2DH12_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, addr);
STATS_INC(g_lis2dh12stats, read_errors);
goto err;
}
@@ -176,7 +176,7 @@ lis2dh12_spi_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, addr);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DH12_ERR("SPI_%u register write failed addr:0x%02X\n",
+ LIS2DH12_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2dh12stats, read_errors);
goto err;
@@ -187,7 +187,7 @@ lis2dh12_spi_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
retval = hal_spi_tx_val(itf->si_num, 0x55);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DH12_ERR("SPI_%u read failed addr:0x%02X\n",
+ LIS2DH12_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2dh12stats, read_errors);
goto err;
@@ -240,7 +240,8 @@ lis2dh12_i2c_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DH12_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ LIS2DH12_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_lis2dh12stats, write_errors);
goto err;
}
@@ -283,7 +284,7 @@ lis2dh12_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, addr);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DH12_ERR("SPI_%u register write failed addr:0x%02X\n",
+ LIS2DH12_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2dh12stats, write_errors);
goto err;
@@ -294,7 +295,7 @@ lis2dh12_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, payload[i]);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DH12_ERR("SPI_%u write failed addr:0x%02X\n",
+ LIS2DH12_LOG(ERROR, "SPI_%u write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2dh12stats, write_errors);
goto err;
@@ -489,7 +490,7 @@ lis2dh12_set_full_scale(struct sensor_itf *itf, uint8_t fs)
uint8_t reg;
if (fs > LIS2DH12_FS_16G) {
- LIS2DH12_ERR("Invalid full scale value\n");
+ LIS2DH12_LOG(ERROR, "Invalid full scale value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -579,7 +580,7 @@ lis2dh12_set_rate(struct sensor_itf *itf, uint8_t rate)
uint8_t reg;
if (rate > LIS2DH12_DATA_RATE_HN_1344HZ_L_5376HZ) {
- LIS2DH12_ERR("Invalid rate value\n");
+ LIS2DH12_LOG(ERROR, "Invalid rate value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -883,8 +884,6 @@ lis2dh12_init(struct os_dev *dev, void *arg)
lis2dh12->cfg.lc_s_mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &lis2dh12->sensor;
/* Initialise the stats entry */
diff --git a/hw/drivers/sensors/lis2dh12/syscfg.yml b/hw/drivers/sensors/lis2dh12/syscfg.yml
index 4156514c7a..334a2cb548 100644
--- a/hw/drivers/sensors/lis2dh12/syscfg.yml
+++ b/hw/drivers/sensors/lis2dh12/syscfg.yml
@@ -21,3 +21,6 @@ syscfg.defs:
LIS2DH12_ITF_LOCK_TMO:
description: 'LIS2DH12 interface lock timeout in milliseconds'
value: 1000
+ LIS2DH12_LOG_MODULE:
+ description: 'Numeric module ID to use for LIS2DH12 log messages'
+ value: 110
diff --git a/hw/drivers/sensors/lis2ds12/pkg.yml b/hw/drivers/sensors/lis2ds12/pkg.yml
index b281a61357..595b74c454 100644
--- a/hw/drivers/sensors/lis2ds12/pkg.yml
+++ b/hw/drivers/sensors/lis2ds12/pkg.yml
@@ -29,7 +29,7 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/lis2ds12/src/lis2ds12.c b/hw/drivers/sensors/lis2ds12/src/lis2ds12.c
index 4bf0e3ffdb..d22960d94d 100644
--- a/hw/drivers/sensors/lis2ds12/src/lis2ds12.c
+++ b/hw/drivers/sensors/lis2ds12/src/lis2ds12.c
@@ -30,7 +30,7 @@
#include "lis2ds12/lis2ds12.h"
#include "lis2ds12_priv.h"
#include "hal/hal_gpio.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -81,10 +81,8 @@ STATS_NAME_END(lis2ds12_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(lis2ds12_stat_section) g_lis2ds12stats;
-#define LOG_MODULE_LIS2DS12 (212)
-#define LIS2DS12_INFO(...) LOG_INFO(&_log, LOG_MODULE_LIS2DS12, __VA_ARGS__)
-#define LIS2DS12_ERR(...) LOG_ERROR(&_log, LOG_MODULE_LIS2DS12, __VA_ARGS__)
-static struct log _log;
+#define LIS2DS12_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(LIS2DS12_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int lis2ds12_sensor_read(struct sensor *, sensor_type_t,
@@ -143,7 +141,8 @@ lis2ds12_i2c_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DS12_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ LIS2DS12_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_lis2ds12stats, write_errors);
goto err;
}
@@ -186,7 +185,7 @@ lis2ds12_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, addr);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DS12_ERR("SPI_%u register write failed addr:0x%02X\n",
+ LIS2DS12_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2ds12stats, write_errors);
goto err;
@@ -197,7 +196,7 @@ lis2ds12_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, payload[i]);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DS12_ERR("SPI_%u write failed addr:0x%02X:0x%02X\n",
+ LIS2DS12_LOG(ERROR, "SPI_%u write failed addr:0x%02X:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2ds12stats, write_errors);
goto err;
@@ -264,7 +263,8 @@ lis2ds12_i2c_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DS12_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ LIS2DS12_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr);
STATS_INC(g_lis2ds12stats, write_errors);
return rc;
}
@@ -276,7 +276,8 @@ lis2ds12_i2c_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DS12_ERR("Failed to read from 0x%02X:0x%02X\n", itf->si_addr, reg);
+ LIS2DS12_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->si_addr, reg);
STATS_INC(g_lis2ds12stats, read_errors);
}
@@ -309,8 +310,8 @@ lis2ds12_spi_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DS12_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ LIS2DS12_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lis2ds12stats, read_errors);
goto err;
}
@@ -320,8 +321,8 @@ lis2ds12_spi_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DS12_ERR("SPI_%u read failed addr:0x%02X\n",
- itf->si_num, reg);
+ LIS2DS12_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lis2ds12stats, read_errors);
goto err;
}
@@ -521,7 +522,7 @@ lis2ds12_set_full_scale(struct sensor_itf *itf, uint8_t fs)
uint8_t reg;
if (fs > LIS2DS12_FS_16G) {
- LIS2DS12_ERR("Invalid full scale value\n");
+ LIS2DS12_LOG(ERROR, "Invalid full scale value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -586,7 +587,7 @@ lis2ds12_set_rate(struct sensor_itf *itf, uint8_t rate)
// TODO probably not the best check for me
if (rate > LIS2DS12_DATA_RATE_LP_10BIT_400HZ) {
- LIS2DS12_ERR("Invalid rate value\n");
+ LIS2DS12_LOG(ERROR, "Invalid rate value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -1834,7 +1835,7 @@ init_intpin(struct lis2ds12 *lis2ds12, hal_gpio_irq_handler_t handler,
}
if (pin < 0) {
- LIS2DS12_ERR("Interrupt pin not configured\n");
+ LIS2DS12_LOG(ERROR, "Interrupt pin not configured\n");
return SYS_EINVAL;
}
@@ -1850,7 +1851,7 @@ init_intpin(struct lis2ds12 *lis2ds12, hal_gpio_irq_handler_t handler,
trig,
HAL_GPIO_PULL_NONE);
if (rc != 0) {
- LIS2DS12_ERR("Failed to initialise interrupt pin %d\n", pin);
+ LIS2DS12_LOG(ERROR, "Failed to initialise interrupt pin %d\n", pin);
return rc;
}
@@ -2392,7 +2393,7 @@ lis2ds12_sensor_handle_interrupt(struct sensor *sensor)
rc = lis2ds12_clear_int(itf, int_src);
if (rc) {
- LIS2DS12_ERR("Could not read int src err=0x%02x\n", rc);
+ LIS2DS12_LOG(ERROR, "Could not read int src err=0x%02x\n", rc);
return rc;
}
@@ -2476,8 +2477,6 @@ lis2ds12_init(struct os_dev *dev, void *arg)
lis2ds12->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &lis2ds12->sensor;
/* Initialise the stats entry */
diff --git a/hw/drivers/sensors/lis2ds12/syscfg.yml b/hw/drivers/sensors/lis2ds12/syscfg.yml
index f4b64e3a20..4dc310b690 100644
--- a/hw/drivers/sensors/lis2ds12/syscfg.yml
+++ b/hw/drivers/sensors/lis2ds12/syscfg.yml
@@ -44,3 +44,6 @@ syscfg.defs:
LIS2DS12_ITF_LOCK_TMO:
description: 'LIS2DS12 interface lock timeout in milliseconds'
value: 1000
+ LIS2DS12_LOG_MODULE:
+ description: 'Numeric module ID to use for LIS2DS12 log messages'
+ value: 212
diff --git a/hw/drivers/sensors/lis2dw12/pkg.yml b/hw/drivers/sensors/lis2dw12/pkg.yml
index f188c49246..d5634bdeb7 100644
--- a/hw/drivers/sensors/lis2dw12/pkg.yml
+++ b/hw/drivers/sensors/lis2dw12/pkg.yml
@@ -29,7 +29,7 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/lis2dw12/src/lis2dw12.c b/hw/drivers/sensors/lis2dw12/src/lis2dw12.c
index fe82314346..8c1aa3089e 100644
--- a/hw/drivers/sensors/lis2dw12/src/lis2dw12.c
+++ b/hw/drivers/sensors/lis2dw12/src/lis2dw12.c
@@ -30,7 +30,7 @@
#include "lis2dw12/lis2dw12.h"
#include "lis2dw12_priv.h"
#include "hal/hal_gpio.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -148,10 +148,8 @@ STATS_NAME_END(lis2dw12_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(lis2dw12_stat_section) g_lis2dw12stats;
-#define LOG_MODULE_LIS2DW12 (212)
-#define LIS2DW12_INFO(...) LOG_INFO(&_log, LOG_MODULE_LIS2DW12, __VA_ARGS__)
-#define LIS2DW12_ERR(...) LOG_ERROR(&_log, LOG_MODULE_LIS2DW12, __VA_ARGS__)
-static struct log _log;
+#define LIS2DW12_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(LIS2DW12_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int lis2dw12_sensor_read(struct sensor *, sensor_type_t,
@@ -210,7 +208,8 @@ lis2dw12_i2c_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DW12_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ LIS2DW12_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_lis2dw12stats, write_errors);
goto err;
}
@@ -253,7 +252,7 @@ lis2dw12_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, addr);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DW12_ERR("SPI_%u register write failed addr:0x%02X\n",
+ LIS2DW12_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2dw12stats, write_errors);
goto err;
@@ -264,7 +263,7 @@ lis2dw12_spi_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *payload,
rc = hal_spi_tx_val(itf->si_num, payload[i]);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DW12_ERR("SPI_%u write failed addr:0x%02X:0x%02X\n",
+ LIS2DW12_LOG(ERROR, "SPI_%u write failed addr:0x%02X:0x%02X\n",
itf->si_num, addr);
STATS_INC(g_lis2dw12stats, write_errors);
goto err;
@@ -338,7 +337,8 @@ lis2dw12_i2c_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DW12_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ LIS2DW12_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr);
STATS_INC(g_lis2dw12stats, write_errors);
return rc;
}
@@ -350,7 +350,8 @@ lis2dw12_i2c_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LIS2DW12_ERR("Failed to read from 0x%02X:0x%02X\n", itf->si_addr, reg);
+ LIS2DW12_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->si_addr, reg);
STATS_INC(g_lis2dw12stats, read_errors);
}
@@ -383,8 +384,8 @@ lis2dw12_spi_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DW12_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ LIS2DW12_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lis2dw12stats, read_errors);
goto err;
}
@@ -394,8 +395,8 @@ lis2dw12_spi_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LIS2DW12_ERR("SPI_%u read failed addr:0x%02X\n",
- itf->si_num, reg);
+ LIS2DW12_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lis2dw12stats, read_errors);
goto err;
}
@@ -595,7 +596,7 @@ lis2dw12_set_full_scale(struct sensor_itf *itf, uint8_t fs)
uint8_t reg;
if (fs > LIS2DW12_FS_16G) {
- LIS2DW12_ERR("Invalid full scale value\n");
+ LIS2DW12_LOG(ERROR, "Invalid full scale value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -659,7 +660,7 @@ lis2dw12_set_rate(struct sensor_itf *itf, uint8_t rate)
uint8_t reg;
if (rate > LIS2DW12_DATA_RATE_1600HZ) {
- LIS2DW12_ERR("Invalid rate value\n");
+ LIS2DW12_LOG(ERROR, "Invalid rate value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -2220,7 +2221,7 @@ init_intpin(struct lis2dw12 *lis2dw12, hal_gpio_irq_handler_t handler,
}
if (pin < 0) {
- LIS2DW12_ERR("Interrupt pin not configured\n");
+ LIS2DW12_LOG(ERROR, "Interrupt pin not configured\n");
return SYS_EINVAL;
}
@@ -2236,7 +2237,7 @@ init_intpin(struct lis2dw12 *lis2dw12, hal_gpio_irq_handler_t handler,
trig,
HAL_GPIO_PULL_NONE);
if (rc != 0) {
- LIS2DW12_ERR("Failed to initialise interrupt pin %d\n", pin);
+ LIS2DW12_LOG(ERROR, "Failed to initialise interrupt pin %d\n", pin);
return rc;
}
@@ -2831,7 +2832,7 @@ lis2dw12_sensor_handle_interrupt(struct sensor *sensor)
*/
rc = lis2dw12_get_int_status(itf, &int_status);
if (rc) {
- LIS2DW12_ERR("Could not read int status err=0x%02x\n", rc);
+ LIS2DW12_LOG(ERROR, "Could not read int status err=0x%02x\n", rc);
return rc;
}
@@ -2852,7 +2853,7 @@ lis2dw12_sensor_handle_interrupt(struct sensor *sensor)
rc = lis2dw12_get_sixd_src(itf, &sixd_src);
if (rc) {
- LIS2DW12_ERR("Could not read sixd src err=0x%02x\n", rc);
+ LIS2DW12_LOG(ERROR, "Could not read sixd src err=0x%02x\n", rc);
goto err;
}
@@ -2934,7 +2935,7 @@ lis2dw12_sensor_handle_interrupt(struct sensor *sensor)
rc = lis2dw12_clear_int(itf, &int_src);
if (rc) {
- LIS2DW12_ERR("Could not read int src err=0x%02x\n", rc);
+ LIS2DW12_LOG(ERROR, "Could not read int src err=0x%02x\n", rc);
return rc;
}
@@ -3055,8 +3056,6 @@ lis2dw12_init(struct os_dev *dev, void *arg)
lis2dw12->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &lis2dw12->sensor;
/* Initialise the stats entry */
diff --git a/hw/drivers/sensors/lis2dw12/syscfg.yml b/hw/drivers/sensors/lis2dw12/syscfg.yml
index 794e3c7df0..3d31eb88d2 100644
--- a/hw/drivers/sensors/lis2dw12/syscfg.yml
+++ b/hw/drivers/sensors/lis2dw12/syscfg.yml
@@ -47,3 +47,6 @@ syscfg.defs:
LIS2DW12_ITF_LOCK_TMO:
description: 'LIS2DW12 interface lock timeout in milliseconds'
value: 1000
+ LIS2DW12_LOG_MODULE:
+ description: 'Numeric module ID to use for LIS2DW12 log messages'
+ value: 213
diff --git a/hw/drivers/sensors/lps33hw/pkg.yml b/hw/drivers/sensors/lps33hw/pkg.yml
index a9aad3b42e..ea9a608032 100644
--- a/hw/drivers/sensors/lps33hw/pkg.yml
+++ b/hw/drivers/sensors/lps33hw/pkg.yml
@@ -33,10 +33,10 @@ pkg.deps:
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.LPS33HW_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/lps33hw/src/lps33hw.c b/hw/drivers/sensors/lps33hw/src/lps33hw.c
index 38268d47e0..815cff675b 100644
--- a/hw/drivers/sensors/lps33hw/src/lps33hw.c
+++ b/hw/drivers/sensors/lps33hw/src/lps33hw.c
@@ -31,7 +31,7 @@
#include "sensor/temperature.h"
#include "lps33hw/lps33hw.h"
#include "lps33hw_priv.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -57,10 +57,8 @@ STATS_NAME_END(lps33hw_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(lps33hw_stat_section) g_lps33hwstats;
-#define LOG_MODULE_LPS33HW (33)
-#define LPS33HW_INFO(...) LOG_INFO(&_log, LOG_MODULE_LPS33HW, __VA_ARGS__)
-#define LPS33HW_ERR(...) LOG_ERROR(&_log, LOG_MODULE_LPS33HW, __VA_ARGS__)
-static struct log _log;
+#define LPS33HW_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(LPS33HW_LOG_MODULE), __VA_ARGS__)
#define LPS33HW_PRESS_OUT_DIV (40.96)
#define LPS33HW_TEMP_OUT_DIV (100.0)
@@ -181,8 +179,9 @@ lps33hw_i2c_set_reg(struct sensor_itf *itf, uint8_t reg, uint8_t value)
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LPS33HW_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
- itf->si_addr, reg, value);
+ LPS33HW_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02X\n",
+ itf->si_addr, reg, value);
STATS_INC(g_lps33hwstats, read_errors);
}
@@ -211,8 +210,8 @@ lps33hw_spi_set_reg(struct sensor_itf *itf, uint8_t reg, uint8_t value)
rc = hal_spi_tx_val(itf->si_num, reg & ~LPS33HW_SPI_READ_CMD_BIT);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LPS33HW_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ LPS33HW_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lps33hwstats, write_errors);
goto err;
}
@@ -221,8 +220,8 @@ lps33hw_spi_set_reg(struct sensor_itf *itf, uint8_t reg, uint8_t value)
rc = hal_spi_tx_val(itf->si_num, value);
if (rc == 0xFFFF) {
rc = SYS_EINVAL;
- LPS33HW_ERR("SPI_%u write failed addr:0x%02X\n",
- itf->si_num, reg);
+ LPS33HW_LOG(ERROR, "SPI_%u write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lps33hwstats, write_errors);
goto err;
}
@@ -296,8 +295,8 @@ lps33hw_spi_get_regs(struct sensor_itf *itf, uint8_t reg, uint8_t size,
retval = hal_spi_tx_val(itf->si_num, reg | LPS33HW_SPI_READ_CMD_BIT);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LPS33HW_ERR("SPI_%u register write failed addr:0x%02X\n",
- itf->si_num, reg);
+ LPS33HW_LOG(ERROR, "SPI_%u register write failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lps33hwstats, read_errors);
goto err;
}
@@ -307,8 +306,8 @@ lps33hw_spi_get_regs(struct sensor_itf *itf, uint8_t reg, uint8_t size,
retval = hal_spi_tx_val(itf->si_num, 0);
if (retval == 0xFFFF) {
rc = SYS_EINVAL;
- LPS33HW_ERR("SPI_%u read failed addr:0x%02X\n",
- itf->si_num, reg);
+ LPS33HW_LOG(ERROR, "SPI_%u read failed addr:0x%02X\n",
+ itf->si_num, reg);
STATS_INC(g_lps33hwstats, read_errors);
goto err;
}
@@ -350,7 +349,8 @@ lps33hw_i2c_get_regs(struct sensor_itf *itf, uint8_t reg, uint8_t size,
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LPS33HW_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ LPS33HW_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr);
STATS_INC(g_lps33hwstats, write_errors);
return rc;
}
@@ -362,8 +362,9 @@ lps33hw_i2c_get_regs(struct sensor_itf *itf, uint8_t reg, uint8_t size,
(OS_TICKS_PER_SEC / 10) * size, 1);
if (rc) {
- LPS33HW_ERR("Failed to read from 0x%02X:0x%02X\n", itf->si_addr, reg);
- STATS_INC(g_lps33hwstats, read_errors);
+ LPS33HW_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->si_addr, reg);
+ STATS_INC(g_lps33hwstats, read_errors);
}
return rc;
}
@@ -631,7 +632,7 @@ lps33hw_disable_interrupt(struct sensor *sensor)
static int
lps33hw_sensor_handle_interrupt(struct sensor *sensor)
{
- LPS33HW_ERR("Unhandled interrupt\n");
+ LPS33HW_LOG(ERROR, "Unhandled interrupt\n");
return 0;
}
@@ -871,8 +872,6 @@ lps33hw_init(struct os_dev *dev, void *arg)
sensor = &lps->sensor;
lps->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
/* Initialise the stats entry */
rc = stats_init(
STATS_HDR(g_lps33hwstats),
@@ -996,7 +995,7 @@ lps33hw_read_interrupt_handler(void *arg)
rc = lps33hw_get_pressure(itf, &spd.spd_press);
if (rc) {
- LPS33HW_ERR("Get pressure failed\n");
+ LPS33HW_LOG(ERROR, "Get pressure failed\n");
spd.spd_press_is_valid = 0;
} else {
spd.spd_press_is_valid = 1;
diff --git a/hw/drivers/sensors/lps33hw/syscfg.yml b/hw/drivers/sensors/lps33hw/syscfg.yml
index c932a30bc3..dd358dba50 100644
--- a/hw/drivers/sensors/lps33hw/syscfg.yml
+++ b/hw/drivers/sensors/lps33hw/syscfg.yml
@@ -35,3 +35,6 @@ syscfg.defs:
LPS33HW_ITF_LOCK_TMO:
description: 'LPS33HW interface lock timeout in milliseconds'
value: 1000
+ LPS33HW_LOG_MODULE:
+ description: 'Numeric module ID to use for LPS33HW log messages'
+ value: 133
diff --git a/hw/drivers/sensors/lsm303dlhc/pkg.yml b/hw/drivers/sensors/lsm303dlhc/pkg.yml
index ba45cdff9a..3b96f9a280 100644
--- a/hw/drivers/sensors/lsm303dlhc/pkg.yml
+++ b/hw/drivers/sensors/lsm303dlhc/pkg.yml
@@ -31,8 +31,8 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/lsm303dlhc/src/lsm303dlhc.c b/hw/drivers/sensors/lsm303dlhc/src/lsm303dlhc.c
index f9840f5a27..d6bf72c62c 100644
--- a/hw/drivers/sensors/lsm303dlhc/src/lsm303dlhc.c
+++ b/hw/drivers/sensors/lsm303dlhc/src/lsm303dlhc.c
@@ -28,7 +28,7 @@
#include "sensor/mag.h"
#include "lsm303dlhc/lsm303dlhc.h"
#include "lsm303dlhc_priv.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
/* Define the stats section and records */
@@ -66,10 +66,8 @@ STATS_NAME_END(lsm303dlhc_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(lsm303dlhc_stat_section) g_lsm303dlhcstats;
-#define LOG_MODULE_LSM303DLHC (303)
-#define LSM303DLHC_INFO(...) LOG_INFO(&_log, LOG_MODULE_LSM303DLHC, __VA_ARGS__)
-#define LSM303DLHC_ERR(...) LOG_ERROR(&_log, LOG_MODULE_LSM303DLHC, __VA_ARGS__)
-static struct log _log;
+#define LSM303DLHC_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(LSM303DLHC_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int lsm303dlhc_sensor_read(struct sensor *, sensor_type_t,
@@ -113,7 +111,8 @@ lsm303dlhc_write8(struct sensor_itf *itf, uint8_t addr, uint8_t reg,
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LSM303DLHC_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02lX\n",
+ LSM303DLHC_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02lX\n",
addr, reg, value);
STATS_INC(g_lsm303dlhcstats, errors);
}
@@ -156,7 +155,7 @@ lsm303dlhc_read8(struct sensor_itf *itf, uint8_t addr, uint8_t reg,
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LSM303DLHC_ERR("I2C access failed at address 0x%02X\n", addr);
+ LSM303DLHC_LOG(ERROR, "I2C access failed at address 0x%02X\n", addr);
STATS_INC(g_lsm303dlhcstats, errors);
goto err;
}
@@ -167,7 +166,8 @@ lsm303dlhc_read8(struct sensor_itf *itf, uint8_t addr, uint8_t reg,
OS_TICKS_PER_SEC / 10, 1);
*value = payload;
if (rc) {
- LSM303DLHC_ERR("Failed to read from 0x%02X:0x%02X\n", addr, reg);
+ LSM303DLHC_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ addr, reg);
STATS_INC(g_lsm303dlhcstats, errors);
}
@@ -212,7 +212,7 @@ lsm303dlhc_read48(struct sensor_itf *itf, uint8_t addr, uint8_t reg,
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LSM303DLHC_ERR("I2C access failed at address 0x%02X\n", addr);
+ LSM303DLHC_LOG(ERROR, "I2C access failed at address 0x%02X\n", addr);
STATS_INC(g_lsm303dlhcstats, errors);
goto err;
}
@@ -224,7 +224,8 @@ lsm303dlhc_read48(struct sensor_itf *itf, uint8_t addr, uint8_t reg,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- LSM303DLHC_ERR("Failed to read from 0x%02X:0x%02X\n", addr, reg);
+ LSM303DLHC_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ addr, reg);
STATS_INC(g_lsm303dlhcstats, errors);
}
@@ -261,8 +262,6 @@ lsm303dlhc_init(struct os_dev *dev, void *arg)
lsm->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &lsm->sensor;
/* Initialise the stats entry */
@@ -442,7 +441,8 @@ lsm303dlhc_sensor_read(struct sensor *sensor, sensor_type_t type,
mg_lsb = 0.012F;
break;
default:
- LSM303DLHC_ERR("Unknown accel range: 0x%02X. Assuming +/-2G.\n",
+ LSM303DLHC_LOG(
+ ERROR, "Unknown accel range: 0x%02X. Assuming +/-2G.\n",
lsm->cfg.accel_range);
mg_lsb = 0.001F;
break;
@@ -517,8 +517,9 @@ lsm303dlhc_sensor_read(struct sensor *sensor, sensor_type_t type,
gauss_lsb_z = 205;
break;
default:
- LSM303DLHC_ERR("Unknown mag gain: 0x%02X. Assuming +/-1.3g.\n",
- lsm->cfg.mag_gain);
+ LSM303DLHC_LOG(ERROR,
+ "Unknown mag gain: 0x%02X. Assuming +/-1.3g.\n",
+ lsm->cfg.mag_gain);
gauss_lsb_xy = 1100;
gauss_lsb_z = 980;
break;
diff --git a/hw/drivers/sensors/lsm303dlhc/syscfg.yml b/hw/drivers/sensors/lsm303dlhc/syscfg.yml
index 06f9780f0c..981725a588 100644
--- a/hw/drivers/sensors/lsm303dlhc/syscfg.yml
+++ b/hw/drivers/sensors/lsm303dlhc/syscfg.yml
@@ -1,4 +1,3 @@
-#
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
@@ -21,3 +20,6 @@ syscfg.defs:
LSM303DLHC_ITF_LOCK_TMO:
description: 'LSM303DLHC interface lock timeout in milliseconds'
value: 1000
+ LSM303DLHC_LOG_MODULE:
+ description: 'Numeric module ID to use for LSM303DLHC log messages'
+ value: 195
diff --git a/hw/drivers/sensors/mpu6050/pkg.yml b/hw/drivers/sensors/mpu6050/pkg.yml
index 331dbf24a2..2355a26d33 100644
--- a/hw/drivers/sensors/mpu6050/pkg.yml
+++ b/hw/drivers/sensors/mpu6050/pkg.yml
@@ -31,7 +31,7 @@ pkg.deps:
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/mpu6050/src/mpu6050.c b/hw/drivers/sensors/mpu6050/src/mpu6050.c
index d715204e60..c236f5f0ca 100644
--- a/hw/drivers/sensors/mpu6050/src/mpu6050.c
+++ b/hw/drivers/sensors/mpu6050/src/mpu6050.c
@@ -28,7 +28,7 @@
#include "sensor/gyro.h"
#include "mpu6050/mpu6050.h"
#include "mpu6050_priv.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -47,10 +47,8 @@ STATS_NAME_END(mpu6050_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(mpu6050_stat_section) g_mpu6050stats;
-#define LOG_MODULE_MPU6050 (6050)
-#define MPU6050_INFO(...) LOG_INFO(&_log, LOG_MODULE_MPU6050, __VA_ARGS__)
-#define MPU6050_ERR(...) LOG_ERROR(&_log, LOG_MODULE_MPU6050, __VA_ARGS__)
-static struct log _log;
+#define MPU6050_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(MPU6050_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int mpu6050_sensor_read(struct sensor *, sensor_type_t,
@@ -93,8 +91,9 @@ mpu6050_write8(struct sensor_itf *itf, uint8_t reg, uint32_t value)
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MPU6050_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02lX\n",
- itf->si_addr, reg, value);
+ MPU6050_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02lX\n",
+ itf->si_addr, reg, value);
STATS_INC(g_mpu6050stats, read_errors);
}
@@ -132,7 +131,8 @@ mpu6050_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- MPU6050_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ MPU6050_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr);
STATS_INC(g_mpu6050stats, write_errors);
return rc;
}
@@ -143,8 +143,9 @@ mpu6050_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MPU6050_ERR("Failed to read from 0x%02X:0x%02X\n", itf->si_addr, reg);
- STATS_INC(g_mpu6050stats, read_errors);
+ MPU6050_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->si_addr, reg);
+ STATS_INC(g_mpu6050stats, read_errors);
}
sensor_itf_unlock(itf);
@@ -181,7 +182,8 @@ mpu6050_read48(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 0);
if (rc) {
- MPU6050_ERR("I2C access failed at address 0x%02X\n", itf->si_addr);
+ MPU6050_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ itf->si_addr);
STATS_INC(g_mpu6050stats, write_errors);
return rc;
}
@@ -193,8 +195,9 @@ mpu6050_read48(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer)
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MPU6050_ERR("Failed to read from 0x%02X:0x%02X\n", itf->si_addr, reg);
- STATS_INC(g_mpu6050stats, read_errors);
+ MPU6050_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ itf->si_addr, reg);
+ STATS_INC(g_mpu6050stats, read_errors);
}
sensor_itf_unlock(itf);
@@ -401,8 +404,6 @@ mpu6050_init(struct os_dev *dev, void *arg)
mpu->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &mpu->sensor;
/* Initialise the stats entry */
diff --git a/hw/drivers/sensors/mpu6050/syscfg.yml b/hw/drivers/sensors/mpu6050/syscfg.yml
index 805d75f516..429c6fe647 100644
--- a/hw/drivers/sensors/mpu6050/syscfg.yml
+++ b/hw/drivers/sensors/mpu6050/syscfg.yml
@@ -1,4 +1,3 @@
-#
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
@@ -21,3 +20,6 @@ syscfg.defs:
MPU6050_ITF_LOCK_TMO:
description: 'MPU6050 interface lock timeout in milliseconds'
value: 1000
+ MPU6050_LOG_MODULE:
+ description: 'Numeric module ID to use for MPU6050 log messages'
+ value: 115
diff --git a/hw/drivers/sensors/ms5837/pkg.yml b/hw/drivers/sensors/ms5837/pkg.yml
index 0e5dc1980a..784a648859 100644
--- a/hw/drivers/sensors/ms5837/pkg.yml
+++ b/hw/drivers/sensors/ms5837/pkg.yml
@@ -31,7 +31,7 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/ms5837/src/ms5837.c b/hw/drivers/sensors/ms5837/src/ms5837.c
index 9781712c89..37089b9f13 100644
--- a/hw/drivers/sensors/ms5837/src/ms5837.c
+++ b/hw/drivers/sensors/ms5837/src/ms5837.c
@@ -30,7 +30,7 @@
#include "sensor/pressure.h"
#include "ms5837_priv.h"
#include "console/console.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -60,10 +60,8 @@ STATS_NAME_END(ms5837_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(ms5837_stat_section) g_ms5837stats;
-#define LOG_MODULE_MS5837 (5837)
-#define MS5837_INFO(...) LOG_INFO(&_log, LOG_MODULE_MS5837, __VA_ARGS__)
-#define MS5837_ERR(...) LOG_ERROR(&_log, LOG_MODULE_MS5837, __VA_ARGS__)
-static struct log _log;
+#define MS5837_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(MS5837_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int ms5837_sensor_read(struct sensor *, sensor_type_t,
@@ -101,8 +99,6 @@ ms5837_init(struct os_dev *dev, void *arg)
ms5837 = (struct ms5837 *)dev;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &ms5837->sensor;
itf = SENSOR_GET_ITF(sensor);
@@ -341,7 +337,7 @@ ms5837_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MS5837_ERR("I2C write command write failed at address 0x%02X\n",
+ MS5837_LOG(ERROR, "I2C write command write failed at address 0x%02X\n",
data_struct.address);
STATS_INC(g_ms5837stats, write_errors);
}
@@ -385,7 +381,7 @@ ms5837_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Command write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MS5837_ERR("I2C read command write failed at address 0x%02X\n",
+ MS5837_LOG(ERROR, "I2C read command write failed at address 0x%02X\n",
data_struct.address);
STATS_INC(g_ms5837stats, write_errors);
goto err;
@@ -396,7 +392,8 @@ ms5837_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MS5837_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, addr);
+ MS5837_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, addr);
STATS_INC(g_ms5837stats, read_errors);
goto err;
}
@@ -440,7 +437,7 @@ ms5837_read_eeprom(struct sensor_itf *itf, uint16_t *coeff)
rc = ms5837_crc_check(payload, (payload[MS5837_IDX_CRC] & 0xF000) >> 12);
if (rc) {
rc = SYS_EINVAL;
- MS5837_ERR("Failure in CRC, 0x%02X\n",
+ MS5837_LOG(ERROR, "Failure in CRC, 0x%02X\n",
payload[MS5837_IDX_CRC] & 0xF000 >> 12);
STATS_INC(g_ms5837stats, eeprom_crc_errors);
goto err;
diff --git a/hw/drivers/sensors/ms5837/syscfg.yml b/hw/drivers/sensors/ms5837/syscfg.yml
index 7cc9b7156b..2cacb293d6 100644
--- a/hw/drivers/sensors/ms5837/syscfg.yml
+++ b/hw/drivers/sensors/ms5837/syscfg.yml
@@ -1,4 +1,3 @@
-#
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
@@ -21,3 +20,6 @@ syscfg.defs:
MS5837_ITF_LOCK_TMO:
description: 'MS5837 interface lock timeout in milliseconds'
value: 1000
+ MS5837_LOG_MODULE:
+ description: 'Numeric module ID to use for MS5837 log messages'
+ value: 140
diff --git a/hw/drivers/sensors/ms5840/pkg.yml b/hw/drivers/sensors/ms5840/pkg.yml
index c75b2054c8..d990ce0f00 100644
--- a/hw/drivers/sensors/ms5840/pkg.yml
+++ b/hw/drivers/sensors/ms5840/pkg.yml
@@ -31,7 +31,7 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
diff --git a/hw/drivers/sensors/ms5840/src/ms5840.c b/hw/drivers/sensors/ms5840/src/ms5840.c
index b1ba2aa453..3a8bf90415 100644
--- a/hw/drivers/sensors/ms5840/src/ms5840.c
+++ b/hw/drivers/sensors/ms5840/src/ms5840.c
@@ -33,7 +33,7 @@
#include "ms5840_priv.h"
#include "os/os_cputime.h"
#include "console/console.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -63,10 +63,8 @@ STATS_NAME_END(ms5840_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(ms5840_stat_section) g_ms5840stats;
-#define LOG_MODULE_MS5840 (5840)
-#define MS5840_INFO(...) LOG_INFO(&_log, LOG_MODULE_MS5840, __VA_ARGS__)
-#define MS5840_ERR(...) LOG_ERROR(&_log, LOG_MODULE_MS5840, __VA_ARGS__)
-static struct log _log;
+#define MS5840_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(MS5840_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int ms5840_sensor_read(struct sensor *, sensor_type_t,
@@ -104,8 +102,6 @@ ms5840_init(struct os_dev *dev, void *arg)
ms5840 = (struct ms5840 *)dev;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &ms5840->sensor;
itf = SENSOR_GET_ITF(sensor);
@@ -342,7 +338,7 @@ ms5840_writelen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Register write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MS5840_ERR("I2C write command write failed at address 0x%02X\n",
+ MS5840_LOG(ERROR, "I2C write command write failed at address 0x%02X\n",
data_struct.address);
STATS_INC(g_ms5840stats, write_errors);
}
@@ -386,7 +382,7 @@ ms5840_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
/* Command write */
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MS5840_ERR("I2C read command write failed at address 0x%02X\n",
+ MS5840_LOG(ERROR, "I2C read command write failed at address 0x%02X\n",
data_struct.address);
STATS_INC(g_ms5840stats, write_errors);
goto err;
@@ -397,7 +393,8 @@ ms5840_readlen(struct sensor_itf *itf, uint8_t addr, uint8_t *buffer,
data_struct.len = len;
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- MS5840_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, addr);
+ MS5840_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, addr);
STATS_INC(g_ms5840stats, read_errors);
goto err;
}
@@ -442,7 +439,7 @@ ms5840_read_eeprom(struct sensor_itf *itf, uint16_t *coeff)
rc = ms5840_crc_check(payload, (payload[MS5840_IDX_CRC] & 0xF000) >> 12);
if (rc) {
rc = SYS_EINVAL;
- MS5840_ERR("Failure in CRC, 0x%02X\n",
+ MS5840_LOG(ERROR, "Failure in CRC, 0x%02X\n",
payload[MS5840_IDX_CRC] & 0xF000 >> 12);
STATS_INC(g_ms5840stats, eeprom_crc_errors);
goto err;
diff --git a/hw/drivers/sensors/ms5840/syscfg.yml b/hw/drivers/sensors/ms5840/syscfg.yml
index 9b726b64ad..a8e2acdb14 100644
--- a/hw/drivers/sensors/ms5840/syscfg.yml
+++ b/hw/drivers/sensors/ms5840/syscfg.yml
@@ -1,4 +1,3 @@
-#
# Licensed to the Apache Software Foundation (ASF) under one
# or more contributor license agreements. See the NOTICE file
# distributed with this work for additional information
@@ -21,3 +20,6 @@ syscfg.defs:
MS5840_ITF_LOCK_TMO:
description: 'MS5840 interface lock timeout in milliseconds'
value: 1000
+ MS5840_LOG_MODULE:
+ description: 'Numeric module ID to use for MS5840 log messages'
+ value: 170
diff --git a/hw/drivers/sensors/tcs34725/pkg.yml b/hw/drivers/sensors/tcs34725/pkg.yml
index 47e4ebf85f..92049f1754 100644
--- a/hw/drivers/sensors/tcs34725/pkg.yml
+++ b/hw/drivers/sensors/tcs34725/pkg.yml
@@ -31,10 +31,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.TCS34725_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/tcs34725/src/tcs34725.c b/hw/drivers/sensors/tcs34725/src/tcs34725.c
index 446c2693e4..98b964102f 100644
--- a/hw/drivers/sensors/tcs34725/src/tcs34725.c
+++ b/hw/drivers/sensors/tcs34725/src/tcs34725.c
@@ -27,7 +27,7 @@
#include "tcs34725/tcs34725.h"
#include "tcs34725_priv.h"
#include "sensor/color.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -58,10 +58,8 @@ STATS_NAME_END(tcs34725_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(tcs34725_stat_section) g_tcs34725stats;
-#define LOG_MODULE_TCS34725 (307)
-#define TCS34725_INFO(...) LOG_INFO(&_log, LOG_MODULE_TCS34725, __VA_ARGS__)
-#define TCS34725_ERR(...) LOG_ERROR(&_log, LOG_MODULE_TCS34725, __VA_ARGS__)
-static struct log _log;
+#define TCS34725_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(TCS34725_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int tcs34725_sensor_read(struct sensor *, sensor_type_t,
@@ -103,8 +101,9 @@ tcs34725_write8(struct sensor_itf *itf, uint8_t reg, uint32_t value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TCS34725_ERR("Failed to write to 0x%02X:0x%02X with value 0x%02lX\n",
- data_struct.address, reg, value);
+ TCS34725_LOG(ERROR,
+ "Failed to write to 0x%02X:0x%02X with value 0x%02lX\n",
+ data_struct.address, reg, value);
STATS_INC(g_tcs34725stats, errors);
}
@@ -143,7 +142,8 @@ tcs34725_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
payload = reg | TCS34725_COMMAND_BIT;
rc = hal_i2c_master_write(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TCS34725_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ TCS34725_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_tcs34725stats, errors);
goto err;
}
@@ -153,7 +153,8 @@ tcs34725_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
rc = hal_i2c_master_read(itf->si_num, &data_struct, OS_TICKS_PER_SEC / 10, 1);
*value = payload;
if (rc) {
- TCS34725_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ TCS34725_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
STATS_INC(g_tcs34725stats, errors);
}
@@ -196,7 +197,8 @@ tcs34725_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8_t l
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TCS34725_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ TCS34725_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_tcs34725stats, errors);
goto err;
}
@@ -208,7 +210,8 @@ tcs34725_readlen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8_t l
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TCS34725_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ TCS34725_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
STATS_INC(g_tcs34725stats, errors);
goto err;
}
@@ -259,7 +262,8 @@ tcs34725_writelen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8_t
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TCS34725_ERR("I2C access failed at address 0x%02X\n", data_struct.address);
+ TCS34725_LOG(ERROR, "I2C access failed at address 0x%02X\n",
+ data_struct.address);
STATS_INC(g_tcs34725stats, errors);
goto err;
}
@@ -270,7 +274,8 @@ tcs34725_writelen(struct sensor_itf *itf, uint8_t reg, uint8_t *buffer, uint8_t
OS_TICKS_PER_SEC / 10, len);
if (rc) {
- TCS34725_ERR("Failed to read from 0x%02X:0x%02X\n", data_struct.address, reg);
+ TCS34725_LOG(ERROR, "Failed to read from 0x%02X:0x%02X\n",
+ data_struct.address, reg);
STATS_INC(g_tcs34725stats, errors);
goto err;
}
@@ -361,8 +366,6 @@ tcs34725_init(struct os_dev *dev, void *arg)
tcs34725->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &tcs34725->sensor;
/* Initialise the stats entry */
@@ -493,7 +496,7 @@ tcs34725_set_gain(struct sensor_itf *itf, uint8_t gain)
int rc;
if (gain > TCS34725_GAIN_60X) {
- TCS34725_ERR("Invalid gain value\n");
+ TCS34725_LOG(ERROR, "Invalid gain value\n");
rc = SYS_EINVAL;
goto err;
}
diff --git a/hw/drivers/sensors/tcs34725/syscfg.yml b/hw/drivers/sensors/tcs34725/syscfg.yml
index cf82dfb1b5..7922406b45 100644
--- a/hw/drivers/sensors/tcs34725/syscfg.yml
+++ b/hw/drivers/sensors/tcs34725/syscfg.yml
@@ -33,4 +33,6 @@ syscfg.defs:
TCS34725_ITF_LOCK_TMO:
description: 'TCS34725 interface lock timeout in milliseconds'
value: 1000
-
+ TCS34725_LOG_MODULE:
+ description: 'Numeric module ID to use for TCS34725 log messages'
+ value: 254
diff --git a/hw/drivers/sensors/tsl2561/pkg.yml b/hw/drivers/sensors/tsl2561/pkg.yml
index 523e9119ea..c0c8e91eee 100644
--- a/hw/drivers/sensors/tsl2561/pkg.yml
+++ b/hw/drivers/sensors/tsl2561/pkg.yml
@@ -34,10 +34,10 @@ pkg.deps:
- "@apache-mynewt-core/kernel/os"
- "@apache-mynewt-core/hw/hal"
- "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
pkg.req_apis:
- stats
- - log
pkg.deps.TSL2561_CLI:
- "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/tsl2561/src/tsl2561.c b/hw/drivers/sensors/tsl2561/src/tsl2561.c
index 9a165fb9e3..c934552d48 100644
--- a/hw/drivers/sensors/tsl2561/src/tsl2561.c
+++ b/hw/drivers/sensors/tsl2561/src/tsl2561.c
@@ -45,7 +45,7 @@
#include "sensor/light.h"
#include "tsl2561/tsl2561.h"
#include "tsl2561_priv.h"
-#include "log/log.h"
+#include "modlog/modlog.h"
#include "stats/stats.h"
#include <syscfg/syscfg.h>
@@ -64,10 +64,8 @@ STATS_NAME_END(tsl2561_stat_section)
/* Global variable used to hold stats data */
STATS_SECT_DECL(tsl2561_stat_section) g_tsl2561stats;
-#define LOG_MODULE_TSL2561 (2561)
-#define TSL2561_INFO(...) LOG_INFO(&_log, LOG_MODULE_TSL2561, __VA_ARGS__)
-#define TSL2561_ERR(...) LOG_ERROR(&_log, LOG_MODULE_TSL2561, __VA_ARGS__)
-static struct log _log;
+#define TSL2561_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(TSL2561_LOG_MODULE), __VA_ARGS__)
/* Exports for the sensor API */
static int tsl2561_sensor_read(struct sensor *, sensor_type_t,
@@ -100,7 +98,8 @@ tsl2561_write8(struct sensor_itf *itf, uint8_t reg, uint32_t value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TSL2561_ERR("Failed to write 0x%02X:0x%02X with value 0x%02lX\n",
+ TSL2561_LOG(ERROR,
+ "Failed to write 0x%02X:0x%02X with value 0x%02lX\n",
data_struct.address, reg, value);
STATS_INC(g_tsl2561stats, errors);
}
@@ -130,7 +129,8 @@ tsl2561_write16(struct sensor_itf *itf, uint8_t reg, uint16_t value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TSL2561_ERR("Failed to write @0x%02X with value 0x%02X 0x%02X\n",
+ TSL2561_LOG(ERROR,
+ "Failed to write @0x%02X with value 0x%02X 0x%02X\n",
reg, payload[0], payload[1]);
}
@@ -161,7 +161,7 @@ tsl2561_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TSL2561_ERR("Failed to address sensor\n");
+ TSL2561_LOG(ERROR, "Failed to address sensor\n");
goto err;
}
@@ -171,7 +171,7 @@ tsl2561_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
OS_TICKS_PER_SEC / 10, 1);
*value = payload;
if (rc) {
- TSL2561_ERR("Failed to read @0x%02X\n", reg);
+ TSL2561_LOG(ERROR, "Failed to read @0x%02X\n", reg);
}
err:
@@ -201,7 +201,7 @@ tsl2561_read16(struct sensor_itf *itf, uint8_t reg, uint16_t *value)
rc = hal_i2c_master_write(itf->si_num, &data_struct,
OS_TICKS_PER_SEC / 10, 1);
if (rc) {
- TSL2561_ERR("Failed to address sensor\n");
+ TSL2561_LOG(ERROR, "Failed to address sensor\n");
goto err;
}
@@ -212,7 +212,7 @@ tsl2561_read16(struct sensor_itf *itf, uint8_t reg, uint16_t *value)
OS_TICKS_PER_SEC / 10, 1);
*value = (uint16_t)payload[0] | ((uint16_t)payload[1] << 8);
if (rc) {
- TSL2561_ERR("Failed to read @0x%02X\n", reg);
+ TSL2561_LOG(ERROR, "Failed to read @0x%02X\n", reg);
goto err;
}
@@ -347,7 +347,7 @@ tsl2561_set_gain(struct sensor_itf *itf, uint8_t gain)
uint8_t int_time;
if ((gain != TSL2561_LIGHT_GAIN_1X) && (gain != TSL2561_LIGHT_GAIN_16X)) {
- TSL2561_ERR("Invalid gain value\n");
+ TSL2561_LOG(ERROR, "Invalid gain value\n");
rc = SYS_EINVAL;
goto err;
}
@@ -508,7 +508,8 @@ tsl2561_enable_interrupt(struct sensor_itf *itf, uint8_t enable)
uint8_t persist_val;
if (enable > 1) {
- TSL2561_ERR("Invalid value 0x%02X in tsl2561_enable_interrupt\n",
+ TSL2561_LOG(ERROR,
+ "Invalid value 0x%02X in tsl2561_enable_interrupt\n",
enable);
rc = SYS_EINVAL;
goto err;
@@ -589,8 +590,6 @@ tsl2561_init(struct os_dev *dev, void *arg)
tsl2561->cfg.mask = SENSOR_TYPE_ALL;
- log_register(dev->od_name, &_log, &log_console_handler, NULL, LOG_SYSLEVEL);
-
sensor = &tsl2561->sensor;
/* Initialise the stats entry */
diff --git a/hw/drivers/sensors/tsl2561/syscfg.yml b/hw/drivers/sensors/tsl2561/syscfg.yml
index 3a542702da..3c3fff99a0 100644
--- a/hw/drivers/sensors/tsl2561/syscfg.yml
+++ b/hw/drivers/sensors/tsl2561/syscfg.yml
@@ -36,3 +36,6 @@ syscfg.defs:
TSL2561_ITF_LOCK_TMO:
description: 'TSL2561 interface lock timeout in milliseconds'
value: 1000
+ TSL2561_LOG_MODULE:
+ description: 'Numeric module ID to use for TSL2561 log messages'
+ value: 107
diff --git a/hw/drivers/sensors/tsl2591/include/tsl2591/tsl2591.h b/hw/drivers/sensors/tsl2591/include/tsl2591/tsl2591.h
new file mode 100644
index 0000000000..8705fac71c
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/include/tsl2591/tsl2591.h
@@ -0,0 +1,224 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * resarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __TSL2591_H__
+#define __TSL2591_H__
+
+#include "os/mynewt.h"
+#include "sensor/sensor.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum tsl2591_light_gain {
+ TSL2591_LIGHT_GAIN_LOW = 0x00, /* 1X */
+ TSL2591_LIGHT_GAIN_MED = 0x10, /* ~25X */
+ TSL2591_LIGHT_GAIN_HIGH = 0x20, /* ~428X */
+ TSL2591_LIGHT_GAIN_MAX = 0x30 /* ~9876X */
+};
+
+enum tsl2591_light_itime {
+ TSL2591_LIGHT_ITIME_100MS = 0x00, /* 100ms */
+ TSL2591_LIGHT_ITIME_200MS = 0x01, /* 200ms */
+ TSL2591_LIGHT_ITIME_300MS = 0x02, /* 300ms */
+ TSL2591_LIGHT_ITIME_400MS = 0x03, /* 400ms */
+ TSL2591_LIGHT_ITIME_500MS = 0x04, /* 500ms */
+ TSL2591_LIGHT_ITIME_600MS = 0x05 /* 600ms */
+};
+
+struct tsl2591_cfg {
+ uint8_t gain;
+ uint8_t integration_time;
+ sensor_type_t mask;
+};
+
+struct tsl2591 {
+ struct os_dev dev;
+ struct sensor sensor;
+ struct tsl2591_cfg cfg;
+ os_time_t last_read_time;
+};
+
+/**
+ * Expects to be called back through os_dev_create().
+ *
+ * @param ptr to the device object associated with this luminosity sensor
+ * @param argument passed to OS device init
+ *
+ * @return 0 on success, non-zero on failure.
+ */
+int tsl2591_init(struct os_dev *dev, void *arg);
+
+/**
+ * Enable or disables the sensor to save power
+ *
+ * @param The sensor interface
+ * @param state 1 to enable the sensor, 0 to disable it
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_enable(struct sensor_itf *itf, uint8_t state);
+
+/**
+ * Gets the current 'enabled' state for the IC
+ *
+ * @param The sensor interface
+ * @param ptr to the enabled variable to be filled up
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_get_enable(struct sensor_itf *itf, uint8_t *enabled);
+
+/**
+ * Gets a new data sample from the light sensor.
+ *
+ * @param The sensor interface
+ * @param broadband The full (visible + ir) sensor output
+ * @param ir The ir sensor output
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_get_data(struct sensor_itf *itf, uint16_t *broadband, uint16_t *ir);
+
+/**
+ * Sets the integration time used when sampling light values.
+ *
+ * @param The sensor interface
+ * @param int_time The integration time which can be one of:
+ * - 0x00: 100ms
+ * - 0x01: 200ms
+ * - 0x02: 300ms
+ * - 0x03: 400ms
+ * - 0x04: 500ms
+ * - 0x05: 600ms
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_set_integration_time(struct sensor_itf *itf, uint8_t int_time);
+
+/**
+ * Gets the current integration time used when sampling light values.
+ *
+ * @param The sensor interface
+ * @param ptr to the integration time which can be one of:
+ * - 0x00: 100ms
+ * - 0x01: 200ms
+ * - 0x02: 300ms
+ * - 0x03: 400ms
+ * - 0x04: 500ms
+ * - 0x05: 600ms
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_get_integration_time(struct sensor_itf *itf, uint8_t *int_time);
+
+/**
+ * Sets the gain increment used when sampling light values.
+ *
+ * @param The sensor interface
+ * @param gain The gain increment which can be one of:
+ * - 0x00: Low (no gain)
+ * - 0x10: Medium (~25x gain)
+ * - 0x20: High (~428x gain)
+ * - 0x30: Max (~9876x gain)
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_set_gain(struct sensor_itf *itf, uint8_t gain);
+
+/**
+ * Gets the current gain increment used when sampling light values.
+ *
+ * @param The sensor interface
+ * @param ptr to the gain increment which can be one of:
+ * - 0x00: Low (no gain)
+ * - 0x10: Medium (~25x gain)
+ * - 0x20: High (~428x gain)
+ * - 0x30: Max (~9876x gain)
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_get_gain(struct sensor_itf *itf, uint8_t *gain);
+
+/**
+ * Configure the sensor
+ *
+ * @param ptr to sensor driver
+ * @param ptr to sensor driver config
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_config(struct tsl2591 *, struct tsl2591_cfg *);
+
+/**
+ * Calculate light level in lux based on the full spectrum and IR readings
+ *
+ * NOTE: This function assumes that the gain and integration time used when
+ * reading the full spectrum and IR readings are the same as when this
+ * function gets called. If gain or integration time have changed, a
+ * fresh sample should be read before calling this function.
+ *
+ * @param ptr to sensor driver
+ * @param Full spectrum (broadband) light reading
+ * @param IR light reading
+ * @param ptr to the sensor driver config
+ *
+ * @return 0 on failure, otherwise the converted light level in lux as an
+ * unsigned 32-bit integer.
+ */
+uint32_t tsl2591_calculate_lux(struct sensor_itf *itf, uint16_t broadband,
+ uint16_t ir, struct tsl2591_cfg *cfg);
+
+/**
+ * Calculate light level in lux based on the full spectrum and IR readings
+ *
+ * NOTE: This function assumes that the gain and integration time used when
+ * reading the full spectrum and IR readings are the same as when this
+ * function gets called. If gain or integration time have changed, a
+ * fresh sample should be read before calling this function.
+ *
+ * @param ptr to sensor driver
+ * @param Full spectrum (broadband) light reading
+ * @param IR light reading
+ * @param ptr to the sensor driver config
+ *
+ * @return 0 on failure, otherwise the converted light level in lux as a
+ * single precision float.
+ */
+float tsl2591_calculate_lux_f(struct sensor_itf *itf, uint16_t broadband,
+ uint16_t ir, struct tsl2591_cfg *cfg);
+
+#if MYNEWT_VAL(TSL2591_CLI)
+int tsl2591_shell_init(void);
+#endif
+
+#ifdef ARCH_sim
+/**
+ * Registers the sim driver with the hal_i2c simulation layer
+ *
+ * @return 0 on success, non-zero on failure
+ */
+int tsl2591_sim_init(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TSL2591_H__ */
diff --git a/hw/drivers/sensors/tsl2591/pkg.yml b/hw/drivers/sensors/tsl2591/pkg.yml
new file mode 100644
index 0000000000..d74225b835
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/pkg.yml
@@ -0,0 +1,40 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/drivers/sensors/tsl2591
+pkg.description: Driver for the TSL2591 light to digital sensor
+pkg.author: "Kevin Townsend"
+pkg.homepage: "https://www.adafruit.com/product/1980"
+pkg.keywords:
+ - adafruit
+ - tsl2591
+ - i2c
+ - sensor
+
+pkg.deps:
+ - "@apache-mynewt-core/kernel/os"
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/sensor"
+ - "@apache-mynewt-core/sys/log/modlog"
+
+pkg.req_apis:
+ - stats
+
+pkg.deps.TSL2591_CLI:
+ - "@apache-mynewt-core/util/parse"
diff --git a/hw/drivers/sensors/tsl2591/src/tsl2591.c b/hw/drivers/sensors/tsl2591/src/tsl2591.c
new file mode 100644
index 0000000000..bdc93412a0
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/src/tsl2591.c
@@ -0,0 +1,706 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * resarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdio.h>
+#include <errno.h>
+#include <string.h>
+
+#include "os/mynewt.h"
+#include "hal/hal_i2c.h"
+#include "sensor/sensor.h"
+#include "sensor/light.h"
+#include "tsl2591/tsl2591.h"
+#include "tsl2591_priv.h"
+#include "modlog/modlog.h"
+#include "syscfg/syscfg.h"
+#include "stats/stats.h"
+
+/* Define the stats section and records */
+STATS_SECT_START(tsl2591_stat_section)
+ STATS_SECT_ENTRY(polled)
+ STATS_SECT_ENTRY(gain_changed)
+ STATS_SECT_ENTRY(timing_changed)
+ STATS_SECT_ENTRY(ints_cleared)
+ STATS_SECT_ENTRY(errors)
+STATS_SECT_END
+
+/* Define stat names for querying */
+STATS_NAME_START(tsl2591_stat_section)
+ STATS_NAME(tsl2591_stat_section, polled)
+ STATS_NAME(tsl2591_stat_section, gain_changed)
+ STATS_NAME(tsl2591_stat_section, timing_changed)
+ STATS_NAME(tsl2591_stat_section, ints_cleared)
+ STATS_NAME(tsl2591_stat_section, errors)
+STATS_NAME_END(tsl2591_stat_section)
+
+/* Global variable used to hold stats data */
+STATS_SECT_DECL(tsl2591_stat_section) g_tsl2591stats;
+
+#define TSL2591_LOG(lvl_, ...) \
+ MODLOG_ ## lvl_(MYNEWT_VAL(TSL2591_LOG_MODULE), __VA_ARGS__)
+
+#if MYNEWT_VAL(TSL2591_ITIME_DELAY)
+static int g_tsl2591_itime_delay_ms;
+#endif
+
+/* Exports for the sensor API */
+static int tsl2591_sensor_read(struct sensor *, sensor_type_t,
+ sensor_data_func_t, void *, uint32_t);
+static int tsl2591_sensor_get_config(struct sensor *, sensor_type_t,
+ struct sensor_cfg *);
+
+static const struct sensor_driver g_tsl2591_sensor_driver = {
+ tsl2591_sensor_read,
+ tsl2591_sensor_get_config
+};
+
+int
+tsl2591_write8(struct sensor_itf *itf, uint8_t reg, uint32_t value)
+{
+ int rc;
+ uint8_t payload[2] = { reg, value & 0xFF };
+
+ struct hal_i2c_master_data data_struct = {
+ .address = itf->si_addr,
+ .len = 2,
+ .buffer = payload
+ };
+
+ rc = sensor_itf_lock(itf, MYNEWT_VAL(TSL2591_ITF_LOCK_TMO));
+ if (rc) {
+ return rc;
+ }
+
+ rc = hal_i2c_master_write(itf->si_num, &data_struct,
+ OS_TICKS_PER_SEC / 10, 1);
+ if (rc) {
+ TSL2591_LOG(ERROR,
+ "Failed to write 0x%02X:0x%02X with value 0x%02lX\n",
+ data_struct.address, reg, value);
+ STATS_INC(g_tsl2591stats, errors);
+ }
+
+ sensor_itf_unlock(itf);
+
+ return rc;
+}
+
+int
+tsl2591_write16(struct sensor_itf *itf, uint8_t reg, uint16_t value)
+{
+ int rc;
+ uint8_t payload[3] = { reg, value & 0xFF, (value >> 8) & 0xFF };
+
+ struct hal_i2c_master_data data_struct = {
+ .address = itf->si_addr,
+ .len = 3,
+ .buffer = payload
+ };
+
+ rc = sensor_itf_lock(itf, MYNEWT_VAL(TSL2591_ITF_LOCK_TMO));
+ if (rc) {
+ return rc;
+ }
+
+ rc = hal_i2c_master_write(itf->si_num, &data_struct,
+ OS_TICKS_PER_SEC / 10, 1);
+ if (rc) {
+ TSL2591_LOG(ERROR,
+ "Failed to write @0x%02X with value 0x%02X 0x%02X\n",
+ reg, payload[0], payload[1]);
+ STATS_INC(g_tsl2591stats, errors);
+ }
+
+ sensor_itf_unlock(itf);
+
+ return rc;
+}
+
+int
+tsl2591_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value)
+{
+ int rc;
+ uint8_t payload;
+
+ struct hal_i2c_master_data data_struct = {
+ .address = itf->si_addr,
+ .len = 1,
+ .buffer = &payload
+ };
+
+ rc = sensor_itf_lock(itf, MYNEWT_VAL(TSL2591_ITF_LOCK_TMO));
+ if (rc) {
+ return rc;
+ }
+
+ /* Register write */
+ payload = reg;
+ rc = hal_i2c_master_write(itf->si_num, &data_struct,
+ OS_TICKS_PER_SEC / 10, 1);
+ if (rc) {
+ TSL2591_LOG(ERROR, "Failed to address sensor\n");
+ STATS_INC(g_tsl2591stats, errors);
+ goto err;
+ }
+
+ /* Read one byte back */
+ payload = 0;
+ rc = hal_i2c_master_read(itf->si_num, &data_struct,
+ OS_TICKS_PER_SEC / 10, 1);
+ *value = payload;
+ if (rc) {
+ TSL2591_LOG(ERROR, "Failed to read @0x%02X\n", reg);
+ STATS_INC(g_tsl2591stats, errors);
+ }
+
+err:
+ sensor_itf_unlock(itf);
+
+ return rc;
+}
+
+int
+tsl2591_read16(struct sensor_itf *itf, uint8_t reg, uint16_t *value)
+{
+ int rc;
+ uint8_t payload[2] = { reg, 0 };
+
+ struct hal_i2c_master_data data_struct = {
+ .address = itf->si_addr,
+ .len = 1,
+ .buffer = payload
+ };
+
+ rc = sensor_itf_lock(itf, MYNEWT_VAL(TSL2591_ITF_LOCK_TMO));
+ if (rc) {
+ return rc;
+ }
+
+ /* Register write */
+ rc = hal_i2c_master_write(itf->si_num, &data_struct,
+ OS_TICKS_PER_SEC / 10, 1);
+ if (rc) {
+ TSL2591_LOG(ERROR, "Failed to address sensor\n");
+ STATS_INC(g_tsl2591stats, errors);
+ goto err;
+ }
+
+ /* Read two bytes back */
+ memset(payload, 0, 2);
+ data_struct.len = 2;
+ rc = hal_i2c_master_read(itf->si_num, &data_struct,
+ OS_TICKS_PER_SEC / 10, 1);
+ *value = (uint16_t)payload[0] | ((uint16_t)payload[1] << 8);
+ if (rc) {
+ TSL2591_LOG(ERROR, "Failed to read @0x%02X\n", reg);
+ STATS_INC(g_tsl2591stats, errors);
+ goto err;
+ }
+
+err:
+ sensor_itf_unlock(itf);
+
+ return rc;
+}
+
+int
+tsl2591_enable(struct sensor_itf *itf, uint8_t state)
+{
+ /* Enable the device by setting the PON and AEN bits */
+ return tsl2591_write8(itf, TSL2591_COMMAND_BIT | TSL2591_REGISTER_ENABLE,
+ state ? TSL2591_ENABLE_POWERON | TSL2591_ENABLE_AEN :
+ TSL2591_ENABLE_POWEROFF);
+}
+
+int
+tsl2591_get_enable(struct sensor_itf *itf, uint8_t *enabled)
+{
+ int rc;
+ uint8_t reg;
+
+ /* Check the two enable bits (PON and AEN) */
+ rc = tsl2591_read8(itf, TSL2591_COMMAND_BIT | TSL2591_REGISTER_ENABLE,
+ ®);
+ if (rc) {
+ goto err;
+ }
+
+ *enabled = reg & (TSL2591_ENABLE_POWERON | TSL2591_ENABLE_AEN) ? 1 : 0;
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_set_integration_time(struct sensor_itf *itf,
+ uint8_t int_time)
+{
+ int rc;
+ uint8_t gain;
+
+ if (int_time > TSL2591_LIGHT_ITIME_600MS) {
+ int_time = TSL2591_LIGHT_ITIME_600MS;
+ }
+
+ rc = tsl2591_get_gain(itf, &gain);
+ if (rc) {
+ goto err;
+ }
+
+ rc = tsl2591_write8(itf, TSL2591_COMMAND_BIT | TSL2591_REGISTER_CONTROL,
+ int_time | gain);
+ if (rc) {
+ goto err;
+ }
+
+#if MYNEWT_VAL(TSL2591_ITIME_DELAY)
+ /* Set the intergration time delay value in ms (+8% margin of error) */
+ g_tsl2591_itime_delay_ms = (int_time + 1) * 108;
+#endif
+
+ /* Increment the timing changed counter */
+ STATS_INC(g_tsl2591stats, timing_changed);
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_get_integration_time(struct sensor_itf *itf, uint8_t *itime)
+{
+ int rc;
+ uint8_t reg;
+
+ rc = tsl2591_read8(itf, TSL2591_COMMAND_BIT | TSL2591_REGISTER_CONTROL,
+ ®);
+ if (rc) {
+ goto err;
+ }
+
+ *itime = reg & 0x07;
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_set_gain(struct sensor_itf *itf, uint8_t gain)
+{
+ int rc;
+ uint8_t int_time;
+
+ if ((gain != TSL2591_LIGHT_GAIN_LOW)
+ && (gain != TSL2591_LIGHT_GAIN_MED)
+ && (gain != TSL2591_LIGHT_GAIN_HIGH)
+ && (gain != TSL2591_LIGHT_GAIN_MAX)) {
+ TSL2591_LOG(ERROR, "Invalid gain value\n");
+ rc = SYS_EINVAL;
+ goto err;
+ }
+
+ rc = tsl2591_get_integration_time(itf, &int_time);
+ if (rc) {
+ goto err;
+ }
+
+ rc = tsl2591_write8(itf, TSL2591_COMMAND_BIT | TSL2591_REGISTER_CONTROL,
+ int_time | gain);
+ if (rc) {
+ goto err;
+ }
+
+ /* Increment the gain change counter */
+ STATS_INC(g_tsl2591stats, gain_changed);
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_get_gain(struct sensor_itf *itf, uint8_t *gain)
+{
+ int rc;
+ uint8_t reg;
+
+ rc = tsl2591_read8(itf, TSL2591_COMMAND_BIT | TSL2591_REGISTER_CONTROL,
+ ®);
+ if (rc) {
+ goto err;
+ }
+
+ *gain = reg & 0x30;
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_get_data_r(struct sensor_itf *itf, uint16_t *broadband, uint16_t *ir)
+{
+ int rc;
+
+#if MYNEWT_VAL(TSL2591_ITIME_DELAY)
+ /* Insert a delay of integration time to ensure valid sample */
+ os_time_delay((OS_TICKS_PER_SEC * g_tsl2591_itime_delay_ms) / 1000);
+#endif
+
+ /* CHAN0 must be read before CHAN1 */
+ /* See: https://forums.adafruit.com/viewtopic.php?f=19&t=124176 */
+ *broadband = *ir = 0;
+ rc = tsl2591_read16(itf, TSL2591_COMMAND_BIT |
+ TSL2591_REGISTER_CHAN0_LOW, broadband);
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_read16(itf, TSL2591_COMMAND_BIT |
+ TSL2591_REGISTER_CHAN1_LOW, ir);
+ if (rc) {
+ goto err;
+ }
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_get_data(struct sensor_itf *itf, uint16_t *broadband, uint16_t *ir)
+{
+ int rc;
+ uint8_t itime;
+ uint16_t igain;
+ uint16_t maxval;
+ uint16_t divisor;
+
+#if !(MYNEWT_VAL(TSL2591_AUTO_GAIN))
+ rc = tsl2591_get_data_r(itf, broadband, ir);
+ if (rc) {
+ goto err;
+ }
+
+ /* Increment the polling counter */
+ STATS_INC(g_tsl2591stats, polled);
+
+ return rc;
+#endif
+
+ /* Use auto-gain algorithm for better range at the expensive of */
+ /* unpredictable conversion times */
+
+ /* Get the integration time to determine max raw value */
+ rc = tsl2591_get_integration_time(itf, &itime);
+ if (rc) {
+ goto err;
+ }
+ /* Max value for 100ms = 37888, otherwise 65535 */
+ maxval = itime ? 65535 : 37888;
+
+ /* Set gain to 1x for the baseline conversion */
+ rc = tsl2591_set_gain(itf, TSL2591_LIGHT_GAIN_LOW);
+ if (rc) {
+ goto err;
+ }
+
+ /* Get the baseline conversion values */
+ /* Note: double-read required to empty cached values with prev gain */
+ rc = tsl2591_get_data_r(itf, broadband, ir);
+ rc = tsl2591_get_data_r(itf, broadband, ir);
+ if (rc) {
+ goto err;
+ }
+
+ /* Determine the ideal gain setting */
+ divisor = *broadband > *ir ? *broadband : *ir;
+ /* Avoid potential divide by 0 errors in low light */
+ igain = maxval / (divisor == 0 ? 1 : divisor);
+
+
+ /* Find the closest gain <= igain */
+ if (igain < 25) {
+ /* Gain 1x, return the current sample */
+ return 0;
+ } else if (igain < 428) {
+ /* Set gain to ~25x */
+ rc = tsl2591_set_gain(itf, TSL2591_LIGHT_GAIN_MED);
+ if (rc) {
+ goto err;
+ }
+ } else if (igain < 9876) {
+ /* Set gain to ~428x */
+ rc = tsl2591_set_gain(itf, TSL2591_LIGHT_GAIN_HIGH);
+ if (rc) {
+ goto err;
+ }
+ } else {
+ /* Set gain to ~9876x */
+ rc = tsl2591_set_gain(itf, TSL2591_LIGHT_GAIN_MAX);
+ if (rc) {
+ goto err;
+ }
+ }
+
+ /* Get a new data sample */
+ /* Note: double-read required to empty cached values with prev gain */
+ rc = tsl2591_get_data_r(itf, broadband, ir);
+ rc = tsl2591_get_data_r(itf, broadband, ir);
+ if (rc) {
+ goto err;
+ }
+
+ /* Increment the polling counter */
+ STATS_INC(g_tsl2591stats, polled);
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_init(struct os_dev *dev, void *arg)
+{
+ struct tsl2591 *tsl2591;
+ struct sensor *sensor;
+ int rc;
+
+ if (!arg || !dev) {
+ rc = SYS_ENODEV;
+ goto err;
+ }
+
+ tsl2591 = (struct tsl2591 *) dev;
+
+ tsl2591->cfg.mask = SENSOR_TYPE_ALL;
+
+ sensor = &tsl2591->sensor;
+
+ /* Initialise the stats entry */
+ rc = stats_init(
+ STATS_HDR(g_tsl2591stats),
+ STATS_SIZE_INIT_PARMS(g_tsl2591stats, STATS_SIZE_32),
+ STATS_NAME_INIT_PARMS(tsl2591_stat_section));
+ SYSINIT_PANIC_ASSERT(rc == 0);
+ /* Register the entry with the stats registry */
+ rc = stats_register(dev->od_name, STATS_HDR(g_tsl2591stats));
+ SYSINIT_PANIC_ASSERT(rc == 0);
+
+#ifdef ARCH_sim
+ /* Register the sim driver */
+ tsl2591_sim_init();
+#endif
+
+ rc = sensor_init(sensor, dev);
+ if (rc) {
+ goto err;
+ }
+
+ /* Add the light driver */
+ rc = sensor_set_driver(sensor, SENSOR_TYPE_LIGHT,
+ (struct sensor_driver *) &g_tsl2591_sensor_driver);
+ if (rc) {
+ goto err;
+ }
+
+ /* Set the interface */
+ rc = sensor_set_interface(sensor, arg);
+ if (rc) {
+ goto err;
+ }
+
+ rc = sensor_mgr_register(sensor);
+ if (rc) {
+ goto err;
+ }
+
+ return 0;
+err:
+ STATS_INC(g_tsl2591stats, errors);
+ return rc;
+}
+
+float tsl2591_calculate_lux_f(struct sensor_itf *itf, uint16_t broadband,
+ uint16_t ir, struct tsl2591_cfg *cfg)
+{
+ int rc;
+ uint8_t itime;
+ uint8_t gain;
+ float again;
+ float cpl;
+ float lux;
+
+ /* Check for overflow conditions */
+ if ((broadband == 0xFFFF) | (ir == 0xFFFF)) {
+ return 0;
+ }
+
+ rc = tsl2591_get_gain(itf, &gain);
+ if (rc) {
+ return 0;
+ }
+
+ switch (gain)
+ {
+ case TSL2591_LIGHT_GAIN_MED :
+ again = 25.0F;
+ break;
+ case TSL2591_LIGHT_GAIN_HIGH :
+ again = 428.0F;
+ break;
+ case TSL2591_LIGHT_GAIN_MAX :
+ again = 9876.0F;
+ break;
+ case TSL2591_LIGHT_GAIN_LOW :
+ default:
+ again = 1.0F;
+ break;
+ }
+
+ rc = tsl2591_get_integration_time(itf, &itime);
+ if (rc) {
+ return 0;
+ }
+
+ cpl = ((float)((itime+1)*101) * again) / TSL2591_LUX_DF;
+
+ lux = (((float)broadband - (float)ir)) *
+ (1.0F - ((float)ir/(float)broadband)) / cpl;
+
+ /* Note that this implementation will truncate values < 1.0 lux! */
+ return lux;
+}
+
+uint32_t
+tsl2591_calculate_lux(struct sensor_itf *itf, uint16_t broadband, uint16_t ir,
+ struct tsl2591_cfg *cfg)
+{
+ return (uint32_t)tsl2591_calculate_lux_f(itf, broadband, ir, cfg);
+}
+
+static int
+tsl2591_sensor_read(struct sensor *sensor, sensor_type_t type,
+ sensor_data_func_t data_func, void *data_arg, uint32_t timeout)
+{
+ struct tsl2591 *tsl2591;
+ struct sensor_light_data sld;
+ struct sensor_itf *itf;
+ uint16_t full;
+ uint16_t ir;
+ uint32_t lux;
+ int rc;
+
+ /* If the read isn't looking for light data, don't do anything. */
+ if (!(type & SENSOR_TYPE_LIGHT)) {
+ rc = SYS_EINVAL;
+ goto err;
+ }
+
+ itf = SENSOR_GET_ITF(sensor);
+ tsl2591 = (struct tsl2591 *)SENSOR_GET_DEVICE(sensor);
+
+ /* Get a new light sample */
+ if (type & SENSOR_TYPE_LIGHT) {
+ full = ir = 0;
+
+ rc = tsl2591_get_data(itf, &full, &ir);
+ if (rc) {
+ goto err;
+ }
+
+ lux = tsl2591_calculate_lux(itf, full, ir, &(tsl2591->cfg));
+ sld.sld_full = full;
+ sld.sld_ir = ir;
+ sld.sld_lux = lux;
+
+ sld.sld_full_is_valid = 1;
+ sld.sld_ir_is_valid = 1;
+ sld.sld_lux_is_valid = 1;
+
+ /* Call data function */
+ rc = data_func(sensor, data_arg, &sld, SENSOR_TYPE_LIGHT);
+ if (rc != 0) {
+ goto err;
+ }
+ }
+
+ return 0;
+err:
+ return rc;
+}
+
+static int
+tsl2591_sensor_get_config(struct sensor *sensor, sensor_type_t type,
+ struct sensor_cfg *cfg)
+{
+ int rc;
+
+ if ((type != SENSOR_TYPE_LIGHT)) {
+ rc = SYS_EINVAL;
+ goto err;
+ }
+
+ cfg->sc_valtype = SENSOR_VALUE_TYPE_INT32;
+
+ return 0;
+err:
+ return rc;
+}
+
+int
+tsl2591_config(struct tsl2591 *tsl2591, struct tsl2591_cfg *cfg)
+{
+ int rc;
+ struct sensor_itf *itf;
+
+ itf = SENSOR_GET_ITF(&(tsl2591->sensor));
+
+ rc = tsl2591_enable(itf, 1);
+ if (rc) {
+ goto err;
+ }
+
+ rc = tsl2591_set_integration_time(itf, cfg->integration_time);
+ if (rc) {
+ goto err;
+ }
+
+ tsl2591->cfg.integration_time = cfg->integration_time;
+
+ rc = tsl2591_set_gain(itf, cfg->gain);
+ if (rc) {
+ goto err;
+ }
+
+ tsl2591->cfg.gain = cfg->gain;
+
+ rc = sensor_set_type_mask(&(tsl2591->sensor), cfg->mask);
+ if (rc) {
+ goto err;
+ }
+
+ tsl2591->cfg.mask = cfg->mask;
+
+ return 0;
+err:
+ return rc;
+}
diff --git a/hw/drivers/sensors/tsl2591/src/tsl2591_priv.h b/hw/drivers/sensors/tsl2591/src/tsl2591_priv.h
new file mode 100644
index 0000000000..e06e4bb430
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/src/tsl2591_priv.h
@@ -0,0 +1,78 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * resarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __TSL2591_PRIV_H__
+#define __TSL2591_PRIV_H__
+
+#define TSL2591_REGISTER_ENABLE (0x00) /*< Enable register */
+#define TSL2591_REGISTER_CONTROL (0x01) /*< Control register */
+#define TSL2591_REGISTER_THRESHOLD_AILTL (0x04) /*< ALS low threshold lower byte */
+#define TSL2591_REGISTER_THRESHOLD_AILTH (0x05) /*< ALS low threshold upper byte */
+#define TSL2591_REGISTER_THRESHOLD_AIHTL (0x06) /*< ALS high threshold lower byte */
+#define TSL2591_REGISTER_THRESHOLD_AIHTH (0x07) /*< ALS high threshold upper byte */
+#define TSL2591_REGISTER_THRESHOLD_NPAILTL (0x08) /*< No Persist ALS low threshold lower byte */
+#define TSL2591_REGISTER_THRESHOLD_NPAILTH (0x09) /*< No Persist ALS low threshold higher byte */
+#define TSL2591_REGISTER_THRESHOLD_NPAIHTL (0x0A) /*< No Persist ALS high threshold lower byte */
+#define TSL2591_REGISTER_THRESHOLD_NPAIHTH (0x0B) /*< No Persist ALS high threshold higher byte */
+#define TSL2591_REGISTER_PERSIST_FILTER (0x0C) /*< Interrupt persistence filter */
+#define TSL2591_REGISTER_PACKAGE_PID (0x11) /*< Package Identification */
+#define TSL2591_REGISTER_DEVICE_ID (0x12) /*< Device Identification */
+#define TSL2591_REGISTER_DEVICE_STATUS (0x13) /*< Internal Status */
+#define TSL2591_REGISTER_CHAN0_LOW (0x14) /*< Channel 0 data, low byte */
+#define TSL2591_REGISTER_CHAN0_HIGH (0x15) /*< Channel 0 data, high byte */
+#define TSL2591_REGISTER_CHAN1_LOW (0x16) /*< Channel 1 data, low byte */
+#define TSL2591_REGISTER_CHAN1_HIGH (0x17) /*< Channel 1 data, high byte */
+
+#define TSL2591_VISIBLE (2) /*< (channel 0) - (channel 1) */
+#define TSL2591_INFRARED (1) /*< channel 1 */
+#define TSL2591_FULLSPECTRUM (0) /*< channel 0 */
+
+#define TSL2591_COMMAND_BIT (0xA0) /*< 1010 0000: bits 7 and 5 for 'command normal' */
+
+#define TSL2591_CLEAR_INT (0xE7) /*! Special Function Command for "Clear ALS and no persist ALS interrupt" */
+#define TSL2591_TEST_INT (0xE4) /*! Special Function Command for "Interrupt set - forces an interrupt" */
+
+#define TSL2591_WORD_BIT (0x20) /*< 1 = read/write word (rather than byte) */
+#define TSL2591_BLOCK_BIT (0x10) /*< 1 = using block read/write */
+
+#define TSL2591_ENABLE_POWEROFF (0x00) /*< Flag for ENABLE register to disable */
+#define TSL2591_ENABLE_POWERON (0x01) /*< Flag for ENABLE register to enable */
+#define TSL2591_ENABLE_AEN (0x02) /*< ALS Enable. This field activates ALS function. Writing a one activates the ALS. Writing a zero disables the ALS. */
+#define TSL2591_ENABLE_AIEN (0x10) /*< ALS Interrupt Enable. When asserted permits ALS interrupts to be generated, subject to the persist filter. */
+#define TSL2591_ENABLE_NPIEN (0x80) /*< No Persist Interrupt Enable. When asserted NP Threshold conditions will generate an interrupt, bypassing the persist filter */
+
+#define TSL2591_LUX_DF (408.0F) /*< Lux cooefficient */
+#define TSL2591_LUX_COEFB (1.64F) /*< CH0 coefficient */
+#define TSL2591_LUX_COEFC (0.59F) /*< CH1 coefficient A */
+#define TSL2591_LUX_COEFD (0.86F) /*< CH2 coefficient B */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int tsl2591_write8(struct sensor_itf *itf, uint8_t reg, uint32_t value);
+int tsl2591_write16(struct sensor_itf *itf, uint8_t reg, uint16_t value);
+int tsl2591_read8(struct sensor_itf *itf, uint8_t reg, uint8_t *value);
+int tsl2591_read16(struct sensor_itf *itf, uint8_t reg, uint16_t *value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TSL2591_PRIV_H_ */
diff --git a/hw/drivers/sensors/tsl2591/src/tsl2591_shell.c b/hw/drivers/sensors/tsl2591/src/tsl2591_shell.c
new file mode 100644
index 0000000000..48a04dc9b1
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/src/tsl2591_shell.c
@@ -0,0 +1,457 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * resarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <string.h>
+#include <errno.h>
+#include "os/mynewt.h"
+#include "console/console.h"
+#include "shell/shell.h"
+#include "hal/hal_gpio.h"
+#include "tsl2591/tsl2591.h"
+#include "tsl2591_priv.h"
+#include "parse/parse.h"
+
+#if MYNEWT_VAL(TSL2591_CLI)
+
+static int tsl2591_shell_cmd(int argc, char **argv);
+
+static struct shell_cmd tsl2591_shell_cmd_struct = {
+ .sc_cmd = "tsl2591",
+ .sc_cmd_func = tsl2591_shell_cmd
+};
+
+static struct sensor_itf g_sensor_itf = {
+ .si_type = MYNEWT_VAL(TSL2591_SHELL_ITF_TYPE),
+ .si_num = MYNEWT_VAL(TSL2591_SHELL_ITF_NUM),
+ .si_addr = MYNEWT_VAL(TSL2591_SHELL_ITF_ADDR),
+};
+
+static int
+tsl2591_shell_err_too_many_args(char *cmd_name)
+{
+ console_printf("Error: too many arguments for command \"%s\"\n",
+ cmd_name);
+ return EINVAL;
+}
+
+static int
+tsl2591_shell_err_unknown_arg(char *cmd_name)
+{
+ console_printf("Error: unknown argument \"%s\"\n",
+ cmd_name);
+ return EINVAL;
+}
+
+static int
+tsl2591_shell_err_invalid_arg(char *cmd_name)
+{
+ console_printf("Error: invalid argument \"%s\"\n",
+ cmd_name);
+ return EINVAL;
+}
+
+static int
+tsl2591_shell_help(void)
+{
+ console_printf("%s cmd [flags...]\n", tsl2591_shell_cmd_struct.sc_cmd);
+ console_printf("cmd:\n");
+ console_printf("\tr [n_samples]\n");
+ console_printf("\tgain [0|1|2|3]\n");
+ console_printf("\ttime [100|200|300|400|500|600]\n");
+ console_printf("\ten [0|1]\n");
+ console_printf("\tdump\n");
+
+ return 0;
+}
+
+static int
+tsl2591_shell_cmd_read(int argc, char **argv)
+{
+ uint16_t full;
+ uint16_t ir;
+ uint16_t samples;
+ uint16_t val;
+ float lux;
+ int rc;
+
+ samples = 1;
+
+ if (argc > 3) {
+ return tsl2591_shell_err_too_many_args(argv[1]);
+ }
+
+ /* Check if more than one sample requested */
+ if (argc == 3) {
+ val = parse_ll_bounds(argv[2], 1, UINT16_MAX, &rc);
+ if (rc) {
+ return tsl2591_shell_err_invalid_arg(argv[2]);
+ }
+ samples = val;
+ }
+
+ while(samples--) {
+ /* Get raw broadband and IR readings */
+ rc = tsl2591_get_data(&g_sensor_itf, &full, &ir);
+ if (rc) {
+ console_printf("Read failed: %d\n", rc);
+ return rc;
+ }
+ /* Get lux estimation */
+ lux = tsl2591_calculate_lux_f(&g_sensor_itf, full, ir, NULL);
+ console_printf("Lux: %lu.%lu\n", (uint32_t)lux,
+ (uint32_t)(lux*1000)%1000);
+ console_printf("Full: %u\n", full);
+ console_printf("IR: %u\n", ir);
+ }
+
+ return 0;
+}
+
+static int
+tsl2591_shell_cmd_gain(int argc, char **argv)
+{
+ uint8_t val;
+ uint8_t gain;
+ int rc;
+
+ if (argc > 3) {
+ return tsl2591_shell_err_too_many_args(argv[1]);
+ }
+
+ /* Display the gain */
+ if (argc == 2) {
+ rc = tsl2591_get_gain(&g_sensor_itf, &gain);
+ if (rc) {
+ console_printf("Getting gain failed rc:%d", rc);
+ goto err;
+ }
+ switch (gain) {
+ case TSL2591_LIGHT_GAIN_LOW:
+ console_printf("0 (1x)\n");
+ break;
+ case TSL2591_LIGHT_GAIN_MED:
+ console_printf("1 (25x)\n");
+ break;
+ case TSL2591_LIGHT_GAIN_HIGH:
+ console_printf("2 (428x)\n");
+ break;
+ case TSL2591_LIGHT_GAIN_MAX:
+ console_printf("3 (9876x)\n");
+ break;
+ default:
+ console_printf("ERROR!\n");
+ break;
+ }
+ }
+
+ /* Update the gain */
+ if (argc == 3) {
+ val = parse_ll_bounds(argv[2], 0, 3, &rc);
+ /* Make sure gain is valid */
+ if (rc) {
+ return tsl2591_shell_err_invalid_arg(argv[2]);
+ }
+ rc = tsl2591_set_gain(&g_sensor_itf, val << 4);
+ if (rc) {
+ console_printf("Setting gain failed rc:%d", rc);
+ }
+ }
+
+err:
+ return rc;
+}
+
+static int
+tsl2591_shell_cmd_time(int argc, char **argv)
+{
+ uint8_t time;
+ long val;
+ int rc;
+
+ if (argc > 3) {
+ return tsl2591_shell_err_too_many_args(argv[1]);
+ }
+
+ /* Display the integration time */
+ if (argc == 2) {
+ rc = tsl2591_get_integration_time(&g_sensor_itf, &time);
+ if (rc) {
+ console_printf("Getting integration time failed rc:%d", rc);
+ goto err;
+ }
+
+ switch (time) {
+ case TSL2591_LIGHT_ITIME_100MS:
+ console_printf("100\n");
+ break;
+ case TSL2591_LIGHT_ITIME_200MS:
+ console_printf("200\n");
+ break;
+ case TSL2591_LIGHT_ITIME_300MS:
+ console_printf("300\n");
+ break;
+ case TSL2591_LIGHT_ITIME_400MS:
+ console_printf("400\n");
+ break;
+ case TSL2591_LIGHT_ITIME_500MS:
+ console_printf("500\n");
+ break;
+ case TSL2591_LIGHT_ITIME_600MS:
+ console_printf("600\n");
+ break;
+ }
+ }
+
+ /* Set the integration time */
+ if (argc == 3) {
+ val = parse_ll_bounds(argv[2], 100, 600, &rc);
+ /* Make sure val is 100, 200, 300, 400, 500 or 600 */
+ if (rc || ((val != 100) && (val != 200) && (val != 300) &&
+ (val != 400) && (val != 500) && (val != 600))) {
+ return tsl2591_shell_err_invalid_arg(argv[2]);
+ }
+ switch(val) {
+ case 100:
+ rc = tsl2591_set_integration_time(&g_sensor_itf, TSL2591_LIGHT_ITIME_100MS);
+ break;
+ case 200:
+ rc = tsl2591_set_integration_time(&g_sensor_itf, TSL2591_LIGHT_ITIME_200MS);
+ break;
+ case 300:
+ rc = tsl2591_set_integration_time(&g_sensor_itf, TSL2591_LIGHT_ITIME_300MS);
+ break;
+ case 400:
+ rc = tsl2591_set_integration_time(&g_sensor_itf, TSL2591_LIGHT_ITIME_400MS);
+ break;
+ case 500:
+ rc = tsl2591_set_integration_time(&g_sensor_itf, TSL2591_LIGHT_ITIME_500MS);
+ break;
+ case 600:
+ rc = tsl2591_set_integration_time(&g_sensor_itf, TSL2591_LIGHT_ITIME_600MS);
+ break;
+ }
+
+ if (rc) {
+ console_printf("Setting integration time failed rc:%d", rc);
+ }
+ }
+
+err:
+ return rc;
+}
+
+static int
+tsl2591_shell_cmd_en(int argc, char **argv)
+{
+ char *endptr;
+ long lval;
+ int rc;
+ uint8_t enabled;
+
+ if (argc > 3) {
+ return tsl2591_shell_err_too_many_args(argv[1]);
+ }
+
+ /* Display current enable state */
+ if (argc == 2) {
+ rc = tsl2591_get_enable(&g_sensor_itf, &enabled);
+ if (rc) {
+ console_printf("Enable read failure rc:%d", rc);
+ goto err;
+ }
+
+ console_printf("%u\n", enabled);
+ }
+
+ /* Update the enable state */
+ if (argc == 3) {
+ lval = strtol(argv[2], &endptr, 10); /* Base 10 */
+ if (argv[2][0] != '\0' && *endptr == '\0' &&
+ lval >= 0 && lval <= 1) {
+ rc = tsl2591_enable(&g_sensor_itf, lval);
+ if (rc) {
+ console_printf("Could not enable sensor rc:%d", rc);
+ goto err;
+ }
+ } else {
+ return tsl2591_shell_err_invalid_arg(argv[2]);
+ }
+ }
+
+ return 0;
+err:
+ return rc;
+}
+
+static int
+tsl2591_shell_print_reg(int reg, char *name)
+{
+ uint8_t val;
+ int rc;
+
+ val = 0;
+ rc = tsl2591_read8(&g_sensor_itf,
+ TSL2591_COMMAND_BIT | reg,
+ &val);
+ if (rc) {
+ goto err;
+ }
+ console_printf("0x%02X (%s): 0x%02X\n", reg, name, val);
+
+ return 0;
+err:
+ return rc;
+}
+
+static int
+tsl2591_shell_cmd_dump(int argc, char **argv)
+{
+ int rc;
+
+ if (argc > 3) {
+ return tsl2591_shell_err_too_many_args(argv[1]);
+ }
+
+ /* Dump all the register values for debug purposes */
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_ENABLE, "ENABLE");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_CONTROL, "CONTROL");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_AILTL, "AILTL");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_AILTH, "AILTH");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_AIHTL, "AIHTL");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_AIHTH, "AIHTH");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_NPAILTL, "NPAILTL");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_NPAILTH, "NPAILTH");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_NPAIHTL, "NPAIHTL");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_THRESHOLD_NPAIHTH, "NPAIHTH");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_PERSIST_FILTER, "FILTER");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_PACKAGE_PID, "PACKAGEID");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_DEVICE_ID, "DEVICEID");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_DEVICE_STATUS, "STATUS");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_CHAN0_LOW, "CHAN0_LOW");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_CHAN0_HIGH, "CHAN0_HIGH");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_CHAN1_LOW, "CHAN1_LOW");
+ if (rc) {
+ goto err;
+ }
+ rc = tsl2591_shell_print_reg(TSL2591_REGISTER_CHAN1_HIGH, "CHAN1_HIGH");
+ if (rc) {
+ goto err;
+ }
+
+ return 0;
+err:
+ console_printf("Read failed rc:%d", rc);
+ return rc;
+}
+
+static int
+tsl2591_shell_cmd(int argc, char **argv)
+{
+ if (argc == 1) {
+ return tsl2591_shell_help();
+ }
+
+ /* Read command (get a new data sample) */
+ if (argc > 1 && strcmp(argv[1], "r") == 0) {
+ return tsl2591_shell_cmd_read(argc, argv);
+ }
+
+ /* Gain command */
+ if (argc > 1 && strcmp(argv[1], "gain") == 0) {
+ return tsl2591_shell_cmd_gain(argc, argv);
+ }
+
+ /* Integration time command */
+ if (argc > 1 && strcmp(argv[1], "time") == 0) {
+ return tsl2591_shell_cmd_time(argc, argv);
+ }
+
+ /* Enable */
+ if (argc > 1 && strcmp(argv[1], "en") == 0) {
+ return tsl2591_shell_cmd_en(argc, argv);
+ }
+
+ /* Debug */
+ if (argc > 1 && strcmp(argv[1], "dump") == 0) {
+ return tsl2591_shell_cmd_dump(argc, argv);
+ }
+
+ return tsl2591_shell_err_unknown_arg(argv[1]);
+}
+
+int
+tsl2591_shell_init(void)
+{
+ int rc;
+
+ rc = shell_cmd_register(&tsl2591_shell_cmd_struct);
+ SYSINIT_PANIC_ASSERT(rc == 0);
+
+ return rc;
+}
+
+#endif
diff --git a/hw/drivers/sensors/tsl2591/src/tsl2591_sim.c b/hw/drivers/sensors/tsl2591/src/tsl2591_sim.c
new file mode 100644
index 0000000000..30c6d3d7e4
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/src/tsl2591_sim.c
@@ -0,0 +1,122 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * resarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifdef ARCH_sim
+
+#include <string.h>
+#include <errno.h>
+#include "os/mynewt.h"
+#include "tsl2591/tsl2591.h"
+#include "tsl2591_priv.h"
+#include "mcu/mcu_sim_i2c.h"
+
+/* Default register values for this sensor */
+static uint8_t g_tsl2591_sim_regs[TSL2591_REGISTER_CHAN1_HIGH] = {
+ /* 0x00 = TSL2591_REGISTER_ENABLE */
+ 0x00,
+ /* 0x01 = TSL2591_REGISTER_CONTROL */
+ 0x00,
+ /* 0x02 = RESERVED */
+ 0x00,
+ /* 0x03 = RESERVED */
+ 0x00,
+ /* 0x04 = TSL2591_REGISTER_THRESHOLD_AILTL */
+ 0x00,
+ /* 0x05 = TSL2591_REGISTER_THRESHOLD_AILTH */
+ 0x00,
+ /* 0x06 = TSL2591_REGISTER_THRESHOLD_AIHTL */
+ 0x00,
+ /* 0x07 = TSL2591_REGISTER_THRESHOLD_AIHTH */
+ 0x00,
+ /* 0x08 = TSL2591_REGISTER_THRESHOLD_NPAILTL */
+ 0x00,
+ /* 0x09 = TSL2591_REGISTER_THRESHOLD_NPAILTH */
+ 0x00,
+ /* 0x0A = TSL2591_REGISTER_THRESHOLD_NPAIHTL */
+ 0x00,
+ /* 0x0B = TSL2591_REGISTER_THRESHOLD_NPAIHTH */
+ 0x00,
+ /* 0x0C = TSL2591_REGISTER_PERSIST_FILTER */
+ 0x00,
+ /* 0x11 = TSL2591_REGISTER_PACKAGE_PID */
+ 0x00,
+ /* 0x12 = TSL2591_REGISTER_DEVICE_ID */
+ 0x50,
+ /* 0x13 = TSL2591_REGISTER_DEVICE_STATUS */
+ 0x00,
+ /* 0x14 = TSL2591_REGISTER_CHAN0_LOW */
+ 0x00,
+ /* 0x15 = TSL2591_REGISTER_CHAN0_HIGH */
+ 0x00,
+ /* 0x16 = TSL2591_REGISTER_CHAN1_LOW */
+ 0x00,
+ /* 0x17 = TSL2591_REGISTER_CHAN1_HIGH */
+ 0x00
+};
+
+int
+tsl2591_sensor_sim_write(uint8_t i2c_num, struct hal_i2c_master_data *pdata,
+ uint32_t timeout, uint8_t last_op)
+{
+ printf("TSL2591 wrote %d byte(s):", pdata->len);
+ for (uint16_t i=0; i<pdata->len; i++) {
+ printf(" 0x%02X", pdata->buffer[i]);
+ }
+ printf("\n");
+ fflush(stdout);
+
+ return 0;
+}
+
+int
+tsl2591_sensor_sim_read(uint8_t i2c_num, struct hal_i2c_master_data *pdata,
+ uint32_t timeout, uint8_t last_op)
+{
+ printf("TSL2591 read %d byte(s):", pdata->len);
+ for (uint16_t i=0; i<pdata->len; i++) {
+ printf(" 0x%02X", pdata->buffer[i]);
+ }
+ printf("\n");
+ fflush(stdout);
+
+ return 0;
+}
+
+static const struct hal_i2c_sim_driver g_tsl2591_sensor_sim_driver = {
+ .sd_write = tsl2591_sensor_sim_write,
+ .sd_read = tsl2591_sensor_sim_read,
+ .addr = MYNEWT_VAL(TSL2591_SHELL_ITF_ADDR)
+};
+
+int
+tsl2591_sim_init(void)
+{
+ printf("Registering TSL2591 sim driver\n");
+ fflush(stdout);
+
+ (void)g_tsl2591_sim_regs;
+
+ /* Register this sim driver with the hal_i2c simulator */
+ hal_i2c_sim_register((struct hal_i2c_sim_driver *)
+ &g_tsl2591_sensor_sim_driver);
+
+ return 0;
+}
+
+#endif /* ARCH_sim */
diff --git a/hw/drivers/sensors/tsl2591/syscfg.yml b/hw/drivers/sensors/tsl2591/syscfg.yml
new file mode 100644
index 0000000000..0efb9d238a
--- /dev/null
+++ b/hw/drivers/sensors/tsl2591/syscfg.yml
@@ -0,0 +1,44 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ TSL2591_CLI:
+ description: 'Enable shell support for the TSL2591'
+ value: 0
+ TSL2591_AUTO_GAIN:
+ description: 'Enable auto gain adjustements when reading samples'
+ value: 0
+ TSL2591_SHELL_ITF_TYPE:
+ description: 'Select interface type'
+ value: 1
+ TSL2591_SHELL_ITF_NUM:
+ description: 'Select interface number'
+ value: 0
+ TSL2591_SHELL_ITF_ADDR:
+ description: 'TSL2591 I2C Addresss'
+ value: 0x29
+ TSL2591_ITF_LOCK_TMO:
+ description: 'TSL2591 interface lock timeout in milliseconds'
+ value: 1000
+ TSL2591_ITIME_DELAY:
+ description: 'Enable an internal read delay based on integration time'
+ value: 0
+ TSL2591_LOG_MODULE:
+ description: 'Numeric module ID to use for TSL2591 log messages'
+ value: 108
diff --git a/hw/drivers/trng/trng_nrf52/pkg.yml b/hw/drivers/trng/trng_nrf52/pkg.yml
index 9d9dc048d2..75161fd594 100644
--- a/hw/drivers/trng/trng_nrf52/pkg.yml
+++ b/hw/drivers/trng/trng_nrf52/pkg.yml
@@ -27,4 +27,4 @@ pkg.apis:
- TRNG_HW_IMPL
pkg.deps:
- - hw/drivers/trng
+ - "@apache-mynewt-core/hw/drivers/trng"
diff --git a/hw/drivers/trng/trng_stm32/pkg.yml b/hw/drivers/trng/trng_stm32/pkg.yml
index edd928a386..57aecf1e91 100644
--- a/hw/drivers/trng/trng_stm32/pkg.yml
+++ b/hw/drivers/trng/trng_stm32/pkg.yml
@@ -26,4 +26,4 @@ pkg.keywords:
pkg.apis:
- TRNG_HW_IMPL
pkg.deps:
- - hw/drivers/trng
+ - "@apache-mynewt-core/hw/drivers/trng"
diff --git a/hw/drivers/uart/uart_bitbang/pkg.yml b/hw/drivers/uart/uart_bitbang/pkg.yml
index dfbe3651bc..8e28897db3 100644
--- a/hw/drivers/uart/uart_bitbang/pkg.yml
+++ b/hw/drivers/uart/uart_bitbang/pkg.yml
@@ -24,5 +24,5 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.apis:
pkg.deps:
- - hw/hal
- - hw/drivers/uart
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/drivers/uart"
diff --git a/hw/drivers/uart/uart_hal/pkg.yml b/hw/drivers/uart/uart_hal/pkg.yml
index 0827a05820..996e93931e 100644
--- a/hw/drivers/uart/uart_hal/pkg.yml
+++ b/hw/drivers/uart/uart_hal/pkg.yml
@@ -24,5 +24,5 @@ pkg.homepage: "http://mynewt.apache.org/"
pkg.keywords:
pkg.apis:
pkg.deps:
- - hw/hal
- - hw/drivers/uart
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/drivers/uart"
diff --git a/hw/mcu/ambiq/apollo2/pkg.yml b/hw/mcu/ambiq/apollo2/pkg.yml
index df339b9766..b68a575031 100644
--- a/hw/mcu/ambiq/apollo2/pkg.yml
+++ b/hw/mcu/ambiq/apollo2/pkg.yml
@@ -26,7 +26,7 @@ pkg.keywords:
- apollo2
pkg.deps:
- - hw/hal
- - hw/mcu/ambiq
- - hw/cmsis-core
- - compiler/arm-none-eabi-m4
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/ambiq"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/compiler/arm-none-eabi-m4"
diff --git a/hw/mcu/ambiq/pkg.yml b/hw/mcu/ambiq/pkg.yml
index ae89b65c05..1574cee61c 100644
--- a/hw/mcu/ambiq/pkg.yml
+++ b/hw/mcu/ambiq/pkg.yml
@@ -36,5 +36,5 @@ pkg.cflags:
- '-Wno-enum-compare'
pkg.deps:
- - hw/hal
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/arc/pkg.yml b/hw/mcu/arc/pkg.yml
index db5c87e6a1..f0e6141153 100644
--- a/hw/mcu/arc/pkg.yml
+++ b/hw/mcu/arc/pkg.yml
@@ -36,4 +36,4 @@ pkg.src_dirs:
- "src/ext/sdk/"
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/mcu/arc/snps/pkg.yml b/hw/mcu/arc/snps/pkg.yml
index 2d49676db2..2119f44594 100644
--- a/hw/mcu/arc/snps/pkg.yml
+++ b/hw/mcu/arc/snps/pkg.yml
@@ -25,5 +25,5 @@ pkg.keywords:
- arc
pkg.deps:
- - hw/hal
- - hw/mcu/arc
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/arc"
diff --git a/hw/mcu/microchip/pic32mx470f512h/pkg.yml b/hw/mcu/microchip/pic32mx470f512h/pkg.yml
index 08eeb73db8..1bc575c547 100644
--- a/hw/mcu/microchip/pic32mx470f512h/pkg.yml
+++ b/hw/mcu/microchip/pic32mx470f512h/pkg.yml
@@ -25,4 +25,4 @@ pkg.keywords:
- pic32
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/mcu/microchip/pic32mz2048efg100/pkg.yml b/hw/mcu/microchip/pic32mz2048efg100/pkg.yml
index a7c3712164..171b9f32d3 100644
--- a/hw/mcu/microchip/pic32mz2048efg100/pkg.yml
+++ b/hw/mcu/microchip/pic32mz2048efg100/pkg.yml
@@ -25,4 +25,4 @@ pkg.keywords:
- pic32
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/mcu/mips/danube/pkg.yml b/hw/mcu/mips/danube/pkg.yml
index fb586e81d3..80de97b816 100644
--- a/hw/mcu/mips/danube/pkg.yml
+++ b/hw/mcu/mips/danube/pkg.yml
@@ -26,4 +26,4 @@ pkg.keywords:
- danube
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/mcu/native/pkg.yml b/hw/mcu/native/pkg.yml
index 72e7c72901..29e7044398 100644
--- a/hw/mcu/native/pkg.yml
+++ b/hw/mcu/native/pkg.yml
@@ -26,7 +26,7 @@ pkg.keywords:
- x86
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
pkg.req_apis:
- console
diff --git a/hw/mcu/nordic/nrf51xxx/include/mcu/mcu.h b/hw/mcu/nordic/nrf51xxx/include/mcu/mcu.h
index 2bf6ee0816..c854b229a3 100644
--- a/hw/mcu/nordic/nrf51xxx/include/mcu/mcu.h
+++ b/hw/mcu/nordic/nrf51xxx/include/mcu/mcu.h
@@ -24,6 +24,8 @@
extern "C" {
#endif
+#define SVC_IRQ_NUMBER SVCall_IRQn
+
/*
* Defines for naming GPIOs.
*/
diff --git a/hw/mcu/nordic/nrf51xxx/pkg.yml b/hw/mcu/nordic/nrf51xxx/pkg.yml
index 577a553b44..98055c2934 100644
--- a/hw/mcu/nordic/nrf51xxx/pkg.yml
+++ b/hw/mcu/nordic/nrf51xxx/pkg.yml
@@ -26,6 +26,6 @@ pkg.keywords:
- nrfx
pkg.deps:
- - hw/mcu/nordic
- - hw/cmsis-core
- - hw/hal
+ - "@apache-mynewt-core/hw/mcu/nordic"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/mcu/nordic/nrf51xxx/src/hal_gpio.c b/hw/mcu/nordic/nrf51xxx/src/hal_gpio.c
index eb997e0dd4..67e1f197b2 100644
--- a/hw/mcu/nordic/nrf51xxx/src/hal_gpio.c
+++ b/hw/mcu/nordic/nrf51xxx/src/hal_gpio.c
@@ -97,7 +97,8 @@ hal_gpio_init_out(int pin, int val)
} else {
NRF_GPIO->OUTCLR = HAL_GPIO_MASK(pin);
}
- NRF_GPIO->PIN_CNF[pin] = GPIO_PIN_CNF_DIR_Output;
+ NRF_GPIO->PIN_CNF[pin] = GPIO_PIN_CNF_DIR_Output |
+ (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
NRF_GPIO->DIRSET = HAL_GPIO_MASK(pin);
return 0;
}
diff --git a/hw/mcu/nordic/nrf52xxx/pkg.yml b/hw/mcu/nordic/nrf52xxx/pkg.yml
index b91b762133..9a52e7bdf7 100644
--- a/hw/mcu/nordic/nrf52xxx/pkg.yml
+++ b/hw/mcu/nordic/nrf52xxx/pkg.yml
@@ -26,9 +26,9 @@ pkg.keywords:
- nrfx
pkg.deps:
- - hw/mcu/nordic
- - hw/cmsis-core
- - hw/hal
+ - "@apache-mynewt-core/hw/mcu/nordic"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/hw/hal"
# NRF52810 doesn't support SPI/I2C (Use SPIM/I2CM instead)
pkg.ign_files.BSP_NRF52810:
diff --git a/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c b/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
index 2aabb32d64..707e0b6fd1 100644
--- a/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
+++ b/hw/mcu/nordic/nrf52xxx/src/hal_gpio.c
@@ -132,7 +132,8 @@ hal_gpio_init_out(int pin, int val)
} else {
port->OUTCLR = HAL_GPIO_MASK(pin);
}
- port->PIN_CNF[pin_index] = GPIO_PIN_CNF_DIR_Output;
+ port->PIN_CNF[pin_index] = GPIO_PIN_CNF_DIR_Output |
+ (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
port->DIRSET = HAL_GPIO_MASK(pin);
return 0;
diff --git a/hw/mcu/nordic/pkg.yml b/hw/mcu/nordic/pkg.yml
index 111e5408aa..0e9fdc5d8e 100644
--- a/hw/mcu/nordic/pkg.yml
+++ b/hw/mcu/nordic/pkg.yml
@@ -54,5 +54,5 @@ pkg.src_dirs:
pkg.cflags: -std=gnu99 -DNRF52_PAN_28
pkg.deps:
- - hw/hal
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/nxp/MK64F12/pkg.yml b/hw/mcu/nxp/MK64F12/pkg.yml
index d6a1e994e0..39c7ecabeb 100644
--- a/hw/mcu/nxp/MK64F12/pkg.yml
+++ b/hw/mcu/nxp/MK64F12/pkg.yml
@@ -23,6 +23,6 @@ pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
pkg.homepage: "http://mynewt.apache.org/"
pkg.deps:
- - hw/hal
- - hw/cmsis-core
- - hw/mcu/nxp
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/hw/mcu/nxp"
diff --git a/hw/mcu/nxp/mkw41z/include/mcu/mcu.h b/hw/mcu/nxp/mkw41z/include/mcu/mcu.h
index 7451c57e81..65b3cad951 100644
--- a/hw/mcu/nxp/mkw41z/include/mcu/mcu.h
+++ b/hw/mcu/nxp/mkw41z/include/mcu/mcu.h
@@ -24,6 +24,8 @@
extern "C" {
#endif
+#define SVC_IRQ_NUMBER SVCall_IRQn
+
/*
* Defines for naming GPIOs.
*/
diff --git a/hw/mcu/nxp/mkw41z/pkg.yml b/hw/mcu/nxp/mkw41z/pkg.yml
index c523c813c0..d39c69ab58 100644
--- a/hw/mcu/nxp/mkw41z/pkg.yml
+++ b/hw/mcu/nxp/mkw41z/pkg.yml
@@ -26,5 +26,5 @@ pkg.keywords:
- nxp
pkg.deps:
- - hw/cmsis-core
- - hw/hal
+ - "@apache-mynewt-core/hw/cmsis-core"
+ - "@apache-mynewt-core/hw/hal"
diff --git a/hw/mcu/nxp/pkg.yml b/hw/mcu/nxp/pkg.yml
index 302e81eb41..04ced8256e 100644
--- a/hw/mcu/nxp/pkg.yml
+++ b/hw/mcu/nxp/pkg.yml
@@ -40,5 +40,5 @@ pkg.src_dirs:
pkg.cflags: -std=gnu99 -D__assert_func=__assert_func_nxp
pkg.deps:
- - hw/hal
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/sifive/fe310/pkg.yml b/hw/mcu/sifive/fe310/pkg.yml
index 431db7e66b..833fd86abf 100644
--- a/hw/mcu/sifive/fe310/pkg.yml
+++ b/hw/mcu/sifive/fe310/pkg.yml
@@ -26,7 +26,7 @@ pkg.keywords:
- riscv64
pkg.deps:
- - hw/hal
- - hw/mcu/sifive
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/sifive"
pkg.cflags: -march=rv32imac -mabi=ilp32
diff --git a/hw/mcu/sifive/pkg.yml b/hw/mcu/sifive/pkg.yml
index 55953cc92c..5cb48d1df1 100644
--- a/hw/mcu/sifive/pkg.yml
+++ b/hw/mcu/sifive/pkg.yml
@@ -27,7 +27,7 @@ pkg.keywords:
- riscv64
pkg.deps:
- - hw/hal
+ - "@apache-mynewt-core/hw/hal"
pkg.src_dirs:
- "src/ext/freedom-e-sdk_3235929/bsp"
diff --git a/hw/mcu/stm/stm32_common/pkg.yml b/hw/mcu/stm/stm32_common/pkg.yml
index 90575b30f1..ba5c173252 100644
--- a/hw/mcu/stm/stm32_common/pkg.yml
+++ b/hw/mcu/stm/stm32_common/pkg.yml
@@ -25,5 +25,5 @@ pkg.keywords:
- stm32
pkg.deps:
- - hw/hal
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32_common/src/hal_gpio.c b/hw/mcu/stm/stm32_common/src/hal_gpio.c
index cc2e26bfad..20763ec3f9 100644
--- a/hw/mcu/stm/stm32_common/src/hal_gpio.c
+++ b/hw/mcu/stm/stm32_common/src/hal_gpio.c
@@ -753,7 +753,11 @@ hal_gpio_irq_enable(int pin)
mask = GPIO_MASK(pin);
__HAL_DISABLE_INTERRUPTS(ctx);
+#if MYNEWT_VAL(MCU_STM32L4)
+ EXTI->IMR1 |= mask;
+#else
EXTI->IMR |= mask;
+#endif
__HAL_ENABLE_INTERRUPTS(ctx);
}
@@ -771,6 +775,10 @@ hal_gpio_irq_disable(int pin)
mask = GPIO_MASK(pin);
__HAL_DISABLE_INTERRUPTS(ctx);
+#if MYNEWT_VAL(MCU_STM32L4)
+ EXTI->IMR1 |= mask;
+#else
EXTI->IMR &= ~mask;
+#endif
__HAL_ENABLE_INTERRUPTS(ctx);
}
diff --git a/hw/mcu/stm/stm32_common/src/hal_i2c.c b/hw/mcu/stm/stm32_common/src/hal_i2c.c
index 83d4fe50f5..dc1896be3a 100644
--- a/hw/mcu/stm/stm32_common/src/hal_i2c.c
+++ b/hw/mcu/stm/stm32_common/src/hal_i2c.c
@@ -99,7 +99,7 @@ hal_i2c_init(uint8_t i2c_num, void *usercfg)
init = &dev->hid_handle.Init;
dev->hid_handle.Instance = cfg->hic_i2c;
-#if defined(STM32F3) || defined(STM32F7)
+#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
init->Timing = cfg->hic_timingr;
#else
init->ClockSpeed = cfg->hic_speed;
diff --git a/hw/mcu/stm/stm32_common/src/hal_timer.c b/hw/mcu/stm/stm32_common/src/hal_timer.c
index 4446c009e6..741066839b 100644
--- a/hw/mcu/stm/stm32_common/src/hal_timer.c
+++ b/hw/mcu/stm/stm32_common/src/hal_timer.c
@@ -190,7 +190,7 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
#ifdef TIM1
if (regs == TIM1) {
stm32_tmr_reg_irq(TIM1_CC_IRQn, func);
-#if defined(STM32F3)
+#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32L4)
stm32_tmr_reg_irq(TIM1_UP_TIM16_IRQn, func);
#else
stm32_tmr_reg_irq(TIM1_UP_TIM10_IRQn, func);
@@ -219,7 +219,7 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
#ifdef TIM8
if (regs == TIM8) {
stm32_tmr_reg_irq(TIM8_CC_IRQn, func);
-#if defined(STM32F3)
+#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32L4)
stm32_tmr_reg_irq(TIM8_UP_IRQn, func);
#else
stm32_tmr_reg_irq(TIM8_UP_TIM13_IRQn, func);
@@ -229,7 +229,7 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
#endif
#ifdef TIM9
if (regs == TIM9) {
-#if defined(STM32L1)
+#if MYNEWT_VAL(MCU_STM32L1)
stm32_tmr_reg_irq(TIM9_IRQn, func);
#else
stm32_tmr_reg_irq(TIM1_BRK_TIM9_IRQn, func);
@@ -239,7 +239,7 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
#endif
#ifdef TIM10
if (regs == TIM10) {
-#if defined(STM32L1)
+#if MYNEWT_VAL(MCU_STM32L1) || MYNEWT_VAL(MCU_STM32L4)
stm32_tmr_reg_irq(TIM10_IRQn, func);
#else
stm32_tmr_reg_irq(TIM1_UP_TIM10_IRQn, func);
@@ -249,7 +249,7 @@ stm32_hw_setup(int num, TIM_TypeDef *regs)
#endif
#ifdef TIM11
if (regs == TIM11) {
-#if defined(STM32L1)
+#if MYNEWT_VAL(MCU_STM32L1)
stm32_tmr_reg_irq(TIM11_IRQn, func);
#else
stm32_tmr_reg_irq(TIM1_TRG_COM_TIM11_IRQn, func);
diff --git a/hw/mcu/stm/stm32_common/src/hal_uart.c b/hw/mcu/stm/stm32_common/src/hal_uart.c
index 4fd514351f..188ec17a68 100644
--- a/hw/mcu/stm/stm32_common/src/hal_uart.c
+++ b/hw/mcu/stm/stm32_common/src/hal_uart.c
@@ -58,7 +58,7 @@ static struct hal_uart_irq uart_irqs[4];
static struct hal_uart_irq uart_irqs[3];
#endif
-#if defined(STM32F3) || defined(STM32F7)
+#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
# define STATUS(x) ((x)->ISR)
# define RXNE USART_ISR_RXNE
# define TXE USART_ISR_TXE
@@ -140,7 +140,7 @@ uart_irq_handler(int num)
}
regs->CR1 = cr1;
}
-#if defined(STM32F3) || defined(STM32F7)
+#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
/* clear overrun */
if (isr & USART_ISR_ORE) {
regs->ICR |= USART_ICR_ORECF;
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c
index c6e02a8dd9..61335d3204 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v1.c
@@ -29,7 +29,7 @@
#include <mcu/stm32_hal.h>
#include <syscfg/syscfg.h>
-#if !defined(STM32F3) && !defined(STM32F7)
+#if !MYNEWT_VAL(MCU_STM32F3) && !MYNEWT_VAL(MCU_STM32F7) && !MYNEWT_VAL(MCU_STM32L4)
#define I2C_TIMEOUT_BUSY_FLAG 25U /*!< Timeout 25 ms */
#define I2C_NO_OPTION_FRAME 0xFFFF0000U /*!< XferOptions default value */
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c
index 1ad2a10cef..134a64c479 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_i2c_v2.c
@@ -30,7 +30,7 @@
#include <mcu/stm32_hal.h>
#include <syscfg/syscfg.h>
-#if defined(STM32F3) || defined(STM32F7)
+#if MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4)
#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
diff --git a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c
index dfb7d7d7cf..9f54ee2be7 100644
--- a/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c
+++ b/hw/mcu/stm/stm32_common/src/stm32_driver_mod_spi.c
@@ -32,7 +32,7 @@
HAL_StatusTypeDef HAL_SPI_Slave_Queue_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
HAL_StatusTypeDef HAL_SPI_QueueTransmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-#define SPI_HAS_FIFO (defined(STM32F3) || defined(STM32F7))
+#define SPI_HAS_FIFO (MYNEWT_VAL(MCU_STM32F3) || MYNEWT_VAL(MCU_STM32F7) || MYNEWT_VAL(MCU_STM32L4))
#if SPI_HAS_FIFO && (MYNEWT_VAL(SPI_0_SLAVE) || \
MYNEWT_VAL(SPI_1_SLAVE) || \
diff --git a/hw/mcu/stm/stm32f1xx/pkg.yml b/hw/mcu/stm/stm32f1xx/pkg.yml
index d7bb5b8f69..917f7a2ffa 100644
--- a/hw/mcu/stm/stm32f1xx/pkg.yml
+++ b/hw/mcu/stm/stm32f1xx/pkg.yml
@@ -34,6 +34,6 @@ pkg.ign_dirs:
- "Device"
pkg.deps:
- - hw/hal
- - hw/mcu/stm/stm32_common
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32f3xx/pkg.yml b/hw/mcu/stm/stm32f3xx/pkg.yml
index b98c64ed24..6fffc0cb67 100644
--- a/hw/mcu/stm/stm32f3xx/pkg.yml
+++ b/hw/mcu/stm/stm32f3xx/pkg.yml
@@ -34,6 +34,6 @@ pkg.ign_dirs:
- "Device"
pkg.deps:
- - hw/hal
- - hw/mcu/stm/stm32_common
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32f4xx/pkg.yml b/hw/mcu/stm/stm32f4xx/pkg.yml
index d08025b059..c1bfe120bf 100644
--- a/hw/mcu/stm/stm32f4xx/pkg.yml
+++ b/hw/mcu/stm/stm32f4xx/pkg.yml
@@ -40,6 +40,6 @@ pkg.ign_dirs:
- "Device"
pkg.deps:
- - hw/hal
- - hw/mcu/stm/stm32_common
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32f7xx/pkg.yml b/hw/mcu/stm/stm32f7xx/pkg.yml
index e0df78f32a..e5a34ac8bf 100644
--- a/hw/mcu/stm/stm32f7xx/pkg.yml
+++ b/hw/mcu/stm/stm32f7xx/pkg.yml
@@ -34,6 +34,6 @@ pkg.ign_dirs:
- "Device"
pkg.deps:
- - hw/hal
- - hw/mcu/stm/stm32_common
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32l1xx/pkg.yml b/hw/mcu/stm/stm32l1xx/pkg.yml
index 64e822252d..b961036199 100644
--- a/hw/mcu/stm/stm32l1xx/pkg.yml
+++ b/hw/mcu/stm/stm32l1xx/pkg.yml
@@ -34,6 +34,6 @@ pkg.ign_dirs:
- "Device"
pkg.deps:
- - hw/hal
- - hw/mcu/stm/stm32_common
- - hw/cmsis-core
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32l4xx/include/mcu/cmsis_nvic.h b/hw/mcu/stm/stm32l4xx/include/mcu/cmsis_nvic.h
new file mode 100644
index 0000000000..74e1790745
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/include/mcu/cmsis_nvic.h
@@ -0,0 +1,29 @@
+/* mbed Microcontroller Library - cmsis_nvic
+ * Copyright (c) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * CMSIS-style functionality to support dynamic vectors
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#include <stdint.h>
+
+#define NVIC_NUM_VECTORS (16 + 82) // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET 16
+
+#include "stm32l4xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_Relocate(void);
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hw/mcu/stm/stm32l4xx/include/mcu/cortex_m4.h b/hw/mcu/stm/stm32l4xx/include/mcu/cortex_m4.h
new file mode 100644
index 0000000000..22ce8b3426
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/include/mcu/cortex_m4.h
@@ -0,0 +1,35 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_CORTEX_M4_H__
+#define __MCU_CORTEX_M4_H__
+
+#include "stm32l4xx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define OS_TICKS_PER_SEC (1000)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_CORTEX_M4_H__ */
diff --git a/hw/mcu/stm/stm32l4xx/include/mcu/mcu.h b/hw/mcu/stm/stm32l4xx/include/mcu/mcu.h
new file mode 100644
index 0000000000..f46881629e
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/include/mcu/mcu.h
@@ -0,0 +1,46 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_MCU_H_
+#define __MCU_MCU_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SVC_IRQ_NUMBER SVC_IRQn
+
+/*
+ * Defines for naming GPIOs.
+ */
+#define MCU_GPIO_PORTA(pin) ((0 * 16) + (pin))
+#define MCU_GPIO_PORTB(pin) ((1 * 16) + (pin))
+#define MCU_GPIO_PORTC(pin) ((2 * 16) + (pin))
+#define MCU_GPIO_PORTD(pin) ((3 * 16) + (pin))
+#define MCU_GPIO_PORTE(pin) ((4 * 16) + (pin))
+#define MCU_GPIO_PORTF(pin) ((5 * 16) + (pin))
+#define MCU_GPIO_PORTG(pin) ((6 * 16) + (pin))
+#define MCU_GPIO_PORTH(pin) ((7 * 16) + (pin))
+#define MCU_GPIO_PORTI(pin) ((8 * 16) + (pin))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_MCU_H_ */
diff --git a/hw/mcu/stm/stm32l4xx/include/mcu/stm32_hal.h b/hw/mcu/stm/stm32l4xx/include/mcu/stm32_hal.h
new file mode 100644
index 0000000000..e3e7fcaef7
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/include/mcu/stm32_hal.h
@@ -0,0 +1,83 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef STM32_HAL_H
+#define STM32_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <mcu/cortex_m4.h>
+
+#include "stm32l4xx_hal.h"
+#include "stm32l4xx_hal_def.h"
+
+#include "stm32l4xx_mynewt_hal.h"
+
+/* hal_watchdog */
+#include "stm32l4xx_hal_iwdg.h"
+#define STM32_HAL_WATCHDOG_CUSTOM_INIT(x) \
+ do { \
+ (x)->Init.Window = IWDG_WINDOW_DISABLE; \
+ } while (0)
+
+/* hal_system_start */
+#define STM32_HAL_FLASH_REMAP() \
+ do { \
+ SYSCFG->MEMRMP = 0; \
+ __DSB(); \
+ } while (0)
+
+/* hal_spi */
+#include "stm32l4xx.h"
+#include "stm32l4xx_hal_dma.h"
+#include "stm32l4xx_hal_spi.h"
+#include "stm32l4xx_hal_gpio.h"
+#include "stm32l4xx_hal_gpio_ex.h"
+#include "stm32l4xx_hal_rcc.h"
+
+struct stm32_hal_spi_cfg {
+ int ss_pin; /* for slave mode */
+ int sck_pin;
+ int miso_pin;
+ int mosi_pin;
+ int irq_prio;
+};
+
+/* hal_i2c */
+#include "stm32l4xx_hal_i2c.h"
+#include "mcu/stm32l4xx_mynewt_hal.h"
+
+/* hal_uart */
+#include "stm32l4xx_hal_uart.h"
+#include "mcu/stm32l4_bsp.h"
+
+/* hal_timer */
+#include "stm32l4xx_hal_tim.h"
+#include "stm32l4xx_ll_bus.h"
+#include "stm32l4xx_ll_tim.h"
+
+#define STM32_HAL_TIMER_MAX (3)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32_HAL_H */
diff --git a/hw/mcu/stm/stm32l4xx/include/mcu/stm32l4_bsp.h b/hw/mcu/stm/stm32l4xx/include/mcu/stm32l4_bsp.h
new file mode 100644
index 0000000000..6dc9e44843
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/include/mcu/stm32l4_bsp.h
@@ -0,0 +1,58 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_STM32L4_BSP_H_
+#define __MCU_STM32L4_BSP_H_
+
+#include <hal/hal_gpio.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * BSP specific UART settings.
+ */
+struct stm32_uart_cfg {
+ USART_TypeDef *suc_uart; /* UART dev registers */
+ volatile uint32_t *suc_rcc_reg; /* RCC register to modify */
+ uint32_t suc_rcc_dev; /* RCC device ID */
+ int8_t suc_pin_tx; /* pins for IO */
+ int8_t suc_pin_rx;
+ int8_t suc_pin_rts;
+ int8_t suc_pin_cts;
+ uint8_t suc_pin_af; /* AF selection for this */
+ IRQn_Type suc_irqn; /* NVIC IRQn */
+};
+
+/*
+ * Internal API for stm32l4xx mcu specific code.
+ */
+int hal_gpio_init_af(int pin, uint8_t af_type, enum hal_gpio_pull pull, uint8_t
+od);
+
+struct hal_flash;
+extern struct hal_flash stm32l4_flash_dev;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_STM32L4_BSP_H_ */
diff --git a/hw/mcu/stm/stm32l4xx/include/mcu/stm32l4xx_mynewt_hal.h b/hw/mcu/stm/stm32l4xx/include/mcu/stm32l4xx_mynewt_hal.h
new file mode 100644
index 0000000000..292dade41e
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/include/mcu/stm32l4xx_mynewt_hal.h
@@ -0,0 +1,66 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#ifndef __MCU_STM32L4_MYNEWT_HAL_H
+#define __MCU_STM32L4_MYNEWT_HAL_H
+
+#include "stm32l4xx.h"
+#include "stm32l4xx_hal_dma.h"
+#include "stm32l4xx_hal_gpio.h"
+#include "stm32l4xx_hal_i2c.h"
+#include "stm32l4xx_hal_spi.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(x) \
+ do { \
+ x = __get_PRIMASK(); \
+ __disable_irq(); \
+ } while(0);
+
+#define __HAL_ENABLE_INTERRUPTS(x) \
+ do { \
+ if (!x) { \
+ __enable_irq(); \
+ } \
+ } while(0);
+
+
+int hal_gpio_init_stm(int pin, GPIO_InitTypeDef *cfg);
+int hal_gpio_deinit_stm(int pin, GPIO_InitTypeDef *cfg);
+
+struct stm32_hal_i2c_cfg {
+ I2C_TypeDef *hic_i2c;
+ volatile uint32_t *hic_rcc_reg; /* RCC register to modify */
+ uint32_t hic_rcc_dev; /* RCC device ID */
+ uint8_t hic_pin_sda;
+ uint8_t hic_pin_scl;
+ uint8_t hic_pin_af;
+ uint8_t hic_10bit;
+ uint32_t hic_timingr; /* TIMINGR register */
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MCU_STM32L4_MYNEWT_HAL_H */
diff --git a/hw/mcu/stm/stm32l4xx/pkg.yml b/hw/mcu/stm/stm32l4xx/pkg.yml
new file mode 100644
index 0000000000..1a0ec82646
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/pkg.yml
@@ -0,0 +1,39 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/mcu/stm/stm32l4xx
+pkg.description: MCU definition for STM32L4 ARM Cortex-M4 chips.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - stm32
+ - stm32l4
+
+pkg.type: sdk
+
+pkg.ign_files:
+ - ".*template.*"
+
+pkg.ign_dirs:
+ - "Device"
+
+pkg.deps:
+ - "@apache-mynewt-core/hw/hal"
+ - "@apache-mynewt-core/hw/mcu/stm/stm32_common"
+ - "@apache-mynewt-core/hw/cmsis-core"
diff --git a/hw/mcu/stm/stm32l4xx/src/ext/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h b/hw/mcu/stm/stm32l4xx/src/ext/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h
new file mode 100644
index 0000000000..c6a6979724
--- /dev/null
+++ b/hw/mcu/stm/stm32l4xx/src/ext/Drivers/CMSIS/Device/ST/STM32L4xx/Include/stm32l431xx.h
@@ -0,0 +1,15067 @@
+/**
+ ******************************************************************************
+ * @file stm32l431xx.h
+ * @author MCD Application Team
+ * @brief CMSIS STM32L431xx Device Peripheral Access Layer Header File.
+ *
+ * This file contains:
+ * - Data structures and the address mapping for all peripherals
+ * - Peripheral's registers declarations and bits definition
+ * - Macros to access peripheral�s registers hardware
+ *
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/** @addtogroup CMSIS_Device
+ * @{
+ */
+
+/** @addtogroup stm32l431xx
+ * @{
+ */
+
+#ifndef __STM32L431xx_H
+#define __STM32L431xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+
+/** @addtogroup Configuration_section_for_CMSIS
+ * @{
+ */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
+ */
+#define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
+#define __MPU_PRESENT 1 /*!< STM32L4XX provides an MPU */
+#define __NVIC_PRIO_BITS 4 /*!< STM32L4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT 1 /*!< FPU present */
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+ * @{
+ */
+
+/**
+ * @brief STM32L4XX Interrupt Number Definition, according to the selected device
+ * in @ref Library_configuration_section
+ */
+typedef enum
+{
+/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+ NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
+ HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
+/****** STM32 specific Interrupt Numbers **********************************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ PVD_PVM_IRQn = 1, /*!< PVD/PVM1/PVM2/PVM3/PVM4 through EXTI Line detection Interrupts */
+ TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
+ RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
+ FLASH_IRQn = 4, /*!< FLASH global Interrupt */
+ RCC_IRQn = 5, /*!< RCC global Interrupt */
+ EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
+ EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
+ EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
+ EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
+ EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
+ DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
+ DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
+ DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
+ DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
+ DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
+ DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
+ DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
+ ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
+ CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupt */
+ CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupt */
+ CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
+ CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
+ EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
+ TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break interrupt and TIM15 global interrupt */
+ TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update Interrupt and TIM16 global interrupt */
+ TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
+ TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
+ TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
+ I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
+ I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
+ I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
+ I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
+ SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
+ SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
+ USART1_IRQn = 37, /*!< USART1 global Interrupt */
+ USART2_IRQn = 38, /*!< USART2 global Interrupt */
+ USART3_IRQn = 39, /*!< USART3 global Interrupt */
+ EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
+ RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
+ SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
+ SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
+ TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
+ TIM7_IRQn = 55, /*!< TIM7 global interrupt */
+ DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
+ DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
+ DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
+ DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
+ DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
+ COMP_IRQn = 64, /*!< COMP1 and COMP2 Interrupts */
+ LPTIM1_IRQn = 65, /*!< LP TIM1 interrupt */
+ LPTIM2_IRQn = 66, /*!< LP TIM2 interrupt */
+ DMA2_Channel6_IRQn = 68, /*!< DMA2 Channel 6 global interrupt */
+ DMA2_Channel7_IRQn = 69, /*!< DMA2 Channel 7 global interrupt */
+ LPUART1_IRQn = 70, /*!< LP UART1 interrupt */
+ QUADSPI_IRQn = 71, /*!< Quad SPI global interrupt */
+ I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
+ I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
+ SAI1_IRQn = 74, /*!< Serial Audio Interface 1 global interrupt */
+ SWPMI1_IRQn = 76, /*!< Serial Wire Interface 1 global interrupt */
+ TSC_IRQn = 77, /*!< Touch Sense Controller global interrupt */
+ RNG_IRQn = 80, /*!< RNG global interrupt */
+ FPU_IRQn = 81, /*!< FPU global interrupt */
+ CRS_IRQn = 82 /*!< CRS global interrupt */
+} IRQn_Type;
+
+/**
+ * @}
+ */
+
+#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
+#include "system_stm32l4xx.h"
+#include <stdint.h>
+
+/** @addtogroup Peripheral_registers_structures
+ * @{
+ */
+
+/**
+ * @brief Analog to Digital Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< ADC configuration register 1, Address offset: 0x0C */
+ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
+ __IO uint32_t SMPR1; /*!< ADC sampling time register 1, Address offset: 0x14 */
+ __IO uint32_t SMPR2; /*!< ADC sampling time register 2, Address offset: 0x18 */
+ uint32_t RESERVED1; /*!< Reserved, 0x1C */
+ __IO uint32_t TR1; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
+ __IO uint32_t TR2; /*!< ADC analog watchdog 2 threshold register, Address offset: 0x24 */
+ __IO uint32_t TR3; /*!< ADC analog watchdog 3 threshold register, Address offset: 0x28 */
+ uint32_t RESERVED2; /*!< Reserved, 0x2C */
+ __IO uint32_t SQR1; /*!< ADC group regular sequencer register 1, Address offset: 0x30 */
+ __IO uint32_t SQR2; /*!< ADC group regular sequencer register 2, Address offset: 0x34 */
+ __IO uint32_t SQR3; /*!< ADC group regular sequencer register 3, Address offset: 0x38 */
+ __IO uint32_t SQR4; /*!< ADC group regular sequencer register 4, Address offset: 0x3C */
+ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
+ uint32_t RESERVED3; /*!< Reserved, 0x44 */
+ uint32_t RESERVED4; /*!< Reserved, 0x48 */
+ __IO uint32_t JSQR; /*!< ADC group injected sequencer register, Address offset: 0x4C */
+ uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
+ __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
+ __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
+ __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
+ __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
+ uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
+ __IO uint32_t JDR1; /*!< ADC group injected rank 1 data register, Address offset: 0x80 */
+ __IO uint32_t JDR2; /*!< ADC group injected rank 2 data register, Address offset: 0x84 */
+ __IO uint32_t JDR3; /*!< ADC group injected rank 3 data register, Address offset: 0x88 */
+ __IO uint32_t JDR4; /*!< ADC group injected rank 4 data register, Address offset: 0x8C */
+ uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
+ __IO uint32_t AWD2CR; /*!< ADC analog watchdog 1 configuration register, Address offset: 0xA0 */
+ __IO uint32_t AWD3CR; /*!< ADC analog watchdog 3 Configuration Register, Address offset: 0xA4 */
+ uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
+ uint32_t RESERVED9; /*!< Reserved, 0x0AC */
+ __IO uint32_t DIFSEL; /*!< ADC differential mode selection register, Address offset: 0xB0 */
+ __IO uint32_t CALFACT; /*!< ADC calibration factors, Address offset: 0xB4 */
+
+} ADC_TypeDef;
+
+typedef struct
+{
+ uint32_t RESERVED1; /*!< Reserved, Address offset: ADC1 base address + 0x300 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: ADC1 base address + 0x304 */
+ __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: ADC1 base address + 0x30C */
+} ADC_Common_TypeDef;
+
+
+/**
+ * @brief Controller Area Network TxMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
+ __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+ __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+ __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FIFOMailBox
+ */
+
+typedef struct
+{
+ __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
+ __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+ __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+ __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/**
+ * @brief Controller Area Network FilterRegister
+ */
+
+typedef struct
+{
+ __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+ __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/**
+ * @brief Controller Area Network
+ */
+
+typedef struct
+{
+ __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
+ __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
+ __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
+ __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
+ __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
+ __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
+ __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
+ uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
+ CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
+ CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
+ uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
+ __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
+ __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
+ uint32_t RESERVED2; /*!< Reserved, 0x208 */
+ __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
+ uint32_t RESERVED3; /*!< Reserved, 0x210 */
+ __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
+ uint32_t RESERVED4; /*!< Reserved, 0x218 */
+ __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
+ uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
+ CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
+} CAN_TypeDef;
+
+
+/**
+ * @brief Comparator
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */
+} COMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
+} COMP_Common_TypeDef;
+
+/**
+ * @brief CRC calculation unit
+ */
+
+typedef struct
+{
+ __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
+ __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
+ uint8_t RESERVED0; /*!< Reserved, 0x05 */
+ uint16_t RESERVED1; /*!< Reserved, 0x06 */
+ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
+ uint32_t RESERVED2; /*!< Reserved, 0x0C */
+ __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
+ __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
+} CRC_TypeDef;
+
+/**
+ * @brief Clock Recovery System
+ */
+typedef struct
+{
+__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
+__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
+__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
+__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
+} CRS_TypeDef;
+
+/**
+ * @brief Digital to Analog Converter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
+ __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
+ __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+ __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
+ __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
+ __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+ __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
+ __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
+ __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
+ __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
+ __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
+ __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
+ __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
+ __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
+ __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
+ __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
+ __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
+ __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
+ __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
+ __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
+} DAC_TypeDef;
+
+
+/**
+ * @brief Debug MCU
+ */
+
+typedef struct
+{
+ __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
+ __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
+ __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */
+ __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */
+ __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */
+} DBGMCU_TypeDef;
+
+
+/**
+ * @brief DMA Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t CCR; /*!< DMA channel x configuration register */
+ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
+ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
+ __IO uint32_t CMAR; /*!< DMA channel x memory address register */
+} DMA_Channel_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
+ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
+} DMA_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSELR; /*!< DMA channel selection register */
+} DMA_Request_TypeDef;
+
+/* Legacy define */
+#define DMA_request_TypeDef DMA_Request_TypeDef
+
+
+/**
+ * @brief External Interrupt/Event Controller
+ */
+
+typedef struct
+{
+ __IO uint32_t IMR1; /*!< EXTI Interrupt mask register 1, Address offset: 0x00 */
+ __IO uint32_t EMR1; /*!< EXTI Event mask register 1, Address offset: 0x04 */
+ __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register 1, Address offset: 0x08 */
+ __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register 1, Address offset: 0x0C */
+ __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register 1, Address offset: 0x10 */
+ __IO uint32_t PR1; /*!< EXTI Pending register 1, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved, 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, 0x1C */
+ __IO uint32_t IMR2; /*!< EXTI Interrupt mask register 2, Address offset: 0x20 */
+ __IO uint32_t EMR2; /*!< EXTI Event mask register 2, Address offset: 0x24 */
+ __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register 2, Address offset: 0x28 */
+ __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register 2, Address offset: 0x2C */
+ __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register 2, Address offset: 0x30 */
+ __IO uint32_t PR2; /*!< EXTI Pending register 2, Address offset: 0x34 */
+} EXTI_TypeDef;
+
+
+/**
+ * @brief Firewall
+ */
+
+typedef struct
+{
+ __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
+ __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
+ __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
+ __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
+ __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
+ __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
+ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */
+ __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
+} FIREWALL_TypeDef;
+
+
+/**
+ * @brief FLASH Registers
+ */
+
+typedef struct
+{
+ __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
+ __IO uint32_t PDKEYR; /*!< FLASH power down key register, Address offset: 0x04 */
+ __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x08 */
+ __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x10 */
+ __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x14 */
+ __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x18 */
+ __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x1C */
+ __IO uint32_t OPTR; /*!< FLASH option register, Address offset: 0x20 */
+ __IO uint32_t PCROP1SR; /*!< FLASH bank1 PCROP start address register, Address offset: 0x24 */
+ __IO uint32_t PCROP1ER; /*!< FLASH bank1 PCROP end address register, Address offset: 0x28 */
+ __IO uint32_t WRP1AR; /*!< FLASH bank1 WRP area A address register, Address offset: 0x2C */
+ __IO uint32_t WRP1BR; /*!< FLASH bank1 WRP area B address register, Address offset: 0x30 */
+} FLASH_TypeDef;
+
+
+
+/**
+ * @brief General Purpose I/O
+ */
+
+typedef struct
+{
+ __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
+ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
+ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
+ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
+ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
+ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
+ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */
+ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
+ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
+ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */
+
+} GPIO_TypeDef;
+
+
+/**
+ * @brief Inter-integrated Circuit Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
+ __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
+ __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
+ __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
+ __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
+ __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
+ __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
+ __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
+ __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
+ __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
+} I2C_TypeDef;
+
+/**
+ * @brief Independent WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
+ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
+ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
+ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
+ __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
+} IWDG_TypeDef;
+
+/**
+ * @brief LPTIMER
+ */
+typedef struct
+{
+ __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
+ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
+ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
+ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
+ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
+ __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
+ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
+ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
+ __IO uint32_t OR; /*!< LPTIM Option register, Address offset: 0x20 */
+} LPTIM_TypeDef;
+
+/**
+ * @brief Operational Amplifier (OPAMP)
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
+ __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
+ __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
+} OPAMP_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to several OPAMP instances, Address offset: 0x00 */
+} OPAMP_Common_TypeDef;
+
+/**
+ * @brief Power Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x08 */
+ __IO uint32_t CR4; /*!< PWR power control register 4, Address offset: 0x0C */
+ __IO uint32_t SR1; /*!< PWR power status register 1, Address offset: 0x10 */
+ __IO uint32_t SR2; /*!< PWR power status register 2, Address offset: 0x14 */
+ __IO uint32_t SCR; /*!< PWR power status reset register, Address offset: 0x18 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t PUCRA; /*!< Pull_up control register of portA, Address offset: 0x20 */
+ __IO uint32_t PDCRA; /*!< Pull_Down control register of portA, Address offset: 0x24 */
+ __IO uint32_t PUCRB; /*!< Pull_up control register of portB, Address offset: 0x28 */
+ __IO uint32_t PDCRB; /*!< Pull_Down control register of portB, Address offset: 0x2C */
+ __IO uint32_t PUCRC; /*!< Pull_up control register of portC, Address offset: 0x30 */
+ __IO uint32_t PDCRC; /*!< Pull_Down control register of portC, Address offset: 0x34 */
+ __IO uint32_t PUCRD; /*!< Pull_up control register of portD, Address offset: 0x38 */
+ __IO uint32_t PDCRD; /*!< Pull_Down control register of portD, Address offset: 0x3C */
+ __IO uint32_t PUCRE; /*!< Pull_up control register of portE, Address offset: 0x40 */
+ __IO uint32_t PDCRE; /*!< Pull_Down control register of portE, Address offset: 0x44 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x48 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x4C */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x50 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x54 */
+ __IO uint32_t PUCRH; /*!< Pull_up control register of portH, Address offset: 0x58 */
+ __IO uint32_t PDCRH; /*!< Pull_Down control register of portH, Address offset: 0x5C */
+} PWR_TypeDef;
+
+
+/**
+ * @brief QUAD Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
+ __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
+ __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
+ __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
+ __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
+ __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
+ __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
+ __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
+ __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
+ __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
+ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
+} QUADSPI_TypeDef;
+
+
+/**
+ * @brief Reset and Clock Control
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
+ __IO uint32_t ICSCR; /*!< RCC internal clock sources calibration register, Address offset: 0x04 */
+ __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x08 */
+ __IO uint32_t PLLCFGR; /*!< RCC system PLL configuration register, Address offset: 0x0C */
+ __IO uint32_t PLLSAI1CFGR; /*!< RCC PLL SAI1 configuration register, Address offset: 0x10 */
+ uint32_t RESERVED; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t CIER; /*!< RCC clock interrupt enable register, Address offset: 0x18 */
+ __IO uint32_t CIFR; /*!< RCC clock interrupt flag register, Address offset: 0x1C */
+ __IO uint32_t CICR; /*!< RCC clock interrupt clear register, Address offset: 0x20 */
+ uint32_t RESERVED0; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
+ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
+ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x30 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x34 */
+ __IO uint32_t APB1RSTR1; /*!< RCC APB1 peripheral reset register 1, Address offset: 0x38 */
+ __IO uint32_t APB1RSTR2; /*!< RCC APB1 peripheral reset register 2, Address offset: 0x3C */
+ __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x40 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x44 */
+ __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clocks enable register, Address offset: 0x48 */
+ __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clocks enable register, Address offset: 0x4C */
+ __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clocks enable register, Address offset: 0x50 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x54 */
+ __IO uint32_t APB1ENR1; /*!< RCC APB1 peripheral clocks enable register 1, Address offset: 0x58 */
+ __IO uint32_t APB1ENR2; /*!< RCC APB1 peripheral clocks enable register 2, Address offset: 0x5C */
+ __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clocks enable register, Address offset: 0x60 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x64 */
+ __IO uint32_t AHB1SMENR; /*!< RCC AHB1 peripheral clocks enable in sleep and stop modes register, Address offset: 0x68 */
+ __IO uint32_t AHB2SMENR; /*!< RCC AHB2 peripheral clocks enable in sleep and stop modes register, Address offset: 0x6C */
+ __IO uint32_t AHB3SMENR; /*!< RCC AHB3 peripheral clocks enable in sleep and stop modes register, Address offset: 0x70 */
+ uint32_t RESERVED5; /*!< Reserved, Address offset: 0x74 */
+ __IO uint32_t APB1SMENR1; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 1, Address offset: 0x78 */
+ __IO uint32_t APB1SMENR2; /*!< RCC APB1 peripheral clocks enable in sleep mode and stop modes register 2, Address offset: 0x7C */
+ __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clocks enable in sleep mode and stop modes register, Address offset: 0x80 */
+ uint32_t RESERVED6; /*!< Reserved, Address offset: 0x84 */
+ __IO uint32_t CCIPR; /*!< RCC peripherals independent clock configuration register, Address offset: 0x88 */
+ uint32_t RESERVED7; /*!< Reserved, Address offset: 0x8C */
+ __IO uint32_t BDCR; /*!< RCC backup domain control register, Address offset: 0x90 */
+ __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x94 */
+ __IO uint32_t CRRCR; /*!< RCC clock recovery RC register, Address offset: 0x98 */
+} RCC_TypeDef;
+
+/**
+ * @brief Real-Time Clock
+ */
+
+typedef struct
+{
+ __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
+ __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
+ __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
+ __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
+ __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
+ uint32_t reserved; /*!< Reserved */
+ __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
+ __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
+ __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
+ __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
+ __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
+ __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
+ __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
+ __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
+ __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
+ __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
+ __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
+ __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
+ __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
+ __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
+ __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
+ __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
+ __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
+ __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
+ __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
+ __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
+ __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
+ __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
+ __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
+ __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
+ __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
+ __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
+ __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
+ __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
+ __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
+ __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
+ __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
+ __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
+ __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
+ __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
+ __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
+ __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
+ __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
+ __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
+ __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
+ __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
+ __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
+ __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
+ __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
+ __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
+ __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
+} RTC_TypeDef;
+
+
+/**
+ * @brief Serial Audio Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
+} SAI_TypeDef;
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
+ __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
+ __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
+ __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
+ __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
+ __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
+ __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
+ __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
+} SAI_Block_TypeDef;
+
+
+/**
+ * @brief Secure digital input/output Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
+ __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
+ __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
+ __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
+ __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
+ __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
+ __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
+ __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
+ __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
+ __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
+ __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
+ __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
+ __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
+ __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
+ __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
+ __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
+ uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
+ __I uint32_t FIFOCNT; /*!< SDMMC FIFO counter register, Address offset: 0x48 */
+ uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
+ __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
+} SDMMC_TypeDef;
+
+
+/**
+ * @brief Serial Peripheral Interface
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
+ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
+ __IO uint32_t CRCPR; /*!< SPI CRC polynomial register, Address offset: 0x10 */
+ __IO uint32_t RXCRCR; /*!< SPI Rx CRC register, Address offset: 0x14 */
+ __IO uint32_t TXCRCR; /*!< SPI Tx CRC register, Address offset: 0x18 */
+} SPI_TypeDef;
+
+
+/**
+ * @brief Single Wire Protocol Master Interface SPWMI
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
+ __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
+ uint32_t RESERVED1; /*!< Reserved, 0x08 */
+ __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
+ __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
+ __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
+ __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
+ __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
+ __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
+ __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
+} SWPMI_TypeDef;
+
+
+/**
+ * @brief System configuration controller
+ */
+
+typedef struct
+{
+ __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
+ __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */
+ __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+ __IO uint32_t SCSR; /*!< SYSCFG SRAM2 control and status register, Address offset: 0x18 */
+ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x1C */
+ __IO uint32_t SWPR; /*!< SYSCFG SRAM2 write protection register, Address offset: 0x20 */
+ __IO uint32_t SKR; /*!< SYSCFG SRAM2 key register, Address offset: 0x24 */
+} SYSCFG_TypeDef;
+
+
+/**
+ * @brief TIM
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
+ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
+ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
+ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
+ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
+ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
+ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
+ __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
+ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
+ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
+ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
+ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
+ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
+ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
+ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
+ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
+ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
+ __IO uint32_t OR1; /*!< TIM option register 1, Address offset: 0x50 */
+ __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
+ __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
+ __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
+ __IO uint32_t OR2; /*!< TIM option register 2, Address offset: 0x60 */
+ __IO uint32_t OR3; /*!< TIM option register 3, Address offset: 0x64 */
+} TIM_TypeDef;
+
+
+/**
+ * @brief Touch Sensing Controller (TSC)
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
+ __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
+ __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
+ __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
+ __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
+ uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
+ __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
+ uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
+ __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
+ uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
+ __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
+ uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
+ __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
+ __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
+} TSC_TypeDef;
+
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter
+ */
+
+typedef struct
+{
+ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
+ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
+ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
+ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
+ __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
+ uint16_t RESERVED2; /*!< Reserved, 0x12 */
+ __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
+ __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
+ uint16_t RESERVED3; /*!< Reserved, 0x1A */
+ __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
+ __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
+ __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
+ uint16_t RESERVED4; /*!< Reserved, 0x26 */
+ __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
+ uint16_t RESERVED5; /*!< Reserved, 0x2A */
+} USART_TypeDef;
+
+/**
+ * @brief VREFBUF
+ */
+
+typedef struct
+{
+ __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
+ __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
+} VREFBUF_TypeDef;
+
+/**
+ * @brief Window WATCHDOG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
+ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
+ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/**
+ * @brief RNG
+ */
+
+typedef struct
+{
+ __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
+ __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
+ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_memory_map
+ * @{
+ */
+#define FLASH_BASE (0x08000000UL) /*!< FLASH(up to 256 KB) base address */
+#define SRAM1_BASE (0x20000000UL) /*!< SRAM1(up to 48 KB) base address */
+#define SRAM2_BASE (0x10000000UL) /*!< SRAM2(16 KB) base address */
+#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */
+#define QSPI_BASE (0x90000000UL) /*!< QUADSPI memories accessible over AHB base address */
+
+#define QSPI_R_BASE (0xA0001000UL) /*!< QUADSPI control registers base address */
+#define SRAM1_BB_BASE (0x22000000UL) /*!< SRAM1(96 KB) base address in the bit-band region */
+#define PERIPH_BB_BASE (0x42000000UL) /*!< Peripheral base address in the bit-band region */
+
+/* Legacy defines */
+#define SRAM_BASE SRAM1_BASE
+#define SRAM_BB_BASE SRAM1_BB_BASE
+
+#define SRAM1_SIZE_MAX (0x0000C000UL) /*!< maximum SRAM1 size (up to 48 KBytes) */
+#define SRAM2_SIZE (0x00004000UL) /*!< SRAM2 size (16 KBytes) */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE PERIPH_BASE
+#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
+#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
+#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
+
+
+/*!< APB1 peripherals */
+#define TIM2_BASE (APB1PERIPH_BASE + 0x0000UL)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000UL)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400UL)
+#define RTC_BASE (APB1PERIPH_BASE + 0x2800UL)
+#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00UL)
+#define IWDG_BASE (APB1PERIPH_BASE + 0x3000UL)
+#define SPI2_BASE (APB1PERIPH_BASE + 0x3800UL)
+#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00UL)
+#define USART2_BASE (APB1PERIPH_BASE + 0x4400UL)
+#define USART3_BASE (APB1PERIPH_BASE + 0x4800UL)
+#define I2C1_BASE (APB1PERIPH_BASE + 0x5400UL)
+#define I2C2_BASE (APB1PERIPH_BASE + 0x5800UL)
+#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00UL)
+#define CRS_BASE (APB1PERIPH_BASE + 0x6000UL)
+#define CAN1_BASE (APB1PERIPH_BASE + 0x6400UL)
+#define PWR_BASE (APB1PERIPH_BASE + 0x7000UL)
+#define DAC_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define DAC1_BASE (APB1PERIPH_BASE + 0x7400UL)
+#define OPAMP_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define OPAMP1_BASE (APB1PERIPH_BASE + 0x7800UL)
+#define LPTIM1_BASE (APB1PERIPH_BASE + 0x7C00UL)
+#define LPUART1_BASE (APB1PERIPH_BASE + 0x8000UL)
+#define SWPMI1_BASE (APB1PERIPH_BASE + 0x8800UL)
+#define LPTIM2_BASE (APB1PERIPH_BASE + 0x9400UL)
+
+
+/*!< APB2 peripherals */
+#define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000UL)
+#define VREFBUF_BASE (APB2PERIPH_BASE + 0x0030UL)
+#define COMP1_BASE (APB2PERIPH_BASE + 0x0200UL)
+#define COMP2_BASE (APB2PERIPH_BASE + 0x0204UL)
+#define EXTI_BASE (APB2PERIPH_BASE + 0x0400UL)
+#define FIREWALL_BASE (APB2PERIPH_BASE + 0x1C00UL)
+#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2800UL)
+#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00UL)
+#define SPI1_BASE (APB2PERIPH_BASE + 0x3000UL)
+#define USART1_BASE (APB2PERIPH_BASE + 0x3800UL)
+#define TIM15_BASE (APB2PERIPH_BASE + 0x4000UL)
+#define TIM16_BASE (APB2PERIPH_BASE + 0x4400UL)
+#define SAI1_BASE (APB2PERIPH_BASE + 0x5400UL)
+#define SAI1_Block_A_BASE (SAI1_BASE + 0x0004UL)
+#define SAI1_Block_B_BASE (SAI1_BASE + 0x0024UL)
+
+/*!< AHB1 peripherals */
+#define DMA1_BASE (AHB1PERIPH_BASE)
+#define DMA2_BASE (AHB1PERIPH_BASE + 0x0400UL)
+#define RCC_BASE (AHB1PERIPH_BASE + 0x1000UL)
+#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x2000UL)
+#define CRC_BASE (AHB1PERIPH_BASE + 0x3000UL)
+#define TSC_BASE (AHB1PERIPH_BASE + 0x4000UL)
+
+
+#define DMA1_Channel1_BASE (DMA1_BASE + 0x0008UL)
+#define DMA1_Channel2_BASE (DMA1_BASE + 0x001CUL)
+#define DMA1_Channel3_BASE (DMA1_BASE + 0x0030UL)
+#define DMA1_Channel4_BASE (DMA1_BASE + 0x0044UL)
+#define DMA1_Channel5_BASE (DMA1_BASE + 0x0058UL)
+#define DMA1_Channel6_BASE (DMA1_BASE + 0x006CUL)
+#define DMA1_Channel7_BASE (DMA1_BASE + 0x0080UL)
+#define DMA1_CSELR_BASE (DMA1_BASE + 0x00A8UL)
+
+
+#define DMA2_Channel1_BASE (DMA2_BASE + 0x0008UL)
+#define DMA2_Channel2_BASE (DMA2_BASE + 0x001CUL)
+#define DMA2_Channel3_BASE (DMA2_BASE + 0x0030UL)
+#define DMA2_Channel4_BASE (DMA2_BASE + 0x0044UL)
+#define DMA2_Channel5_BASE (DMA2_BASE + 0x0058UL)
+#define DMA2_Channel6_BASE (DMA2_BASE + 0x006CUL)
+#define DMA2_Channel7_BASE (DMA2_BASE + 0x0080UL)
+#define DMA2_CSELR_BASE (DMA2_BASE + 0x00A8UL)
+
+
+/*!< AHB2 peripherals */
+#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000UL)
+#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400UL)
+#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800UL)
+#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00UL)
+#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000UL)
+#define GPIOH_BASE (AHB2PERIPH_BASE + 0x1C00UL)
+
+
+#define ADC1_BASE (AHB2PERIPH_BASE + 0x08040000UL)
+#define ADC1_COMMON_BASE (AHB2PERIPH_BASE + 0x08040300UL)
+
+
+#define RNG_BASE (AHB2PERIPH_BASE + 0x08060800UL)
+
+
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE (0xE0042000UL)
+
+
+#define PACKAGE_BASE (0x1FFF7500UL) /*!< Package data register base address */
+#define UID_BASE (0x1FFF7590UL) /*!< Unique device ID register base address */
+#define FLASHSIZE_BASE (0x1FFF75E0UL) /*!< Flash size data register base address */
+/**
+ * @}
+ */
+
+/** @addtogroup Peripheral_declaration
+ * @{
+ */
+#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
+#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
+#define RTC ((RTC_TypeDef *) RTC_BASE)
+#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
+#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
+#define USART2 ((USART_TypeDef *) USART2_BASE)
+#define USART3 ((USART_TypeDef *) USART3_BASE)
+#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
+#define CRS ((CRS_TypeDef *) CRS_BASE)
+#define CAN ((CAN_TypeDef *) CAN1_BASE)
+#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
+#define PWR ((PWR_TypeDef *) PWR_BASE)
+#define DAC ((DAC_TypeDef *) DAC1_BASE)
+#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
+#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
+#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
+#define OPAMP1_COMMON ((OPAMP_Common_TypeDef *) OPAMP1_BASE)
+#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
+#define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
+#define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
+#define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
+
+#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
+#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
+#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
+#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
+#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
+#define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
+#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
+#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
+#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
+#define USART1 ((USART_TypeDef *) USART1_BASE)
+#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
+#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
+#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
+#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
+#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
+#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
+#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
+#define RCC ((RCC_TypeDef *) RCC_BASE)
+#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
+#define CRC ((CRC_TypeDef *) CRC_BASE)
+#define TSC ((TSC_TypeDef *) TSC_BASE)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
+#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
+#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC1_COMMON_BASE)
+#define RNG ((RNG_TypeDef *) RNG_BASE)
+
+
+#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
+#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
+#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
+#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
+#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
+#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
+#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
+#define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
+
+
+#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
+#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
+#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
+#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
+#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
+#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
+#define DMA2_CSELR ((DMA_Request_TypeDef *) DMA2_CSELR_BASE)
+
+
+
+#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
+
+#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+ * @}
+ */
+
+/** @addtogroup Exported_constants
+ * @{
+ */
+
+/** @addtogroup Peripheral_Registers_Bits_Definition
+ * @{
+ */
+
+/******************************************************************************/
+/* Peripheral Registers_Bits_Definition */
+/******************************************************************************/
+
+/******************************************************************************/
+/* */
+/* Analog to Digital Converter */
+/* */
+/******************************************************************************/
+
+/*
+ * @brief Specific device feature definitions (not present on all devices in the STM32L4 serie)
+ */
+/* Note: No specific macro feature on this device */
+
+/******************** Bit definition for ADC_ISR register *******************/
+#define ADC_ISR_ADRDY_Pos (0U)
+#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
+#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
+#define ADC_ISR_EOSMP_Pos (1U)
+#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
+#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
+#define ADC_ISR_EOC_Pos (2U)
+#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
+#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
+#define ADC_ISR_EOS_Pos (3U)
+#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
+#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
+#define ADC_ISR_OVR_Pos (4U)
+#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
+#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
+#define ADC_ISR_JEOC_Pos (5U)
+#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
+#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */
+#define ADC_ISR_JEOS_Pos (6U)
+#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
+#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */
+#define ADC_ISR_AWD1_Pos (7U)
+#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
+#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
+#define ADC_ISR_AWD2_Pos (8U)
+#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
+#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */
+#define ADC_ISR_AWD3_Pos (9U)
+#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
+#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */
+#define ADC_ISR_JQOVF_Pos (10U)
+#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
+#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */
+
+/******************** Bit definition for ADC_IER register *******************/
+#define ADC_IER_ADRDYIE_Pos (0U)
+#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
+#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
+#define ADC_IER_EOSMPIE_Pos (1U)
+#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
+#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
+#define ADC_IER_EOCIE_Pos (2U)
+#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
+#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
+#define ADC_IER_EOSIE_Pos (3U)
+#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
+#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
+#define ADC_IER_OVRIE_Pos (4U)
+#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
+#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
+#define ADC_IER_JEOCIE_Pos (5U)
+#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
+#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */
+#define ADC_IER_JEOSIE_Pos (6U)
+#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
+#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */
+#define ADC_IER_AWD1IE_Pos (7U)
+#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
+#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
+#define ADC_IER_AWD2IE_Pos (8U)
+#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
+#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */
+#define ADC_IER_AWD3IE_Pos (9U)
+#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
+#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */
+#define ADC_IER_JQOVFIE_Pos (10U)
+#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
+#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */
+
+/* Legacy defines */
+#define ADC_IER_ADRDY (ADC_IER_ADRDYIE)
+#define ADC_IER_EOSMP (ADC_IER_EOSMPIE)
+#define ADC_IER_EOC (ADC_IER_EOCIE)
+#define ADC_IER_EOS (ADC_IER_EOSIE)
+#define ADC_IER_OVR (ADC_IER_OVRIE)
+#define ADC_IER_JEOC (ADC_IER_JEOCIE)
+#define ADC_IER_JEOS (ADC_IER_JEOSIE)
+#define ADC_IER_AWD1 (ADC_IER_AWD1IE)
+#define ADC_IER_AWD2 (ADC_IER_AWD2IE)
+#define ADC_IER_AWD3 (ADC_IER_AWD3IE)
+#define ADC_IER_JQOVF (ADC_IER_JQOVFIE)
+
+/******************** Bit definition for ADC_CR register ********************/
+#define ADC_CR_ADEN_Pos (0U)
+#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
+#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
+#define ADC_CR_ADDIS_Pos (1U)
+#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
+#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
+#define ADC_CR_ADSTART_Pos (2U)
+#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
+#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
+#define ADC_CR_JADSTART_Pos (3U)
+#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
+#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */
+#define ADC_CR_ADSTP_Pos (4U)
+#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
+#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
+#define ADC_CR_JADSTP_Pos (5U)
+#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
+#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */
+#define ADC_CR_ADVREGEN_Pos (28U)
+#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
+#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */
+#define ADC_CR_DEEPPWD_Pos (29U)
+#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
+#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */
+#define ADC_CR_ADCALDIF_Pos (30U)
+#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
+#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */
+#define ADC_CR_ADCAL_Pos (31U)
+#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
+#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
+
+/******************** Bit definition for ADC_CFGR register ******************/
+#define ADC_CFGR_DMAEN_Pos (0U)
+#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */
+#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */
+#define ADC_CFGR_DMACFG_Pos (1U)
+#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */
+#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */
+
+#define ADC_CFGR_RES_Pos (3U)
+#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */
+#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */
+#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
+#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR_ALIGN_Pos (5U)
+#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00000020 */
+#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignement */
+
+#define ADC_CFGR_EXTSEL_Pos (6U)
+#define ADC_CFGR_EXTSEL_Msk (0xFUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003C0 */
+#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */
+#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
+#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
+#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
+#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
+
+#define ADC_CFGR_EXTEN_Pos (10U)
+#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
+#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */
+#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
+#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
+
+#define ADC_CFGR_OVRMOD_Pos (12U)
+#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
+#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */
+#define ADC_CFGR_CONT_Pos (13U)
+#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
+#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */
+#define ADC_CFGR_AUTDLY_Pos (14U)
+#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
+#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */
+
+#define ADC_CFGR_DISCEN_Pos (16U)
+#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
+#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
+
+#define ADC_CFGR_DISCNUM_Pos (17U)
+#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
+#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */
+#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
+#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
+#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
+
+#define ADC_CFGR_JDISCEN_Pos (20U)
+#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
+#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */
+#define ADC_CFGR_JQM_Pos (21U)
+#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
+#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */
+#define ADC_CFGR_AWD1SGL_Pos (22U)
+#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
+#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
+#define ADC_CFGR_AWD1EN_Pos (23U)
+#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
+#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
+#define ADC_CFGR_JAWD1EN_Pos (24U)
+#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
+#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */
+#define ADC_CFGR_JAUTO_Pos (25U)
+#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
+#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */
+
+#define ADC_CFGR_AWD1CH_Pos (26U)
+#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
+#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
+#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
+#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
+#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
+#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
+#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
+
+#define ADC_CFGR_JQDIS_Pos (31U)
+#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
+#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */
+
+/******************** Bit definition for ADC_CFGR2 register *****************/
+#define ADC_CFGR2_ROVSE_Pos (0U)
+#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
+#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */
+#define ADC_CFGR2_JOVSE_Pos (1U)
+#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
+#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */
+
+#define ADC_CFGR2_OVSR_Pos (2U)
+#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */
+#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */
+#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */
+#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */
+#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */
+
+#define ADC_CFGR2_OVSS_Pos (5U)
+#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
+#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */
+#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
+#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
+#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
+#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
+
+#define ADC_CFGR2_TROVS_Pos (9U)
+#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
+#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */
+#define ADC_CFGR2_ROVSM_Pos (10U)
+#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
+#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */
+
+/******************** Bit definition for ADC_SMPR1 register *****************/
+#define ADC_SMPR1_SMP0_Pos (0U)
+#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
+#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */
+#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
+#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
+#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR1_SMP1_Pos (3U)
+#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
+#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */
+#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
+#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
+#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR1_SMP2_Pos (6U)
+#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */
+#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
+#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
+#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR1_SMP3_Pos (9U)
+#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */
+#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
+#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
+#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR1_SMP4_Pos (12U)
+#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
+#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */
+#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
+#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
+#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR1_SMP5_Pos (15U)
+#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
+#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */
+#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
+#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
+#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR1_SMP6_Pos (18U)
+#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */
+#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
+#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
+#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR1_SMP7_Pos (21U)
+#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */
+#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
+#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
+#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR1_SMP8_Pos (24U)
+#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
+#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */
+#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
+#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
+#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
+
+#define ADC_SMPR1_SMP9_Pos (27U)
+#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
+#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */
+#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
+#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
+#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
+
+/******************** Bit definition for ADC_SMPR2 register *****************/
+#define ADC_SMPR2_SMP10_Pos (0U)
+#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
+#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */
+#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
+#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
+#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
+
+#define ADC_SMPR2_SMP11_Pos (3U)
+#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
+#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */
+#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
+#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
+#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
+
+#define ADC_SMPR2_SMP12_Pos (6U)
+#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
+#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */
+#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
+#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
+#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
+
+#define ADC_SMPR2_SMP13_Pos (9U)
+#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
+#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */
+#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
+#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
+#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
+
+#define ADC_SMPR2_SMP14_Pos (12U)
+#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
+#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */
+#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
+#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
+#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
+
+#define ADC_SMPR2_SMP15_Pos (15U)
+#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
+#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */
+#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
+#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
+#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
+
+#define ADC_SMPR2_SMP16_Pos (18U)
+#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
+#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */
+#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
+#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
+#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
+
+#define ADC_SMPR2_SMP17_Pos (21U)
+#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
+#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */
+#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
+#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
+#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
+
+#define ADC_SMPR2_SMP18_Pos (24U)
+#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
+#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */
+#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
+#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
+#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
+
+/******************** Bit definition for ADC_TR1 register *******************/
+#define ADC_TR1_LT1_Pos (0U)
+#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
+#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
+#define ADC_TR1_LT1_0 (0x001UL << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
+#define ADC_TR1_LT1_1 (0x002UL << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
+#define ADC_TR1_LT1_2 (0x004UL << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
+#define ADC_TR1_LT1_3 (0x008UL << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
+#define ADC_TR1_LT1_4 (0x010UL << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
+#define ADC_TR1_LT1_5 (0x020UL << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
+#define ADC_TR1_LT1_6 (0x040UL << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
+#define ADC_TR1_LT1_7 (0x080UL << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
+#define ADC_TR1_LT1_8 (0x100UL << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
+#define ADC_TR1_LT1_9 (0x200UL << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
+#define ADC_TR1_LT1_10 (0x400UL << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
+#define ADC_TR1_LT1_11 (0x800UL << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
+
+#define ADC_TR1_HT1_Pos (16U)
+#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
+#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
+#define ADC_TR1_HT1_0 (0x001UL << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
+#define ADC_TR1_HT1_1 (0x002UL << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
+#define ADC_TR1_HT1_2 (0x004UL << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
+#define ADC_TR1_HT1_3 (0x008UL << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
+#define ADC_TR1_HT1_4 (0x010UL << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
+#define ADC_TR1_HT1_5 (0x020UL << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
+#define ADC_TR1_HT1_6 (0x040UL << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
+#define ADC_TR1_HT1_7 (0x080UL << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
+#define ADC_TR1_HT1_8 (0x100UL << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
+#define ADC_TR1_HT1_9 (0x200UL << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
+#define ADC_TR1_HT1_10 (0x400UL << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
+#define ADC_TR1_HT1_11 (0x800UL << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
+
+/******************** Bit definition for ADC_TR2 register *******************/
+#define ADC_TR2_LT2_Pos (0U)
+#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */
+#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */
+#define ADC_TR2_LT2_0 (0x01UL << ADC_TR2_LT2_Pos) /*!< 0x00000001 */
+#define ADC_TR2_LT2_1 (0x02UL << ADC_TR2_LT2_Pos) /*!< 0x00000002 */
+#define ADC_TR2_LT2_2 (0x04UL << ADC_TR2_LT2_Pos) /*!< 0x00000004 */
+#define ADC_TR2_LT2_3 (0x08UL << ADC_TR2_LT2_Pos) /*!< 0x00000008 */
+#define ADC_TR2_LT2_4 (0x10UL << ADC_TR2_LT2_Pos) /*!< 0x00000010 */
+#define ADC_TR2_LT2_5 (0x20UL << ADC_TR2_LT2_Pos) /*!< 0x00000020 */
+#define ADC_TR2_LT2_6 (0x40UL << ADC_TR2_LT2_Pos) /*!< 0x00000040 */
+#define ADC_TR2_LT2_7 (0x80UL << ADC_TR2_LT2_Pos) /*!< 0x00000080 */
+
+#define ADC_TR2_HT2_Pos (16U)
+#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */
+#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */
+#define ADC_TR2_HT2_0 (0x01UL << ADC_TR2_HT2_Pos) /*!< 0x00010000 */
+#define ADC_TR2_HT2_1 (0x02UL << ADC_TR2_HT2_Pos) /*!< 0x00020000 */
+#define ADC_TR2_HT2_2 (0x04UL << ADC_TR2_HT2_Pos) /*!< 0x00040000 */
+#define ADC_TR2_HT2_3 (0x08UL << ADC_TR2_HT2_Pos) /*!< 0x00080000 */
+#define ADC_TR2_HT2_4 (0x10UL << ADC_TR2_HT2_Pos) /*!< 0x00100000 */
+#define ADC_TR2_HT2_5 (0x20UL << ADC_TR2_HT2_Pos) /*!< 0x00200000 */
+#define ADC_TR2_HT2_6 (0x40UL << ADC_TR2_HT2_Pos) /*!< 0x00400000 */
+#define ADC_TR2_HT2_7 (0x80UL << ADC_TR2_HT2_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_TR3 register *******************/
+#define ADC_TR3_LT3_Pos (0U)
+#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */
+#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */
+#define ADC_TR3_LT3_0 (0x01UL << ADC_TR3_LT3_Pos) /*!< 0x00000001 */
+#define ADC_TR3_LT3_1 (0x02UL << ADC_TR3_LT3_Pos) /*!< 0x00000002 */
+#define ADC_TR3_LT3_2 (0x04UL << ADC_TR3_LT3_Pos) /*!< 0x00000004 */
+#define ADC_TR3_LT3_3 (0x08UL << ADC_TR3_LT3_Pos) /*!< 0x00000008 */
+#define ADC_TR3_LT3_4 (0x10UL << ADC_TR3_LT3_Pos) /*!< 0x00000010 */
+#define ADC_TR3_LT3_5 (0x20UL << ADC_TR3_LT3_Pos) /*!< 0x00000020 */
+#define ADC_TR3_LT3_6 (0x40UL << ADC_TR3_LT3_Pos) /*!< 0x00000040 */
+#define ADC_TR3_LT3_7 (0x80UL << ADC_TR3_LT3_Pos) /*!< 0x00000080 */
+
+#define ADC_TR3_HT3_Pos (16U)
+#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */
+#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */
+#define ADC_TR3_HT3_0 (0x01UL << ADC_TR3_HT3_Pos) /*!< 0x00010000 */
+#define ADC_TR3_HT3_1 (0x02UL << ADC_TR3_HT3_Pos) /*!< 0x00020000 */
+#define ADC_TR3_HT3_2 (0x04UL << ADC_TR3_HT3_Pos) /*!< 0x00040000 */
+#define ADC_TR3_HT3_3 (0x08UL << ADC_TR3_HT3_Pos) /*!< 0x00080000 */
+#define ADC_TR3_HT3_4 (0x10UL << ADC_TR3_HT3_Pos) /*!< 0x00100000 */
+#define ADC_TR3_HT3_5 (0x20UL << ADC_TR3_HT3_Pos) /*!< 0x00200000 */
+#define ADC_TR3_HT3_6 (0x40UL << ADC_TR3_HT3_Pos) /*!< 0x00400000 */
+#define ADC_TR3_HT3_7 (0x80UL << ADC_TR3_HT3_Pos) /*!< 0x00800000 */
+
+/******************** Bit definition for ADC_SQR1 register ******************/
+#define ADC_SQR1_L_Pos (0U)
+#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
+#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */
+#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
+#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
+#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
+#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
+
+#define ADC_SQR1_SQ1_Pos (6U)
+#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
+#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */
+#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
+#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
+#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
+#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
+#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR1_SQ2_Pos (12U)
+#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
+#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */
+#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
+#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
+#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
+#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
+#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR1_SQ3_Pos (18U)
+#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
+#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */
+#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
+#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
+#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
+#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
+#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR1_SQ4_Pos (24U)
+#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
+#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */
+#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
+#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
+#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
+#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
+#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR2 register ******************/
+#define ADC_SQR2_SQ5_Pos (0U)
+#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
+#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */
+#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
+#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
+#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
+#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
+#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR2_SQ6_Pos (6U)
+#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
+#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */
+#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
+#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
+#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
+#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
+#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR2_SQ7_Pos (12U)
+#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
+#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */
+#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
+#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
+#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
+#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
+#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR2_SQ8_Pos (18U)
+#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
+#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */
+#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
+#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
+#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
+#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
+#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR2_SQ9_Pos (24U)
+#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
+#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */
+#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
+#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
+#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
+#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
+#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR3 register ******************/
+#define ADC_SQR3_SQ10_Pos (0U)
+#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
+#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */
+#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
+#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
+#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
+#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
+#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR3_SQ11_Pos (6U)
+#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
+#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */
+#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
+#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
+#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
+#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
+#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
+
+#define ADC_SQR3_SQ12_Pos (12U)
+#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
+#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */
+#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
+#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
+#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
+#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
+#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
+
+#define ADC_SQR3_SQ13_Pos (18U)
+#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
+#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */
+#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
+#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
+#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
+#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
+#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
+
+#define ADC_SQR3_SQ14_Pos (24U)
+#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
+#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */
+#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
+#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
+#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
+#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
+#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
+
+/******************** Bit definition for ADC_SQR4 register ******************/
+#define ADC_SQR4_SQ15_Pos (0U)
+#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
+#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */
+#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
+#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
+#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
+#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
+#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
+
+#define ADC_SQR4_SQ16_Pos (6U)
+#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
+#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */
+#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
+#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
+#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
+#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
+#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
+
+/******************** Bit definition for ADC_DR register ********************/
+#define ADC_DR_RDATA_Pos (0U)
+#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */
+#define ADC_DR_RDATA_0 (0x0001UL << ADC_DR_RDATA_Pos) /*!< 0x00000001 */
+#define ADC_DR_RDATA_1 (0x0002UL << ADC_DR_RDATA_Pos) /*!< 0x00000002 */
+#define ADC_DR_RDATA_2 (0x0004UL << ADC_DR_RDATA_Pos) /*!< 0x00000004 */
+#define ADC_DR_RDATA_3 (0x0008UL << ADC_DR_RDATA_Pos) /*!< 0x00000008 */
+#define ADC_DR_RDATA_4 (0x0010UL << ADC_DR_RDATA_Pos) /*!< 0x00000010 */
+#define ADC_DR_RDATA_5 (0x0020UL << ADC_DR_RDATA_Pos) /*!< 0x00000020 */
+#define ADC_DR_RDATA_6 (0x0040UL << ADC_DR_RDATA_Pos) /*!< 0x00000040 */
+#define ADC_DR_RDATA_7 (0x0080UL << ADC_DR_RDATA_Pos) /*!< 0x00000080 */
+#define ADC_DR_RDATA_8 (0x0100UL << ADC_DR_RDATA_Pos) /*!< 0x00000100 */
+#define ADC_DR_RDATA_9 (0x0200UL << ADC_DR_RDATA_Pos) /*!< 0x00000200 */
+#define ADC_DR_RDATA_10 (0x0400UL << ADC_DR_RDATA_Pos) /*!< 0x00000400 */
+#define ADC_DR_RDATA_11 (0x0800UL << ADC_DR_RDATA_Pos) /*!< 0x00000800 */
+#define ADC_DR_RDATA_12 (0x1000UL << ADC_DR_RDATA_Pos) /*!< 0x00001000 */
+#define ADC_DR_RDATA_13 (0x2000UL << ADC_DR_RDATA_Pos) /*!< 0x00002000 */
+#define ADC_DR_RDATA_14 (0x4000UL << ADC_DR_RDATA_Pos) /*!< 0x00004000 */
+#define ADC_DR_RDATA_15 (0x8000UL << ADC_DR_RDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JSQR register ******************/
+#define ADC_JSQR_JL_Pos (0U)
+#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
+#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */
+#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
+#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
+
+#define ADC_JSQR_JEXTSEL_Pos (2U)
+#define ADC_JSQR_JEXTSEL_Msk (0xFUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000003C */
+#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */
+#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
+#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
+#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
+#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
+
+#define ADC_JSQR_JEXTEN_Pos (6U)
+#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x000000C0 */
+#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */
+#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000040 */
+#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
+
+#define ADC_JSQR_JSQ1_Pos (8U)
+#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001F00 */
+#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */
+#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000100 */
+#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
+#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
+#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
+#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
+
+#define ADC_JSQR_JSQ2_Pos (14U)
+#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */
+#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */
+#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */
+#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
+#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
+#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
+#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
+
+#define ADC_JSQR_JSQ3_Pos (20U)
+#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x01F00000 */
+#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */
+#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00100000 */
+#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
+#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
+#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
+#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
+
+#define ADC_JSQR_JSQ4_Pos (26U)
+#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x7C000000 */
+#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */
+#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x04000000 */
+#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
+#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
+#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
+#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
+
+/******************** Bit definition for ADC_OFR1 register ******************/
+#define ADC_OFR1_OFFSET1_Pos (0U)
+#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */
+#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */
+#define ADC_OFR1_OFFSET1_0 (0x001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
+#define ADC_OFR1_OFFSET1_1 (0x002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
+#define ADC_OFR1_OFFSET1_2 (0x004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
+#define ADC_OFR1_OFFSET1_3 (0x008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
+#define ADC_OFR1_OFFSET1_4 (0x010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
+#define ADC_OFR1_OFFSET1_5 (0x020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
+#define ADC_OFR1_OFFSET1_6 (0x040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
+#define ADC_OFR1_OFFSET1_7 (0x080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
+#define ADC_OFR1_OFFSET1_8 (0x100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
+#define ADC_OFR1_OFFSET1_9 (0x200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
+#define ADC_OFR1_OFFSET1_10 (0x400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
+#define ADC_OFR1_OFFSET1_11 (0x800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR1_OFFSET1_CH_Pos (26U)
+#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */
+#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR1_OFFSET1_EN_Pos (31U)
+#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */
+
+/******************** Bit definition for ADC_OFR2 register ******************/
+#define ADC_OFR2_OFFSET2_Pos (0U)
+#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */
+#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */
+#define ADC_OFR2_OFFSET2_0 (0x001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
+#define ADC_OFR2_OFFSET2_1 (0x002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
+#define ADC_OFR2_OFFSET2_2 (0x004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
+#define ADC_OFR2_OFFSET2_3 (0x008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
+#define ADC_OFR2_OFFSET2_4 (0x010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
+#define ADC_OFR2_OFFSET2_5 (0x020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
+#define ADC_OFR2_OFFSET2_6 (0x040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
+#define ADC_OFR2_OFFSET2_7 (0x080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
+#define ADC_OFR2_OFFSET2_8 (0x100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
+#define ADC_OFR2_OFFSET2_9 (0x200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
+#define ADC_OFR2_OFFSET2_10 (0x400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
+#define ADC_OFR2_OFFSET2_11 (0x800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR2_OFFSET2_CH_Pos (26U)
+#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */
+#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR2_OFFSET2_EN_Pos (31U)
+#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */
+
+/******************** Bit definition for ADC_OFR3 register ******************/
+#define ADC_OFR3_OFFSET3_Pos (0U)
+#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */
+#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */
+#define ADC_OFR3_OFFSET3_0 (0x001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
+#define ADC_OFR3_OFFSET3_1 (0x002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
+#define ADC_OFR3_OFFSET3_2 (0x004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
+#define ADC_OFR3_OFFSET3_3 (0x008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
+#define ADC_OFR3_OFFSET3_4 (0x010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
+#define ADC_OFR3_OFFSET3_5 (0x020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
+#define ADC_OFR3_OFFSET3_6 (0x040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
+#define ADC_OFR3_OFFSET3_7 (0x080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
+#define ADC_OFR3_OFFSET3_8 (0x100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
+#define ADC_OFR3_OFFSET3_9 (0x200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
+#define ADC_OFR3_OFFSET3_10 (0x400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
+#define ADC_OFR3_OFFSET3_11 (0x800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR3_OFFSET3_CH_Pos (26U)
+#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */
+#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR3_OFFSET3_EN_Pos (31U)
+#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */
+
+/******************** Bit definition for ADC_OFR4 register ******************/
+#define ADC_OFR4_OFFSET4_Pos (0U)
+#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */
+#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */
+#define ADC_OFR4_OFFSET4_0 (0x001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
+#define ADC_OFR4_OFFSET4_1 (0x002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
+#define ADC_OFR4_OFFSET4_2 (0x004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
+#define ADC_OFR4_OFFSET4_3 (0x008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
+#define ADC_OFR4_OFFSET4_4 (0x010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
+#define ADC_OFR4_OFFSET4_5 (0x020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
+#define ADC_OFR4_OFFSET4_6 (0x040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
+#define ADC_OFR4_OFFSET4_7 (0x080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
+#define ADC_OFR4_OFFSET4_8 (0x100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
+#define ADC_OFR4_OFFSET4_9 (0x200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
+#define ADC_OFR4_OFFSET4_10 (0x400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
+#define ADC_OFR4_OFFSET4_11 (0x800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
+
+#define ADC_OFR4_OFFSET4_CH_Pos (26U)
+#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
+#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */
+#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
+#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
+#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
+#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
+#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
+
+#define ADC_OFR4_OFFSET4_EN_Pos (31U)
+#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */
+#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */
+
+/******************** Bit definition for ADC_JDR1 register ******************/
+#define ADC_JDR1_JDATA_Pos (0U)
+#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */
+#define ADC_JDR1_JDATA_0 (0x0001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR1_JDATA_1 (0x0002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR1_JDATA_2 (0x0004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR1_JDATA_3 (0x0008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR1_JDATA_4 (0x0010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR1_JDATA_5 (0x0020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR1_JDATA_6 (0x0040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR1_JDATA_7 (0x0080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR1_JDATA_8 (0x0100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR1_JDATA_9 (0x0200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR1_JDATA_10 (0x0400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR1_JDATA_11 (0x0800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR1_JDATA_12 (0x1000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR1_JDATA_13 (0x2000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR1_JDATA_14 (0x4000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR1_JDATA_15 (0x8000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR2 register ******************/
+#define ADC_JDR2_JDATA_Pos (0U)
+#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */
+#define ADC_JDR2_JDATA_0 (0x0001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR2_JDATA_1 (0x0002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR2_JDATA_2 (0x0004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR2_JDATA_3 (0x0008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR2_JDATA_4 (0x0010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR2_JDATA_5 (0x0020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR2_JDATA_6 (0x0040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR2_JDATA_7 (0x0080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR2_JDATA_8 (0x0100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR2_JDATA_9 (0x0200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR2_JDATA_10 (0x0400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR2_JDATA_11 (0x0800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR2_JDATA_12 (0x1000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR2_JDATA_13 (0x2000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR2_JDATA_14 (0x4000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR2_JDATA_15 (0x8000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR3 register ******************/
+#define ADC_JDR3_JDATA_Pos (0U)
+#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */
+#define ADC_JDR3_JDATA_0 (0x0001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR3_JDATA_1 (0x0002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR3_JDATA_2 (0x0004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR3_JDATA_3 (0x0008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR3_JDATA_4 (0x0010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR3_JDATA_5 (0x0020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR3_JDATA_6 (0x0040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR3_JDATA_7 (0x0080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR3_JDATA_8 (0x0100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR3_JDATA_9 (0x0200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR3_JDATA_10 (0x0400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR3_JDATA_11 (0x0800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR3_JDATA_12 (0x1000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR3_JDATA_13 (0x2000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR3_JDATA_14 (0x4000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR3_JDATA_15 (0x8000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_JDR4 register ******************/
+#define ADC_JDR4_JDATA_Pos (0U)
+#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */
+#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */
+#define ADC_JDR4_JDATA_0 (0x0001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
+#define ADC_JDR4_JDATA_1 (0x0002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
+#define ADC_JDR4_JDATA_2 (0x0004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
+#define ADC_JDR4_JDATA_3 (0x0008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
+#define ADC_JDR4_JDATA_4 (0x0010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
+#define ADC_JDR4_JDATA_5 (0x0020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
+#define ADC_JDR4_JDATA_6 (0x0040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
+#define ADC_JDR4_JDATA_7 (0x0080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
+#define ADC_JDR4_JDATA_8 (0x0100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
+#define ADC_JDR4_JDATA_9 (0x0200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
+#define ADC_JDR4_JDATA_10 (0x0400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
+#define ADC_JDR4_JDATA_11 (0x0800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
+#define ADC_JDR4_JDATA_12 (0x1000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
+#define ADC_JDR4_JDATA_13 (0x2000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
+#define ADC_JDR4_JDATA_14 (0x4000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
+#define ADC_JDR4_JDATA_15 (0x8000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
+
+/******************** Bit definition for ADC_AWD2CR register ****************/
+#define ADC_AWD2CR_AWD2CH_Pos (0U)
+#define ADC_AWD2CR_AWD2CH_Msk (0x7FFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */
+#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_AWD3CR register ****************/
+#define ADC_AWD3CR_AWD3CH_Pos (0U)
+#define ADC_AWD3CR_AWD3CH_Msk (0x7FFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */
+#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */
+#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
+#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
+#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
+#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
+#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
+#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
+#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
+#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
+#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
+#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
+#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
+#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
+#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
+#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
+#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
+#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
+#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
+#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
+#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_DIFSEL register ****************/
+#define ADC_DIFSEL_DIFSEL_Pos (0U)
+#define ADC_DIFSEL_DIFSEL_Msk (0x7FFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */
+#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
+#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
+#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
+#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
+#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
+#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
+#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
+#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
+#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
+#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
+#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
+#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
+#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
+#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
+#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
+#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
+#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
+#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
+#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
+#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
+
+/******************** Bit definition for ADC_CALFACT register ***************/
+#define ADC_CALFACT_CALFACT_S_Pos (0U)
+#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */
+#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
+#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
+#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
+#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
+#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
+#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
+#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
+#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
+
+#define ADC_CALFACT_CALFACT_D_Pos (16U)
+#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */
+#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */
+#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
+#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
+#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
+#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
+#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
+#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
+#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
+
+/************************* ADC Common registers *****************************/
+/******************** Bit definition for ADC_CCR register *******************/
+#define ADC_CCR_CKMODE_Pos (16U)
+#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
+#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */
+#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
+#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
+
+#define ADC_CCR_PRESC_Pos (18U)
+#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
+#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */
+#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
+#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
+#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
+#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
+
+#define ADC_CCR_VREFEN_Pos (22U)
+#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
+#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
+#define ADC_CCR_TSEN_Pos (23U)
+#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
+#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
+#define ADC_CCR_VBATEN_Pos (24U)
+#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
+#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
+
+/******************************************************************************/
+/* */
+/* Controller Area Network */
+/* */
+/******************************************************************************/
+/*!<CAN control and status registers */
+/******************* Bit definition for CAN_MCR register ********************/
+#define CAN_MCR_INRQ_Pos (0U)
+#define CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos) /*!< 0x00000001 */
+#define CAN_MCR_INRQ CAN_MCR_INRQ_Msk /*!<Initialization Request */
+#define CAN_MCR_SLEEP_Pos (1U)
+#define CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos) /*!< 0x00000002 */
+#define CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk /*!<Sleep Mode Request */
+#define CAN_MCR_TXFP_Pos (2U)
+#define CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos) /*!< 0x00000004 */
+#define CAN_MCR_TXFP CAN_MCR_TXFP_Msk /*!<Transmit FIFO Priority */
+#define CAN_MCR_RFLM_Pos (3U)
+#define CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos) /*!< 0x00000008 */
+#define CAN_MCR_RFLM CAN_MCR_RFLM_Msk /*!<Receive FIFO Locked Mode */
+#define CAN_MCR_NART_Pos (4U)
+#define CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos) /*!< 0x00000010 */
+#define CAN_MCR_NART CAN_MCR_NART_Msk /*!<No Automatic Retransmission */
+#define CAN_MCR_AWUM_Pos (5U)
+#define CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos) /*!< 0x00000020 */
+#define CAN_MCR_AWUM CAN_MCR_AWUM_Msk /*!<Automatic Wakeup Mode */
+#define CAN_MCR_ABOM_Pos (6U)
+#define CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos) /*!< 0x00000040 */
+#define CAN_MCR_ABOM CAN_MCR_ABOM_Msk /*!<Automatic Bus-Off Management */
+#define CAN_MCR_TTCM_Pos (7U)
+#define CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos) /*!< 0x00000080 */
+#define CAN_MCR_TTCM CAN_MCR_TTCM_Msk /*!<Time Triggered Communication Mode */
+#define CAN_MCR_RESET_Pos (15U)
+#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00008000 */
+#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!<bxCAN software master reset */
+
+/******************* Bit definition for CAN_MSR register ********************/
+#define CAN_MSR_INAK_Pos (0U)
+#define CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos) /*!< 0x00000001 */
+#define CAN_MSR_INAK CAN_MSR_INAK_Msk /*!<Initialization Acknowledge */
+#define CAN_MSR_SLAK_Pos (1U)
+#define CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos) /*!< 0x00000002 */
+#define CAN_MSR_SLAK CAN_MSR_SLAK_Msk /*!<Sleep Acknowledge */
+#define CAN_MSR_ERRI_Pos (2U)
+#define CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos) /*!< 0x00000004 */
+#define CAN_MSR_ERRI CAN_MSR_ERRI_Msk /*!<Error Interrupt */
+#define CAN_MSR_WKUI_Pos (3U)
+#define CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos) /*!< 0x00000008 */
+#define CAN_MSR_WKUI CAN_MSR_WKUI_Msk /*!<Wakeup Interrupt */
+#define CAN_MSR_SLAKI_Pos (4U)
+#define CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos) /*!< 0x00000010 */
+#define CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk /*!<Sleep Acknowledge Interrupt */
+#define CAN_MSR_TXM_Pos (8U)
+#define CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos) /*!< 0x00000100 */
+#define CAN_MSR_TXM CAN_MSR_TXM_Msk /*!<Transmit Mode */
+#define CAN_MSR_RXM_Pos (9U)
+#define CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos) /*!< 0x00000200 */
+#define CAN_MSR_RXM CAN_MSR_RXM_Msk /*!<Receive Mode */
+#define CAN_MSR_SAMP_Pos (10U)
+#define CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos) /*!< 0x00000400 */
+#define CAN_MSR_SAMP CAN_MSR_SAMP_Msk /*!<Last Sample Point */
+#define CAN_MSR_RX_Pos (11U)
+#define CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos) /*!< 0x00000800 */
+#define CAN_MSR_RX CAN_MSR_RX_Msk /*!<CAN Rx Signal */
+
+/******************* Bit definition for CAN_TSR register ********************/
+#define CAN_TSR_RQCP0_Pos (0U)
+#define CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos) /*!< 0x00000001 */
+#define CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk /*!<Request Completed Mailbox0 */
+#define CAN_TSR_TXOK0_Pos (1U)
+#define CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos) /*!< 0x00000002 */
+#define CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk /*!<Transmission OK of Mailbox0 */
+#define CAN_TSR_ALST0_Pos (2U)
+#define CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos) /*!< 0x00000004 */
+#define CAN_TSR_ALST0 CAN_TSR_ALST0_Msk /*!<Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0_Pos (3U)
+#define CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos) /*!< 0x00000008 */
+#define CAN_TSR_TERR0 CAN_TSR_TERR0_Msk /*!<Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0_Pos (7U)
+#define CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos) /*!< 0x00000080 */
+#define CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk /*!<Abort Request for Mailbox0 */
+#define CAN_TSR_RQCP1_Pos (8U)
+#define CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos) /*!< 0x00000100 */
+#define CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk /*!<Request Completed Mailbox1 */
+#define CAN_TSR_TXOK1_Pos (9U)
+#define CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos) /*!< 0x00000200 */
+#define CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk /*!<Transmission OK of Mailbox1 */
+#define CAN_TSR_ALST1_Pos (10U)
+#define CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos) /*!< 0x00000400 */
+#define CAN_TSR_ALST1 CAN_TSR_ALST1_Msk /*!<Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1_Pos (11U)
+#define CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos) /*!< 0x00000800 */
+#define CAN_TSR_TERR1 CAN_TSR_TERR1_Msk /*!<Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1_Pos (15U)
+#define CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos) /*!< 0x00008000 */
+#define CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk /*!<Abort Request for Mailbox 1 */
+#define CAN_TSR_RQCP2_Pos (16U)
+#define CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos) /*!< 0x00010000 */
+#define CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk /*!<Request Completed Mailbox2 */
+#define CAN_TSR_TXOK2_Pos (17U)
+#define CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos) /*!< 0x00020000 */
+#define CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk /*!<Transmission OK of Mailbox 2 */
+#define CAN_TSR_ALST2_Pos (18U)
+#define CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos) /*!< 0x00040000 */
+#define CAN_TSR_ALST2 CAN_TSR_ALST2_Msk /*!<Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2_Pos (19U)
+#define CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos) /*!< 0x00080000 */
+#define CAN_TSR_TERR2 CAN_TSR_TERR2_Msk /*!<Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2_Pos (23U)
+#define CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos) /*!< 0x00800000 */
+#define CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk /*!<Abort Request for Mailbox 2 */
+#define CAN_TSR_CODE_Pos (24U)
+#define CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos) /*!< 0x03000000 */
+#define CAN_TSR_CODE CAN_TSR_CODE_Msk /*!<Mailbox Code */
+
+#define CAN_TSR_TME_Pos (26U)
+#define CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos) /*!< 0x1C000000 */
+#define CAN_TSR_TME CAN_TSR_TME_Msk /*!<TME[2:0] bits */
+#define CAN_TSR_TME0_Pos (26U)
+#define CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos) /*!< 0x04000000 */
+#define CAN_TSR_TME0 CAN_TSR_TME0_Msk /*!<Transmit Mailbox 0 Empty */
+#define CAN_TSR_TME1_Pos (27U)
+#define CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos) /*!< 0x08000000 */
+#define CAN_TSR_TME1 CAN_TSR_TME1_Msk /*!<Transmit Mailbox 1 Empty */
+#define CAN_TSR_TME2_Pos (28U)
+#define CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos) /*!< 0x10000000 */
+#define CAN_TSR_TME2 CAN_TSR_TME2_Msk /*!<Transmit Mailbox 2 Empty */
+
+#define CAN_TSR_LOW_Pos (29U)
+#define CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos) /*!< 0xE0000000 */
+#define CAN_TSR_LOW CAN_TSR_LOW_Msk /*!<LOW[2:0] bits */
+#define CAN_TSR_LOW0_Pos (29U)
+#define CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos) /*!< 0x20000000 */
+#define CAN_TSR_LOW0 CAN_TSR_LOW0_Msk /*!<Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1_Pos (30U)
+#define CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos) /*!< 0x40000000 */
+#define CAN_TSR_LOW1 CAN_TSR_LOW1_Msk /*!<Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2_Pos (31U)
+#define CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos) /*!< 0x80000000 */
+#define CAN_TSR_LOW2 CAN_TSR_LOW2_Msk /*!<Lowest Priority Flag for Mailbox 2 */
+
+/******************* Bit definition for CAN_RF0R register *******************/
+#define CAN_RF0R_FMP0_Pos (0U)
+#define CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos) /*!< 0x00000003 */
+#define CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk /*!<FIFO 0 Message Pending */
+#define CAN_RF0R_FULL0_Pos (3U)
+#define CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos) /*!< 0x00000008 */
+#define CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk /*!<FIFO 0 Full */
+#define CAN_RF0R_FOVR0_Pos (4U)
+#define CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos) /*!< 0x00000010 */
+#define CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk /*!<FIFO 0 Overrun */
+#define CAN_RF0R_RFOM0_Pos (5U)
+#define CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos) /*!< 0x00000020 */
+#define CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk /*!<Release FIFO 0 Output Mailbox */
+
+/******************* Bit definition for CAN_RF1R register *******************/
+#define CAN_RF1R_FMP1_Pos (0U)
+#define CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos) /*!< 0x00000003 */
+#define CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk /*!<FIFO 1 Message Pending */
+#define CAN_RF1R_FULL1_Pos (3U)
+#define CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos) /*!< 0x00000008 */
+#define CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk /*!<FIFO 1 Full */
+#define CAN_RF1R_FOVR1_Pos (4U)
+#define CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos) /*!< 0x00000010 */
+#define CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk /*!<FIFO 1 Overrun */
+#define CAN_RF1R_RFOM1_Pos (5U)
+#define CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos) /*!< 0x00000020 */
+#define CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk /*!<Release FIFO 1 Output Mailbox */
+
+/******************** Bit definition for CAN_IER register *******************/
+#define CAN_IER_TMEIE_Pos (0U)
+#define CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos) /*!< 0x00000001 */
+#define CAN_IER_TMEIE CAN_IER_TMEIE_Msk /*!<Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0_Pos (1U)
+#define CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos) /*!< 0x00000002 */
+#define CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0_Pos (2U)
+#define CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos) /*!< 0x00000004 */
+#define CAN_IER_FFIE0 CAN_IER_FFIE0_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0_Pos (3U)
+#define CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos) /*!< 0x00000008 */
+#define CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1_Pos (4U)
+#define CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos) /*!< 0x00000010 */
+#define CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk /*!<FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1_Pos (5U)
+#define CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos) /*!< 0x00000020 */
+#define CAN_IER_FFIE1 CAN_IER_FFIE1_Msk /*!<FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1_Pos (6U)
+#define CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos) /*!< 0x00000040 */
+#define CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk /*!<FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE_Pos (8U)
+#define CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos) /*!< 0x00000100 */
+#define CAN_IER_EWGIE CAN_IER_EWGIE_Msk /*!<Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE_Pos (9U)
+#define CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos) /*!< 0x00000200 */
+#define CAN_IER_EPVIE CAN_IER_EPVIE_Msk /*!<Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE_Pos (10U)
+#define CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos) /*!< 0x00000400 */
+#define CAN_IER_BOFIE CAN_IER_BOFIE_Msk /*!<Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE_Pos (11U)
+#define CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos) /*!< 0x00000800 */
+#define CAN_IER_LECIE CAN_IER_LECIE_Msk /*!<Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE_Pos (15U)
+#define CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos) /*!< 0x00008000 */
+#define CAN_IER_ERRIE CAN_IER_ERRIE_Msk /*!<Error Interrupt Enable */
+#define CAN_IER_WKUIE_Pos (16U)
+#define CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos) /*!< 0x00010000 */
+#define CAN_IER_WKUIE CAN_IER_WKUIE_Msk /*!<Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE_Pos (17U)
+#define CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos) /*!< 0x00020000 */
+#define CAN_IER_SLKIE CAN_IER_SLKIE_Msk /*!<Sleep Interrupt Enable */
+
+/******************** Bit definition for CAN_ESR register *******************/
+#define CAN_ESR_EWGF_Pos (0U)
+#define CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos) /*!< 0x00000001 */
+#define CAN_ESR_EWGF CAN_ESR_EWGF_Msk /*!<Error Warning Flag */
+#define CAN_ESR_EPVF_Pos (1U)
+#define CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos) /*!< 0x00000002 */
+#define CAN_ESR_EPVF CAN_ESR_EPVF_Msk /*!<Error Passive Flag */
+#define CAN_ESR_BOFF_Pos (2U)
+#define CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos) /*!< 0x00000004 */
+#define CAN_ESR_BOFF CAN_ESR_BOFF_Msk /*!<Bus-Off Flag */
+
+#define CAN_ESR_LEC_Pos (4U)
+#define CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos) /*!< 0x00000070 */
+#define CAN_ESR_LEC CAN_ESR_LEC_Msk /*!<LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos) /*!< 0x00000010 */
+#define CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos) /*!< 0x00000020 */
+#define CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos) /*!< 0x00000040 */
+
+#define CAN_ESR_TEC_Pos (16U)
+#define CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos) /*!< 0x00FF0000 */
+#define CAN_ESR_TEC CAN_ESR_TEC_Msk /*!<Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC_Pos (24U)
+#define CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos) /*!< 0xFF000000 */
+#define CAN_ESR_REC CAN_ESR_REC_Msk /*!<Receive Error Counter */
+
+/******************* Bit definition for CAN_BTR register ********************/
+#define CAN_BTR_BRP_Pos (0U)
+#define CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos) /*!< 0x000003FF */
+#define CAN_BTR_BRP CAN_BTR_BRP_Msk /*!<Baud Rate Prescaler */
+#define CAN_BTR_TS1_Pos (16U)
+#define CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos) /*!< 0x000F0000 */
+#define CAN_BTR_TS1 CAN_BTR_TS1_Msk /*!<Time Segment 1 */
+#define CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos) /*!< 0x00010000 */
+#define CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos) /*!< 0x00020000 */
+#define CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos) /*!< 0x00040000 */
+#define CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos) /*!< 0x00080000 */
+#define CAN_BTR_TS2_Pos (20U)
+#define CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos) /*!< 0x00700000 */
+#define CAN_BTR_TS2 CAN_BTR_TS2_Msk /*!<Time Segment 2 */
+#define CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos) /*!< 0x00100000 */
+#define CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos) /*!< 0x00200000 */
+#define CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos) /*!< 0x00400000 */
+#define CAN_BTR_SJW_Pos (24U)
+#define CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos) /*!< 0x03000000 */
+#define CAN_BTR_SJW CAN_BTR_SJW_Msk /*!<Resynchronization Jump Width */
+#define CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos) /*!< 0x01000000 */
+#define CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos) /*!< 0x02000000 */
+#define CAN_BTR_LBKM_Pos (30U)
+#define CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos) /*!< 0x40000000 */
+#define CAN_BTR_LBKM CAN_BTR_LBKM_Msk /*!<Loop Back Mode (Debug) */
+#define CAN_BTR_SILM_Pos (31U)
+#define CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos) /*!< 0x80000000 */
+#define CAN_BTR_SILM CAN_BTR_SILM_Msk /*!<Silent Mode */
+
+/*!<Mailbox registers */
+/****************** Bit definition for CAN_TI0R register ********************/
+#define CAN_TI0R_TXRQ_Pos (0U)
+#define CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI0R_RTR_Pos (1U)
+#define CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI0R_RTR CAN_TI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI0R_IDE_Pos (2U)
+#define CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI0R_IDE CAN_TI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI0R_EXID_Pos (3U)
+#define CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI0R_EXID CAN_TI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI0R_STID_Pos (21U)
+#define CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI0R_STID CAN_TI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/****************** Bit definition for CAN_TDT0R register *******************/
+#define CAN_TDT0R_DLC_Pos (0U)
+#define CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT0R_TGT_Pos (8U)
+#define CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT0R_TIME_Pos (16U)
+#define CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/****************** Bit definition for CAN_TDL0R register *******************/
+#define CAN_TDL0R_DATA0_Pos (0U)
+#define CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL0R_DATA1_Pos (8U)
+#define CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL0R_DATA2_Pos (16U)
+#define CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL0R_DATA3_Pos (24U)
+#define CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/****************** Bit definition for CAN_TDH0R register *******************/
+#define CAN_TDH0R_DATA4_Pos (0U)
+#define CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH0R_DATA5_Pos (8U)
+#define CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH0R_DATA6_Pos (16U)
+#define CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH0R_DATA7_Pos (24U)
+#define CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI1R register *******************/
+#define CAN_TI1R_TXRQ_Pos (0U)
+#define CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI1R_RTR_Pos (1U)
+#define CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI1R_RTR CAN_TI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI1R_IDE_Pos (2U)
+#define CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI1R_IDE CAN_TI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI1R_EXID_Pos (3U)
+#define CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI1R_EXID CAN_TI1R_EXID_Msk /*!<Extended Identifier */
+#define CAN_TI1R_STID_Pos (21U)
+#define CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI1R_STID CAN_TI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT1R register ******************/
+#define CAN_TDT1R_DLC_Pos (0U)
+#define CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT1R_TGT_Pos (8U)
+#define CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT1R_TIME_Pos (16U)
+#define CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL1R register ******************/
+#define CAN_TDL1R_DATA0_Pos (0U)
+#define CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL1R_DATA1_Pos (8U)
+#define CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL1R_DATA2_Pos (16U)
+#define CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL1R_DATA3_Pos (24U)
+#define CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH1R register ******************/
+#define CAN_TDH1R_DATA4_Pos (0U)
+#define CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH1R_DATA5_Pos (8U)
+#define CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH1R_DATA6_Pos (16U)
+#define CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH1R_DATA7_Pos (24U)
+#define CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_TI2R register *******************/
+#define CAN_TI2R_TXRQ_Pos (0U)
+#define CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos) /*!< 0x00000001 */
+#define CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk /*!<Transmit Mailbox Request */
+#define CAN_TI2R_RTR_Pos (1U)
+#define CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_TI2R_RTR CAN_TI2R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_TI2R_IDE_Pos (2U)
+#define CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_TI2R_IDE CAN_TI2R_IDE_Msk /*!<Identifier Extension */
+#define CAN_TI2R_EXID_Pos (3U)
+#define CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_TI2R_EXID CAN_TI2R_EXID_Msk /*!<Extended identifier */
+#define CAN_TI2R_STID_Pos (21U)
+#define CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_TI2R_STID CAN_TI2R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_TDT2R register ******************/
+#define CAN_TDT2R_DLC_Pos (0U)
+#define CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk /*!<Data Length Code */
+#define CAN_TDT2R_TGT_Pos (8U)
+#define CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos) /*!< 0x00000100 */
+#define CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk /*!<Transmit Global Time */
+#define CAN_TDT2R_TIME_Pos (16U)
+#define CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_TDL2R register ******************/
+#define CAN_TDL2R_DATA0_Pos (0U)
+#define CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_TDL2R_DATA1_Pos (8U)
+#define CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_TDL2R_DATA2_Pos (16U)
+#define CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_TDL2R_DATA3_Pos (24U)
+#define CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_TDH2R register ******************/
+#define CAN_TDH2R_DATA4_Pos (0U)
+#define CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_TDH2R_DATA5_Pos (8U)
+#define CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_TDH2R_DATA6_Pos (16U)
+#define CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_TDH2R_DATA7_Pos (24U)
+#define CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI0R register *******************/
+#define CAN_RI0R_RTR_Pos (1U)
+#define CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI0R_RTR CAN_RI0R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI0R_IDE_Pos (2U)
+#define CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI0R_IDE CAN_RI0R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI0R_EXID_Pos (3U)
+#define CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI0R_EXID CAN_RI0R_EXID_Msk /*!<Extended Identifier */
+#define CAN_RI0R_STID_Pos (21U)
+#define CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI0R_STID CAN_RI0R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT0R register ******************/
+#define CAN_RDT0R_DLC_Pos (0U)
+#define CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT0R_FMI_Pos (8U)
+#define CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT0R_TIME_Pos (16U)
+#define CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL0R register ******************/
+#define CAN_RDL0R_DATA0_Pos (0U)
+#define CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL0R_DATA1_Pos (8U)
+#define CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL0R_DATA2_Pos (16U)
+#define CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL0R_DATA3_Pos (24U)
+#define CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH0R register ******************/
+#define CAN_RDH0R_DATA4_Pos (0U)
+#define CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH0R_DATA5_Pos (8U)
+#define CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH0R_DATA6_Pos (16U)
+#define CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH0R_DATA7_Pos (24U)
+#define CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk /*!<Data byte 7 */
+
+/******************* Bit definition for CAN_RI1R register *******************/
+#define CAN_RI1R_RTR_Pos (1U)
+#define CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos) /*!< 0x00000002 */
+#define CAN_RI1R_RTR CAN_RI1R_RTR_Msk /*!<Remote Transmission Request */
+#define CAN_RI1R_IDE_Pos (2U)
+#define CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos) /*!< 0x00000004 */
+#define CAN_RI1R_IDE CAN_RI1R_IDE_Msk /*!<Identifier Extension */
+#define CAN_RI1R_EXID_Pos (3U)
+#define CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos) /*!< 0x001FFFF8 */
+#define CAN_RI1R_EXID CAN_RI1R_EXID_Msk /*!<Extended identifier */
+#define CAN_RI1R_STID_Pos (21U)
+#define CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos) /*!< 0xFFE00000 */
+#define CAN_RI1R_STID CAN_RI1R_STID_Msk /*!<Standard Identifier or Extended Identifier */
+
+/******************* Bit definition for CAN_RDT1R register ******************/
+#define CAN_RDT1R_DLC_Pos (0U)
+#define CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos) /*!< 0x0000000F */
+#define CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk /*!<Data Length Code */
+#define CAN_RDT1R_FMI_Pos (8U)
+#define CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos) /*!< 0x0000FF00 */
+#define CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk /*!<Filter Match Index */
+#define CAN_RDT1R_TIME_Pos (16U)
+#define CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos) /*!< 0xFFFF0000 */
+#define CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk /*!<Message Time Stamp */
+
+/******************* Bit definition for CAN_RDL1R register ******************/
+#define CAN_RDL1R_DATA0_Pos (0U)
+#define CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos) /*!< 0x000000FF */
+#define CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk /*!<Data byte 0 */
+#define CAN_RDL1R_DATA1_Pos (8U)
+#define CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos) /*!< 0x0000FF00 */
+#define CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk /*!<Data byte 1 */
+#define CAN_RDL1R_DATA2_Pos (16U)
+#define CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos) /*!< 0x00FF0000 */
+#define CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk /*!<Data byte 2 */
+#define CAN_RDL1R_DATA3_Pos (24U)
+#define CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos) /*!< 0xFF000000 */
+#define CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk /*!<Data byte 3 */
+
+/******************* Bit definition for CAN_RDH1R register ******************/
+#define CAN_RDH1R_DATA4_Pos (0U)
+#define CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos) /*!< 0x000000FF */
+#define CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk /*!<Data byte 4 */
+#define CAN_RDH1R_DATA5_Pos (8U)
+#define CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos) /*!< 0x0000FF00 */
+#define CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk /*!<Data byte 5 */
+#define CAN_RDH1R_DATA6_Pos (16U)
+#define CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos) /*!< 0x00FF0000 */
+#define CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk /*!<Data byte 6 */
+#define CAN_RDH1R_DATA7_Pos (24U)
+#define CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos) /*!< 0xFF000000 */
+#define CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk /*!<Data byte 7 */
+
+/*!<CAN filter registers */
+/******************* Bit definition for CAN_FMR register ********************/
+#define CAN_FMR_FINIT_Pos (0U)
+#define CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos) /*!< 0x00000001 */
+#define CAN_FMR_FINIT CAN_FMR_FINIT_Msk /*!<Filter Init Mode */
+
+/******************* Bit definition for CAN_FM1R register *******************/
+#define CAN_FM1R_FBM_Pos (0U)
+#define CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos) /*!< 0x00003FFF */
+#define CAN_FM1R_FBM CAN_FM1R_FBM_Msk /*!<Filter Mode */
+#define CAN_FM1R_FBM0_Pos (0U)
+#define CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos) /*!< 0x00000001 */
+#define CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk /*!<Filter Init Mode bit 0 */
+#define CAN_FM1R_FBM1_Pos (1U)
+#define CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos) /*!< 0x00000002 */
+#define CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk /*!<Filter Init Mode bit 1 */
+#define CAN_FM1R_FBM2_Pos (2U)
+#define CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos) /*!< 0x00000004 */
+#define CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk /*!<Filter Init Mode bit 2 */
+#define CAN_FM1R_FBM3_Pos (3U)
+#define CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos) /*!< 0x00000008 */
+#define CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk /*!<Filter Init Mode bit 3 */
+#define CAN_FM1R_FBM4_Pos (4U)
+#define CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos) /*!< 0x00000010 */
+#define CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk /*!<Filter Init Mode bit 4 */
+#define CAN_FM1R_FBM5_Pos (5U)
+#define CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos) /*!< 0x00000020 */
+#define CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk /*!<Filter Init Mode bit 5 */
+#define CAN_FM1R_FBM6_Pos (6U)
+#define CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos) /*!< 0x00000040 */
+#define CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk /*!<Filter Init Mode bit 6 */
+#define CAN_FM1R_FBM7_Pos (7U)
+#define CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos) /*!< 0x00000080 */
+#define CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk /*!<Filter Init Mode bit 7 */
+#define CAN_FM1R_FBM8_Pos (8U)
+#define CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos) /*!< 0x00000100 */
+#define CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk /*!<Filter Init Mode bit 8 */
+#define CAN_FM1R_FBM9_Pos (9U)
+#define CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos) /*!< 0x00000200 */
+#define CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk /*!<Filter Init Mode bit 9 */
+#define CAN_FM1R_FBM10_Pos (10U)
+#define CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos) /*!< 0x00000400 */
+#define CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk /*!<Filter Init Mode bit 10 */
+#define CAN_FM1R_FBM11_Pos (11U)
+#define CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos) /*!< 0x00000800 */
+#define CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk /*!<Filter Init Mode bit 11 */
+#define CAN_FM1R_FBM12_Pos (12U)
+#define CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos) /*!< 0x00001000 */
+#define CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk /*!<Filter Init Mode bit 12 */
+#define CAN_FM1R_FBM13_Pos (13U)
+#define CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos) /*!< 0x00002000 */
+#define CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk /*!<Filter Init Mode bit 13 */
+
+/******************* Bit definition for CAN_FS1R register *******************/
+#define CAN_FS1R_FSC_Pos (0U)
+#define CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos) /*!< 0x00003FFF */
+#define CAN_FS1R_FSC CAN_FS1R_FSC_Msk /*!<Filter Scale Configuration */
+#define CAN_FS1R_FSC0_Pos (0U)
+#define CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos) /*!< 0x00000001 */
+#define CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk /*!<Filter Scale Configuration bit 0 */
+#define CAN_FS1R_FSC1_Pos (1U)
+#define CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos) /*!< 0x00000002 */
+#define CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk /*!<Filter Scale Configuration bit 1 */
+#define CAN_FS1R_FSC2_Pos (2U)
+#define CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos) /*!< 0x00000004 */
+#define CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk /*!<Filter Scale Configuration bit 2 */
+#define CAN_FS1R_FSC3_Pos (3U)
+#define CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos) /*!< 0x00000008 */
+#define CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk /*!<Filter Scale Configuration bit 3 */
+#define CAN_FS1R_FSC4_Pos (4U)
+#define CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos) /*!< 0x00000010 */
+#define CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk /*!<Filter Scale Configuration bit 4 */
+#define CAN_FS1R_FSC5_Pos (5U)
+#define CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos) /*!< 0x00000020 */
+#define CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk /*!<Filter Scale Configuration bit 5 */
+#define CAN_FS1R_FSC6_Pos (6U)
+#define CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos) /*!< 0x00000040 */
+#define CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk /*!<Filter Scale Configuration bit 6 */
+#define CAN_FS1R_FSC7_Pos (7U)
+#define CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos) /*!< 0x00000080 */
+#define CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk /*!<Filter Scale Configuration bit 7 */
+#define CAN_FS1R_FSC8_Pos (8U)
+#define CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos) /*!< 0x00000100 */
+#define CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk /*!<Filter Scale Configuration bit 8 */
+#define CAN_FS1R_FSC9_Pos (9U)
+#define CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos) /*!< 0x00000200 */
+#define CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk /*!<Filter Scale Configuration bit 9 */
+#define CAN_FS1R_FSC10_Pos (10U)
+#define CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos) /*!< 0x00000400 */
+#define CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk /*!<Filter Scale Configuration bit 10 */
+#define CAN_FS1R_FSC11_Pos (11U)
+#define CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos) /*!< 0x00000800 */
+#define CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk /*!<Filter Scale Configuration bit 11 */
+#define CAN_FS1R_FSC12_Pos (12U)
+#define CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos) /*!< 0x00001000 */
+#define CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk /*!<Filter Scale Configuration bit 12 */
+#define CAN_FS1R_FSC13_Pos (13U)
+#define CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos) /*!< 0x00002000 */
+#define CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk /*!<Filter Scale Configuration bit 13 */
+
+/****************** Bit definition for CAN_FFA1R register *******************/
+#define CAN_FFA1R_FFA_Pos (0U)
+#define CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos) /*!< 0x00003FFF */
+#define CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk /*!<Filter FIFO Assignment */
+#define CAN_FFA1R_FFA0_Pos (0U)
+#define CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos) /*!< 0x00000001 */
+#define CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk /*!<Filter FIFO Assignment for Filter 0 */
+#define CAN_FFA1R_FFA1_Pos (1U)
+#define CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos) /*!< 0x00000002 */
+#define CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk /*!<Filter FIFO Assignment for Filter 1 */
+#define CAN_FFA1R_FFA2_Pos (2U)
+#define CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos) /*!< 0x00000004 */
+#define CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk /*!<Filter FIFO Assignment for Filter 2 */
+#define CAN_FFA1R_FFA3_Pos (3U)
+#define CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos) /*!< 0x00000008 */
+#define CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk /*!<Filter FIFO Assignment for Filter 3 */
+#define CAN_FFA1R_FFA4_Pos (4U)
+#define CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos) /*!< 0x00000010 */
+#define CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk /*!<Filter FIFO Assignment for Filter 4 */
+#define CAN_FFA1R_FFA5_Pos (5U)
+#define CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos) /*!< 0x00000020 */
+#define CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk /*!<Filter FIFO Assignment for Filter 5 */
+#define CAN_FFA1R_FFA6_Pos (6U)
+#define CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos) /*!< 0x00000040 */
+#define CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk /*!<Filter FIFO Assignment for Filter 6 */
+#define CAN_FFA1R_FFA7_Pos (7U)
+#define CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos) /*!< 0x00000080 */
+#define CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk /*!<Filter FIFO Assignment for Filter 7 */
+#define CAN_FFA1R_FFA8_Pos (8U)
+#define CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos) /*!< 0x00000100 */
+#define CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk /*!<Filter FIFO Assignment for Filter 8 */
+#define CAN_FFA1R_FFA9_Pos (9U)
+#define CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos) /*!< 0x00000200 */
+#define CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk /*!<Filter FIFO Assignment for Filter 9 */
+#define CAN_FFA1R_FFA10_Pos (10U)
+#define CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos) /*!< 0x00000400 */
+#define CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk /*!<Filter FIFO Assignment for Filter 10 */
+#define CAN_FFA1R_FFA11_Pos (11U)
+#define CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos) /*!< 0x00000800 */
+#define CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk /*!<Filter FIFO Assignment for Filter 11 */
+#define CAN_FFA1R_FFA12_Pos (12U)
+#define CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos) /*!< 0x00001000 */
+#define CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk /*!<Filter FIFO Assignment for Filter 12 */
+#define CAN_FFA1R_FFA13_Pos (13U)
+#define CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos) /*!< 0x00002000 */
+#define CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk /*!<Filter FIFO Assignment for Filter 13 */
+
+/******************* Bit definition for CAN_FA1R register *******************/
+#define CAN_FA1R_FACT_Pos (0U)
+#define CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos) /*!< 0x00003FFF */
+#define CAN_FA1R_FACT CAN_FA1R_FACT_Msk /*!<Filter Active */
+#define CAN_FA1R_FACT0_Pos (0U)
+#define CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos) /*!< 0x00000001 */
+#define CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk /*!<Filter 0 Active */
+#define CAN_FA1R_FACT1_Pos (1U)
+#define CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos) /*!< 0x00000002 */
+#define CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk /*!<Filter 1 Active */
+#define CAN_FA1R_FACT2_Pos (2U)
+#define CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos) /*!< 0x00000004 */
+#define CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk /*!<Filter 2 Active */
+#define CAN_FA1R_FACT3_Pos (3U)
+#define CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos) /*!< 0x00000008 */
+#define CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk /*!<Filter 3 Active */
+#define CAN_FA1R_FACT4_Pos (4U)
+#define CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos) /*!< 0x00000010 */
+#define CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk /*!<Filter 4 Active */
+#define CAN_FA1R_FACT5_Pos (5U)
+#define CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos) /*!< 0x00000020 */
+#define CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk /*!<Filter 5 Active */
+#define CAN_FA1R_FACT6_Pos (6U)
+#define CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos) /*!< 0x00000040 */
+#define CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk /*!<Filter 6 Active */
+#define CAN_FA1R_FACT7_Pos (7U)
+#define CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos) /*!< 0x00000080 */
+#define CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk /*!<Filter 7 Active */
+#define CAN_FA1R_FACT8_Pos (8U)
+#define CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos) /*!< 0x00000100 */
+#define CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk /*!<Filter 8 Active */
+#define CAN_FA1R_FACT9_Pos (9U)
+#define CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos) /*!< 0x00000200 */
+#define CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk /*!<Filter 9 Active */
+#define CAN_FA1R_FACT10_Pos (10U)
+#define CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos) /*!< 0x00000400 */
+#define CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk /*!<Filter 10 Active */
+#define CAN_FA1R_FACT11_Pos (11U)
+#define CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos) /*!< 0x00000800 */
+#define CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk /*!<Filter 11 Active */
+#define CAN_FA1R_FACT12_Pos (12U)
+#define CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos) /*!< 0x00001000 */
+#define CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk /*!<Filter 12 Active */
+#define CAN_FA1R_FACT13_Pos (13U)
+#define CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos) /*!< 0x00002000 */
+#define CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk /*!<Filter 13 Active */
+
+/******************* Bit definition for CAN_F0R1 register *******************/
+#define CAN_F0R1_FB0_Pos (0U)
+#define CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F0R1_FB0 CAN_F0R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F0R1_FB1_Pos (1U)
+#define CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F0R1_FB1 CAN_F0R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F0R1_FB2_Pos (2U)
+#define CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F0R1_FB2 CAN_F0R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F0R1_FB3_Pos (3U)
+#define CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F0R1_FB3 CAN_F0R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F0R1_FB4_Pos (4U)
+#define CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F0R1_FB4 CAN_F0R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F0R1_FB5_Pos (5U)
+#define CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F0R1_FB5 CAN_F0R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F0R1_FB6_Pos (6U)
+#define CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F0R1_FB6 CAN_F0R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F0R1_FB7_Pos (7U)
+#define CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F0R1_FB7 CAN_F0R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F0R1_FB8_Pos (8U)
+#define CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F0R1_FB8 CAN_F0R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F0R1_FB9_Pos (9U)
+#define CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F0R1_FB9 CAN_F0R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F0R1_FB10_Pos (10U)
+#define CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F0R1_FB10 CAN_F0R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F0R1_FB11_Pos (11U)
+#define CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F0R1_FB11 CAN_F0R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F0R1_FB12_Pos (12U)
+#define CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F0R1_FB12 CAN_F0R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F0R1_FB13_Pos (13U)
+#define CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F0R1_FB13 CAN_F0R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F0R1_FB14_Pos (14U)
+#define CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F0R1_FB14 CAN_F0R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F0R1_FB15_Pos (15U)
+#define CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F0R1_FB15 CAN_F0R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F0R1_FB16_Pos (16U)
+#define CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F0R1_FB16 CAN_F0R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F0R1_FB17_Pos (17U)
+#define CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F0R1_FB17 CAN_F0R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F0R1_FB18_Pos (18U)
+#define CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F0R1_FB18 CAN_F0R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F0R1_FB19_Pos (19U)
+#define CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F0R1_FB19 CAN_F0R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F0R1_FB20_Pos (20U)
+#define CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F0R1_FB20 CAN_F0R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F0R1_FB21_Pos (21U)
+#define CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F0R1_FB21 CAN_F0R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F0R1_FB22_Pos (22U)
+#define CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F0R1_FB22 CAN_F0R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F0R1_FB23_Pos (23U)
+#define CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F0R1_FB23 CAN_F0R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F0R1_FB24_Pos (24U)
+#define CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F0R1_FB24 CAN_F0R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F0R1_FB25_Pos (25U)
+#define CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F0R1_FB25 CAN_F0R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F0R1_FB26_Pos (26U)
+#define CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F0R1_FB26 CAN_F0R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F0R1_FB27_Pos (27U)
+#define CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F0R1_FB27 CAN_F0R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F0R1_FB28_Pos (28U)
+#define CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F0R1_FB28 CAN_F0R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F0R1_FB29_Pos (29U)
+#define CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F0R1_FB29 CAN_F0R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F0R1_FB30_Pos (30U)
+#define CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F0R1_FB30 CAN_F0R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F0R1_FB31_Pos (31U)
+#define CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F0R1_FB31 CAN_F0R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F1R1 register *******************/
+#define CAN_F1R1_FB0_Pos (0U)
+#define CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F1R1_FB0 CAN_F1R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F1R1_FB1_Pos (1U)
+#define CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F1R1_FB1 CAN_F1R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F1R1_FB2_Pos (2U)
+#define CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F1R1_FB2 CAN_F1R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F1R1_FB3_Pos (3U)
+#define CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F1R1_FB3 CAN_F1R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F1R1_FB4_Pos (4U)
+#define CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F1R1_FB4 CAN_F1R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F1R1_FB5_Pos (5U)
+#define CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F1R1_FB5 CAN_F1R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F1R1_FB6_Pos (6U)
+#define CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F1R1_FB6 CAN_F1R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F1R1_FB7_Pos (7U)
+#define CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F1R1_FB7 CAN_F1R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F1R1_FB8_Pos (8U)
+#define CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F1R1_FB8 CAN_F1R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F1R1_FB9_Pos (9U)
+#define CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F1R1_FB9 CAN_F1R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F1R1_FB10_Pos (10U)
+#define CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F1R1_FB10 CAN_F1R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F1R1_FB11_Pos (11U)
+#define CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F1R1_FB11 CAN_F1R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F1R1_FB12_Pos (12U)
+#define CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F1R1_FB12 CAN_F1R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F1R1_FB13_Pos (13U)
+#define CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F1R1_FB13 CAN_F1R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F1R1_FB14_Pos (14U)
+#define CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F1R1_FB14 CAN_F1R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F1R1_FB15_Pos (15U)
+#define CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F1R1_FB15 CAN_F1R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F1R1_FB16_Pos (16U)
+#define CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F1R1_FB16 CAN_F1R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F1R1_FB17_Pos (17U)
+#define CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F1R1_FB17 CAN_F1R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F1R1_FB18_Pos (18U)
+#define CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F1R1_FB18 CAN_F1R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F1R1_FB19_Pos (19U)
+#define CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F1R1_FB19 CAN_F1R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F1R1_FB20_Pos (20U)
+#define CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F1R1_FB20 CAN_F1R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F1R1_FB21_Pos (21U)
+#define CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F1R1_FB21 CAN_F1R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F1R1_FB22_Pos (22U)
+#define CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F1R1_FB22 CAN_F1R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F1R1_FB23_Pos (23U)
+#define CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F1R1_FB23 CAN_F1R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F1R1_FB24_Pos (24U)
+#define CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F1R1_FB24 CAN_F1R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F1R1_FB25_Pos (25U)
+#define CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F1R1_FB25 CAN_F1R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F1R1_FB26_Pos (26U)
+#define CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F1R1_FB26 CAN_F1R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F1R1_FB27_Pos (27U)
+#define CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F1R1_FB27 CAN_F1R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F1R1_FB28_Pos (28U)
+#define CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F1R1_FB28 CAN_F1R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F1R1_FB29_Pos (29U)
+#define CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F1R1_FB29 CAN_F1R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F1R1_FB30_Pos (30U)
+#define CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F1R1_FB30 CAN_F1R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F1R1_FB31_Pos (31U)
+#define CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F1R1_FB31 CAN_F1R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F2R1 register *******************/
+#define CAN_F2R1_FB0_Pos (0U)
+#define CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F2R1_FB0 CAN_F2R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F2R1_FB1_Pos (1U)
+#define CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F2R1_FB1 CAN_F2R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F2R1_FB2_Pos (2U)
+#define CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F2R1_FB2 CAN_F2R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F2R1_FB3_Pos (3U)
+#define CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F2R1_FB3 CAN_F2R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F2R1_FB4_Pos (4U)
+#define CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F2R1_FB4 CAN_F2R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F2R1_FB5_Pos (5U)
+#define CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F2R1_FB5 CAN_F2R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F2R1_FB6_Pos (6U)
+#define CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F2R1_FB6 CAN_F2R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F2R1_FB7_Pos (7U)
+#define CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F2R1_FB7 CAN_F2R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F2R1_FB8_Pos (8U)
+#define CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F2R1_FB8 CAN_F2R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F2R1_FB9_Pos (9U)
+#define CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F2R1_FB9 CAN_F2R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F2R1_FB10_Pos (10U)
+#define CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F2R1_FB10 CAN_F2R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F2R1_FB11_Pos (11U)
+#define CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F2R1_FB11 CAN_F2R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F2R1_FB12_Pos (12U)
+#define CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F2R1_FB12 CAN_F2R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F2R1_FB13_Pos (13U)
+#define CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F2R1_FB13 CAN_F2R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F2R1_FB14_Pos (14U)
+#define CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F2R1_FB14 CAN_F2R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F2R1_FB15_Pos (15U)
+#define CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F2R1_FB15 CAN_F2R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F2R1_FB16_Pos (16U)
+#define CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F2R1_FB16 CAN_F2R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F2R1_FB17_Pos (17U)
+#define CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F2R1_FB17 CAN_F2R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F2R1_FB18_Pos (18U)
+#define CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F2R1_FB18 CAN_F2R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F2R1_FB19_Pos (19U)
+#define CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F2R1_FB19 CAN_F2R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F2R1_FB20_Pos (20U)
+#define CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F2R1_FB20 CAN_F2R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F2R1_FB21_Pos (21U)
+#define CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F2R1_FB21 CAN_F2R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F2R1_FB22_Pos (22U)
+#define CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F2R1_FB22 CAN_F2R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F2R1_FB23_Pos (23U)
+#define CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F2R1_FB23 CAN_F2R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F2R1_FB24_Pos (24U)
+#define CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F2R1_FB24 CAN_F2R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F2R1_FB25_Pos (25U)
+#define CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F2R1_FB25 CAN_F2R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F2R1_FB26_Pos (26U)
+#define CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F2R1_FB26 CAN_F2R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F2R1_FB27_Pos (27U)
+#define CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F2R1_FB27 CAN_F2R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F2R1_FB28_Pos (28U)
+#define CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F2R1_FB28 CAN_F2R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F2R1_FB29_Pos (29U)
+#define CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F2R1_FB29 CAN_F2R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F2R1_FB30_Pos (30U)
+#define CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F2R1_FB30 CAN_F2R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F2R1_FB31_Pos (31U)
+#define CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F2R1_FB31 CAN_F2R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F3R1 register *******************/
+#define CAN_F3R1_FB0_Pos (0U)
+#define CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F3R1_FB0 CAN_F3R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F3R1_FB1_Pos (1U)
+#define CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F3R1_FB1 CAN_F3R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F3R1_FB2_Pos (2U)
+#define CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F3R1_FB2 CAN_F3R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F3R1_FB3_Pos (3U)
+#define CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F3R1_FB3 CAN_F3R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F3R1_FB4_Pos (4U)
+#define CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F3R1_FB4 CAN_F3R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F3R1_FB5_Pos (5U)
+#define CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F3R1_FB5 CAN_F3R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F3R1_FB6_Pos (6U)
+#define CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F3R1_FB6 CAN_F3R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F3R1_FB7_Pos (7U)
+#define CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F3R1_FB7 CAN_F3R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F3R1_FB8_Pos (8U)
+#define CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F3R1_FB8 CAN_F3R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F3R1_FB9_Pos (9U)
+#define CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F3R1_FB9 CAN_F3R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F3R1_FB10_Pos (10U)
+#define CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F3R1_FB10 CAN_F3R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F3R1_FB11_Pos (11U)
+#define CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F3R1_FB11 CAN_F3R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F3R1_FB12_Pos (12U)
+#define CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F3R1_FB12 CAN_F3R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F3R1_FB13_Pos (13U)
+#define CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F3R1_FB13 CAN_F3R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F3R1_FB14_Pos (14U)
+#define CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F3R1_FB14 CAN_F3R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F3R1_FB15_Pos (15U)
+#define CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F3R1_FB15 CAN_F3R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F3R1_FB16_Pos (16U)
+#define CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F3R1_FB16 CAN_F3R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F3R1_FB17_Pos (17U)
+#define CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F3R1_FB17 CAN_F3R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F3R1_FB18_Pos (18U)
+#define CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F3R1_FB18 CAN_F3R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F3R1_FB19_Pos (19U)
+#define CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F3R1_FB19 CAN_F3R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F3R1_FB20_Pos (20U)
+#define CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F3R1_FB20 CAN_F3R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F3R1_FB21_Pos (21U)
+#define CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F3R1_FB21 CAN_F3R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F3R1_FB22_Pos (22U)
+#define CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F3R1_FB22 CAN_F3R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F3R1_FB23_Pos (23U)
+#define CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F3R1_FB23 CAN_F3R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F3R1_FB24_Pos (24U)
+#define CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F3R1_FB24 CAN_F3R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F3R1_FB25_Pos (25U)
+#define CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F3R1_FB25 CAN_F3R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F3R1_FB26_Pos (26U)
+#define CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F3R1_FB26 CAN_F3R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F3R1_FB27_Pos (27U)
+#define CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F3R1_FB27 CAN_F3R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F3R1_FB28_Pos (28U)
+#define CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F3R1_FB28 CAN_F3R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F3R1_FB29_Pos (29U)
+#define CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F3R1_FB29 CAN_F3R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F3R1_FB30_Pos (30U)
+#define CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F3R1_FB30 CAN_F3R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F3R1_FB31_Pos (31U)
+#define CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F3R1_FB31 CAN_F3R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F4R1 register *******************/
+#define CAN_F4R1_FB0_Pos (0U)
+#define CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F4R1_FB0 CAN_F4R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F4R1_FB1_Pos (1U)
+#define CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F4R1_FB1 CAN_F4R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F4R1_FB2_Pos (2U)
+#define CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F4R1_FB2 CAN_F4R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F4R1_FB3_Pos (3U)
+#define CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F4R1_FB3 CAN_F4R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F4R1_FB4_Pos (4U)
+#define CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F4R1_FB4 CAN_F4R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F4R1_FB5_Pos (5U)
+#define CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F4R1_FB5 CAN_F4R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F4R1_FB6_Pos (6U)
+#define CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F4R1_FB6 CAN_F4R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F4R1_FB7_Pos (7U)
+#define CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F4R1_FB7 CAN_F4R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F4R1_FB8_Pos (8U)
+#define CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F4R1_FB8 CAN_F4R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F4R1_FB9_Pos (9U)
+#define CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F4R1_FB9 CAN_F4R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F4R1_FB10_Pos (10U)
+#define CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F4R1_FB10 CAN_F4R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F4R1_FB11_Pos (11U)
+#define CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F4R1_FB11 CAN_F4R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F4R1_FB12_Pos (12U)
+#define CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F4R1_FB12 CAN_F4R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F4R1_FB13_Pos (13U)
+#define CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F4R1_FB13 CAN_F4R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F4R1_FB14_Pos (14U)
+#define CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F4R1_FB14 CAN_F4R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F4R1_FB15_Pos (15U)
+#define CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F4R1_FB15 CAN_F4R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F4R1_FB16_Pos (16U)
+#define CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F4R1_FB16 CAN_F4R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F4R1_FB17_Pos (17U)
+#define CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F4R1_FB17 CAN_F4R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F4R1_FB18_Pos (18U)
+#define CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F4R1_FB18 CAN_F4R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F4R1_FB19_Pos (19U)
+#define CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F4R1_FB19 CAN_F4R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F4R1_FB20_Pos (20U)
+#define CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F4R1_FB20 CAN_F4R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F4R1_FB21_Pos (21U)
+#define CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F4R1_FB21 CAN_F4R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F4R1_FB22_Pos (22U)
+#define CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F4R1_FB22 CAN_F4R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F4R1_FB23_Pos (23U)
+#define CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F4R1_FB23 CAN_F4R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F4R1_FB24_Pos (24U)
+#define CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F4R1_FB24 CAN_F4R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F4R1_FB25_Pos (25U)
+#define CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F4R1_FB25 CAN_F4R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F4R1_FB26_Pos (26U)
+#define CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F4R1_FB26 CAN_F4R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F4R1_FB27_Pos (27U)
+#define CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F4R1_FB27 CAN_F4R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F4R1_FB28_Pos (28U)
+#define CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F4R1_FB28 CAN_F4R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F4R1_FB29_Pos (29U)
+#define CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F4R1_FB29 CAN_F4R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F4R1_FB30_Pos (30U)
+#define CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F4R1_FB30 CAN_F4R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F4R1_FB31_Pos (31U)
+#define CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F4R1_FB31 CAN_F4R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F5R1 register *******************/
+#define CAN_F5R1_FB0_Pos (0U)
+#define CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F5R1_FB0 CAN_F5R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F5R1_FB1_Pos (1U)
+#define CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F5R1_FB1 CAN_F5R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F5R1_FB2_Pos (2U)
+#define CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F5R1_FB2 CAN_F5R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F5R1_FB3_Pos (3U)
+#define CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F5R1_FB3 CAN_F5R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F5R1_FB4_Pos (4U)
+#define CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F5R1_FB4 CAN_F5R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F5R1_FB5_Pos (5U)
+#define CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F5R1_FB5 CAN_F5R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F5R1_FB6_Pos (6U)
+#define CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F5R1_FB6 CAN_F5R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F5R1_FB7_Pos (7U)
+#define CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F5R1_FB7 CAN_F5R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F5R1_FB8_Pos (8U)
+#define CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F5R1_FB8 CAN_F5R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F5R1_FB9_Pos (9U)
+#define CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F5R1_FB9 CAN_F5R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F5R1_FB10_Pos (10U)
+#define CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F5R1_FB10 CAN_F5R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F5R1_FB11_Pos (11U)
+#define CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F5R1_FB11 CAN_F5R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F5R1_FB12_Pos (12U)
+#define CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F5R1_FB12 CAN_F5R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F5R1_FB13_Pos (13U)
+#define CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F5R1_FB13 CAN_F5R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F5R1_FB14_Pos (14U)
+#define CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F5R1_FB14 CAN_F5R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F5R1_FB15_Pos (15U)
+#define CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F5R1_FB15 CAN_F5R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F5R1_FB16_Pos (16U)
+#define CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F5R1_FB16 CAN_F5R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F5R1_FB17_Pos (17U)
+#define CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F5R1_FB17 CAN_F5R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F5R1_FB18_Pos (18U)
+#define CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F5R1_FB18 CAN_F5R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F5R1_FB19_Pos (19U)
+#define CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F5R1_FB19 CAN_F5R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F5R1_FB20_Pos (20U)
+#define CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F5R1_FB20 CAN_F5R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F5R1_FB21_Pos (21U)
+#define CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F5R1_FB21 CAN_F5R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F5R1_FB22_Pos (22U)
+#define CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F5R1_FB22 CAN_F5R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F5R1_FB23_Pos (23U)
+#define CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F5R1_FB23 CAN_F5R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F5R1_FB24_Pos (24U)
+#define CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F5R1_FB24 CAN_F5R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F5R1_FB25_Pos (25U)
+#define CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F5R1_FB25 CAN_F5R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F5R1_FB26_Pos (26U)
+#define CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F5R1_FB26 CAN_F5R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F5R1_FB27_Pos (27U)
+#define CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F5R1_FB27 CAN_F5R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F5R1_FB28_Pos (28U)
+#define CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F5R1_FB28 CAN_F5R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F5R1_FB29_Pos (29U)
+#define CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F5R1_FB29 CAN_F5R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F5R1_FB30_Pos (30U)
+#define CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F5R1_FB30 CAN_F5R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F5R1_FB31_Pos (31U)
+#define CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F5R1_FB31 CAN_F5R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F6R1 register *******************/
+#define CAN_F6R1_FB0_Pos (0U)
+#define CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F6R1_FB0 CAN_F6R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F6R1_FB1_Pos (1U)
+#define CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F6R1_FB1 CAN_F6R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F6R1_FB2_Pos (2U)
+#define CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F6R1_FB2 CAN_F6R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F6R1_FB3_Pos (3U)
+#define CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F6R1_FB3 CAN_F6R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F6R1_FB4_Pos (4U)
+#define CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F6R1_FB4 CAN_F6R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F6R1_FB5_Pos (5U)
+#define CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F6R1_FB5 CAN_F6R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F6R1_FB6_Pos (6U)
+#define CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F6R1_FB6 CAN_F6R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F6R1_FB7_Pos (7U)
+#define CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F6R1_FB7 CAN_F6R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F6R1_FB8_Pos (8U)
+#define CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F6R1_FB8 CAN_F6R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F6R1_FB9_Pos (9U)
+#define CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F6R1_FB9 CAN_F6R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F6R1_FB10_Pos (10U)
+#define CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F6R1_FB10 CAN_F6R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F6R1_FB11_Pos (11U)
+#define CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F6R1_FB11 CAN_F6R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F6R1_FB12_Pos (12U)
+#define CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F6R1_FB12 CAN_F6R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F6R1_FB13_Pos (13U)
+#define CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F6R1_FB13 CAN_F6R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F6R1_FB14_Pos (14U)
+#define CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F6R1_FB14 CAN_F6R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F6R1_FB15_Pos (15U)
+#define CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F6R1_FB15 CAN_F6R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F6R1_FB16_Pos (16U)
+#define CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F6R1_FB16 CAN_F6R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F6R1_FB17_Pos (17U)
+#define CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F6R1_FB17 CAN_F6R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F6R1_FB18_Pos (18U)
+#define CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F6R1_FB18 CAN_F6R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F6R1_FB19_Pos (19U)
+#define CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F6R1_FB19 CAN_F6R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F6R1_FB20_Pos (20U)
+#define CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F6R1_FB20 CAN_F6R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F6R1_FB21_Pos (21U)
+#define CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F6R1_FB21 CAN_F6R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F6R1_FB22_Pos (22U)
+#define CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F6R1_FB22 CAN_F6R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F6R1_FB23_Pos (23U)
+#define CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F6R1_FB23 CAN_F6R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F6R1_FB24_Pos (24U)
+#define CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F6R1_FB24 CAN_F6R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F6R1_FB25_Pos (25U)
+#define CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F6R1_FB25 CAN_F6R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F6R1_FB26_Pos (26U)
+#define CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F6R1_FB26 CAN_F6R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F6R1_FB27_Pos (27U)
+#define CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F6R1_FB27 CAN_F6R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F6R1_FB28_Pos (28U)
+#define CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F6R1_FB28 CAN_F6R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F6R1_FB29_Pos (29U)
+#define CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F6R1_FB29 CAN_F6R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F6R1_FB30_Pos (30U)
+#define CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F6R1_FB30 CAN_F6R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F6R1_FB31_Pos (31U)
+#define CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F6R1_FB31 CAN_F6R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F7R1 register *******************/
+#define CAN_F7R1_FB0_Pos (0U)
+#define CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F7R1_FB0 CAN_F7R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F7R1_FB1_Pos (1U)
+#define CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F7R1_FB1 CAN_F7R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F7R1_FB2_Pos (2U)
+#define CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F7R1_FB2 CAN_F7R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F7R1_FB3_Pos (3U)
+#define CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F7R1_FB3 CAN_F7R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F7R1_FB4_Pos (4U)
+#define CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F7R1_FB4 CAN_F7R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F7R1_FB5_Pos (5U)
+#define CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F7R1_FB5 CAN_F7R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F7R1_FB6_Pos (6U)
+#define CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F7R1_FB6 CAN_F7R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F7R1_FB7_Pos (7U)
+#define CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F7R1_FB7 CAN_F7R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F7R1_FB8_Pos (8U)
+#define CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F7R1_FB8 CAN_F7R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F7R1_FB9_Pos (9U)
+#define CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F7R1_FB9 CAN_F7R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F7R1_FB10_Pos (10U)
+#define CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F7R1_FB10 CAN_F7R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F7R1_FB11_Pos (11U)
+#define CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F7R1_FB11 CAN_F7R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F7R1_FB12_Pos (12U)
+#define CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F7R1_FB12 CAN_F7R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F7R1_FB13_Pos (13U)
+#define CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F7R1_FB13 CAN_F7R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F7R1_FB14_Pos (14U)
+#define CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F7R1_FB14 CAN_F7R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F7R1_FB15_Pos (15U)
+#define CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F7R1_FB15 CAN_F7R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F7R1_FB16_Pos (16U)
+#define CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F7R1_FB16 CAN_F7R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F7R1_FB17_Pos (17U)
+#define CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F7R1_FB17 CAN_F7R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F7R1_FB18_Pos (18U)
+#define CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F7R1_FB18 CAN_F7R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F7R1_FB19_Pos (19U)
+#define CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F7R1_FB19 CAN_F7R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F7R1_FB20_Pos (20U)
+#define CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F7R1_FB20 CAN_F7R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F7R1_FB21_Pos (21U)
+#define CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F7R1_FB21 CAN_F7R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F7R1_FB22_Pos (22U)
+#define CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F7R1_FB22 CAN_F7R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F7R1_FB23_Pos (23U)
+#define CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F7R1_FB23 CAN_F7R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F7R1_FB24_Pos (24U)
+#define CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F7R1_FB24 CAN_F7R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F7R1_FB25_Pos (25U)
+#define CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F7R1_FB25 CAN_F7R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F7R1_FB26_Pos (26U)
+#define CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F7R1_FB26 CAN_F7R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F7R1_FB27_Pos (27U)
+#define CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F7R1_FB27 CAN_F7R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F7R1_FB28_Pos (28U)
+#define CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F7R1_FB28 CAN_F7R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F7R1_FB29_Pos (29U)
+#define CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F7R1_FB29 CAN_F7R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F7R1_FB30_Pos (30U)
+#define CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F7R1_FB30 CAN_F7R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F7R1_FB31_Pos (31U)
+#define CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F7R1_FB31 CAN_F7R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F8R1 register *******************/
+#define CAN_F8R1_FB0_Pos (0U)
+#define CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F8R1_FB0 CAN_F8R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F8R1_FB1_Pos (1U)
+#define CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F8R1_FB1 CAN_F8R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F8R1_FB2_Pos (2U)
+#define CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F8R1_FB2 CAN_F8R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F8R1_FB3_Pos (3U)
+#define CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F8R1_FB3 CAN_F8R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F8R1_FB4_Pos (4U)
+#define CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F8R1_FB4 CAN_F8R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F8R1_FB5_Pos (5U)
+#define CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F8R1_FB5 CAN_F8R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F8R1_FB6_Pos (6U)
+#define CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F8R1_FB6 CAN_F8R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F8R1_FB7_Pos (7U)
+#define CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F8R1_FB7 CAN_F8R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F8R1_FB8_Pos (8U)
+#define CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F8R1_FB8 CAN_F8R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F8R1_FB9_Pos (9U)
+#define CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F8R1_FB9 CAN_F8R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F8R1_FB10_Pos (10U)
+#define CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F8R1_FB10 CAN_F8R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F8R1_FB11_Pos (11U)
+#define CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F8R1_FB11 CAN_F8R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F8R1_FB12_Pos (12U)
+#define CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F8R1_FB12 CAN_F8R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F8R1_FB13_Pos (13U)
+#define CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F8R1_FB13 CAN_F8R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F8R1_FB14_Pos (14U)
+#define CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F8R1_FB14 CAN_F8R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F8R1_FB15_Pos (15U)
+#define CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F8R1_FB15 CAN_F8R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F8R1_FB16_Pos (16U)
+#define CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F8R1_FB16 CAN_F8R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F8R1_FB17_Pos (17U)
+#define CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F8R1_FB17 CAN_F8R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F8R1_FB18_Pos (18U)
+#define CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F8R1_FB18 CAN_F8R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F8R1_FB19_Pos (19U)
+#define CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F8R1_FB19 CAN_F8R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F8R1_FB20_Pos (20U)
+#define CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F8R1_FB20 CAN_F8R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F8R1_FB21_Pos (21U)
+#define CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F8R1_FB21 CAN_F8R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F8R1_FB22_Pos (22U)
+#define CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F8R1_FB22 CAN_F8R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F8R1_FB23_Pos (23U)
+#define CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F8R1_FB23 CAN_F8R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F8R1_FB24_Pos (24U)
+#define CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F8R1_FB24 CAN_F8R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F8R1_FB25_Pos (25U)
+#define CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F8R1_FB25 CAN_F8R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F8R1_FB26_Pos (26U)
+#define CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F8R1_FB26 CAN_F8R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F8R1_FB27_Pos (27U)
+#define CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F8R1_FB27 CAN_F8R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F8R1_FB28_Pos (28U)
+#define CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F8R1_FB28 CAN_F8R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F8R1_FB29_Pos (29U)
+#define CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F8R1_FB29 CAN_F8R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F8R1_FB30_Pos (30U)
+#define CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F8R1_FB30 CAN_F8R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F8R1_FB31_Pos (31U)
+#define CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F8R1_FB31 CAN_F8R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F9R1 register *******************/
+#define CAN_F9R1_FB0_Pos (0U)
+#define CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F9R1_FB0 CAN_F9R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F9R1_FB1_Pos (1U)
+#define CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F9R1_FB1 CAN_F9R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F9R1_FB2_Pos (2U)
+#define CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F9R1_FB2 CAN_F9R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F9R1_FB3_Pos (3U)
+#define CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F9R1_FB3 CAN_F9R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F9R1_FB4_Pos (4U)
+#define CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F9R1_FB4 CAN_F9R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F9R1_FB5_Pos (5U)
+#define CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F9R1_FB5 CAN_F9R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F9R1_FB6_Pos (6U)
+#define CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F9R1_FB6 CAN_F9R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F9R1_FB7_Pos (7U)
+#define CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F9R1_FB7 CAN_F9R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F9R1_FB8_Pos (8U)
+#define CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F9R1_FB8 CAN_F9R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F9R1_FB9_Pos (9U)
+#define CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F9R1_FB9 CAN_F9R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F9R1_FB10_Pos (10U)
+#define CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F9R1_FB10 CAN_F9R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F9R1_FB11_Pos (11U)
+#define CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F9R1_FB11 CAN_F9R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F9R1_FB12_Pos (12U)
+#define CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F9R1_FB12 CAN_F9R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F9R1_FB13_Pos (13U)
+#define CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F9R1_FB13 CAN_F9R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F9R1_FB14_Pos (14U)
+#define CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F9R1_FB14 CAN_F9R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F9R1_FB15_Pos (15U)
+#define CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F9R1_FB15 CAN_F9R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F9R1_FB16_Pos (16U)
+#define CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F9R1_FB16 CAN_F9R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F9R1_FB17_Pos (17U)
+#define CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F9R1_FB17 CAN_F9R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F9R1_FB18_Pos (18U)
+#define CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F9R1_FB18 CAN_F9R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F9R1_FB19_Pos (19U)
+#define CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F9R1_FB19 CAN_F9R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F9R1_FB20_Pos (20U)
+#define CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F9R1_FB20 CAN_F9R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F9R1_FB21_Pos (21U)
+#define CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F9R1_FB21 CAN_F9R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F9R1_FB22_Pos (22U)
+#define CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F9R1_FB22 CAN_F9R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F9R1_FB23_Pos (23U)
+#define CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F9R1_FB23 CAN_F9R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F9R1_FB24_Pos (24U)
+#define CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F9R1_FB24 CAN_F9R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F9R1_FB25_Pos (25U)
+#define CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F9R1_FB25 CAN_F9R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F9R1_FB26_Pos (26U)
+#define CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F9R1_FB26 CAN_F9R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F9R1_FB27_Pos (27U)
+#define CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F9R1_FB27 CAN_F9R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F9R1_FB28_Pos (28U)
+#define CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F9R1_FB28 CAN_F9R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F9R1_FB29_Pos (29U)
+#define CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F9R1_FB29 CAN_F9R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F9R1_FB30_Pos (30U)
+#define CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F9R1_FB30 CAN_F9R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F9R1_FB31_Pos (31U)
+#define CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F9R1_FB31 CAN_F9R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F10R1 register ******************/
+#define CAN_F10R1_FB0_Pos (0U)
+#define CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F10R1_FB0 CAN_F10R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F10R1_FB1_Pos (1U)
+#define CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F10R1_FB1 CAN_F10R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F10R1_FB2_Pos (2U)
+#define CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F10R1_FB2 CAN_F10R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F10R1_FB3_Pos (3U)
+#define CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F10R1_FB3 CAN_F10R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F10R1_FB4_Pos (4U)
+#define CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F10R1_FB4 CAN_F10R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F10R1_FB5_Pos (5U)
+#define CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F10R1_FB5 CAN_F10R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F10R1_FB6_Pos (6U)
+#define CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F10R1_FB6 CAN_F10R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F10R1_FB7_Pos (7U)
+#define CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F10R1_FB7 CAN_F10R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F10R1_FB8_Pos (8U)
+#define CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F10R1_FB8 CAN_F10R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F10R1_FB9_Pos (9U)
+#define CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F10R1_FB9 CAN_F10R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F10R1_FB10_Pos (10U)
+#define CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F10R1_FB10 CAN_F10R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F10R1_FB11_Pos (11U)
+#define CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F10R1_FB11 CAN_F10R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F10R1_FB12_Pos (12U)
+#define CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F10R1_FB12 CAN_F10R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F10R1_FB13_Pos (13U)
+#define CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F10R1_FB13 CAN_F10R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F10R1_FB14_Pos (14U)
+#define CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F10R1_FB14 CAN_F10R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F10R1_FB15_Pos (15U)
+#define CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F10R1_FB15 CAN_F10R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F10R1_FB16_Pos (16U)
+#define CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F10R1_FB16 CAN_F10R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F10R1_FB17_Pos (17U)
+#define CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F10R1_FB17 CAN_F10R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F10R1_FB18_Pos (18U)
+#define CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F10R1_FB18 CAN_F10R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F10R1_FB19_Pos (19U)
+#define CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F10R1_FB19 CAN_F10R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F10R1_FB20_Pos (20U)
+#define CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F10R1_FB20 CAN_F10R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F10R1_FB21_Pos (21U)
+#define CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F10R1_FB21 CAN_F10R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F10R1_FB22_Pos (22U)
+#define CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F10R1_FB22 CAN_F10R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F10R1_FB23_Pos (23U)
+#define CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F10R1_FB23 CAN_F10R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F10R1_FB24_Pos (24U)
+#define CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F10R1_FB24 CAN_F10R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F10R1_FB25_Pos (25U)
+#define CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F10R1_FB25 CAN_F10R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F10R1_FB26_Pos (26U)
+#define CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F10R1_FB26 CAN_F10R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F10R1_FB27_Pos (27U)
+#define CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F10R1_FB27 CAN_F10R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F10R1_FB28_Pos (28U)
+#define CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F10R1_FB28 CAN_F10R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F10R1_FB29_Pos (29U)
+#define CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F10R1_FB29 CAN_F10R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F10R1_FB30_Pos (30U)
+#define CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F10R1_FB30 CAN_F10R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F10R1_FB31_Pos (31U)
+#define CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F10R1_FB31 CAN_F10R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F11R1 register ******************/
+#define CAN_F11R1_FB0_Pos (0U)
+#define CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F11R1_FB0 CAN_F11R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F11R1_FB1_Pos (1U)
+#define CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F11R1_FB1 CAN_F11R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F11R1_FB2_Pos (2U)
+#define CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F11R1_FB2 CAN_F11R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F11R1_FB3_Pos (3U)
+#define CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F11R1_FB3 CAN_F11R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F11R1_FB4_Pos (4U)
+#define CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F11R1_FB4 CAN_F11R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F11R1_FB5_Pos (5U)
+#define CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F11R1_FB5 CAN_F11R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F11R1_FB6_Pos (6U)
+#define CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F11R1_FB6 CAN_F11R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F11R1_FB7_Pos (7U)
+#define CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F11R1_FB7 CAN_F11R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F11R1_FB8_Pos (8U)
+#define CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F11R1_FB8 CAN_F11R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F11R1_FB9_Pos (9U)
+#define CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F11R1_FB9 CAN_F11R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F11R1_FB10_Pos (10U)
+#define CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F11R1_FB10 CAN_F11R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F11R1_FB11_Pos (11U)
+#define CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F11R1_FB11 CAN_F11R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F11R1_FB12_Pos (12U)
+#define CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F11R1_FB12 CAN_F11R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F11R1_FB13_Pos (13U)
+#define CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F11R1_FB13 CAN_F11R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F11R1_FB14_Pos (14U)
+#define CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F11R1_FB14 CAN_F11R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F11R1_FB15_Pos (15U)
+#define CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F11R1_FB15 CAN_F11R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F11R1_FB16_Pos (16U)
+#define CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F11R1_FB16 CAN_F11R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F11R1_FB17_Pos (17U)
+#define CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F11R1_FB17 CAN_F11R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F11R1_FB18_Pos (18U)
+#define CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F11R1_FB18 CAN_F11R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F11R1_FB19_Pos (19U)
+#define CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F11R1_FB19 CAN_F11R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F11R1_FB20_Pos (20U)
+#define CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F11R1_FB20 CAN_F11R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F11R1_FB21_Pos (21U)
+#define CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F11R1_FB21 CAN_F11R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F11R1_FB22_Pos (22U)
+#define CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F11R1_FB22 CAN_F11R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F11R1_FB23_Pos (23U)
+#define CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F11R1_FB23 CAN_F11R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F11R1_FB24_Pos (24U)
+#define CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F11R1_FB24 CAN_F11R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F11R1_FB25_Pos (25U)
+#define CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F11R1_FB25 CAN_F11R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F11R1_FB26_Pos (26U)
+#define CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F11R1_FB26 CAN_F11R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F11R1_FB27_Pos (27U)
+#define CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F11R1_FB27 CAN_F11R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F11R1_FB28_Pos (28U)
+#define CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F11R1_FB28 CAN_F11R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F11R1_FB29_Pos (29U)
+#define CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F11R1_FB29 CAN_F11R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F11R1_FB30_Pos (30U)
+#define CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F11R1_FB30 CAN_F11R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F11R1_FB31_Pos (31U)
+#define CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F11R1_FB31 CAN_F11R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F12R1 register ******************/
+#define CAN_F12R1_FB0_Pos (0U)
+#define CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F12R1_FB0 CAN_F12R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F12R1_FB1_Pos (1U)
+#define CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F12R1_FB1 CAN_F12R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F12R1_FB2_Pos (2U)
+#define CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F12R1_FB2 CAN_F12R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F12R1_FB3_Pos (3U)
+#define CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F12R1_FB3 CAN_F12R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F12R1_FB4_Pos (4U)
+#define CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F12R1_FB4 CAN_F12R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F12R1_FB5_Pos (5U)
+#define CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F12R1_FB5 CAN_F12R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F12R1_FB6_Pos (6U)
+#define CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F12R1_FB6 CAN_F12R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F12R1_FB7_Pos (7U)
+#define CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F12R1_FB7 CAN_F12R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F12R1_FB8_Pos (8U)
+#define CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F12R1_FB8 CAN_F12R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F12R1_FB9_Pos (9U)
+#define CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F12R1_FB9 CAN_F12R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F12R1_FB10_Pos (10U)
+#define CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F12R1_FB10 CAN_F12R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F12R1_FB11_Pos (11U)
+#define CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F12R1_FB11 CAN_F12R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F12R1_FB12_Pos (12U)
+#define CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F12R1_FB12 CAN_F12R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F12R1_FB13_Pos (13U)
+#define CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F12R1_FB13 CAN_F12R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F12R1_FB14_Pos (14U)
+#define CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F12R1_FB14 CAN_F12R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F12R1_FB15_Pos (15U)
+#define CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F12R1_FB15 CAN_F12R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F12R1_FB16_Pos (16U)
+#define CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F12R1_FB16 CAN_F12R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F12R1_FB17_Pos (17U)
+#define CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F12R1_FB17 CAN_F12R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F12R1_FB18_Pos (18U)
+#define CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F12R1_FB18 CAN_F12R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F12R1_FB19_Pos (19U)
+#define CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F12R1_FB19 CAN_F12R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F12R1_FB20_Pos (20U)
+#define CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F12R1_FB20 CAN_F12R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F12R1_FB21_Pos (21U)
+#define CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F12R1_FB21 CAN_F12R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F12R1_FB22_Pos (22U)
+#define CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F12R1_FB22 CAN_F12R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F12R1_FB23_Pos (23U)
+#define CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F12R1_FB23 CAN_F12R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F12R1_FB24_Pos (24U)
+#define CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F12R1_FB24 CAN_F12R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F12R1_FB25_Pos (25U)
+#define CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F12R1_FB25 CAN_F12R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F12R1_FB26_Pos (26U)
+#define CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F12R1_FB26 CAN_F12R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F12R1_FB27_Pos (27U)
+#define CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F12R1_FB27 CAN_F12R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F12R1_FB28_Pos (28U)
+#define CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F12R1_FB28 CAN_F12R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F12R1_FB29_Pos (29U)
+#define CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos) /*!< 0x20000000 */
+#define CAN_F12R1_FB29 CAN_F12R1_FB29_Msk /*!<Filter bit 29 */
+#define CAN_F12R1_FB30_Pos (30U)
+#define CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos) /*!< 0x40000000 */
+#define CAN_F12R1_FB30 CAN_F12R1_FB30_Msk /*!<Filter bit 30 */
+#define CAN_F12R1_FB31_Pos (31U)
+#define CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos) /*!< 0x80000000 */
+#define CAN_F12R1_FB31 CAN_F12R1_FB31_Msk /*!<Filter bit 31 */
+
+/******************* Bit definition for CAN_F13R1 register ******************/
+#define CAN_F13R1_FB0_Pos (0U)
+#define CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos) /*!< 0x00000001 */
+#define CAN_F13R1_FB0 CAN_F13R1_FB0_Msk /*!<Filter bit 0 */
+#define CAN_F13R1_FB1_Pos (1U)
+#define CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos) /*!< 0x00000002 */
+#define CAN_F13R1_FB1 CAN_F13R1_FB1_Msk /*!<Filter bit 1 */
+#define CAN_F13R1_FB2_Pos (2U)
+#define CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos) /*!< 0x00000004 */
+#define CAN_F13R1_FB2 CAN_F13R1_FB2_Msk /*!<Filter bit 2 */
+#define CAN_F13R1_FB3_Pos (3U)
+#define CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos) /*!< 0x00000008 */
+#define CAN_F13R1_FB3 CAN_F13R1_FB3_Msk /*!<Filter bit 3 */
+#define CAN_F13R1_FB4_Pos (4U)
+#define CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos) /*!< 0x00000010 */
+#define CAN_F13R1_FB4 CAN_F13R1_FB4_Msk /*!<Filter bit 4 */
+#define CAN_F13R1_FB5_Pos (5U)
+#define CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos) /*!< 0x00000020 */
+#define CAN_F13R1_FB5 CAN_F13R1_FB5_Msk /*!<Filter bit 5 */
+#define CAN_F13R1_FB6_Pos (6U)
+#define CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos) /*!< 0x00000040 */
+#define CAN_F13R1_FB6 CAN_F13R1_FB6_Msk /*!<Filter bit 6 */
+#define CAN_F13R1_FB7_Pos (7U)
+#define CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos) /*!< 0x00000080 */
+#define CAN_F13R1_FB7 CAN_F13R1_FB7_Msk /*!<Filter bit 7 */
+#define CAN_F13R1_FB8_Pos (8U)
+#define CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos) /*!< 0x00000100 */
+#define CAN_F13R1_FB8 CAN_F13R1_FB8_Msk /*!<Filter bit 8 */
+#define CAN_F13R1_FB9_Pos (9U)
+#define CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos) /*!< 0x00000200 */
+#define CAN_F13R1_FB9 CAN_F13R1_FB9_Msk /*!<Filter bit 9 */
+#define CAN_F13R1_FB10_Pos (10U)
+#define CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos) /*!< 0x00000400 */
+#define CAN_F13R1_FB10 CAN_F13R1_FB10_Msk /*!<Filter bit 10 */
+#define CAN_F13R1_FB11_Pos (11U)
+#define CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos) /*!< 0x00000800 */
+#define CAN_F13R1_FB11 CAN_F13R1_FB11_Msk /*!<Filter bit 11 */
+#define CAN_F13R1_FB12_Pos (12U)
+#define CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos) /*!< 0x00001000 */
+#define CAN_F13R1_FB12 CAN_F13R1_FB12_Msk /*!<Filter bit 12 */
+#define CAN_F13R1_FB13_Pos (13U)
+#define CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos) /*!< 0x00002000 */
+#define CAN_F13R1_FB13 CAN_F13R1_FB13_Msk /*!<Filter bit 13 */
+#define CAN_F13R1_FB14_Pos (14U)
+#define CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos) /*!< 0x00004000 */
+#define CAN_F13R1_FB14 CAN_F13R1_FB14_Msk /*!<Filter bit 14 */
+#define CAN_F13R1_FB15_Pos (15U)
+#define CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos) /*!< 0x00008000 */
+#define CAN_F13R1_FB15 CAN_F13R1_FB15_Msk /*!<Filter bit 15 */
+#define CAN_F13R1_FB16_Pos (16U)
+#define CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos) /*!< 0x00010000 */
+#define CAN_F13R1_FB16 CAN_F13R1_FB16_Msk /*!<Filter bit 16 */
+#define CAN_F13R1_FB17_Pos (17U)
+#define CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos) /*!< 0x00020000 */
+#define CAN_F13R1_FB17 CAN_F13R1_FB17_Msk /*!<Filter bit 17 */
+#define CAN_F13R1_FB18_Pos (18U)
+#define CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos) /*!< 0x00040000 */
+#define CAN_F13R1_FB18 CAN_F13R1_FB18_Msk /*!<Filter bit 18 */
+#define CAN_F13R1_FB19_Pos (19U)
+#define CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos) /*!< 0x00080000 */
+#define CAN_F13R1_FB19 CAN_F13R1_FB19_Msk /*!<Filter bit 19 */
+#define CAN_F13R1_FB20_Pos (20U)
+#define CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos) /*!< 0x00100000 */
+#define CAN_F13R1_FB20 CAN_F13R1_FB20_Msk /*!<Filter bit 20 */
+#define CAN_F13R1_FB21_Pos (21U)
+#define CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos) /*!< 0x00200000 */
+#define CAN_F13R1_FB21 CAN_F13R1_FB21_Msk /*!<Filter bit 21 */
+#define CAN_F13R1_FB22_Pos (22U)
+#define CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos) /*!< 0x00400000 */
+#define CAN_F13R1_FB22 CAN_F13R1_FB22_Msk /*!<Filter bit 22 */
+#define CAN_F13R1_FB23_Pos (23U)
+#define CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos) /*!< 0x00800000 */
+#define CAN_F13R1_FB23 CAN_F13R1_FB23_Msk /*!<Filter bit 23 */
+#define CAN_F13R1_FB24_Pos (24U)
+#define CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos) /*!< 0x01000000 */
+#define CAN_F13R1_FB24 CAN_F13R1_FB24_Msk /*!<Filter bit 24 */
+#define CAN_F13R1_FB25_Pos (25U)
+#define CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos) /*!< 0x02000000 */
+#define CAN_F13R1_FB25 CAN_F13R1_FB25_Msk /*!<Filter bit 25 */
+#define CAN_F13R1_FB26_Pos (26U)
+#define CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos) /*!< 0x04000000 */
+#define CAN_F13R1_FB26 CAN_F13R1_FB26_Msk /*!<Filter bit 26 */
+#define CAN_F13R1_FB27_Pos (27U)
+#define CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos) /*!< 0x08000000 */
+#define CAN_F13R1_FB27 CAN_F13R1_FB27_Msk /*!<Filter bit 27 */
+#define CAN_F13R1_FB28_Pos (28U)
+#define CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos) /*!< 0x10000000 */
+#define CAN_F13R1_FB28 CAN_F13R1_FB28_Msk /*!<Filter bit 28 */
+#define CAN_F13R1_FB29_Pos (29U)
+#define CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos) /*!< 0x20000000 */
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