[GitHub] [tvm] Hzfengsy commented on a diff in pull request #13700: [TIR][Schedule] Improve cache_index to cache common subexpressions

[GitBox <gi...@apache.org>]

Hzfengsy commented on code in PR #13700:
URL: https://github.com/apache/tvm/pull/13700#discussion_r1068841038


##########
python/tvm/tir/schedule/schedule.py:
##########
@@ -1289,7 +1289,10 @@ def cache_inplace(data_io: T.Buffer[64, "int32"]) -> None:
 
     @type_checked
     def cache_index(
-        self, block: Union[BlockRV, str], buffer_index: Union[int, str, Buffer]
+        self,
+        block: Union[BlockRV, str],
+        storage_scope: str,
+        cse_thresh: int,

Review Comment:
   Can we set a default value for `cse_thresh`? e.g. 0/-1 for not enabling cse?



##########
tests/python/unittest/test_tir_schedule_cache_index.py:
##########
@@ -66,13 +65,408 @@ def resize_cache_index(
             B[n, c, vi, vj] = A[n, c, index_var_0[vi, vj], index_var_1[vj]]
 
 
+@T.prim_func
+def bilinear_resize(
+    x: T.Buffer[(1, 3, 40, 40), "float16"], resize: T.Buffer[(1, 3, 80, 80), "float16"]
+):
+    for i0, i1, i2, i3 in T.grid(1, 3, 80, 80):
+        with T.block("resize"):
+            i0_1, i1_1, i2_1, i3_1 = T.axis.remap("SSSS", [i0, i1, i2, i3])
+            T.reads(x[i0_1, i1_1, 0:40, 0:40])
+            T.writes(resize[i0_1, i1_1, i2_1, i3_1])
+            resize[i0_1, i1_1, i2_1, i3_1] = T.Cast(
+                "float16",
+                (
+                    T.Cast(

Review Comment:
   Can we have a much simpler case for better readability? Also, please use `#fmt: off` to turn off formatter for complex TVMScript 



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