[GitHub] [incubator-nuttx] gustavonihei commented on a change in pull request #4388: esp32: Re-organize the interrupt handling process to correctly handle the SMP case

[GitBox <gi...@apache.org>]

gustavonihei commented on a change in pull request #4388:
URL: https://github.com/apache/incubator-nuttx/pull/4388#discussion_r693084934



##########
File path: arch/xtensa/src/esp32/esp32_irq.c
##########
@@ -334,3 +626,301 @@ uintptr_t xtensa_intstack_alloc(void)
   return g_cpu_intstack_top[up_cpu_index()] - INTSTACK_SIZE;
 }
 #endif
+
+/****************************************************************************
+ * Name:  esp32_cpuint_initialize
+ *
+ * Description:
+ *   Initialize CPU interrupts
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; A negated errno value is returned on
+ *   any failure.
+ *
+ ****************************************************************************/
+
+int esp32_cpuint_initialize(void)
+{
+  uintptr_t regaddr;
+  uint8_t *intmap;
+#ifdef CONFIG_SMP
+  int cpu;
+#endif
+  int i;
+
+#ifdef CONFIG_SMP
+  /* Which CPU are we initializing */
+
+  cpu = up_cpu_index();
+  DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS);
+#endif
+
+  /* Disable all CPU interrupts on this CPU */
+
+  xtensa_disable_all();
+
+  /* Detach all peripheral sources PRO CPU interrupts */
+
+  for (i = 0; i < ESP32_NPERIPHERALS; i++)
+    {
+#ifdef CONFIG_SMP
+      if (cpu != 0)
+        {
+          regaddr = DPORT_APP_MAP_REGADDR(i);
+        }
+      else
+#endif
+        {
+          regaddr = DPORT_PRO_MAP_REGADDR(i);
+        }
+
+      putreg32(NO_CPUINT, regaddr);
+    }
+
+  /* Initialize CPU interrupt-to-IRQ mapping table */
+
+#ifdef CONFIG_SMP
+  if (cpu != 0)
+    {
+      intmap = g_cpu1_intmap;
+    }
+  else
+#endif
+    {
+      intmap = g_cpu0_intmap;
+    }
+
+  /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
+
+  memset(intmap, CPUINT_UNASSIGNED, ESP32_NCPUINTS);
+
+  /* Special case the 6 internal interrupts.
+   *
+   *   CPU interrupt bit           IRQ number
+   *   --------------------------- ---------------------
+   *   ESP32_CPUINT_MAC         0  ESP32_IRQ_MAC      4
+   *   ESP32_CPUINT_TIMER0      6  XTENSA_IRQ_TIMER0  0
+   *   ESP32_CPUINT_SOFTWARE0   7  Not yet defined
+   *   ESP32_CPUINT_PROFILING  11  Not yet defined
+   *   ESP32_CPUINT_TIMER1     15  XTENSA_IRQ_TIMER1  1
+   *   ESP32_CPUINT_TIMER2     16  XTENSA_IRQ_TIMER2  2
+   *   ESP32_CPUINT_SOFTWARE1  29  Not yet defined
+   */
+
+  intmap[ESP32_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0);
+  intmap[ESP32_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1);
+  intmap[ESP32_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2);
+
+  /* Reserve CPU interrupt for some special drivers */
+
+#ifdef CONFIG_ESP32_WIRELESS
+  intmap[ESP32_CPUINT_MAC]    = CPUINT_ASSIGN(ESP32_IRQ_MAC);
+#endif
+
+  return OK;
+}
+
+/****************************************************************************
+ * Name:  esp32_setup_irq
+ *
+ * Description:
+ *   This function sets up the IRQ. It allocates a CPU interrupt of the given
+ *   priority and type and attaches it to the given peripheral.
+ *
+ * Input Parameters:
+ *   cpu      - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ *   periphid - The peripheral number from irq.h to be assigned to
+ *              a CPU interrupt.
+ *   priority - Interrupt's priority (1 - 5).
+ *   type     - Interrupt's type (level or edge).
+ *
+ * Returned Value:
+ *   The allocated CPU interrupt on success, a negated errno value on
+ *   failure.
+ *
+ ****************************************************************************/
+
+int esp32_setup_irq(int cpu, int periphid, int priority, int type)
+{
+  irqstate_t irqstate;
+  uintptr_t regaddr;
+  uint8_t *intmap;
+  int irq;
+  int cpuint;
+
+  irqstate = enter_critical_section();
+
+  /* Setting up an IRQ includes the following steps:
+   *    1. Allocate a CPU interrupt.
+   *    2. Attach that CPU interrup to the peripheral.

Review comment:
       ```suggestion
      *    2. Attach that CPU interrupt to the peripheral.
   ```




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