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Posted to commits@mynewt.apache.org by st...@apache.org on 2016/07/28 00:19:01 UTC
[22/28] incubator-mynewt-core git commit: remove nrf52xx custom
nordic headers and replace them with local headers.
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/260aad13/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_bitfields.h
----------------------------------------------------------------------
diff --git a/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_bitfields.h b/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_bitfields.h
deleted file mode 100755
index 6d7de32..0000000
--- a/hw/mcu/nordic/nrf52xxx/include/mcu/nrf52_bitfields.h
+++ /dev/null
@@ -1,12140 +0,0 @@
-/* Copyright (c) 2015, Nordic Semiconductor ASA
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * * Redistributions of source code must retain the above copyright notice, this
- * list of conditions and the following disclaimer.
- *
- * * Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * * Neither the name of Nordic Semiconductor ASA nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- */
-#ifndef __NRF52_BITS_H
-#define __NRF52_BITS_H
-
-/*lint ++flb "Enter library region" */
-
-/* Peripheral: AAR */
-/* Description: Accelerated Address Resolver */
-
-/* Register: AAR_INTENSET */
-/* Description: Enable interrupt */
-
-/* Bit 2 : Write '1' to Enable interrupt on EVENTS_NOTRESOLVED event */
-#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
-#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
-#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
-
-/* Bit 1 : Write '1' to Enable interrupt on EVENTS_RESOLVED event */
-#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
-#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
-#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
-
-/* Bit 0 : Write '1' to Enable interrupt on EVENTS_END event */
-#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
-#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
-#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
-
-/* Register: AAR_INTENCLR */
-/* Description: Disable interrupt */
-
-/* Bit 2 : Write '1' to Clear interrupt on EVENTS_NOTRESOLVED event */
-#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
-#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
-#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
-#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
-
-/* Bit 1 : Write '1' to Clear interrupt on EVENTS_RESOLVED event */
-#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
-#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
-#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
-#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
-
-/* Bit 0 : Write '1' to Clear interrupt on EVENTS_END event */
-#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
-#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
-#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
-#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
-#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
-
-/* Register: AAR_STATUS */
-/* Description: Resolution status */
-
-/* Bits 3..0 : The IRK that was used last time an address was resolved */
-#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
-
-/* Register: AAR_ENABLE */
-/* Description: Enable AAR */
-
-/* Bits 1..0 : Enable or disable AAR */
-#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
-#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
-
-/* Register: AAR_NIRK */
-/* Description: Number of IRKs */
-
-/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
-#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
-#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
-
-/* Register: AAR_IRKPTR */
-/* Description: Pointer to IRK data structure */
-
-/* Bits 31..0 : Pointer to the IRK data structure */
-#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
-#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
-
-/* Register: AAR_ADDRPTR */
-/* Description: Pointer to the resolvable address */
-
-/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
-#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
-#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
-
-/* Register: AAR_SCRATCHPTR */
-/* Description: Pointer to data area used for temporary storage */
-
-/* Bits 31..0 : Pointer to a "scratch" data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
-#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
-#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
-
-
-/* Peripheral: BPROT */
-/* Description: Block Protect */
-
-/* Register: BPROT_CONFIG0 */
-/* Description: Block protect configuration register 0 */
-
-/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
-#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
-#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
-#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
-#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
-#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
-#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
-#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
-#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
-#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
-#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
-#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
-#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
-#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
-#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
-#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
-#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
-#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
-#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
-#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
-#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
-#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
-#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
-#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
-#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
-#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
-#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
-#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
-#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
-#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
-#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
-#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
-#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
-#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
-#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
-#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
-#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
-#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
-#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
-#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
-#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
-#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
-#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
-#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
-#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
-#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
-#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
-#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
-#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
-#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
-#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
-#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
-#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
-#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
-#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
-#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
-#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
-#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
-#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
-#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
-#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
-#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
-#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
-
-/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
-#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
-#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
-#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
-
-/* Register: BPROT_CONFIG1 */
-/* Description: Block protect configuration register 1 */
-
-/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
-#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
-#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
-#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
-#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
-#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
-#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
-#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
-#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
-#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
-#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
-#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
-#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
-#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
-#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
-#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
-#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
-#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
-#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
-#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
-#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
-#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
-#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
-#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
-#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
-#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
-#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
-#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
-#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
-#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
-#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
-#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
-#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
-#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
-#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
-#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
-#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
-#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
-#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
-#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
-#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
-#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
-#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
-#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
-#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
-#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
-#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
-#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
-#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
-#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
-#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
-#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
-#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
-#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
-#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
-#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
-#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
-#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
-#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
-#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
-#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
-#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
-#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
-#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
-#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
-#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
-
-/* Register: BPROT_DISABLEINDEBUG */
-/* Description: Disable protection mechanism in debug mode */
-
-/* Bit 0 : Disable the protection mechanism for NVM regions while in debug mode. This register will only disable the protection mechanism if the device is in debug mode. */
-#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
-#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
-#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
-#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
-
-/* Register: BPROT_CONFIG2 */
-/* Description: Block protect configuration register 2 */
-
-/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
-#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
-#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
-#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
-#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
-#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
-#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
-#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
-#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
-#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
-#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
-#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
-#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
-#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
-#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
-#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
-#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
-#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
-#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
-#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
-#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
-#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
-#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
-#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
-#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
-#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
-#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
-#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
-#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
-#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
-#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
-#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
-#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
-#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
-#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
-#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
-#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
-#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
-#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
-#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
-#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
-#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
-#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
-#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
-#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
-#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
-#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
-#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
-#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
-#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
-#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
-#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
-#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
-#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
-#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
-#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
-#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
-#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
-#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
-#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
-#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
-#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
-#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
-#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
-#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
-#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
-
-/* Register: BPROT_CONFIG3 */
-/* Description: Block protect configuration register 3 */
-
-/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
-#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
-#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
-#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
-#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
-#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
-#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
-#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
-#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
-#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
-#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
-#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
-#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
-#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
-#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
-#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
-#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
-#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
-#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
-#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
-#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
-#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
-#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
-#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
-#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
-#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
-#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
-#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
-#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
-#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
-#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
-#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
-#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
-#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
-#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
-#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
-#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
-#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
-#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
-#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
-#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
-#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
-#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
-#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
-#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
-#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
-#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
-#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
-#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
-#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
-#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
-#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
-#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
-#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
-#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
-#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
-#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
-#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
-#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
-#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
-#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
-#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
-#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
-
-/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
-#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
-#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
-#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
-#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
-
-
-/* Peripheral: CCM */
-/* Description: AES CCM Mode Encryption */
-
-/* Register: CCM_SHORTS */
-/* Description: Shortcut register */
-
-/* Bit 0 : Shortcut between EVENTS_ENDKSGEN event and TASKS_CRYPT task */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
-#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
-
-/* Register: CCM_INTENSET */
-/* Description: Enable interrupt */
-
-/* Bit 2 : Write '1' to Enable interrupt on EVENTS_ERROR event */
-#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
-#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
-#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
-
-/* Bit 1 : Write '1' to Enable interrupt on EVENTS_ENDCRYPT event */
-#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
-#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
-#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
-
-/* Bit 0 : Write '1' to Enable interrupt on EVENTS_ENDKSGEN event */
-#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
-#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
-#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
-
-/* Register: CCM_INTENCLR */
-/* Description: Disable interrupt */
-
-/* Bit 2 : Write '1' to Clear interrupt on EVENTS_ERROR event */
-#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
-#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
-#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
-#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
-#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
-
-/* Bit 1 : Write '1' to Clear interrupt on EVENTS_ENDCRYPT event */
-#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
-#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
-#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
-#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
-
-/* Bit 0 : Write '1' to Clear interrupt on EVENTS_ENDKSGEN event */
-#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
-#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
-#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
-#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
-
-/* Register: CCM_MICSTATUS */
-/* Description: MIC check result */
-
-/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
-#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
-#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
-#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
-
-/* Register: CCM_ENABLE */
-/* Description: Enable */
-
-/* Bits 1..0 : Enable or disable CCM */
-#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
-#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
-
-/* Register: CCM_MODE */
-/* Description: Operation mode */
-
-/* Bit 24 : Packet length configuration */
-#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
-#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
-#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
-#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
-
-/* Bit 16 : Data rate that the CCM shall run in synch with */
-#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
-#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
-#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
-#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
-
-/* Bit 0 : The mode of operation to be used */
-#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
-#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
-#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
-#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
-
-/* Register: CCM_CNFPTR */
-/* Description: Pointer to data structure holding AES key and NONCE vector */
-
-/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
-#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
-#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
-
-/* Register: CCM_INPTR */
-/* Description: Input pointer */
-
-/* Bits 31..0 : Input pointer */
-#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
-#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
-
-/* Register: CCM_OUTPTR */
-/* Description: Output pointer */
-
-/* Bits 31..0 : Output pointer */
-#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
-#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
-
-/* Register: CCM_SCRATCHPTR */
-/* Description: Pointer to data area used for temporary storage */
-
-/* Bits 31..0 : Pointer to a "scratch" data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.The scratch area is used for temporary storage of data during key-stream generation and encryption. A space of minimum 43 bytes must be reserved. */
-#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
-#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
-
-
-/* Peripheral: CLOCK */
-/* Description: Clock control */
-
-/* Register: CLOCK_INTENSET */
-/* Description: Enable interrupt */
-
-/* Bit 4 : Write '1' to Enable interrupt on EVENTS_CTTO event */
-#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
-
-/* Bit 3 : Write '1' to Enable interrupt on EVENTS_DONE event */
-#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
-
-/* Bit 1 : Write '1' to Enable interrupt on EVENTS_LFCLKSTARTED event */
-#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
-
-/* Bit 0 : Write '1' to Enable interrupt on EVENTS_HFCLKSTARTED event */
-#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
-
-/* Register: CLOCK_INTENCLR */
-/* Description: Disable interrupt */
-
-/* Bit 4 : Write '1' to Clear interrupt on EVENTS_CTTO event */
-#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
-#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
-
-/* Bit 3 : Write '1' to Clear interrupt on EVENTS_DONE event */
-#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
-#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
-#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
-
-/* Bit 1 : Write '1' to Clear interrupt on EVENTS_LFCLKSTARTED event */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
-
-/* Bit 0 : Write '1' to Clear interrupt on EVENTS_HFCLKSTARTED event */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
-#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
-
-/* Register: CLOCK_HFCLKRUN */
-/* Description: Status indicating that HFCLKSTART task has been triggered */
-
-/* Bit 0 : HFCLKSTART task triggered or not */
-#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
-#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
-
-/* Register: CLOCK_HFCLKSTAT */
-/* Description: Which HFCLK source is running */
-
-/* Bit 16 : HFCLK state */
-#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
-#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
-
-/* Bit 0 : Active clock source */
-#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal oscillator (HFINT) */
-#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 32 MHz crystal oscillator (HFXO) */
-
-/* Register: CLOCK_LFCLKRUN */
-/* Description: Status indicating that LFCLKSTART task has been triggered */
-
-/* Bit 0 : LFCLKSTART task triggered or not */
-#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
-#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
-#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
-
-/* Register: CLOCK_LFCLKSTAT */
-/* Description: Which LFCLK source is running */
-
-/* Bit 16 : LFCLK state */
-#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
-#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
-#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
-
-/* Bits 1..0 : Active clock source */
-#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
-#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
-#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
-
-/* Register: CLOCK_LFCLKSRCCOPY */
-/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
-
-/* Bits 1..0 : Clock source */
-#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
-#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
-#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
-
-/* Register: CLOCK_LFCLKSRC */
-/* Description: Clock source for the LFCLK */
-
-/* Bits 1..0 : Clock source */
-#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
-#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
-#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
-#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
-
-/* Register: CLOCK_CTIV */
-/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
-
-/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
-#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
-#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
-
-/* Register: CLOCK_TRACECONFIG */
-/* Description: Clocking options for the Trace Port debug interface */
-
-/* Bits 17..16 : Pin multiplexing of trace signals. */
-#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
-#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
-#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
-#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
-#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
-
-/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
-#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
-#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
-#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
-#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
-#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
-#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
-
-
-/* Peripheral: COMP */
-/* Description: Comparator */
-
-/* Register: COMP_SHORTS */
-/* Description: Shortcut register */
-
-/* Bit 4 : Shortcut between EVENTS_CROSS event and TASKS_STOP task */
-#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
-#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
-#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
-#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
-
-/* Bit 3 : Shortcut between EVENTS_UP event and TASKS_STOP task */
-#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
-#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
-#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
-#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
-
-/* Bit 2 : Shortcut between EVENTS_DOWN event and TASKS_STOP task */
-#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
-#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
-#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
-#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
-
-/* Bit 1 : Shortcut between EVENTS_READY event and TASKS_STOP task */
-#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
-#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
-#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
-#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
-
-/* Bit 0 : Shortcut between EVENTS_READY event and TASKS_SAMPLE task */
-#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
-#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
-#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
-#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
-
-/* Register: COMP_INTEN */
-/* Description: Enable or disable interrupt */
-
-/* Bit 3 : Enable or disable interrupt on EVENTS_CROSS event */
-#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
-#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
-
-/* Bit 2 : Enable or disable interrupt on EVENTS_UP event */
-#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
-#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
-#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
-#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
-
-/* Bit 1 : Enable or disable interrupt on EVENTS_DOWN event */
-#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
-#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
-
-/* Bit 0 : Enable or disable interrupt on EVENTS_READY event */
-#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
-#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
-#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
-#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
-
-/* Register: COMP_INTENSET */
-/* Description: Enable interrupt */
-
-/* Bit 3 : Write '1' to Enable interrupt on EVENTS_CROSS event */
-#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
-
-/* Bit 2 : Write '1' to Enable interrupt on EVENTS_UP event */
-#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
-#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
-#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
-
-/* Bit 1 : Write '1' to Enable interrupt on EVENTS_DOWN event */
-#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
-
-/* Bit 0 : Write '1' to Enable interrupt on EVENTS_READY event */
-#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
-#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
-#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
-
-/* Register: COMP_INTENCLR */
-/* Description: Disable interrupt */
-
-/* Bit 3 : Write '1' to Clear interrupt on EVENTS_CROSS event */
-#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
-#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
-#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
-
-/* Bit 2 : Write '1' to Clear interrupt on EVENTS_UP event */
-#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
-#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
-#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
-
-/* Bit 1 : Write '1' to Clear interrupt on EVENTS_DOWN event */
-#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
-#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
-#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
-
-/* Bit 0 : Write '1' to Clear interrupt on EVENTS_READY event */
-#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
-#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
-#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
-#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
-#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
-
-/* Register: COMP_RESULT */
-/* Description: Compare result */
-
-/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
-#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
-#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
-#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ < VIN-) */
-#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ > VIN-) */
-
-/* Register: COMP_ENABLE */
-/* Description: COMP enable */
-
-/* Bits 1..0 : Enable or disable COMP */
-#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
-#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
-#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
-#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
-
-/* Register: COMP_PSEL */
-/* Description: Pin select */
-
-/* Bits 2..0 : Analog pin select */
-#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
-#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
-#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
-#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
-
-/* Register: COMP_REFSEL */
-/* Description: Reference source select */
-
-/* Bits 2..0 : Reference select */
-#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
-#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
-#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD >= 1.7 V) */
-#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V) */
-#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V) */
-#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
-#define COMP_REFSEL_REFSEL_ARef (5UL) /*!< VREF = AREF (VDD >= VREF >= AREFMIN) */
-
-/* Register: COMP_EXTREFSEL */
-/* Description: External reference select */
-
-/* Bit 0 : External analog reference select */
-#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
-#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
-#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
-#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
-
-/* Register: COMP_TH */
-/* Description: Threshold configuration for hysteresis unit */
-
-/* Bits 13..8 : VDOWN = (THDOWN+1)/64*VREF */
-#define COMP_TH_THDOWN_Pos (8UL) /*!<
<TRUNCATED>