[GitHub] [tvm-rfcs] wrongtest commented on pull request #18: [RFC] Adding initial SVE implementation

[GitBox <gi...@apache.org>]

wrongtest commented on PR #18:
URL: https://github.com/apache/tvm-rfcs/pull/18#issuecomment-1173003679

   Hi~ here are my two questions :) 
   cc @kparzysz-quic 
   
   - > 2\. Make vector length a parameter to `stage.vectorize`.
   
       What is the different between 
       - `sch[C].vectorize(v, vector_length=32)` and 
       - `vo, vi = sch[C].split(v, 32)` then `sch[C].vectorize(vi)`
   
        It seems that we could also choose to properly lower the split's predicate to reach the same goal as proposed below. For example,  weapons introduced in RFC https://github.com/apache/tvm-rfcs/pull/77 may help? 
   
   
   - > 3\. Introduce "predicate" to `BufferLoad` and `BufferStore`.
   
       Our team also get confused on how to represent predicated ld/st, when several months ago the upstream upgrade `T.load`/`T.store` (who have 1D predicate field) to `BufferLoad`/`BufferStore`. Now since `BufferLoad`/`BufferStore` are multi-dimensional, the predicate seems to also be multi-dimensional predicate? 
   
       Another concern is whether embedding predicate into `BufferLoad`/`BufferStore` increase the complexity (or break) buffer region related analysis in existing implementations. Could we leverage `T.select(pred, A[...], undef)` to represent `A[..., pred]`, or just match the predicated memory access pattern like `if (pred) C[...] = ...`?
   
   Thanks!
   
   
   
   
   
   


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