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Posted to commits@mynewt.apache.org by GitBox <gi...@apache.org> on 2021/08/15 22:19:31 UTC
[GitHub] [mynewt-core] kasjer opened a new pull request #2662: pic32 updates and 2 more pic32 BSPs
kasjer opened a new pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662
Supported PIC32 MCU were not up to date with current state of mynewt.
Those are the changes that update PIC32 ecosystem:
- two PIC32MZ boards
- COUNTER register (used for ticks) stopped when debugger stops
- context switch updated
- compiler changes that allows to actually build more then blinky
- idle task stack had to be increased for PIC32
- support for MCUBOOT
- support for stock _sbrk
- memory usage reduction
- fixes in pin assignments
- support for 64/100/124/144 pin chips
- download via JLink (no pickitX support yet)
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[GitHub] [mynewt-core] kasjer commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
kasjer commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691431210
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/mips_bsp.h
##########
@@ -0,0 +1,24 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_MIPS_BSP_
+#define H_MIPS_BSP_
+
+extern const struct hal_flash pic32mz_flash_dev;
+
+#endif /* H_NATIVE_BSP_ */
Review comment:
done
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/mips_hal.h
##########
@@ -0,0 +1,63 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the HAL implementations within this MCU */
+
+#ifndef MIPS_HAL_H
+#define MIPS_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_UNUSED 0xFF
+
+/* I/O pins for UART */
+struct mips_uart_cfg {
+ uint8_t tx;
+ uint8_t rx;
+ uint8_t rts;
+ uint8_t cts;
+};
+
+/* I/O pins for SPI, SS pin is not handled by the driver */
+struct mips_spi_cfg {
+ uint8_t mosi;
+ uint8_t miso;
+ uint8_t sck;
+};
+
+/* I/O pins for I2C, also set frequency */
+struct mips_i2c_cfg {
+ uint8_t scl;
+ uint8_t sda;
+ uint32_t frequency;
+};
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MCU_HAL_H */
Review comment:
done
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/pps.h
##########
@@ -0,0 +1,161 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the Periphal Pin Select module within this MCU */
Review comment:
done
##########
File path: hw/bsp/olimex-pic32-hmz144/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = HS
+#if 1
+#pragma config FNOSC = FRCDIV
+#elif MYNEWT_VAL(CLOCK_FREQ) == 24000000
+#pragma config FNOSC = POSC
+/* 24MHz posc input -> 50mhz*/
+#pragma config FPLLICLK=0
+#elif MYNEWT_VAL(CLOCK_FREQ) == 50000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3 -> 8, multiply by 50 -> 400, div by 8 -> 50mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_8
+#elif MYNEWT_VAL(CLOCK_FREQ) == 100000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 4 -> 100mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_4
+#elif MYNEWT_VAL(CLOCK_FREQ) == 200000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#else
+#error Clock requency not supported
+#endif
+#endif
+/* USB off */
+#pragma config FUSBIDIO=0
+/*
+ * Watchdog in non-window mode, watchdog disabled during flash programming,
+ * period: 32s
+ */
+#pragma config WINDIS=1, WDTSPGM=1, WDTPS=15
+
+#endif
+//uint32_t SystemCoreClock = MYNEWT_VAL(CLOCK_FREQ);
Review comment:
done
##########
File path: hw/bsp/olimex-pic32-emz64/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = EC
+#if 1
Review comment:
done
##########
File path: kernel/os/src/arch/pic32/asm/ctx.S
##########
@@ -90,20 +88,24 @@
sw k0, CTX_EPC(sp)
mfc0 k0, _CP0_BADVADDR
sw k0, CTX_BADVADDR(sp)
+ mfc0 k0, _CP0_CAUSE
+ sw k0, CTX_CAUSE(sp)
+
Review comment:
tabs removed
##########
File path: hw/mcu/microchip/pic32mz/src/hal_timer.c
##########
@@ -0,0 +1,599 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <os/mynewt.h>
+#include <xc.h>
+#include <mcu/pic32.h>
+#include <hal/hal_timer.h>
+#include <mcu/mips_hal.h>
+
+#define PIC32MZ_TIMER_COUNT (8)
+#define PIC32MZ_PRESCALER_COUNT (8)
+
+#define TxCON(T) (base_address[T][0x0 / 0x4])
+#define TxCONCLR(T) (base_address[T][0x4 / 0x4])
+#define TxCONSET(T) (base_address[T][0x8 / 0x4])
+#define TMRx(T) (base_address[T][0x10 / 0x4])
+#define PRx(T) (base_address[T][0x20 / 0x4])
+
+static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = {
+ (volatile uint32_t *)_TMR2_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR3_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR4_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR5_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR6_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR7_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR8_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR9_BASE_ADDRESS
+};
+
+static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] =
+{1, 2, 4, 8, 16, 32, 64, 256};
Review comment:
done
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
Review comment:
done
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
Review comment:
donw
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
+ if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
+ return -1;
+ }
+
+ mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ assert(uarts[port].u_pins->rts != PIN_UNUSED);
+ mode |= ((uarts[port].u_pins->cts != PIN_UNUSED) ? 2 : 1) << _U1MODE_UEN0_POSITION;
+ }
+ uarts[port].u_rx_stall = 0;
+
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ if (databits == 9) {
+ mode |= _U1MODE_PDSEL_MASK;
+ }
+ break;
+ case HAL_UART_PARITY_ODD:
+ if (databits == 9) { // PIC does not do 9 bit data + parity.
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL1_MASK;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ if (databits == 9) {
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL0_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ /* Configure TX/RX pins */
+ if (uarts[port].u_pins) {
+ ret = 0;
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U1TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U1RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U1RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U1CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U2TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U2RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U2RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U2CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U3TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U3RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U3RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U3CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U4TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U4RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U4RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U4CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U5TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U5RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U5RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U5CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U6TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U6RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U6RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U6CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+ default:
+ return -1;
+ }
+ if (ret) {
+ return -1;
+ }
+ }
+
+ /* Set pin as digital input to clear ANSEL bit if any */
+ hal_gpio_init_in(uarts[port].u_pins->rx, HAL_GPIO_PULL_NONE);
+
+ divisor = peripheral_clk / (4 * baudrate) - 1;
+
+ /* disable */
+ UxMODE(port) = 0;
+ _nop();
+ UxBRG(port) = divisor;
+ UxMODE(port) = mode;
+ UxSTA(port) = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
+
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ /* clear RX interrupt flag */
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC3SET = _IEC3_U1RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC28CLR = _IPC28_U1RXIP_MASK;
+ IPC28SET = (1 << _IPC28_U1RXIP_POSITION); // priority 1
Review comment:
done
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
Review comment:
done
##########
File path: hw/mcu/microchip/pic32mz/src/pic32mz_periph.c
##########
@@ -0,0 +1,382 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+
+#include <os/mynewt.h>
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_i2c.h>
+#include <hal/hal_timer.h>
+#include <hal/hal_spi.h>
+#include <uart/uart.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <uart_hal/uart_hal.h>
+#include <bsp/bsp.h>
+
+static struct uart_dev uart_0_dev;
+static struct uart_dev uart_1_dev;
+static struct uart_dev uart_2_dev;
+static struct uart_dev uart_3_dev;
+static struct uart_dev uart_4_dev;
+static struct uart_dev uart_5_dev;
+
+static const struct mips_uart_cfg uart_0_cfg = {
+ .tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_1_cfg = {
+ .tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_1_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_2_cfg = {
+ .tx = MYNEWT_VAL(UART_2_PIN_TX),
+ .rx = MYNEWT_VAL(UART_2_PIN_RX),
+ .rts = MYNEWT_VAL(UART_2_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_2_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_3_cfg = {
+ .tx = MYNEWT_VAL(UART_3_PIN_TX),
+ .rx = MYNEWT_VAL(UART_3_PIN_RX),
+ .rts = MYNEWT_VAL(UART_3_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_3_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_4_cfg = {
+ .tx = MYNEWT_VAL(UART_4_PIN_TX),
+ .rx = MYNEWT_VAL(UART_4_PIN_RX),
+ .rts = MYNEWT_VAL(UART_4_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_4_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_5_cfg = {
+ .tx = MYNEWT_VAL(UART_5_PIN_TX),
+ .rx = MYNEWT_VAL(UART_5_PIN_RX),
+ .rts = MYNEWT_VAL(UART_5_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_5_PIN_CTS),
+};
+
+/*
+ * SPI_0
+ * SCK1 -> RD1
+ */
+static const struct mips_spi_cfg spi_0_cfg = {
+ .mosi = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(1),
+};
+
+/*
+ * SPI_1
+ * SCK2 -> RG6
+ */
+static const struct mips_spi_cfg spi_1_cfg = {
+ .mosi = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTG(6),
+};
+
+/*
+ * SPI_2
+ * SCK3 -> B14
+ */
+static const struct mips_spi_cfg spi_2_cfg = {
+ .mosi = MYNEWT_VAL(SPI_2_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_2_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTB(14),
+};
+
+/*
+ * SPI_3
+ * SCK4 -> RD10
+ */
+static const struct mips_spi_cfg spi_3_cfg = {
+ .mosi = MYNEWT_VAL(SPI_3_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_3_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(10),
+};
+
+#ifdef _SPI5_BASE_ADDRESS
+/*
+ * SPI_4
+ * SCK5 -> RF13
+ */
+static const struct mips_spi_cfg spi_4_cfg = {
+ .mosi = MYNEWT_VAL(SPI_4_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_4_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTF(13),
+};
+#endif
+
+#ifdef _SPI6_BASE_ADDRESS
+/*
+ * SPI_5
+ * SCK6 -> RD15
+ */
+static const struct mips_spi_cfg spi_5_cfg = {
+ .mosi = MYNEWT_VAL(SPI_5_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_5_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(15),
+};
+#endif
+
+/*
+ * I2C_0 -> I2C1
+ * SCL1 -> RA14 (D10 for 64 pin packges)
+ * SDA1 -> RA15 (D9 for 64 pin packges)
+ */
+static const struct mips_i2c_cfg i2c_0_cfg = {
+#if __PIC32_PIN_COUNT > 64
+ .scl = MCU_GPIO_PORTA(14),
+ .sda = MCU_GPIO_PORTA(15),
+#else
+ .scl = MCU_GPIO_PORTD(10),
+ .sda = MCU_GPIO_PORTD(9),
+#endif
+ .frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ) * 1000,
+};
+
+#ifdef _I2C2_BASE_ADDRESS
+/*
+ * I2C_1 -> I2C2
+ * SCL2 -> RA2
+ * SDA2 -> RA3
+ */
+static const struct mips_i2c_cfg i2c_1_cfg = {
+ .scl = MCU_GPIO_PORTA(2),
+ .sda = MCU_GPIO_PORTA(3),
+ .frequency = MYNEWT_VAL(I2C_1_FREQ_KHZ) * 1000,
+};
+#endif
+
+/*
+ * I2C_2 -> I2C3
+ * SCL3 -> RF8 (D3 for 64 pin packges)
+ * SDA3 -> RF2 (D2 for 64 pin packges)
+ */
+static const struct mips_i2c_cfg i2c_2_cfg = {
+#if __PIC32_PIN_COUNT > 64
+ .scl = MCU_GPIO_PORTF(8),
+ .sda = MCU_GPIO_PORTF(2),
+#else
+ .scl = MCU_GPIO_PORTD(3),
+ .sda = MCU_GPIO_PORTD(2),
+#endif
+ .frequency = MYNEWT_VAL(I2C_2_FREQ_KHZ) * 1000,
+};
+
+/*
+ * I2C_3 -> I2C4
+ * SCL4 -> RG8
+ * SDA4 -> RG7
+ */
+static const struct mips_i2c_cfg i2c_3_cfg = {
+ .scl = MCU_GPIO_PORTG(8),
+ .sda = MCU_GPIO_PORTG(7),
+ .frequency = MYNEWT_VAL(I2C_3_FREQ_KHZ) * 1000,
+};
+
+/*
+ * I2C_4 -> I2C5
+ * SCL5 -> RF5
+ * SDA5 -> RF4
+ */
+static const struct mips_i2c_cfg i2c_4_cfg = {
+ .scl = MCU_GPIO_PORTF(5),
+ .sda = MCU_GPIO_PORTF(4),
+ .frequency = MYNEWT_VAL(I2C_4_FREQ_KHZ) * 1000,
+};
+
+static void
+pic32mz_periph_create_timer_devs(void)
+{
+ int rc;
+
+ if (MYNEWT_VAL(TIMER_0)) {
Review comment:
With this style generate code is same but paths that are not included in binary are still check for syntax.
It also eliminates need to `#ifdef` RC or `(void)rc`;
Also static variables would need to be in `#ifdef` block can be left alone and `-gc-section` will take care of them
##########
File path: hw/mcu/microchip/pic32mz/syscfg.yml
##########
@@ -0,0 +1,279 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ MCU_FLASH_MIN_WRITE_SIZE:
+ description: >
+ Specifies the required alignment for internal flash writes.
+ Used internally by the newt tool.
+ value: 4
+ I2C_0:
+ description: 'I2C interface 0'
+ value: 0
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_1:
+ description: 'I2C interface 1'
+ value: 0
+ I2C_1_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_2:
+ description: 'I2C interface 2'
+ value: 0
+ I2C_2_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_3:
+ description: 'I2C interface 3'
+ value: 0
+ I2C_3_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_4:
+ description: 'I2C interface 4'
+ value: 0
+ I2C_4_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
+ SPI_0_MASTER:
+ description: 'SPI 0 master'
+ value: 0
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 0xFF
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 0xFF
+ SPI_1_MASTER:
+ description: 'SPI 1 master'
+ value: 0
+ SPI_1_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 0xFF
+ SPI_1_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 0xFF
+ SPI_2_MASTER:
+ description: 'SPI 2 master'
+ value: 0
+ SPI_2_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 0xFF
+ SPI_2_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 0xFF
+ SPI_3_MASTER:
+ description: 'SPI 3 master'
+ value: 0
+ SPI_3_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 0xFF
+ SPI_3_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 0xFF
+ SPI_4_MASTER:
+ description: 'SPI 4 master'
+ value: 0
+ SPI_4_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 0xFF
+ SPI_4_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 0xFF
+ SPI_5_MASTER:
+ description: 'SPI 5 master'
+ value: 0
+ SPI_5_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 0xFF
+ SPI_5_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 0xFF
+
+ UART_0:
+ description: Enable UART_0 (Datasheet peripheral name UART1)
+ value: 0
+ UART_0_PIN_TX:
+ description: 'TX pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_RX:
+ description: 'RX pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_RTS:
+ description: 'RTS pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_CTS:
+ description: 'CTS pin for UART_0'
+ value: 0xFF
+
+ UART_1:
+ description: Enable UART_1 (Datasheet peripheral name UART2)
+ value: 0
+ UART_1_PIN_TX:
+ description: 'TX pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_RX:
+ description: 'RX pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_RTS:
+ description: 'RTS pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_CTS:
+ description: 'CTS pin for UART_1'
+ value: 0xFF
+
+ UART_2:
+ description: Enable UART_2 (Datasheet peripheral name UART3)
+ value: 0
+ UART_2_PIN_TX:
+ description: 'TX pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_RX:
+ description: 'RX pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_RTS:
+ description: 'RTS pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_CTS:
+ description: 'CTS pin for UART_2'
+ value: 0xFF
+
+ UART_3:
+ description: Enable UART_4 (Datasheet peripheral name UART4)
+ value: 0
+ UART_3_PIN_TX:
+ description: 'TX pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_RX:
+ description: 'RX pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_RTS:
+ description: 'RTS pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_CTS:
+ description: 'CTS pin for UART_3'
+ value: 0xFF
+
+ UART_4:
+ description: Enable UART_4 (Datasheet peripheral name UART5)
+ value: 0
+ UART_4_PIN_TX:
+ description: 'TX pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_RX:
+ description: 'RX pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_RTS:
+ description: 'RTS pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_CTS:
+ description: 'CTS pin for UART_4'
+ value: 0xFF
+
+ UART_5:
+ description: Enable UART_5 (Datasheet peripheral name UART6)
+ value: 0
+ UART_5_PIN_TX:
+ description: 'TX pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_RX:
+ description: 'RX pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_RTS:
+ description: 'RTS pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_CTS:
+ description: 'CTS pin for UART_5'
+ value: 0xFF
+
+ TIMER_0:
+ description: "Whether to enable Timer 0"
+ value: 1
+
+ TIMER_1:
+ description: "Whether to enable Timer 1"
+ value: 0
+
+ TIMER_2:
+ description: "Whether to enable Timer 2"
+ value: 0
+
+ TIMER_3:
+ description: "Whether to enable Timer 3"
+ value: 0
+
+ TIMER_4:
+ description: "Whether to enable Timer 4"
+ value: 0
+
+ TIMER_5:
+ description: "Whether to enable Timer 5"
+ value: 0
+
+ TIMER_6:
+ description: "Whether to enable Timer 6"
+ value: 0
+
+ TIMER_7:
+ description: "Whether to enable Timer 7"
+ value: 0
+
+ SYSTEM_CLOCK_OSC_FREQ:
+ descriprion: HS Oscilator/External clock freqency.
+ value:
+ SYSTEM_CLOCK_SRC:
+ description: >
+ Select system clock source, that will affect both CONFIG registers
+ and startup code.
+ value:
+ choices:
+ - FRC_DIV
+ - FRC_PLL
+ - POSC
+ - POSC_PLL
+ SYSTEM_CLOCK_FRC_DIV:
+ description: FRCDIV value
+ range: 1,2,4,6,8,16,32,64,256
+ value: 1
+ SYSTEM_CLOCK_PLLIDIV:
+ description:
+ range: 1..8
+ value:
+ SYSTEM_CLOCK_PLLRANGE:
+ description:
+ range: 1..5
+ value:
+ SYSTEM_CLOCK_PLLMULT:
+ description:
+ range: 1..128
+ value:
+ SYSTEM_CLOCK_PLLODIV:
+ description:
+ range: 2,4,8,16,32
+ value:
+
+ MCU_NO_BOOTLOADER_BUILD:
+ description: >
+ Set this value to 1 when building elf files that are not
+ converted to img files.
+ value: 0
+syscfg.vals:
Review comment:
done
##########
File path: hw/bsp/olimex-pic32-emz64/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = EC
+#if 1
+#pragma config FNOSC = FRCDIV
+#elif MYNEWT_VAL(CLOCK_FREQ) == 24000000
+#pragma config FNOSC = POSC
+/* 24MHz posc input -> 50mhz*/
+#pragma config FPLLICLK=0
+#elif MYNEWT_VAL(CLOCK_FREQ) == 50000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3 -> 8, multiply by 50 -> 400, div by 8 -> 50mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_8
+#elif MYNEWT_VAL(CLOCK_FREQ) == 100000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 4 -> 100mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_4
+#elif MYNEWT_VAL(CLOCK_FREQ) == 200000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#else
+#error Clock requency not supported
+#endif
+#endif
+/* USB off */
+#pragma config FUSBIDIO=0
+/*
+ * Watchdog in non-window mode, watchdog disabled during flash programming,
+ * period: 32s
+ */
+#pragma config WINDIS=1, WDTSPGM=1, WDTPS=15
+
+#endif
+//uint32_t SystemCoreClock = MYNEWT_VAL(CLOCK_FREQ);
Review comment:
done
##########
File path: hw/bsp/olimex-pic32-hmz144/pkg.yml
##########
@@ -0,0 +1,38 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/olimex-pic32-hmz144
+pkg.type: bsp
+pkg.description: BSP definition for the Olimex PIC32-HMZ144 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFM144
+ - -G6
+pkg.lflags:
+ - "-L@apache-mynewt-core/hw/bsp/olimex-pic32-hmz144"
Review comment:
This one requires some explanation:
linker script allow only one **MEMORY** section and PIC32 has this part very long.
PIC32MZ MCUs differ very little in memory sizes to make part that is different small
I decided to include fragment of MEMORY section in statement `INCLUDE p32mz_app_mem.ld`
but this requires additional **pkg.lflags** to access BSP part of linker script.
In ARM based linker scripts MEMORY section is very short and is added as separate linker script.
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[GitHub] [mynewt-core] utzig commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691135106
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/mips_hal.h
##########
@@ -0,0 +1,63 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the HAL implementations within this MCU */
+
+#ifndef MIPS_HAL_H
+#define MIPS_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_UNUSED 0xFF
+
+/* I/O pins for UART */
+struct mips_uart_cfg {
+ uint8_t tx;
+ uint8_t rx;
+ uint8_t rts;
+ uint8_t cts;
+};
+
+/* I/O pins for SPI, SS pin is not handled by the driver */
+struct mips_spi_cfg {
+ uint8_t mosi;
+ uint8_t miso;
+ uint8_t sck;
+};
+
+/* I/O pins for I2C, also set frequency */
+struct mips_i2c_cfg {
+ uint8_t scl;
+ uint8_t sda;
+ uint32_t frequency;
+};
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MCU_HAL_H */
Review comment:
`/* MIPS_HAL_H */`
##########
File path: compiler/xc32/compiler.yml
##########
@@ -19,18 +19,19 @@
compiler.path.cc: "xc32-gcc"
compiler.path.as: "xc32-gcc"
+compiler.path.cpp: "xc32-g++"
compiler.path.archive: "xc32-ar"
compiler.path.objdump: "xc32-objdump"
compiler.path.objsize: "xc32-size"
compiler.path.objcopy: "xc32-objcopy"
-compiler.flags.base: [-std=gnu11, -msmart-io=0, -fno-common]
+compiler.flags.base: [-std=gnu11, -fno-common, -mnewlib-libc, -ffunction-sections, -fdata-sections]
compiler.flags.default: [compiler.flags.base, -O2, -g3]
-compiler.flags.optimized: [compiler.flags.base, -Os, -g3]
-compiler.flags.debug: [compiler.flags.base, -g3]
+compiler.flags.optimized: [compiler.flags.base, -O2, -g3]
Review comment:
Wouldn't it be better to use `-Os` for optimized (for size!) and `-O2` (or 3) for `compiler.flags.speed` like it's done for ARM?
##########
File path: hw/bsp/olimex-pic32-emz64/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = EC
+#if 1
+#pragma config FNOSC = FRCDIV
+#elif MYNEWT_VAL(CLOCK_FREQ) == 24000000
+#pragma config FNOSC = POSC
+/* 24MHz posc input -> 50mhz*/
+#pragma config FPLLICLK=0
+#elif MYNEWT_VAL(CLOCK_FREQ) == 50000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3 -> 8, multiply by 50 -> 400, div by 8 -> 50mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_8
+#elif MYNEWT_VAL(CLOCK_FREQ) == 100000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 4 -> 100mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_4
+#elif MYNEWT_VAL(CLOCK_FREQ) == 200000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#else
+#error Clock requency not supported
+#endif
+#endif
+/* USB off */
+#pragma config FUSBIDIO=0
+/*
+ * Watchdog in non-window mode, watchdog disabled during flash programming,
+ * period: 32s
+ */
+#pragma config WINDIS=1, WDTSPGM=1, WDTPS=15
+
+#endif
+//uint32_t SystemCoreClock = MYNEWT_VAL(CLOCK_FREQ);
Review comment:
Can be removed?
##########
File path: kernel/os/src/arch/pic32/asm/ctx.S
##########
@@ -90,20 +88,24 @@
sw k0, CTX_EPC(sp)
mfc0 k0, _CP0_BADVADDR
sw k0, CTX_BADVADDR(sp)
+ mfc0 k0, _CP0_CAUSE
+ sw k0, CTX_CAUSE(sp)
+
Review comment:
These instructions are not aligned, or tabs maybe...
##########
File path: hw/bsp/olimex-pic32-emz64/pkg.yml
##########
@@ -0,0 +1,38 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/olimex-pic32-emz64
+pkg.type: bsp
+pkg.description: BSP definition for the Olimex PIC32-EMZ64 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFH064
+ - -G6
+pkg.lflags:
+ - "-L@apache-mynewt-core/hw/bsp/olimex-pic32-emz64"
Review comment:
Same as for the other BSP, not sure why the `-L` is required here.
##########
File path: hw/mcu/microchip/pic32mz/src/hal_timer.c
##########
@@ -0,0 +1,599 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <os/mynewt.h>
+#include <xc.h>
+#include <mcu/pic32.h>
+#include <hal/hal_timer.h>
+#include <mcu/mips_hal.h>
+
+#define PIC32MZ_TIMER_COUNT (8)
+#define PIC32MZ_PRESCALER_COUNT (8)
+
+#define TxCON(T) (base_address[T][0x0 / 0x4])
+#define TxCONCLR(T) (base_address[T][0x4 / 0x4])
+#define TxCONSET(T) (base_address[T][0x8 / 0x4])
+#define TMRx(T) (base_address[T][0x10 / 0x4])
+#define PRx(T) (base_address[T][0x20 / 0x4])
+
+static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = {
+ (volatile uint32_t *)_TMR2_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR3_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR4_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR5_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR6_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR7_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR8_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR9_BASE_ADDRESS
+};
+
+static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] =
+{1, 2, 4, 8, 16, 32, 64, 256};
Review comment:
could align this one column further...
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/pps.h
##########
@@ -0,0 +1,161 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the Periphal Pin Select module within this MCU */
Review comment:
typo: Peripheral
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
Review comment:
missing space `while (`
##########
File path: hw/bsp/olimex-pic32-hmz144/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = HS
+#if 1
Review comment:
This looks a bit like debug stuff!
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
+ if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
+ return -1;
+ }
+
+ mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ assert(uarts[port].u_pins->rts != PIN_UNUSED);
+ mode |= ((uarts[port].u_pins->cts != PIN_UNUSED) ? 2 : 1) << _U1MODE_UEN0_POSITION;
+ }
+ uarts[port].u_rx_stall = 0;
+
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ if (databits == 9) {
+ mode |= _U1MODE_PDSEL_MASK;
+ }
+ break;
+ case HAL_UART_PARITY_ODD:
+ if (databits == 9) { // PIC does not do 9 bit data + parity.
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL1_MASK;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ if (databits == 9) {
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL0_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ /* Configure TX/RX pins */
+ if (uarts[port].u_pins) {
+ ret = 0;
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U1TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U1RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U1RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U1CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U2TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U2RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U2RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U2CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U3TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U3RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U3RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U3CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U4TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U4RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U4RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U4CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U5TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U5RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U5RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U5CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U6TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U6RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U6RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U6CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+ default:
+ return -1;
+ }
+ if (ret) {
+ return -1;
+ }
+ }
+
+ /* Set pin as digital input to clear ANSEL bit if any */
+ hal_gpio_init_in(uarts[port].u_pins->rx, HAL_GPIO_PULL_NONE);
+
+ divisor = peripheral_clk / (4 * baudrate) - 1;
+
+ /* disable */
+ UxMODE(port) = 0;
+ _nop();
+ UxBRG(port) = divisor;
+ UxMODE(port) = mode;
+ UxSTA(port) = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
+
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ /* clear RX interrupt flag */
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC3SET = _IEC3_U1RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC28CLR = _IPC28_U1RXIP_MASK;
+ IPC28SET = (1 << _IPC28_U1RXIP_POSITION); // priority 1
Review comment:
The section below uses line comments which ain't really part of our coding style (I am totally fine with it myself)...
##########
File path: hw/bsp/olimex-pic32-hmz144/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = HS
+#if 1
+#pragma config FNOSC = FRCDIV
+#elif MYNEWT_VAL(CLOCK_FREQ) == 24000000
+#pragma config FNOSC = POSC
+/* 24MHz posc input -> 50mhz*/
+#pragma config FPLLICLK=0
+#elif MYNEWT_VAL(CLOCK_FREQ) == 50000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3 -> 8, multiply by 50 -> 400, div by 8 -> 50mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_8
+#elif MYNEWT_VAL(CLOCK_FREQ) == 100000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 4 -> 100mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_4
+#elif MYNEWT_VAL(CLOCK_FREQ) == 200000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#else
+#error Clock requency not supported
+#endif
+#endif
+/* USB off */
+#pragma config FUSBIDIO=0
+/*
+ * Watchdog in non-window mode, watchdog disabled during flash programming,
+ * period: 32s
+ */
+#pragma config WINDIS=1, WDTSPGM=1, WDTPS=15
+
+#endif
+//uint32_t SystemCoreClock = MYNEWT_VAL(CLOCK_FREQ);
Review comment:
Shouldn't this be removed?
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
Review comment:
should be `/* check input */`
##########
File path: hw/mcu/microchip/pic32mz/syscfg.yml
##########
@@ -0,0 +1,279 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ MCU_FLASH_MIN_WRITE_SIZE:
+ description: >
+ Specifies the required alignment for internal flash writes.
+ Used internally by the newt tool.
+ value: 4
+ I2C_0:
+ description: 'I2C interface 0'
+ value: 0
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_1:
+ description: 'I2C interface 1'
+ value: 0
+ I2C_1_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_2:
+ description: 'I2C interface 2'
+ value: 0
+ I2C_2_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_3:
+ description: 'I2C interface 3'
+ value: 0
+ I2C_3_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_4:
+ description: 'I2C interface 4'
+ value: 0
+ I2C_4_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
+ SPI_0_MASTER:
+ description: 'SPI 0 master'
+ value: 0
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 0xFF
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 0xFF
+ SPI_1_MASTER:
+ description: 'SPI 1 master'
+ value: 0
+ SPI_1_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 0xFF
+ SPI_1_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 0xFF
+ SPI_2_MASTER:
+ description: 'SPI 2 master'
+ value: 0
+ SPI_2_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 0xFF
+ SPI_2_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 0xFF
+ SPI_3_MASTER:
+ description: 'SPI 3 master'
+ value: 0
+ SPI_3_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 0xFF
+ SPI_3_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 0xFF
+ SPI_4_MASTER:
+ description: 'SPI 4 master'
+ value: 0
+ SPI_4_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 0xFF
+ SPI_4_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 0xFF
+ SPI_5_MASTER:
+ description: 'SPI 5 master'
+ value: 0
+ SPI_5_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 0xFF
+ SPI_5_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 0xFF
+
+ UART_0:
+ description: Enable UART_0 (Datasheet peripheral name UART1)
+ value: 0
+ UART_0_PIN_TX:
+ description: 'TX pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_RX:
+ description: 'RX pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_RTS:
+ description: 'RTS pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_CTS:
+ description: 'CTS pin for UART_0'
+ value: 0xFF
+
+ UART_1:
+ description: Enable UART_1 (Datasheet peripheral name UART2)
+ value: 0
+ UART_1_PIN_TX:
+ description: 'TX pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_RX:
+ description: 'RX pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_RTS:
+ description: 'RTS pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_CTS:
+ description: 'CTS pin for UART_1'
+ value: 0xFF
+
+ UART_2:
+ description: Enable UART_2 (Datasheet peripheral name UART3)
+ value: 0
+ UART_2_PIN_TX:
+ description: 'TX pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_RX:
+ description: 'RX pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_RTS:
+ description: 'RTS pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_CTS:
+ description: 'CTS pin for UART_2'
+ value: 0xFF
+
+ UART_3:
+ description: Enable UART_4 (Datasheet peripheral name UART4)
+ value: 0
+ UART_3_PIN_TX:
+ description: 'TX pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_RX:
+ description: 'RX pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_RTS:
+ description: 'RTS pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_CTS:
+ description: 'CTS pin for UART_3'
+ value: 0xFF
+
+ UART_4:
+ description: Enable UART_4 (Datasheet peripheral name UART5)
+ value: 0
+ UART_4_PIN_TX:
+ description: 'TX pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_RX:
+ description: 'RX pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_RTS:
+ description: 'RTS pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_CTS:
+ description: 'CTS pin for UART_4'
+ value: 0xFF
+
+ UART_5:
+ description: Enable UART_5 (Datasheet peripheral name UART6)
+ value: 0
+ UART_5_PIN_TX:
+ description: 'TX pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_RX:
+ description: 'RX pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_RTS:
+ description: 'RTS pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_CTS:
+ description: 'CTS pin for UART_5'
+ value: 0xFF
+
+ TIMER_0:
+ description: "Whether to enable Timer 0"
+ value: 1
+
+ TIMER_1:
+ description: "Whether to enable Timer 1"
+ value: 0
+
+ TIMER_2:
+ description: "Whether to enable Timer 2"
+ value: 0
+
+ TIMER_3:
+ description: "Whether to enable Timer 3"
+ value: 0
+
+ TIMER_4:
+ description: "Whether to enable Timer 4"
+ value: 0
+
+ TIMER_5:
+ description: "Whether to enable Timer 5"
+ value: 0
+
+ TIMER_6:
+ description: "Whether to enable Timer 6"
+ value: 0
+
+ TIMER_7:
+ description: "Whether to enable Timer 7"
+ value: 0
+
+ SYSTEM_CLOCK_OSC_FREQ:
+ descriprion: HS Oscilator/External clock freqency.
+ value:
+ SYSTEM_CLOCK_SRC:
+ description: >
+ Select system clock source, that will affect both CONFIG registers
+ and startup code.
+ value:
+ choices:
+ - FRC_DIV
+ - FRC_PLL
+ - POSC
+ - POSC_PLL
+ SYSTEM_CLOCK_FRC_DIV:
+ description: FRCDIV value
+ range: 1,2,4,6,8,16,32,64,256
+ value: 1
+ SYSTEM_CLOCK_PLLIDIV:
+ description:
+ range: 1..8
+ value:
+ SYSTEM_CLOCK_PLLRANGE:
+ description:
+ range: 1..5
+ value:
+ SYSTEM_CLOCK_PLLMULT:
+ description:
+ range: 1..128
+ value:
+ SYSTEM_CLOCK_PLLODIV:
+ description:
+ range: 2,4,8,16,32
+ value:
+
+ MCU_NO_BOOTLOADER_BUILD:
+ description: >
+ Set this value to 1 when building elf files that are not
+ converted to img files.
+ value: 0
+syscfg.vals:
Review comment:
Could add an empty line above...
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/mips_bsp.h
##########
@@ -0,0 +1,24 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_MIPS_BSP_
+#define H_MIPS_BSP_
+
+extern const struct hal_flash pic32mz_flash_dev;
+
+#endif /* H_NATIVE_BSP_ */
Review comment:
The comment should be `HW_MIPS_BSP_`
##########
File path: hw/bsp/olimex-pic32-hmz144/pkg.yml
##########
@@ -0,0 +1,38 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/olimex-pic32-hmz144
+pkg.type: bsp
+pkg.description: BSP definition for the Olimex PIC32-HMZ144 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFM144
+ - -G6
+pkg.lflags:
+ - "-L@apache-mynewt-core/hw/bsp/olimex-pic32-hmz144"
Review comment:
Weird, why does the BSP home have to be manually added here?
##########
File path: hw/mcu/microchip/pic32mz/src/pic32mz_periph.c
##########
@@ -0,0 +1,382 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+
+#include <os/mynewt.h>
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_i2c.h>
+#include <hal/hal_timer.h>
+#include <hal/hal_spi.h>
+#include <uart/uart.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <uart_hal/uart_hal.h>
+#include <bsp/bsp.h>
+
+static struct uart_dev uart_0_dev;
+static struct uart_dev uart_1_dev;
+static struct uart_dev uart_2_dev;
+static struct uart_dev uart_3_dev;
+static struct uart_dev uart_4_dev;
+static struct uart_dev uart_5_dev;
+
+static const struct mips_uart_cfg uart_0_cfg = {
+ .tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_1_cfg = {
+ .tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_1_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_2_cfg = {
+ .tx = MYNEWT_VAL(UART_2_PIN_TX),
+ .rx = MYNEWT_VAL(UART_2_PIN_RX),
+ .rts = MYNEWT_VAL(UART_2_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_2_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_3_cfg = {
+ .tx = MYNEWT_VAL(UART_3_PIN_TX),
+ .rx = MYNEWT_VAL(UART_3_PIN_RX),
+ .rts = MYNEWT_VAL(UART_3_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_3_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_4_cfg = {
+ .tx = MYNEWT_VAL(UART_4_PIN_TX),
+ .rx = MYNEWT_VAL(UART_4_PIN_RX),
+ .rts = MYNEWT_VAL(UART_4_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_4_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_5_cfg = {
+ .tx = MYNEWT_VAL(UART_5_PIN_TX),
+ .rx = MYNEWT_VAL(UART_5_PIN_RX),
+ .rts = MYNEWT_VAL(UART_5_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_5_PIN_CTS),
+};
+
+/*
+ * SPI_0
+ * SCK1 -> RD1
+ */
+static const struct mips_spi_cfg spi_0_cfg = {
+ .mosi = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(1),
+};
+
+/*
+ * SPI_1
+ * SCK2 -> RG6
+ */
+static const struct mips_spi_cfg spi_1_cfg = {
+ .mosi = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTG(6),
+};
+
+/*
+ * SPI_2
+ * SCK3 -> B14
+ */
+static const struct mips_spi_cfg spi_2_cfg = {
+ .mosi = MYNEWT_VAL(SPI_2_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_2_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTB(14),
+};
+
+/*
+ * SPI_3
+ * SCK4 -> RD10
+ */
+static const struct mips_spi_cfg spi_3_cfg = {
+ .mosi = MYNEWT_VAL(SPI_3_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_3_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(10),
+};
+
+#ifdef _SPI5_BASE_ADDRESS
+/*
+ * SPI_4
+ * SCK5 -> RF13
+ */
+static const struct mips_spi_cfg spi_4_cfg = {
+ .mosi = MYNEWT_VAL(SPI_4_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_4_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTF(13),
+};
+#endif
+
+#ifdef _SPI6_BASE_ADDRESS
+/*
+ * SPI_5
+ * SCK6 -> RD15
+ */
+static const struct mips_spi_cfg spi_5_cfg = {
+ .mosi = MYNEWT_VAL(SPI_5_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_5_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(15),
+};
+#endif
+
+/*
+ * I2C_0 -> I2C1
+ * SCL1 -> RA14 (D10 for 64 pin packges)
+ * SDA1 -> RA15 (D9 for 64 pin packges)
+ */
+static const struct mips_i2c_cfg i2c_0_cfg = {
+#if __PIC32_PIN_COUNT > 64
+ .scl = MCU_GPIO_PORTA(14),
+ .sda = MCU_GPIO_PORTA(15),
+#else
+ .scl = MCU_GPIO_PORTD(10),
+ .sda = MCU_GPIO_PORTD(9),
+#endif
+ .frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ) * 1000,
+};
+
+#ifdef _I2C2_BASE_ADDRESS
+/*
+ * I2C_1 -> I2C2
+ * SCL2 -> RA2
+ * SDA2 -> RA3
+ */
+static const struct mips_i2c_cfg i2c_1_cfg = {
+ .scl = MCU_GPIO_PORTA(2),
+ .sda = MCU_GPIO_PORTA(3),
+ .frequency = MYNEWT_VAL(I2C_1_FREQ_KHZ) * 1000,
+};
+#endif
+
+/*
+ * I2C_2 -> I2C3
+ * SCL3 -> RF8 (D3 for 64 pin packges)
+ * SDA3 -> RF2 (D2 for 64 pin packges)
+ */
+static const struct mips_i2c_cfg i2c_2_cfg = {
+#if __PIC32_PIN_COUNT > 64
+ .scl = MCU_GPIO_PORTF(8),
+ .sda = MCU_GPIO_PORTF(2),
+#else
+ .scl = MCU_GPIO_PORTD(3),
+ .sda = MCU_GPIO_PORTD(2),
+#endif
+ .frequency = MYNEWT_VAL(I2C_2_FREQ_KHZ) * 1000,
+};
+
+/*
+ * I2C_3 -> I2C4
+ * SCL4 -> RG8
+ * SDA4 -> RG7
+ */
+static const struct mips_i2c_cfg i2c_3_cfg = {
+ .scl = MCU_GPIO_PORTG(8),
+ .sda = MCU_GPIO_PORTG(7),
+ .frequency = MYNEWT_VAL(I2C_3_FREQ_KHZ) * 1000,
+};
+
+/*
+ * I2C_4 -> I2C5
+ * SCL5 -> RF5
+ * SDA5 -> RF4
+ */
+static const struct mips_i2c_cfg i2c_4_cfg = {
+ .scl = MCU_GPIO_PORTF(5),
+ .sda = MCU_GPIO_PORTF(4),
+ .frequency = MYNEWT_VAL(I2C_4_FREQ_KHZ) * 1000,
+};
+
+static void
+pic32mz_periph_create_timer_devs(void)
+{
+ int rc;
+
+ if (MYNEWT_VAL(TIMER_0)) {
Review comment:
Does this deviate from the usual `#if MYNEWT_VAL(x)` style on purpose?
##########
File path: hw/bsp/olimex-pic32-emz64/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = EC
+#if 1
Review comment:
For debug?
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[GitHub] [mynewt-core] kasjer merged pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
kasjer merged pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662
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[GitHub] [mynewt-core] kasjer commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
kasjer commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691476943
##########
File path: hw/bsp/olimex-pic32-hmz144/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = HS
+#if 1
Review comment:
it is, eagle eye, fixed
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[GitHub] [mynewt-core] utzig commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691135106
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/mips_hal.h
##########
@@ -0,0 +1,63 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the HAL implementations within this MCU */
+
+#ifndef MIPS_HAL_H
+#define MIPS_HAL_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PIN_UNUSED 0xFF
+
+/* I/O pins for UART */
+struct mips_uart_cfg {
+ uint8_t tx;
+ uint8_t rx;
+ uint8_t rts;
+ uint8_t cts;
+};
+
+/* I/O pins for SPI, SS pin is not handled by the driver */
+struct mips_spi_cfg {
+ uint8_t mosi;
+ uint8_t miso;
+ uint8_t sck;
+};
+
+/* I/O pins for I2C, also set frequency */
+struct mips_i2c_cfg {
+ uint8_t scl;
+ uint8_t sda;
+ uint32_t frequency;
+};
+
+/* Helper functions to enable/disable interrupts. */
+#define __HAL_DISABLE_INTERRUPTS(__os_sr) do {__os_sr = __builtin_get_isr_state(); \
+ __builtin_disable_interrupts();} while(0)
+
+#define __HAL_ENABLE_INTERRUPTS(__os_sr) __builtin_set_isr_state(__os_sr)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MCU_HAL_H */
Review comment:
`/* MIPS_HAL_H */`
##########
File path: compiler/xc32/compiler.yml
##########
@@ -19,18 +19,19 @@
compiler.path.cc: "xc32-gcc"
compiler.path.as: "xc32-gcc"
+compiler.path.cpp: "xc32-g++"
compiler.path.archive: "xc32-ar"
compiler.path.objdump: "xc32-objdump"
compiler.path.objsize: "xc32-size"
compiler.path.objcopy: "xc32-objcopy"
-compiler.flags.base: [-std=gnu11, -msmart-io=0, -fno-common]
+compiler.flags.base: [-std=gnu11, -fno-common, -mnewlib-libc, -ffunction-sections, -fdata-sections]
compiler.flags.default: [compiler.flags.base, -O2, -g3]
-compiler.flags.optimized: [compiler.flags.base, -Os, -g3]
-compiler.flags.debug: [compiler.flags.base, -g3]
+compiler.flags.optimized: [compiler.flags.base, -O2, -g3]
Review comment:
Wouldn't it be better to use `-Os` for optimized (for size!) and `-O2` (or 3) for `compiler.flags.speed` like it's done for ARM?
##########
File path: hw/bsp/olimex-pic32-emz64/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = EC
+#if 1
+#pragma config FNOSC = FRCDIV
+#elif MYNEWT_VAL(CLOCK_FREQ) == 24000000
+#pragma config FNOSC = POSC
+/* 24MHz posc input -> 50mhz*/
+#pragma config FPLLICLK=0
+#elif MYNEWT_VAL(CLOCK_FREQ) == 50000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3 -> 8, multiply by 50 -> 400, div by 8 -> 50mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_8
+#elif MYNEWT_VAL(CLOCK_FREQ) == 100000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 4 -> 100mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_4
+#elif MYNEWT_VAL(CLOCK_FREQ) == 200000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#else
+#error Clock requency not supported
+#endif
+#endif
+/* USB off */
+#pragma config FUSBIDIO=0
+/*
+ * Watchdog in non-window mode, watchdog disabled during flash programming,
+ * period: 32s
+ */
+#pragma config WINDIS=1, WDTSPGM=1, WDTPS=15
+
+#endif
+//uint32_t SystemCoreClock = MYNEWT_VAL(CLOCK_FREQ);
Review comment:
Can be removed?
##########
File path: kernel/os/src/arch/pic32/asm/ctx.S
##########
@@ -90,20 +88,24 @@
sw k0, CTX_EPC(sp)
mfc0 k0, _CP0_BADVADDR
sw k0, CTX_BADVADDR(sp)
+ mfc0 k0, _CP0_CAUSE
+ sw k0, CTX_CAUSE(sp)
+
Review comment:
These instructions are not aligned, or tabs maybe...
##########
File path: hw/bsp/olimex-pic32-emz64/pkg.yml
##########
@@ -0,0 +1,38 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/olimex-pic32-emz64
+pkg.type: bsp
+pkg.description: BSP definition for the Olimex PIC32-EMZ64 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFH064
+ - -G6
+pkg.lflags:
+ - "-L@apache-mynewt-core/hw/bsp/olimex-pic32-emz64"
Review comment:
Same as for the other BSP, not sure why the `-L` is required here.
##########
File path: hw/mcu/microchip/pic32mz/src/hal_timer.c
##########
@@ -0,0 +1,599 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <os/mynewt.h>
+#include <xc.h>
+#include <mcu/pic32.h>
+#include <hal/hal_timer.h>
+#include <mcu/mips_hal.h>
+
+#define PIC32MZ_TIMER_COUNT (8)
+#define PIC32MZ_PRESCALER_COUNT (8)
+
+#define TxCON(T) (base_address[T][0x0 / 0x4])
+#define TxCONCLR(T) (base_address[T][0x4 / 0x4])
+#define TxCONSET(T) (base_address[T][0x8 / 0x4])
+#define TMRx(T) (base_address[T][0x10 / 0x4])
+#define PRx(T) (base_address[T][0x20 / 0x4])
+
+static volatile uint32_t * base_address[PIC32MZ_TIMER_COUNT] = {
+ (volatile uint32_t *)_TMR2_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR3_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR4_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR5_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR6_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR7_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR8_BASE_ADDRESS,
+ (volatile uint32_t *)_TMR9_BASE_ADDRESS
+};
+
+static uint32_t timer_prescalers[PIC32MZ_PRESCALER_COUNT] =
+{1, 2, 4, 8, 16, 32, 64, 256};
Review comment:
could align this one column further...
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/pps.h
##########
@@ -0,0 +1,161 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+/* This file defines the Periphal Pin Select module within this MCU */
Review comment:
typo: Peripheral
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
Review comment:
missing space `while (`
##########
File path: hw/bsp/olimex-pic32-hmz144/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = HS
+#if 1
Review comment:
This looks a bit like debug stuff!
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
+ if ((databits < 8) || (databits > 9) || (stopbits < 1) || (stopbits > 2)) {
+ return -1;
+ }
+
+ mode = _U1MODE_BRGH_MASK | (stopbits >> 1);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ assert(uarts[port].u_pins->rts != PIN_UNUSED);
+ mode |= ((uarts[port].u_pins->cts != PIN_UNUSED) ? 2 : 1) << _U1MODE_UEN0_POSITION;
+ }
+ uarts[port].u_rx_stall = 0;
+
+ switch (parity) {
+ case HAL_UART_PARITY_NONE:
+ if (databits == 9) {
+ mode |= _U1MODE_PDSEL_MASK;
+ }
+ break;
+ case HAL_UART_PARITY_ODD:
+ if (databits == 9) { // PIC does not do 9 bit data + parity.
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL1_MASK;
+ break;
+ case HAL_UART_PARITY_EVEN:
+ if (databits == 9) {
+ return -1;
+ }
+ mode |= _U1MODE_PDSEL0_MASK;
+ break;
+ default:
+ return -1;
+ }
+
+ /* Configure TX/RX pins */
+ if (uarts[port].u_pins) {
+ ret = 0;
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U1TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U1RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U1RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U1CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U2TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U2RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U2RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U2CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U3TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U3RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U3RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U3CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U4TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U4RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U4RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U4CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U5TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U5RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U5RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U5CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ ret += pps_configure_output(uarts[port].u_pins->tx, U6TX_OUT_FUNC);
+ ret += pps_configure_input(uarts[port].u_pins->rx, U6RX_IN_FUNC);
+ if (flow_ctl == HAL_UART_FLOW_CTL_RTS_CTS) {
+ ret += pps_configure_output(uarts[port].u_pins->rts, U6RTS_OUT_FUNC);
+ if (uarts[port].u_pins->cts != PIN_UNUSED) {
+ ret += pps_configure_input(uarts[port].u_pins->cts, U6CTS_IN_FUNC);
+ }
+ }
+ break;
+#endif
+ default:
+ return -1;
+ }
+ if (ret) {
+ return -1;
+ }
+ }
+
+ /* Set pin as digital input to clear ANSEL bit if any */
+ hal_gpio_init_in(uarts[port].u_pins->rx, HAL_GPIO_PULL_NONE);
+
+ divisor = peripheral_clk / (4 * baudrate) - 1;
+
+ /* disable */
+ UxMODE(port) = 0;
+ _nop();
+ UxBRG(port) = divisor;
+ UxMODE(port) = mode;
+ UxSTA(port) = _U1STA_URXEN_MASK | _U1STA_UTXEN_MASK;
+
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ /* clear RX interrupt flag */
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+
+ /* enable RX interrupt */
+ IEC3SET = _IEC3_U1RXIE_MASK;
+
+ /* set rx interrupt priority */
+ IPC28CLR = _IPC28_U1RXIP_MASK;
+ IPC28SET = (1 << _IPC28_U1RXIP_POSITION); // priority 1
Review comment:
The section below uses line comments which ain't really part of our coding style (I am totally fine with it myself)...
##########
File path: hw/bsp/olimex-pic32-hmz144/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = HS
+#if 1
+#pragma config FNOSC = FRCDIV
+#elif MYNEWT_VAL(CLOCK_FREQ) == 24000000
+#pragma config FNOSC = POSC
+/* 24MHz posc input -> 50mhz*/
+#pragma config FPLLICLK=0
+#elif MYNEWT_VAL(CLOCK_FREQ) == 50000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3 -> 8, multiply by 50 -> 400, div by 8 -> 50mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_8
+#elif MYNEWT_VAL(CLOCK_FREQ) == 100000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 4 -> 100mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_4
+#elif MYNEWT_VAL(CLOCK_FREQ) == 200000000
+#pragma config FNOSC = SPLL
+/* 24MHz posc input to pll, div by 3, multiply by 50, div by 2 -> 200mhz*/
+#pragma config FPLLICLK=0, FPLLIDIV=DIV_3, FPLLRNG=RANGE_5_10_MHZ, FPLLMULT=MUL_50, FPLLODIV=DIV_2
+#else
+#error Clock requency not supported
+#endif
+#endif
+/* USB off */
+#pragma config FUSBIDIO=0
+/*
+ * Watchdog in non-window mode, watchdog disabled during flash programming,
+ * period: 32s
+ */
+#pragma config WINDIS=1, WDTSPGM=1, WDTPS=15
+
+#endif
+//uint32_t SystemCoreClock = MYNEWT_VAL(CLOCK_FREQ);
Review comment:
Shouldn't this be removed?
##########
File path: hw/mcu/microchip/pic32mz/src/hal_uart.c
##########
@@ -0,0 +1,736 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <os/mynewt.h>
+#include <bsp/bsp.h>
+#include <hal/hal_gpio.h>
+#include <hal/hal_uart.h>
+#include <mcu/pps.h>
+#include <mcu/pic32.h>
+#include <mcu/mips_hal.h>
+
+#include <xc.h>
+
+#define UxMODE(U) (base_address[U][0x0 / 0x4])
+#define UxMODESET(U) (base_address[U][0x8 / 0x4])
+#define UxSTA(U) (base_address[U][0x10 / 0x4])
+#define UxTXREG(U) (base_address[U][0x20 / 0x4])
+#define UxRXREG(U) (base_address[U][0x30 / 0x4])
+#define UxBRG(U) (base_address[U][0x40 / 0x4])
+
+static volatile uint32_t* base_address[UART_CNT] = {
+ (volatile uint32_t *)_UART1_BASE_ADDRESS,
+ (volatile uint32_t *)_UART2_BASE_ADDRESS,
+ (volatile uint32_t *)_UART3_BASE_ADDRESS,
+ (volatile uint32_t *)_UART4_BASE_ADDRESS,
+ (volatile uint32_t *)_UART5_BASE_ADDRESS,
+ (volatile uint32_t *)_UART6_BASE_ADDRESS
+};
+
+struct hal_uart {
+ volatile uint8_t u_rx_stall:1;
+ volatile uint8_t u_rx_data;
+ hal_uart_rx_char u_rx_func;
+ hal_uart_tx_char u_tx_func;
+ hal_uart_tx_done u_tx_done;
+ void *u_func_arg;
+ const struct mips_uart_cfg *u_pins;
+};
+static struct hal_uart uarts[UART_CNT];
+
+int
+hal_uart_init_cbs(int port, hal_uart_tx_char tx_func, hal_uart_tx_done tx_done,
+ hal_uart_rx_char rx_func, void *arg)
+{
+ uarts[port].u_rx_func = rx_func;
+ uarts[port].u_tx_func = tx_func;
+ uarts[port].u_tx_done = tx_done;
+ uarts[port].u_func_arg = arg;
+ return 0;
+}
+
+static void
+uart_disable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_tx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5TXIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6TXIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_disable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3CLR = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4CLR = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4CLR = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5CLR = _IEC5_U4RXIE_MASK; // | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5CLR = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5CLR = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+static void
+uart_enable_rx_int(int port)
+{
+ switch (port) {
+#if MYNEWT_VAL(UART_0)
+ case 0:
+ IEC3SET = _IEC3_U1RXIE_MASK | _IEC3_U1EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_1)
+ case 1:
+ IEC4SET = _IEC4_U2RXIE_MASK | _IEC4_U2EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_2)
+ case 2:
+ IEC4SET = _IEC4_U3RXIE_MASK | _IEC4_U3EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_3)
+ case 3:
+ IEC5SET = _IEC5_U4RXIE_MASK | _IEC5_U4EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_4)
+ case 4:
+ IEC5SET = _IEC5_U5RXIE_MASK | _IEC5_U5EIE_MASK;
+ break;
+#endif
+#if MYNEWT_VAL(UART_5)
+ case 5:
+ IEC5SET = _IEC5_U6RXIE_MASK | _IEC5_U6EIE_MASK;
+ break;
+#endif
+ }
+}
+
+uint32_t rx_times[256];
+uint8_t rx_times_ix;
+
+static void
+uart_receive_ready(int port)
+{
+ int c;
+
+ rx_times[++rx_times_ix] = _CP0_GET_COUNT();
+ while (UxSTA(port) & _U1STA_URXDA_MASK) {
+ uarts[port].u_rx_data = UxRXREG(port);
+
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c < 0) {
+ uart_disable_rx_int(port);
+ uarts[port].u_rx_stall = 1;
+ break;
+ }
+ }
+}
+
+static void
+uart_transmit_ready(int port)
+{
+ int c;
+
+ while(!(UxSTA(port) & _U1STA_UTXBF_MASK)) {
+ c = uarts[port].u_tx_func(uarts[port].u_func_arg);
+ if (c < 0) {
+ uart_disable_tx_int(port);
+
+ /* call tx done cb */
+ if (uarts[port].u_tx_done) {
+ uarts[port].u_tx_done(uarts[port].u_func_arg);
+ }
+ break;
+ }
+
+ UxTXREG(port) = (uint32_t)c & 0xff;
+ }
+}
+
+#if MYNEWT_VAL(UART_0)
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART1_FAULT_VECTOR), no_fpu)) uart_1_fault_isr(void)
+{
+ IFS3CLR = _IFS3_U1EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_RX_VECTOR), no_fpu)) uart_1_rx_isr(void)
+{
+ uart_receive_ready(0);
+ IFS3CLR = _IFS3_U1RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART1_TX_VECTOR), no_fpu)) uart_1_tx_isr(void)
+{
+ uart_transmit_ready(0);
+ IFS3CLR = _IFS3_U1TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_1)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_FAULT_VECTOR), no_fpu)) uart_2_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U2EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART2_RX_VECTOR), no_fpu)) uart_2_rx_isr(void)
+{
+ uart_receive_ready(1);
+ IFS4CLR = _IFS4_U2RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART2_TX_VECTOR), no_fpu)) uart_2_tx_isr(void)
+{
+ uart_transmit_ready(1);
+ IFS4CLR = _IFS4_U2TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_2)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_FAULT_VECTOR), no_fpu)) uart_3_fault_isr(void)
+{
+ IFS4CLR = _IFS4_U3EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART3_RX_VECTOR), no_fpu)) uart_3_rx_isr(void)
+{
+ uart_receive_ready(2);
+ IFS4CLR = _IFS4_U3RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART3_TX_VECTOR), no_fpu)) uart_3_tx_isr(void)
+{
+ uart_transmit_ready(2);
+ IFS4CLR = _IFS4_U3TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_3)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_FAULT_VECTOR), no_fpu)) uart_4_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U4EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART4_RX_VECTOR), no_fpu)) uart_4_rx_isr(void)
+{
+ uart_receive_ready(3);
+ IFS5CLR = _IFS5_U4RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART4_TX_VECTOR), no_fpu)) uart_4_tx_isr(void)
+{
+ uart_transmit_ready(3);
+ IFS5CLR = _IFS5_U4TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_4)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_FAULT_VECTOR), no_fpu)) uart_5_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U5EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART5_RX_VECTOR), no_fpu)) uart_5_rx_isr(void)
+{
+ uart_receive_ready(4);
+ IFS5CLR = _IFS5_U5RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART5_TX_VECTOR), no_fpu)) uart_5_tx_isr(void)
+{
+ uart_transmit_ready(4);
+ IFS5CLR = _IFS5_U5TXIF_MASK;
+}
+#endif
+
+#if MYNEWT_VAL(UART_5)
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_FAULT_VECTOR), no_fpu)) uart_6_fault_isr(void)
+{
+ IFS5CLR = _IFS5_U6EIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL1AUTO), vector(_UART6_RX_VECTOR), no_fpu)) uart_6_rx_isr(void)
+{
+ uart_receive_ready(5);
+ IFS5CLR = _IFS5_U6RXIF_MASK;
+}
+
+void
+__attribute__((interrupt(IPL2AUTO), vector(_UART6_TX_VECTOR), no_fpu)) uart_6_tx_isr(void)
+{
+ uart_transmit_ready(5);
+ IFS5CLR = _IFS5_U6TXIF_MASK;
+}
+#endif
+
+void
+hal_uart_start_rx(int port)
+{
+ uint32_t sr;
+ int c;
+
+ if (uarts[port].u_rx_stall) {
+ /* recover saved data */
+ __HAL_DISABLE_INTERRUPTS(sr);
+ c = uarts[port].u_rx_func(uarts[port].u_func_arg,
+ uarts[port].u_rx_data);
+ if (c >= 0) {
+ uarts[port].u_rx_stall = 0;
+ uart_enable_rx_int(port);
+ }
+ __HAL_ENABLE_INTERRUPTS(sr);
+ }
+}
+
+void
+hal_uart_start_tx(int port)
+{
+ uart_enable_tx_int(port);
+}
+
+void
+hal_uart_blocking_tx(int port, uint8_t data)
+{
+ /* wait for transmit holding register to be empty */
+ while(!(UxSTA(port) & _U1STA_TRMT_MASK)) {
+ }
+
+ UxTXREG(port) = data;
+}
+
+int
+hal_uart_init(int port, void *arg)
+{
+ if (port >= UART_CNT) {
+ return -1;
+ }
+
+ uarts[port].u_pins = arg;
+
+ return 0;
+}
+
+int
+hal_uart_config(int port, int32_t baudrate, uint8_t databits, uint8_t stopbits,
+ enum hal_uart_parity parity, enum hal_uart_flow_ctl flow_ctl)
+{
+ uint16_t divisor;
+ uint32_t peripheral_clk = SystemCoreClock / ((PB2DIV & _PB2DIV_PBDIV_MASK) + 1);
+ int ret;
+ uint16_t mode;
+
+ // check input
Review comment:
should be `/* check input */`
##########
File path: hw/mcu/microchip/pic32mz/syscfg.yml
##########
@@ -0,0 +1,279 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+syscfg.defs:
+ MCU_FLASH_MIN_WRITE_SIZE:
+ description: >
+ Specifies the required alignment for internal flash writes.
+ Used internally by the newt tool.
+ value: 4
+ I2C_0:
+ description: 'I2C interface 0'
+ value: 0
+ I2C_0_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_1:
+ description: 'I2C interface 1'
+ value: 0
+ I2C_1_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_2:
+ description: 'I2C interface 2'
+ value: 0
+ I2C_2_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_3:
+ description: 'I2C interface 3'
+ value: 0
+ I2C_3_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+ I2C_4:
+ description: 'I2C interface 4'
+ value: 0
+ I2C_4_FREQ_KHZ:
+ description: 'Frequency in khz for I2C_0 bus'
+ value: 100
+
+ SPI_0_MASTER:
+ description: 'SPI 0 master'
+ value: 0
+ SPI_0_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 0xFF
+ SPI_0_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_0_MASTER'
+ value: 0xFF
+ SPI_1_MASTER:
+ description: 'SPI 1 master'
+ value: 0
+ SPI_1_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 0xFF
+ SPI_1_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_1_MASTER'
+ value: 0xFF
+ SPI_2_MASTER:
+ description: 'SPI 2 master'
+ value: 0
+ SPI_2_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 0xFF
+ SPI_2_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_2_MASTER'
+ value: 0xFF
+ SPI_3_MASTER:
+ description: 'SPI 3 master'
+ value: 0
+ SPI_3_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 0xFF
+ SPI_3_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_3_MASTER'
+ value: 0xFF
+ SPI_4_MASTER:
+ description: 'SPI 4 master'
+ value: 0
+ SPI_4_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 0xFF
+ SPI_4_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_4_MASTER'
+ value: 0xFF
+ SPI_5_MASTER:
+ description: 'SPI 5 master'
+ value: 0
+ SPI_5_MASTER_PIN_MOSI:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 0xFF
+ SPI_5_MASTER_PIN_MISO:
+ description: 'MOSI pin for SPI_5_MASTER'
+ value: 0xFF
+
+ UART_0:
+ description: Enable UART_0 (Datasheet peripheral name UART1)
+ value: 0
+ UART_0_PIN_TX:
+ description: 'TX pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_RX:
+ description: 'RX pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_RTS:
+ description: 'RTS pin for UART_0'
+ value: 0xFF
+ UART_0_PIN_CTS:
+ description: 'CTS pin for UART_0'
+ value: 0xFF
+
+ UART_1:
+ description: Enable UART_1 (Datasheet peripheral name UART2)
+ value: 0
+ UART_1_PIN_TX:
+ description: 'TX pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_RX:
+ description: 'RX pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_RTS:
+ description: 'RTS pin for UART_1'
+ value: 0xFF
+ UART_1_PIN_CTS:
+ description: 'CTS pin for UART_1'
+ value: 0xFF
+
+ UART_2:
+ description: Enable UART_2 (Datasheet peripheral name UART3)
+ value: 0
+ UART_2_PIN_TX:
+ description: 'TX pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_RX:
+ description: 'RX pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_RTS:
+ description: 'RTS pin for UART_2'
+ value: 0xFF
+ UART_2_PIN_CTS:
+ description: 'CTS pin for UART_2'
+ value: 0xFF
+
+ UART_3:
+ description: Enable UART_4 (Datasheet peripheral name UART4)
+ value: 0
+ UART_3_PIN_TX:
+ description: 'TX pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_RX:
+ description: 'RX pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_RTS:
+ description: 'RTS pin for UART_3'
+ value: 0xFF
+ UART_3_PIN_CTS:
+ description: 'CTS pin for UART_3'
+ value: 0xFF
+
+ UART_4:
+ description: Enable UART_4 (Datasheet peripheral name UART5)
+ value: 0
+ UART_4_PIN_TX:
+ description: 'TX pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_RX:
+ description: 'RX pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_RTS:
+ description: 'RTS pin for UART_4'
+ value: 0xFF
+ UART_4_PIN_CTS:
+ description: 'CTS pin for UART_4'
+ value: 0xFF
+
+ UART_5:
+ description: Enable UART_5 (Datasheet peripheral name UART6)
+ value: 0
+ UART_5_PIN_TX:
+ description: 'TX pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_RX:
+ description: 'RX pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_RTS:
+ description: 'RTS pin for UART_5'
+ value: 0xFF
+ UART_5_PIN_CTS:
+ description: 'CTS pin for UART_5'
+ value: 0xFF
+
+ TIMER_0:
+ description: "Whether to enable Timer 0"
+ value: 1
+
+ TIMER_1:
+ description: "Whether to enable Timer 1"
+ value: 0
+
+ TIMER_2:
+ description: "Whether to enable Timer 2"
+ value: 0
+
+ TIMER_3:
+ description: "Whether to enable Timer 3"
+ value: 0
+
+ TIMER_4:
+ description: "Whether to enable Timer 4"
+ value: 0
+
+ TIMER_5:
+ description: "Whether to enable Timer 5"
+ value: 0
+
+ TIMER_6:
+ description: "Whether to enable Timer 6"
+ value: 0
+
+ TIMER_7:
+ description: "Whether to enable Timer 7"
+ value: 0
+
+ SYSTEM_CLOCK_OSC_FREQ:
+ descriprion: HS Oscilator/External clock freqency.
+ value:
+ SYSTEM_CLOCK_SRC:
+ description: >
+ Select system clock source, that will affect both CONFIG registers
+ and startup code.
+ value:
+ choices:
+ - FRC_DIV
+ - FRC_PLL
+ - POSC
+ - POSC_PLL
+ SYSTEM_CLOCK_FRC_DIV:
+ description: FRCDIV value
+ range: 1,2,4,6,8,16,32,64,256
+ value: 1
+ SYSTEM_CLOCK_PLLIDIV:
+ description:
+ range: 1..8
+ value:
+ SYSTEM_CLOCK_PLLRANGE:
+ description:
+ range: 1..5
+ value:
+ SYSTEM_CLOCK_PLLMULT:
+ description:
+ range: 1..128
+ value:
+ SYSTEM_CLOCK_PLLODIV:
+ description:
+ range: 2,4,8,16,32
+ value:
+
+ MCU_NO_BOOTLOADER_BUILD:
+ description: >
+ Set this value to 1 when building elf files that are not
+ converted to img files.
+ value: 0
+syscfg.vals:
Review comment:
Could add an empty line above...
##########
File path: hw/mcu/microchip/pic32mz/include/mcu/mips_bsp.h
##########
@@ -0,0 +1,24 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#ifndef H_MIPS_BSP_
+#define H_MIPS_BSP_
+
+extern const struct hal_flash pic32mz_flash_dev;
+
+#endif /* H_NATIVE_BSP_ */
Review comment:
The comment should be `HW_MIPS_BSP_`
##########
File path: hw/bsp/olimex-pic32-hmz144/pkg.yml
##########
@@ -0,0 +1,38 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/olimex-pic32-hmz144
+pkg.type: bsp
+pkg.description: BSP definition for the Olimex PIC32-HMZ144 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFM144
+ - -G6
+pkg.lflags:
+ - "-L@apache-mynewt-core/hw/bsp/olimex-pic32-hmz144"
Review comment:
Weird, why does the BSP home have to be manually added here?
##########
File path: hw/mcu/microchip/pic32mz/src/pic32mz_periph.c
##########
@@ -0,0 +1,382 @@
+/*
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+
+#include <assert.h>
+
+#include <os/mynewt.h>
+
+#include <hal/hal_bsp.h>
+#include <hal/hal_i2c.h>
+#include <hal/hal_timer.h>
+#include <hal/hal_spi.h>
+#include <uart/uart.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <uart_hal/uart_hal.h>
+#include <bsp/bsp.h>
+
+static struct uart_dev uart_0_dev;
+static struct uart_dev uart_1_dev;
+static struct uart_dev uart_2_dev;
+static struct uart_dev uart_3_dev;
+static struct uart_dev uart_4_dev;
+static struct uart_dev uart_5_dev;
+
+static const struct mips_uart_cfg uart_0_cfg = {
+ .tx = MYNEWT_VAL(UART_0_PIN_TX),
+ .rx = MYNEWT_VAL(UART_0_PIN_RX),
+ .rts = MYNEWT_VAL(UART_0_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_0_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_1_cfg = {
+ .tx = MYNEWT_VAL(UART_1_PIN_TX),
+ .rx = MYNEWT_VAL(UART_1_PIN_RX),
+ .rts = MYNEWT_VAL(UART_1_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_1_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_2_cfg = {
+ .tx = MYNEWT_VAL(UART_2_PIN_TX),
+ .rx = MYNEWT_VAL(UART_2_PIN_RX),
+ .rts = MYNEWT_VAL(UART_2_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_2_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_3_cfg = {
+ .tx = MYNEWT_VAL(UART_3_PIN_TX),
+ .rx = MYNEWT_VAL(UART_3_PIN_RX),
+ .rts = MYNEWT_VAL(UART_3_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_3_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_4_cfg = {
+ .tx = MYNEWT_VAL(UART_4_PIN_TX),
+ .rx = MYNEWT_VAL(UART_4_PIN_RX),
+ .rts = MYNEWT_VAL(UART_4_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_4_PIN_CTS),
+};
+
+static const struct mips_uart_cfg uart_5_cfg = {
+ .tx = MYNEWT_VAL(UART_5_PIN_TX),
+ .rx = MYNEWT_VAL(UART_5_PIN_RX),
+ .rts = MYNEWT_VAL(UART_5_PIN_RTS),
+ .cts = MYNEWT_VAL(UART_5_PIN_CTS),
+};
+
+/*
+ * SPI_0
+ * SCK1 -> RD1
+ */
+static const struct mips_spi_cfg spi_0_cfg = {
+ .mosi = MYNEWT_VAL(SPI_0_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_0_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(1),
+};
+
+/*
+ * SPI_1
+ * SCK2 -> RG6
+ */
+static const struct mips_spi_cfg spi_1_cfg = {
+ .mosi = MYNEWT_VAL(SPI_1_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_1_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTG(6),
+};
+
+/*
+ * SPI_2
+ * SCK3 -> B14
+ */
+static const struct mips_spi_cfg spi_2_cfg = {
+ .mosi = MYNEWT_VAL(SPI_2_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_2_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTB(14),
+};
+
+/*
+ * SPI_3
+ * SCK4 -> RD10
+ */
+static const struct mips_spi_cfg spi_3_cfg = {
+ .mosi = MYNEWT_VAL(SPI_3_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_3_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(10),
+};
+
+#ifdef _SPI5_BASE_ADDRESS
+/*
+ * SPI_4
+ * SCK5 -> RF13
+ */
+static const struct mips_spi_cfg spi_4_cfg = {
+ .mosi = MYNEWT_VAL(SPI_4_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_4_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTF(13),
+};
+#endif
+
+#ifdef _SPI6_BASE_ADDRESS
+/*
+ * SPI_5
+ * SCK6 -> RD15
+ */
+static const struct mips_spi_cfg spi_5_cfg = {
+ .mosi = MYNEWT_VAL(SPI_5_MASTER_PIN_MOSI),
+ .miso = MYNEWT_VAL(SPI_5_MASTER_PIN_MISO),
+ .sck = MCU_GPIO_PORTD(15),
+};
+#endif
+
+/*
+ * I2C_0 -> I2C1
+ * SCL1 -> RA14 (D10 for 64 pin packges)
+ * SDA1 -> RA15 (D9 for 64 pin packges)
+ */
+static const struct mips_i2c_cfg i2c_0_cfg = {
+#if __PIC32_PIN_COUNT > 64
+ .scl = MCU_GPIO_PORTA(14),
+ .sda = MCU_GPIO_PORTA(15),
+#else
+ .scl = MCU_GPIO_PORTD(10),
+ .sda = MCU_GPIO_PORTD(9),
+#endif
+ .frequency = MYNEWT_VAL(I2C_0_FREQ_KHZ) * 1000,
+};
+
+#ifdef _I2C2_BASE_ADDRESS
+/*
+ * I2C_1 -> I2C2
+ * SCL2 -> RA2
+ * SDA2 -> RA3
+ */
+static const struct mips_i2c_cfg i2c_1_cfg = {
+ .scl = MCU_GPIO_PORTA(2),
+ .sda = MCU_GPIO_PORTA(3),
+ .frequency = MYNEWT_VAL(I2C_1_FREQ_KHZ) * 1000,
+};
+#endif
+
+/*
+ * I2C_2 -> I2C3
+ * SCL3 -> RF8 (D3 for 64 pin packges)
+ * SDA3 -> RF2 (D2 for 64 pin packges)
+ */
+static const struct mips_i2c_cfg i2c_2_cfg = {
+#if __PIC32_PIN_COUNT > 64
+ .scl = MCU_GPIO_PORTF(8),
+ .sda = MCU_GPIO_PORTF(2),
+#else
+ .scl = MCU_GPIO_PORTD(3),
+ .sda = MCU_GPIO_PORTD(2),
+#endif
+ .frequency = MYNEWT_VAL(I2C_2_FREQ_KHZ) * 1000,
+};
+
+/*
+ * I2C_3 -> I2C4
+ * SCL4 -> RG8
+ * SDA4 -> RG7
+ */
+static const struct mips_i2c_cfg i2c_3_cfg = {
+ .scl = MCU_GPIO_PORTG(8),
+ .sda = MCU_GPIO_PORTG(7),
+ .frequency = MYNEWT_VAL(I2C_3_FREQ_KHZ) * 1000,
+};
+
+/*
+ * I2C_4 -> I2C5
+ * SCL5 -> RF5
+ * SDA5 -> RF4
+ */
+static const struct mips_i2c_cfg i2c_4_cfg = {
+ .scl = MCU_GPIO_PORTF(5),
+ .sda = MCU_GPIO_PORTF(4),
+ .frequency = MYNEWT_VAL(I2C_4_FREQ_KHZ) * 1000,
+};
+
+static void
+pic32mz_periph_create_timer_devs(void)
+{
+ int rc;
+
+ if (MYNEWT_VAL(TIMER_0)) {
Review comment:
Does this deviate from the usual `#if MYNEWT_VAL(x)` style on purpose?
##########
File path: hw/bsp/olimex-pic32-emz64/src/hal_bsp.c
##########
@@ -0,0 +1,157 @@
+/**
+ * Licensed to the Apache Software Foundation (ASF) under one
+ * or more contributor license agreements. See the NOTICE file
+ * distributed with this work for additional information
+ * regarding copyright ownership. The ASF licenses this file
+ * to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance
+ * with the License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing,
+ * software distributed under the License is distributed on an
+ * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+ * KIND, either express or implied. See the License for the
+ * specific language governing permissions and limitations
+ * under the License.
+ */
+#include <assert.h>
+
+#include "os/mynewt.h"
+
+#include <bsp/bsp.h>
+#include <hal/hal_bsp.h>
+#include <mcu/mips_bsp.h>
+#include <mcu/mips_hal.h>
+#include <mcu/pic32mz_periph.h>
+#include <string.h>
+#include <xc.h>
+
+#if MYNEWT_VAL(SPIFLASH)
+#include <spiflash/spiflash.h>
+#endif
+
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_NO_BOOTLOADER_BUILD)
+/* JTAG on, WDT off */
+#pragma config FDMTEN=0, FSOSCEN=0, DMTCNT=1
+#pragma config DEBUG=ON
+#pragma config JTAGEN=OFF
+#pragma config FSLEEP=OFF
+#pragma config TRCEN=OFF
+#pragma config ICESEL=ICS_PGx2
+
+#if MYNEWT_VAL(CLOCK_FREQ) == 8000000
+#pragma config POSCMOD = OFF
+#pragma config FNOSC = FRCDIV
+#pragma config FPLLICLK=0
+#else
+#pragma config POSCMOD = EC
+#if 1
Review comment:
For debug?
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[GitHub] [mynewt-core] utzig commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691452119
##########
File path: hw/bsp/olimex-pic32-hmz144/pkg.yml
##########
@@ -0,0 +1,38 @@
+#
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+#
+
+pkg.name: hw/bsp/olimex-pic32-hmz144
+pkg.type: bsp
+pkg.description: BSP definition for the Olimex PIC32-HMZ144 board.
+pkg.author: "Apache Mynewt <de...@mynewt.apache.org>"
+pkg.homepage: "http://mynewt.apache.org/"
+pkg.keywords:
+ - pic32
+ - microchip
+
+pkg.cflags:
+ - -mprocessor=32MZ2048EFM144
+ - -G6
+pkg.lflags:
+ - "-L@apache-mynewt-core/hw/bsp/olimex-pic32-hmz144"
Review comment:
Makes sense, thanks!
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[GitHub] [mynewt-core] kasjer commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
kasjer commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691460164
##########
File path: compiler/xc32/compiler.yml
##########
@@ -19,18 +19,19 @@
compiler.path.cc: "xc32-gcc"
compiler.path.as: "xc32-gcc"
+compiler.path.cpp: "xc32-g++"
compiler.path.archive: "xc32-ar"
compiler.path.objdump: "xc32-objdump"
compiler.path.objsize: "xc32-size"
compiler.path.objcopy: "xc32-objcopy"
-compiler.flags.base: [-std=gnu11, -msmart-io=0, -fno-common]
+compiler.flags.base: [-std=gnu11, -fno-common, -mnewlib-libc, -ffunction-sections, -fdata-sections]
compiler.flags.default: [compiler.flags.base, -O2, -g3]
-compiler.flags.optimized: [compiler.flags.base, -Os, -g3]
-compiler.flags.debug: [compiler.flags.base, -g3]
+compiler.flags.optimized: [compiler.flags.base, -O2, -g3]
Review comment:
Free compiler from microchip is limited when -Os is selected:
`cc1.exe: note: Disable the option or visit http://www.microchip.com/MPLABXCcompilers to purchase a new MPLAB XC compiler license.
repos/apache-mynewt-core/hw/hal/src/sbrk_sim.c:1:0: warning: Compiler option (Optimize for size) ignored because this feature requires the MPLAB XC32 PRO compiler [enabled by default]
`
To avail this warning -O2 is selected
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[GitHub] [mynewt-core] utzig commented on a change in pull request #2662: pic32 updates and 2 more pic32 BSPs
Posted by GitBox <gi...@apache.org>.
utzig commented on a change in pull request #2662:
URL: https://github.com/apache/mynewt-core/pull/2662#discussion_r691465440
##########
File path: compiler/xc32/compiler.yml
##########
@@ -19,18 +19,19 @@
compiler.path.cc: "xc32-gcc"
compiler.path.as: "xc32-gcc"
+compiler.path.cpp: "xc32-g++"
compiler.path.archive: "xc32-ar"
compiler.path.objdump: "xc32-objdump"
compiler.path.objsize: "xc32-size"
compiler.path.objcopy: "xc32-objcopy"
-compiler.flags.base: [-std=gnu11, -msmart-io=0, -fno-common]
+compiler.flags.base: [-std=gnu11, -fno-common, -mnewlib-libc, -ffunction-sections, -fdata-sections]
compiler.flags.default: [compiler.flags.base, -O2, -g3]
-compiler.flags.optimized: [compiler.flags.base, -Os, -g3]
-compiler.flags.debug: [compiler.flags.base, -g3]
+compiler.flags.optimized: [compiler.flags.base, -O2, -g3]
Review comment:
Oh, sad.
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