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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2023/01/09 19:01:10 UTC

[GitHub] [nuttx] xiaoxiang781216 commented on a diff in pull request #8047: xtensa/esp32: SPI support to configure as R/W/RW mode

xiaoxiang781216 commented on code in PR #8047:
URL: https://github.com/apache/nuttx/pull/8047#discussion_r1065006792


##########
arch/xtensa/src/esp32/Kconfig:
##########
@@ -1158,6 +1158,37 @@ config ESP32_SPI2_MISOPIN
 	default 12
 	range 0 39
 
+choice ESP32_SPI2_MASTER_IO
+	prompt "SPI2 master I/O mode"
+	default ESP32_SPI2_MASTER_IO_RW

Review Comment:
   but the current design allow use select ESP32_SPI2_MASTER_IO_RW and ESP32_SPI2_SLAVE_IO_RW, which looks wrong. You should merge ESP32_SPI2_MASTER_IO_RW and ESP32_SPI2_SLAVE_IO_RW into one choice to avoid the invalid combination.



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