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Posted to commits@nuttx.apache.org by ac...@apache.org on 2020/11/26 21:42:26 UTC
[incubator-nuttx] branch master updated (a59c774 -> d6c2431)
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git.
from a59c774 Documentation: support versioned docs
new baabe5e libs/libc/machine: Remove ARCH_CORTEXM33 dependence from LIBM_ARCH_xxx
new edca49f libc/machine/arm: Use the correct arch Kconfig for variant check
new 74ab69a libs/libc/machine/arm: Rename armv8 to armv8-m
new afb0e33 libc/machine/arch: Support armv8-m relocation
new d6c2431 Fix nxstyle warning
The 5 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
libs/libc/machine/Kconfig | 24 +-
libs/libc/machine/arm/Kconfig | 15 +-
libs/libc/machine/arm/Make.defs | 14 +-
libs/libc/machine/arm/{armv8 => armv8-m}/Kconfig | 4 +-
libs/libc/machine/arm/{armv8 => armv8-m}/Make.defs | 14 +-
.../machine/arm/{armv8 => armv8-m}/arch_ceil.c | 4 +-
.../machine/arm/{armv8 => armv8-m}/arch_ceilf.c | 4 +-
libs/libc/machine/arm/armv8-m/arch_elf.c | 511 +++++++++++++++++++++
.../machine/arm/{armv8 => armv8-m}/arch_floor.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_floorf.c | 4 +-
.../arm/{armv8 => armv8-m}/arch_nearbyint.c | 2 +-
.../arm/{armv8 => armv8-m}/arch_nearbyintf.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_rint.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_rintf.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_round.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_roundf.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_trunc.c | 2 +-
.../machine/arm/{armv8 => armv8-m}/arch_truncf.c | 2 +-
18 files changed, 567 insertions(+), 45 deletions(-)
rename libs/libc/machine/arm/{armv8 => armv8-m}/Kconfig (95%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/Make.defs (91%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_ceil.c (95%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_ceilf.c (95%)
create mode 100644 libs/libc/machine/arm/armv8-m/arch_elf.c
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_floor.c (98%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_floorf.c (95%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_nearbyint.c (97%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_nearbyintf.c (97%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_rint.c (98%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_rintf.c (98%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_round.c (98%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_roundf.c (98%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_trunc.c (98%)
rename libs/libc/machine/arm/{armv8 => armv8-m}/arch_truncf.c (98%)
[incubator-nuttx] 01/05: libs/libc/machine: Remove ARCH_CORTEXM33
dependence from LIBM_ARCH_xxx
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit baabe5e08a2d358ba980812bef4c7a0a673fb0a9
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Thu Nov 26 20:27:27 2020 +0800
libs/libc/machine: Remove ARCH_CORTEXM33 dependence from LIBM_ARCH_xxx
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
libs/libc/machine/Kconfig | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/libs/libc/machine/Kconfig b/libs/libc/machine/Kconfig
index 19163c9..f0f439f 100644
--- a/libs/libc/machine/Kconfig
+++ b/libs/libc/machine/Kconfig
@@ -100,62 +100,62 @@ config LIBC_ARCH_ELF_64BIT
config LIBM_ARCH_CEIL
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_FLOOR
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_NEARBYINT
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_RINT
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_ROUND
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_TRUNC
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_CEILF
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_FLOORF
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_NEARBYINTF
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_RINTF
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_ROUNDF
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
config LIBM_ARCH_TRUNCF
bool
default n
- depends on LIBM && ARCH_CORTEXM33
+ depends on LIBM
# One or more the of above may be selected by architecture specific logic
[incubator-nuttx] 05/05: Fix nxstyle warning
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit d6c24312aa94430ff68a8430484b1972dbee6e66
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Fri Nov 27 00:33:25 2020 +0800
Fix nxstyle warning
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
libs/libc/machine/arm/armv8-m/arch_ceil.c | 2 +-
libs/libc/machine/arm/armv8-m/arch_ceilf.c | 2 +-
libs/libc/machine/arm/armv8-m/arch_elf.c | 56 ++++++++++++++---------------
libs/libc/machine/arm/armv8-m/arch_floorf.c | 2 +-
4 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/libs/libc/machine/arm/armv8-m/arch_ceil.c b/libs/libc/machine/arm/armv8-m/arch_ceil.c
index 9394fde..4210245 100644
--- a/libs/libc/machine/arm/armv8-m/arch_ceil.c
+++ b/libs/libc/machine/arm/armv8-m/arch_ceil.c
@@ -48,7 +48,7 @@
double ceil(double x)
{
double result;
- asm volatile ( "vrintp.f64\t%P0, %P1" : "=w" (result) : "w" (x) );
+ asm volatile("vrintp.f64\t%P0, %P1" : "=w"(result) : "w"(x));
return result;
}
diff --git a/libs/libc/machine/arm/armv8-m/arch_ceilf.c b/libs/libc/machine/arm/armv8-m/arch_ceilf.c
index 490c4ca..ed27ec7 100644
--- a/libs/libc/machine/arm/armv8-m/arch_ceilf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_ceilf.c
@@ -48,7 +48,7 @@
float ceilf(float x)
{
float result;
- asm volatile ( "vrintp.f32\t%0, %1" : "=t" (result) : "t" (x) );
+ asm volatile("vrintp.f32\t%0, %1" : "=t"(result) : "t"(x));
return result;
}
diff --git a/libs/libc/machine/arm/armv8-m/arch_elf.c b/libs/libc/machine/arm/armv8-m/arch_elf.c
index 6664584..a70f100 100644
--- a/libs/libc/machine/arm/armv8-m/arch_elf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_elf.c
@@ -210,23 +210,23 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
*
* upper_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +----------+---+-------------------------------+--------------+
- * |1 1 1 |OP1| OP2 | | 32-Bit Instructions
- * +----------+---+--+-----+----------------------+--------------+
- * |1 1 1 | 1 0| S | imm10 | BL Instruction
- * +----------+------+-----+-------------------------------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------+---+----------------------+-----------+
+ * |1 1 1|OP1| OP2 | | 32Bit Instruction
+ * +-------+---+-+---+----------------+-----------+
+ * |1 1 1| 1 0| S | imm10 | BL Instruction
+ * +-------+-----+---+----------------------------+
*
* lower_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +---+---------------------------------------------------------+
- * |OP | | 32-Bit Instructions
- * +---+--+---+---+---+------------------------------------------+
- * |1 1 |J1 | 1 |J2 | imm11 | BL Instruction
- * +------+---+---+---+------------------------------------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +--+-------------------------------------------+
+ * |OP| | 32Bit Instruction
+ * +--+-+--+--+--+--------------------------------+
+ * |1 1|J1| 1|J2| imm11 | BL Instruction
+ * +----+--+--+--+--------------------------------+
*
* The branch target is encoded in these bits:
*
@@ -385,23 +385,23 @@ int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
*
* upper_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +----------+---+-------------------------------+--------------+
- * |1 1 1 |OP1| OP2 | | 32-Bit Instructions
- * +----------+---+--+-----+----------------------+--------------+
- * |1 1 1 | 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
- * +----------+------+-----+----------------------+--------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-------+---+-----------------------+----------+
+ * |1 1 1|OP1| OP2 | | 32Bit Instruction
+ * +-------+---+-+---+-----------------+----------+
+ * |1 1 1| 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
+ * +-------+-----+---+-----------------+----------+
*
* lower_insn:
*
- * 1 1 1 1 1 1
- * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
- * +---+---------------------------------------------------------+
- * |OP | | 32-Bit Instructions
- * +---+----------+--------------+-------------------------------+
- * |0 | imm3 | Rd | imm8 | MOVT Instruction
- * +---+----------+--------------+-------------------------------+
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +--+-------------------------------------------+
+ * |OP| | 32Bit Instruction
+ * +--+--------+----------+-----------------------+
+ * |0 | imm3 | Rd | imm8 | MOVT Instruction
+ * +--+--------+----------+-----------------------+
*
* The 16-bit immediate value is encoded in these bits:
*
diff --git a/libs/libc/machine/arm/armv8-m/arch_floorf.c b/libs/libc/machine/arm/armv8-m/arch_floorf.c
index 6adb678..5d481ec 100644
--- a/libs/libc/machine/arm/armv8-m/arch_floorf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_floorf.c
@@ -48,7 +48,7 @@
float floorf(float x)
{
float result;
- asm volatile ( "vrintm.f32\t%0, %1" : "=t" (result) : "t" (x) );
+ asm volatile("vrintm.f32\t%0, %1" : "=t"(result) : "t"(x));
return result;
}
[incubator-nuttx] 04/05: libc/machine/arch: Support armv8-m
relocation
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit afb0e331388bbd463e82643b97b6700260812112
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Thu Nov 26 22:02:02 2020 +0800
libc/machine/arch: Support armv8-m relocation
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
libs/libc/machine/arm/armv8-m/Make.defs | 4 +
libs/libc/machine/arm/armv8-m/arch_elf.c | 511 +++++++++++++++++++++++++++++++
2 files changed, 515 insertions(+)
diff --git a/libs/libc/machine/arm/armv8-m/Make.defs b/libs/libc/machine/arm/armv8-m/Make.defs
index f2bdda5..07062aa 100644
--- a/libs/libc/machine/arm/armv8-m/Make.defs
+++ b/libs/libc/machine/arm/armv8-m/Make.defs
@@ -33,6 +33,10 @@
#
############################################################################
+ifeq ($(CONFIG_LIBC_ARCH_ELF),y)
+CSRCS += arch_elf.c
+endif
+
ifeq ($(CONFIG_ARMV8M_LIBM),y)
ifeq ($(LIBM_ARCH_CEIL),y)
diff --git a/libs/libc/machine/arm/armv8-m/arch_elf.c b/libs/libc/machine/arm/armv8-m/arch_elf.c
new file mode 100644
index 0000000..6664584
--- /dev/null
+++ b/libs/libc/machine/arm/armv8-m/arch_elf.c
@@ -0,0 +1,511 @@
+/****************************************************************************
+ * libs/libc/machine/arm/armv8-m/arch_elf.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <inttypes.h>
+#include <stdlib.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/elf.h>
+#include <nuttx/elf.h>
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_checkarch
+ *
+ * Description:
+ * Given the ELF header in 'hdr', verify that the ELF file is appropriate
+ * for the current, configured architecture. Every architecture that uses
+ * the ELF loader must provide this function.
+ *
+ * Input Parameters:
+ * hdr - The ELF header read from the ELF file.
+ *
+ * Returned Value:
+ * True if the architecture supports this ELF file.
+ *
+ ****************************************************************************/
+
+bool up_checkarch(FAR const Elf32_Ehdr *ehdr)
+{
+ /* Make sure it's an ARM executable */
+
+ if (ehdr->e_machine != EM_ARM)
+ {
+ berr("ERROR: Not for ARM: e_machine=%04x\n", ehdr->e_machine);
+ return false;
+ }
+
+ /* Make sure that 32-bit objects are supported */
+
+ if (ehdr->e_ident[EI_CLASS] != ELFCLASS32)
+ {
+ berr("ERROR: Need 32-bit objects: e_ident[EI_CLASS]=%02x\n",
+ ehdr->e_ident[EI_CLASS]);
+ return false;
+ }
+
+ /* Verify endian-ness */
+
+#ifdef CONFIG_ENDIAN_BIG
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2MSB)
+#else
+ if (ehdr->e_ident[EI_DATA] != ELFDATA2LSB)
+#endif
+ {
+ berr("ERROR: Wrong endian-ness: e_ident[EI_DATA]=%02x\n",
+ ehdr->e_ident[EI_DATA]);
+ return false;
+ }
+
+ /* TODO: Check ABI here. */
+
+ return true;
+}
+
+/****************************************************************************
+ * Name: up_relocate and up_relocateadd
+ *
+ * Description:
+ * Perform on architecture-specific ELF relocation. Every architecture
+ * that uses the ELF loader must provide this function.
+ *
+ * Input Parameters:
+ * rel - The relocation type
+ * sym - The ELF symbol structure containing the fully resolved value.
+ * There are a few relocation types for a few architectures that do
+ * not require symbol information. For those, this value will be
+ * NULL. Implementations of these functions must be able to handle
+ * that case.
+ * addr - The address that requires the relocation.
+ *
+ * Returned Value:
+ * Zero (OK) if the relocation was successful. Otherwise, a negated errno
+ * value indicating the cause of the relocation failure.
+ *
+ ****************************************************************************/
+
+int up_relocate(FAR const Elf32_Rel *rel, FAR const Elf32_Sym *sym,
+ uintptr_t addr)
+{
+ int32_t offset;
+ uint32_t upper_insn;
+ uint32_t lower_insn;
+ unsigned int relotype;
+
+ /* All relocations except R_ARM_V4BX depend upon having valid symbol
+ * information.
+ */
+
+ relotype = ELF32_R_TYPE(rel->r_info);
+ if (sym == NULL && relotype != R_ARM_NONE && relotype != R_ARM_V4BX)
+ {
+ return -EINVAL;
+ }
+
+ /* Handle the relocation by relocation type */
+
+ switch (relotype)
+ {
+ case R_ARM_NONE:
+ {
+ /* No relocation */
+ }
+ break;
+
+ case R_ARM_PC24:
+ case R_ARM_CALL:
+ case R_ARM_JUMP24:
+ {
+ binfo("Performing PC24 [%" PRId32 "] link at "
+ "addr %08lx [%08lx] to sym '%p' st_value=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), (long)addr,
+ (long)(*(uint32_t *)addr),
+ sym, (long)sym->st_value);
+
+ offset = (*(uint32_t *)addr & 0x00ffffff) << 2;
+ if (offset & 0x02000000)
+ {
+ offset -= 0x04000000;
+ }
+
+ offset += sym->st_value - addr;
+ if (offset & 3 || offset < (int32_t) 0xfe000000 ||
+ offset >= (int32_t) 0x02000000)
+ {
+ berr("ERROR: ERROR: PC24 [%" PRId32 "] "
+ "relocation out of range, offset=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), offset);
+
+ return -EINVAL;
+ }
+
+ offset >>= 2;
+
+ *(uint32_t *)addr &= 0xff000000;
+ *(uint32_t *)addr |= offset & 0x00ffffff;
+ }
+ break;
+
+ case R_ARM_ABS32:
+ case R_ARM_TARGET1: /* New ABI: TARGET1 always treated as ABS32 */
+ {
+ binfo("Performing ABS32 link "
+ "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ (long)addr, (long)(*(uint32_t *)addr),
+ sym, (long)sym->st_value);
+
+ *(uint32_t *)addr += sym->st_value;
+ }
+ break;
+
+#ifdef CONFIG_ARMV7M_TARGET2_PREL
+ case R_ARM_TARGET2: /* TARGET2 is a platform-specific relocation: gcc-arm-none-eabi
+ * performs a self relocation */
+ {
+ binfo("Performing TARGET2 link "
+ "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ (long)addr, (long)(*(uint32_t *)addr),
+ sym, (long)sym->st_value);
+
+ *(uint32_t *)addr += sym->st_value - addr;
+ }
+ break;
+#endif
+
+ case R_ARM_THM_CALL:
+ case R_ARM_THM_JUMP24:
+ {
+ uint32_t S;
+ uint32_t J1;
+ uint32_t J2;
+
+ /* Thumb BL and B.W instructions. Encoding:
+ *
+ * upper_insn:
+ *
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +----------+---+-------------------------------+--------------+
+ * |1 1 1 |OP1| OP2 | | 32-Bit Instructions
+ * +----------+---+--+-----+----------------------+--------------+
+ * |1 1 1 | 1 0| S | imm10 | BL Instruction
+ * +----------+------+-----+-------------------------------------+
+ *
+ * lower_insn:
+ *
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +---+---------------------------------------------------------+
+ * |OP | | 32-Bit Instructions
+ * +---+--+---+---+---+------------------------------------------+
+ * |1 1 |J1 | 1 |J2 | imm11 | BL Instruction
+ * +------+---+---+---+------------------------------------------+
+ *
+ * The branch target is encoded in these bits:
+ *
+ * S = upper_insn[10]
+ * imm10 = upper_insn[0:9]
+ * imm11 = lower_insn[0:10]
+ * J1 = lower_insn[13]
+ * J2 = lower_insn[11]
+ */
+
+ upper_insn = (uint32_t)(*(uint16_t *)addr);
+ lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
+
+ binfo("Performing THM_JUMP24 [%" PRId32 "] link "
+ "at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), (long)addr,
+ (int)upper_insn, (int)lower_insn,
+ sym, (long)sym->st_value);
+
+ /* Extract the 25-bit offset from the 32-bit instruction:
+ *
+ * offset[24] = S
+ * offset[23] = ~(J1 ^ S)
+ * offset[22] = ~(J2 ^ S)]
+ * offset[12:21] = imm10
+ * offset[1:11] = imm11
+ * offset[0] = 0
+ */
+
+ S = (upper_insn >> 10) & 1;
+ J1 = (lower_insn >> 13) & 1;
+ J2 = (lower_insn >> 11) & 1;
+
+ offset = (S << 24) | /* S - > offset[24] */
+ ((~(J1 ^ S) & 1) << 23) | /* J1 -> offset[23] */
+ ((~(J2 ^ S) & 1) << 22) | /* J2 -> offset[22] */
+ ((upper_insn & 0x03ff) << 12) | /* imm10 -> offset[12:21] */
+ ((lower_insn & 0x07ff) << 1); /* imm11 -> offset[1:11] */
+ /* 0 -> offset[0] */
+
+ /* Sign extend */
+
+ if (offset & 0x01000000)
+ {
+ offset -= 0x02000000;
+ }
+
+ /* And perform the relocation */
+
+ binfo(" S=%" PRId32 " J1=%" PRId32 " J2=%" PRId32
+ " offset=%08" PRIx32 " branch target=%08lx\n",
+ S, J1, J2, offset, offset + sym->st_value - addr);
+
+ offset += sym->st_value - addr;
+
+ /* Is this a function symbol? If so, then the branch target must be
+ * an odd Thumb address
+ */
+
+ if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
+ {
+ berr("ERROR: ERROR: JUMP24 [%" PRId32 "] "
+ "requires odd offset, offset=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), offset);
+
+ return -EINVAL;
+ }
+
+ /* Check the range of the offset */
+
+ if (offset < (int32_t)0xff000000 || offset >= (int32_t)0x01000000)
+ {
+ berr("ERROR: ERROR: JUMP24 [%" PRId32 "] "
+ "relocation out of range, branch target=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), offset);
+
+ return -EINVAL;
+ }
+
+ /* Now, reconstruct the 32-bit instruction using the new, relocated
+ * branch target.
+ */
+
+ S = (offset >> 24) & 1;
+ J1 = S ^ (~(offset >> 23) & 1);
+ J2 = S ^ (~(offset >> 22) & 1);
+
+ upper_insn = ((upper_insn & 0xf800) | (S << 10) |
+ ((offset >> 12) & 0x03ff));
+ *(uint16_t *)addr = (uint16_t)upper_insn;
+
+ lower_insn = ((lower_insn & 0xd000) | (J1 << 13) | (J2 << 11) |
+ ((offset >> 1) & 0x07ff));
+ *(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
+
+ binfo(" S=%" PRId32 " J1=%" PRId32 " J2=%" PRId32
+ " insn [%04" PRIx32 " %04" PRIx32 "]\n",
+ S, J1, J2, upper_insn, lower_insn);
+ }
+ break;
+
+ case R_ARM_V4BX:
+ {
+ binfo("Performing V4BX link at addr=%08lx [%08lx]\n",
+ (long)addr, (long)(*(uint32_t *)addr));
+
+ /* Preserve only Rm and the condition code */
+
+ *(uint32_t *)addr &= 0xf000000f;
+
+ /* Change instruction to 'mov pc, Rm' */
+
+ *(uint32_t *)addr |= 0x01a0f000;
+ }
+ break;
+
+ case R_ARM_PREL31:
+ {
+ binfo("Performing PREL31 link "
+ "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ (long)addr, (long)(*(uint32_t *)addr),
+ sym, (long)sym->st_value);
+
+ offset = *(uint32_t *)addr + sym->st_value - addr;
+ *(uint32_t *)addr = offset & 0x7fffffff;
+ }
+ break;
+
+ case R_ARM_MOVW_ABS_NC:
+ case R_ARM_MOVT_ABS:
+ {
+ binfo("Performing MOVx_ABS [%" PRId32 "] link "
+ "at addr=%08lx [%08lx] to sym=%p st_value=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), (long)addr,
+ (long)(*(uint32_t *)addr),
+ sym, (long)sym->st_value);
+
+ offset = *(uint32_t *)addr;
+ offset = ((offset & 0xf0000) >> 4) | (offset & 0xfff);
+
+ offset += sym->st_value;
+ if (ELF32_R_TYPE(rel->r_info) == R_ARM_MOVT_ABS)
+ {
+ offset >>= 16;
+ }
+
+ *(uint32_t *)addr &= 0xfff0f000;
+ *(uint32_t *)addr |= ((offset & 0xf000) << 4) | (offset & 0x0fff);
+ }
+ break;
+
+ case R_ARM_THM_MOVW_ABS_NC:
+ case R_ARM_THM_MOVT_ABS:
+ {
+ /* Thumb BL and B.W instructions. Encoding:
+ *
+ * upper_insn:
+ *
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +----------+---+-------------------------------+--------------+
+ * |1 1 1 |OP1| OP2 | | 32-Bit Instructions
+ * +----------+---+--+-----+----------------------+--------------+
+ * |1 1 1 | 1 0| i | 1 0 1 1 0 0 | imm4 | MOVT Instruction
+ * +----------+------+-----+----------------------+--------------+
+ *
+ * lower_insn:
+ *
+ * 1 1 1 1 1 1
+ * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +---+---------------------------------------------------------+
+ * |OP | | 32-Bit Instructions
+ * +---+----------+--------------+-------------------------------+
+ * |0 | imm3 | Rd | imm8 | MOVT Instruction
+ * +---+----------+--------------+-------------------------------+
+ *
+ * The 16-bit immediate value is encoded in these bits:
+ *
+ * i = imm16[11] = upper_insn[10]
+ * imm4 = imm16[12:15] = upper_insn[3:0]
+ * imm3 = imm16[8:10] = lower_insn[14:12]
+ * imm8 = imm16[0:7] = lower_insn[7:0]
+ */
+
+ upper_insn = (uint32_t)(*(uint16_t *)addr);
+ lower_insn = (uint32_t)(*(uint16_t *)(addr + 2));
+
+ binfo("Performing THM_MOVx [%" PRId32 "] link "
+ "at addr=%08lx [%04x %04x] to sym=%p st_value=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), (long)addr,
+ (int)upper_insn, (int)lower_insn,
+ sym, (long)sym->st_value);
+
+ /* Extract the 16-bit offset from the 32-bit instruction */
+
+ offset = ((upper_insn & 0x000f) << 12) | /* imm4 -> imm16[8:10] */
+ ((upper_insn & 0x0400) << 1) | /* i -> imm16[11] */
+ ((lower_insn & 0x7000) >> 4) | /* imm3 -> imm16[8:10] */
+ (lower_insn & 0x00ff); /* imm8 -> imm16[0:7] */
+
+ /* And perform the relocation */
+
+ binfo(" offset=%08lx branch target=%08lx\n",
+ (long)offset, offset + sym->st_value);
+
+ offset += sym->st_value;
+
+ /* Update the immediate value in the instruction.
+ * For MOVW we want the bottom 16-bits; for MOVT we want
+ * the top 16-bits.
+ */
+
+ if (ELF32_R_TYPE(rel->r_info) == R_ARM_THM_MOVT_ABS)
+ {
+ offset >>= 16;
+ }
+
+ upper_insn = ((upper_insn & 0xfbf0) | ((offset & 0xf000) >> 12) |
+ ((offset & 0x0800) >> 1));
+ *(uint16_t *)addr = (uint16_t)upper_insn;
+
+ lower_insn = ((lower_insn & 0x8f00) | ((offset & 0x0700) << 4) |
+ (offset & 0x00ff));
+ *(uint16_t *)(addr + 2) = (uint16_t)lower_insn;
+
+ binfo(" insn [%04x %04x]\n",
+ (int)upper_insn, (int)lower_insn);
+ }
+ break;
+
+ case R_ARM_THM_JUMP11:
+ {
+ offset = (uint32_t)(*(uint16_t *)addr & 0x7ff) << 1;
+ if (offset & 0x0800)
+ {
+ offset -= 0x1000;
+ }
+
+ offset += sym->st_value - addr;
+
+ if (ELF32_ST_TYPE(sym->st_info) == STT_FUNC && (offset & 1) == 0)
+ {
+ berr("ERROR: JUMP11 [%" PRId32 "] "
+ "requires odd offset, offset=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), offset);
+
+ return -EINVAL;
+ }
+
+ /* Check the range of the offset */
+
+ if (offset < (int32_t)0xfffff800 || offset >= (int32_t)0x0800)
+ {
+ berr("ERROR: JUMP11 [%" PRId32 "] "
+ "relocation out of range, branch taget=%08lx\n",
+ ELF32_R_TYPE(rel->r_info), offset);
+
+ return -EINVAL;
+ }
+
+ offset >>= 1;
+
+ *(uint16_t *)addr &= 0xf800;
+ *(uint16_t *)addr |= offset & 0x7ff;
+ }
+ break;
+
+ default:
+ berr("ERROR: Unsupported relocation: %" PRId32 "\n",
+ ELF32_R_TYPE(rel->r_info));
+ return -EINVAL;
+ }
+
+ return OK;
+}
+
+int up_relocateadd(FAR const Elf32_Rela *rel, FAR const Elf32_Sym *sym,
+ uintptr_t addr)
+{
+ berr("ERROR: RELA relocation not supported\n");
+ return -ENOSYS;
+}
[incubator-nuttx] 03/05: libs/libc/machine/arm: Rename armv8 to
armv8-m
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 74ab69af62e001ca60a7786ecd399336a927eb36
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Thu Nov 26 20:06:21 2020 +0800
libs/libc/machine/arm: Rename armv8 to armv8-m
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
libs/libc/machine/arm/Kconfig | 2 +-
libs/libc/machine/arm/Make.defs | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/Kconfig | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/Make.defs | 10 +++++-----
libs/libc/machine/arm/{armv8 => armv8-m}/arch_ceil.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_ceilf.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_floor.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_floorf.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_nearbyint.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_nearbyintf.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_rint.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_rintf.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_round.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_roundf.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_trunc.c | 2 +-
libs/libc/machine/arm/{armv8 => armv8-m}/arch_truncf.c | 2 +-
16 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/libs/libc/machine/arm/Kconfig b/libs/libc/machine/arm/Kconfig
index a56ac57..6adc22c 100644
--- a/libs/libc/machine/arm/Kconfig
+++ b/libs/libc/machine/arm/Kconfig
@@ -25,5 +25,5 @@ source libs/libc/machine/arm/armv7-m/Kconfig
endif
if ARCH_ARMV8M
-source libs/libc/machine/arm/armv8/Kconfig
+source libs/libc/machine/arm/armv8-m/Kconfig
endif
diff --git a/libs/libc/machine/arm/Make.defs b/libs/libc/machine/arm/Make.defs
index 89e008e..dfdaee6 100644
--- a/libs/libc/machine/arm/Make.defs
+++ b/libs/libc/machine/arm/Make.defs
@@ -54,7 +54,7 @@ include $(TOPDIR)/libs/libc/machine/arm/armv6-m/Make.defs
else ifeq ($(CONFIG_ARCH_ARMV7M),y) # All ARMv7-M
include $(TOPDIR)/libs/libc/machine/arm/armv7-m/Make.defs
else ifeq ($(CONFIG_ARCH_ARMV8M),y) # All ARMv8-M
-include $(TOPDIR)/libs/libc/machine/arm/armv8/Make.defs
+include $(TOPDIR)/libs/libc/machine/arm/armv8-m/Make.defs
endif
ifeq ($(CONFIG_CXX_EXCEPTION),y)
diff --git a/libs/libc/machine/arm/armv8/Kconfig b/libs/libc/machine/arm/armv8-m/Kconfig
similarity index 97%
rename from libs/libc/machine/arm/armv8/Kconfig
rename to libs/libc/machine/arm/armv8-m/Kconfig
index dab8132..825ee73 100644
--- a/libs/libc/machine/arm/armv8/Kconfig
+++ b/libs/libc/machine/arm/armv8-m/Kconfig
@@ -5,7 +5,7 @@
if ARCH_ARMV8M
-config ARMV8_LIBM
+config ARMV8M_LIBM
bool "Architecture specific optimizations"
default n
select LIBM_ARCH_CEIL if CONFIG_ARCH_DPFPU
diff --git a/libs/libc/machine/arm/armv8/Make.defs b/libs/libc/machine/arm/armv8-m/Make.defs
similarity index 93%
rename from libs/libc/machine/arm/armv8/Make.defs
rename to libs/libc/machine/arm/armv8-m/Make.defs
index 8e306f5..f2bdda5 100644
--- a/libs/libc/machine/arm/armv8/Make.defs
+++ b/libs/libc/machine/arm/armv8-m/Make.defs
@@ -1,5 +1,5 @@
############################################################################
-# libs/libc/machine/arm/armv8/Make.defs
+# libs/libc/machine/arm/armv8-m/Make.defs
#
# Copyright (C) 2017 Gregory Nutt. All rights reserved.
# Author: Gregory Nutt <gn...@nuttx.org>
@@ -33,7 +33,7 @@
#
############################################################################
-ifeq ($(CONFIG_ARMV8_LIBM),y)
+ifeq ($(CONFIG_ARMV8M_LIBM),y)
ifeq ($(LIBM_ARCH_CEIL),y)
CSRCS += arch_ceil.c
@@ -83,7 +83,7 @@ ifeq ($(LIBM_ARCH_TRUNC),y)
CSRCS += arch_trunc.c
endif
-DEPPATH += --dep-path machine/arm/armv8
-VPATH += :machine/arm/armv8
+DEPPATH += --dep-path machine/arm/armv8-m
+VPATH += :machine/arm/armv8-m
-endif # CONFIG_ARMV8_LIBM
+endif # CONFIG_ARMV8M_LIBM
diff --git a/libs/libc/machine/arm/armv8/arch_ceil.c b/libs/libc/machine/arm/armv8-m/arch_ceil.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_ceil.c
rename to libs/libc/machine/arm/armv8-m/arch_ceil.c
index bca708e..9394fde 100644
--- a/libs/libc/machine/arm/armv8/arch_ceil.c
+++ b/libs/libc/machine/arm/armv8-m/arch_ceil.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_ceil.c
+ * libs/libc/machine/arm/armv8-m/arch_ceil.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_ceilf.c b/libs/libc/machine/arm/armv8-m/arch_ceilf.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_ceilf.c
rename to libs/libc/machine/arm/armv8-m/arch_ceilf.c
index c5cff28..490c4ca 100644
--- a/libs/libc/machine/arm/armv8/arch_ceilf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_ceilf.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_ceilf.c
+ * libs/libc/machine/arm/armv8-m/arch_ceilf.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_floor.c b/libs/libc/machine/arm/armv8-m/arch_floor.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_floor.c
rename to libs/libc/machine/arm/armv8-m/arch_floor.c
index e401226..f9a0b9c 100644
--- a/libs/libc/machine/arm/armv8/arch_floor.c
+++ b/libs/libc/machine/arm/armv8-m/arch_floor.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_floor.c
+ * libs/libc/machine/arm/armv8-m/arch_floor.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_floorf.c b/libs/libc/machine/arm/armv8-m/arch_floorf.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_floorf.c
rename to libs/libc/machine/arm/armv8-m/arch_floorf.c
index b9dc9c2..6adb678 100644
--- a/libs/libc/machine/arm/armv8/arch_floorf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_floorf.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_floorf.c
+ * libs/libc/machine/arm/armv8-m/arch_floorf.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_nearbyint.c b/libs/libc/machine/arm/armv8-m/arch_nearbyint.c
similarity index 97%
rename from libs/libc/machine/arm/armv8/arch_nearbyint.c
rename to libs/libc/machine/arm/armv8-m/arch_nearbyint.c
index a4fae9b..701e787 100644
--- a/libs/libc/machine/arm/armv8/arch_nearbyint.c
+++ b/libs/libc/machine/arm/armv8-m/arch_nearbyint.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_nearbyint.c
+ * libs/libc/machine/arm/armv8-m/arch_nearbyint.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_nearbyintf.c b/libs/libc/machine/arm/armv8-m/arch_nearbyintf.c
similarity index 97%
rename from libs/libc/machine/arm/armv8/arch_nearbyintf.c
rename to libs/libc/machine/arm/armv8-m/arch_nearbyintf.c
index c00c848..6769066 100644
--- a/libs/libc/machine/arm/armv8/arch_nearbyintf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_nearbyintf.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_nearbyintf.c
+ * libs/libc/machine/arm/armv8-m/arch_nearbyintf.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_rint.c b/libs/libc/machine/arm/armv8-m/arch_rint.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_rint.c
rename to libs/libc/machine/arm/armv8-m/arch_rint.c
index 8e90941..b3b9d31 100644
--- a/libs/libc/machine/arm/armv8/arch_rint.c
+++ b/libs/libc/machine/arm/armv8-m/arch_rint.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_rint.c
+ * libs/libc/machine/arm/armv8-m/arch_rint.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_rintf.c b/libs/libc/machine/arm/armv8-m/arch_rintf.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_rintf.c
rename to libs/libc/machine/arm/armv8-m/arch_rintf.c
index 76ae43d..7c57f92 100644
--- a/libs/libc/machine/arm/armv8/arch_rintf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_rintf.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_rintf.c
+ * libs/libc/machine/arm/armv8-m/arch_rintf.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_round.c b/libs/libc/machine/arm/armv8-m/arch_round.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_round.c
rename to libs/libc/machine/arm/armv8-m/arch_round.c
index fd890cd..969a859 100644
--- a/libs/libc/machine/arm/armv8/arch_round.c
+++ b/libs/libc/machine/arm/armv8-m/arch_round.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_round.c
+ * libs/libc/machine/arm/armv8-m/arch_round.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_roundf.c b/libs/libc/machine/arm/armv8-m/arch_roundf.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_roundf.c
rename to libs/libc/machine/arm/armv8-m/arch_roundf.c
index b791d32..6e9a85c 100644
--- a/libs/libc/machine/arm/armv8/arch_roundf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_roundf.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_roundf.c
+ * libs/libc/machine/arm/armv8-m/arch_roundf.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_trunc.c b/libs/libc/machine/arm/armv8-m/arch_trunc.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_trunc.c
rename to libs/libc/machine/arm/armv8-m/arch_trunc.c
index a8845ba..2929b6d 100644
--- a/libs/libc/machine/arm/armv8/arch_trunc.c
+++ b/libs/libc/machine/arm/armv8-m/arch_trunc.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_trunc.c
+ * libs/libc/machine/arm/armv8-m/arch_trunc.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
diff --git a/libs/libc/machine/arm/armv8/arch_truncf.c b/libs/libc/machine/arm/armv8-m/arch_truncf.c
similarity index 98%
rename from libs/libc/machine/arm/armv8/arch_truncf.c
rename to libs/libc/machine/arm/armv8-m/arch_truncf.c
index 470ece3..5d51344 100644
--- a/libs/libc/machine/arm/armv8/arch_truncf.c
+++ b/libs/libc/machine/arm/armv8-m/arch_truncf.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * libs/libc/machine/arm/armv8/arch_truncf.c
+ * libs/libc/machine/arm/armv8-m/arch_truncf.c
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
*
[incubator-nuttx] 02/05: libc/machine/arm: Use the correct arch
Kconfig for variant check
Posted by ac...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit edca49fb5fc39e186b94ab46723a6ddaf501fe81
Author: Xiang Xiao <xi...@xiaomi.com>
AuthorDate: Thu Nov 26 19:59:11 2020 +0800
libc/machine/arm: Use the correct arch Kconfig for variant check
Signed-off-by: Xiang Xiao <xi...@xiaomi.com>
---
libs/libc/machine/arm/Kconfig | 13 +++++++------
libs/libc/machine/arm/Make.defs | 12 +++++++++---
libs/libc/machine/arm/armv8/Kconfig | 2 +-
3 files changed, 17 insertions(+), 10 deletions(-)
diff --git a/libs/libc/machine/arm/Kconfig b/libs/libc/machine/arm/Kconfig
index f263aa8..a56ac57 100644
--- a/libs/libc/machine/arm/Kconfig
+++ b/libs/libc/machine/arm/Kconfig
@@ -3,26 +3,27 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
-if ARCH_ARM7TDMI || ARCH_ARM920T || ARCH_ARM926EJS
+if ARCH_ARM7TDMI || ARCH_ARM920T || ARCH_ARM926EJS || \
+ ARCH_ARM1136J || ARCH_ARM1156T2 || ARCH_ARM1176JZ
source libs/libc/machine/arm/arm/Kconfig
endif
-if ARCH_CORTEXA5 || ARCH_CORTEXA8 || ARCH_CORTEXA9
+if ARCH_ARMV7A
source libs/libc/machine/arm/armv7-a/Kconfig
endif
-if ARCH_CORTEXR4 || ARCH_CORTEXR5 || ARCH_CORTEXR7
+if ARCH_ARMV7R
source libs/libc/machine/arm/armv7-r/Kconfig
endif
-if ARCH_CORTEXM0
+if ARCH_ARMV6M
source libs/libc/machine/arm/armv6-m/Kconfig
endif
-if ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7
+if ARCH_ARMV7M
source libs/libc/machine/arm/armv7-m/Kconfig
endif
-if ARCH_CORTEXM33
+if ARCH_ARMV8M
source libs/libc/machine/arm/armv8/Kconfig
endif
diff --git a/libs/libc/machine/arm/Make.defs b/libs/libc/machine/arm/Make.defs
index 0afb80c..89e008e 100644
--- a/libs/libc/machine/arm/Make.defs
+++ b/libs/libc/machine/arm/Make.defs
@@ -37,17 +37,23 @@ ifeq ($(CONFIG_ARCH_ARM7TDMI),y) # ARM7TDMI is ARMv4T
include $(TOPDIR)/libs/libc/machine/arm/arm/Make.defs
else ifeq ($(CONFIG_ARCH_ARM920T),y) # ARM920T is ARMv4T
include $(TOPDIR)/libs/libc/machine/arm/arm/Make.defs
-else ifeq ($(CONFIG_ARCH_ARM926EJS),y) # ARM926EJS is ARMv5TE
+else ifeq ($(CONFIG_ARCH_ARM926EJS),y) # ARM926EJS is ARMv5TEJ
+include $(TOPDIR)/libs/libc/machine/arm/arm/Make.defs
+else ifeq ($(CONFIG_ARCH_ARM1136J),y) # ARM1136J is ARMv6
+include $(TOPDIR)/libs/libc/machine/arm/arm/Make.defs
+else ifeq ($(CONFIG_ARCH_ARM1156T2),y) # ARM1156T2 is ARMv6T2
+include $(TOPDIR)/libs/libc/machine/arm/arm/Make.defs
+else ifeq ($(CONFIG_ARCH_ARM1176JZ),y) # ARM1176JZ is ARMv6Z
include $(TOPDIR)/libs/libc/machine/arm/arm/Make.defs
else ifeq ($(CONFIG_ARCH_ARMV7A),y) # All ARMv7-A
include $(TOPDIR)/libs/libc/machine/arm/armv7-a/Make.defs
else ifeq ($(CONFIG_ARCH_ARMV7R),y) # All ARMv7-R
include $(TOPDIR)/libs/libc/machine/arm/armv7-r/Make.defs
-else ifeq ($(CONFIG_ARCH_CORTEXM0),y) # Cortex-M0 is ARMv6-M
+else ifeq ($(CONFIG_ARCH_ARMV6M),y) # All ARMv6-M
include $(TOPDIR)/libs/libc/machine/arm/armv6-m/Make.defs
else ifeq ($(CONFIG_ARCH_ARMV7M),y) # All ARMv7-M
include $(TOPDIR)/libs/libc/machine/arm/armv7-m/Make.defs
-else ifeq ($(CONFIG_ARCH_CORTEXM33),y) # Cortex-M33 is ARMv8-M
+else ifeq ($(CONFIG_ARCH_ARMV8M),y) # All ARMv8-M
include $(TOPDIR)/libs/libc/machine/arm/armv8/Make.defs
endif
diff --git a/libs/libc/machine/arm/armv8/Kconfig b/libs/libc/machine/arm/armv8/Kconfig
index 002c44d..dab8132 100644
--- a/libs/libc/machine/arm/armv8/Kconfig
+++ b/libs/libc/machine/arm/armv8/Kconfig
@@ -3,7 +3,7 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
-if ARCH_CORTEXM33
+if ARCH_ARMV8M
config ARMV8_LIBM
bool "Architecture specific optimizations"