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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/09/10 06:34:41 UTC
(nuttx) 04/10: arm64/qemu_boot: add arm64 pci io memory map
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit bf5c57109889bf29524a4e737fefea92945c51ad
Author: Bowen Wang <wa...@xiaomi.com>
AuthorDate: Mon May 6 15:17:27 2024 +0800
arm64/qemu_boot: add arm64 pci io memory map
and rename other pci region name to make them more
readable
Signed-off-by: Bowen Wang <wa...@xiaomi.com>
---
arch/arm64/include/qemu/chip.h | 11 +++++++----
arch/arm64/src/qemu/qemu_boot.c | 13 ++++++++-----
2 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/qemu/chip.h b/arch/arm64/include/qemu/chip.h
index dfe854341b..ceb3290289 100644
--- a/arch/arm64/include/qemu/chip.h
+++ b/arch/arm64/include/qemu/chip.h
@@ -61,11 +61,14 @@
#define CONFIG_DEVICEIO_BASEADDR 0x7000000
#define CONFIG_DEVICEIO_SIZE MB(512)
-#define CONFIG_DEVICEPCIE_BASEADDR 0x4010000000
-#define CONFIG_DEVICEPCIE_SIZE MB(256)
+#define CONFIG_PCI_CFG_BASEADDR 0x4010000000
+#define CONFIG_PCI_CFG_SIZE MB(256)
-#define CONFIG_PCI_BASEADDR 0x8000000000
-#define CONFIG_PCI_SIZE GB(512)
+#define CONFIG_PCI_MEM_BASEADDR 0x8000000000
+#define CONFIG_PCI_MEM_SIZE GB(512)
+
+#define CONFIG_PCI_IO_BASEADDR 0x3eff0000
+#define CONFIG_PCI_IO_SIZE KB(64)
#define CONFIG_LOAD_BASE 0x40280000
diff --git a/arch/arm64/src/qemu/qemu_boot.c b/arch/arm64/src/qemu/qemu_boot.c
index cb13d00ecf..5242887b47 100644
--- a/arch/arm64/src/qemu/qemu_boot.c
+++ b/arch/arm64/src/qemu/qemu_boot.c
@@ -63,13 +63,16 @@ static const struct arm_mmu_region g_mmu_regions[] =
CONFIG_RAMBANK1_ADDR, CONFIG_RAMBANK1_SIZE,
MT_NORMAL | MT_RW | MT_SECURE),
- MMU_REGION_FLAT_ENTRY("PCI-E",
- CONFIG_DEVICEPCIE_BASEADDR,
- CONFIG_DEVICEPCIE_SIZE,
+ MMU_REGION_FLAT_ENTRY("PCI_CFG",
+ CONFIG_PCI_CFG_BASEADDR, CONFIG_PCI_CFG_SIZE,
MT_NORMAL | MT_RW | MT_SECURE),
- MMU_REGION_FLAT_ENTRY("PCI",
- CONFIG_PCI_BASEADDR, CONFIG_PCI_SIZE,
+ MMU_REGION_FLAT_ENTRY("PCI_MEM",
+ CONFIG_PCI_MEM_BASEADDR, CONFIG_PCI_MEM_SIZE,
+ MT_NORMAL | MT_RW | MT_SECURE),
+
+ MMU_REGION_FLAT_ENTRY("PCI_IO",
+ CONFIG_PCI_IO_BASEADDR, CONFIG_PCI_IO_SIZE,
MT_NORMAL | MT_RW | MT_SECURE),
};