You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by je...@apache.org on 2021/10/26 17:04:11 UTC
[mynewt-core] branch master updated (35b0596 -> f639e90)
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git.
from 35b0596 tinyusb: Add WINUSB descriptor support
new 7a8083b mcu/nrf5340: Add non-secure peripheral mapping
new 223b94c mcu/nrf5340: Add non-secure peripheral mapping in HAL
new b2bbe46 mcu/nrf5340: Add non-secure flash access
new b15e22c mcu/nfr5340: Disable QSPI errata in non-secure code
new 85b9a4a hw/ipc_nrf5340: Split ipc_nrf5340_init
new 19a9df8 hw/ipc_nrf5340: Configure shared memory in APP core only
new 3622bc4 hw/ipc_nrf5340: Use NRF_IPC_NS
new 0de28de hw/ipc_nrf5340: Allow non-secure execution
new a8cd86b mcu/nrf5340: Add system start for non-secure application
new f639e90 tinyusb/nrf5340: Allow for non-secure peripheral
The 10 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
hw/bsp/nordic_pca10095_net/nrf5340_net.ld | 1 -
.../include/ipc_nrf5340/ipc_nrf5340_priv.h} | 39 +++---
hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c | 134 +++++++++++++++------
hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h | 4 +-
hw/mcu/nordic/nrf5340/include/nrfx_config.h | 85 ++++++++++++-
hw/mcu/nordic/nrf5340/nrf5340.ld | 8 --
hw/mcu/nordic/nrf5340/pkg.yml | 2 +
hw/mcu/nordic/nrf5340/src/hal_flash.c | 18 ++-
hw/mcu/nordic/nrf5340/src/hal_nvreg.c | 5 +-
hw/mcu/nordic/nrf5340/src/hal_os_tick.c | 3 +-
hw/mcu/nordic/nrf5340/src/hal_qspi.c | 2 +
hw/mcu/nordic/nrf5340/src/hal_reset_cause.c | 5 +-
hw/mcu/nordic/nrf5340/src/hal_spi.c | 5 +-
hw/mcu/nordic/nrf5340/src/hal_system.c | 37 +++---
hw/mcu/nordic/nrf5340/src/hal_system_start.c | 91 ++++++++++++++
hw/mcu/nordic/nrf5340/src/hal_timer.c | 18 +--
hw/mcu/nordic/nrf5340/src/hal_uart.c | 8 +-
hw/mcu/nordic/nrf5340/src/hal_watchdog.c | 19 +--
hw/mcu/nordic/nrf5340/src/system_nrf5340.c | 11 +-
hw/mcu/nordic/nrf5340/syscfg.yml | 6 +
hw/mcu/nordic/nrf5340_net/nrf5340_net.ld | 6 -
hw/mcu/nordic/nrf5340_net/src/hal_vflash.c | 8 +-
hw/usb/tinyusb/nrf53/src/nrf53.c | 16 +--
23 files changed, 389 insertions(+), 142 deletions(-)
copy hw/{mcu/stm/stm32f3xx/include/mcu/cmsis_nvic.h => drivers/ipc_nrf5340/include/ipc_nrf5340/ipc_nrf5340_priv.h} (59%)
[mynewt-core] 02/10: mcu/nrf5340: Add non-secure peripheral mapping
in HAL
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 223b94c065dfb6199030fb8c58e83b212ee100df
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 10:33:23 2021 +0200
mcu/nrf5340: Add non-secure peripheral mapping in HAL
HAL functions were always using secure peripheral (NRF_XXX_S).
Now in most cases NRF_XXX is used that is mapped to _S or _NS
depending on build configuration.
---
hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h | 4 ++-
hw/mcu/nordic/nrf5340/src/hal_nvreg.c | 5 ++--
hw/mcu/nordic/nrf5340/src/hal_os_tick.c | 3 +-
hw/mcu/nordic/nrf5340/src/hal_reset_cause.c | 5 ++--
hw/mcu/nordic/nrf5340/src/hal_spi.c | 5 ++--
hw/mcu/nordic/nrf5340/src/hal_system.c | 37 +++++++++++++------------
hw/mcu/nordic/nrf5340/src/hal_timer.c | 18 ++++++------
hw/mcu/nordic/nrf5340/src/hal_uart.c | 8 +++---
hw/mcu/nordic/nrf5340/src/hal_watchdog.c | 19 +++++++------
hw/mcu/nordic/nrf5340/src/system_nrf5340.c | 11 +++-----
10 files changed, 60 insertions(+), 55 deletions(-)
diff --git a/hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h b/hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h
index ba72c5d..fe66fad 100644
--- a/hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h
+++ b/hw/mcu/nordic/nrf5340/include/mcu/nrf5340_hal.h
@@ -24,6 +24,8 @@
extern "C" {
#endif
+#include <nrfx_config.h>
+
/* Helper functions to enable/disable interrupts. */
#define __HAL_DISABLE_INTERRUPTS(x) \
do { \
@@ -75,7 +77,7 @@ struct nrf5340_hal_spi_cfg {
*/
#define HAL_GPIO_INDEX(pin) ((pin) & 0x1F)
-#define HAL_GPIO_PORT(pin) ((pin) > 31 ? NRF_P1_S : NRF_P0_S)
+#define HAL_GPIO_PORT(pin) ((pin) > 31 ? NRF_P1 : NRF_P0)
#define HAL_GPIO_MASK(pin) (1 << HAL_GPIO_INDEX(pin))
#define HAL_GPIOTE_PIN_MASK (0x3FUL << GPIOTE_CONFIG_PSEL_Pos)
diff --git a/hw/mcu/nordic/nrf5340/src/hal_nvreg.c b/hw/mcu/nordic/nrf5340/src/hal_nvreg.c
index 7c0bb21..2d983e9 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_nvreg.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_nvreg.c
@@ -20,6 +20,7 @@
#include <mcu/cortex_m33.h>
#include <hal/hal_nvreg.h>
#include <nrf.h>
+#include <nrfx_config.h>
/* There are two GPREGRET registers on the NRF5340 */
#define HAL_NVREG_MAX (2)
@@ -31,7 +32,7 @@ void
hal_nvreg_write(unsigned int reg, uint32_t val)
{
if (reg < HAL_NVREG_MAX) {
- NRF_POWER_S->GPREGRET[reg] = val;
+ NRF_POWER->GPREGRET[reg] = val;
}
}
@@ -41,7 +42,7 @@ hal_nvreg_read(unsigned int reg)
uint32_t val = 0;
if (reg < HAL_NVREG_MAX) {
- val = NRF_POWER_S->GPREGRET[reg];
+ val = NRF_POWER->GPREGRET[reg];
}
return val;
diff --git a/hw/mcu/nordic/nrf5340/src/hal_os_tick.c b/hw/mcu/nordic/nrf5340/src/hal_os_tick.c
index e641a7c..e6c6446 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_os_tick.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_os_tick.c
@@ -21,6 +21,7 @@
#include <os/mynewt.h>
#include <hal/hal_os_tick.h>
#include <nrf.h>
+#include <nrfx_config.h>
#include <mcu/cmsis_nvic.h>
/* The OS scheduler requires a low-frequency timer. */
@@ -29,7 +30,7 @@
#endif
#define RTC_FREQ 32768 /* in Hz */
-#define OS_TICK_TIMER NRF_RTC1_S
+#define OS_TICK_TIMER NRF_RTC1
#define OS_TICK_IRQ RTC1_IRQn
#define OS_TICK_CMPREG 3
#define RTC_COMPARE_INT_MASK(ccreg) (1UL << ((ccreg) + 16))
diff --git a/hw/mcu/nordic/nrf5340/src/hal_reset_cause.c b/hw/mcu/nordic/nrf5340/src/hal_reset_cause.c
index 4eedb1a..04c7939 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_reset_cause.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_reset_cause.c
@@ -18,6 +18,7 @@
*/
#include <nrf.h>
+#include <nrfx_config.h>
#include <hal/hal_system.h>
enum hal_reset_reason
@@ -30,7 +31,7 @@ hal_reset_cause(void)
return reason;
}
- reg = NRF_RESET_S->RESETREAS;
+ reg = NRF_RESET->RESETREAS;
if (reg & (RESET_RESETREAS_DOG0_Msk | RESET_RESETREAS_DOG1_Msk | RESET_RESETREAS_LOCKUP_Msk)) {
reason = HAL_RESET_WATCHDOG;
@@ -44,7 +45,7 @@ hal_reset_cause(void)
reason = HAL_RESET_POR; /* could also be brownout */
}
- NRF_RESET_S->RESETREAS = reg;
+ NRF_RESET->RESETREAS = reg;
return reason;
}
diff --git a/hw/mcu/nordic/nrf5340/src/hal_spi.c b/hw/mcu/nordic/nrf5340/src/hal_spi.c
index ded7bc6..1ba5c34 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_spi.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_spi.c
@@ -25,6 +25,7 @@
#include <hal/hal_spi.h>
#include <mcu/nrf5340_hal.h>
#include <nrf.h>
+#include <nrfx_config.h>
#define SPIM_TXD_MAXCNT_MAX 0xffff
@@ -347,9 +348,9 @@ hal_spi_config_master(struct nrf5340_hal_spi *spi,
*/
pin = spim->PSEL.SCK & SPIM_PSEL_SCK_PIN_Msk;
if (spim->PSEL.SCK & SPIM_PSEL_SCK_PORT_Msk) {
- port = NRF_P1_S;
+ port = NRF_P1;
} else {
- port = NRF_P0_S;
+ port = NRF_P0;
}
if (settings->data_mode <= HAL_SPI_MODE1) {
diff --git a/hw/mcu/nordic/nrf5340/src/hal_system.c b/hw/mcu/nordic/nrf5340/src/hal_system.c
index 4b9058b..668718a 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_system.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_system.c
@@ -22,6 +22,7 @@
#include <hal/hal_system.h>
#include <hal/hal_debug.h>
#include <nrf.h>
+#include <nrfx_config.h>
/**
* Function called at startup. Called after BSS and .data initialized but
@@ -41,10 +42,10 @@ hal_system_init(void)
#endif
#if MYNEWT_VAL(MCU_DCDC_ENABLED)
- NRF_REGULATORS_S->VREGMAIN.DCDCEN = 1;
+ NRF_REGULATORS->VREGMAIN.DCDCEN = 1;
#if MYNEWT_VAL(BSP_NRF5340_NET_ENABLE)
- NRF_REGULATORS_S->VREGRADIO.DCDCEN = 1;
+ NRF_REGULATORS->VREGRADIO.DCDCEN = 1;
#endif
#endif
}
@@ -85,8 +86,8 @@ hal_system_clock_start(void)
regval = CLOCK_LFCLKSTAT_STATE_Running << CLOCK_LFCLKSTAT_STATE_Pos;
#if MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFXO)
- NRF_P0_S->PIN_CNF[0] |= GPIO_PIN_CNF_MCUSEL_Peripheral << GPIO_PIN_CNF_MCUSEL_Pos;
- NRF_P0_S->PIN_CNF[1] |= GPIO_PIN_CNF_MCUSEL_Peripheral << GPIO_PIN_CNF_MCUSEL_Pos;
+ NRF_P0->PIN_CNF[0] |= GPIO_PIN_CNF_MCUSEL_Peripheral << GPIO_PIN_CNF_MCUSEL_Pos;
+ NRF_P0->PIN_CNF[1] |= GPIO_PIN_CNF_MCUSEL_Peripheral << GPIO_PIN_CNF_MCUSEL_Pos;
regval |= CLOCK_LFCLKSTAT_SRC_LFXO << CLOCK_LFCLKSTAT_SRC_Pos;
clksrc = CLOCK_LFCLKSTAT_SRC_LFXO;
#elif MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFSYNTH)
@@ -101,12 +102,12 @@ hal_system_clock_start(void)
#if MYNEWT_VAL_CHOICE(MCU_LFCLK_SOURCE, LFSYNTH)
/* Must turn on HFLCK for synthesized 32768 crystal */
- if ((NRF_CLOCK_S->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk) !=
+ if ((NRF_CLOCK->HFCLKSTAT & CLOCK_HFCLKSTAT_STATE_Msk) !=
(CLOCK_HFCLKSTAT_STATE_Running << CLOCK_HFCLKSTAT_STATE_Pos)) {
- NRF_CLOCK_S->EVENTS_HFCLKSTARTED = 0;
- NRF_CLOCK_S->TASKS_HFCLKSTART = 1;
+ NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
+ NRF_CLOCK->TASKS_HFCLKSTART = 1;
while (1) {
- if ((NRF_CLOCK_S->EVENTS_HFCLKSTARTED) != 0) {
+ if ((NRF_CLOCK->EVENTS_HFCLKSTARTED) != 0) {
break;
}
}
@@ -114,16 +115,16 @@ hal_system_clock_start(void)
#endif
/* Check if this clock source is already running */
- if ((NRF_CLOCK_S->LFCLKSTAT & regmsk) != regval) {
- NRF_CLOCK_S->TASKS_LFCLKSTOP = 1;
- NRF_CLOCK_S->EVENTS_LFCLKSTARTED = 0;
- NRF_CLOCK_S->LFCLKSRC = clksrc;
- NRF_CLOCK_S->TASKS_LFCLKSTART = 1;
+ if ((NRF_CLOCK->LFCLKSTAT & regmsk) != regval) {
+ NRF_CLOCK->TASKS_LFCLKSTOP = 1;
+ NRF_CLOCK->EVENTS_LFCLKSTARTED = 0;
+ NRF_CLOCK->LFCLKSRC = clksrc;
+ NRF_CLOCK->TASKS_LFCLKSTART = 1;
/* Wait here till started! */
while (1) {
- if (NRF_CLOCK_S->EVENTS_LFCLKSTARTED) {
- if ((NRF_CLOCK_S->LFCLKSTAT & regmsk) == regval) {
+ if (NRF_CLOCK->EVENTS_LFCLKSTARTED) {
+ if ((NRF_CLOCK->LFCLKSTAT & regmsk) == regval) {
break;
}
}
@@ -131,10 +132,10 @@ hal_system_clock_start(void)
}
#endif
if (MYNEWT_VAL(MCU_HFCLCK192_DIV) == 1) {
- NRF_CLOCK_S->HFCLK192MCTRL = 0;
+ NRF_CLOCK->HFCLK192MCTRL = 0;
} else if (MYNEWT_VAL(MCU_HFCLCK192_DIV) == 2) {
- NRF_CLOCK_S->HFCLK192MCTRL = 1;
+ NRF_CLOCK->HFCLK192MCTRL = 1;
} else if (MYNEWT_VAL(MCU_HFCLCK192_DIV) == 4) {
- NRF_CLOCK_S->HFCLK192MCTRL = 2;
+ NRF_CLOCK->HFCLK192MCTRL = 2;
}
}
diff --git a/hw/mcu/nordic/nrf5340/src/hal_timer.c b/hw/mcu/nordic/nrf5340/src/hal_timer.c
index f642c49..cdc6c1e 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_timer.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_timer.c
@@ -454,28 +454,28 @@ hal_timer_init(int timer_num, void *cfg)
#if MYNEWT_VAL(TIMER_0)
case 0:
irq_num = TIMER0_IRQn;
- hwtimer = NRF_TIMER0_S;
+ hwtimer = NRF_TIMER0;
irq_isr = nrf5340_timer0_irq_handler;
break;
#endif
#if MYNEWT_VAL(TIMER_1)
case 1:
irq_num = TIMER1_IRQn;
- hwtimer = NRF_TIMER1_S;
+ hwtimer = NRF_TIMER1;
irq_isr = nrf5340_timer1_irq_handler;
break;
#endif
#if MYNEWT_VAL(TIMER_2)
case 2:
irq_num = TIMER2_IRQn;
- hwtimer = NRF_TIMER2_S;
+ hwtimer = NRF_TIMER2;
irq_isr = nrf5340_timer2_irq_handler;
break;
#endif
#if MYNEWT_VAL(TIMER_3)
case 3:
irq_num = RTC0_IRQn;
- hwtimer = NRF_RTC0_S;
+ hwtimer = NRF_RTC0;
irq_isr = nrf5340_timer3_irq_handler;
bsptimer->tmr_rtc = 1;
break;
@@ -483,7 +483,7 @@ hal_timer_init(int timer_num, void *cfg)
#if MYNEWT_VAL(TIMER_4)
case 4:
irq_num = RTC1_IRQn;
- hwtimer = NRF_RTC1_S;
+ hwtimer = NRF_RTC1;
irq_isr = nrf5340_timer4_irq_handler;
bsptimer->tmr_rtc = 1;
break;
@@ -613,13 +613,13 @@ hal_timer_config(int timer_num, uint32_t freq_hz)
__HAL_DISABLE_INTERRUPTS(ctx);
/* Make sure HFXO is started */
- if ((NRF_CLOCK_S->HFCLKSTAT &
+ if ((NRF_CLOCK->HFCLKSTAT &
(CLOCK_HFCLKSTAT_SRC_Msk | CLOCK_HFCLKSTAT_STATE_Msk)) !=
(CLOCK_HFCLKSTAT_SRC_Msk | CLOCK_HFCLKSTAT_STATE_Msk)) {
- NRF_CLOCK_S->EVENTS_HFCLKSTARTED = 0;
- NRF_CLOCK_S->TASKS_HFCLKSTART = 1;
+ NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
+ NRF_CLOCK->TASKS_HFCLKSTART = 1;
while (1) {
- if ((NRF_CLOCK_S->EVENTS_HFCLKSTARTED) != 0) {
+ if ((NRF_CLOCK->EVENTS_HFCLKSTARTED) != 0) {
break;
}
}
diff --git a/hw/mcu/nordic/nrf5340/src/hal_uart.c b/hw/mcu/nordic/nrf5340/src/hal_uart.c
index dbe4f5a..e4a2dac 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_uart.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_uart.c
@@ -324,28 +324,28 @@ hal_uart_init(int port, void *arg)
switch (port) {
#if MYNEWT_VAL(UART_0)
case 0:
- u->nrf_uart = NRF_UARTE0_S;
+ u->nrf_uart = NRF_UARTE0;
u->handler = (uint32_t)uart0_irq_handler;
u->irqn = SPIM0_SPIS0_TWIM0_TWIS0_UARTE0_IRQn;
break;
#endif
#if MYNEWT_VAL(UART_1)
case 1:
- u->nrf_uart = NRF_UARTE1_S;
+ u->nrf_uart = NRF_UARTE1;
u->handler = (uint32_t)uart1_irq_handler;
u->irqn = SPIM1_SPIS1_TWIM1_TWIS1_UARTE1_IRQn;
break;
#endif
#if MYNEWT_VAL(UART_2)
case 2:
- u->nrf_uart = NRF_UARTE2_S;
+ u->nrf_uart = NRF_UARTE2;
u->handler = (uint32_t)uart2_irq_handler;
u->irqn = SPIM2_SPIS2_TWIM2_TWIS2_UARTE2_IRQn;
break;
#endif
#if MYNEWT_VAL(UART_3)
case 3:
- u->nrf_uart = NRF_UARTE3_S;
+ u->nrf_uart = NRF_UARTE3;
u->handler = (uint32_t)uart3_irq_handler;
u->irqn = SPIM3_SPIS3_TWIM3_TWIS3_UARTE3_IRQn;
break;
diff --git a/hw/mcu/nordic/nrf5340/src/hal_watchdog.c b/hw/mcu/nordic/nrf5340/src/hal_watchdog.c
index bc015f8..19a26b9 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_watchdog.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_watchdog.c
@@ -22,6 +22,7 @@
#include <hal/hal_watchdog.h>
#include <mcu/cmsis_nvic.h>
#include <nrf.h>
+#include <nrfx_config.h>
static void
nrf5340_hal_wdt_default_handler(void)
@@ -34,8 +35,8 @@ static void
nrf5340_wdt_irq_handler(void)
{
os_trace_isr_enter();
- if (NRF_WDT0_S->INTENSET & WDT_INTENSET_TIMEOUT_Msk) {
- NRF_WDT0_S->EVENTS_TIMEOUT = 0;
+ if (NRF_WDT0->INTENSET & WDT_INTENSET_TIMEOUT_Msk) {
+ NRF_WDT0->EVENTS_TIMEOUT = 0;
nrf5340_hal_wdt_default_handler();
}
os_trace_isr_exit();
@@ -46,19 +47,19 @@ hal_watchdog_init(uint32_t expire_msecs)
{
uint64_t expiration;
- NRF_WDT0_S->CONFIG = WDT_CONFIG_SLEEP_Msk;
+ NRF_WDT0->CONFIG = WDT_CONFIG_SLEEP_Msk;
/* Convert msec timeout to counts of a 32768 crystal */
expiration = ((uint64_t)expire_msecs * 32768) / 1000;
- NRF_WDT0_S->CRV = (uint32_t)expiration;
+ NRF_WDT0->CRV = (uint32_t)expiration;
- NRF_WDT0_S->CRV = (expire_msecs * 32) + ((expire_msecs * 96) / 125);
+ NRF_WDT0->CRV = (expire_msecs * 32) + ((expire_msecs * 96) / 125);
NVIC_SetVector(WDT0_IRQn, (uint32_t)nrf5340_wdt_irq_handler);
NVIC_SetPriority(WDT0_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
NVIC_ClearPendingIRQ(WDT0_IRQn);
NVIC_EnableIRQ(WDT0_IRQn);
- NRF_WDT0_S->RREN |= 0x1;
+ NRF_WDT0->RREN |= 0x1;
return 0;
}
@@ -66,13 +67,13 @@ hal_watchdog_init(uint32_t expire_msecs)
void
hal_watchdog_enable(void)
{
- NRF_WDT0_S->INTENSET = WDT_INTENSET_TIMEOUT_Msk;
- NRF_WDT0_S->TASKS_START = 1;
+ NRF_WDT0->INTENSET = WDT_INTENSET_TIMEOUT_Msk;
+ NRF_WDT0->TASKS_START = 1;
}
void
hal_watchdog_tickle(void)
{
- NRF_WDT0_S->RR[0] = WDT_RR_RR_Reload;
+ NRF_WDT0->RR[0] = WDT_RR_RR_Reload;
}
diff --git a/hw/mcu/nordic/nrf5340/src/system_nrf5340.c b/hw/mcu/nordic/nrf5340/src/system_nrf5340.c
index 4ebd8ce..84fa385 100644
--- a/hw/mcu/nordic/nrf5340/src/system_nrf5340.c
+++ b/hw/mcu/nordic/nrf5340/src/system_nrf5340.c
@@ -27,6 +27,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
#include <stdbool.h>
#include <syscfg/syscfg.h>
#include <nrf.h>
+#include <nrfx_config.h>
#include <nrf_erratas.h>
#include <system_nrf5340_application.h>
#include <mcu/cmsis_nvic.h>
@@ -62,11 +63,7 @@ NOTICE: This file has been modified by Nordic Semiconductor ASA.
void SystemCoreClockUpdate(void)
{
-#if defined(NRF_TRUSTZONE_NONSECURE)
- SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_NS->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
-#else
- SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK_S->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
-#endif
+ SystemCoreClock = __SYSTEM_CLOCK_MAX >> (NRF_CLOCK->HFCLKCTRL & (CLOCK_HFCLKCTRL_HCLK_Msk));
}
void SystemInit(void)
@@ -247,9 +244,9 @@ void SystemInit(void)
#endif
if (MYNEWT_VAL(MCU_HFCLK_DIV) == 1) {
- NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div1 << CLOCK_HFCLKCTRL_HCLK_Pos;
+ NRF_CLOCK->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div1 << CLOCK_HFCLKCTRL_HCLK_Pos;
} else {
- NRF_CLOCK_S->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
+ NRF_CLOCK->HFCLKCTRL = CLOCK_HFCLKCTRL_HCLK_Div2 << CLOCK_HFCLKCTRL_HCLK_Pos;
}
SystemCoreClockUpdate();
[mynewt-core] 01/10: mcu/nrf5340: Add non-secure peripheral mapping
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 7a8083b3ea5eaf053b672ea7c1df68afc0f40963
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 10:23:28 2021 +0200
mcu/nrf5340: Add non-secure peripheral mapping
So far application core was using secure version of all peripherals.
If ARM TrustZone is to be used non-secure mapping is needed.
This adds syscfg value MCU_APP_SECURE that chooses if secure on
non-secure peripherals are to be used.
---
hw/mcu/nordic/nrf5340/include/nrfx_config.h | 85 +++++++++++++++++++++++++++--
hw/mcu/nordic/nrf5340/syscfg.yml | 6 ++
2 files changed, 87 insertions(+), 4 deletions(-)
diff --git a/hw/mcu/nordic/nrf5340/include/nrfx_config.h b/hw/mcu/nordic/nrf5340/include/nrfx_config.h
index 87fa001..141085e 100644
--- a/hw/mcu/nordic/nrf5340/include/nrfx_config.h
+++ b/hw/mcu/nordic/nrf5340/include/nrfx_config.h
@@ -54,6 +54,8 @@
#endif
#endif
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_APP_SECURE)
+
/*
* The MDK provides macros for accessing the peripheral register structures
* by using their secure and non-secure address mappings (with the names
@@ -127,6 +129,85 @@
#define NRF_WDT0 NRF_WDT0_S
#define NRF_WDT1 NRF_WDT1_S
+/* Fixups for GPIOTE driver. */
+#define NRF_GPIOTE NRF_GPIOTE0_S
+#define GPIOTE_IRQHandler GPIOTE0_IRQHandler
+
+#else
+
+#define NRF_TRUSTZONE_NONSECURE
+
+#define NRF_COMP NRF_COMP_NS
+#define NRF_CLOCK NRF_CLOCK_NS
+#define NRF_DCNF NRF_DCNF_NS
+#define NRF_DPPIC NRF_DPPIC_NS
+#define NRF_EGU0 NRF_EGU0_NS
+#define NRF_EGU1 NRF_EGU1_NS
+#define NRF_EGU2 NRF_EGU2_NS
+#define NRF_EGU3 NRF_EGU3_NS
+#define NRF_EGU4 NRF_EGU4_NS
+#define NRF_EGU5 NRF_EGU5_NS
+#define NRF_FPU NRF_FPU_NS
+#define NRF_I2S NRF_I2S0_NS
+#define NRF_IPC NRF_IPC_NS
+#define NRF_KMU NRF_KMU_NS
+#define NRF_LPCOMP NRF_LPCOMP_NS
+#define NRF_MUTEX NRF_MUTEX_NS
+#define NRF_NFCT NRF_NFCT_NS
+#define NRF_NVMC NRF_NVMC_NS
+#define NRF_OSCILLATORS NRF_OSCILLATORS_NS
+#define NRF_P0 NRF_P0_NS
+#define NRF_P1 NRF_P1_NS
+#define NRF_PDM0 NRF_PDM0_NS
+#define NRF_POWER NRF_POWER_NS
+#define NRF_PWM0 NRF_PWM0_NS
+#define NRF_PWM1 NRF_PWM1_NS
+#define NRF_PWM2 NRF_PWM2_NS
+#define NRF_PWM3 NRF_PWM3_NS
+#define NRF_QDEC0 NRF_QDEC0_NS
+#define NRF_QDEC1 NRF_QDEC1_NS
+#define NRF_QSPI NRF_QSPI_NS
+#define NRF_REGULATORS NRF_REGULATORS_NS
+#define NRF_RESET NRF_RESET_NS
+#define NRF_RTC0 NRF_RTC0_NS
+#define NRF_RTC1 NRF_RTC1_NS
+#define NRF_SAADC NRF_SAADC_NS
+#define NRF_SPIM0 NRF_SPIM0_NS
+#define NRF_SPIM1 NRF_SPIM1_NS
+#define NRF_SPIM2 NRF_SPIM2_NS
+#define NRF_SPIM3 NRF_SPIM3_NS
+#define NRF_SPIM4 NRF_SPIM4_NS
+#define NRF_SPIS0 NRF_SPIS0_NS
+#define NRF_SPIS1 NRF_SPIS1_NS
+#define NRF_SPIS2 NRF_SPIS2_NS
+#define NRF_SPIS3 NRF_SPIS3_NS
+#define NRF_TIMER0 NRF_TIMER0_NS
+#define NRF_TIMER1 NRF_TIMER1_NS
+#define NRF_TIMER2 NRF_TIMER2_NS
+#define NRF_TWIM0 NRF_TWIM0_NS
+#define NRF_TWIM1 NRF_TWIM1_NS
+#define NRF_TWIM2 NRF_TWIM2_NS
+#define NRF_TWIM3 NRF_TWIM3_NS
+#define NRF_TWIS0 NRF_TWIS0_NS
+#define NRF_TWIS1 NRF_TWIS1_NS
+#define NRF_TWIS2 NRF_TWIS2_NS
+#define NRF_TWIS3 NRF_TWIS3_NS
+#define NRF_UARTE0 NRF_UARTE0_NS
+#define NRF_UARTE1 NRF_UARTE1_NS
+#define NRF_UARTE2 NRF_UARTE2_NS
+#define NRF_UARTE3 NRF_UARTE3_NS
+#define NRF_USBD NRF_USBD_NS
+#define NRF_USBREGULATOR NRF_USBREGULATOR_NS
+#define NRF_VMC NRF_VMC_NS
+#define NRF_WDT0 NRF_WDT0_NS
+#define NRF_WDT1 NRF_WDT1_NS
+
+/* Fixups for GPIOTE driver. */
+#define NRF_GPIOTE NRF_GPIOTE1_NS
+#define GPIOTE_IRQHandler GPIOTE1_IRQHandler
+
+#endif
+
/*
* The following section provides the name translation for peripherals with
* only one type of access available. For these peripherals, you cannot choose
@@ -142,10 +223,6 @@
#define NRF_SPU NRF_SPU_S
#define NRF_UICR NRF_UICR_S
-/* Fixups for GPIOTE driver. */
-#define NRF_GPIOTE NRF_GPIOTE0_S
-#define GPIOTE_IRQHandler GPIOTE0_IRQHandler
-
/* Fixups for QDEC driver. */
#define NRF_QDEC NRF_QDEC0
#define QDEC_IRQHandler QDEC0_IRQHandler
diff --git a/hw/mcu/nordic/nrf5340/syscfg.yml b/hw/mcu/nordic/nrf5340/syscfg.yml
index 9a07ebb..7480df9 100644
--- a/hw/mcu/nordic/nrf5340/syscfg.yml
+++ b/hw/mcu/nordic/nrf5340/syscfg.yml
@@ -96,6 +96,12 @@ syscfg.defs:
MCU/BSP wants to handle APPROTECT on its own.
value: 0
+ MCU_APP_SECURE:
+ description: >
+ Application code to runs in secure mode.
+ This settings must have same value for bootloader and application build.
+ value: 1
+
# MCU peripherals definitions
ADC_0:
description: 'Enable nRF5340 ADC 0'
[mynewt-core] 04/10: mcu/nfr5340: Disable QSPI errata in non-secure
code
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit b15e22ceaf03280336e89f3e220f8eb1e50b6cf2
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 10:44:22 2021 +0200
mcu/nfr5340: Disable QSPI errata in non-secure code
Errata 121 have to be executed in secure state.
In non-secure state executing nrf53_errata12() result in
access violation exception.
When QSPI is to be used in non-secure application,
bootloader must enable QSPI for correct errata usage.
---
hw/mcu/nordic/nrf5340/src/hal_qspi.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/hw/mcu/nordic/nrf5340/src/hal_qspi.c b/hw/mcu/nordic/nrf5340/src/hal_qspi.c
index c554bb1..d3142e6 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_qspi.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_qspi.c
@@ -375,6 +375,7 @@ nrf5340_qspi_init(const struct hal_flash *dev)
NRF_QSPI->XIPOFFSET = MYNEWT_VAL(QSPI_XIP_OFFSET);
+#if !defined(NRF_TRUSTZONE_NONSECURE)
/* Workaround for Errata 121: QSPI: Configuration of peripheral requires additional steps */
if (nrf53_errata_121()) {
NRF_QSPI->IFTIMING = (NRF_QSPI->IFTIMING & ~(7 << 8)) | (6 << 8);
@@ -385,6 +386,7 @@ nrf5340_qspi_init(const struct hal_flash *dev)
NRF_QSPI->IFCONFIG0 |= (1 << 16);
}
}
+#endif
#if (MYNEWT_VAL(QSPI_READOC) > 2) || (MYNEWT_VAL(QSPI_WRITEOC) > 1)
NRF_QSPI->PSEL.IO2 = MYNEWT_VAL(QSPI_PIN_DIO2);
[mynewt-core] 10/10: tinyusb/nrf5340: Allow for non-secure
peripheral
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit f639e90be8b0886d0b1c4252e6279c90ee61a2c4
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 16:51:58 2021 +0200
tinyusb/nrf5340: Allow for non-secure peripheral
NRF_USBREGULATOR_S was always used now for non-secure
build NRF_USBREGULATOR will map to NRF_USBREGULATOR_NS.
---
hw/usb/tinyusb/nrf53/src/nrf53.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/hw/usb/tinyusb/nrf53/src/nrf53.c b/hw/usb/tinyusb/nrf53/src/nrf53.c
index 795fb07..a439b06 100644
--- a/hw/usb/tinyusb/nrf53/src/nrf53.c
+++ b/hw/usb/tinyusb/nrf53/src/nrf53.c
@@ -57,18 +57,18 @@ nrf_usbreg_event_get_and_clear(NRF_USBREG_Type *p_reg,
static void
USBREG_IRQHandler(void)
{
- if (nrf_usbreg_int_enable_check(NRF_USBREGULATOR_S, NRF_USBREG_INT_USBDETECTED) &&
- (nrf_usbreg_event_get_and_clear(NRF_USBREGULATOR_S, NRF_USBREG_EVENT_USBDETECTED))) {
+ if (nrf_usbreg_int_enable_check(NRF_USBREGULATOR, NRF_USBREG_INT_USBDETECTED) &&
+ (nrf_usbreg_event_get_and_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBDETECTED))) {
tusb_hal_nrf_power_event(USB_EVT_DETECTED);
}
- if (nrf_usbreg_int_enable_check(NRF_USBREGULATOR_S, NRF_USBREG_INT_USBREMOVED) &&
- nrf_usbreg_event_get_and_clear(NRF_USBREGULATOR_S,NRF_USBREG_EVENT_USBREMOVED)) {
+ if (nrf_usbreg_int_enable_check(NRF_USBREGULATOR, NRF_USBREG_INT_USBREMOVED) &&
+ nrf_usbreg_event_get_and_clear(NRF_USBREGULATOR,NRF_USBREG_EVENT_USBREMOVED)) {
tusb_hal_nrf_power_event(USB_EVT_REMOVED);
}
- if (nrf_usbreg_int_enable_check(NRF_USBREGULATOR_S, NRF_USBREG_INT_USBPWRRDY) &&
- nrf_usbreg_event_get_and_clear(NRF_USBREGULATOR_S, NRF_USBREG_EVENT_USBPWRRDY)) {
+ if (nrf_usbreg_int_enable_check(NRF_USBREGULATOR, NRF_USBREG_INT_USBPWRRDY) &&
+ nrf_usbreg_event_get_and_clear(NRF_USBREGULATOR, NRF_USBREG_EVENT_USBPWRRDY)) {
tusb_hal_nrf_power_event(USB_EVT_READY);
}
}
@@ -83,7 +83,7 @@ tinyusb_hardware_init(void)
/* Setup Power IRQ to detect USB VBUS state (detected, ready, removed) */
NVIC_SetVector(USBREGULATOR_IRQn, (uint32_t)USBREG_IRQHandler);
NVIC_SetPriority(USBREGULATOR_IRQn, 7);
- nrf_usbreg_int_enable(NRF_USBREGULATOR_S,
+ nrf_usbreg_int_enable(NRF_USBREGULATOR,
USBREG_INTEN_USBDETECTED_Msk |
USBREG_INTEN_USBREMOVED_Msk |
USBREG_INTEN_USBPWRRDY_Msk);
@@ -94,7 +94,7 @@ tinyusb_hardware_init(void)
* USB power may already be ready at this time -> no event generated
* We need to invoke the handler based on the status initially
*/
- uint32_t usb_reg = NRF_USBREGULATOR_S->USBREGSTATUS;
+ uint32_t usb_reg = NRF_USBREGULATOR->USBREGSTATUS;
if (usb_reg & USBREG_USBREGSTATUS_VBUSDETECT_Msk) {
tusb_hal_nrf_power_event(USB_EVT_DETECTED);
[mynewt-core] 08/10: hw/ipc_nrf5340: Allow non-secure execution
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 0de28dec7b33921abb823ff806fcca54c9d08785
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 16:18:45 2021 +0200
hw/ipc_nrf5340: Allow non-secure execution
Code was using NRF_RESET_S.
Now it uses NRF_RESET which can be non-secure.
In case of secure execution net core gains access to app core RAM.
In case of non-secure execution RAM is non-secure so no permission
change is needed (it would be not possible anyway since NRF_SPU_S is
secure only peripheral).
---
hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
index 1690955..e1a3ee5 100644
--- a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
+++ b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
@@ -22,6 +22,10 @@
#include <ipc_nrf5340/ipc_nrf5340.h>
#include <ipc_nrf5340/ipc_nrf5340_priv.h>
#include <nrfx.h>
+#include <hal/hal_gpio.h>
+#include <bsp.h>
+#include <nrf_mutex.h>
+
#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
#include <mcu/nrf5340_hal.h>
#include <bsp/bsp.h>
@@ -219,7 +223,7 @@ ipc_nrf5340_init(void)
#endif
/* Make sure network core if off when we set up IPC */
- NRF_RESET_S->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold;
+ NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold;
memset(shms, 0, sizeof(shms));
for (i = 0; i < IPC_MAX_CHANS; ++i) {
@@ -252,11 +256,13 @@ ipc_nrf5340_init(void)
ipc_nrf5340_init_nrf_ipc();
- /* this allows netcore to access appcore RAM */
- NRF_SPU_S->EXTDOMAIN[0].PERM = SPU_EXTDOMAIN_PERM_SECATTR_Secure << SPU_EXTDOMAIN_PERM_SECATTR_Pos;
+ if (MYNEWT_VAL(MCU_APP_SECURE)) {
+ /* this allows netcore to access appcore RAM */
+ NRF_SPU_S->EXTDOMAIN[0].PERM = SPU_EXTDOMAIN_PERM_SECATTR_Secure << SPU_EXTDOMAIN_PERM_SECATTR_Pos;
+ }
/* Start Network Core */
- NRF_RESET_S->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release;
+ NRF_RESET->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release;
#if MYNEWT_VAL(NRF5340_EMBED_NET_CORE)
/*
[mynewt-core] 05/10: hw/ipc_nrf5340: Split ipc_nrf5340_init
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 85b9a4aada44781188c568b26b76f9ffef5770ad
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 11:20:08 2021 +0200
hw/ipc_nrf5340: Split ipc_nrf5340_init
APP and NET core IPC initialization differs a lot.
Function ipc_nrf5340_init was almost every line conditionally
compiled except small common code.
Now common code that initializes NRF_IPC block (same for NET and APP)
is extracted to separate function and rest is put in one block
for APP and second for NET for easier read.
No change in logic.
---
hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c | 73 +++++++++++++++++++-------------
1 file changed, 43 insertions(+), 30 deletions(-)
diff --git a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
index b0d7da8..bb3ae04 100644
--- a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
+++ b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
@@ -160,18 +160,35 @@ ipc_nrf5340_isr(void)
#define STRIP_PARENS(X) X
#define UNMANGLE_MYNEWT_VAL(X) STRIP_PARENS(_Args X)
-void
-ipc_nrf5340_init(void)
+static void
+ipc_nrf5340_init_nrf_ipc(void)
{
int i;
+ /* Enable IPC channels */
+ for (i = 0; i < IPC_MAX_CHANS; i++) {
+ NRF_IPC->SEND_CNF[i] = (0x01UL << i);
+ NRF_IPC->RECEIVE_CNF[i] = 0;
+ }
+
+ NRF_IPC->INTENCLR = 0xFFFF;
+ NVIC_ClearPendingIRQ(IPC_IRQn);
+ NVIC_SetVector(IPC_IRQn, (uint32_t)ipc_nrf5340_isr);
+ NVIC_EnableIRQ(IPC_IRQn);
+}
+
#if MYNEWT_VAL(MCU_APP_CORE)
+void
+ipc_nrf5340_init(void)
+{
#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
+ int i;
+
unsigned int gpios[] = { UNMANGLE_MYNEWT_VAL(MYNEWT_VAL(IPC_NRF5340_NET_GPIO)) };
NRF_GPIO_Type *nrf_gpio;
#endif
-#if MYNEWT_VAL(MCU_APP_CORE) && MYNEWT_VAL(NRF5340_EMBED_NET_CORE)
+#if MYNEWT_VAL(NRF5340_EMBED_NET_CORE)
/*
* Get network core image size and placement in application flash.
* Then pass those two values in NRF_IPC GPMEM registers to be used
@@ -195,40 +212,16 @@ ipc_nrf5340_init(void)
GPIO_PIN_CNF_MCUSEL_NetworkMCU << GPIO_PIN_CNF_MCUSEL_Pos;
}
#endif
-#endif
-
-#if MYNEWT_VAL(MCU_NET_CORE)
- /*
- * When network core IPCs starts it clears GPMEM from APP core registers
- * So IPC nows that netcore is running.
- * This is a workaround that is needed till application side code waits
- * on IPC for network core controller to sent NOP first.
- */
-#define NRF_APP_IPC_NS ((NRF_IPC_Type *)0x4002A000)
-#define NRF_APP_IPC_S ((NRF_IPC_Type *)0x5002A000)
- NRF_APP_IPC_S->GPMEM[0] = 0;
- NRF_APP_IPC_S->GPMEM[1] = 0;
-#endif
- /* Enable IPC channels */
- for (i = 0; i < IPC_MAX_CHANS; i++) {
- NRF_IPC->SEND_CNF[i] = (0x01UL << i);
- NRF_IPC->RECEIVE_CNF[i] = 0;
- }
+ ipc_nrf5340_init_nrf_ipc();
- NRF_IPC->INTENCLR = 0xFFFF;
- NVIC_ClearPendingIRQ(IPC_IRQn);
- NVIC_SetVector(IPC_IRQn, (uint32_t)ipc_nrf5340_isr);
- NVIC_EnableIRQ(IPC_IRQn);
-
-#if MYNEWT_VAL(MCU_APP_CORE)
/* this allows netcore to access appcore RAM */
NRF_SPU_S->EXTDOMAIN[0].PERM = SPU_EXTDOMAIN_PERM_SECATTR_Secure << SPU_EXTDOMAIN_PERM_SECATTR_Pos;
/* Start Network Core */
NRF_RESET_S->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Release;
-#endif
-#if MYNEWT_VAL(MCU_APP_CORE) && MYNEWT_VAL(NRF5340_EMBED_NET_CORE)
+
+#if MYNEWT_VAL(NRF5340_EMBED_NET_CORE)
/*
* TODO: Remove below workaround:
* For now app core waits for NET core to start.
@@ -247,6 +240,26 @@ ipc_nrf5340_init(void)
}
#endif
}
+#endif
+
+#if MYNEWT_VAL(MCU_NET_CORE)
+void
+ipc_nrf5340_init(void)
+{
+ /*
+ * When network core IPCs starts it clears GPMEM from APP core registers
+ * So IPC knows that netcore is running.
+ * This is a workaround that is needed till application side code waits
+ * on IPC for network core controller to sent NOP first.
+ */
+#define NRF_APP_IPC_NS ((NRF_IPC_Type *)0x4002A000)
+#define NRF_APP_IPC_S ((NRF_IPC_Type *)0x5002A000)
+ NRF_APP_IPC_S->GPMEM[0] = 0;
+ NRF_APP_IPC_S->GPMEM[1] = 0;
+
+ ipc_nrf5340_init_nrf_ipc();
+}
+#endif
void
ipc_nrf5340_recv(int channel, ipc_nrf5340_recv_cb cb, void *user_data)
[mynewt-core] 06/10: hw/ipc_nrf5340: Configure shared memory in APP
core only
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 19a9df8ae41b10db84d915421b59eddf50238a83
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 12:17:11 2021 +0200
hw/ipc_nrf5340: Configure shared memory in APP core only
So far number of channels and size of memory buffers used for shared
memory had to be set to same value at compile time for NET and APP
core. Failure to keep value the same could result in hard to solve
IPC issues.
This leaves configuration of IPC memory in application only (it is
part of application RAM that is used for this any way).
It also changes how parameters about SHM (and for vflash) are passed to
network core.
For IPC hard-coded .ipc section was used in linker scripts (both cores).
For net core image NRF_IPC->MEMGP was used.
Now NRF_IPC->MEMGP is used to pass shared data (ipc_shared) to net core.
It will be used by ipc_nrf5340 driver and by vflash driver on net core.
---
hw/bsp/nordic_pca10095_net/nrf5340_net.ld | 1 -
.../include/ipc_nrf5340/ipc_nrf5340_priv.h} | 36 ++++++++++++++----
hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c | 43 ++++++++++++++++++----
hw/mcu/nordic/nrf5340/nrf5340.ld | 8 ----
hw/mcu/nordic/nrf5340_net/nrf5340_net.ld | 6 ---
hw/mcu/nordic/nrf5340_net/src/hal_vflash.c | 8 +++-
6 files changed, 70 insertions(+), 32 deletions(-)
diff --git a/hw/bsp/nordic_pca10095_net/nrf5340_net.ld b/hw/bsp/nordic_pca10095_net/nrf5340_net.ld
index 5327829..0737752 100644
--- a/hw/bsp/nordic_pca10095_net/nrf5340_net.ld
+++ b/hw/bsp/nordic_pca10095_net/nrf5340_net.ld
@@ -20,7 +20,6 @@ MEMORY
{
FLASH (rx) : ORIGIN = 0x01008000, LENGTH = 0x30000
RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
- IPC (rw) : ORIGIN = 0x20000400, LENGTH = 0x40000
}
/* This linker script is used for images and thus contains an image header */
diff --git a/hw/bsp/nordic_pca10095_net/nrf5340_net.ld b/hw/drivers/ipc_nrf5340/include/ipc_nrf5340/ipc_nrf5340_priv.h
similarity index 53%
copy from hw/bsp/nordic_pca10095_net/nrf5340_net.ld
copy to hw/drivers/ipc_nrf5340/include/ipc_nrf5340/ipc_nrf5340_priv.h
index 5327829..c1d2e82 100644
--- a/hw/bsp/nordic_pca10095_net/nrf5340_net.ld
+++ b/hw/drivers/ipc_nrf5340/include/ipc_nrf5340/ipc_nrf5340_priv.h
@@ -16,12 +16,34 @@
* specific language governing permissions and limitations
* under the License.
*/
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x01008000, LENGTH = 0x30000
- RAM (rwx) : ORIGIN = 0x21000000, LENGTH = 0x10000
- IPC (rw) : ORIGIN = 0x20000400, LENGTH = 0x40000
+
+#ifndef _HW_DRIVERS_IPC_NRF5340_PRIV_H
+#define _HW_DRIVERS_IPC_NRF5340_PRIV_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Initialization structure passed from APP core to NET core.
+ * Keeps various parameters that otherwise should be configured on
+ * both sides.
+ */
+struct ipc_shared {
+ /** NET core embedded image address in application flash */
+ void *net_core_image_address;
+ /** NET core embedded image size */
+ uint32_t net_core_image_size;
+ /** Number of IPC channels */
+ uint8_t ipc_channel_count;
+ /* Array of shared memories used for IPC */
+ struct ipc_shm *ipc_shms;
+};
+
+#ifdef __cplusplus
}
+#endif
-/* This linker script is used for images and thus contains an image header */
-_imghdr_size = 0x20;
+#endif /* _HW_DRIVERS_IPC_NRF5340_PRIV_H */
diff --git a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
index bb3ae04..e28fbf2 100644
--- a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
+++ b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
@@ -20,6 +20,7 @@
#include <errno.h>
#include <os/os.h>
#include <ipc_nrf5340/ipc_nrf5340.h>
+#include <ipc_nrf5340/ipc_nrf5340_priv.h>
#include <nrfx.h>
#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
#include <mcu/nrf5340_hal.h>
@@ -52,11 +53,24 @@ struct ipc_channel {
struct ipc_shm {
volatile uint16_t head;
volatile uint16_t tail;
- uint8_t buf[IPC_BUF_SIZE];
+ uint16_t buf_size;
+ uint8_t *buf;
};
static struct ipc_channel ipcs[IPC_MAX_CHANS];
-static struct ipc_shm __attribute__((section (".ipc"))) shms[IPC_MAX_CHANS];
+#if MYNEWT_VAL(MCU_APP_CORE)
+static struct ipc_shm shms[IPC_MAX_CHANS];
+static uint8_t shms_bufs[IPC_MAX_CHANS][IPC_BUF_SIZE];
+static struct ipc_shared ipc_shared[1];
+
+#else
+static struct ipc_shm *shms;
+static struct ipc_shared *ipc_shared;
+#undef IPC_MAX_CHANS
+#undef IPC_BUF_SIZE
+#define IPC_MAX_CHANS ipc_shared->ipc_channel_count
+#define IPC_BUF_SIZE ipc_shared->ipc_shms->buf_size
+#endif
static uint16_t
ipc_nrf5340_shm_get_data_length(uint16_t head, uint16_t tail)
@@ -181,9 +195,10 @@ ipc_nrf5340_init_nrf_ipc(void)
void
ipc_nrf5340_init(void)
{
-#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
int i;
+#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
+
unsigned int gpios[] = { UNMANGLE_MYNEWT_VAL(MYNEWT_VAL(IPC_NRF5340_NET_GPIO)) };
NRF_GPIO_Type *nrf_gpio;
#endif
@@ -191,12 +206,12 @@ ipc_nrf5340_init(void)
#if MYNEWT_VAL(NRF5340_EMBED_NET_CORE)
/*
* Get network core image size and placement in application flash.
- * Then pass those two values in NRF_IPC GPMEM registers to be used
+ * Then pass those two values to ipc_shared data to be used
* by virtual flash driver on network side.
*/
if (&_binary_net_core_img_end - &_binary_net_core_img_start > 32) {
- NRF_IPC->GPMEM[0] = (uint32_t)&_binary_net_core_img_start;
- NRF_IPC->GPMEM[1] = &_binary_net_core_img_end - &_binary_net_core_img_start;
+ ipc_shared->net_core_image_address = (void *)&_binary_net_core_img_start;
+ ipc_shared->net_core_image_size = &_binary_net_core_img_end - &_binary_net_core_img_start;
}
#endif
@@ -204,6 +219,15 @@ ipc_nrf5340_init(void)
NRF_RESET_S->NETWORK.FORCEOFF = RESET_NETWORK_FORCEOFF_FORCEOFF_Hold;
memset(shms, 0, sizeof(shms));
+ for (i = 0; i < IPC_MAX_CHANS; ++i) {
+ shms[i].buf = shms_bufs[i];
+ shms[i].buf_size = IPC_BUF_SIZE;
+ }
+ ipc_shared->ipc_channel_count = IPC_MAX_CHANS;
+ ipc_shared->ipc_shms = shms;
+
+ NRF_IPC->GPMEM[0] = (uint32_t)ipc_shared;
+
#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
/* Configure GPIOs for Networking Core */
for (i = 0; i < ARRAY_SIZE(gpios); i++) {
@@ -236,7 +260,7 @@ ipc_nrf5340_init(void)
* Application side prepared image for net core.
* When net core starts it's ipc_nrf5340_init() will clear those.
*/
- while (NRF_IPC->GPMEM[1]);
+ while (NRF_IPC->GPMEM[0]);
}
#endif
}
@@ -254,8 +278,11 @@ ipc_nrf5340_init(void)
*/
#define NRF_APP_IPC_NS ((NRF_IPC_Type *)0x4002A000)
#define NRF_APP_IPC_S ((NRF_IPC_Type *)0x5002A000)
+ ipc_shared = (struct ipc_shared *)NRF_APP_IPC_S->GPMEM[0];
+ assert(ipc_shared);
+ shms = ipc_shared->ipc_shms;
+ assert(ipc_shared->ipc_channel_count <= ARRAY_SIZE(ipcs));
NRF_APP_IPC_S->GPMEM[0] = 0;
- NRF_APP_IPC_S->GPMEM[1] = 0;
ipc_nrf5340_init_nrf_ipc();
}
diff --git a/hw/mcu/nordic/nrf5340/nrf5340.ld b/hw/mcu/nordic/nrf5340/nrf5340.ld
index 25ce143..ca11f17 100644
--- a/hw/mcu/nordic/nrf5340/nrf5340.ld
+++ b/hw/mcu/nordic/nrf5340/nrf5340.ld
@@ -137,14 +137,6 @@ SECTIONS
. = ALIGN(4);
} > RAM
- /* Section for app-net cores IPC */
- .ipc 0x20000400 (NOLOAD):
- {
- . = ALIGN(4);
- *(.ipc)
- . = ALIGN(4);
- } > RAM
-
/* This section will be zeroed by RTT package init */
.rtt (NOLOAD):
{
diff --git a/hw/mcu/nordic/nrf5340_net/nrf5340_net.ld b/hw/mcu/nordic/nrf5340_net/nrf5340_net.ld
index 9a64264..f3f8b4c 100644
--- a/hw/mcu/nordic/nrf5340_net/nrf5340_net.ld
+++ b/hw/mcu/nordic/nrf5340_net/nrf5340_net.ld
@@ -130,12 +130,6 @@ SECTIONS
. = ALIGN(4);
} > RAM
- /* Section for app-net cores IPC */
- .ipc (NOLOAD):
- {
- *(.ipc)
- } > IPC
-
/* This section will be zeroed by RTT package init */
.rtt (NOLOAD):
{
diff --git a/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c b/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c
index c2ffa7f..d06c8a5 100644
--- a/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c
+++ b/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c
@@ -27,6 +27,7 @@
#include <nrfx_ipc.h>
#include <bootutil/bootutil.h>
#include <bootutil/image.h>
+#include <ipc_nrf5340/ipc_nrf5340_priv.h>
#define NRF5340_NET_VFLASH_SECTOR_SZ 2048
@@ -217,6 +218,7 @@ static int
nrf5340_net_vflash_init(const struct hal_flash *dev)
{
struct nrf5340_vflash *vflash = (struct nrf5340_vflash *)dev;
+ const struct ipc_shared *ipc_shared = (const struct ipc_shared *)NRF_APP_IPC_S->GPMEM[0];
/*
* Application side IPC will set GPMEM registers to address and size of
@@ -225,8 +227,10 @@ nrf5340_net_vflash_init(const struct hal_flash *dev)
* and there no need to provide any data.
* Set nv_image_size to 0 and all reads will return empty values (0xff)
*/
- vflash->nv_image_address = (const uint8_t *)NRF_APP_IPC_S->GPMEM[0];
- vflash->nv_image_size = NRF_APP_IPC_S->GPMEM[1];
+ if (ipc_shared && ipc_shared->net_core_image_address) {
+ vflash->nv_image_address = ipc_shared->net_core_image_address;
+ vflash->nv_image_size = ipc_shared->net_core_image_size;
+ }
return 0;
}
[mynewt-core] 07/10: hw/ipc_nrf5340: Use NRF_IPC_NS
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit 3622bc475cbc527addf4044518b97b4267409ebc
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 16:09:10 2021 +0200
hw/ipc_nrf5340: Use NRF_IPC_NS
So far NRF_IPC_S was used.
Now NRF_IPC_NS will be used even if application is secure.
It will simplify configuration.
Network core use application core NRF_IPC peripheral to get
information about shared data.
If it uses non-secure version always there is no need to
build net core application differently for secure/non-secure
build.
If MCU_APP_SECURE is 1 ICP code switches NRF_IPC to non-secure.
If MCU_APP_SECURE is 0, this was already done by bootloader.
---
hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c | 20 ++++++++++++++++----
hw/mcu/nordic/nrf5340_net/src/hal_vflash.c | 2 +-
2 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
index e28fbf2..1690955 100644
--- a/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
+++ b/hw/drivers/ipc_nrf5340/src/ipc_nrf5340.c
@@ -63,6 +63,9 @@ static struct ipc_shm shms[IPC_MAX_CHANS];
static uint8_t shms_bufs[IPC_MAX_CHANS][IPC_BUF_SIZE];
static struct ipc_shared ipc_shared[1];
+/* Always use unsecure peripheral for IPC */
+#undef NRF_IPC
+#define NRF_IPC NRF_IPC_NS
#else
static struct ipc_shm *shms;
static struct ipc_shared *ipc_shared;
@@ -226,7 +229,17 @@ ipc_nrf5340_init(void)
ipc_shared->ipc_channel_count = IPC_MAX_CHANS;
ipc_shared->ipc_shms = shms;
- NRF_IPC->GPMEM[0] = (uint32_t)ipc_shared;
+ if (MYNEWT_VAL(MCU_APP_SECURE)) {
+ /*
+ * When bootloader is secure and application is not all peripherals are
+ * in unsecure mode. This is done by bootloader.
+ * If application runs in secure mode IPC manually chooses to use unsecure version
+ * so NETCORE can always use same peripheral to get shares memory configuration
+ * description from GPMEM[0].
+ */
+ NRF_SPU->PERIPHID[42].PERM &= ~SPU_PERIPHID_PERM_SECATTR_Msk;
+ }
+ NRF_IPC_NS->GPMEM[0] = (uint32_t)ipc_shared;
#if MYNEWT_VAL(IPC_NRF5340_NET_GPIO)
/* Configure GPIOs for Networking Core */
@@ -277,12 +290,11 @@ ipc_nrf5340_init(void)
* on IPC for network core controller to sent NOP first.
*/
#define NRF_APP_IPC_NS ((NRF_IPC_Type *)0x4002A000)
-#define NRF_APP_IPC_S ((NRF_IPC_Type *)0x5002A000)
- ipc_shared = (struct ipc_shared *)NRF_APP_IPC_S->GPMEM[0];
+ ipc_shared = (struct ipc_shared *)NRF_APP_IPC_NS->GPMEM[0];
assert(ipc_shared);
shms = ipc_shared->ipc_shms;
assert(ipc_shared->ipc_channel_count <= ARRAY_SIZE(ipcs));
- NRF_APP_IPC_S->GPMEM[0] = 0;
+ NRF_APP_IPC_NS->GPMEM[0] = 0;
ipc_nrf5340_init_nrf_ipc();
}
diff --git a/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c b/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c
index d06c8a5..11aa778 100644
--- a/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c
+++ b/hw/mcu/nordic/nrf5340_net/src/hal_vflash.c
@@ -218,7 +218,7 @@ static int
nrf5340_net_vflash_init(const struct hal_flash *dev)
{
struct nrf5340_vflash *vflash = (struct nrf5340_vflash *)dev;
- const struct ipc_shared *ipc_shared = (const struct ipc_shared *)NRF_APP_IPC_S->GPMEM[0];
+ const struct ipc_shared *ipc_shared = (const struct ipc_shared *)NRF_APP_IPC_NS->GPMEM[0];
/*
* Application side IPC will set GPMEM registers to address and size of
[mynewt-core] 03/10: mcu/nrf5340: Add non-secure flash access
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit b2bbe46e408281ea002feede583a7e6d322c896c
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 10:38:59 2021 +0200
mcu/nrf5340: Add non-secure flash access
Flash secure and non-secure peripheral differs slightly.
This adds support for non-secure access depending on build configuration.
---
hw/mcu/nordic/nrf5340/src/hal_flash.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/hw/mcu/nordic/nrf5340/src/hal_flash.c b/hw/mcu/nordic/nrf5340/src/hal_flash.c
index 659dda1..9e4fe5b 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_flash.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_flash.c
@@ -33,7 +33,7 @@ nrf5340_flash_wait_ready(void)
int i;
for (i = 0; i < 100000; i++) {
- if (NRF_NVMC_S->READY == NVMC_READY_READY_Ready) {
+ if (NRF_NVMC->READY == NVMC_READY_READY_Ready) {
return 0;
}
}
@@ -65,7 +65,11 @@ nrf5340_flash_write(const struct hal_flash *dev, uint32_t address,
return -1;
}
__HAL_DISABLE_INTERRUPTS(sr);
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_APP_SECURE)
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Wen; /* Enable erase OP */
+#else
+ NRF_NVMC_NS->CONFIGNS = NVMC_CONFIGNS_WEN_Wen; /* Enable erase OP */
+#endif
tmp = address & 0x3;
if (tmp) {
if (nrf5340_flash_wait_ready()) {
@@ -113,7 +117,11 @@ nrf5340_flash_write(const struct hal_flash *dev, uint32_t address,
rc = nrf5340_flash_wait_ready();
out:
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_APP_SECURE)
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
+#else
+ NRF_NVMC_NS->CONFIGNS = NVMC_CONFIGNS_WEN_Ren;
+#endif
__HAL_ENABLE_INTERRUPTS(sr);
return rc;
}
@@ -131,12 +139,20 @@ nrf5340_flash_erase_sector(const struct hal_flash *dev, uint32_t sector_address)
}
__HAL_DISABLE_INTERRUPTS(sr);
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_APP_SECURE)
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Een; /* Enable erase OP */
+#else
+ NRF_NVMC_NS->CONFIGNS = NVMC_CONFIGNS_WEN_Een; /* Enable erase OP */
+#endif
*(uint32_t *)sector_address = 0xFFFFFFFF;
rc = nrf5340_flash_wait_ready();
+#if MYNEWT_VAL(BOOT_LOADER) || MYNEWT_VAL(MCU_APP_SECURE)
NRF_NVMC_S->CONFIG = NVMC_CONFIG_WEN_Ren;
+#else
+ NRF_NVMC_NS->CONFIGNS = NVMC_CONFIGNS_WEN_Ren;
+#endif
__HAL_ENABLE_INTERRUPTS(sr);
return rc;
[mynewt-core] 09/10: mcu/nrf5340: Add system start for non-secure
application
Posted by je...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
jerzy pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit a8cd86b2fd5960a6a63ff4fd275cab4d45b2f816
Author: Jerzy Kasenberg <je...@codecoup.pl>
AuthorDate: Wed Oct 20 16:38:40 2021 +0200
mcu/nrf5340: Add system start for non-secure application
This modifies hal_system_start() to execute non-secure code.
Bootloader that runs secure code changes peripheral/memory permissions
to non-secure before jumping to application code.
Interrupts are also marked as unsecure.
---
hw/mcu/nordic/nrf5340/pkg.yml | 2 +
hw/mcu/nordic/nrf5340/src/hal_system_start.c | 91 ++++++++++++++++++++++++++++
2 files changed, 93 insertions(+)
diff --git a/hw/mcu/nordic/nrf5340/pkg.yml b/hw/mcu/nordic/nrf5340/pkg.yml
index 4ffbaec..b1dd4c9 100644
--- a/hw/mcu/nordic/nrf5340/pkg.yml
+++ b/hw/mcu/nordic/nrf5340/pkg.yml
@@ -40,6 +40,8 @@ pkg.cflags.NFC_PINS_AS_GPIO:
pkg.cflags.GPIO_AS_PIN_RESET:
- '-DCONFIG_GPIO_AS_PINRESET=1'
+pkg.cflags:
+ - -mcmse
pkg.deps.UART_0:
- "@apache-mynewt-core/hw/drivers/uart/uart_hal"
diff --git a/hw/mcu/nordic/nrf5340/src/hal_system_start.c b/hw/mcu/nordic/nrf5340/src/hal_system_start.c
index 3a2066b..fca96a4 100644
--- a/hw/mcu/nordic/nrf5340/src/hal_system_start.c
+++ b/hw/mcu/nordic/nrf5340/src/hal_system_start.c
@@ -22,6 +22,95 @@
#include <mcu/cortex_m33.h>
#include <mcu/nrf5340_hal.h>
+#if MCUBOOT_MYNEWT
+#include <bootutil/bootutil.h>
+#endif
+#include <os/util.h>
+
+#if MYNEWT_VAL(BOOT_LOADER) && !MYNEWT_VAL(MCU_APP_SECURE)
+
+struct periph_id_range {
+ uint8_t first;
+ uint8_t last;
+};
+
+/* Array of peripheral ID ranges that will be set as unsecure before bootloader jumps to application code */
+static const struct periph_id_range ns_peripheral_ids[] = {
+ { 0, 0 },
+ { 4, 6 },
+ { 8, 12 },
+ { 14, 17 },
+ { 20, 21 },
+ { 23, 36 },
+ { 38, 38 },
+ { 40, 40 },
+ { 42, 43 },
+ { 45, 45 },
+ { 48, 48 },
+ { 51, 52 },
+ { 54, 55 },
+ { 57, 57 },
+ { 66, 66 },
+ { 128, 129 },
+};
+
+void
+hal_system_start(void *img_start)
+{
+ int i;
+ int j;
+ int range_count;
+ struct flash_sector_range sr;
+ uintptr_t *img_data;
+ /* Number of 16kB flash regions used by bootloader */
+ int bootloader_flash_regions;
+ __attribute__((cmse_nonsecure_call, noreturn)) void (* app_reset)(void);
+
+ /* Mark selected peripherals as unsecure */
+ for (i = 0; i < ARRAY_SIZE(ns_peripheral_ids); ++i) {
+ for (j = ns_peripheral_ids[i].first; j <= ns_peripheral_ids[i].last; ++j) {
+ if (((NRF_SPU->PERIPHID[j].PERM & SPU_PERIPHID_PERM_PRESENT_Msk) == 0) ||
+ ((NRF_SPU->PERIPHID[j].PERM & SPU_PERIPHID_PERM_SECUREMAPPING_Msk) < SPU_PERIPHID_PERM_SECUREMAPPING_UserSelectable)) {
+ continue;
+ }
+ NRF_SPU->PERIPHID[j].PERM &= ~SPU_PERIPHID_PERM_SECATTR_Msk;
+ }
+ }
+
+ /* Route exceptions to non-secure, allow software reset from non-secure */
+ SCB->AIRCR = 0x05FA0000 | (SCB->AIRCR & (~SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk)) | SCB_AIRCR_BFHFNMINS_Msk;
+ for (i = 0; i < ARRAY_SIZE(NVIC->ITNS); ++i) {
+ NVIC->ITNS[i] = 0xFFFFFFFF;
+ }
+
+ /* Mark non-bootloader flash regions as non-secure */
+ flash_area_to_sector_ranges(FLASH_AREA_BOOTLOADER, &range_count, &sr);
+ bootloader_flash_regions = (sr.fsr_sector_count * sr.fsr_sector_size) / 0x4000;
+
+ for (i = bootloader_flash_regions; i < 64; ++i) {
+ NRF_SPU->FLASHREGION[i].PERM &= ~SPU_FLASHREGION_PERM_SECATTR_Msk;
+ }
+
+ /* Mark RAM as non-secure */
+ for (i = 0; i < 64; ++i) {
+ NRF_SPU->RAMREGION[i].PERM &= ~SPU_FLASHREGION_PERM_SECATTR_Msk;
+ }
+
+ /* Move DPPI to non-secure area */
+ NRF_SPU->DPPI->PERM = 0;
+
+ /* Move GPIO to non-secure area */
+ NRF_SPU->GPIOPORT[0].PERM = 0;
+ NRF_SPU->GPIOPORT[1].PERM = 0;
+
+ img_data = img_start;
+ app_reset = (void *)(img_data[1]);
+ __TZ_set_MSP_NS(img_data[0]);
+ app_reset();
+}
+
+#else
+
/**
* Boots the image described by the supplied image header.
*
@@ -41,6 +130,8 @@ hal_system_start(void *img_start)
: "r" (img_data[0]), "r" (img_data[1]));
}
+#endif
+
/**
* Boots the image described by the supplied image header.
* This routine is used in split-app scenario when loader decides