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Posted to commits@mynewt.apache.org by ut...@apache.org on 2019/09/24 15:36:45 UTC
[mynewt-core] 04/05: [STM32F3] Add syscfg clocking system
This is an automated email from the ASF dual-hosted git repository.
utzig pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-core.git
commit ba5e9e28cdc8b1dd2a6dce7577fdb663534784da
Author: Fabio Utzig <ut...@apache.org>
AuthorDate: Mon Sep 2 19:03:18 2019 -0300
[STM32F3] Add syscfg clocking system
---
.../nucleo-f303k8/include/bsp/stm32f3xx_hal_conf.h | 52 ++--
hw/bsp/nucleo-f303k8/src/hal_bsp.c | 2 -
hw/bsp/nucleo-f303k8/src/system_stm32f3xx.c | 312 ---------------------
hw/bsp/nucleo-f303k8/syscfg.yml | 11 +-
.../nucleo-f303re/include/bsp/stm32f3xx_hal_conf.h | 53 ++--
hw/bsp/nucleo-f303re/src/hal_bsp.c | 2 -
hw/bsp/nucleo-f303re/src/system_stm32f3xx.c | 312 ---------------------
hw/bsp/nucleo-f303re/syscfg.yml | 11 +-
.../include/bsp/stm32f3xx_hal_conf.h | 53 ++--
hw/bsp/stm32f3discovery/src/hal_bsp.c | 2 -
hw/bsp/stm32f3discovery/src/system_stm32f3xx.c | 312 ---------------------
hw/bsp/stm32f3discovery/syscfg.yml | 10 +
hw/mcu/stm/stm32f3xx/src/clock_stm32f3xx.c | 216 ++++++++++++++
hw/mcu/stm/stm32f3xx/src/hal_system_clock.c | 50 ----
hw/mcu/stm/stm32f3xx/src/system_stm32f3xx.c | 212 ++++++++++++++
hw/mcu/stm/stm32f3xx/syscfg.yml | 68 ++++-
16 files changed, 603 insertions(+), 1075 deletions(-)
diff --git a/hw/bsp/nucleo-f303k8/include/bsp/stm32f3xx_hal_conf.h b/hw/bsp/nucleo-f303k8/include/bsp/stm32f3xx_hal_conf.h
index 6483236..ce59158 100644
--- a/hw/bsp/nucleo-f303k8/include/bsp/stm32f3xx_hal_conf.h
+++ b/hw/bsp/nucleo-f303k8/include/bsp/stm32f3xx_hal_conf.h
@@ -31,12 +31,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
#define __STM32F3xx_HAL_CONF_H
+#include <syscfg/syscfg.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -46,7 +48,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
@@ -87,15 +89,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
@@ -104,25 +106,25 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
- #define LSI_VALUE (40000U)
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (40000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -131,7 +133,7 @@
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
+#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
@@ -142,7 +144,7 @@
/**
* @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
+ * This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
@@ -157,25 +159,25 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
+ */
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
#define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 0U
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1*/
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -189,7 +191,7 @@
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f3xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -236,8 +238,8 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
@@ -316,7 +318,7 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
@@ -325,8 +327,8 @@
void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
diff --git a/hw/bsp/nucleo-f303k8/src/hal_bsp.c b/hw/bsp/nucleo-f303k8/src/hal_bsp.c
index 472400a..c2b6c6e 100644
--- a/hw/bsp/nucleo-f303k8/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f303k8/src/hal_bsp.c
@@ -179,8 +179,6 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
- hal_system_clock_start();
-
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *)&hal_uart[UART_0_DEV_ID],
stm32_uart_dev_name[UART_0_DEV_ID],
diff --git a/hw/bsp/nucleo-f303k8/src/system_stm32f3xx.c b/hw/bsp/nucleo-f303k8/src/system_stm32f3xx.c
deleted file mode 100644
index 772d1db..0000000
--- a/hw/bsp/nucleo-f303k8/src/system_stm32f3xx.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f3xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f3xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F3xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- * USB Clock | DISABLE
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f3xx_system
- * @{
- */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f3xx.h"
-#include "mcu/cmsis_nvic.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 8000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
-
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR &= 0xF87FC00C;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW and TIMs bits */
- RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Relocate the vector table */
- NVIC_Relocate();
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
- else
- {
- /* HSI oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
- }
-#else
- if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/nucleo-f303k8/syscfg.yml b/hw/bsp/nucleo-f303k8/syscfg.yml
index dd0b72c..6e20700 100644
--- a/hw/bsp/nucleo-f303k8/syscfg.yml
+++ b/hw/bsp/nucleo-f303k8/syscfg.yml
@@ -48,4 +48,13 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
- MCU_SYSCLK_PLL_HSI: 0
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 0
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL16'
+ STM32_CLOCK_PREDIV: 'RCC_HSE_PREDIV_DIV1'
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV2'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_2'
+ STM32_FLASH_PREFETCH_ENABLE: 1
diff --git a/hw/bsp/nucleo-f303re/include/bsp/stm32f3xx_hal_conf.h b/hw/bsp/nucleo-f303re/include/bsp/stm32f3xx_hal_conf.h
index 6483236..3039a0b 100644
--- a/hw/bsp/nucleo-f303re/include/bsp/stm32f3xx_hal_conf.h
+++ b/hw/bsp/nucleo-f303re/include/bsp/stm32f3xx_hal_conf.h
@@ -31,12 +31,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
#define __STM32F3xx_HAL_CONF_H
+#include <syscfg/syscfg.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -46,7 +48,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
@@ -87,15 +89,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
@@ -104,25 +106,25 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
- #define LSI_VALUE (40000U)
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (49000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -131,7 +133,7 @@
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
+#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
@@ -142,7 +144,7 @@
/**
* @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
+ * This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
@@ -157,25 +159,25 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
+ */
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
#define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 0U
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1*/
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -189,7 +191,7 @@
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f3xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -236,8 +238,8 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
@@ -316,7 +318,7 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
@@ -325,13 +327,12 @@
void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CONF_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/nucleo-f303re/src/hal_bsp.c b/hw/bsp/nucleo-f303re/src/hal_bsp.c
index 5ee9626..61e42e2 100644
--- a/hw/bsp/nucleo-f303re/src/hal_bsp.c
+++ b/hw/bsp/nucleo-f303re/src/hal_bsp.c
@@ -179,8 +179,6 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
- hal_system_clock_start();
-
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *)&hal_uart[UART_0_DEV_ID],
stm32_uart_dev_name[UART_0_DEV_ID],
diff --git a/hw/bsp/nucleo-f303re/src/system_stm32f3xx.c b/hw/bsp/nucleo-f303re/src/system_stm32f3xx.c
deleted file mode 100644
index 772d1db..0000000
--- a/hw/bsp/nucleo-f303re/src/system_stm32f3xx.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f3xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f3xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F3xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- * USB Clock | DISABLE
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f3xx_system
- * @{
- */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f3xx.h"
-#include "mcu/cmsis_nvic.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 8000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
-
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR &= 0xF87FC00C;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW and TIMs bits */
- RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Relocate the vector table */
- NVIC_Relocate();
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
- else
- {
- /* HSI oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
- }
-#else
- if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/nucleo-f303re/syscfg.yml b/hw/bsp/nucleo-f303re/syscfg.yml
index 96a0bd4..5546139 100644
--- a/hw/bsp/nucleo-f303re/syscfg.yml
+++ b/hw/bsp/nucleo-f303re/syscfg.yml
@@ -48,4 +48,13 @@ syscfg.vals:
CONFIG_FCB_FLASH_AREA: FLASH_AREA_NFFS
NFFS_FLASH_AREA: FLASH_AREA_NFFS
COREDUMP_FLASH_AREA: FLASH_AREA_IMAGE_1
- MCU_SYSCLK_PLL_HSI: 0
+ STM32_CLOCK_HSI: 1
+ STM32_CLOCK_HSE: 0
+ STM32_CLOCK_HSE_BYPASS: 0
+ STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL9'
+ STM32_CLOCK_PREDIV: 'RCC_PREDIV_DIV1'
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV2'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_2'
+ STM32_FLASH_PREFETCH_ENABLE: 1
diff --git a/hw/bsp/stm32f3discovery/include/bsp/stm32f3xx_hal_conf.h b/hw/bsp/stm32f3discovery/include/bsp/stm32f3xx_hal_conf.h
index 5640df6..32094a4 100644
--- a/hw/bsp/stm32f3discovery/include/bsp/stm32f3xx_hal_conf.h
+++ b/hw/bsp/stm32f3discovery/include/bsp/stm32f3xx_hal_conf.h
@@ -31,12 +31,14 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F3xx_HAL_CONF_H
#define __STM32F3xx_HAL_CONF_H
+#include <syscfg/syscfg.h>
+
#ifdef __cplusplus
extern "C" {
#endif
@@ -46,7 +48,7 @@
/* ########################## Module Selection ############################## */
/**
- * @brief This is the list of modules to be used in the HAL driver
+ * @brief This is the list of modules to be used in the HAL driver
*/
#define HAL_MODULE_ENABLED
/* #define HAL_ADC_MODULE_ENABLED */
@@ -87,15 +89,15 @@
/**
* @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSE is used as system clock source, directly or through the PLL).
+ * (when HSE is used as system clock source, directly or through the PLL).
*/
-#if !defined (HSE_VALUE)
+#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000U) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- * Timeout value
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
+ * Timeout value
*/
#if !defined (HSE_STARTUP_TIMEOUT)
#define HSE_STARTUP_TIMEOUT (100U) /*!< Time out for HSE start up, in ms */
@@ -104,25 +106,25 @@
/**
* @brief Internal High Speed oscillator (HSI) value.
* This value is used by the RCC HAL module to compute the system frequency
- * (when HSI is used as system clock source, directly or through the PLL).
+ * (when HSI is used as system clock source, directly or through the PLL).
*/
#if !defined (HSI_VALUE)
#define HSI_VALUE (8000000U) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */
/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- * Timeout value
+ * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
+ * Timeout value
*/
-#if !defined (HSI_STARTUP_TIMEOUT)
+#if !defined (HSI_STARTUP_TIMEOUT)
#define HSI_STARTUP_TIMEOUT (5000U) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
+#endif /* HSI_STARTUP_TIMEOUT */
/**
* @brief Internal Low Speed oscillator (LSI) value.
*/
-#if !defined (LSI_VALUE)
- #define LSI_VALUE (40000U)
+#if !defined (LSI_VALUE)
+ #define LSI_VALUE (40000U)
#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
The real value may vary depending on the variations
in voltage and temperature. */
@@ -131,7 +133,7 @@
*/
#if !defined (LSE_VALUE)
#define LSE_VALUE (32768U) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
+#endif /* LSE_VALUE */
/**
* @brief Time out for LSE start up value in ms.
@@ -142,7 +144,7 @@
/**
* @brief External clock source for I2S peripheral
- * This value is used by the I2S HAL module to compute the I2S clock source
+ * This value is used by the I2S HAL module to compute the I2S clock source
* frequency, this source is inserted directly through I2S_CKIN pad.
* - External clock generated through external PLL component on EVAL 303 (based on MCO or crystal)
* - External clock not generated on EVAL 373
@@ -157,25 +159,25 @@
/* ########################### System Configuration ######################### */
/**
* @brief This is the HAL system configuration section
- */
+ */
#define VDD_VALUE (3300U) /*!< Value of VDD in mv */
#define TICK_INT_PRIORITY ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U) /*!< tick interrupt priority (lowest by default) */
#define USE_RTOS 0U
-#define PREFETCH_ENABLE 1U
+#define PREFETCH_ENABLE MYNEWT_VAL(STM32_FLASH_PREFETCH_ENABLE)
#define INSTRUCTION_CACHE_ENABLE 0U
#define DATA_CACHE_ENABLE 0U
#define USE_SPI_CRC 0U
/* ########################## Assert Selection ############################## */
/**
- * @brief Uncomment the line below to expanse the "assert_param" macro in the
+ * @brief Uncomment the line below to expanse the "assert_param" macro in the
* HAL drivers code
*/
/*#define USE_FULL_ASSERT 1*/
/* Includes ------------------------------------------------------------------*/
/**
- * @brief Include module's header file
+ * @brief Include module's header file
*/
#ifdef HAL_RCC_MODULE_ENABLED
@@ -189,7 +191,7 @@
#ifdef HAL_DMA_MODULE_ENABLED
#include "stm32f3xx_hal_dma.h"
#endif /* HAL_DMA_MODULE_ENABLED */
-
+
#ifdef HAL_CORTEX_MODULE_ENABLED
#include "stm32f3xx_hal_cortex.h"
#endif /* HAL_CORTEX_MODULE_ENABLED */
@@ -236,8 +238,8 @@
#ifdef HAL_PCCARD_MODULE_ENABLED
#include "stm32f3xx_hal_pccard.h"
-#endif /* HAL_PCCARD_MODULE_ENABLED */
-
+#endif /* HAL_PCCARD_MODULE_ENABLED */
+
#ifdef HAL_HRTIM_MODULE_ENABLED
#include "stm32f3xx_hal_hrtim.h"
#endif /* HAL_HRTIM_MODULE_ENABLED */
@@ -316,7 +318,7 @@
* @brief The assert_param macro is used for function's parameters check.
* @param expr: If expr is false, it calls assert_failed function
* which reports the name of the source file and the source
- * line number of the call that failed.
+ * line number of the call that failed.
* If expr is true, it returns no value.
* @retval None
*/
@@ -325,13 +327,12 @@
void assert_failed(char* file, uint32_t line);
#else
#define assert_param(expr) ((void)0U)
-#endif /* USE_FULL_ASSERT */
-
+#endif /* USE_FULL_ASSERT */
+
#ifdef __cplusplus
}
#endif
#endif /* __STM32F3xx_HAL_CONF_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/bsp/stm32f3discovery/src/hal_bsp.c b/hw/bsp/stm32f3discovery/src/hal_bsp.c
index c1a935b..3471a36 100644
--- a/hw/bsp/stm32f3discovery/src/hal_bsp.c
+++ b/hw/bsp/stm32f3discovery/src/hal_bsp.c
@@ -162,8 +162,6 @@ hal_bsp_init(void)
int rc;
(void)rc; /* in case there are no devices declared */
- hal_system_clock_start();
-
#if MYNEWT_VAL(UART_0)
rc = os_dev_create((struct os_dev *)&hal_uart[0], UART_DEV_NAME,
OS_DEV_INIT_PRIMARY, 0, uart_hal_init, (void *)&uart_cfg[0]);
diff --git a/hw/bsp/stm32f3discovery/src/system_stm32f3xx.c b/hw/bsp/stm32f3discovery/src/system_stm32f3xx.c
deleted file mode 100644
index 772d1db..0000000
--- a/hw/bsp/stm32f3discovery/src/system_stm32f3xx.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f3xx.c
- * @author MCD Application Team
- * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f3xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. This file configures the system clock as follows:
- *=============================================================================
- * Supported STM32F3xx device
- *-----------------------------------------------------------------------------
- * System Clock source | HSI
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 8000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- * USB Clock | DISABLE
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f3xx_system
- * @{
- */
-
-/** @addtogroup STM32F3xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f3xx.h"
-#include "mcu/cmsis_nvic.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Defines
- * @{
- */
-#if !defined (HSE_VALUE)
- #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined (HSI_VALUE)
- #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
- This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
- Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
- This value must be a multiple of 0x200. */
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Variables
- * @{
- */
- /* This variable is updated in three ways:
- 1) by calling CMSIS function SystemCoreClockUpdate()
- 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
- 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
- Note: If you use this function to configure the system clock there is no need to
- call the 2 first functions listed above, since SystemCoreClock variable is
- updated automatically.
- */
-uint32_t SystemCoreClock = 8000000;
-
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F3xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system
- * Initialize the FPU setting, vector table location and the PLL configuration is reset.
- * @param None
- * @retval None
- */
-void SystemInit(void)
-{
- /* FPU settings ------------------------------------------------------------*/
- #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
- #endif
-
- /* Reset the RCC clock configuration to the default reset state ------------*/
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset CFGR register */
- RCC->CFGR &= 0xF87FC00C;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
- RCC->CFGR &= (uint32_t)0xFF80FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW and TIMs bits */
- RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Relocate the vector table */
- NVIC_Relocate();
-}
-
-/**
- * @brief Update SystemCoreClock variable according to Clock Register Values.
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
-#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx)
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
- {
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
- else
- {
- /* HSI oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
- }
-#else
- if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
- }
-#endif /* STM32F302xE || STM32F303xE || STM32F398xx */
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/hw/bsp/stm32f3discovery/syscfg.yml b/hw/bsp/stm32f3discovery/syscfg.yml
index 924afef..3e1f35b 100644
--- a/hw/bsp/stm32f3discovery/syscfg.yml
+++ b/hw/bsp/stm32f3discovery/syscfg.yml
@@ -49,3 +49,13 @@ syscfg.vals:
BOOT_SERIAL_DETECT_PIN: 0 # USER button
BOOT_SERIAL_DETECT_PIN_CFG: 'HAL_GPIO_PULL_NONE'
BOOT_SERIAL_DETECT_PIN_VAL: 1
+ STM32_CLOCK_HSI: 0
+ STM32_CLOCK_HSE: 1
+ STM32_CLOCK_HSE_BYPASS: 1
+ STM32_CLOCK_PLL_MUL: 'RCC_PLL_MUL9'
+ STM32_CLOCK_PREDIV: 'RCC_HSE_PREDIV_DIV1'
+ STM32_CLOCK_AHB_DIVIDER: 'RCC_SYSCLK_DIV1'
+ STM32_CLOCK_APB1_DIVIDER: 'RCC_HCLK_DIV2'
+ STM32_CLOCK_APB2_DIVIDER: 'RCC_HCLK_DIV1'
+ STM32_FLASH_LATENCY: 'FLASH_LATENCY_2'
+ STM32_FLASH_PREFETCH_ENABLE: 1
diff --git a/hw/mcu/stm/stm32f3xx/src/clock_stm32f3xx.c b/hw/mcu/stm/stm32f3xx/src/clock_stm32f3xx.c
new file mode 100644
index 0000000..a57b95e
--- /dev/null
+++ b/hw/mcu/stm/stm32f3xx/src/clock_stm32f3xx.c
@@ -0,0 +1,216 @@
+/*
+ * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "stm32f3xx_hal_pwr_ex.h"
+#include "stm32f3xx_hal_rcc.h"
+#include "stm32f3xx_hal.h"
+#include <assert.h>
+
+/*
+ * This allows an user to have a custom clock configuration by zeroing
+ * every possible clock source in the syscfg.
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSE) || MYNEWT_VAL(STM32_CLOCK_LSE) || \
+ MYNEWT_VAL(STM32_CLOCK_HSI) || MYNEWT_VAL(STM32_CLOCK_LSI)
+
+/*
+ * HSI is turned on by default, but can be turned off and use HSE instead.
+ */
+#if (((MYNEWT_VAL(STM32_CLOCK_HSE) != 0) + (MYNEWT_VAL(STM32_CLOCK_HSI) != 0)) < 1)
+#error "At least one of HSE or HSI clock source must be enabled"
+#endif
+
+void
+SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef osc_init;
+ RCC_ClkInitTypeDef clk_init;
+ HAL_StatusTypeDef status;
+
+ /*
+ * Enable Power Control clock
+ */
+ __HAL_RCC_PWR_CLK_ENABLE();
+
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+
+ /*
+ * LSI is used to clock the independent watchdog and optionally the RTC.
+ * It can be disabled per user request, but is automatically enabled again
+ * when the IWDG is started.
+ *
+ * XXX currently the watchdog is not optional, so there's no point in
+ * disabling LSI through syscfg.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSI;
+#if MYNEWT_VAL(STM32_CLOCK_LSI)
+ osc_init.LSIState = RCC_LSI_ON;
+#else
+ osc_init.LSIState = RCC_LSI_OFF;
+#endif
+
+ /*
+ * LSE is only used to clock the RTC.
+ */
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_LSE;
+#if (MYNEWT_VAL(STM32_CLOCK_LSE) == 0)
+ osc_init.LSEState = RCC_LSE_OFF;
+#elif MYNEWT_VAL(STM32_CLOCK_LSE_BYPASS)
+ osc_init.LSEState = RCC_LSE_BYPASS;
+#else
+ osc_init.LSEState = RCC_LSE_ON;
+#endif
+
+ /*
+ * HSE Oscillator (can be used as PLL, SYSCLK and RTC clock source)
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSE)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+#if MYNEWT_VAL(STM32_CLOCK_HSE_BYPASS)
+ osc_init.HSEState = RCC_HSE_BYPASS;
+#else
+ osc_init.HSEState = RCC_HSE_ON;
+#endif
+#endif
+
+ /*
+ * HSI Oscillator (can be used as PLL and SYSCLK clock source). It is
+ * already turned on by default but a new calibration setting might be
+ * used. If the user chooses to turn it off, it must be turned off after
+ * SYSCLK was updated to use HSE/PLL.
+ */
+#if MYNEWT_VAL(STM32_CLOCK_HSI)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_ON;
+ /* HSI calibration is not optional when HSI is enabled */
+ osc_init.HSICalibrationValue = MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION);
+
+#if MYNEWT_VAL(STM32_CLOCK_HSI) && \
+ !IS_RCC_CALIBRATION_VALUE(MYNEWT_VAL(STM32_CLOCK_HSI_CALIBRATION))
+#error "Invalid HSI calibration value"
+#endif
+#endif
+
+ /*
+ * Default to HSE as source, when both HSE and HSI are enabled.
+ */
+ osc_init.PLL.PLLState = RCC_PLL_ON;
+#if MYNEWT_VAL(STM32_CLOCK_HSE)
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+#else
+ osc_init.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+#endif
+
+#if !IS_RCC_PLL_MUL(MYNEWT_VAL(STM32_CLOCK_PLL_MUL))
+#error "PLL MUL value is invalid"
+#endif
+
+ osc_init.PLL.PLLMUL = MYNEWT_VAL(STM32_CLOCK_PLL_MUL);
+
+ /*
+ * xD/xE series implement the divider block after PLLSRC; other families
+ * do it before the signal goes into PLLSRC. When the divider is connected
+ * before the PLLSRC, it is connected only to HSE, and HSI has a
+ * non-optional /2 divider.
+ */
+#if defined(RCC_CFGR_PLLSRC_HSI_DIV2)
+# if !IS_RCC_HSE_PREDIV(MYNEWT_VAL(STM32_CLOCK_PREDIV))
+# error "HSE PREDIV value is invalid"
+# endif
+ osc_init.HSEPredivValue = MYNEWT_VAL(STM32_CLOCK_PREDIV);
+#else
+# if !IS_RCC_PREDIV(MYNEWT_VAL(STM32_CLOCK_PREDIV))
+# error "PLL PREDIV value is invalid"
+# endif
+ osc_init.PLL.PREDIV = MYNEWT_VAL(STM32_CLOCK_PREDIV);
+#endif
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+ /*
+ * Select PLL as system clock source and configure the HCLK, PCLK1 and
+ * PCLK2 clocks dividers. HSI and HSE are also valid system clock sources,
+ * although there is no much point in supporting them now.
+ */
+ clk_init.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK |
+ RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ clk_init.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+
+#if !IS_RCC_HCLK(MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER))
+#error "AHB clock divider is invalid"
+#endif
+
+#if !IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER))
+#error "APB1 clock divider is invalid"
+#endif
+
+#if !IS_RCC_PCLK(MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER))
+#error "APB2 clock divider is invalid"
+#endif
+
+ clk_init.AHBCLKDivider = MYNEWT_VAL(STM32_CLOCK_AHB_DIVIDER);
+ clk_init.APB1CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB1_DIVIDER);
+ clk_init.APB2CLKDivider = MYNEWT_VAL(STM32_CLOCK_APB2_DIVIDER);
+
+#if !IS_FLASH_LATENCY(MYNEWT_VAL(STM32_FLASH_LATENCY))
+#error "Flash latency value is invalid"
+#endif
+
+ status = HAL_RCC_ClockConfig(&clk_init, MYNEWT_VAL(STM32_FLASH_LATENCY));
+ if (status != HAL_OK) {
+ assert(0);
+ }
+
+#if ((MYNEWT_VAL(STM32_CLOCK_HSI) == 0) || (MYNEWT_VAL(STM32_CLOCK_HSE) == 0))
+ /*
+ * Turn off HSE/HSI oscillator; this must be done at the end because
+ * SYSCLK source has to be updated first.
+ */
+ osc_init.OscillatorType = RCC_OSCILLATORTYPE_NONE;
+#if (MYNEWT_VAL(STM32_CLOCK_HSE) == 0)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSE;
+ osc_init.HSEState = RCC_HSE_OFF;
+#endif
+#if (MYNEWT_VAL(STM32_CLOCK_HSI) == 0)
+ osc_init.OscillatorType |= RCC_OSCILLATORTYPE_HSI;
+ osc_init.HSIState = RCC_HSI_OFF;
+#endif
+ osc_init.PLL.PLLState = RCC_PLL_NONE;
+
+ status = HAL_RCC_OscConfig(&osc_init);
+ if (status != HAL_OK) {
+ assert(0);
+ }
+#endif
+
+#if PREFETCH_ENABLE
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif
+}
+#endif
diff --git a/hw/mcu/stm/stm32f3xx/src/hal_system_clock.c b/hw/mcu/stm/stm32f3xx/src/hal_system_clock.c
deleted file mode 100644
index c339923..0000000
--- a/hw/mcu/stm/stm32f3xx/src/hal_system_clock.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Licensed to the Apache Software Foundation (ASF) under one
- * or more contributor license agreements. See the NOTICE file
- * distributed with this work for additional information
- * regarding copyright ownership. The ASF licenses this file
- * to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance
- * with the License. You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing,
- * software distributed under the License is distributed on an
- * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
- * KIND, either express or implied. See the License for the
- * specific language governing permissions and limitations
- * under the License.
- */
-
-#include <assert.h>
-#include <hal/hal_system.h>
-#include <mcu/cortex_m4.h>
-#include "stm32f3xx_hal.h"
-#include "stm32f3xx_hal_rcc.h"
-
-void
-hal_system_clock_start(void)
-{
-#if MYNEWT_VAL(MCU_SYSCLK_PLL_HSI)
- RCC_OscInitTypeDef osc;
- RCC_ClkInitTypeDef clk;
-
- osc.OscillatorType = RCC_OSCILLATORTYPE_NONE;
- osc.PLL.PLLState = RCC_PLL_ON;
- osc.PLL.PLLSource = RCC_PLLSOURCE_HSI;
-#if defined(RCC_CFGR_PLLSRC_HSI_PREDIV)
- osc.PLL.PREDIV = RCC_PREDIV_DIV2;
-#endif
- osc.PLL.PLLMUL = RCC_PLL_MUL16;
- osc.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- assert(HAL_OK == HAL_RCC_OscConfig(&osc));
-
- clk.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
- clk.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
- clk.AHBCLKDivider = RCC_SYSCLK_DIV1;
- clk.APB1CLKDivider = RCC_HCLK_DIV2;
- clk.APB2CLKDivider = RCC_HCLK_DIV1;
- assert(HAL_OK == HAL_RCC_ClockConfig(&clk, FLASH_LATENCY_2));
-#endif
-}
diff --git a/hw/mcu/stm/stm32f3xx/src/system_stm32f3xx.c b/hw/mcu/stm/stm32f3xx/src/system_stm32f3xx.c
new file mode 100644
index 0000000..57c6526
--- /dev/null
+++ b/hw/mcu/stm/stm32f3xx/src/system_stm32f3xx.c
@@ -0,0 +1,212 @@
+/**
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+#include "bsp/stm32f3xx_hal_conf.h"
+#include "stm32f3xx.h"
+#include "mcu/cmsis_nvic.h"
+
+/*
+ * This variable is updated in three ways:
+ * 1) by calling CMSIS function SystemCoreClockUpdate()
+ * 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+ * 3) each time HAL_RCC_ClockConfig() is called to configure the system clock
+ * frequency
+ * Note: If you use this function to configure the system clock; then there
+ * is no need to call the 2 first functions listed above, since SystemCoreClock
+ * variable is updated automatically.
+ */
+uint32_t SystemCoreClock;
+const uint8_t AHBPrescTable[16] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
+};
+const uint8_t APBPrescTable[8] = {
+ 0, 0, 0, 0, 1, 2, 3, 4
+};
+
+/*
+ * XXX BSP specific
+ */
+void SystemClock_Config(void);
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and the PLL configuration is reset.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /*
+ * FPU settings
+ */
+
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ /* set CP10 and CP11 Full Access */
+ SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2));
+#endif
+
+ /*
+ * Reset the RCC clock configuration to the default reset state
+ */
+
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR &= 0xF87FC00C;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE bits */
+ RCC->CFGR &= (uint32_t)0xFF80FFFF;
+
+ /* Reset PREDIV1[3:0] bits */
+ RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
+
+ /* Reset USARTSW[1:0], I2CSW and TIMs bits */
+ RCC->CFGR3 &= (uint32_t)0xFF00FCCC;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+ /* Configure System Clock */
+ SystemClock_Config();
+
+ /* Update SystemCoreClock global variable */
+ SystemCoreClockUpdate();
+
+ /* Relocate the vector table */
+ NVIC_Relocate();
+}
+
+/**
+ * @brief Update SystemCoreClock variable according to Clock Register Values.
+ * The SystemCoreClock variable contains the core clock (HCLK), it can
+ * be used by the user application to setup the SysTick timer or configure
+ * other parameters.
+ *
+ * @note Each time the core clock (HCLK) changes, this function must be called
+ * to update SystemCoreClock variable value. Otherwise, any configuration
+ * based on this variable will be incorrect.
+ *
+ * @note - The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
+ * constant and the selected clock source:
+ *
+ * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+ *
+ * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+ *
+ * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ *
+ * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+ * 8 MHz) but the real value may vary depending on the variations
+ * in voltage and temperature.
+ *
+ * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value
+ * 8 MHz), user has to ensure that HSE_VALUE is same as the real
+ * frequency of the crystal used. Otherwise, this function may
+ * have wrong result.
+ *
+ * - The result of this function could be not correct when using fractional
+ * value for HSE crystal.
+ *
+ * @param None
+ * @retval None
+ */
+void SystemCoreClockUpdate (void)
+{
+ uint32_t tmp;
+ uint32_t pllmull;
+ uint32_t pllsource;
+ uint32_t predivfactor;
+
+ /*
+ * Get SYSCLK source
+ */
+
+ tmp = RCC->CFGR & RCC_CFGR_SWS;
+ switch (tmp) {
+ /* HSE used as system clock */
+ case RCC_CFGR_SWS_HSE:
+ SystemCoreClock = HSE_VALUE;
+ break;
+
+ /* PLL used as system clock */
+ case RCC_CFGR_SWS_PLL:
+ /*
+ * Get PLL clock source and multiplication factor
+ */
+ pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
+ pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
+ pllmull = (pllmull >> 18) + 2;
+
+#if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) {
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ } else {
+ /* HSI oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull;
+ }
+#else
+ if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) {
+ /* HSI oscillator clock divided by 2 selected as PLL clock entry */
+ SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
+ } else {
+ predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
+ /* HSE oscillator clock selected as PREDIV1 clock entry */
+ SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull;
+ }
+#endif
+ break;
+
+ /* HSI used as system clock */
+ default:
+ SystemCoreClock = HSI_VALUE;
+ break;
+ }
+
+ /*
+ * Compute HCLK clock frequency
+ */
+
+ /* Get HCLK prescaler */
+ tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+
+ /* HCLK clock frequency */
+ SystemCoreClock >>= tmp;
+}
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/hw/mcu/stm/stm32f3xx/syscfg.yml b/hw/mcu/stm/stm32f3xx/syscfg.yml
index 38a90de..b5a1cd3 100644
--- a/hw/mcu/stm/stm32f3xx/syscfg.yml
+++ b/hw/mcu/stm/stm32f3xx/syscfg.yml
@@ -27,6 +27,70 @@ syscfg.defs:
description: MCUs are of STM32F3xx family
value: 1
+ STM32_CLOCK_LSI:
+ description: Enable low-speed internal clock source
+ value: 1
+
+ STM32_CLOCK_LSE:
+ description: Enable low-speed external clock source (aka RTC xtal)
+ value: 0
+
+ STM32_CLOCK_LSE_BYPASS:
+ description: 0 for 32768 xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSE:
+ description: Enable high-speed external clock source
+ value: 0
+
+ STM32_CLOCK_HSE_BYPASS:
+ description: 0 for xtal; 1 for input clock
+ value: 0
+
+ STM32_CLOCK_HSI:
+ description: Enable high-speed internal clock source
+ value: 1
+
+ STM32_CLOCK_HSI_CALIBRATION:
+ description: HSI calibration value
+ value: 'RCC_HSICALIBRATION_DEFAULT'
+
+ STM32_CLOCK_PLL_MUL:
+ description: PLL clock multiplication
+ value: 0
+
+ STM32_CLOCK_PREDIV:
+ description: Clock divider (pre or post PLL)
+ value: 0
+
+ STM32_CLOCK_AHB_DIVIDER:
+ description: AHB prescaler
+ value: 0
+
+ STM32_CLOCK_APB1_DIVIDER:
+ description: APB low-speed prescaler
+ value: 0
+
+ STM32_CLOCK_APB2_DIVIDER:
+ description: APB high-speed prescaler
+ value: 0
+
+ STM32_FLASH_LATENCY:
+ description: Number of wait-states
+ value: 0
+
+ STM32_FLASH_PREFETCH_ENABLE:
+ description: Enable pre-fetch of instructions (when latency > 0)
+ value: 0
+
+ STM32_INSTRUCTION_CACHE_ENABLE:
+ description: Enable flash instruction cache
+ value: 0
+
+ STM32_DATA_CACHE_ENABLE:
+ description: Enable flash data cache
+ value: 0
+
STM32_HAL_SPI_HAS_FIFO:
description: This MCU has a SPI with FIFO
value: 1
@@ -51,10 +115,6 @@ syscfg.defs:
description: This MCU's Flash sector size in bytes.
value: 2048
- MCU_SYSCLK_PLL_HSI:
- description: Configure PLL as sysclock driven by HSI.
- value: 0
-
SPI_0_MASTER:
description: 'SPI 0 master'
value: 0