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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2021/04/15 19:04:22 UTC
[GitHub] [incubator-nuttx] davids5 opened a new pull request #3557: stm32h7 Add serial RX and TX DMA
davids5 opened a new pull request #3557:
URL: https://github.com/apache/incubator-nuttx/pull/3557
## Summary
This adds DMA support to the stm32h7 serial driver.
## Impact
Lowers load a 3Mbps
## Testing
px4_fmu-v6x, nucleo-h743zi
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[GitHub] [incubator-nuttx] davids5 commented on a change in pull request #3557: stm32h7 Add serial RX and TX DMA
Posted by GitBox <gi...@apache.org>.
davids5 commented on a change in pull request #3557:
URL: https://github.com/apache/incubator-nuttx/pull/3557#discussion_r615087180
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -2324,10 +3619,10 @@ void arm_serialinit(void)
int ret;
#endif
+#ifdef CONFIG_PM
/* Register to receive power management callbacks */
-#ifdef CONFIG_PM
- ret = pm_register(&g_serialcb);
+ ret = pm_register(&g_serialpm.pm_cb);
Review comment:
It is squashed ...
```
stm32h7:Serial Apply formatting suggestions from code review
Co-authored-by: Mateusz Szafoni <ra...@gmail.com>
stm32h7: Serail Add Power Managment (Untested)
```
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[GitHub] [incubator-nuttx] davids5 commented on a change in pull request #3557: stm32h7 Add serial RX and TX DMA
Posted by GitBox <gi...@apache.org>.
davids5 commented on a change in pull request #3557:
URL: https://github.com/apache/incubator-nuttx/pull/3557#discussion_r614771421
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -2324,10 +3619,10 @@ void arm_serialinit(void)
int ret;
#endif
+#ifdef CONFIG_PM
/* Register to receive power management callbacks */
-#ifdef CONFIG_PM
- ret = pm_register(&g_serialcb);
+ ret = pm_register(&g_serialpm.pm_cb);
Review comment:
@raiden00pl - thank you for the thorough review! I will squash the formatting changes and fix the PM or removed it.
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[GitHub] [incubator-nuttx] raiden00pl commented on a change in pull request #3557: stm32h7 Add serial RX and TX DMA
Posted by GitBox <gi...@apache.org>.
raiden00pl commented on a change in pull request #3557:
URL: https://github.com/apache/incubator-nuttx/pull/3557#discussion_r614579684
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -63,6 +65,410 @@
#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART)
+/* DMA configuration */
+
+/* If DMA is enabled on any USART, then very that other pre-requisites
+ * have also been selected.
+ */
+
+#ifdef SERIAL_HAVE_RXDMA
+
+/* Verify that RX DMA configuration. */
+
+# if defined(CONFIG_USART1_RXDMA)
+# if !defined(DMAMAP_USART1_RX)
+# error "USART1 DMA map not defined (DMAMAP_USART1_RX)"
+# endif
+# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART2_RXDMA)
+# if !defined(DMAMAP_USART2_RX)
+# error "USART2 DMA map not defined (DMAMAP_USART2_RX)"
+# endif
+# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART3_RXDMA)
+# if !defined(DMAMAP_USART3_RX)
+# error "USART3 DMA map not defined (DMAMAP_USART3_RX)"
+# endif
+# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART4_RXDMA)
+# if !defined(DMAMAP_UART4_RX)
+# error "UART4 DMA map not defined (DMAMAP_UART4_RX)"
+# endif
+# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART5_RXDMA)
+# if !defined(DMAMAP_UART5_RX)
+# error "UART5 DMA map not defined (DMAMAP_UART5_RX)"
+# endif
+# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART6_RXDMA)
+# if !defined(DMAMAP_USART6_RX)
+# error "USART6 DMA map not defined (DMAMAP_USART6_RX)"
+# endif
+# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART7_RXDMA)
+# if !defined(DMAMAP_UART7_RX)
+# error "UART7 DMA map not defined (DMAMAP_UART7_RX)"
+# endif
+# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART8_RXDMA)
+# if !defined(DMAMAP_UART8_RX)
+# error "UART8 DMA map not defined (DMAMAP_UART8_RX)"
+# endif
+# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+/* Currently RS-485 support cannot be enabled when RXDMA is in use due to
+ * lack of testing - RS-485 support was developed on STM32F1x
+ */
+
+# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
+ (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
+ (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
+ (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
+ (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
+ (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485)) || \
+ (defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_RS485)) || \
+ (defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_RS485))
+# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
+# endif
+
+/* The DMA buffer size when using RX DMA to emulate a FIFO.
+ *
+ * When streaming data, the generic serial layer will be called every time
+ * the FIFO receives half this number of bytes.
+ *
+ * This buffer size should be an even multiple of the Cortex-M7 D-Cache line
+ * size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated.
+ *
+ * Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
+ * would be zero!
+ */
+
+# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
+# undef ARMV7M_DCACHE_LINESIZE
+# define ARMV7M_DCACHE_LINESIZE 32
+# endif
+
+# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \
+ (CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE)
+# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE
+# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE
+# endif
+
+# define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
+# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \
+ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
+
+/* DMA priority */
+
+# ifndef CONFIG_USART_RXDMAPRIO
+# define CONFIG_USART_RXDMAPRIO DMA_SCR_PRIMED
+# endif
+
+# if (CONFIG_USART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0
+# error "Illegal value for CONFIG_USART_RXDMAPRIO"
+# endif
+
+/* DMA control words */
+
+# define SERIAL_RXDMA_CONTROL_WORD \
+ (DMA_SCR_DIR_P2M | \
+ DMA_SCR_CIRC | \
+ DMA_SCR_MINC | \
+ DMA_SCR_PSIZE_8BITS | \
+ DMA_SCR_MSIZE_8BITS | \
+ CONFIG_USART_RXDMAPRIO | \
+ DMA_SCR_PBURST_SINGLE | \
+ DMA_SCR_MBURST_SINGLE)
+
+#endif /* SERIAL_HAVE_RXDMA */
+
+#ifdef SERIAL_HAVE_TXDMA
+
+/* Verify that TX DMA configuration. */
+
+# if defined(CONFIG_USART1_TXDMA)
+# if !defined(DMAMAP_USART1_TX)
+# error "USART1 DMA map not defined (DMAMAP_USART1_TX)"
+# endif
+# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART2_TXDMA)
+# if !defined(DMAMAP_USART2_TX)
+# error "USART2 DMA map not defined (DMAMAP_USART2_TX)"
+# endif
+# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART3_TXDMA)
+# if !defined(DMAMAP_USART3_TX)
+# error "USART3 DMA map not defined (DMAMAP_USART3_TX)"
+# endif
+# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART4_TXDMA)
+# if !defined(DMAMAP_UART4_TX)
+# error "UART4 DMA map not defined (DMAMAP_UART4_TX)"
+# endif
+# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART5_TXDMA)
+# if !defined(DMAMAP_UART5_TX)
+# error "UART5 DMA map not defined (DMAMAP_UART5_TX)"
+# endif
+# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART6_TXDMA)
+# if !defined(DMAMAP_USART6_TX)
+# error "USART6 DMA map not defined (DMAMAP_USART6_TX)"
+# endif
+# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART7_TXDMA)
+# if !defined(DMAMAP_UART7_TX)
+# error "UART7 DMA map not defined (DMAMAP_UART7_TX)"
+# endif
+# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART8_TXDMA)
+# if !defined(DMAMAP_UART8_TX)
+# error "UART8 DMA map not defined (DMAMAP_UART8_TX)"
+# endif
+# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+#endif
Review comment:
```suggestion
#endif
```
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -2028,6 +2947,322 @@ static bool up_rxflowcontrol(struct uart_dev_s *dev,
}
#endif
+/****************************************************************************
+ * Name: up_dma_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the USART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ ****************************************************************************/
+
+#ifdef SERIAL_HAVE_RXDMA
+static int up_dma_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+ uint32_t nextrx = up_dma_nextrx(priv);
+ int c = 0;
+
+ /* Check if more data is available */
+
+ if (nextrx != priv->rxdmanext)
+ {
+#ifdef CONFIG_ARMV7M_DCACHE
+ /* If the data cache is enabled, then we will also need to manage
+ * cache coherency. Are any bytes available in the currently coherent
+ * region of the data cache?
+ */
+
+ if (priv->rxdmaavail == 0)
+ {
+ uint32_t rxdmaavail;
+ uintptr_t addr;
+
+ /* No.. then we will have to invalidate additional space in the Rx
+ * DMA buffer.
+ */
+
+ if (nextrx > priv->rxdmanext)
+ {
+ /* Number of available bytes */
+
+ rxdmaavail = nextrx - priv->rxdmanext;
+ }
+ else
+ {
+ /* Number of available bytes up to the end of RXDMA buffer */
+
+ rxdmaavail = RXDMA_BUFFER_SIZE - priv->rxdmanext;
+ }
+
+ /* Invalidate the DMA buffer range */
+
+ addr = (uintptr_t)&priv->rxfifo[priv->rxdmanext];
+ up_invalidate_dcache(addr, addr + rxdmaavail);
+
+ /* We don't need to invalidate the data cache for the next
+ * rxdmaavail number of next bytes.
+ */
+
+ priv->rxdmaavail = rxdmaavail;
+ }
+
+ priv->rxdmaavail--;
+#endif
+
+ /* Now read from the DMA buffer */
+
+ c = priv->rxfifo[priv->rxdmanext];
+
+ priv->rxdmanext++;
+ if (priv->rxdmanext == RXDMA_BUFFER_SIZE)
+ {
+ priv->rxdmanext = 0;
+ }
+ }
+
+ /* NOTE: If no data is available, then we would return NULL which is,
+ * of course, valid binary data. The protocol is that the upper half
+ * driver must call up_dma_rxavailable prior to calling this function to
+ * assure that this never happens.
+ */
+
+ return c;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_dma_reenable
+ *
+ * Description:
+ * Call to re-enable RX DMA.
+ *
+ ****************************************************************************/
+
+#if defined(SERIAL_HAVE_RXDMA) && defined(CONFIG_PM)
+static void up_dma_reenable(struct up_dev_s *priv)
+{
+ struct stm32_dma_config_s rxdmacfg;
+
+ /* Configure for circular DMA reception into the RX FIFO */
+
+ rxdmacfg.paddr = priv->usartbase + STM32_USART_RDR_OFFSET;
+ rxdmacfg.maddr = (uint32_t)priv->rxfifo;
+ rxdmacfg.ndata = RXDMA_BUFFER_SIZE;
+ rxdmacfg.cfg1 = SERIAL_RXDMA_CONTROL_WORD;
+ rxdmacfg.cfg2 = 0;
+ stm32_dmasetup(priv->rxdma, &rxdmacfg);
+
+ /* Reset our DMA shadow pointer and Rx data availability count to match
+ * the address just programmed above.
+ */
+
+ priv->rxdmanext = 0;
+#ifdef CONFIG_ARMV7M_DCACHE
+ priv->rxdmaavail = 0;
+#endif
+
+ /* Start the DMA channel, and arrange for callbacks at the half and
+ * full points in the FIFO. This ensures that we have half a FIFO
+ * worth of time to claim bytes before they are overwritten.
+ */
+
+ stm32_dmastart(priv->rxdma, up_dma_rxcallback, (void *)priv, true);
+
+ /* Clear DMA suspended flag. */
+
+ priv->rxdmasusp = false;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_dma_rxint
+ *
+ * Description:
+ * Call to enable or disable RX interrupts
+ *
+ ****************************************************************************/
+
+#ifdef SERIAL_HAVE_RXDMA
+static void up_dma_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Enable/disable DMA reception.
+ *
+ * Note that it is not safe to check for available bytes and immediately
+ * pass them to uart_recvchars as that could potentially recurse back
+ * to us again. Instead, bytes must wait until the next up_dma_poll or
+ * DMA event.
+ */
+
+ priv->rxenable = enable;
+}
+#endif
+
+/****************************************************************************
+ * Name: up_dma_rxavailable
+ *
+ * Description:
+ * Return true if the receive register is not empty
+ *
+ ****************************************************************************/
+
+#ifdef SERIAL_HAVE_RXDMA
+static bool up_dma_rxavailable(struct uart_dev_s *dev)
+{
+ struct up_dev_s *priv = (struct up_dev_s *)dev->priv;
+
+ /* Compare our receive pointer to the current DMA pointer, if they
+ * do not match, then there are bytes to be received.
+ */
+
+ return (up_dma_nextrx(priv) != priv->rxdmanext);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_dma_txcallback
+ *
+ * Description:
+ * This function clears dma buffer at complete of DMA transfer and wakes up
+ * threads waiting for space in buffer.
+ *
+ ****************************************************************************/
+
+#ifdef SERIAL_HAVE_TXDMA
+static void up_dma_txcallback(DMA_HANDLE handle, uint8_t status, void *arg)
+{
+ struct stm32_dma_config_s txdmacfg;
+ struct up_dev_s *priv = (struct up_dev_s *)arg;
+
+ /* Update 'nbytes' indicating number of bytes actually transferred by DMA.
+ * This is important to free TX buffer space by 'uart_xmitchars_done'.
+ */
+
+ if (status & DMA_SCR_HTIE)
+ {
+ priv->dev.dmatx.nbytes += priv->dev.dmatx.length / 2;
+ }
+ else if (status & DMA_SCR_TCIE)
+ {
+ priv->dev.dmatx.nbytes += priv->dev.dmatx.length;
+ if (priv->dev.dmatx.nlength)
+ {
+ /* Set up DMA on next buffer */
+
+ txdmacfg.paddr = priv->usartbase + STM32_USART_TDR_OFFSET;
+ txdmacfg.maddr = (uint32_t) priv->dev.dmatx.nbuffer;
+ txdmacfg.ndata = (size_t) priv->dev.dmatx.nlength;
+ txdmacfg.cfg1 = SERIAL_TXDMA_CONTROL_WORD;
+ txdmacfg.cfg2 = 0;
+ stm32_dmasetup(priv->txdma, &txdmacfg);
+
+ /* Set length for next completion */
+
+ priv->dev.dmatx.length = priv->dev.dmatx.nlength;
+ priv->dev.dmatx.nlength = 0;
+
+ /* Start transmission with the callback on DMA completion */
+
+ stm32_dmastart(priv->txdma, up_dma_txcallback,
+ (void *)priv, false);
+
+ return;
+ }
+ }
+
+ nxsem_post(&priv->txdmasem);
+
+ /* Adjust the pointers */
+
+ uart_xmitchars_done(&priv->dev);
+}
+#endif
+
+/****************************************************************************
+ * Name: up_dma_txavailable
+ *
+ * Description:
+ * Informs DMA that Tx data is available and is ready for transfer.
Review comment:
```suggestion
* Informs DMA that Tx data is available and is ready for transfer.
```
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -63,6 +65,410 @@
#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART)
+/* DMA configuration */
+
+/* If DMA is enabled on any USART, then very that other pre-requisites
Review comment:
```suggestion
/* If DMA is enabled on any USART, then verify that other pre-requisites
```
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -2324,10 +3619,10 @@ void arm_serialinit(void)
int ret;
#endif
+#ifdef CONFIG_PM
/* Register to receive power management callbacks */
-#ifdef CONFIG_PM
- ret = pm_register(&g_serialcb);
+ ret = pm_register(&g_serialpm.pm_cb);
Review comment:
g_serialpm is not defined in this file. Probably `static struct pm_callback_s g_serialcb` should be replaced with `static struct pm_config_s g_serialpm`
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -63,6 +65,410 @@
#define STM32_NSERIAL (STM32H7_NUSART + STM32H7_NUART)
+/* DMA configuration */
+
+/* If DMA is enabled on any USART, then very that other pre-requisites
+ * have also been selected.
+ */
+
+#ifdef SERIAL_HAVE_RXDMA
+
+/* Verify that RX DMA configuration. */
+
+# if defined(CONFIG_USART1_RXDMA)
+# if !defined(DMAMAP_USART1_RX)
+# error "USART1 DMA map not defined (DMAMAP_USART1_RX)"
+# endif
+# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART1 using DMAMAP_DMA12_USART1RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART1_RX == DMAMAP_DMA12_USART1RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART1 using DMAMAP_DMA12_USART1RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART2_RXDMA)
+# if !defined(DMAMAP_USART2_RX)
+# error "USART2 DMA map not defined (DMAMAP_USART2_RX)"
+# endif
+# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART2 using DMAMAP_DMA12_USART2RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART2_RX == DMAMAP_DMA12_USART2RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART2 using DMAMAP_DMA12_USART2RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART3_RXDMA)
+# if !defined(DMAMAP_USART3_RX)
+# error "USART3 DMA map not defined (DMAMAP_USART3_RX)"
+# endif
+# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART3 using DMAMAP_DMA12_USART3RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART3_RX == DMAMAP_DMA12_USART3RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART3 using DMAMAP_DMA12_USART3RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART4_RXDMA)
+# if !defined(DMAMAP_UART4_RX)
+# error "UART4 DMA map not defined (DMAMAP_UART4_RX)"
+# endif
+# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART4 using DMAMAP_DMA12_UART4RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART4_RX == DMAMAP_DMA12_UART4RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART4 using DMAMAP_DMA12_UART4RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART5_RXDMA)
+# if !defined(DMAMAP_UART5_RX)
+# error "UART5 DMA map not defined (DMAMAP_UART5_RX)"
+# endif
+# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART5 using DMAMAP_DMA12_UART5RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART5_RX == DMAMAP_DMA12_UART5RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART5 using DMAMAP_DMA12_UART5RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART6_RXDMA)
+# if !defined(DMAMAP_USART6_RX)
+# error "USART6 DMA map not defined (DMAMAP_USART6_RX)"
+# endif
+# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART6 using DMAMAP_DMA12_USART6RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART6_RX == DMAMAP_DMA12_USART6RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART6 using DMAMAP_DMA12_USART6RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART7_RXDMA)
+# if !defined(DMAMAP_UART7_RX)
+# error "UART7 DMA map not defined (DMAMAP_UART7_RX)"
+# endif
+# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART7 using DMAMAP_DMA12_UART7RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART7_RX == DMAMAP_DMA12_UART7RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART7 using DMAMAP_DMA12_UART7RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART8_RXDMA)
+# if !defined(DMAMAP_UART8_RX)
+# error "UART8 DMA map not defined (DMAMAP_UART8_RX)"
+# endif
+# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART8 using DMAMAP_DMA12_UART8RX_0 for receive DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART8_RX == DMAMAP_DMA12_UART8RX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART8 using DMAMAP_DMA12_UART8RX_1 for receive DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+/* Currently RS-485 support cannot be enabled when RXDMA is in use due to
+ * lack of testing - RS-485 support was developed on STM32F1x
+ */
+
+# if (defined(CONFIG_USART1_RXDMA) && defined(CONFIG_USART1_RS485)) || \
+ (defined(CONFIG_USART2_RXDMA) && defined(CONFIG_USART2_RS485)) || \
+ (defined(CONFIG_USART3_RXDMA) && defined(CONFIG_USART3_RS485)) || \
+ (defined(CONFIG_UART4_RXDMA) && defined(CONFIG_UART4_RS485)) || \
+ (defined(CONFIG_UART5_RXDMA) && defined(CONFIG_UART5_RS485)) || \
+ (defined(CONFIG_USART6_RXDMA) && defined(CONFIG_USART6_RS485)) || \
+ (defined(CONFIG_UART7_RXDMA) && defined(CONFIG_UART7_RS485)) || \
+ (defined(CONFIG_UART8_RXDMA) && defined(CONFIG_UART8_RS485))
+# error "RXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
+# endif
+
+/* The DMA buffer size when using RX DMA to emulate a FIFO.
+ *
+ * When streaming data, the generic serial layer will be called every time
+ * the FIFO receives half this number of bytes.
+ *
+ * This buffer size should be an even multiple of the Cortex-M7 D-Cache line
+ * size, ARMV7M_DCACHE_LINESIZE, so that it can be individually invalidated.
+ *
+ * Should there be a Cortex-M7 without a D-Cache, ARMV7M_DCACHE_LINESIZE
+ * would be zero!
+ */
+
+# if !defined(ARMV7M_DCACHE_LINESIZE) || ARMV7M_DCACHE_LINESIZE == 0
+# undef ARMV7M_DCACHE_LINESIZE
+# define ARMV7M_DCACHE_LINESIZE 32
+# endif
+
+# if !defined(CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE) || \
+ (CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE < ARMV7M_DCACHE_LINESIZE)
+# undef CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE
+# define CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE ARMV7M_DCACHE_LINESIZE
+# endif
+
+# define RXDMA_BUFFER_MASK (ARMV7M_DCACHE_LINESIZE - 1)
+# define RXDMA_BUFFER_SIZE ((CONFIG_STM32H7_SERIAL_RXDMA_BUFFER_SIZE \
+ + RXDMA_BUFFER_MASK) & ~RXDMA_BUFFER_MASK)
+
+/* DMA priority */
+
+# ifndef CONFIG_USART_RXDMAPRIO
+# define CONFIG_USART_RXDMAPRIO DMA_SCR_PRIMED
+# endif
+
+# if (CONFIG_USART_RXDMAPRIO & ~DMA_SCR_PL_MASK) != 0
+# error "Illegal value for CONFIG_USART_RXDMAPRIO"
+# endif
+
+/* DMA control words */
+
+# define SERIAL_RXDMA_CONTROL_WORD \
+ (DMA_SCR_DIR_P2M | \
+ DMA_SCR_CIRC | \
+ DMA_SCR_MINC | \
+ DMA_SCR_PSIZE_8BITS | \
+ DMA_SCR_MSIZE_8BITS | \
+ CONFIG_USART_RXDMAPRIO | \
+ DMA_SCR_PBURST_SINGLE | \
+ DMA_SCR_MBURST_SINGLE)
+
+#endif /* SERIAL_HAVE_RXDMA */
+
+#ifdef SERIAL_HAVE_TXDMA
+
+/* Verify that TX DMA configuration. */
+
+# if defined(CONFIG_USART1_TXDMA)
+# if !defined(DMAMAP_USART1_TX)
+# error "USART1 DMA map not defined (DMAMAP_USART1_TX)"
+# endif
+# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART1 using DMAMAP_DMA12_USART1TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART1_TX == DMAMAP_DMA12_USART1TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART1 using DMAMAP_DMA12_USART1TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART2_TXDMA)
+# if !defined(DMAMAP_USART2_TX)
+# error "USART2 DMA map not defined (DMAMAP_USART2_TX)"
+# endif
+# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART2 using DMAMAP_DMA12_USART2TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART2_TX == DMAMAP_DMA12_USART2TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART2 using DMAMAP_DMA12_USART2TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART3_TXDMA)
+# if !defined(DMAMAP_USART3_TX)
+# error "USART3 DMA map not defined (DMAMAP_USART3_TX)"
+# endif
+# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART3 using DMAMAP_DMA12_USART3TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART3_TX == DMAMAP_DMA12_USART3TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART3 using DMAMAP_DMA12_USART3TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART4_TXDMA)
+# if !defined(DMAMAP_UART4_TX)
+# error "UART4 DMA map not defined (DMAMAP_UART4_TX)"
+# endif
+# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART4 using DMAMAP_DMA12_UART4TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART4_TX == DMAMAP_DMA12_UART4TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART4 using DMAMAP_DMA12_UART4TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART5_TXDMA)
+# if !defined(DMAMAP_UART5_TX)
+# error "UART5 DMA map not defined (DMAMAP_UART5_TX)"
+# endif
+# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART5 using DMAMAP_DMA12_UART5TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART5_TX == DMAMAP_DMA12_UART5TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART5 using DMAMAP_DMA12_UART5TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_USART6_TXDMA)
+# if !defined(DMAMAP_USART6_TX)
+# error "USART6 DMA map not defined (DMAMAP_USART6_TX)"
+# endif
+# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 USART6 using DMAMAP_DMA12_USART6TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_USART6_TX == DMAMAP_DMA12_USART6TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 USART6 using DMAMAP_DMA12_USART6TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART7_TXDMA)
+# if !defined(DMAMAP_UART7_TX)
+# error "UART7 DMA map not defined (DMAMAP_UART7_TX)"
+# endif
+# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART7 using DMAMAP_DMA12_UART7TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART7_TX == DMAMAP_DMA12_UART7TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART7 using DMAMAP_DMA12_UART7TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+
+# if defined(CONFIG_UART8_TXDMA)
+# if !defined(DMAMAP_UART8_TX)
+# error "UART8 DMA map not defined (DMAMAP_UART8_TX)"
+# endif
+# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_0 && !defined(CONFIG_STM32H7_DMA1)
+# error STM32 UART8 using DMAMAP_DMA12_UART8TX_0 for transmit DMA requires CONFIG_STM32H7_DMA1
+# endif
+# if DMAMAP_UART8_TX == DMAMAP_DMA12_UART8TX_1 && !defined(CONFIG_STM32H7_DMA2)
+# error STM32 UART8 using DMAMAP_DMA12_UART8TX_1 for transmit DMA requires CONFIG_STM32H7_DMA2
+# endif
+# endif
+#endif
+/* Currently RS-485 support cannot be enabled when TXDMA is in use due to
+ * lack of testing - RS-485 support was developed on STM32F1x
+ */
+
+# if (defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RS485)) || \
+ (defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RS485)) || \
+ (defined(CONFIG_USART3_TXDMA) && defined(CONFIG_USART3_RS485)) || \
+ (defined(CONFIG_UART4_TXDMA) && defined(CONFIG_UART4_RS485)) || \
+ (defined(CONFIG_UART5_TXDMA) && defined(CONFIG_UART5_RS485)) || \
+ (defined(CONFIG_USART6_TXDMA) && defined(CONFIG_USART6_RS485)) || \
+ (defined(CONFIG_UART7_TXDMA) && defined(CONFIG_UART7_RS485)) || \
+ (defined(CONFIG_UART8_TXDMA) && defined(CONFIG_UART8_RS485))
+# error "TXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
+# endif
Review comment:
```suggestion
#if (defined(CONFIG_USART1_TXDMA) && defined(CONFIG_USART1_RS485)) || \
(defined(CONFIG_USART2_TXDMA) && defined(CONFIG_USART2_RS485)) || \
(defined(CONFIG_USART3_TXDMA) && defined(CONFIG_USART3_RS485)) || \
(defined(CONFIG_UART4_TXDMA) && defined(CONFIG_UART4_RS485)) || \
(defined(CONFIG_UART5_TXDMA) && defined(CONFIG_UART5_RS485)) || \
(defined(CONFIG_USART6_TXDMA) && defined(CONFIG_USART6_RS485)) || \
(defined(CONFIG_UART7_TXDMA) && defined(CONFIG_UART7_RS485)) || \
(defined(CONFIG_UART8_TXDMA) && defined(CONFIG_UART8_RS485))
# error "TXDMA and RS-485 cannot be enabled at the same time for the same U[S]ART"
#endif
```
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[GitHub] [incubator-nuttx] raiden00pl merged pull request #3557: stm32h7 Add serial RX and TX DMA
Posted by GitBox <gi...@apache.org>.
raiden00pl merged pull request #3557:
URL: https://github.com/apache/incubator-nuttx/pull/3557
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[GitHub] [incubator-nuttx] davids5 commented on a change in pull request #3557: stm32h7 Add serial RX and TX DMA
Posted by GitBox <gi...@apache.org>.
davids5 commented on a change in pull request #3557:
URL: https://github.com/apache/incubator-nuttx/pull/3557#discussion_r615085773
##########
File path: arch/arm/src/stm32h7/stm32_serial.c
##########
@@ -2324,10 +3619,10 @@ void arm_serialinit(void)
int ret;
#endif
+#ifdef CONFIG_PM
/* Register to receive power management callbacks */
-#ifdef CONFIG_PM
- ret = pm_register(&g_serialcb);
+ ret = pm_register(&g_serialpm.pm_cb);
Review comment:
@raiden00pl - I pulled in the PM from the F7 which is closer to one that works and have marked it untested.
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