You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@mynewt.apache.org by an...@apache.org on 2022/02/16 08:16:13 UTC
[mynewt-nimble] 01/04: ble_ll: Add BabbleSim support
This is an automated email from the ASF dual-hosted git repository.
andk pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/mynewt-nimble.git
commit bf31ad05b7e560821a2a8764842b06e080a54614
Author: Magdalena Kasenberg <ma...@codecoup.pl>
AuthorDate: Tue Nov 2 15:36:10 2021 +0100
ble_ll: Add BabbleSim support
Co-authored-by: Jakub Rotkiewicz <ja...@codecoup.pl>
---
nimble/controller/src/ble_ll.c | 4 +
nimble/controller/src/ble_ll_rand.c | 7 ++
nimble/drivers/nrf52/src/ble_hw.c | 24 ++--
nimble/drivers/nrf52/src/ble_phy.c | 243 +++++++++++++++++++++++-------------
4 files changed, 182 insertions(+), 96 deletions(-)
diff --git a/nimble/controller/src/ble_ll.c b/nimble/controller/src/ble_ll.c
index ec40925..5d3cb63 100644
--- a/nimble/controller/src/ble_ll.c
+++ b/nimble/controller/src/ble_ll.c
@@ -358,12 +358,16 @@ static void ble_ll_event_dbuf_overflow(struct ble_npl_event *ev);
#if MYNEWT
+#if BABBLESIM
+#define BLE_LL_STACK_SIZE (4000)
+#else
/* The BLE LL task data structure */
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_EXT_ADV)
#define BLE_LL_STACK_SIZE (120)
#else
#define BLE_LL_STACK_SIZE (90)
#endif
+#endif
struct os_task g_ble_ll_task;
diff --git a/nimble/controller/src/ble_ll_rand.c b/nimble/controller/src/ble_ll_rand.c
index 8aa7127..06e5d12 100644
--- a/nimble/controller/src/ble_ll_rand.c
+++ b/nimble/controller/src/ble_ll_rand.c
@@ -33,6 +33,10 @@
#include "trng/trng.h"
#endif
+#if BABBLESIM
+extern void tm_tick(void);
+#endif
+
#if MYNEWT_VAL(TRNG)
static struct trng_dev *g_trng;
#else
@@ -116,6 +120,9 @@ ble_ll_rand_data_get(uint8_t *buf, uint8_t len)
while ((g_ble_ll_rnum_data.rnd_size < len) &&
(g_ble_ll_rnum_data.rnd_size < MYNEWT_VAL(BLE_LL_RNG_BUFSIZE))) {
/* Spin here */
+#if BABBLESIM
+ tm_tick();
+#endif
}
}
}
diff --git a/nimble/drivers/nrf52/src/ble_hw.c b/nimble/drivers/nrf52/src/ble_hw.c
index 79a7772..ef4c28b 100644
--- a/nimble/drivers/nrf52/src/ble_hw.c
+++ b/nimble/drivers/nrf52/src/ble_hw.c
@@ -34,6 +34,8 @@
#include <nimble/nimble_npl_os.h>
#endif
#include "os/os_trace_api.h"
+#include <hal/nrf_rng.h>
+#include "hal/nrf_ecb.h"
/* Total number of resolving list elements */
#define BLE_HW_RESOLV_LIST_SIZE (16)
@@ -44,6 +46,10 @@ static uint8_t g_ble_hw_whitelist_mask;
/* Random number generator isr callback */
ble_rng_isr_cb_t g_ble_rng_isr_cb;
+#if BABBLESIM
+extern void tm_tick(void);
+#endif
+
/* If LL privacy is enabled, allocate memory for AAR */
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_PRIVACY)
@@ -263,14 +269,14 @@ ble_hw_encrypt_block(struct ble_encryption_block *ecb)
uint32_t err;
/* Stop ECB */
- NRF_ECB->TASKS_STOPECB = 1;
+ nrf_ecb_task_trigger(NRF_ECB, NRF_ECB_TASK_STOPECB);
/* XXX: does task stop clear these counters? Anyway to do this quicker? */
NRF_ECB->EVENTS_ENDECB = 0;
NRF_ECB->EVENTS_ERRORECB = 0;
NRF_ECB->ECBDATAPTR = (uint32_t)ecb;
/* Start ECB */
- NRF_ECB->TASKS_STARTECB = 1;
+ nrf_ecb_task_trigger(NRF_ECB, NRF_ECB_TASK_STARTECB);
/* Wait till error or done */
rc = 0;
@@ -283,6 +289,9 @@ ble_hw_encrypt_block(struct ble_encryption_block *ecb)
}
break;
}
+#if BABBLESIM
+ tm_tick();
+#endif
}
return rc;
@@ -300,7 +309,7 @@ ble_rng_isr(void)
/* No callback? Clear and disable interrupts */
if (g_ble_rng_isr_cb == NULL) {
- NRF_RNG->INTENCLR = 1;
+ nrf_rng_int_disable(NRF_RNG, NRF_RNG_INT_VALRDY_MASK);
NRF_RNG->EVENTS_VALRDY = 0;
(void)NRF_RNG->SHORTS;
os_trace_isr_exit();
@@ -365,10 +374,11 @@ ble_hw_rng_start(void)
/* No need for interrupt if there is no callback */
OS_ENTER_CRITICAL(sr);
NRF_RNG->EVENTS_VALRDY = 0;
+
if (g_ble_rng_isr_cb) {
- NRF_RNG->INTENSET = 1;
+ nrf_rng_int_enable(NRF_RNG, NRF_RNG_INT_VALRDY_MASK);
}
- NRF_RNG->TASKS_START = 1;
+ nrf_rng_task_trigger(NRF_RNG, NRF_RNG_TASK_START);
OS_EXIT_CRITICAL(sr);
return 0;
@@ -386,8 +396,8 @@ ble_hw_rng_stop(void)
/* No need for interrupt if there is no callback */
OS_ENTER_CRITICAL(sr);
- NRF_RNG->INTENCLR = 1;
- NRF_RNG->TASKS_STOP = 1;
+ nrf_rng_int_disable(NRF_RNG, NRF_RNG_INT_VALRDY_MASK);
+ nrf_rng_task_trigger(NRF_RNG, NRF_RNG_TASK_STOP);
NRF_RNG->EVENTS_VALRDY = 0;
OS_EXIT_CRITICAL(sr);
diff --git a/nimble/drivers/nrf52/src/ble_phy.c b/nimble/drivers/nrf52/src/ble_phy.c
index 7a12bb5..6752413 100644
--- a/nimble/drivers/nrf52/src/ble_phy.c
+++ b/nimble/drivers/nrf52/src/ble_phy.c
@@ -20,6 +20,12 @@
#include <stdint.h>
#include <string.h>
#include <assert.h>
+#include <hal/nrf_radio.h>
+#include <hal/nrf_ccm.h>
+#include <hal/nrf_aar.h>
+#include <hal/nrf_timer.h>
+#include <hal/nrf_ppi.h>
+#include <hal/nrf_rtc.h>
#include "syscfg/syscfg.h"
#include "os/os.h"
/* Keep os_cputime explicitly to enable build on non-Mynewt platforms */
@@ -47,6 +53,10 @@
#endif
#endif
+#if BABBLESIM
+extern void tm_tick(void);
+#endif
+
/*
* NOTE: This code uses a couple of PPI channels so care should be taken when
* using PPI somewhere else.
@@ -165,6 +175,37 @@ static const uint16_t g_ble_phy_mode_pkt_start_off[BLE_PHY_NUM_MODE] = {
/* Radio ramp-up times in usecs (fast mode) */
#define BLE_PHY_T_TXENFAST (XCVR_TX_RADIO_RAMPUP_USECS)
#define BLE_PHY_T_RXENFAST (XCVR_RX_RADIO_RAMPUP_USECS)
+
+#if BABBLESIM
+/* delay between EVENTS_READY and start of tx */
+static const uint8_t g_ble_phy_t_txdelay[BLE_PHY_NUM_MODE] = {
+ [BLE_PHY_MODE_1M] = 0,
+ [BLE_PHY_MODE_2M] = 3,
+ [BLE_PHY_MODE_CODED_125KBPS] = 5,
+ [BLE_PHY_MODE_CODED_500KBPS] = 5
+};
+/* delay between EVENTS_END and end of txd packet */
+static const uint8_t g_ble_phy_t_txenddelay[BLE_PHY_NUM_MODE] = {
+ [BLE_PHY_MODE_1M] = 1,
+ [BLE_PHY_MODE_2M] = 3,
+ [BLE_PHY_MODE_CODED_125KBPS] = 9,
+ [BLE_PHY_MODE_CODED_500KBPS] = 3
+};
+/* delay between rxd access address (w/ TERM1 for coded) and EVENTS_ADDRESS */
+static const uint8_t g_ble_phy_t_rxaddrdelay[BLE_PHY_NUM_MODE] = {
+ [BLE_PHY_MODE_1M] = 9,
+ [BLE_PHY_MODE_2M] = 2,
+ [BLE_PHY_MODE_CODED_125KBPS] = 17,
+ [BLE_PHY_MODE_CODED_500KBPS] = 17
+};
+/* delay between end of rxd packet and EVENTS_END */
+static const uint8_t g_ble_phy_t_rxenddelay[BLE_PHY_NUM_MODE] = {
+ [BLE_PHY_MODE_1M] = 9,
+ [BLE_PHY_MODE_2M] = 2,
+ [BLE_PHY_MODE_CODED_125KBPS] = 27,
+ [BLE_PHY_MODE_CODED_500KBPS] = 22
+};
+#else
/* delay between EVENTS_READY and start of tx */
static const uint8_t g_ble_phy_t_txdelay[BLE_PHY_NUM_MODE] = {
[BLE_PHY_MODE_1M] = 4,
@@ -193,6 +234,7 @@ static const uint8_t g_ble_phy_t_rxenddelay[BLE_PHY_NUM_MODE] = {
[BLE_PHY_MODE_CODED_125KBPS] = 27,
[BLE_PHY_MODE_CODED_500KBPS] = 22
};
+#endif
/* Statistics */
STATS_SECT_START(ble_phy_stats)
@@ -303,6 +345,7 @@ static uint8_t plna_lna_idx;
#endif
+#ifndef BABBLESIM
static void
ble_phy_apply_errata_102_106_107(void)
{
@@ -313,6 +356,7 @@ ble_phy_apply_errata_102_106_107(void)
*(volatile uint32_t *)0x40001774 = ((*(volatile uint32_t *)0x40001774) &
0xfffffffe) | 0x01000000;
}
+#endif
#if (BLE_LL_BT5_PHY_SUPPORTED == 1)
@@ -527,6 +571,11 @@ ble_phy_rxpdu_copy(uint8_t *dptr, struct os_mbuf *rxpdu)
rem_len -= copy_len;
block_rem_len -= copy_len;
+#if BABBLESIM
+ memcpy(dst, src, copy_len);
+ dst += copy_len;
+ src += copy_len;
+#else
__asm__ volatile (".syntax unified \n"
" mov r4, %[len] \n"
" b 2f \n"
@@ -541,6 +590,7 @@ ble_phy_rxpdu_copy(uint8_t *dptr, struct os_mbuf *rxpdu)
:
: "r3", "r4", "memory"
);
+#endif
if ((rem_len < 4) && (block_rem_len >= rem_len)) {
break;
@@ -553,6 +603,10 @@ ble_phy_rxpdu_copy(uint8_t *dptr, struct os_mbuf *rxpdu)
/* Copy remaining bytes, if any, to last mbuf */
om->om_len += rem_len;
+
+#if BABBLESIM
+ memcpy(dst, src, rem_len);
+#else
__asm__ volatile (".syntax unified \n"
" b 2f \n"
"1: ldrb r3, [%[src], %[len]] \n"
@@ -563,6 +617,7 @@ ble_phy_rxpdu_copy(uint8_t *dptr, struct os_mbuf *rxpdu)
: [dst] "r" (dst), [src] "r" (src)
: "r3", "memory"
);
+#endif
/* Copy header */
memcpy(BLE_MBUF_HDR_PTR(rxpdu), &g_ble_phy_data.rxhdr,
@@ -587,6 +642,9 @@ nrf_wait_disabled(void)
while (NRF_RADIO->STATE == state) {
/* If this fails, something is really wrong. Should last
* no more than 6 usecs */
+#if BABBLESIM
+ tm_tick();
+#endif
}
}
}
@@ -658,17 +716,17 @@ ble_phy_set_start_time(uint32_t cputime, uint8_t rem_usecs, bool tx)
}
/* Clear and set TIMER0 to fire off at proper time */
- NRF_TIMER0->TASKS_CLEAR = 1;
- NRF_TIMER0->CC[0] = rem_usecs;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_CLEAR);
+ nrf_timer_cc_set(NRF_TIMER0, 0, rem_usecs);
NRF_TIMER0->EVENTS_COMPARE[0] = 0;
/* Set RTC compare to start TIMER0 */
NRF_RTC0->EVENTS_COMPARE[0] = 0;
- NRF_RTC0->CC[0] = next_cc;
- NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
+ nrf_rtc_cc_set(NRF_RTC0, 0, next_cc);
+ nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE0_Msk);
/* Enable PPI */
- NRF_PPI->CHENSET = PPI_CHEN_CH31_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH31_Msk);
/* Store the cputime at which we set the RTC */
g_ble_phy_data.phy_start_cputime = cputime;
@@ -688,8 +746,8 @@ ble_phy_set_start_now(void)
* Set TIMER0 to fire immediately. We can't set CC to 0 as compare will not
* occur in such case.
*/
- NRF_TIMER0->TASKS_CLEAR = 1;
- NRF_TIMER0->CC[0] = 1;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_CLEAR);
+ nrf_timer_cc_set(NRF_TIMER0, 0, 1);
NRF_TIMER0->EVENTS_COMPARE[0] = 0;
/*
@@ -700,12 +758,11 @@ ble_phy_set_start_now(void)
*/
now = os_cputime_get32();
NRF_RTC0->EVENTS_COMPARE[0] = 0;
- NRF_RTC0->CC[0] = now + 3;
- NRF_RTC0->EVTENSET = RTC_EVTENSET_COMPARE0_Msk;
+ nrf_rtc_cc_set(NRF_RTC0, 0, now + 3);
+ nrf_rtc_event_enable(NRF_RTC0, RTC_EVTENSET_COMPARE0_Msk);
/* Enable PPI */
- NRF_PPI->CHENSET = PPI_CHEN_CH31_Msk;
-
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH31_Msk);
/*
* Store the cputime at which we set the RTC
*
@@ -780,11 +837,11 @@ ble_phy_wfr_enable(int txrx, uint8_t tx_phy_mode, uint32_t wfr_usecs)
end_time += g_ble_phy_t_rxaddrdelay[phy];
/* wfr_secs is the time from rxen until timeout */
- NRF_TIMER0->CC[3] = end_time;
+ nrf_timer_cc_set(NRF_TIMER0, 3, end_time);
NRF_TIMER0->EVENTS_COMPARE[3] = 0;
/* Enable wait for response PPI */
- NRF_PPI->CHENSET = (PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk);
+ nrf_ppi_channels_enable(NRF_PPI, (PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk));
/*
* It may happen that if CPU is halted for a brief moment (e.g. during flash
@@ -798,10 +855,10 @@ ble_phy_wfr_enable(int txrx, uint8_t tx_phy_mode, uint32_t wfr_usecs)
* CC[1] is only used as a reference on RX start, we do not need it here so
* it can be used to read TIMER0 counter.
*/
- NRF_TIMER0->TASKS_CAPTURE[1] = 1;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_CAPTURE1);
if (NRF_TIMER0->CC[1] > NRF_TIMER0->CC[3]) {
- NRF_PPI->CHENCLR = PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk;
- NRF_RADIO->TASKS_DISABLE = 1;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk);
+ nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_DISABLE);
}
}
@@ -854,8 +911,8 @@ ble_phy_rx_xcvr_setup(void)
NRF_CCM->SHORTS = 0;
NRF_CCM->EVENTS_ERROR = 0;
NRF_CCM->EVENTS_ENDCRYPT = 0;
- NRF_CCM->TASKS_KSGEN = 1;
- NRF_PPI->CHENSET = PPI_CHEN_CH25_Msk;
+ nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH25_Msk);
} else {
NRF_RADIO->PACKETPTR = (uint32_t)dptr;
}
@@ -879,7 +936,7 @@ ble_phy_rx_xcvr_setup(void)
#endif
/* Turn off trigger TXEN on output compare match and AAR on bcmatch */
- NRF_PPI->CHENCLR = PPI_CHEN_CH20_Msk | PPI_CHEN_CH23_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH20_Msk | PPI_CHEN_CH23_Msk);
/* Reset the rx started flag. Used for the wait for response */
g_ble_phy_data.phy_rx_started = 0;
@@ -901,7 +958,7 @@ ble_phy_rx_xcvr_setup(void)
#endif
/* I want to know when 1st byte received (after address) */
- NRF_RADIO->BCC = 8 + g_ble_phy_data.phy_bcc_offset; /* in bits */
+ nrf_radio_bcc_set(NRF_RADIO, 8 + g_ble_phy_data.phy_bcc_offset); /* in bits */
NRF_RADIO->EVENTS_ADDRESS = 0;
NRF_RADIO->EVENTS_DEVMATCH = 0;
NRF_RADIO->EVENTS_BCMATCH = 0;
@@ -913,8 +970,8 @@ ble_phy_rx_xcvr_setup(void)
RADIO_SHORTS_ADDRESS_RSSISTART_Msk |
RADIO_SHORTS_DISABLED_RSSISTOP_Msk;
- NRF_RADIO->INTENSET = RADIO_INTENSET_ADDRESS_Msk |
- RADIO_INTENSET_DISABLED_Msk;
+ nrf_radio_int_enable(NRF_RADIO, RADIO_INTENSET_ADDRESS_Msk |
+ RADIO_INTENSET_DISABLED_Msk);
}
/**
@@ -978,9 +1035,9 @@ ble_phy_tx_end_isr(void)
/* Start listening a bit earlier due to allowed active clock accuracy */
rx_time -= 2;
- NRF_TIMER0->CC[0] = rx_time;
+ nrf_timer_cc_set(NRF_TIMER0, 0, rx_time);
NRF_TIMER0->EVENTS_COMPARE[0] = 0;
- NRF_PPI->CHENSET = PPI_CHEN_CH21_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH21_Msk);
ble_phy_plna_enable_lna();
} else {
@@ -988,10 +1045,10 @@ ble_phy_tx_end_isr(void)
* XXX: not sure we need to stop the timer here all the time. Or that
* it should be stopped here.
*/
- NRF_TIMER0->TASKS_STOP = 1;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_STOP);
NRF_TIMER0->TASKS_SHUTDOWN = 1;
- NRF_PPI->CHENCLR = PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk |
- PPI_CHEN_CH20_Msk | PPI_CHEN_CH31_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk |
+ PPI_CHEN_CH20_Msk | PPI_CHEN_CH31_Msk);
assert(transition == BLE_PHY_TRANSITION_NONE);
}
}
@@ -1031,7 +1088,7 @@ ble_phy_rx_end_isr(void)
struct ble_mbuf_hdr *ble_hdr;
/* Disable automatic RXEN */
- NRF_PPI->CHENCLR = PPI_CHEN_CH21_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH21_Msk);
/* Set RSSI and CRC status flag in header */
ble_hdr = &g_ble_phy_data.rxhdr;
@@ -1107,9 +1164,9 @@ ble_phy_rx_end_isr(void)
/* Adjust for delay between EVENT_READY and actual TX start time */
tx_time -= g_ble_phy_t_txdelay[g_ble_phy_data.phy_cur_phy_mode];
- NRF_TIMER0->CC[0] = tx_time;
+ nrf_timer_cc_set(NRF_TIMER0, 0, tx_time);
NRF_TIMER0->EVENTS_COMPARE[0] = 0;
- NRF_PPI->CHENSET = PPI_CHEN_CH20_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH20_Msk);
ble_phy_plna_enable_pa();
@@ -1125,9 +1182,9 @@ ble_phy_rx_end_isr(void)
*
* Note: CC[3] is used only for wfr which we do not need here.
*/
- NRF_TIMER0->TASKS_CAPTURE[3] = 1;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_CAPTURE3);
if (NRF_TIMER0->CC[3] > NRF_TIMER0->CC[0]) {
- NRF_PPI->CHENCLR = PPI_CHEN_CH20_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH20_Msk);
g_ble_phy_data.phy_transition_late = 1;
}
@@ -1162,10 +1219,10 @@ ble_phy_rx_start_isr(void)
/* Clear events and clear interrupt */
NRF_RADIO->EVENTS_ADDRESS = 0;
- NRF_RADIO->INTENCLR = RADIO_INTENCLR_ADDRESS_Msk;
+ nrf_radio_int_disable(NRF_RADIO, RADIO_INTENCLR_ADDRESS_Msk);
/* Clear wfr timer channels */
- NRF_PPI->CHENCLR = PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk);
/* Initialize the ble mbuf header */
ble_hdr = &g_ble_phy_data.rxhdr;
@@ -1221,10 +1278,14 @@ ble_phy_rx_start_isr(void)
* something is wrong!
*/
if (state == RADIO_STATE_STATE_Disabled) {
- NRF_RADIO->INTENCLR = NRF_RADIO_IRQ_MASK_ALL;
+ nrf_radio_int_disable(NRF_RADIO, NRF_RADIO_IRQ_MASK_ALL);
NRF_RADIO->SHORTS = 0;
return false;
}
+
+#if BABBLESIM
+ tm_tick();
+#endif
}
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_PRIVACY)
@@ -1243,9 +1304,9 @@ ble_phy_rx_start_isr(void)
/* Trigger AAR after last bit of AdvA is received */
NRF_RADIO->EVENTS_BCMATCH = 0;
- NRF_PPI->CHENSET = PPI_CHEN_CH23_Msk;
- NRF_RADIO->BCC = (BLE_LL_PDU_HDR_LEN + adva_offset + BLE_DEV_ADDR_LEN) * 8 +
- g_ble_phy_data.phy_bcc_offset;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH23_Msk);
+ nrf_radio_bcc_set(NRF_RADIO, (BLE_LL_PDU_HDR_LEN + adva_offset +
+ BLE_DEV_ADDR_LEN) * 8 + g_ble_phy_data.phy_bcc_offset);
}
#endif
@@ -1276,7 +1337,7 @@ ble_phy_isr(void)
os_trace_isr_enter();
/* Read irq register to determine which interrupts are enabled */
- irq_en = NRF_RADIO->INTENCLR;
+ irq_en = NRF_RADIO->INTENSET;
/*
* NOTE: order of checking is important! Possible, if things get delayed,
@@ -1311,7 +1372,7 @@ ble_phy_isr(void)
!g_ble_phy_data.phy_rx_started));
NRF_RADIO->EVENTS_END = 0;
NRF_RADIO->EVENTS_DISABLED = 0;
- NRF_RADIO->INTENCLR = RADIO_INTENCLR_DISABLED_Msk;
+ nrf_radio_int_disable(NRF_RADIO, RADIO_INTENCLR_DISABLED_Msk);
switch (g_ble_phy_data.phy_state) {
case BLE_PHY_STATE_RX:
@@ -1397,39 +1458,40 @@ ble_phy_dbg_time_setup(void)
#if MYNEWT_VAL(BLE_PHY_DBG_TIME_TXRXEN_READY_PIN) >= 0
idx = ble_phy_gpiote_configure(MYNEWT_VAL(BLE_PHY_DBG_TIME_TXRXEN_READY_PIN));
- NRF_PPI->CH[17].EEP = (uint32_t)&(NRF_RADIO->EVENTS_READY);
- NRF_PPI->CH[17].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]);
- NRF_PPI->CHENSET = PPI_CHEN_CH17_Msk;
+ nrf_ppi_channel_endpoint_setup(NRF_PPI, 17, (uint32_t)&(NRF_RADIO->EVENTS_READY),
+ (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]));
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH17_Msk);
/* CH[20] and PPI CH[21] are on to trigger TASKS_TXEN or TASKS_RXEN */
- NRF_PPI->FORK[20].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]);
- NRF_PPI->FORK[21].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]);
+ nrf_ppi_fork_endpoint_setup(NRF_PPI, 20, (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]));
+ nrf_ppi_fork_endpoint_setup(NRF_PPI, 21, (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]));
#endif
#if MYNEWT_VAL(BLE_PHY_DBG_TIME_ADDRESS_END_PIN) >= 0
idx = ble_phy_gpiote_configure(MYNEWT_VAL(BLE_PHY_DBG_TIME_ADDRESS_END_PIN));
/* CH[26] and CH[27] are always on for EVENT_ADDRESS and EVENT_END */
- NRF_PPI->FORK[26].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]);
- NRF_PPI->FORK[27].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]);
+ nrf_ppi_fork_endpoint_setup(NRF_PPI, 26, (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]));
+ nrf_ppi_fork_endpoint_setup(NRF_PPI, 27, (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]));
#endif
#if MYNEWT_VAL(BLE_PHY_DBG_TIME_WFR_PIN) >= 0
idx = ble_phy_gpiote_configure(MYNEWT_VAL(BLE_PHY_DBG_TIME_WFR_PIN));
#if NRF52840_XXAA
- NRF_PPI->CH[18].EEP = (uint32_t)&(NRF_RADIO->EVENTS_RXREADY);
+ nrf_ppi_channel_endpoint_setup(NRF_PPI, 18, (uint32_t)&(NRF_RADIO->EVENTS_RXREADY),
+ (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]));
#else
- NRF_PPI->CH[18].EEP = (uint32_t)&(NRF_RADIO->EVENTS_READY);
+ nrf_ppi_channel_endpoint_setup(NRF_PPI, 18, (uint32_t)&(NRF_RADIO->EVENTS_READY),
+ (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]));
#endif
- NRF_PPI->CH[18].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_SET[idx]);
- NRF_PPI->CH[19].EEP = (uint32_t)&(NRF_RADIO->EVENTS_DISABLED);
- NRF_PPI->CH[19].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]);
- NRF_PPI->CHENSET = PPI_CHEN_CH18_Msk | PPI_CHEN_CH19_Msk;
+ nrf_ppi_channel_endpoint_setup(NRF_PPI, 19, (uint32_t)&(NRF_RADIO->EVENTS_DISABLED),
+ (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]));
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH18_Msk | PPI_CHEN_CH19_Msk);
/* CH[4] and CH[5] are always on for wfr */
- NRF_PPI->FORK[4].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]);
- NRF_PPI->FORK[5].TEP = (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]);
+ nrf_ppi_fork_endpoint_setup(NRF_PPI, 4, (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]));
+ nrf_ppi_fork_endpoint_setup(NRF_PPI, 5, (uint32_t)&(NRF_GPIOTE->TASKS_CLR[idx]));
#endif
}
@@ -1458,11 +1520,11 @@ ble_phy_init(void)
g_ble_phy_data.phy_chan = BLE_PHY_NUM_CHANS;
/* Toggle peripheral power to reset (just in case) */
- NRF_RADIO->POWER = 0;
- NRF_RADIO->POWER = 1;
+ nrf_radio_power_set(NRF_RADIO, false);
+ nrf_radio_power_set(NRF_RADIO, true);
/* Disable all interrupts */
- NRF_RADIO->INTENCLR = NRF_RADIO_IRQ_MASK_ALL;
+ nrf_radio_int_disable(NRF_RADIO, NRF_RADIO_IRQ_MASK_ALL);
/* Set configuration registers */
NRF_RADIO->MODE = RADIO_MODE_MODE_Ble_1Mbit;
@@ -1492,10 +1554,10 @@ ble_phy_init(void)
NRF_RADIO->TIFS = BLE_LL_IFS;
/* Captures tx/rx start in timer0 cc 1 and tx/rx end in timer0 cc 2 */
- NRF_PPI->CHENSET = PPI_CHEN_CH26_Msk | PPI_CHEN_CH27_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH26_Msk | PPI_CHEN_CH27_Msk);
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LE_ENCRYPTION)
- NRF_CCM->INTENCLR = 0xffffffff;
+ nrf_ccm_int_disable(NRF_CCM, 0xffffffff);
NRF_CCM->SHORTS = CCM_SHORTS_ENDKSGEN_CRYPT_Msk;
NRF_CCM->EVENTS_ERROR = 0;
memset(g_nrf_encrypt_scratchpad, 0, sizeof(g_nrf_encrypt_scratchpad));
@@ -1504,7 +1566,7 @@ ble_phy_init(void)
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LL_PRIVACY)
g_ble_phy_data.phy_aar_scratch = 0;
NRF_AAR->IRKPTR = (uint32_t)&g_nrf_irk_list[0];
- NRF_AAR->INTENCLR = 0xffffffff;
+ nrf_aar_int_disable(NRF_AAR, 0xffffffff);
NRF_AAR->EVENTS_END = 0;
NRF_AAR->EVENTS_RESOLVED = 0;
NRF_AAR->EVENTS_NOTRESOLVED = 0;
@@ -1512,7 +1574,7 @@ ble_phy_init(void)
#endif
/* TIMER0 setup for PHY when using RTC */
- NRF_TIMER0->TASKS_STOP = 1;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_STOP);
NRF_TIMER0->TASKS_SHUTDOWN = 1;
NRF_TIMER0->BITMODE = 3; /* 32-bit timer */
NRF_TIMER0->MODE = 0; /* Timer mode */
@@ -1525,10 +1587,12 @@ ble_phy_init(void)
* Channel 5: TIMER0 CC[3] to TASKS_DISABLE on radio. This is the wait
* for response timer.
*/
- NRF_PPI->CH[4].EEP = (uint32_t)&(NRF_RADIO->EVENTS_ADDRESS);
- NRF_PPI->CH[4].TEP = (uint32_t)&(NRF_TIMER0->TASKS_CAPTURE[3]);
- NRF_PPI->CH[5].EEP = (uint32_t)&(NRF_TIMER0->EVENTS_COMPARE[3]);
- NRF_PPI->CH[5].TEP = (uint32_t)&(NRF_RADIO->TASKS_DISABLE);
+ nrf_ppi_channel_endpoint_setup(NRF_PPI, NRF_PPI_CHANNEL4,
+ (uint32_t)&(NRF_RADIO->EVENTS_ADDRESS),
+ (uint32_t)&(NRF_TIMER0->TASKS_CAPTURE[3]));
+ nrf_ppi_channel_endpoint_setup(NRF_PPI, NRF_PPI_CHANNEL5,
+ (uint32_t)&(NRF_TIMER0->EVENTS_COMPARE[3]),
+ (uint32_t)&(NRF_RADIO->TASKS_DISABLE));
#if MYNEWT_VAL(BLE_LL_PA) || MYNEWT_VAL(BLE_LL_LNA)
#if PLNA_SINGLE_GPIO
@@ -1606,7 +1670,7 @@ ble_phy_rx(void)
}
/* Make sure all interrupts are disabled */
- NRF_RADIO->INTENCLR = NRF_RADIO_IRQ_MASK_ALL;
+ nrf_radio_int_disable(NRF_RADIO, NRF_RADIO_IRQ_MASK_ALL);
/* Clear events prior to enabling receive */
NRF_RADIO->EVENTS_END = 0;
@@ -1656,8 +1720,8 @@ ble_phy_encrypt_set_pkt_cntr(uint64_t pkt_counter, int dir)
void
ble_phy_encrypt_disable(void)
{
- NRF_PPI->CHENCLR = PPI_CHEN_CH25_Msk;
- NRF_CCM->TASKS_STOP = 1;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH25_Msk);
+ nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_STOP);
NRF_CCM->EVENTS_ERROR = 0;
NRF_CCM->ENABLE = CCM_ENABLE_ENABLE_Disabled;
@@ -1703,7 +1767,7 @@ ble_phy_tx_set_start_time(uint32_t cputime, uint8_t rem_usecs)
/* XXX: This should not be necessary, but paranoia is good! */
/* Clear timer0 compare to RXEN since we are transmitting */
- NRF_PPI->CHENCLR = PPI_CHEN_CH21_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH21_Msk);
if (ble_phy_set_start_time(cputime, rem_usecs, true) != 0) {
STATS_INC(ble_phy_stats, tx_late);
@@ -1711,7 +1775,7 @@ ble_phy_tx_set_start_time(uint32_t cputime, uint8_t rem_usecs)
rc = BLE_PHY_ERR_TX_LATE;
} else {
/* Enable PPI to automatically start TXEN */
- NRF_PPI->CHENSET = PPI_CHEN_CH20_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH20_Msk);
rc = 0;
ble_phy_plna_enable_pa();
@@ -1747,7 +1811,7 @@ ble_phy_rx_set_start_time(uint32_t cputime, uint8_t rem_usecs)
/* XXX: This should not be necessary, but paranoia is good! */
/* Clear timer0 compare to TXEN since we are transmitting */
- NRF_PPI->CHENCLR = PPI_CHEN_CH20_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH20_Msk);
if (ble_phy_set_start_time(cputime, rem_usecs, false) != 0) {
STATS_INC(ble_phy_stats, rx_late);
@@ -1759,7 +1823,7 @@ ble_phy_rx_set_start_time(uint32_t cputime, uint8_t rem_usecs)
}
/* Enable PPI to automatically start RXEN */
- NRF_PPI->CHENSET = PPI_CHEN_CH21_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH21_Msk);
ble_phy_plna_enable_lna();
@@ -1807,8 +1871,8 @@ ble_phy_tx(ble_phy_tx_pducb_t pducb, void *pducb_arg, uint8_t end_trans)
* paranoid, and if you are going to clear one, might as well clear them
* all.
*/
- NRF_PPI->CHENCLR = PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk | PPI_CHEN_CH23_Msk |
- PPI_CHEN_CH25_Msk;
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk |
+ PPI_CHEN_CH23_Msk | PPI_CHEN_CH25_Msk);
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LE_ENCRYPTION)
if (g_ble_phy_data.phy_encrypted) {
@@ -1844,7 +1908,7 @@ ble_phy_tx(ble_phy_tx_pducb_t pducb, void *pducb_arg, uint8_t end_trans)
#if MYNEWT_VAL(BLE_LL_CFG_FEAT_LE_ENCRYPTION)
/* Start key-stream generation and encryption (via short) */
if (g_ble_phy_data.phy_encrypted) {
- NRF_CCM->TASKS_KSGEN = 1;
+ nrf_ccm_task_trigger(NRF_CCM, NRF_CCM_TASK_KSGEN);
}
#endif
@@ -1858,7 +1922,7 @@ ble_phy_tx(ble_phy_tx_pducb_t pducb, void *pducb_arg, uint8_t end_trans)
/* Enable shortcuts for transmit start/end. */
shortcuts = RADIO_SHORTS_END_DISABLE_Msk | RADIO_SHORTS_READY_START_Msk;
NRF_RADIO->SHORTS = shortcuts;
- NRF_RADIO->INTENSET = RADIO_INTENSET_DISABLED_Msk;
+ nrf_radio_int_enable(NRF_RADIO, RADIO_INTENSET_DISABLED_Msk);
/* Set the PHY transition */
g_ble_phy_data.phy_transition = end_trans;
@@ -1970,8 +2034,9 @@ ble_phy_set_access_addr(uint32_t access_addr)
g_ble_phy_data.phy_access_address = access_addr;
+#ifndef BABBLESIM
ble_phy_apply_errata_102_106_107();
-
+#endif
return 0;
}
@@ -2038,9 +2103,9 @@ ble_phy_setchan(uint8_t chan, uint32_t access_addr, uint32_t crcinit)
static void
ble_phy_stop_usec_timer(void)
{
- NRF_TIMER0->TASKS_STOP = 1;
+ nrf_timer_task_trigger(NRF_TIMER0, NRF_TIMER_TASK_STOP);
NRF_TIMER0->TASKS_SHUTDOWN = 1;
- NRF_RTC0->EVTENCLR = RTC_EVTENSET_COMPARE0_Msk;
+ nrf_rtc_event_disable(NRF_RTC0, RTC_EVTENSET_COMPARE0_Msk);
}
/**
@@ -2054,13 +2119,13 @@ ble_phy_stop_usec_timer(void)
static void
ble_phy_disable_irq_and_ppi(void)
{
- NRF_RADIO->INTENCLR = NRF_RADIO_IRQ_MASK_ALL;
+ nrf_radio_int_disable(NRF_RADIO, NRF_RADIO_IRQ_MASK_ALL);
NRF_RADIO->SHORTS = 0;
- NRF_RADIO->TASKS_DISABLE = 1;
- NRF_PPI->CHENCLR = PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk | PPI_CHEN_CH20_Msk |
- PPI_CHEN_CH21_Msk | PPI_CHEN_CH23_Msk |
- PPI_CHEN_CH25_Msk | PPI_CHEN_CH31_Msk;
- NRF_PPI->CHENCLR = PPI_CHEN_CH6_Msk | PPI_CHEN_CH7_Msk;
+ nrf_radio_task_trigger(NRF_RADIO, NRF_RADIO_TASK_DISABLE);
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH4_Msk | PPI_CHEN_CH5_Msk |
+ PPI_CHEN_CH20_Msk | PPI_CHEN_CH21_Msk | PPI_CHEN_CH23_Msk |
+ PPI_CHEN_CH25_Msk | PPI_CHEN_CH31_Msk);
+ nrf_ppi_channels_disable(NRF_PPI, PPI_CHEN_CH6_Msk | PPI_CHEN_CH7_Msk);
NVIC_ClearPendingIRQ(RADIO_IRQn);
g_ble_phy_data.phy_state = BLE_PHY_STATE_IDLE;
}
@@ -2073,7 +2138,7 @@ ble_phy_restart_rx(void)
ble_phy_set_start_now();
/* Enable PPI to automatically start RXEN */
- NRF_PPI->CHENSET = PPI_CHEN_CH21_Msk;
+ nrf_ppi_channels_enable(NRF_PPI, PPI_CHEN_CH21_Msk);
ble_phy_rx();
}
@@ -2185,7 +2250,7 @@ ble_phy_rfclk_enable(void)
#if MYNEWT
nrf52_clock_hfxo_request();
#else
- NRF_CLOCK->TASKS_HFCLKSTART = 1;
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTART);
#endif
}
@@ -2195,6 +2260,6 @@ ble_phy_rfclk_disable(void)
#if MYNEWT
nrf52_clock_hfxo_release();
#else
- NRF_CLOCK->TASKS_HFCLKSTOP = 1;
+ nrf_clock_task_trigger(NRF_CLOCK, NRF_CLOCK_TASK_HFCLKSTOP);
#endif
}