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Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:04:11 UTC
[28/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/efm32.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/efm32.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/efm32.c
new file mode 100755
index 0000000..ab543d6
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/efm32.c
@@ -0,0 +1,1069 @@
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * Copyright (C) 2011 by Andreas Fritiofson *
+ * andreas.fritiofson@gmail.com *
+ * *
+ * Copyright (C) 2013 by Roman Dmitrienko *
+ * me@iamroman.org *
+ * *
+ * Copyright (C) 2014 Nemui Trinomius *
+ * nemuisan_kawausogasuki@live.jp *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+#include <target/cortex_m.h>
+
+/* keep family IDs in decimal */
+#define EFM_FAMILY_ID_GECKO 71
+#define EFM_FAMILY_ID_GIANT_GECKO 72
+#define EFM_FAMILY_ID_TINY_GECKO 73
+#define EFM_FAMILY_ID_LEOPARD_GECKO 74
+#define EFM_FAMILY_ID_WONDER_GECKO 75
+#define EFM_FAMILY_ID_ZERO_GECKO 76
+#define EFM_FAMILY_ID_HAPPY_GECKO 77
+#define EZR_FAMILY_ID_WONDER_GECKO 120
+#define EZR_FAMILY_ID_LEOPARD_GECKO 121
+
+#define EFM32_FLASH_ERASE_TMO 100
+#define EFM32_FLASH_WDATAREADY_TMO 100
+#define EFM32_FLASH_WRITE_TMO 100
+
+/* size in bytes, not words; must fit all Gecko devices */
+#define LOCKBITS_PAGE_SZ 512
+
+#define EFM32_MSC_INFO_BASE 0x0fe00000
+
+#define EFM32_MSC_USER_DATA EFM32_MSC_INFO_BASE
+#define EFM32_MSC_LOCK_BITS (EFM32_MSC_INFO_BASE+0x4000)
+#define EFM32_MSC_DEV_INFO (EFM32_MSC_INFO_BASE+0x8000)
+
+/* PAGE_SIZE is only present in Leopard, Giant and Wonder Gecko MCUs */
+#define EFM32_MSC_DI_PAGE_SIZE (EFM32_MSC_DEV_INFO+0x1e7)
+#define EFM32_MSC_DI_FLASH_SZ (EFM32_MSC_DEV_INFO+0x1f8)
+#define EFM32_MSC_DI_RAM_SZ (EFM32_MSC_DEV_INFO+0x1fa)
+#define EFM32_MSC_DI_PART_NUM (EFM32_MSC_DEV_INFO+0x1fc)
+#define EFM32_MSC_DI_PART_FAMILY (EFM32_MSC_DEV_INFO+0x1fe)
+#define EFM32_MSC_DI_PROD_REV (EFM32_MSC_DEV_INFO+0x1ff)
+
+#define EFM32_MSC_REGBASE 0x400c0000
+#define EFM32_MSC_WRITECTRL (EFM32_MSC_REGBASE+0x008)
+#define EFM32_MSC_WRITECTRL_WREN_MASK 0x1
+#define EFM32_MSC_WRITECMD (EFM32_MSC_REGBASE+0x00c)
+#define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
+#define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
+#define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
+#define EFM32_MSC_ADDRB (EFM32_MSC_REGBASE+0x010)
+#define EFM32_MSC_WDATA (EFM32_MSC_REGBASE+0x018)
+#define EFM32_MSC_STATUS (EFM32_MSC_REGBASE+0x01c)
+#define EFM32_MSC_STATUS_BUSY_MASK 0x1
+#define EFM32_MSC_STATUS_LOCKED_MASK 0x2
+#define EFM32_MSC_STATUS_INVADDR_MASK 0x4
+#define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
+#define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
+#define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
+#define EFM32_MSC_LOCK (EFM32_MSC_REGBASE+0x03c)
+#define EFM32_MSC_LOCK_LOCKKEY 0x1b71
+
+struct efm32x_flash_bank {
+ int probed;
+ uint32_t lb_page[LOCKBITS_PAGE_SZ/4];
+};
+
+struct efm32_info {
+ uint16_t flash_sz_kib;
+ uint16_t ram_sz_kib;
+ uint16_t part_num;
+ uint8_t part_family;
+ uint8_t prod_rev;
+ uint16_t page_size;
+};
+
+static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count);
+
+static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
+{
+ return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
+}
+
+static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
+{
+ return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
+}
+
+static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
+{
+ return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
+}
+
+static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
+{
+ return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
+}
+
+static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
+{
+ return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
+}
+
+static int efm32x_read_info(struct flash_bank *bank,
+ struct efm32_info *efm32_info)
+{
+ int ret;
+ uint32_t cpuid = 0;
+
+ memset(efm32_info, 0, sizeof(struct efm32_info));
+
+ ret = target_read_u32(bank->target, CPUID, &cpuid);
+ if (ERROR_OK != ret)
+ return ret;
+
+ if (((cpuid >> 4) & 0xfff) == 0xc23) {
+ /* Cortex M3 device */
+ } else if (((cpuid >> 4) & 0xfff) == 0xc24) {
+ /* Cortex M4 device(WONDER GECKO) */
+ } else if (((cpuid >> 4) & 0xfff) == 0xc60) {
+ /* Cortex M0plus device */
+ } else {
+ LOG_ERROR("Target is not Cortex-Mx Device");
+ return ERROR_FAIL;
+ }
+
+ ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
+ if (ERROR_OK != ret)
+ return ret;
+
+ if (EFM_FAMILY_ID_GECKO == efm32_info->part_family ||
+ EFM_FAMILY_ID_TINY_GECKO == efm32_info->part_family)
+ efm32_info->page_size = 512;
+ else if (EFM_FAMILY_ID_ZERO_GECKO == efm32_info->part_family ||
+ EFM_FAMILY_ID_HAPPY_GECKO == efm32_info->part_family)
+ efm32_info->page_size = 1024;
+ else if (EFM_FAMILY_ID_GIANT_GECKO == efm32_info->part_family ||
+ EFM_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
+ if (efm32_info->prod_rev >= 18) {
+ uint8_t pg_size = 0;
+ ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
+ &pg_size);
+ if (ERROR_OK != ret)
+ return ret;
+
+ efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
+ } else {
+ /* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
+ for MCUs with PROD_REV < 18 */
+ if (efm32_info->flash_sz_kib < 512)
+ efm32_info->page_size = 2048;
+ else
+ efm32_info->page_size = 4096;
+ }
+
+ if ((2048 != efm32_info->page_size) &&
+ (4096 != efm32_info->page_size)) {
+ LOG_ERROR("Invalid page size %u", efm32_info->page_size);
+ return ERROR_FAIL;
+ }
+ } else if (EFM_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
+ EZR_FAMILY_ID_WONDER_GECKO == efm32_info->part_family ||
+ EZR_FAMILY_ID_LEOPARD_GECKO == efm32_info->part_family) {
+ uint8_t pg_size = 0;
+ ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
+ &pg_size);
+ if (ERROR_OK != ret)
+ return ret;
+
+ efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
+ if (2048 != efm32_info->page_size) {
+ LOG_ERROR("Invalid page size %u", efm32_info->page_size);
+ return ERROR_FAIL;
+ }
+ } else {
+ LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+/*
+ * Helper to create a human friendly string describing a part
+ */
+static int efm32x_decode_info(struct efm32_info *info, char *buf, int buf_size)
+{
+ int printed = 0;
+
+ switch (info->part_family) {
+ case EZR_FAMILY_ID_WONDER_GECKO:
+ case EZR_FAMILY_ID_LEOPARD_GECKO:
+ printed = snprintf(buf, buf_size, "EZR32 ");
+ break;
+ default:
+ printed = snprintf(buf, buf_size, "EFM32 ");
+ }
+
+ buf += printed;
+ buf_size -= printed;
+
+ if (0 >= buf_size)
+ return ERROR_BUF_TOO_SMALL;
+
+ switch (info->part_family) {
+ case EFM_FAMILY_ID_GECKO:
+ printed = snprintf(buf, buf_size, "Gecko");
+ break;
+ case EFM_FAMILY_ID_GIANT_GECKO:
+ printed = snprintf(buf, buf_size, "Giant Gecko");
+ break;
+ case EFM_FAMILY_ID_TINY_GECKO:
+ printed = snprintf(buf, buf_size, "Tiny Gecko");
+ break;
+ case EFM_FAMILY_ID_LEOPARD_GECKO:
+ case EZR_FAMILY_ID_LEOPARD_GECKO:
+ printed = snprintf(buf, buf_size, "Leopard Gecko");
+ break;
+ case EFM_FAMILY_ID_WONDER_GECKO:
+ case EZR_FAMILY_ID_WONDER_GECKO:
+ printed = snprintf(buf, buf_size, "Wonder Gecko");
+ break;
+ case EFM_FAMILY_ID_ZERO_GECKO:
+ printed = snprintf(buf, buf_size, "Zero Gecko");
+ break;
+ case EFM_FAMILY_ID_HAPPY_GECKO:
+ printed = snprintf(buf, buf_size, "Happy Gecko");
+ break;
+ }
+
+ buf += printed;
+ buf_size -= printed;
+
+ if (0 >= buf_size)
+ return ERROR_BUF_TOO_SMALL;
+
+ printed = snprintf(buf, buf_size, " - Rev: %d", info->prod_rev);
+ buf += printed;
+ buf_size -= printed;
+
+ if (0 >= buf_size)
+ return ERROR_BUF_TOO_SMALL;
+
+ return ERROR_OK;
+}
+
+/* flash bank efm32 <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
+{
+ struct efm32x_flash_bank *efm32x_info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ efm32x_info = malloc(sizeof(struct efm32x_flash_bank));
+
+ bank->driver_priv = efm32x_info;
+ efm32x_info->probed = 0;
+ memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
+
+ return ERROR_OK;
+}
+
+/* set or reset given bits in a register */
+static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
+ uint32_t bitmask, int set)
+{
+ int ret = 0;
+ uint32_t reg_val = 0;
+
+ ret = target_read_u32(bank->target, reg, ®_val);
+ if (ERROR_OK != ret)
+ return ret;
+
+ if (set)
+ reg_val |= bitmask;
+ else
+ reg_val &= ~bitmask;
+
+ return target_write_u32(bank->target, reg, reg_val);
+}
+
+static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
+{
+ return efm32x_set_reg_bits(bank, EFM32_MSC_WRITECTRL,
+ EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
+}
+
+static int efm32x_msc_lock(struct flash_bank *bank, int lock)
+{
+ return target_write_u32(bank->target, EFM32_MSC_LOCK,
+ (lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
+}
+
+static int efm32x_wait_status(struct flash_bank *bank, int timeout,
+ uint32_t wait_mask, int wait_for_set)
+{
+ int ret = 0;
+ uint32_t status = 0;
+
+ while (1) {
+ ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
+ if (ERROR_OK != ret)
+ break;
+
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
+
+ if (((status & wait_mask) == 0) && (0 == wait_for_set))
+ break;
+ else if (((status & wait_mask) != 0) && wait_for_set)
+ break;
+
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for MSC status");
+ return ERROR_FAIL;
+ }
+
+ alive_sleep(1);
+ }
+
+ if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
+ LOG_WARNING("page erase was aborted");
+
+ return ret;
+}
+
+static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
+{
+ /* this function DOES NOT set WREN; must be set already */
+ /* 1. write address to ADDRB
+ 2. write LADDRIM
+ 3. check status (INVADDR, LOCKED)
+ 4. write ERASEPAGE
+ 5. wait until !STATUS_BUSY
+ */
+ int ret = 0;
+ uint32_t status = 0;
+
+ LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
+
+ ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
+ EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
+ if (ERROR_OK != ret)
+ return ret;
+
+ LOG_DEBUG("status 0x%" PRIx32, status);
+
+ if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
+ LOG_ERROR("Page is locked");
+ return ERROR_FAIL;
+ } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
+ LOG_ERROR("Invalid address 0x%" PRIx32, addr);
+ return ERROR_FAIL;
+ }
+
+ ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
+ EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
+ if (ERROR_OK != ret)
+ return ret;
+
+ return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
+ EFM32_MSC_STATUS_BUSY_MASK, 0);
+}
+
+static int efm32x_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ int i = 0;
+ int ret = 0;
+
+ if (TARGET_HALTED != target->state) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ efm32x_msc_lock(bank, 0);
+ ret = efm32x_set_wren(bank, 1);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to enable MSC write");
+ return ret;
+ }
+
+ for (i = first; i <= last; i++) {
+ ret = efm32x_erase_page(bank, bank->sectors[i].offset);
+ if (ERROR_OK != ret)
+ LOG_ERROR("Failed to erase page %d", i);
+ }
+
+ ret = efm32x_set_wren(bank, 0);
+ efm32x_msc_lock(bank, 1);
+
+ return ret;
+}
+
+static int efm32x_read_lock_data(struct flash_bank *bank)
+{
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct target *target = bank->target;
+ int i = 0;
+ int data_size = 0;
+ uint32_t *ptr = NULL;
+ int ret = 0;
+
+ assert(!(bank->num_sectors & 0x1f));
+
+ data_size = bank->num_sectors / 8; /* number of data bytes */
+ data_size /= 4; /* ...and data dwords */
+
+ ptr = efm32x_info->lb_page;
+
+ for (i = 0; i < data_size; i++, ptr++) {
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read PLW %d", i);
+ return ret;
+ }
+ }
+
+ /* also, read ULW, DLW and MLW */
+
+ /* ULW, word 126 */
+ ptr = efm32x_info->lb_page + 126;
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read ULW");
+ return ret;
+ }
+
+ /* DLW, word 127 */
+ ptr = efm32x_info->lb_page + 127;
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read DLW");
+ return ret;
+ }
+
+ /* MLW, word 125, present in GG and LG */
+ ptr = efm32x_info->lb_page + 125;
+ ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read MLW");
+ return ret;
+ }
+
+ return ERROR_OK;
+}
+
+static int efm32x_write_lock_data(struct flash_bank *bank)
+{
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ int ret = 0;
+
+ ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to erase LB page");
+ return ret;
+ }
+
+ return efm32x_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS,
+ LOCKBITS_PAGE_SZ);
+}
+
+static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
+{
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ uint32_t dw = efm32x_info->lb_page[page >> 5];
+ uint32_t mask = 0;
+
+ mask = 1 << (page & 0x1f);
+
+ return (dw & mask) ? 0 : 1;
+}
+
+static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
+{
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ uint32_t *dw = &efm32x_info->lb_page[page >> 5];
+ uint32_t mask = 0;
+
+ mask = 1 << (page & 0x1f);
+
+ if (!set)
+ *dw |= mask;
+ else
+ *dw &= ~mask;
+
+ return ERROR_OK;
+}
+
+static int efm32x_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct target *target = bank->target;
+ int i = 0;
+ int ret = 0;
+
+ if (!set) {
+ LOG_ERROR("Erase device data to reset page locks");
+ return ERROR_FAIL;
+ }
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ for (i = first; i <= last; i++) {
+ ret = efm32x_set_page_lock(bank, i, set);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to set lock on page %d", i);
+ return ret;
+ }
+ }
+
+ ret = efm32x_write_lock_data(bank);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to write LB page");
+ return ret;
+ }
+
+ return ERROR_OK;
+}
+
+static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[5];
+ struct armv7m_algorithm armv7m_info;
+ int ret = ERROR_OK;
+
+ /* see contrib/loaders/flash/efm32.S for src */
+ static const uint8_t efm32x_flash_write_code[] = {
+ /* #define EFM32_MSC_WRITECTRL_OFFSET 0x008 */
+ /* #define EFM32_MSC_WRITECMD_OFFSET 0x00c */
+ /* #define EFM32_MSC_ADDRB_OFFSET 0x010 */
+ /* #define EFM32_MSC_WDATA_OFFSET 0x018 */
+ /* #define EFM32_MSC_STATUS_OFFSET 0x01c */
+ /* #define EFM32_MSC_LOCK_OFFSET 0x03c */
+
+ 0x15, 0x4e, /* ldr r6, =#0x1b71 */
+ 0xc6, 0x63, /* str r6, [r0, #EFM32_MSC_LOCK_OFFSET] */
+ 0x01, 0x26, /* movs r6, #1 */
+ 0x86, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
+
+ /* wait_fifo: */
+ 0x16, 0x68, /* ldr r6, [r2, #0] */
+ 0x00, 0x2e, /* cmp r6, #0 */
+ 0x22, 0xd0, /* beq exit */
+ 0x55, 0x68, /* ldr r5, [r2, #4] */
+ 0xb5, 0x42, /* cmp r5, r6 */
+ 0xf9, 0xd0, /* beq wait_fifo */
+
+ 0x04, 0x61, /* str r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
+ 0x01, 0x26, /* movs r6, #1 */
+ 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
+ 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
+ 0x06, 0x27, /* movs r7, #6 */
+ 0x3e, 0x42, /* tst r6, r7 */
+ 0x16, 0xd1, /* bne error */
+
+ /* wait_wdataready: */
+ 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
+ 0x08, 0x27, /* movs r7, #8 */
+ 0x3e, 0x42, /* tst r6, r7 */
+ 0xfb, 0xd0, /* beq wait_wdataready */
+
+ 0x2e, 0x68, /* ldr r6, [r5] */
+ 0x86, 0x61, /* str r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
+ 0x08, 0x26, /* movs r6, #8 */
+ 0xc6, 0x60, /* str r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
+
+ 0x04, 0x35, /* adds r5, #4 */
+ 0x04, 0x34, /* adds r4, #4 */
+
+ /* busy: */
+ 0xc6, 0x69, /* ldr r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
+ 0x01, 0x27, /* movs r7, #1 */
+ 0x3e, 0x42, /* tst r6, r7 */
+ 0xfb, 0xd1, /* bne busy */
+
+ 0x9d, 0x42, /* cmp r5, r3 */
+ 0x01, 0xd3, /* bcc no_wrap */
+ 0x15, 0x46, /* mov r5, r2 */
+ 0x08, 0x35, /* adds r5, #8 */
+
+ /* no_wrap: */
+ 0x55, 0x60, /* str r5, [r2, #4] */
+ 0x01, 0x39, /* subs r1, r1, #1 */
+ 0x00, 0x29, /* cmp r1, #0 */
+ 0x02, 0xd0, /* beq exit */
+ 0xdb, 0xe7, /* b wait_fifo */
+
+ /* error: */
+ 0x00, 0x20, /* movs r0, #0 */
+ 0x50, 0x60, /* str r0, [r2, #4] */
+
+ /* exit: */
+ 0x30, 0x46, /* mov r0, r6 */
+ 0x00, 0xbe, /* bkpt #0 */
+
+ /* LOCKKEY */
+ 0x71, 0x1b, 0x00, 0x00
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ ret = target_write_buffer(target, write_algorithm->address,
+ sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
+ if (ret != ERROR_OK)
+ return ret;
+
+ /* memory buffer */
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ buffer_size /= 2;
+ buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* flash base (in), status (out) */
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* count (word-32bit) */
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* buffer start */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* buffer end */
+ init_reg_param(®_params[4], "r4", 32, PARAM_IN_OUT); /* target address */
+
+ buf_set_u32(reg_params[0].value, 0, 32, EFM32_MSC_REGBASE);
+ buf_set_u32(reg_params[1].value, 0, 32, count);
+ buf_set_u32(reg_params[2].value, 0, 32, source->address);
+ buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
+ buf_set_u32(reg_params[4].value, 0, 32, address);
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ ret = target_run_flash_async_algorithm(target, buf, count, 4,
+ 0, NULL,
+ 5, reg_params,
+ source->address, source->size,
+ write_algorithm->address, 0,
+ &armv7m_info);
+
+ if (ret == ERROR_FLASH_OPERATION_FAILED) {
+ LOG_ERROR("flash write failed at address 0x%"PRIx32,
+ buf_get_u32(reg_params[4].value, 0, 32));
+
+ if (buf_get_u32(reg_params[0].value, 0, 32) &
+ EFM32_MSC_STATUS_LOCKED_MASK) {
+ LOG_ERROR("flash memory write protected");
+ }
+
+ if (buf_get_u32(reg_params[0].value, 0, 32) &
+ EFM32_MSC_STATUS_INVADDR_MASK) {
+ LOG_ERROR("invalid flash memory write address");
+ }
+ }
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+
+ return ret;
+}
+
+static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
+ uint32_t val)
+{
+ /* this function DOES NOT set WREN; must be set already */
+ /* 1. write address to ADDRB
+ 2. write LADDRIM
+ 3. check status (INVADDR, LOCKED)
+ 4. wait for WDATAREADY
+ 5. write data to WDATA
+ 6. write WRITECMD_WRITEONCE to WRITECMD
+ 7. wait until !STATUS_BUSY
+ */
+
+ /* FIXME: EFM32G ref states (7.3.2) that writes should be
+ * performed twice per dword */
+
+ int ret = 0;
+ uint32_t status = 0;
+
+ /* if not called, GDB errors will be reported during large writes */
+ keep_alive();
+
+ ret = target_write_u32(bank->target, EFM32_MSC_ADDRB, addr);
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_set_reg_bits(bank, EFM32_MSC_WRITECMD,
+ EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = target_read_u32(bank->target, EFM32_MSC_STATUS, &status);
+ if (ERROR_OK != ret)
+ return ret;
+
+ LOG_DEBUG("status 0x%" PRIx32, status);
+
+ if (status & EFM32_MSC_STATUS_LOCKED_MASK) {
+ LOG_ERROR("Page is locked");
+ return ERROR_FAIL;
+ } else if (status & EFM32_MSC_STATUS_INVADDR_MASK) {
+ LOG_ERROR("Invalid address 0x%" PRIx32, addr);
+ return ERROR_FAIL;
+ }
+
+ ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
+ EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Wait for WDATAREADY failed");
+ return ret;
+ }
+
+ ret = target_write_u32(bank->target, EFM32_MSC_WDATA, val);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("WDATA write failed");
+ return ret;
+ }
+
+ ret = target_write_u32(bank->target, EFM32_MSC_WRITECMD,
+ EFM32_MSC_WRITECMD_WRITEONCE_MASK);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("WRITECMD write failed");
+ return ret;
+ }
+
+ ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
+ EFM32_MSC_STATUS_BUSY_MASK, 0);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Wait for BUSY failed");
+ return ret;
+ }
+
+ return ERROR_OK;
+}
+
+static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint8_t *new_buffer = NULL;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x3) {
+ LOG_ERROR("offset 0x%" PRIx32 " breaks required 4-byte "
+ "alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ if (count & 0x3) {
+ uint32_t old_count = count;
+ count = (old_count | 3) + 1;
+ new_buffer = malloc(count);
+ if (new_buffer == NULL) {
+ LOG_ERROR("odd number of bytes to write and no memory "
+ "for padding buffer");
+ return ERROR_FAIL;
+ }
+ LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
+ "and padding with 0xff", old_count, count);
+ memset(new_buffer, 0xff, count);
+ buffer = memcpy(new_buffer, buffer, old_count);
+ }
+
+ uint32_t words_remaining = count / 4;
+ int retval, retval2;
+
+ /* unlock flash registers */
+ efm32x_msc_lock(bank, 0);
+ retval = efm32x_set_wren(bank, 1);
+ if (retval != ERROR_OK)
+ goto cleanup;
+
+ /* try using a block write */
+ retval = efm32x_write_block(bank, buffer, offset, words_remaining);
+
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single word accesses */
+ LOG_WARNING("couldn't use block writes, falling back to single "
+ "memory accesses");
+
+ while (words_remaining > 0) {
+ uint32_t value;
+ memcpy(&value, buffer, sizeof(uint32_t));
+
+ retval = efm32x_write_word(bank, offset, value);
+ if (retval != ERROR_OK)
+ goto reset_pg_and_lock;
+
+ words_remaining--;
+ buffer += 4;
+ offset += 4;
+ }
+ }
+
+reset_pg_and_lock:
+ retval2 = efm32x_set_wren(bank, 0);
+ efm32x_msc_lock(bank, 1);
+ if (retval == ERROR_OK)
+ retval = retval2;
+
+cleanup:
+ if (new_buffer)
+ free(new_buffer);
+
+ return retval;
+}
+
+static int efm32x_probe(struct flash_bank *bank)
+{
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ struct efm32_info efm32_mcu_info;
+ int ret;
+ int i;
+ uint32_t base_address = 0x00000000;
+ char buf[256];
+
+ efm32x_info->probed = 0;
+ memset(efm32x_info->lb_page, 0xff, LOCKBITS_PAGE_SZ);
+
+ ret = efm32x_read_info(bank, &efm32_mcu_info);
+ if (ERROR_OK != ret)
+ return ret;
+
+ ret = efm32x_decode_info(&efm32_mcu_info, buf, sizeof(buf));
+ if (ERROR_OK != ret)
+ return ret;
+
+ LOG_INFO("detected part: %s", buf);
+ LOG_INFO("flash size = %dkbytes", efm32_mcu_info.flash_sz_kib);
+ LOG_INFO("flash page size = %dbytes", efm32_mcu_info.page_size);
+
+ assert(0 != efm32_mcu_info.page_size);
+
+ int num_pages = efm32_mcu_info.flash_sz_kib * 1024 /
+ efm32_mcu_info.page_size;
+
+ assert(num_pages > 0);
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->base = base_address;
+ bank->size = (num_pages * efm32_mcu_info.page_size);
+ bank->num_sectors = num_pages;
+
+ ret = efm32x_read_lock_data(bank);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read LB data");
+ return ret;
+ }
+
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+
+ for (i = 0; i < num_pages; i++) {
+ bank->sectors[i].offset = i * efm32_mcu_info.page_size;
+ bank->sectors[i].size = efm32_mcu_info.page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ efm32x_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int efm32x_auto_probe(struct flash_bank *bank)
+{
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+ if (efm32x_info->probed)
+ return ERROR_OK;
+ return efm32x_probe(bank);
+}
+
+static int efm32x_protect_check(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ int ret = 0;
+ int i = 0;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ ret = efm32x_read_lock_data(bank);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read LB data");
+ return ret;
+ }
+
+ assert(NULL != bank->sectors);
+
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
+
+ return ERROR_OK;
+}
+
+static int get_efm32x_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct efm32_info info;
+ int ret = 0;
+
+ ret = efm32x_read_info(bank, &info);
+ if (ERROR_OK != ret) {
+ LOG_ERROR("Failed to read EFM32 info");
+ return ret;
+ }
+
+ return efm32x_decode_info(&info, buf, buf_size);
+}
+
+COMMAND_HANDLER(efm32x_handle_debuglock_command)
+{
+ struct target *target = NULL;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ struct efm32x_flash_bank *efm32x_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ uint32_t *ptr;
+ ptr = efm32x_info->lb_page + 127;
+ *ptr = 0;
+
+ retval = efm32x_write_lock_data(bank);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Failed to write LB page");
+ return retval;
+ }
+
+ command_print(CMD_CTX, "efm32x debug interface locked, reset the device to apply");
+
+ return ERROR_OK;
+}
+
+static const struct command_registration efm32x_exec_command_handlers[] = {
+ {
+ .name = "debuglock",
+ .handler = efm32x_handle_debuglock_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Lock the debug interface of the device.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration efm32x_command_handlers[] = {
+ {
+ .name = "efm32",
+ .mode = COMMAND_ANY,
+ .help = "efm32 flash command group",
+ .usage = "",
+ .chain = efm32x_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver efm32_flash = {
+ .name = "efm32",
+ .commands = efm32x_command_handlers,
+ .flash_bank_command = efm32x_flash_bank_command,
+ .erase = efm32x_erase,
+ .protect = efm32x_protect,
+ .write = efm32x_write,
+ .read = default_flash_read,
+ .probe = efm32x_probe,
+ .auto_probe = efm32x_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = efm32x_protect_check,
+ .info = get_efm32x_info,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/em357.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/em357.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/em357.c
new file mode 100755
index 0000000..6cc922c
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/em357.c
@@ -0,0 +1,941 @@
+/***************************************************************************
+ * Copyright (C) 2005 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ *
+ * Copyright (C) 2011 by Erik Bot�
+ * erik.boto@pelagicore.com
+ *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/binarybuffer.h>
+#include <target/algorithm.h>
+#include <target/armv7m.h>
+
+/* em357 register locations */
+
+#define EM357_FLASH_ACR 0x40008000
+#define EM357_FLASH_KEYR 0x40008004
+#define EM357_FLASH_OPTKEYR 0x40008008
+#define EM357_FLASH_SR 0x4000800C
+#define EM357_FLASH_CR 0x40008010
+#define EM357_FLASH_AR 0x40008014
+#define EM357_FLASH_OBR 0x4000801C
+#define EM357_FLASH_WRPR 0x40008020
+
+#define EM357_FPEC_CLK 0x4000402c
+/* option byte location */
+
+#define EM357_OB_RDP 0x08040800
+#define EM357_OB_WRP0 0x08040808
+#define EM357_OB_WRP1 0x0804080A
+#define EM357_OB_WRP2 0x0804080C
+
+/* FLASH_CR register bits */
+
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER (1 << 2)
+#define FLASH_OPTPG (1 << 4)
+#define FLASH_OPTER (1 << 5)
+#define FLASH_STRT (1 << 6)
+#define FLASH_LOCK (1 << 7)
+#define FLASH_OPTWRE (1 << 9)
+
+/* FLASH_SR register bits */
+
+#define FLASH_BSY (1 << 0)
+#define FLASH_PGERR (1 << 2)
+#define FLASH_WRPRTERR (1 << 4)
+#define FLASH_EOP (1 << 5)
+
+/* EM357_FLASH_OBR bit definitions (reading) */
+
+#define OPT_ERROR 0
+#define OPT_READOUT 1
+
+/* register unlock keys */
+
+#define KEY1 0x45670123
+#define KEY2 0xCDEF89AB
+
+struct em357_options {
+ uint16_t RDP;
+ uint16_t user_options;
+ uint16_t protection[3];
+};
+
+struct em357_flash_bank {
+ struct em357_options option_bytes;
+ int ppage_size;
+ int probed;
+};
+
+static int em357_mass_erase(struct flash_bank *bank);
+
+/* flash bank em357 <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(em357_flash_bank_command)
+{
+ struct em357_flash_bank *em357_info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ em357_info = malloc(sizeof(struct em357_flash_bank));
+ bank->driver_priv = em357_info;
+
+ em357_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static inline int em357_get_flash_status(struct flash_bank *bank, uint32_t *status)
+{
+ struct target *target = bank->target;
+ return target_read_u32(target, EM357_FLASH_SR, status);
+}
+
+static int em357_wait_status_busy(struct flash_bank *bank, int timeout)
+{
+ struct target *target = bank->target;
+ uint32_t status;
+ int retval = ERROR_OK;
+
+ /* wait for busy to clear */
+ for (;; ) {
+ retval = em357_get_flash_status(bank, &status);
+ if (retval != ERROR_OK)
+ return retval;
+ LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ if ((status & FLASH_BSY) == 0)
+ break;
+ if (timeout-- <= 0) {
+ LOG_ERROR("timed out waiting for flash");
+ return ERROR_FAIL;
+ }
+ alive_sleep(1);
+ }
+
+ if (status & FLASH_WRPRTERR) {
+ LOG_ERROR("em357 device protected");
+ retval = ERROR_FAIL;
+ }
+
+ if (status & FLASH_PGERR) {
+ LOG_ERROR("em357 device programming failed");
+ retval = ERROR_FAIL;
+ }
+
+ /* Clear but report errors */
+ if (status & (FLASH_WRPRTERR | FLASH_PGERR)) {
+ /* If this operation fails, we ignore it and report the original
+ * retval
+ */
+ target_write_u32(target, EM357_FLASH_SR, FLASH_WRPRTERR | FLASH_PGERR);
+ }
+ return retval;
+}
+
+static int em357_read_options(struct flash_bank *bank)
+{
+ uint32_t optiondata;
+ struct em357_flash_bank *em357_info = NULL;
+ struct target *target = bank->target;
+
+ em357_info = bank->driver_priv;
+
+ /* read current option bytes */
+ int retval = target_read_u32(target, EM357_FLASH_OBR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+
+ em357_info->option_bytes.user_options = (uint16_t)0xFFFC | ((optiondata >> 2) & 0x03);
+ em357_info->option_bytes.RDP = (optiondata & (1 << OPT_READOUT)) ? 0xFFFF : 0x5AA5;
+
+ if (optiondata & (1 << OPT_READOUT))
+ LOG_INFO("Device Security Bit Set");
+
+ /* each bit refers to a 4bank protection */
+ retval = target_read_u32(target, EM357_FLASH_WRPR, &optiondata);
+ if (retval != ERROR_OK)
+ return retval;
+
+ em357_info->option_bytes.protection[0] = (uint16_t)optiondata;
+ em357_info->option_bytes.protection[1] = (uint16_t)(optiondata >> 8);
+ em357_info->option_bytes.protection[2] = (uint16_t)(optiondata >> 16);
+
+ return ERROR_OK;
+}
+
+static int em357_erase_options(struct flash_bank *bank)
+{
+ struct em357_flash_bank *em357_info = NULL;
+ struct target *target = bank->target;
+
+ em357_info = bank->driver_priv;
+
+ /* read current options */
+ em357_read_options(bank);
+
+ /* unlock flash registers */
+ int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* unlock option flash registers */
+ retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* erase option bytes */
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTER | FLASH_OPTWRE);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTER | FLASH_STRT | FLASH_OPTWRE);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 10);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* clear readout protection and complementary option bytes
+ * this will also force a device unlock if set */
+ em357_info->option_bytes.RDP = 0x5AA5;
+
+ return ERROR_OK;
+}
+
+static int em357_write_options(struct flash_bank *bank)
+{
+ struct em357_flash_bank *em357_info = NULL;
+ struct target *target = bank->target;
+
+ em357_info = bank->driver_priv;
+
+ /* unlock flash registers */
+ int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* unlock option flash registers */
+ retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_OPTKEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* program option bytes */
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_OPTPG | FLASH_OPTWRE);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 10);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write protection byte 1 */
+ retval = target_write_u16(target, EM357_OB_WRP0, em357_info->option_bytes.protection[0]);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 10);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write protection byte 2 */
+ retval = target_write_u16(target, EM357_OB_WRP1, em357_info->option_bytes.protection[1]);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 10);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write protection byte 3 */
+ retval = target_write_u16(target, EM357_OB_WRP2, em357_info->option_bytes.protection[2]);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 10);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write readout protection bit */
+ retval = target_write_u16(target, EM357_OB_RDP, em357_info->option_bytes.RDP);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 10);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int em357_protect_check(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct em357_flash_bank *em357_info = bank->driver_priv;
+
+ uint32_t protection;
+ int i, s;
+ int num_bits;
+ int set;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* each bit refers to a 4bank protection (bit 0-23) */
+ int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* each protection bit is for 4 * 2K pages */
+ num_bits = (bank->num_sectors / em357_info->ppage_size);
+
+ for (i = 0; i < num_bits; i++) {
+ set = 1;
+ if (protection & (1 << i))
+ set = 0;
+
+ for (s = 0; s < em357_info->ppage_size; s++)
+ bank->sectors[(i * em357_info->ppage_size) + s].is_protected = set;
+ }
+
+ return ERROR_OK;
+}
+
+static int em357_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ int i;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first == 0) && (last == (bank->num_sectors - 1)))
+ return em357_mass_erase(bank);
+
+ /* Enable FPEC clock */
+ target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
+
+ /* unlock flash registers */
+ int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ for (i = first; i <= last; i++) {
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PER);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_AR,
+ bank->base + bank->sectors[i].offset);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PER | FLASH_STRT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 100);
+ if (retval != ERROR_OK)
+ return retval;
+
+ bank->sectors[i].is_erased = 1;
+ }
+
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+static int em357_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct em357_flash_bank *em357_info = NULL;
+ struct target *target = bank->target;
+ uint16_t prot_reg[4] = {0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
+ int i, reg, bit;
+ int status;
+ uint32_t protection;
+
+ em357_info = bank->driver_priv;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((first % em357_info->ppage_size) != 0) {
+ LOG_WARNING("aligned start protect sector to a %d sector boundary",
+ em357_info->ppage_size);
+ first = first - (first % em357_info->ppage_size);
+ }
+ if (((last + 1) % em357_info->ppage_size) != 0) {
+ LOG_WARNING("aligned end protect sector to a %d sector boundary",
+ em357_info->ppage_size);
+ last++;
+ last = last - (last % em357_info->ppage_size);
+ last--;
+ }
+
+ /* each bit refers to a 4bank protection */
+ int retval = target_read_u32(target, EM357_FLASH_WRPR, &protection);
+ if (retval != ERROR_OK)
+ return retval;
+
+ prot_reg[0] = (uint16_t)protection;
+ prot_reg[1] = (uint16_t)(protection >> 8);
+ prot_reg[2] = (uint16_t)(protection >> 16);
+
+ for (i = first; i <= last; i++) {
+ reg = (i / em357_info->ppage_size) / 8;
+ bit = (i / em357_info->ppage_size) - (reg * 8);
+
+ LOG_WARNING("reg, bit: %d, %d", reg, bit);
+ if (set)
+ prot_reg[reg] &= ~(1 << bit);
+ else
+ prot_reg[reg] |= (1 << bit);
+ }
+
+ status = em357_erase_options(bank);
+ if (retval != ERROR_OK)
+ return status;
+
+ em357_info->option_bytes.protection[0] = prot_reg[0];
+ em357_info->option_bytes.protection[1] = prot_reg[1];
+ em357_info->option_bytes.protection[2] = prot_reg[2];
+
+ return em357_write_options(bank);
+}
+
+static int em357_write_block(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t buffer_size = 16384;
+ struct working_area *write_algorithm;
+ struct working_area *source;
+ uint32_t address = bank->base + offset;
+ struct reg_param reg_params[4];
+ struct armv7m_algorithm armv7m_info;
+ int retval = ERROR_OK;
+
+ /* see contib/loaders/flash/stm32x.s for src, the same is used here except for
+ * a modified *_FLASH_BASE */
+
+ static const uint8_t em357_flash_write_code[] = {
+ /* #define EM357_FLASH_CR_OFFSET 0x10
+ * #define EM357_FLASH_SR_OFFSET 0x0C
+ * write: */
+ 0x08, 0x4c, /* ldr r4, EM357_FLASH_BASE */
+ 0x1c, 0x44, /* add r4, r3 */
+ /* write_half_word: */
+ 0x01, 0x23, /* movs r3, #0x01 */
+ 0x23, 0x61, /* str r3, [r4,
+ *#EM357_FLASH_CR_OFFSET] */
+ 0x30, 0xf8, 0x02, 0x3b, /* ldrh r3, [r0], #0x02 */
+ 0x21, 0xf8, 0x02, 0x3b, /* strh r3, [r1], #0x02 */
+ /* busy: */
+ 0xe3, 0x68, /* ldr r3, [r4,
+ *#EM357_FLASH_SR_OFFSET] */
+ 0x13, 0xf0, 0x01, 0x0f, /* tst r3, #0x01 */
+ 0xfb, 0xd0, /* beq busy */
+ 0x13, 0xf0, 0x14, 0x0f, /* tst r3, #0x14 */
+ 0x01, 0xd1, /* bne exit */
+ 0x01, 0x3a, /* subs r2, r2, #0x01 */
+ 0xf0, 0xd1, /* bne write_half_word */
+ /* exit: */
+ 0x00, 0xbe, /* bkpt #0x00 */
+ 0x00, 0x80, 0x00, 0x40, /* EM357_FLASH_BASE: .word 0x40008000 */
+ };
+
+ /* flash write code */
+ if (target_alloc_working_area(target, sizeof(em357_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(em357_flash_write_code), em357_flash_write_code);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* memory buffer */
+ while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ buffer_size /= 2;
+ if (buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, write_algorithm);
+
+ LOG_WARNING(
+ "no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+ }
+
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r3", 32, PARAM_IN_OUT);
+
+ while (count > 0) {
+ uint32_t thisrun_count = (count > (buffer_size / 2)) ?
+ (buffer_size / 2) : count;
+
+ retval = target_write_buffer(target, source->address, thisrun_count * 2, buffer);
+ if (retval != ERROR_OK)
+ break;
+
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ buf_set_u32(reg_params[1].value, 0, 32, address);
+ buf_set_u32(reg_params[2].value, 0, 32, thisrun_count);
+ buf_set_u32(reg_params[3].value, 0, 32, 0);
+
+ retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
+ write_algorithm->address, 0, 10000, &armv7m_info);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("error executing em357 flash write algorithm");
+ break;
+ }
+
+ if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_PGERR) {
+ LOG_ERROR("flash memory not erased before writing");
+ /* Clear but report errors */
+ target_write_u32(target, EM357_FLASH_SR, FLASH_PGERR);
+ retval = ERROR_FAIL;
+ break;
+ }
+
+ if (buf_get_u32(reg_params[3].value, 0, 32) & FLASH_WRPRTERR) {
+ LOG_ERROR("flash memory write protected");
+ /* Clear but report errors */
+ target_write_u32(target, EM357_FLASH_SR, FLASH_WRPRTERR);
+ retval = ERROR_FAIL;
+ break;
+ }
+
+ buffer += thisrun_count * 2;
+ address += thisrun_count * 2;
+ count -= thisrun_count;
+ }
+
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+
+ return retval;
+}
+
+static int em357_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ uint32_t words_remaining = (count / 2);
+ uint32_t bytes_remaining = (count & 0x00000001);
+ uint32_t address = bank->base + offset;
+ uint32_t bytes_written = 0;
+ int retval;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (offset & 0x1) {
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required 2-byte alignment", offset);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ /* unlock flash registers */
+ retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
+
+ /* multiple half words (2-byte) to be programmed? */
+ if (words_remaining > 0) {
+ /* try using a block write */
+ retval = em357_write_block(bank, buffer, offset, words_remaining);
+ if (retval != ERROR_OK) {
+ if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
+ /* if block write failed (no sufficient working area),
+ * we use normal (slow) single dword accesses */
+ LOG_WARNING(
+ "couldn't use block writes, falling back to single memory accesses");
+ }
+ } else {
+ buffer += words_remaining * 2;
+ address += words_remaining * 2;
+ words_remaining = 0;
+ }
+ }
+
+ if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
+ return retval;
+
+ while (words_remaining > 0) {
+ uint16_t value;
+ memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
+
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PG);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u16(target, address, value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 5);
+ if (retval != ERROR_OK)
+ return retval;
+
+ bytes_written += 2;
+ words_remaining--;
+ address += 2;
+ }
+
+ if (bytes_remaining) {
+ uint16_t value = 0xffff;
+ memcpy(&value, buffer + bytes_written, bytes_remaining);
+
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_PG);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u16(target, address, value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 5);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
+}
+
+static int em357_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct em357_flash_bank *em357_info = bank->driver_priv;
+ int i;
+ uint16_t num_pages;
+ int page_size;
+ uint32_t base_address = 0x08000000;
+
+ em357_info->probed = 0;
+
+ switch (bank->size) {
+ case 0x10000:
+ /* 64k -- 64 1k pages */
+ num_pages = 64;
+ page_size = 1024;
+ break;
+ case 0x20000:
+ /* 128k -- 128 1k pages */
+ num_pages = 128;
+ page_size = 1024;
+ break;
+ case 0x30000:
+ /* 192k -- 96 2k pages */
+ num_pages = 96;
+ page_size = 2048;
+ break;
+ case 0x40000:
+ /* 256k -- 128 2k pages */
+ num_pages = 128;
+ page_size = 2048;
+ break;
+ default:
+ LOG_WARNING("No size specified for em357 flash driver, assuming 192k!");
+ num_pages = 96;
+ page_size = 2048;
+ break;
+ }
+
+ /* Enable FPEC CLK */
+ int retval = target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
+ if (retval != ERROR_OK)
+ return retval;
+
+ em357_info->ppage_size = 4;
+
+ LOG_INFO("flash size = %dkbytes", num_pages*page_size/1024);
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->base = base_address;
+ bank->size = (num_pages * page_size);
+ bank->num_sectors = num_pages;
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+
+ for (i = 0; i < num_pages; i++) {
+ bank->sectors[i].offset = i * page_size;
+ bank->sectors[i].size = page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ em357_info->probed = 1;
+
+ return ERROR_OK;
+}
+
+static int em357_auto_probe(struct flash_bank *bank)
+{
+ struct em357_flash_bank *em357_info = bank->driver_priv;
+ if (em357_info->probed)
+ return ERROR_OK;
+ return em357_probe(bank);
+}
+
+COMMAND_HANDLER(em357_handle_lock_command)
+{
+ struct target *target = NULL;
+ struct em357_flash_bank *em357_info = NULL;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ em357_info = bank->driver_priv;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (em357_erase_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "em357 failed to erase options");
+ return ERROR_OK;
+ }
+
+ /* set readout protection */
+ em357_info->option_bytes.RDP = 0;
+
+ if (em357_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "em357 failed to lock device");
+ return ERROR_OK;
+ }
+
+ command_print(CMD_CTX, "em357 locked");
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(em357_handle_unlock_command)
+{
+ struct target *target = NULL;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (em357_erase_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "em357 failed to unlock device");
+ return ERROR_OK;
+ }
+
+ if (em357_write_options(bank) != ERROR_OK) {
+ command_print(CMD_CTX, "em357 failed to lock device");
+ return ERROR_OK;
+ }
+
+ command_print(CMD_CTX, "em357 unlocked.\n"
+ "INFO: a reset or power cycle is required "
+ "for the new settings to take effect.");
+
+ return ERROR_OK;
+}
+
+static int em357_mass_erase(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* Make sure the flash clock is on */
+ target_write_u32(target, EM357_FPEC_CLK, 0x00000001);
+
+ /* unlock option flash registers */
+ int retval = target_write_u32(target, EM357_FLASH_KEYR, KEY1);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_KEYR, KEY2);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* mass erase flash memory */
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_MER | FLASH_STRT);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = em357_wait_status_busy(bank, 100);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_u32(target, EM357_FLASH_CR, FLASH_LOCK);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(em357_handle_mass_erase_command)
+{
+ int i;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ retval = em357_mass_erase(bank);
+ if (retval == ERROR_OK) {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_erased = 1;
+
+ command_print(CMD_CTX, "em357 mass erase complete");
+ } else
+ command_print(CMD_CTX, "em357 mass erase failed");
+
+ return retval;
+}
+
+static const struct command_registration em357_exec_command_handlers[] = {
+ {
+ .name = "lock",
+ .usage = "<bank>",
+ .handler = em357_handle_lock_command,
+ .mode = COMMAND_EXEC,
+ .help = "Lock entire flash device.",
+ },
+ {
+ .name = "unlock",
+ .usage = "<bank>",
+ .handler = em357_handle_unlock_command,
+ .mode = COMMAND_EXEC,
+ .help = "Unlock entire protected flash device.",
+ },
+ {
+ .name = "mass_erase",
+ .usage = "<bank>",
+ .handler = em357_handle_mass_erase_command,
+ .mode = COMMAND_EXEC,
+ .help = "Erase entire flash device.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration em357_command_handlers[] = {
+ {
+ .name = "em357",
+ .mode = COMMAND_ANY,
+ .help = "em357 flash command group",
+ .usage = "",
+ .chain = em357_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver em357_flash = {
+ .name = "em357",
+ .commands = em357_command_handlers,
+ .flash_bank_command = em357_flash_bank_command,
+ .erase = em357_erase,
+ .protect = em357_protect,
+ .write = em357_write,
+ .read = default_flash_read,
+ .probe = em357_probe,
+ .auto_probe = em357_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = em357_protect_check,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/faux.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/faux.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/faux.c
new file mode 100755
index 0000000..8198ef5
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/faux.c
@@ -0,0 +1,142 @@
+/***************************************************************************
+ * Copyright (C) 2009 �yvind Harboe *
+ * oyvind.harboe@zylin.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <target/image.h>
+#include "hello.h"
+
+struct faux_flash_bank {
+ struct target *target;
+ uint8_t *memory;
+ uint32_t start_address;
+};
+
+static const int sectorSize = 0x10000;
+
+
+/* flash bank faux <base> <size> <chip_width> <bus_width> <target#> <driverPath>
+ */
+FLASH_BANK_COMMAND_HANDLER(faux_flash_bank_command)
+{
+ struct faux_flash_bank *info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ info = malloc(sizeof(struct faux_flash_bank));
+ if (info == NULL) {
+ LOG_ERROR("no memory for flash bank info");
+ return ERROR_FAIL;
+ }
+ info->memory = malloc(bank->size);
+ if (info->memory == NULL) {
+ free(info);
+ LOG_ERROR("no memory for flash bank info");
+ return ERROR_FAIL;
+ }
+ bank->driver_priv = info;
+
+ /* Use 0x10000 as a fixed sector size. */
+ int i = 0;
+ uint32_t offset = 0;
+ bank->num_sectors = bank->size/sectorSize;
+ bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+ for (i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].offset = offset;
+ bank->sectors[i].size = sectorSize;
+ offset += bank->sectors[i].size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 0;
+ }
+
+ info->target = get_target(CMD_ARGV[5]);
+ if (info->target == NULL) {
+ LOG_ERROR("target '%s' not defined", CMD_ARGV[5]);
+ free(info->memory);
+ free(info);
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static int faux_erase(struct flash_bank *bank, int first, int last)
+{
+ struct faux_flash_bank *info = bank->driver_priv;
+ memset(info->memory + first*sectorSize, 0xff, sectorSize*(last-first + 1));
+ return ERROR_OK;
+}
+
+static int faux_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ LOG_USER("set protection sector %d to %d to %s", first, last, set ? "on" : "off");
+ return ERROR_OK;
+}
+
+static int faux_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct faux_flash_bank *info = bank->driver_priv;
+ memcpy(info->memory + offset, buffer, count);
+ return ERROR_OK;
+}
+
+static int faux_protect_check(struct flash_bank *bank)
+{
+ return ERROR_OK;
+}
+
+static int faux_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ snprintf(buf, buf_size, "faux flash driver");
+ return ERROR_OK;
+}
+
+static int faux_probe(struct flash_bank *bank)
+{
+ return ERROR_OK;
+}
+
+static const struct command_registration faux_command_handlers[] = {
+ {
+ .name = "faux",
+ .mode = COMMAND_ANY,
+ .help = "faux flash command group",
+ .chain = hello_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver faux_flash = {
+ .name = "faux",
+ .commands = faux_command_handlers,
+ .flash_bank_command = faux_flash_bank_command,
+ .erase = faux_erase,
+ .protect = faux_protect,
+ .write = faux_write,
+ .read = default_flash_read,
+ .probe = faux_probe,
+ .auto_probe = faux_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = faux_protect_check,
+ .info = faux_info
+};