You are viewing a plain text version of this content. The canonical link for it is here.
Posted to commits@nuttx.apache.org by xi...@apache.org on 2022/08/11 02:00:45 UTC
[incubator-nuttx] 01/02: arch/arm/samv7: get TX DMA running for HSMCI interface
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 49d26e1b5008dc6c1ead4bbfaa94032dfa692cef
Author: Petro Karashchenko <pe...@gmail.com>
AuthorDate: Thu Aug 11 00:39:37 2022 +0200
arch/arm/samv7: get TX DMA running for HSMCI interface
Signed-off-by: Petro Karashchenko <pe...@gmail.com>
---
arch/arm/src/samv7/sam_hsmci.c | 28 ++++++++++------------------
arch/arm/src/samv7/sam_xdmac.c | 2 +-
arch/arm/src/samv7/sam_xdmac.h | 2 +-
boards/arm/samv7/samv71-xult/README.txt | 26 +++++++++-----------------
4 files changed, 21 insertions(+), 37 deletions(-)
diff --git a/arch/arm/src/samv7/sam_hsmci.c b/arch/arm/src/samv7/sam_hsmci.c
index 9a8a6c0e8d..33761fba59 100644
--- a/arch/arm/src/samv7/sam_hsmci.c
+++ b/arch/arm/src/samv7/sam_hsmci.c
@@ -118,7 +118,7 @@
*/
#undef HSCMI_NORXDMA /* Define to disable RX DMA */
-#define HSCMI_NOTXDMA 1 /* Define to disable TX DMA */
+#undef HSCMI_NOTXDMA /* Define to disable TX DMA */
/* Timing */
@@ -204,7 +204,7 @@
(HSMCI_INT_OVRE | HSMCI_INT_BLKOVRE | HSMCI_INT_CSTOE | HSMCI_INT_DTOE | \
HSMCI_INT_DCRCE)
-#define HSMCI_DATA_DMASEND_ERRORS \
+#define HSMCI_DATA_SEND_ERRORS \
(HSMCI_INT_UNRE | HSMCI_INT_CSTOE | HSMCI_INT_DTOE | HSMCI_INT_DCRCE)
/* Data transfer status and interrupt mask bits.
@@ -228,7 +228,7 @@
#define HSMCI_DMARECV_INTS \
(HSMCI_DATA_RECV_ERRORS | HSMCI_INT_XFRDONE /* | HSMCI_INT_DMADONE */)
#define HSMCI_DMASEND_INTS \
- (HSMCI_DATA_DMASEND_ERRORS | HSMCI_INT_XFRDONE /* | HSMCI_INT_DMADONE */)
+ (HSMCI_DATA_SEND_ERRORS | HSMCI_INT_XFRDONE /* | HSMCI_INT_DMADONE */)
/* Event waiting interrupt mask bits.
*
@@ -1741,6 +1741,7 @@ static sdio_capset_t sam_capabilities(struct sdio_dev_s *dev)
#ifdef CONFIG_SAMV7_HSMCI_DMA
caps |= SDIO_CAPS_DMASUPPORTED;
#endif
+ caps |= SDIO_CAPS_DMABEFOREWRITE;
return caps;
}
@@ -2242,7 +2243,7 @@ static int sam_sendsetup(struct sdio_dev_s *dev,
/* Check the HSMCI status */
sr = sam_getreg(priv, SAM_HSMCI_SR_OFFSET);
- if ((sr & HSMCI_DATA_DMASEND_ERRORS) != 0)
+ if ((sr & HSMCI_DATA_SEND_ERRORS) != 0)
{
/* Some fatal error has occurred */
@@ -2553,7 +2554,7 @@ static int sam_recvshort(struct sdio_dev_s *dev,
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE &&
(cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE)
{
- mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else
@@ -2604,7 +2605,7 @@ static int sam_recvlong(struct sdio_dev_s *dev, uint32_t cmd,
if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE)
{
- mcerr("ERROR: Wrong response CMD=%08x\n", cmd);
+ mcerr("ERROR: Wrong response CMD=%08" PRIx32 "\n", cmd);
ret = -EINVAL;
}
else
@@ -2737,16 +2738,7 @@ static void sam_waitenable(struct sdio_dev_s *dev,
return;
}
- /* Start the watchdog timer. I am not sure why this is, but I am
- * currently seeing some additional delays when DMA is used.
- */
-
- if (priv->txbusy)
- {
- /* TX transfers can be VERY long in the worst case */
-
- timeout = MAX(5000, timeout);
- }
+ /* Start the watchdog timer */
delay = MSEC2TICK(timeout);
ret = wd_start(&priv->waitwdog, delay,
@@ -2980,7 +2972,7 @@ static int sam_dmarecvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
DEBUGASSERT(nblocks > 0 && blocksize > 0 && (blocksize & 3) == 0);
- /* Physical address of the HSCMI source register, either the TDR (for
+ /* Physical address of the HSCMI source register, either the RDR (for
* single transfers) or the first FIFO register, and the physical address
* of the buffer in RAM.
*/
@@ -3135,7 +3127,7 @@ static int sam_dmasendsetup(struct sdio_dev_s *dev,
sam_dmastart(priv->dma, sam_dmacallback, priv);
/* Configure transfer-related interrupts. Transfer interrupts are not
- * enabled until after the transfer is start with an SD command (i.e.,
+ * enabled until after the transfer is started with an SD command (i.e.,
* at the beginning of sam_eventwait().
*/
diff --git a/arch/arm/src/samv7/sam_xdmac.c b/arch/arm/src/samv7/sam_xdmac.c
index d1f9dd6d19..18b3cf61ef 100644
--- a/arch/arm/src/samv7/sam_xdmac.c
+++ b/arch/arm/src/samv7/sam_xdmac.c
@@ -2141,7 +2141,7 @@ void sam_dmastop(DMA_HANDLE handle)
* Name: sam_destaddr
*
* Description:
- * Returns the pointer to the destionation address, i.e the last address
+ * Returns the pointer to the destination address, i.e the last address
* data were written by DMA.
*
* Assumptions:
diff --git a/arch/arm/src/samv7/sam_xdmac.h b/arch/arm/src/samv7/sam_xdmac.h
index f77a78eb63..533fa488d9 100644
--- a/arch/arm/src/samv7/sam_xdmac.h
+++ b/arch/arm/src/samv7/sam_xdmac.h
@@ -228,7 +228,7 @@ extern "C"
* Name: sam_destaddr
*
* Description:
- * Returns the pointer to the destionation address, i.e the last address
+ * Returns the pointer to the destination address, i.e the last address
* data were written by DMA.
*
* Assumptions:
diff --git a/boards/arm/samv7/samv71-xult/README.txt b/boards/arm/samv7/samv71-xult/README.txt
index 8b002d871d..359123da40 100644
--- a/boards/arm/samv7/samv71-xult/README.txt
+++ b/boards/arm/samv7/samv71-xult/README.txt
@@ -84,19 +84,11 @@ to a particular configuration.
is very low priority to me but might be important to you if you are need
very high performance SD card accesses.
- 2. HSMCI TX DMA is currently disabled for the SAMV7. There is some
- issue with the TX DMA setup. This is a bug that needs to be resolved.
-
- DMA is enabled by these settings in the file arch/arm/src/samv7/sam_hsmci.c:
-
- #undef HSCMI_NORXDMA /* Define to disable RX DMA */
- #define HSCMI_NOTXDMA 1 /* Define to disable TX DMA */
-
- 3. There may also be some issues with removing and re-inserting SD cards
+ 2. There may also be some issues with removing and re-inserting SD cards
(of course with appropriate mounting and unmounting). I all not sure
of this and need to do more testing to characterize if the issue.
- 4. There is a port of the SAMA5D4-EK Ethernet driver to the SAMV71-XULT.
+ 3. There is a port of the SAMA5D4-EK Ethernet driver to the SAMV71-XULT.
This driver appears to be 100% functional with the following caveats:
- There is a compiler optimization issue. At -O2, there is odd
@@ -116,7 +108,7 @@ to a particular configuration.
Setting write through mode eliminates the need for cleaning the D-Cache.
If only reloading and invalidating are done, then there is no problem.
- 5. The USBHS device controller driver (DCD) is also fully functional. It
+ 4. The USBHS device controller driver (DCD) is also fully functional. It
has only be tested with the CDC/ACM driver as described below. Like
the Ethernet driver:
@@ -129,29 +121,29 @@ to a particular configuration.
only detects bus reset events. This is probably some issue with
480MHZ high speed clock setup, but I have not yet found the issue.
- 6. The full port for audio support is code complete: WM8904 driver,
+ 5. The full port for audio support is code complete: WM8904 driver,
SSC/I2C driver, and CS2100-CP driver. But this code is untested. The
WM8904 interface was taken directly from the SAMA5D4-EK and may well
need modification due to differences with the physical WM8904
interface.
- 7. An MCAN driver as added and verified on 2015-08-08 using the loopback
+ 6. An MCAN driver as added and verified on 2015-08-08 using the loopback
test at apps/examples/can. Like the Ethernet driver, the MCAN driver
does not work if the D-Cache is configured in write-back mode; write-
through mode is required.
- 8. An SPI slave driver as added on 2015-08-09 but has not been verified
+ 7. An SPI slave driver as added on 2015-08-09 but has not been verified
as of this writing. See discussion in include/nuttx/spi/slave.h and
in the section entitle "SPI Slave" below.
- 9. A QSPI FLASH driver was added and verified on 2015-11-10. This driver
+ 8. A QSPI FLASH driver was added and verified on 2015-11-10. This driver
operated in the memory mapped Serial Memory Mode (SMM). See the
"S25FL116K QuadSPI FLASH" section below for further information.
- 10. On-chip FLASH support as added and verified on 2015-11-13. See the
+ 9. On-chip FLASH support as added and verified on 2015-11-13. See the
"Program FLASH Access" section below for further information.
- 11. The knsh "protected mode" configuration was added on 2015-11-18. The
+ 10. The knsh "protected mode" configuration was added on 2015-11-18. The
configuration has not been tested as of this writing.
Serial Console