[GitHub] [tvm] wrongtest-intellif commented on a diff in pull request #12757: [TIR] Fix plan buffer allocation location for loop carried dependencies

[GitBox <gi...@apache.org>]

wrongtest-intellif commented on code in PR #12757:
URL: https://github.com/apache/tvm/pull/12757#discussion_r974191510


##########
tests/python/unittest/test_tir_transform_plan_update_buffer_allocation_location.py:
##########
@@ -242,9 +243,107 @@ def test_lower_te():
     )  # PlanAndUpdateBufferAllocationLocation should do nothing on TE
 
 
+def test_loop_carried_dependency():
+    """The buffer allocation should be above opaque iter var's loop scopes
+    such that buffer accesses with loop carried dependencies are covered."""
+
+    @T.prim_func
+    def before(A: T.Buffer[(8, 8, 8), "int32"], B: T.Buffer[(8, 8, 8), "int32"]):
+        C = T.alloc_buffer([8, 8, 8], dtype="int32")
+        for i in T.serial(8):
+            for j in T.serial(8):
+                for k in T.serial(8):
+                    with T.block("b0"):
+                        vi, vj, vk = T.axis.remap("SSS", [i, j, k])
+                        C[vi, vj, vk] = A[vi, vj, vk] + 1
+                for k in T.serial(8):
+                    with T.block("b1"):
+                        vi, vk = T.axis.remap("SS", [i, k])
+                        vj = T.axis.opaque(8, j)
+                        B[vi, vj, vk] = C[vi, vj, vk] + T.if_then_else(
+                            0 < vj, C[vi, vj - j, vk], 0, dtype="int32"

Review Comment:
   typo vj - j



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