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Posted to commits@nuttx.apache.org by ac...@apache.org on 2021/05/15 11:38:44 UTC
[incubator-nuttx] branch master updated: riscv/esp32c3: Add
ESP32-C3 LEDC(PWM) driver
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new beed26b6 riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver
beed26b6 is described below
commit beed26b6bf68f9f03913045537575f2943010022
Author: Dong Heng <do...@espressif.com>
AuthorDate: Mon May 3 13:52:39 2021 +0800
riscv/esp32c3: Add ESP32-C3 LEDC(PWM) driver
---
arch/risc-v/src/esp32c3/Kconfig | 70 +
arch/risc-v/src/esp32c3/Make.defs | 4 +
arch/risc-v/src/esp32c3/esp32c3_ledc.c | 776 ++++++
arch/risc-v/src/esp32c3/esp32c3_ledc.h | 52 +
arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h | 2742 ++++++++++++++++++++
.../esp32c3/esp32c3-devkit/configs/pwm/defconfig | 47 +
boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile | 4 +
.../esp32c3/esp32c3-devkit/src/esp32c3-devkit.h | 12 +
.../esp32c3/esp32c3-devkit/src/esp32c3_bringup.c | 8 +
.../esp32c3/esp32c3-devkit/src/esp32c3_ledc.c | 116 +
10 files changed, 3831 insertions(+)
diff --git a/arch/risc-v/src/esp32c3/Kconfig b/arch/risc-v/src/esp32c3/Kconfig
index 8899081..bce1ec8 100644
--- a/arch/risc-v/src/esp32c3/Kconfig
+++ b/arch/risc-v/src/esp32c3/Kconfig
@@ -178,6 +178,11 @@ config ESP32C3_SPI
bool
default n
+config ESP32C3_LEDC
+ bool "LEDC (PWM)"
+ default n
+ select PWM
+
config ESP32C3_GPIO_IRQ
bool "GPIO pin interrupts"
default n
@@ -418,6 +423,71 @@ config ESP32C3_FREERUN
endmenu # Timer/counter Configuration
endif # ESP32C3_TIMER
+menu "LEDC configuration"
+ depends on ESP32C3_LEDC
+
+menuconfig ESP32C3_LEDC_TIM0
+ bool "Timer 0"
+ default n
+
+if ESP32C3_LEDC_TIM0
+
+config ESP32C3_LEDC_TIM0_CHANNELS
+ int "Number of Timer 0 channels"
+ default 2
+
+endif # ESP32C3_LEDC_TIM0
+
+menuconfig ESP32C3_LEDC_TIM1
+ bool "Timer 1"
+ default n
+
+if ESP32C3_LEDC_TIM1
+
+config ESP32C3_LEDC_TIM1_CHANNELS
+ int "Number of Timer 1 channels"
+ default 2
+
+endif # ESP32C3_LEDC_TIM1
+
+menuconfig ESP32C3_LEDC_TIM2
+ bool "Timer 2"
+ default n
+
+if ESP32C3_LEDC_TIM2
+
+config ESP32C3_LEDC_TIM2_CHANNELS
+ int "Number of Timer 2 channels"
+ default 2
+
+endif # ESP32C3_LEDC_TIM2
+
+config ESP32C3_LEDC_CHANNEL0_PIN
+ int "Channel 0 pin"
+ default 2
+
+config ESP32C3_LEDC_CHANNEL1_PIN
+ int "Channel 1 pin"
+ default 3
+
+config ESP32C3_LEDC_CHANNEL2_PIN
+ int "Channel 2 pin"
+ default 4
+
+config ESP32C3_LEDC_CHANNEL3_PIN
+ int "Channel 3 pin"
+ default 5
+
+config ESP32C3_LEDC_CHANNEL4_PIN
+ int "Channel 4 pin"
+ default 6
+
+config ESP32C3_LEDC_CHANNEL5_PIN
+ int "Channel 5 pin"
+ default 7
+
+endmenu # LEDC configuration
+
menu "Wi-Fi configuration"
depends on ESP32C3_WIRELESS
diff --git a/arch/risc-v/src/esp32c3/Make.defs b/arch/risc-v/src/esp32c3/Make.defs
index a65498b..049d85e 100644
--- a/arch/risc-v/src/esp32c3/Make.defs
+++ b/arch/risc-v/src/esp32c3/Make.defs
@@ -121,6 +121,10 @@ endif
CHIP_CSRCS += esp32c3_rtc.c
+ifeq ($(CONFIG_ESP32C3_LEDC),y)
+CHIP_CSRCS += esp32c3_ledc.c
+endif
+
ifeq ($(CONFIG_ESP32C3_WIRELESS),y)
WIRELESS_DRV_UNPACK = esp-wireless-drivers-3rdparty
WIRELESS_DRV_ID = 2b53111
diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.c b/arch/risc-v/src/esp32c3/esp32c3_ledc.c
new file mode 100644
index 0000000..c769d26
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_ledc.c
@@ -0,0 +1,776 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_ledc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <inttypes.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+#include <debug.h>
+#include <errno.h>
+
+#include "esp32c3.h"
+#include "esp32c3_clockconfig.h"
+#include "esp32c3_gpio.h"
+#include "esp32c3_ledc.h"
+
+#include "riscv_arch.h"
+#include "hardware/esp32c3_ledc.h"
+#include "hardware/esp32c3_system.h"
+#include "hardware/esp32c3_gpio_sigmap.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* LEDC total timers */
+
+#define LEDC_TIMERS (3)
+
+/* LEDC total channels */
+
+#if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_CHANNELS (6)
+#else
+# define LEDC_CHANNELS (3)
+#endif
+
+/* LEDC timer0 channels and offset */
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM0
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM0_CHANS CONFIG_ESP32C3_LEDC_TIM0_CHANNELS
+# else
+# define LEDC_TIM0_CHANS (1)
+# endif
+# define LEDC_TIM0_CHANS_OFF (0)
+#endif
+
+/* LEDC timer1 channels and offset */
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM1
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM1_CHANS CONFIG_ESP32C3_LEDC_TIM1_CHANNELS
+# else
+# define LEDC_TIM1_CHANS (1)
+# endif
+# define LEDC_TIM1_CHANS_OFF (LEDC_TIM0_CHANS_OFF + LEDC_TIM0_CHANS)
+#endif
+
+/* LEDC timer2 channels and offset */
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM2
+# if defined(CONFIG_PWM_NCHANNELS) && CONFIG_PWM_NCHANNELS > 1
+# define LEDC_TIM2_CHANS CONFIG_ESP32C3_LEDC_TIM2_CHANNELS
+# else
+# define LEDC_TIM2_CHANS (1)
+# endif
+
+# define LEDC_TIM2_CHANS_OFF (LEDC_TIM1_CHANS_OFF + LEDC_TIM1_CHANS)
+#endif
+
+/* LEDC clock resource */
+
+#define LEDC_CLK_RES (1) /* APB clock */
+
+/* LEDC timer max reload */
+
+#define LEDC_RELOAD_MAX (16384) /* 2^14 */
+
+/* LEDC timer max clock divider parameter */
+
+#define LEDC_CLKDIV_MAX (1024) /* 2^10 */
+
+/* LEDC timer registers mapping */
+
+#define LEDC_TIMER_REG(r, n) ((r) + (n) * (LEDC_TIMER1_CONF_REG - \
+ LEDC_TIMER2_CONF_REG))
+
+/* LEDC timer channel registers mapping */
+
+#define LEDC_CHAN_REG(r, n) ((r) + (n) * (LEDC_CH0_CONF0_REG - \
+ LEDC_CH1_CONF0_REG))
+
+#define SET_TIMER_BITS(t, r, b) setbits(b, LEDC_TIMER_REG(r, (t)->num));
+#define SET_TIMER_REG(t, r, v) putreg32(v, LEDC_TIMER_REG(r, (t)->num));
+
+#define SET_CHAN_BITS(c, r, b) setbits(b, LEDC_CHAN_REG(r, (c)->num));
+#define SET_CHAN_REG(c, r, v) putreg32(v, LEDC_CHAN_REG(r, (c)->num));
+
+#ifndef MIN
+# define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/* LEDC timer channel configuration */
+
+struct esp32c3_ledc_chan_s
+{
+ const uint8_t num; /* Timer channel ID */
+ const uint8_t pin; /* Timer channel GPIO pin number */
+
+ uint16_t duty; /* Timer channel current duty */
+};
+
+/* This structure represents the state of one LEDC timer */
+
+struct esp32c3_ledc_s
+{
+ const struct pwm_ops_s *ops; /* PWM operations */
+
+ const uint8_t num; /* Timer ID */
+
+ const uint8_t channels; /* Timer channels number */
+ struct esp32c3_ledc_chan_s *chans; /* Timer channels pointer */
+
+ uint32_t frequency; /* Timer current frequency */
+ uint32_t reload; /* Timer current reload */
+};
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int pwm_setup(struct pwm_lowerhalf_s *dev);
+static int pwm_shutdown(struct pwm_lowerhalf_s *dev);
+static int pwm_start(struct pwm_lowerhalf_s *dev,
+ const struct pwm_info_s *info);
+static int pwm_stop(struct pwm_lowerhalf_s *dev);
+static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd,
+ unsigned long arg);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* LEDC PWM operations */
+
+static const struct pwm_ops_s g_pwmops =
+{
+ .setup = pwm_setup,
+ .shutdown = pwm_shutdown,
+ .start = pwm_start,
+ .stop = pwm_stop,
+ .ioctl = pwm_ioctl
+};
+
+/* LEDC channels table */
+
+static struct esp32c3_ledc_chan_s g_ledc_chans[LEDC_CHANNELS] =
+{
+ {
+ .num = 0,
+ .pin = CONFIG_ESP32C3_LEDC_CHANNEL0_PIN
+ },
+
+ {
+ .num = 1,
+ .pin = CONFIG_ESP32C3_LEDC_CHANNEL1_PIN
+ },
+
+ {
+ .num = 2,
+ .pin = CONFIG_ESP32C3_LEDC_CHANNEL2_PIN
+ },
+
+#if LEDC_CHANNELS > 3
+ {
+ .num = 3,
+ .pin = CONFIG_ESP32C3_LEDC_CHANNEL3_PIN
+ },
+
+ {
+ .num = 4,
+ .pin = CONFIG_ESP32C3_LEDC_CHANNEL4_PIN
+ },
+
+ {
+ .num = 5,
+ .pin = CONFIG_ESP32C3_LEDC_CHANNEL5_PIN
+ }
+#endif
+};
+
+/* LEDC timer0 private data */
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM0
+static struct esp32c3_ledc_s g_pwm0dev =
+{
+ .ops = &g_pwmops,
+ .num = 0,
+ .channels = LEDC_TIM0_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM0_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32C3_LEDC_TIM0 */
+
+/* LEDC timer1 private data */
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM1
+static struct esp32c3_ledc_s g_pwm1dev =
+{
+ .ops = &g_pwmops,
+ .num = 1,
+ .channels = LEDC_TIM1_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM1_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32C3_LEDC_TIM1 */
+
+/* LEDC timer2 private data */
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM2
+static struct esp32c3_ledc_s g_pwm2dev =
+{
+ .ops = &g_pwmops,
+ .num = 2,
+ .channels = LEDC_TIM2_CHANS,
+ .chans = &g_ledc_chans[LEDC_TIM2_CHANS_OFF]
+};
+#endif /* CONFIG_ESP32C3_LEDC_TIM2 */
+
+/* Clock reference count */
+
+static uint32_t g_clk_ref;
+
+/****************************************************************************
+ * Private functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ledc_enable_clk
+ *
+ * Description:
+ * Enable LEDC clock.
+ *
+ * Input Parameters:
+ * NOne
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void ledc_enable_clk(void)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ if (!g_clk_ref)
+ {
+ setbits(SYSTEM_LEDC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG);
+ resetbits(SYSTEM_LEDC_RST, SYSTEM_PERIP_RST_EN0_REG);
+
+ putreg32(LEDC_CLK_RES, LEDC_CONF_REG);
+
+ pwminfo("Enable ledc clock\n");
+ }
+
+ g_clk_ref++;
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: ledc_disable_clk
+ *
+ * Description:
+ * Disable LEDC clock.
+ *
+ * Input Parameters:
+ * NOne
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void ledc_disable_clk(void)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ g_clk_ref--;
+
+ if (!g_clk_ref)
+ {
+ pwminfo("Disable ledc clock\n");
+
+ setbits(SYSTEM_LEDC_RST, SYSTEM_PERIP_RST_EN0_REG);
+ resetbits(SYSTEM_LEDC_CLK_EN, SYSTEM_PERIP_CLK_EN0_REG);
+ }
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: setup_timer
+ *
+ * Description:
+ * Setup LEDC timer frequency and reload.
+ *
+ * Input Parameters:
+ * priv - A reference to the LEDC timer state structure
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void setup_timer(struct esp32c3_ledc_s *priv)
+{
+ irqstate_t flags;
+ uint32_t regval;
+ uint32_t reload;
+ uint32_t prescaler;
+ uint32_t shift = 1;
+ uint64_t pwmclk = esp32c3_clk_apb_freq();
+
+ /* Reset timer */
+
+ SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_RST);
+
+ /* Calculate optimal values for the timer prescaler and for the timer
+ * modulo register. If' frequency' is the desired frequency, then
+ *
+ * tpmclk = pwmclk / presc
+ * frequency = tpmclk / reload
+ *
+ * ==>
+ *
+ * reload = pwmclk / presc / frequency
+ *
+ * In ESP32-C3, there are 4 clock resources for PWM:
+ *
+ * 1. APB clock (80 MHz)
+ * 2. RTC clock (8 MHz)
+ * 3. XTAL clock (depends on hardware, generally is 40 MHz)
+ * 4. REF clock (this is APB clock divided, generally is 1 MHz)
+ *
+ * We mostly use APB clock generally.
+ *
+ * There are many solutions to this, but the best solution will be the one
+ * that has the largest reload value and the smallest prescaler value.
+ * That is the solution that should give us the most accuracy in the timer
+ * control. Subject to:
+ *
+ * 2 <= presc <= 2^14(16,384)
+ * 1 <= clkdiv <= 2^10
+ *
+ * clkdiv has 8-bit decimal precision, so
+ * clkdiv = pwmclk * 256 / 16384 / frequency would be optimal.
+ *
+ * Example:
+ *
+ * pwmclk = 80 MHz
+ * frequency = 100 Hz
+ *
+ * presc = 80,000,000 * 256 / 16,384 / 100
+ * = 12,500
+ * timclk = 80,000,000 / (12,500 / 256)
+ * = 1,638,400
+ * counter = 1,638,400 / 100
+ * = 16,384
+ * = 2^14
+ * shift = 14
+ */
+
+ reload = (pwmclk * 256 / priv->frequency + LEDC_CLKDIV_MAX) /
+ LEDC_CLKDIV_MAX;
+ if (reload == 0)
+ {
+ reload = 1;
+ }
+ else if (reload > LEDC_RELOAD_MAX)
+ {
+ reload = LEDC_RELOAD_MAX;
+ }
+
+ for (int c = 2; c <= LEDC_RELOAD_MAX; c *= 2)
+ {
+ if (c * 2 > reload)
+ {
+ reload = c;
+ break;
+ }
+
+ shift++;
+ }
+
+ prescaler = pwmclk * 256 / reload / priv->frequency;
+
+ pwminfo("PWM timer%" PRIu8 " frequency=%0.4f reload=%" PRIu32 " shift=%" \
+ PRIu32 " prescaler=%0.4f\n",
+ priv->num, (float)pwmclk / reload / ((float)prescaler / 256),
+ reload, shift, (float)prescaler / 256);
+
+ /* Store reload for channel duty */
+
+ priv->reload = reload;
+
+ flags = enter_critical_section();
+
+ /* Set timer clock divide and reload */
+
+ regval = (shift << LEDC_TIMER0_DUTY_RES_S) |
+ (prescaler << LEDC_CLK_DIV_TIMER0_S);
+ SET_TIMER_REG(priv, LEDC_TIMER0_CONF_REG, regval);
+
+ /* Update clock divide and reload to hardware */
+
+ SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_PARA_UP);
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: setup_channel
+ *
+ * Description:
+ * Setup LEDC timer channel duty.
+ *
+ * Input Parameters:
+ * priv - A reference to the LEDC timer state structure
+ * cn - Timer channel number
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void setup_channel(struct esp32c3_ledc_s *priv, int cn)
+{
+ irqstate_t flags;
+ uint32_t regval;
+ struct esp32c3_ledc_chan_s *chan = &priv->chans[cn];
+
+ /* Duty cycle:
+ *
+ * duty cycle = duty / 65536 * reload (fractional value)
+ */
+
+ regval = b16toi(chan->duty * priv->reload + b16HALF);
+
+ pwminfo("channel=%" PRIu8 " duty=%" PRIu16 "(%0.4f) regval=%" PRIu32 \
+ " reload=%" PRIu32 "\n",
+ chan->num, chan->duty, (float)chan->duty / UINT16_MAX,
+ regval, priv->reload);
+
+ flags = enter_critical_section();
+
+ /* Reset config 0 & 1 registers */
+
+ SET_CHAN_REG(chan, LEDC_CH0_CONF0_REG, 0);
+ SET_CHAN_REG(chan, LEDC_CH0_CONF1_REG, 0);
+
+ /* Set pulse phase 0 */
+
+ SET_CHAN_REG(chan, LEDC_CH0_HPOINT_REG, 0);
+
+ /* Duty register uses bits [18:4] */
+
+ SET_CHAN_REG(chan, LEDC_CH0_DUTY_REG, regval << 4);
+
+ /* Start GPIO output */
+
+ SET_CHAN_BITS(chan, LEDC_CH0_CONF0_REG, LEDC_SIG_OUT_EN_CH0);
+
+ /* Start Duty counter */
+
+ SET_CHAN_BITS(chan, LEDC_CH0_CONF1_REG, LEDC_DUTY_START_CH0);
+
+ /* Update duty and phase to hardware */
+
+ SET_CHAN_BITS(chan, LEDC_CH0_CONF0_REG, LEDC_PARA_UP_CH0);
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: pwm_setup
+ *
+ * Description:
+ * This method is called when the driver is opened. The lower half driver
+ * should configure and initialize the device so that it is ready for use.
+ * It should not, however, output pulses until the start method is called.
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_setup(struct pwm_lowerhalf_s *dev)
+{
+ struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev;
+
+ pwminfo("PWM timer%d\n", priv->num);
+
+ ledc_enable_clk();
+
+ /* Setup channel GPIO pins */
+
+ for (int i = 0; i < priv->channels; i++)
+ {
+ pwminfo("channel%d --> pin%d\n", priv->chans[i].num,
+ priv->chans[i].pin);
+
+ esp32c3_configgpio(priv->chans[i].pin, OUTPUT | PULLUP);
+ esp32c3_gpio_matrix_out(priv->chans[i].pin,
+ LEDC_LS_SIG_OUT0_IDX + priv->chans[i].num,
+ 0, 0);
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_shutdown
+ *
+ * Description:
+ * This method is called when the driver is closed. The lower half driver
+ * stop pulsed output, free any resources, disable the timer hardware, and
+ * put the system into the lowest possible power usage state
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_shutdown(struct pwm_lowerhalf_s *dev)
+{
+ struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev;
+#ifdef CONFIG_PWM_NCHANNELS
+ int channels = MIN(priv->channels, CONFIG_PWM_NCHANNELS);
+#else
+ int channels = 1;
+#endif
+
+ /* Stop timer */
+
+ pwm_stop(dev);
+
+ /* Clear timer and channel configuration */
+
+ priv->frequency = 0;
+ priv->reload = 0;
+ for (int i = 0; i < channels; i++)
+ {
+ priv->chans[i].duty = 0;
+ }
+
+ ledc_disable_clk();
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_start
+ *
+ * Description:
+ * (Re-)initialize the timer resources and start the pulsed output
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * info - A reference to the characteristics of the pulsed output
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_start(struct pwm_lowerhalf_s *dev,
+ const struct pwm_info_s *info)
+{
+ struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev;
+#ifdef CONFIG_PWM_NCHANNELS
+ int channels = MIN(priv->channels, CONFIG_PWM_NCHANNELS);
+#else
+ int channels = 1;
+#endif
+
+ pwminfo("PWM timer%d\n", priv->num);
+
+ /* Update timer with given PWM timer frequency */
+
+ if (priv->frequency != info->frequency)
+ {
+ priv->frequency = info->frequency;
+ setup_timer(priv);
+ }
+
+ /* Update timer with given PWM channel duty */
+
+ for (int i = 0; i < channels; i++)
+ {
+ if (priv->chans[i].duty != info[i].duty)
+ {
+ priv->chans[i].duty = info[i].duty;
+ setup_channel(priv, i);
+ }
+ }
+
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_stop
+ *
+ * Description:
+ * Stop the pulsed output and reset the timer resources.
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_stop(struct pwm_lowerhalf_s *dev)
+{
+ irqstate_t flags;
+ struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev;
+
+ pwminfo("PWM timer%d\n", priv->num);
+
+ flags = enter_critical_section();
+
+ /* Stop timer */
+
+ SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_PAUSE);
+
+ /* Reset timer */
+
+ SET_TIMER_BITS(priv, LEDC_TIMER0_CONF_REG, LEDC_TIMER0_RST);
+
+ leave_critical_section(flags);
+ return 0;
+}
+
+/****************************************************************************
+ * Name: pwm_ioctl
+ *
+ * Description:
+ * Lower-half logic may support platform-specific ioctl commands
+ *
+ * Input Parameters:
+ * dev - A reference to the lower half PWM driver state structure
+ * cmd - The ioctl command
+ * arg - The argument accompanying the ioctl command
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure
+ *
+ ****************************************************************************/
+
+static int pwm_ioctl(struct pwm_lowerhalf_s *dev, int cmd,
+ unsigned long arg)
+{
+#ifdef CONFIG_DEBUG_PWM_INFO
+ struct esp32c3_ledc_s *priv = (struct esp32c3_ledc_s *)dev;
+
+ pwminfo("PWM timer%d\n", priv->num);
+#endif
+
+ return -ENOTTY;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_ledc_init
+ *
+ * Description:
+ * Initialize one LEDC timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * timer - A number identifying the timer use.
+ *
+ * Returned Value:
+ * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is
+ * returned. NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+struct pwm_lowerhalf_s *esp32c3_ledc_init(int timer)
+{
+ struct esp32c3_ledc_s *lower = NULL;
+
+ pwminfo("TIM%u\n", timer);
+
+ switch (timer)
+ {
+#ifdef CONFIG_ESP32C3_LEDC_TIM0
+ case 0:
+ {
+ lower = &g_pwm0dev;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM1
+ case 1:
+ {
+ lower = &g_pwm1dev;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM2
+ case 2:
+ {
+ lower = &g_pwm2dev;
+ break;
+ }
+#endif
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM3
+ case 3:
+ {
+ lower = &g_pwm3dev;
+ break;
+ }
+#endif
+
+ default:
+ {
+ pwmerr("ERROR: No such timer configured %d\n", timer);
+ lower = NULL;
+ break;
+ }
+ }
+
+ return (struct pwm_lowerhalf_s *)lower;
+}
diff --git a/arch/risc-v/src/esp32c3/esp32c3_ledc.h b/arch/risc-v/src/esp32c3/esp32c3_ledc.h
new file mode 100644
index 0000000..73ece77
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/esp32c3_ledc.h
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/esp32c3_ledc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H
+#define __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/timers/pwm.h>
+
+/****************************************************************************
+ * Public functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_ledc_init
+ *
+ * Description:
+ * Initialize one LEDC timer for use with the upper_level PWM driver.
+ *
+ * Input Parameters:
+ * timer - A number identifying the timer use.
+ *
+ * Returned Value:
+ * On success, a pointer to the ESP32-C3 LEDC lower half PWM driver is
+ * returned. NULL is returned on any failure.
+ *
+ ****************************************************************************/
+
+struct pwm_lowerhalf_s *esp32c3_ledc_init(int timer);
+
+#endif /* __ARCH_RISCV_SRC_ESP32C3_ESP32C3_LEDC_H */
diff --git a/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h b/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h
new file mode 100644
index 0000000..6b8846b
--- /dev/null
+++ b/arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h
@@ -0,0 +1,2742 @@
+/****************************************************************************
+ * arch/risc-v/src/esp32c3/hardware/esp32c3_ledc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H
+#define __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32c3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* LEDC_CH0_CONF0_REG register
+ * Configuration register 0 for channel 0
+ */
+
+#define LEDC_CH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0)
+
+/* LEDC_TIMER_SEL_CH0 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 0.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH0 0x00000003
+#define LEDC_TIMER_SEL_CH0_M (LEDC_TIMER_SEL_CH0_V << LEDC_TIMER_SEL_CH0_S)
+#define LEDC_TIMER_SEL_CH0_V 0x00000003
+#define LEDC_TIMER_SEL_CH0_S 0
+
+/* LEDC_SIG_OUT_EN_CH0 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 0.
+ */
+
+#define LEDC_SIG_OUT_EN_CH0 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH0_M (LEDC_SIG_OUT_EN_CH0_V << LEDC_SIG_OUT_EN_CH0_S)
+#define LEDC_SIG_OUT_EN_CH0_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH0_S 2
+
+/* LEDC_IDLE_LV_CH0 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 0 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH0 (BIT(3))
+#define LEDC_IDLE_LV_CH0_M (LEDC_IDLE_LV_CH0_V << LEDC_IDLE_LV_CH0_S)
+#define LEDC_IDLE_LV_CH0_V 0x00000001
+#define LEDC_IDLE_LV_CH0_S 3
+
+/* LEDC_PARA_UP_CH0 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH0_HPOINT and LEDC_CH0_DUTY for
+ * channel 0.
+ */
+
+#define LEDC_PARA_UP_CH0 (BIT(4))
+#define LEDC_PARA_UP_CH0_M (LEDC_PARA_UP_CH0_V << LEDC_PARA_UP_CH0_S)
+#define LEDC_PARA_UP_CH0_V 0x00000001
+#define LEDC_PARA_UP_CH0_S 4
+
+/* LEDC_OVF_NUM_CH0 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH0_INT interrupt will be triggered when channel 0
+ * overflows for (LEDC_OVF_NUM_CH0 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH0 0x000003FF
+#define LEDC_OVF_NUM_CH0_M (LEDC_OVF_NUM_CH0_V << LEDC_OVF_NUM_CH0_S)
+#define LEDC_OVF_NUM_CH0_V 0x000003FF
+#define LEDC_OVF_NUM_CH0_S 5
+
+/* LEDC_OVF_CNT_EN_CH0 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 0.
+ */
+
+#define LEDC_OVF_CNT_EN_CH0 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH0_M (LEDC_OVF_CNT_EN_CH0_V << LEDC_OVF_CNT_EN_CH0_S)
+#define LEDC_OVF_CNT_EN_CH0_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH0_S 15
+
+/* LEDC_OVF_CNT_RESET_CH0 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 0.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH0 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH0_M (LEDC_OVF_CNT_RESET_CH0_V << LEDC_OVF_CNT_RESET_CH0_S)
+#define LEDC_OVF_CNT_RESET_CH0_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH0_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH0 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH0.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH0 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH0_M (LEDC_OVF_CNT_RESET_ST_CH0_V << LEDC_OVF_CNT_RESET_ST_CH0_S)
+#define LEDC_OVF_CNT_RESET_ST_CH0_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH0_S 17
+
+/* LEDC_CH0_HPOINT_REG register
+ * High point register for channel 0
+ */
+
+#define LEDC_CH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x4)
+
+/* LEDC_HPOINT_CH0 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH0 0x00003FFF
+#define LEDC_HPOINT_CH0_M (LEDC_HPOINT_CH0_V << LEDC_HPOINT_CH0_S)
+#define LEDC_HPOINT_CH0_V 0x00003FFF
+#define LEDC_HPOINT_CH0_S 0
+
+/* LEDC_CH0_DUTY_REG register
+ * Initial duty cycle for channel 0
+ */
+
+#define LEDC_CH0_DUTY_REG (DR_REG_LEDC_BASE + 0x8)
+
+/* LEDC_DUTY_CH0 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH0 0x0007FFFF
+#define LEDC_DUTY_CH0_M (LEDC_DUTY_CH0_V << LEDC_DUTY_CH0_S)
+#define LEDC_DUTY_CH0_V 0x0007FFFF
+#define LEDC_DUTY_CH0_S 0
+
+/* LEDC_CH0_CONF1_REG register
+ * Configuration register 1 for channel 0
+ */
+
+#define LEDC_CH0_CONF1_REG (DR_REG_LEDC_BASE + 0xc)
+
+/* LEDC_DUTY_SCALE_CH0 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 0.
+ */
+
+#define LEDC_DUTY_SCALE_CH0 0x000003FF
+#define LEDC_DUTY_SCALE_CH0_M (LEDC_DUTY_SCALE_CH0_V << LEDC_DUTY_SCALE_CH0_S)
+#define LEDC_DUTY_SCALE_CH0_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH0_S 0
+
+/* LEDC_DUTY_CYCLE_CH0 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH0 on channel 0.
+ */
+
+#define LEDC_DUTY_CYCLE_CH0 0x000003FF
+#define LEDC_DUTY_CYCLE_CH0_M (LEDC_DUTY_CYCLE_CH0_V << LEDC_DUTY_CYCLE_CH0_S)
+#define LEDC_DUTY_CYCLE_CH0_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH0_S 10
+
+/* LEDC_DUTY_NUM_CH0 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH0 0x000003FF
+#define LEDC_DUTY_NUM_CH0_M (LEDC_DUTY_NUM_CH0_V << LEDC_DUTY_NUM_CH0_S)
+#define LEDC_DUTY_NUM_CH0_V 0x000003FF
+#define LEDC_DUTY_NUM_CH0_S 20
+
+/* LEDC_DUTY_INC_CH0 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 0. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH0 (BIT(30))
+#define LEDC_DUTY_INC_CH0_M (LEDC_DUTY_INC_CH0_V << LEDC_DUTY_INC_CH0_S)
+#define LEDC_DUTY_INC_CH0_V 0x00000001
+#define LEDC_DUTY_INC_CH0_S 30
+
+/* LEDC_DUTY_START_CH0 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH0_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH0 (BIT(31))
+#define LEDC_DUTY_START_CH0_M (LEDC_DUTY_START_CH0_V << LEDC_DUTY_START_CH0_S)
+#define LEDC_DUTY_START_CH0_V 0x00000001
+#define LEDC_DUTY_START_CH0_S 31
+
+/* LEDC_CH0_DUTY_R_REG register
+ * Current duty cycle for channel 0
+ */
+
+#define LEDC_CH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x10)
+
+/* LEDC_DUTY_R_CH0 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 0.
+ */
+
+#define LEDC_DUTY_R_CH0 0x0007FFFF
+#define LEDC_DUTY_R_CH0_M (LEDC_DUTY_R_CH0_V << LEDC_DUTY_R_CH0_S)
+#define LEDC_DUTY_R_CH0_V 0x0007FFFF
+#define LEDC_DUTY_R_CH0_S 0
+
+/* LEDC_CH1_CONF0_REG register
+ * Configuration register 0 for channel 1
+ */
+
+#define LEDC_CH1_CONF0_REG (DR_REG_LEDC_BASE + 0x14)
+
+/* LEDC_TIMER_SEL_CH1 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 1.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH1 0x00000003
+#define LEDC_TIMER_SEL_CH1_M (LEDC_TIMER_SEL_CH1_V << LEDC_TIMER_SEL_CH1_S)
+#define LEDC_TIMER_SEL_CH1_V 0x00000003
+#define LEDC_TIMER_SEL_CH1_S 0
+
+/* LEDC_SIG_OUT_EN_CH1 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 1.
+ */
+
+#define LEDC_SIG_OUT_EN_CH1 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH1_M (LEDC_SIG_OUT_EN_CH1_V << LEDC_SIG_OUT_EN_CH1_S)
+#define LEDC_SIG_OUT_EN_CH1_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH1_S 2
+
+/* LEDC_IDLE_LV_CH1 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 1 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH1 (BIT(3))
+#define LEDC_IDLE_LV_CH1_M (LEDC_IDLE_LV_CH1_V << LEDC_IDLE_LV_CH1_S)
+#define LEDC_IDLE_LV_CH1_V 0x00000001
+#define LEDC_IDLE_LV_CH1_S 3
+
+/* LEDC_PARA_UP_CH1 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH1_HPOINT and LEDC_CH1_DUTY for
+ * channel 1.
+ */
+
+#define LEDC_PARA_UP_CH1 (BIT(4))
+#define LEDC_PARA_UP_CH1_M (LEDC_PARA_UP_CH1_V << LEDC_PARA_UP_CH1_S)
+#define LEDC_PARA_UP_CH1_V 0x00000001
+#define LEDC_PARA_UP_CH1_S 4
+
+/* LEDC_OVF_NUM_CH1 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH1_INT interrupt will be triggered when channel 1
+ * overflows for (LEDC_OVF_NUM_CH1 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH1 0x000003FF
+#define LEDC_OVF_NUM_CH1_M (LEDC_OVF_NUM_CH1_V << LEDC_OVF_NUM_CH1_S)
+#define LEDC_OVF_NUM_CH1_V 0x000003FF
+#define LEDC_OVF_NUM_CH1_S 5
+
+/* LEDC_OVF_CNT_EN_CH1 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 1.
+ */
+
+#define LEDC_OVF_CNT_EN_CH1 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH1_M (LEDC_OVF_CNT_EN_CH1_V << LEDC_OVF_CNT_EN_CH1_S)
+#define LEDC_OVF_CNT_EN_CH1_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH1_S 15
+
+/* LEDC_OVF_CNT_RESET_CH1 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 1.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH1 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH1_M (LEDC_OVF_CNT_RESET_CH1_V << LEDC_OVF_CNT_RESET_CH1_S)
+#define LEDC_OVF_CNT_RESET_CH1_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH1_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH1 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH1.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH1 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH1_M (LEDC_OVF_CNT_RESET_ST_CH1_V << LEDC_OVF_CNT_RESET_ST_CH1_S)
+#define LEDC_OVF_CNT_RESET_ST_CH1_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH1_S 17
+
+/* LEDC_CH1_HPOINT_REG register
+ * High point register for channel 1
+ */
+
+#define LEDC_CH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x18)
+
+/* LEDC_HPOINT_CH1 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH1 0x00003FFF
+#define LEDC_HPOINT_CH1_M (LEDC_HPOINT_CH1_V << LEDC_HPOINT_CH1_S)
+#define LEDC_HPOINT_CH1_V 0x00003FFF
+#define LEDC_HPOINT_CH1_S 0
+
+/* LEDC_CH1_DUTY_REG register
+ * Initial duty cycle for channel 1
+ */
+
+#define LEDC_CH1_DUTY_REG (DR_REG_LEDC_BASE + 0x1c)
+
+/* LEDC_DUTY_CH1 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH1 0x0007FFFF
+#define LEDC_DUTY_CH1_M (LEDC_DUTY_CH1_V << LEDC_DUTY_CH1_S)
+#define LEDC_DUTY_CH1_V 0x0007FFFF
+#define LEDC_DUTY_CH1_S 0
+
+/* LEDC_CH1_CONF1_REG register
+ * Configuration register 1 for channel 1
+ */
+
+#define LEDC_CH1_CONF1_REG (DR_REG_LEDC_BASE + 0x20)
+
+/* LEDC_DUTY_SCALE_CH1 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 1.
+ */
+
+#define LEDC_DUTY_SCALE_CH1 0x000003FF
+#define LEDC_DUTY_SCALE_CH1_M (LEDC_DUTY_SCALE_CH1_V << LEDC_DUTY_SCALE_CH1_S)
+#define LEDC_DUTY_SCALE_CH1_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH1_S 0
+
+/* LEDC_DUTY_CYCLE_CH1 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH1 on channel 1.
+ */
+
+#define LEDC_DUTY_CYCLE_CH1 0x000003FF
+#define LEDC_DUTY_CYCLE_CH1_M (LEDC_DUTY_CYCLE_CH1_V << LEDC_DUTY_CYCLE_CH1_S)
+#define LEDC_DUTY_CYCLE_CH1_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH1_S 10
+
+/* LEDC_DUTY_NUM_CH1 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH1 0x000003FF
+#define LEDC_DUTY_NUM_CH1_M (LEDC_DUTY_NUM_CH1_V << LEDC_DUTY_NUM_CH1_S)
+#define LEDC_DUTY_NUM_CH1_V 0x000003FF
+#define LEDC_DUTY_NUM_CH1_S 20
+
+/* LEDC_DUTY_INC_CH1 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 1. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH1 (BIT(30))
+#define LEDC_DUTY_INC_CH1_M (LEDC_DUTY_INC_CH1_V << LEDC_DUTY_INC_CH1_S)
+#define LEDC_DUTY_INC_CH1_V 0x00000001
+#define LEDC_DUTY_INC_CH1_S 30
+
+/* LEDC_DUTY_START_CH1 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH1_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH1 (BIT(31))
+#define LEDC_DUTY_START_CH1_M (LEDC_DUTY_START_CH1_V << LEDC_DUTY_START_CH1_S)
+#define LEDC_DUTY_START_CH1_V 0x00000001
+#define LEDC_DUTY_START_CH1_S 31
+
+/* LEDC_CH1_DUTY_R_REG register
+ * Current duty cycle for channel 1
+ */
+
+#define LEDC_CH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x24)
+
+/* LEDC_DUTY_R_CH1 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 1.
+ */
+
+#define LEDC_DUTY_R_CH1 0x0007FFFF
+#define LEDC_DUTY_R_CH1_M (LEDC_DUTY_R_CH1_V << LEDC_DUTY_R_CH1_S)
+#define LEDC_DUTY_R_CH1_V 0x0007FFFF
+#define LEDC_DUTY_R_CH1_S 0
+
+/* LEDC_CH2_CONF0_REG register
+ * Configuration register 0 for channel 2
+ */
+
+#define LEDC_CH2_CONF0_REG (DR_REG_LEDC_BASE + 0x28)
+
+/* LEDC_TIMER_SEL_CH2 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 2.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH2 0x00000003
+#define LEDC_TIMER_SEL_CH2_M (LEDC_TIMER_SEL_CH2_V << LEDC_TIMER_SEL_CH2_S)
+#define LEDC_TIMER_SEL_CH2_V 0x00000003
+#define LEDC_TIMER_SEL_CH2_S 0
+
+/* LEDC_SIG_OUT_EN_CH2 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 2.
+ */
+
+#define LEDC_SIG_OUT_EN_CH2 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH2_M (LEDC_SIG_OUT_EN_CH2_V << LEDC_SIG_OUT_EN_CH2_S)
+#define LEDC_SIG_OUT_EN_CH2_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH2_S 2
+
+/* LEDC_IDLE_LV_CH2 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 2 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH2 (BIT(3))
+#define LEDC_IDLE_LV_CH2_M (LEDC_IDLE_LV_CH2_V << LEDC_IDLE_LV_CH2_S)
+#define LEDC_IDLE_LV_CH2_V 0x00000001
+#define LEDC_IDLE_LV_CH2_S 3
+
+/* LEDC_PARA_UP_CH2 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH2_HPOINT and LEDC_CH2_DUTY for
+ * channel 2.
+ */
+
+#define LEDC_PARA_UP_CH2 (BIT(4))
+#define LEDC_PARA_UP_CH2_M (LEDC_PARA_UP_CH2_V << LEDC_PARA_UP_CH2_S)
+#define LEDC_PARA_UP_CH2_V 0x00000001
+#define LEDC_PARA_UP_CH2_S 4
+
+/* LEDC_OVF_NUM_CH2 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH2_INT interrupt will be triggered when channel 2
+ * overflows for (LEDC_OVF_NUM_CH2 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH2 0x000003FF
+#define LEDC_OVF_NUM_CH2_M (LEDC_OVF_NUM_CH2_V << LEDC_OVF_NUM_CH2_S)
+#define LEDC_OVF_NUM_CH2_V 0x000003FF
+#define LEDC_OVF_NUM_CH2_S 5
+
+/* LEDC_OVF_CNT_EN_CH2 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 2.
+ */
+
+#define LEDC_OVF_CNT_EN_CH2 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH2_M (LEDC_OVF_CNT_EN_CH2_V << LEDC_OVF_CNT_EN_CH2_S)
+#define LEDC_OVF_CNT_EN_CH2_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH2_S 15
+
+/* LEDC_OVF_CNT_RESET_CH2 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 2.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH2 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH2_M (LEDC_OVF_CNT_RESET_CH2_V << LEDC_OVF_CNT_RESET_CH2_S)
+#define LEDC_OVF_CNT_RESET_CH2_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH2_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH2 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH2.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH2 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH2_M (LEDC_OVF_CNT_RESET_ST_CH2_V << LEDC_OVF_CNT_RESET_ST_CH2_S)
+#define LEDC_OVF_CNT_RESET_ST_CH2_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH2_S 17
+
+/* LEDC_CH2_HPOINT_REG register
+ * High point register for channel 2
+ */
+
+#define LEDC_CH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x2c)
+
+/* LEDC_HPOINT_CH2 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH2 0x00003FFF
+#define LEDC_HPOINT_CH2_M (LEDC_HPOINT_CH2_V << LEDC_HPOINT_CH2_S)
+#define LEDC_HPOINT_CH2_V 0x00003FFF
+#define LEDC_HPOINT_CH2_S 0
+
+/* LEDC_CH2_DUTY_REG register
+ * Initial duty cycle for channel 2
+ */
+
+#define LEDC_CH2_DUTY_REG (DR_REG_LEDC_BASE + 0x30)
+
+/* LEDC_DUTY_CH2 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH2 0x0007FFFF
+#define LEDC_DUTY_CH2_M (LEDC_DUTY_CH2_V << LEDC_DUTY_CH2_S)
+#define LEDC_DUTY_CH2_V 0x0007FFFF
+#define LEDC_DUTY_CH2_S 0
+
+/* LEDC_CH2_CONF1_REG register
+ * Configuration register 1 for channel 2
+ */
+
+#define LEDC_CH2_CONF1_REG (DR_REG_LEDC_BASE + 0x34)
+
+/* LEDC_DUTY_SCALE_CH2 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 2.
+ */
+
+#define LEDC_DUTY_SCALE_CH2 0x000003FF
+#define LEDC_DUTY_SCALE_CH2_M (LEDC_DUTY_SCALE_CH2_V << LEDC_DUTY_SCALE_CH2_S)
+#define LEDC_DUTY_SCALE_CH2_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH2_S 0
+
+/* LEDC_DUTY_CYCLE_CH2 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH2 on channel 2.
+ */
+
+#define LEDC_DUTY_CYCLE_CH2 0x000003FF
+#define LEDC_DUTY_CYCLE_CH2_M (LEDC_DUTY_CYCLE_CH2_V << LEDC_DUTY_CYCLE_CH2_S)
+#define LEDC_DUTY_CYCLE_CH2_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH2_S 10
+
+/* LEDC_DUTY_NUM_CH2 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH2 0x000003FF
+#define LEDC_DUTY_NUM_CH2_M (LEDC_DUTY_NUM_CH2_V << LEDC_DUTY_NUM_CH2_S)
+#define LEDC_DUTY_NUM_CH2_V 0x000003FF
+#define LEDC_DUTY_NUM_CH2_S 20
+
+/* LEDC_DUTY_INC_CH2 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 2. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH2 (BIT(30))
+#define LEDC_DUTY_INC_CH2_M (LEDC_DUTY_INC_CH2_V << LEDC_DUTY_INC_CH2_S)
+#define LEDC_DUTY_INC_CH2_V 0x00000001
+#define LEDC_DUTY_INC_CH2_S 30
+
+/* LEDC_DUTY_START_CH2 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH2_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH2 (BIT(31))
+#define LEDC_DUTY_START_CH2_M (LEDC_DUTY_START_CH2_V << LEDC_DUTY_START_CH2_S)
+#define LEDC_DUTY_START_CH2_V 0x00000001
+#define LEDC_DUTY_START_CH2_S 31
+
+/* LEDC_CH2_DUTY_R_REG register
+ * Current duty cycle for channel 2
+ */
+
+#define LEDC_CH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x38)
+
+/* LEDC_DUTY_R_CH2 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 2.
+ */
+
+#define LEDC_DUTY_R_CH2 0x0007FFFF
+#define LEDC_DUTY_R_CH2_M (LEDC_DUTY_R_CH2_V << LEDC_DUTY_R_CH2_S)
+#define LEDC_DUTY_R_CH2_V 0x0007FFFF
+#define LEDC_DUTY_R_CH2_S 0
+
+/* LEDC_CH3_CONF0_REG register
+ * Configuration register 0 for channel 3
+ */
+
+#define LEDC_CH3_CONF0_REG (DR_REG_LEDC_BASE + 0x3c)
+
+/* LEDC_TIMER_SEL_CH3 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 3.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH3 0x00000003
+#define LEDC_TIMER_SEL_CH3_M (LEDC_TIMER_SEL_CH3_V << LEDC_TIMER_SEL_CH3_S)
+#define LEDC_TIMER_SEL_CH3_V 0x00000003
+#define LEDC_TIMER_SEL_CH3_S 0
+
+/* LEDC_SIG_OUT_EN_CH3 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 3.
+ */
+
+#define LEDC_SIG_OUT_EN_CH3 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH3_M (LEDC_SIG_OUT_EN_CH3_V << LEDC_SIG_OUT_EN_CH3_S)
+#define LEDC_SIG_OUT_EN_CH3_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH3_S 2
+
+/* LEDC_IDLE_LV_CH3 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 3 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH3 (BIT(3))
+#define LEDC_IDLE_LV_CH3_M (LEDC_IDLE_LV_CH3_V << LEDC_IDLE_LV_CH3_S)
+#define LEDC_IDLE_LV_CH3_V 0x00000001
+#define LEDC_IDLE_LV_CH3_S 3
+
+/* LEDC_PARA_UP_CH3 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH3_HPOINT and LEDC_CH3_DUTY for
+ * channel 3.
+ */
+
+#define LEDC_PARA_UP_CH3 (BIT(4))
+#define LEDC_PARA_UP_CH3_M (LEDC_PARA_UP_CH3_V << LEDC_PARA_UP_CH3_S)
+#define LEDC_PARA_UP_CH3_V 0x00000001
+#define LEDC_PARA_UP_CH3_S 4
+
+/* LEDC_OVF_NUM_CH3 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH3_INT interrupt will be triggered when channel 3
+ * overflows for (LEDC_OVF_NUM_CH3 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH3 0x000003FF
+#define LEDC_OVF_NUM_CH3_M (LEDC_OVF_NUM_CH3_V << LEDC_OVF_NUM_CH3_S)
+#define LEDC_OVF_NUM_CH3_V 0x000003FF
+#define LEDC_OVF_NUM_CH3_S 5
+
+/* LEDC_OVF_CNT_EN_CH3 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 3.
+ */
+
+#define LEDC_OVF_CNT_EN_CH3 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH3_M (LEDC_OVF_CNT_EN_CH3_V << LEDC_OVF_CNT_EN_CH3_S)
+#define LEDC_OVF_CNT_EN_CH3_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH3_S 15
+
+/* LEDC_OVF_CNT_RESET_CH3 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 3.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH3 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH3_M (LEDC_OVF_CNT_RESET_CH3_V << LEDC_OVF_CNT_RESET_CH3_S)
+#define LEDC_OVF_CNT_RESET_CH3_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH3_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH3 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH3.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH3 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH3_M (LEDC_OVF_CNT_RESET_ST_CH3_V << LEDC_OVF_CNT_RESET_ST_CH3_S)
+#define LEDC_OVF_CNT_RESET_ST_CH3_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH3_S 17
+
+/* LEDC_CH3_HPOINT_REG register
+ * High point register for channel 3
+ */
+
+#define LEDC_CH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x40)
+
+/* LEDC_HPOINT_CH3 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH3 0x00003FFF
+#define LEDC_HPOINT_CH3_M (LEDC_HPOINT_CH3_V << LEDC_HPOINT_CH3_S)
+#define LEDC_HPOINT_CH3_V 0x00003FFF
+#define LEDC_HPOINT_CH3_S 0
+
+/* LEDC_CH3_DUTY_REG register
+ * Initial duty cycle for channel 3
+ */
+
+#define LEDC_CH3_DUTY_REG (DR_REG_LEDC_BASE + 0x44)
+
+/* LEDC_DUTY_CH3 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH3 0x0007FFFF
+#define LEDC_DUTY_CH3_M (LEDC_DUTY_CH3_V << LEDC_DUTY_CH3_S)
+#define LEDC_DUTY_CH3_V 0x0007FFFF
+#define LEDC_DUTY_CH3_S 0
+
+/* LEDC_CH3_CONF1_REG register
+ * Configuration register 1 for channel 3
+ */
+
+#define LEDC_CH3_CONF1_REG (DR_REG_LEDC_BASE + 0x48)
+
+/* LEDC_DUTY_SCALE_CH3 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 3.
+ */
+
+#define LEDC_DUTY_SCALE_CH3 0x000003FF
+#define LEDC_DUTY_SCALE_CH3_M (LEDC_DUTY_SCALE_CH3_V << LEDC_DUTY_SCALE_CH3_S)
+#define LEDC_DUTY_SCALE_CH3_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH3_S 0
+
+/* LEDC_DUTY_CYCLE_CH3 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH3 on channel 3.
+ */
+
+#define LEDC_DUTY_CYCLE_CH3 0x000003FF
+#define LEDC_DUTY_CYCLE_CH3_M (LEDC_DUTY_CYCLE_CH3_V << LEDC_DUTY_CYCLE_CH3_S)
+#define LEDC_DUTY_CYCLE_CH3_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH3_S 10
+
+/* LEDC_DUTY_NUM_CH3 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH3 0x000003FF
+#define LEDC_DUTY_NUM_CH3_M (LEDC_DUTY_NUM_CH3_V << LEDC_DUTY_NUM_CH3_S)
+#define LEDC_DUTY_NUM_CH3_V 0x000003FF
+#define LEDC_DUTY_NUM_CH3_S 20
+
+/* LEDC_DUTY_INC_CH3 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 3. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH3 (BIT(30))
+#define LEDC_DUTY_INC_CH3_M (LEDC_DUTY_INC_CH3_V << LEDC_DUTY_INC_CH3_S)
+#define LEDC_DUTY_INC_CH3_V 0x00000001
+#define LEDC_DUTY_INC_CH3_S 30
+
+/* LEDC_DUTY_START_CH3 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH3_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH3 (BIT(31))
+#define LEDC_DUTY_START_CH3_M (LEDC_DUTY_START_CH3_V << LEDC_DUTY_START_CH3_S)
+#define LEDC_DUTY_START_CH3_V 0x00000001
+#define LEDC_DUTY_START_CH3_S 31
+
+/* LEDC_CH3_DUTY_R_REG register
+ * Current duty cycle for channel 3
+ */
+
+#define LEDC_CH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x4c)
+
+/* LEDC_DUTY_R_CH3 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 3.
+ */
+
+#define LEDC_DUTY_R_CH3 0x0007FFFF
+#define LEDC_DUTY_R_CH3_M (LEDC_DUTY_R_CH3_V << LEDC_DUTY_R_CH3_S)
+#define LEDC_DUTY_R_CH3_V 0x0007FFFF
+#define LEDC_DUTY_R_CH3_S 0
+
+/* LEDC_CH4_CONF0_REG register
+ * Configuration register 0 for channel 4
+ */
+
+#define LEDC_CH4_CONF0_REG (DR_REG_LEDC_BASE + 0x50)
+
+/* LEDC_TIMER_SEL_CH4 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 4.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH4 0x00000003
+#define LEDC_TIMER_SEL_CH4_M (LEDC_TIMER_SEL_CH4_V << LEDC_TIMER_SEL_CH4_S)
+#define LEDC_TIMER_SEL_CH4_V 0x00000003
+#define LEDC_TIMER_SEL_CH4_S 0
+
+/* LEDC_SIG_OUT_EN_CH4 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 4.
+ */
+
+#define LEDC_SIG_OUT_EN_CH4 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH4_M (LEDC_SIG_OUT_EN_CH4_V << LEDC_SIG_OUT_EN_CH4_S)
+#define LEDC_SIG_OUT_EN_CH4_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH4_S 2
+
+/* LEDC_IDLE_LV_CH4 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 4 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH4 (BIT(3))
+#define LEDC_IDLE_LV_CH4_M (LEDC_IDLE_LV_CH4_V << LEDC_IDLE_LV_CH4_S)
+#define LEDC_IDLE_LV_CH4_V 0x00000001
+#define LEDC_IDLE_LV_CH4_S 3
+
+/* LEDC_PARA_UP_CH4 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH4_HPOINT and LEDC_CH4_DUTY for
+ * channel 4.
+ */
+
+#define LEDC_PARA_UP_CH4 (BIT(4))
+#define LEDC_PARA_UP_CH4_M (LEDC_PARA_UP_CH4_V << LEDC_PARA_UP_CH4_S)
+#define LEDC_PARA_UP_CH4_V 0x00000001
+#define LEDC_PARA_UP_CH4_S 4
+
+/* LEDC_OVF_NUM_CH4 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH4_INT interrupt will be triggered when channel 4
+ * overflows for (LEDC_OVF_NUM_CH4 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH4 0x000003FF
+#define LEDC_OVF_NUM_CH4_M (LEDC_OVF_NUM_CH4_V << LEDC_OVF_NUM_CH4_S)
+#define LEDC_OVF_NUM_CH4_V 0x000003FF
+#define LEDC_OVF_NUM_CH4_S 5
+
+/* LEDC_OVF_CNT_EN_CH4 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 4.
+ */
+
+#define LEDC_OVF_CNT_EN_CH4 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH4_M (LEDC_OVF_CNT_EN_CH4_V << LEDC_OVF_CNT_EN_CH4_S)
+#define LEDC_OVF_CNT_EN_CH4_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH4_S 15
+
+/* LEDC_OVF_CNT_RESET_CH4 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 4.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH4 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH4_M (LEDC_OVF_CNT_RESET_CH4_V << LEDC_OVF_CNT_RESET_CH4_S)
+#define LEDC_OVF_CNT_RESET_CH4_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH4_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH4 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH4.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH4 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH4_M (LEDC_OVF_CNT_RESET_ST_CH4_V << LEDC_OVF_CNT_RESET_ST_CH4_S)
+#define LEDC_OVF_CNT_RESET_ST_CH4_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH4_S 17
+
+/* LEDC_CH4_HPOINT_REG register
+ * High point register for channel 4
+ */
+
+#define LEDC_CH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x54)
+
+/* LEDC_HPOINT_CH4 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH4 0x00003FFF
+#define LEDC_HPOINT_CH4_M (LEDC_HPOINT_CH4_V << LEDC_HPOINT_CH4_S)
+#define LEDC_HPOINT_CH4_V 0x00003FFF
+#define LEDC_HPOINT_CH4_S 0
+
+/* LEDC_CH4_DUTY_REG register
+ * Initial duty cycle for channel 4
+ */
+
+#define LEDC_CH4_DUTY_REG (DR_REG_LEDC_BASE + 0x58)
+
+/* LEDC_DUTY_CH4 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH4 0x0007FFFF
+#define LEDC_DUTY_CH4_M (LEDC_DUTY_CH4_V << LEDC_DUTY_CH4_S)
+#define LEDC_DUTY_CH4_V 0x0007FFFF
+#define LEDC_DUTY_CH4_S 0
+
+/* LEDC_CH4_CONF1_REG register
+ * Configuration register 1 for channel 4
+ */
+
+#define LEDC_CH4_CONF1_REG (DR_REG_LEDC_BASE + 0x5c)
+
+/* LEDC_DUTY_SCALE_CH4 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 4.
+ */
+
+#define LEDC_DUTY_SCALE_CH4 0x000003FF
+#define LEDC_DUTY_SCALE_CH4_M (LEDC_DUTY_SCALE_CH4_V << LEDC_DUTY_SCALE_CH4_S)
+#define LEDC_DUTY_SCALE_CH4_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH4_S 0
+
+/* LEDC_DUTY_CYCLE_CH4 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH4 on channel 4.
+ */
+
+#define LEDC_DUTY_CYCLE_CH4 0x000003FF
+#define LEDC_DUTY_CYCLE_CH4_M (LEDC_DUTY_CYCLE_CH4_V << LEDC_DUTY_CYCLE_CH4_S)
+#define LEDC_DUTY_CYCLE_CH4_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH4_S 10
+
+/* LEDC_DUTY_NUM_CH4 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH4 0x000003FF
+#define LEDC_DUTY_NUM_CH4_M (LEDC_DUTY_NUM_CH4_V << LEDC_DUTY_NUM_CH4_S)
+#define LEDC_DUTY_NUM_CH4_V 0x000003FF
+#define LEDC_DUTY_NUM_CH4_S 20
+
+/* LEDC_DUTY_INC_CH4 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 4. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH4 (BIT(30))
+#define LEDC_DUTY_INC_CH4_M (LEDC_DUTY_INC_CH4_V << LEDC_DUTY_INC_CH4_S)
+#define LEDC_DUTY_INC_CH4_V 0x00000001
+#define LEDC_DUTY_INC_CH4_S 30
+
+/* LEDC_DUTY_START_CH4 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH4_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH4 (BIT(31))
+#define LEDC_DUTY_START_CH4_M (LEDC_DUTY_START_CH4_V << LEDC_DUTY_START_CH4_S)
+#define LEDC_DUTY_START_CH4_V 0x00000001
+#define LEDC_DUTY_START_CH4_S 31
+
+/* LEDC_CH4_DUTY_R_REG register
+ * Current duty cycle for channel 4
+ */
+
+#define LEDC_CH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x60)
+
+/* LEDC_DUTY_R_CH4 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 4.
+ */
+
+#define LEDC_DUTY_R_CH4 0x0007FFFF
+#define LEDC_DUTY_R_CH4_M (LEDC_DUTY_R_CH4_V << LEDC_DUTY_R_CH4_S)
+#define LEDC_DUTY_R_CH4_V 0x0007FFFF
+#define LEDC_DUTY_R_CH4_S 0
+
+/* LEDC_CH5_CONF0_REG register
+ * Configuration register 0 for channel 5
+ */
+
+#define LEDC_CH5_CONF0_REG (DR_REG_LEDC_BASE + 0x64)
+
+/* LEDC_TIMER_SEL_CH5 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 5.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH5 0x00000003
+#define LEDC_TIMER_SEL_CH5_M (LEDC_TIMER_SEL_CH5_V << LEDC_TIMER_SEL_CH5_S)
+#define LEDC_TIMER_SEL_CH5_V 0x00000003
+#define LEDC_TIMER_SEL_CH5_S 0
+
+/* LEDC_SIG_OUT_EN_CH5 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 5.
+ */
+
+#define LEDC_SIG_OUT_EN_CH5 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH5_M (LEDC_SIG_OUT_EN_CH5_V << LEDC_SIG_OUT_EN_CH5_S)
+#define LEDC_SIG_OUT_EN_CH5_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH5_S 2
+
+/* LEDC_IDLE_LV_CH5 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 5 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH5 (BIT(3))
+#define LEDC_IDLE_LV_CH5_M (LEDC_IDLE_LV_CH5_V << LEDC_IDLE_LV_CH5_S)
+#define LEDC_IDLE_LV_CH5_V 0x00000001
+#define LEDC_IDLE_LV_CH5_S 3
+
+/* LEDC_PARA_UP_CH5 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH5_HPOINT and LEDC_CH5_DUTY for
+ * channel 5.
+ */
+
+#define LEDC_PARA_UP_CH5 (BIT(4))
+#define LEDC_PARA_UP_CH5_M (LEDC_PARA_UP_CH5_V << LEDC_PARA_UP_CH5_S)
+#define LEDC_PARA_UP_CH5_V 0x00000001
+#define LEDC_PARA_UP_CH5_S 4
+
+/* LEDC_OVF_NUM_CH5 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH5_INT interrupt will be triggered when channel 5
+ * overflows for (LEDC_OVF_NUM_CH5 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH5 0x000003FF
+#define LEDC_OVF_NUM_CH5_M (LEDC_OVF_NUM_CH5_V << LEDC_OVF_NUM_CH5_S)
+#define LEDC_OVF_NUM_CH5_V 0x000003FF
+#define LEDC_OVF_NUM_CH5_S 5
+
+/* LEDC_OVF_CNT_EN_CH5 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 5.
+ */
+
+#define LEDC_OVF_CNT_EN_CH5 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH5_M (LEDC_OVF_CNT_EN_CH5_V << LEDC_OVF_CNT_EN_CH5_S)
+#define LEDC_OVF_CNT_EN_CH5_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH5_S 15
+
+/* LEDC_OVF_CNT_RESET_CH5 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 5.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH5 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH5_M (LEDC_OVF_CNT_RESET_CH5_V << LEDC_OVF_CNT_RESET_CH5_S)
+#define LEDC_OVF_CNT_RESET_CH5_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH5_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH5 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH5.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH5 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH5_M (LEDC_OVF_CNT_RESET_ST_CH5_V << LEDC_OVF_CNT_RESET_ST_CH5_S)
+#define LEDC_OVF_CNT_RESET_ST_CH5_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH5_S 17
+
+/* LEDC_CH5_HPOINT_REG register
+ * High point register for channel 5
+ */
+
+#define LEDC_CH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x68)
+
+/* LEDC_HPOINT_CH5 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH5 0x00003FFF
+#define LEDC_HPOINT_CH5_M (LEDC_HPOINT_CH5_V << LEDC_HPOINT_CH5_S)
+#define LEDC_HPOINT_CH5_V 0x00003FFF
+#define LEDC_HPOINT_CH5_S 0
+
+/* LEDC_CH5_DUTY_REG register
+ * Initial duty cycle for channel 5
+ */
+
+#define LEDC_CH5_DUTY_REG (DR_REG_LEDC_BASE + 0x6c)
+
+/* LEDC_DUTY_CH5 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH5 0x0007FFFF
+#define LEDC_DUTY_CH5_M (LEDC_DUTY_CH5_V << LEDC_DUTY_CH5_S)
+#define LEDC_DUTY_CH5_V 0x0007FFFF
+#define LEDC_DUTY_CH5_S 0
+
+/* LEDC_CH5_CONF1_REG register
+ * Configuration register 1 for channel 5
+ */
+
+#define LEDC_CH5_CONF1_REG (DR_REG_LEDC_BASE + 0x70)
+
+/* LEDC_DUTY_SCALE_CH5 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 5.
+ */
+
+#define LEDC_DUTY_SCALE_CH5 0x000003FF
+#define LEDC_DUTY_SCALE_CH5_M (LEDC_DUTY_SCALE_CH5_V << LEDC_DUTY_SCALE_CH5_S)
+#define LEDC_DUTY_SCALE_CH5_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH5_S 0
+
+/* LEDC_DUTY_CYCLE_CH5 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH5 on channel 5.
+ */
+
+#define LEDC_DUTY_CYCLE_CH5 0x000003FF
+#define LEDC_DUTY_CYCLE_CH5_M (LEDC_DUTY_CYCLE_CH5_V << LEDC_DUTY_CYCLE_CH5_S)
+#define LEDC_DUTY_CYCLE_CH5_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH5_S 10
+
+/* LEDC_DUTY_NUM_CH5 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH5 0x000003FF
+#define LEDC_DUTY_NUM_CH5_M (LEDC_DUTY_NUM_CH5_V << LEDC_DUTY_NUM_CH5_S)
+#define LEDC_DUTY_NUM_CH5_V 0x000003FF
+#define LEDC_DUTY_NUM_CH5_S 20
+
+/* LEDC_DUTY_INC_CH5 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 5. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH5 (BIT(30))
+#define LEDC_DUTY_INC_CH5_M (LEDC_DUTY_INC_CH5_V << LEDC_DUTY_INC_CH5_S)
+#define LEDC_DUTY_INC_CH5_V 0x00000001
+#define LEDC_DUTY_INC_CH5_S 30
+
+/* LEDC_DUTY_START_CH5 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH5_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH5 (BIT(31))
+#define LEDC_DUTY_START_CH5_M (LEDC_DUTY_START_CH5_V << LEDC_DUTY_START_CH5_S)
+#define LEDC_DUTY_START_CH5_V 0x00000001
+#define LEDC_DUTY_START_CH5_S 31
+
+/* LEDC_CH5_DUTY_R_REG register
+ * Current duty cycle for channel 5
+ */
+
+#define LEDC_CH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x74)
+
+/* LEDC_DUTY_R_CH5 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 5.
+ */
+
+#define LEDC_DUTY_R_CH5 0x0007FFFF
+#define LEDC_DUTY_R_CH5_M (LEDC_DUTY_R_CH5_V << LEDC_DUTY_R_CH5_S)
+#define LEDC_DUTY_R_CH5_V 0x0007FFFF
+#define LEDC_DUTY_R_CH5_S 0
+
+/* LEDC_CH6_CONF0_REG register
+ * Configuration register 0 for channel 6
+ */
+
+#define LEDC_CH6_CONF0_REG (DR_REG_LEDC_BASE + 0x78)
+
+/* LEDC_TIMER_SEL_CH6 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 6.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH6 0x00000003
+#define LEDC_TIMER_SEL_CH6_M (LEDC_TIMER_SEL_CH6_V << LEDC_TIMER_SEL_CH6_S)
+#define LEDC_TIMER_SEL_CH6_V 0x00000003
+#define LEDC_TIMER_SEL_CH6_S 0
+
+/* LEDC_SIG_OUT_EN_CH6 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 6.
+ */
+
+#define LEDC_SIG_OUT_EN_CH6 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH6_M (LEDC_SIG_OUT_EN_CH6_V << LEDC_SIG_OUT_EN_CH6_S)
+#define LEDC_SIG_OUT_EN_CH6_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH6_S 2
+
+/* LEDC_IDLE_LV_CH6 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 6 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH6 (BIT(3))
+#define LEDC_IDLE_LV_CH6_M (LEDC_IDLE_LV_CH6_V << LEDC_IDLE_LV_CH6_S)
+#define LEDC_IDLE_LV_CH6_V 0x00000001
+#define LEDC_IDLE_LV_CH6_S 3
+
+/* LEDC_PARA_UP_CH6 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH6_HPOINT and LEDC_CH6_DUTY for
+ * channel 6.
+ */
+
+#define LEDC_PARA_UP_CH6 (BIT(4))
+#define LEDC_PARA_UP_CH6_M (LEDC_PARA_UP_CH6_V << LEDC_PARA_UP_CH6_S)
+#define LEDC_PARA_UP_CH6_V 0x00000001
+#define LEDC_PARA_UP_CH6_S 4
+
+/* LEDC_OVF_NUM_CH6 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH6_INT interrupt will be triggered when channel 6
+ * overflows for (LEDC_OVF_NUM_CH6 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH6 0x000003FF
+#define LEDC_OVF_NUM_CH6_M (LEDC_OVF_NUM_CH6_V << LEDC_OVF_NUM_CH6_S)
+#define LEDC_OVF_NUM_CH6_V 0x000003FF
+#define LEDC_OVF_NUM_CH6_S 5
+
+/* LEDC_OVF_CNT_EN_CH6 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 6.
+ */
+
+#define LEDC_OVF_CNT_EN_CH6 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH6_M (LEDC_OVF_CNT_EN_CH6_V << LEDC_OVF_CNT_EN_CH6_S)
+#define LEDC_OVF_CNT_EN_CH6_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH6_S 15
+
+/* LEDC_OVF_CNT_RESET_CH6 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 6.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH6 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH6_M (LEDC_OVF_CNT_RESET_CH6_V << LEDC_OVF_CNT_RESET_CH6_S)
+#define LEDC_OVF_CNT_RESET_CH6_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH6_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH6 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH6.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH6 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH6_M (LEDC_OVF_CNT_RESET_ST_CH6_V << LEDC_OVF_CNT_RESET_ST_CH6_S)
+#define LEDC_OVF_CNT_RESET_ST_CH6_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH6_S 17
+
+/* LEDC_CH6_HPOINT_REG register
+ * High point register for channel 6
+ */
+
+#define LEDC_CH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x7c)
+
+/* LEDC_HPOINT_CH6 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH6 0x00003FFF
+#define LEDC_HPOINT_CH6_M (LEDC_HPOINT_CH6_V << LEDC_HPOINT_CH6_S)
+#define LEDC_HPOINT_CH6_V 0x00003FFF
+#define LEDC_HPOINT_CH6_S 0
+
+/* LEDC_CH6_DUTY_REG register
+ * Initial duty cycle for channel 6
+ */
+
+#define LEDC_CH6_DUTY_REG (DR_REG_LEDC_BASE + 0x80)
+
+/* LEDC_DUTY_CH6 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH6 0x0007FFFF
+#define LEDC_DUTY_CH6_M (LEDC_DUTY_CH6_V << LEDC_DUTY_CH6_S)
+#define LEDC_DUTY_CH6_V 0x0007FFFF
+#define LEDC_DUTY_CH6_S 0
+
+/* LEDC_CH6_CONF1_REG register
+ * Configuration register 1 for channel 6
+ */
+
+#define LEDC_CH6_CONF1_REG (DR_REG_LEDC_BASE + 0x84)
+
+/* LEDC_DUTY_SCALE_CH6 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 6.
+ */
+
+#define LEDC_DUTY_SCALE_CH6 0x000003FF
+#define LEDC_DUTY_SCALE_CH6_M (LEDC_DUTY_SCALE_CH6_V << LEDC_DUTY_SCALE_CH6_S)
+#define LEDC_DUTY_SCALE_CH6_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH6_S 0
+
+/* LEDC_DUTY_CYCLE_CH6 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH6 on channel 6.
+ */
+
+#define LEDC_DUTY_CYCLE_CH6 0x000003FF
+#define LEDC_DUTY_CYCLE_CH6_M (LEDC_DUTY_CYCLE_CH6_V << LEDC_DUTY_CYCLE_CH6_S)
+#define LEDC_DUTY_CYCLE_CH6_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH6_S 10
+
+/* LEDC_DUTY_NUM_CH6 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH6 0x000003FF
+#define LEDC_DUTY_NUM_CH6_M (LEDC_DUTY_NUM_CH6_V << LEDC_DUTY_NUM_CH6_S)
+#define LEDC_DUTY_NUM_CH6_V 0x000003FF
+#define LEDC_DUTY_NUM_CH6_S 20
+
+/* LEDC_DUTY_INC_CH6 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 6. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH6 (BIT(30))
+#define LEDC_DUTY_INC_CH6_M (LEDC_DUTY_INC_CH6_V << LEDC_DUTY_INC_CH6_S)
+#define LEDC_DUTY_INC_CH6_V 0x00000001
+#define LEDC_DUTY_INC_CH6_S 30
+
+/* LEDC_DUTY_START_CH6 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH6_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH6 (BIT(31))
+#define LEDC_DUTY_START_CH6_M (LEDC_DUTY_START_CH6_V << LEDC_DUTY_START_CH6_S)
+#define LEDC_DUTY_START_CH6_V 0x00000001
+#define LEDC_DUTY_START_CH6_S 31
+
+/* LEDC_CH6_DUTY_R_REG register
+ * Current duty cycle for channel 6
+ */
+
+#define LEDC_CH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x88)
+
+/* LEDC_DUTY_R_CH6 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 6.
+ */
+
+#define LEDC_DUTY_R_CH6 0x0007FFFF
+#define LEDC_DUTY_R_CH6_M (LEDC_DUTY_R_CH6_V << LEDC_DUTY_R_CH6_S)
+#define LEDC_DUTY_R_CH6_V 0x0007FFFF
+#define LEDC_DUTY_R_CH6_S 0
+
+/* LEDC_CH7_CONF0_REG register
+ * Configuration register 0 for channel 7
+ */
+
+#define LEDC_CH7_CONF0_REG (DR_REG_LEDC_BASE + 0x8c)
+
+/* LEDC_TIMER_SEL_CH7 : R/W; bitpos: [1:0]; default: 0;
+ * This field is used to select one of timers for channel 7.
+ *
+ * 0: select timer0
+ *
+ * 1: select timer1
+ *
+ * 2: select timer2
+ *
+ * 3: select timer3
+ */
+
+#define LEDC_TIMER_SEL_CH7 0x00000003
+#define LEDC_TIMER_SEL_CH7_M (LEDC_TIMER_SEL_CH7_V << LEDC_TIMER_SEL_CH7_S)
+#define LEDC_TIMER_SEL_CH7_V 0x00000003
+#define LEDC_TIMER_SEL_CH7_S 0
+
+/* LEDC_SIG_OUT_EN_CH7 : R/W; bitpos: [2]; default: 0;
+ * Set this bit to enable signal output on channel 7.
+ */
+
+#define LEDC_SIG_OUT_EN_CH7 (BIT(2))
+#define LEDC_SIG_OUT_EN_CH7_M (LEDC_SIG_OUT_EN_CH7_V << LEDC_SIG_OUT_EN_CH7_S)
+#define LEDC_SIG_OUT_EN_CH7_V 0x00000001
+#define LEDC_SIG_OUT_EN_CH7_S 2
+
+/* LEDC_IDLE_LV_CH7 : R/W; bitpos: [3]; default: 0;
+ * This bit is used to control the output value when channel 7 is inactive.
+ */
+
+#define LEDC_IDLE_LV_CH7 (BIT(3))
+#define LEDC_IDLE_LV_CH7_M (LEDC_IDLE_LV_CH7_V << LEDC_IDLE_LV_CH7_S)
+#define LEDC_IDLE_LV_CH7_V 0x00000001
+#define LEDC_IDLE_LV_CH7_S 3
+
+/* LEDC_PARA_UP_CH7 : WO; bitpos: [4]; default: 0;
+ * This bit is used to update register LEDC_CH7_HPOINT and LEDC_CH7_DUTY for
+ * channel 7.
+ */
+
+#define LEDC_PARA_UP_CH7 (BIT(4))
+#define LEDC_PARA_UP_CH7_M (LEDC_PARA_UP_CH7_V << LEDC_PARA_UP_CH7_S)
+#define LEDC_PARA_UP_CH7_V 0x00000001
+#define LEDC_PARA_UP_CH7_S 4
+
+/* LEDC_OVF_NUM_CH7 : R/W; bitpos: [14:5]; default: 0;
+ * This register is used to configure the maximum times of overflow minus 1.
+ *
+ * The LEDC_OVF_CNT_CH7_INT interrupt will be triggered when channel 7
+ * overflows for (LEDC_OVF_NUM_CH7 + 1) times.
+ */
+
+#define LEDC_OVF_NUM_CH7 0x000003FF
+#define LEDC_OVF_NUM_CH7_M (LEDC_OVF_NUM_CH7_V << LEDC_OVF_NUM_CH7_S)
+#define LEDC_OVF_NUM_CH7_V 0x000003FF
+#define LEDC_OVF_NUM_CH7_S 5
+
+/* LEDC_OVF_CNT_EN_CH7 : R/W; bitpos: [15]; default: 0;
+ * This bit is used to enable the ovf_cnt of channel 7.
+ */
+
+#define LEDC_OVF_CNT_EN_CH7 (BIT(15))
+#define LEDC_OVF_CNT_EN_CH7_M (LEDC_OVF_CNT_EN_CH7_V << LEDC_OVF_CNT_EN_CH7_S)
+#define LEDC_OVF_CNT_EN_CH7_V 0x00000001
+#define LEDC_OVF_CNT_EN_CH7_S 15
+
+/* LEDC_OVF_CNT_RESET_CH7 : WO; bitpos: [16]; default: 0;
+ * Set this bit to reset the ovf_cnt of channel 7.
+ */
+
+#define LEDC_OVF_CNT_RESET_CH7 (BIT(16))
+#define LEDC_OVF_CNT_RESET_CH7_M (LEDC_OVF_CNT_RESET_CH7_V << LEDC_OVF_CNT_RESET_CH7_S)
+#define LEDC_OVF_CNT_RESET_CH7_V 0x00000001
+#define LEDC_OVF_CNT_RESET_CH7_S 16
+
+/* LEDC_OVF_CNT_RESET_ST_CH7 : RO; bitpos: [17]; default: 0;
+ * This is the status bit of LEDC_OVF_CNT_RESET_CH7.
+ */
+
+#define LEDC_OVF_CNT_RESET_ST_CH7 (BIT(17))
+#define LEDC_OVF_CNT_RESET_ST_CH7_M (LEDC_OVF_CNT_RESET_ST_CH7_V << LEDC_OVF_CNT_RESET_ST_CH7_S)
+#define LEDC_OVF_CNT_RESET_ST_CH7_V 0x00000001
+#define LEDC_OVF_CNT_RESET_ST_CH7_S 17
+
+/* LEDC_CH7_HPOINT_REG register
+ * High point register for channel 7
+ */
+
+#define LEDC_CH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x90)
+
+/* LEDC_HPOINT_CH7 : R/W; bitpos: [13:0]; default: 0;
+ * The output value changes to high when the selected timers has reached the
+ * value specified by this register.
+ */
+
+#define LEDC_HPOINT_CH7 0x00003FFF
+#define LEDC_HPOINT_CH7_M (LEDC_HPOINT_CH7_V << LEDC_HPOINT_CH7_S)
+#define LEDC_HPOINT_CH7_V 0x00003FFF
+#define LEDC_HPOINT_CH7_S 0
+
+/* LEDC_CH7_DUTY_REG register
+ * Initial duty cycle for channel 7
+ */
+
+#define LEDC_CH7_DUTY_REG (DR_REG_LEDC_BASE + 0x94)
+
+/* LEDC_DUTY_CH7 : R/W; bitpos: [18:0]; default: 0;
+ * This register is used to change the output duty by controlling the Lpoint.
+ *
+ * The output value turns to low when the selected timers has reached the
+ * Lpoint.
+ */
+
+#define LEDC_DUTY_CH7 0x0007FFFF
+#define LEDC_DUTY_CH7_M (LEDC_DUTY_CH7_V << LEDC_DUTY_CH7_S)
+#define LEDC_DUTY_CH7_V 0x0007FFFF
+#define LEDC_DUTY_CH7_S 0
+
+/* LEDC_CH7_CONF1_REG register
+ * Configuration register 1 for channel 7
+ */
+
+#define LEDC_CH7_CONF1_REG (DR_REG_LEDC_BASE + 0x98)
+
+/* LEDC_DUTY_SCALE_CH7 : R/W; bitpos: [9:0]; default: 0;
+ * This register is used to configure the changing step scale of duty on
+ * channel 7.
+ */
+
+#define LEDC_DUTY_SCALE_CH7 0x000003FF
+#define LEDC_DUTY_SCALE_CH7_M (LEDC_DUTY_SCALE_CH7_V << LEDC_DUTY_SCALE_CH7_S)
+#define LEDC_DUTY_SCALE_CH7_V 0x000003FF
+#define LEDC_DUTY_SCALE_CH7_S 0
+
+/* LEDC_DUTY_CYCLE_CH7 : R/W; bitpos: [19:10]; default: 0;
+ * The duty will change every LEDC_DUTY_CYCLE_CH7 on channel 7.
+ */
+
+#define LEDC_DUTY_CYCLE_CH7 0x000003FF
+#define LEDC_DUTY_CYCLE_CH7_M (LEDC_DUTY_CYCLE_CH7_V << LEDC_DUTY_CYCLE_CH7_S)
+#define LEDC_DUTY_CYCLE_CH7_V 0x000003FF
+#define LEDC_DUTY_CYCLE_CH7_S 10
+
+/* LEDC_DUTY_NUM_CH7 : R/W; bitpos: [29:20]; default: 0;
+ * This register is used to control the number of times the duty cycle will
+ * be changed.
+ */
+
+#define LEDC_DUTY_NUM_CH7 0x000003FF
+#define LEDC_DUTY_NUM_CH7_M (LEDC_DUTY_NUM_CH7_V << LEDC_DUTY_NUM_CH7_S)
+#define LEDC_DUTY_NUM_CH7_V 0x000003FF
+#define LEDC_DUTY_NUM_CH7_S 20
+
+/* LEDC_DUTY_INC_CH7 : R/W; bitpos: [30]; default: 1;
+ * This register is used to increase or decrease the duty of output signal
+ * on channel 7. 1: Increase;0: Decrease.
+ */
+
+#define LEDC_DUTY_INC_CH7 (BIT(30))
+#define LEDC_DUTY_INC_CH7_M (LEDC_DUTY_INC_CH7_V << LEDC_DUTY_INC_CH7_S)
+#define LEDC_DUTY_INC_CH7_V 0x00000001
+#define LEDC_DUTY_INC_CH7_S 30
+
+/* LEDC_DUTY_START_CH7 : R/W; bitpos: [31]; default: 0;
+ * Other configured fields in LEDC_CH7_CONF1_REG will start to take effect
+ * when this bit is set to 1.
+ */
+
+#define LEDC_DUTY_START_CH7 (BIT(31))
+#define LEDC_DUTY_START_CH7_M (LEDC_DUTY_START_CH7_V << LEDC_DUTY_START_CH7_S)
+#define LEDC_DUTY_START_CH7_V 0x00000001
+#define LEDC_DUTY_START_CH7_S 31
+
+/* LEDC_CH7_DUTY_R_REG register
+ * Current duty cycle for channel 7
+ */
+
+#define LEDC_CH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x9c)
+
+/* LEDC_DUTY_R_CH7 : RO; bitpos: [18:0]; default: 0;
+ * This register stores the current duty of output signal on channel 7.
+ */
+
+#define LEDC_DUTY_R_CH7 0x0007FFFF
+#define LEDC_DUTY_R_CH7_M (LEDC_DUTY_R_CH7_V << LEDC_DUTY_R_CH7_S)
+#define LEDC_DUTY_R_CH7_V 0x0007FFFF
+#define LEDC_DUTY_R_CH7_S 0
+
+/* LEDC_TIMER0_CONF_REG register
+ * Timer 0 configuration
+ */
+
+#define LEDC_TIMER0_CONF_REG (DR_REG_LEDC_BASE + 0xa0)
+
+/* LEDC_TIMER0_DUTY_RES : R/W; bitpos: [3:0]; default: 0;
+ * This register is used to control the range of the counter in timer 0.
+ */
+
+#define LEDC_TIMER0_DUTY_RES 0x0000000F
+#define LEDC_TIMER0_DUTY_RES_M (LEDC_TIMER0_DUTY_RES_V << LEDC_TIMER0_DUTY_RES_S)
+#define LEDC_TIMER0_DUTY_RES_V 0x0000000F
+#define LEDC_TIMER0_DUTY_RES_S 0
+
+/* LEDC_CLK_DIV_TIMER0 : R/W; bitpos: [21:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer 0.
+ *
+ * The least significant eight bits represent the fractional part.
+ */
+
+#define LEDC_CLK_DIV_TIMER0 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER0_M (LEDC_CLK_DIV_TIMER0_V << LEDC_CLK_DIV_TIMER0_S)
+#define LEDC_CLK_DIV_TIMER0_V 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER0_S 4
+
+/* LEDC_TIMER0_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer 0.
+ */
+
+#define LEDC_TIMER0_PAUSE (BIT(22))
+#define LEDC_TIMER0_PAUSE_M (LEDC_TIMER0_PAUSE_V << LEDC_TIMER0_PAUSE_S)
+#define LEDC_TIMER0_PAUSE_V 0x00000001
+#define LEDC_TIMER0_PAUSE_S 22
+
+/* LEDC_TIMER0_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 0. The counter will show 0 after reset.
+ */
+
+#define LEDC_TIMER0_RST (BIT(23))
+#define LEDC_TIMER0_RST_M (LEDC_TIMER0_RST_V << LEDC_TIMER0_RST_S)
+#define LEDC_TIMER0_RST_V 0x00000001
+#define LEDC_TIMER0_RST_S 23
+
+/* LEDC_TICK_SEL_TIMER0 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 0. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ *
+ * 1'h0: SLOW_CLK 1'h1: REF_TICK
+ */
+
+#define LEDC_TICK_SEL_TIMER0 (BIT(24))
+#define LEDC_TICK_SEL_TIMER0_M (LEDC_TICK_SEL_TIMER0_V << LEDC_TICK_SEL_TIMER0_S)
+#define LEDC_TICK_SEL_TIMER0_V 0x00000001
+#define LEDC_TICK_SEL_TIMER0_S 24
+
+/* LEDC_TIMER0_PARA_UP : WO; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER0 and LEDC_TIMER0_DUTY_RES.
+ */
+
+#define LEDC_TIMER0_PARA_UP (BIT(25))
+#define LEDC_TIMER0_PARA_UP_M (LEDC_TIMER0_PARA_UP_V << LEDC_TIMER0_PARA_UP_S)
+#define LEDC_TIMER0_PARA_UP_V 0x00000001
+#define LEDC_TIMER0_PARA_UP_S 25
+
+/* LEDC_TIMER0_VALUE_REG register
+ * Timer 0 current counter value
+ */
+
+#define LEDC_TIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0xa4)
+
+/* LEDC_TIMER0_CNT : RO; bitpos: [13:0]; default: 0;
+ * This register stores the current counter value of timer 0.
+ */
+
+#define LEDC_TIMER0_CNT 0x00003FFF
+#define LEDC_TIMER0_CNT_M (LEDC_TIMER0_CNT_V << LEDC_TIMER0_CNT_S)
+#define LEDC_TIMER0_CNT_V 0x00003FFF
+#define LEDC_TIMER0_CNT_S 0
+
+/* LEDC_TIMER1_CONF_REG register
+ * Timer 1 configuration
+ */
+
+#define LEDC_TIMER1_CONF_REG (DR_REG_LEDC_BASE + 0xa8)
+
+/* LEDC_TIMER1_DUTY_RES : R/W; bitpos: [3:0]; default: 0;
+ * This register is used to control the range of the counter in timer 1.
+ */
+
+#define LEDC_TIMER1_DUTY_RES 0x0000000F
+#define LEDC_TIMER1_DUTY_RES_M (LEDC_TIMER1_DUTY_RES_V << LEDC_TIMER1_DUTY_RES_S)
+#define LEDC_TIMER1_DUTY_RES_V 0x0000000F
+#define LEDC_TIMER1_DUTY_RES_S 0
+
+/* LEDC_CLK_DIV_TIMER1 : R/W; bitpos: [21:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer 1.
+ *
+ * The least significant eight bits represent the fractional part.
+ */
+
+#define LEDC_CLK_DIV_TIMER1 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER1_M (LEDC_CLK_DIV_TIMER1_V << LEDC_CLK_DIV_TIMER1_S)
+#define LEDC_CLK_DIV_TIMER1_V 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER1_S 4
+
+/* LEDC_TIMER1_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer 1.
+ */
+
+#define LEDC_TIMER1_PAUSE (BIT(22))
+#define LEDC_TIMER1_PAUSE_M (LEDC_TIMER1_PAUSE_V << LEDC_TIMER1_PAUSE_S)
+#define LEDC_TIMER1_PAUSE_V 0x00000001
+#define LEDC_TIMER1_PAUSE_S 22
+
+/* LEDC_TIMER1_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 1. The counter will show 0 after reset.
+ */
+
+#define LEDC_TIMER1_RST (BIT(23))
+#define LEDC_TIMER1_RST_M (LEDC_TIMER1_RST_V << LEDC_TIMER1_RST_S)
+#define LEDC_TIMER1_RST_V 0x00000001
+#define LEDC_TIMER1_RST_S 23
+
+/* LEDC_TICK_SEL_TIMER1 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 1. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ *
+ * 1'h0: SLOW_CLK 1'h1: REF_TICK
+ */
+
+#define LEDC_TICK_SEL_TIMER1 (BIT(24))
+#define LEDC_TICK_SEL_TIMER1_M (LEDC_TICK_SEL_TIMER1_V << LEDC_TICK_SEL_TIMER1_S)
+#define LEDC_TICK_SEL_TIMER1_V 0x00000001
+#define LEDC_TICK_SEL_TIMER1_S 24
+
+/* LEDC_TIMER1_PARA_UP : WO; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER1 and LEDC_TIMER1_DUTY_RES.
+ */
+
+#define LEDC_TIMER1_PARA_UP (BIT(25))
+#define LEDC_TIMER1_PARA_UP_M (LEDC_TIMER1_PARA_UP_V << LEDC_TIMER1_PARA_UP_S)
+#define LEDC_TIMER1_PARA_UP_V 0x00000001
+#define LEDC_TIMER1_PARA_UP_S 25
+
+/* LEDC_TIMER1_VALUE_REG register
+ * Timer 1 current counter value
+ */
+
+#define LEDC_TIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0xac)
+
+/* LEDC_TIMER1_CNT : RO; bitpos: [13:0]; default: 0;
+ * This register stores the current counter value of timer 1.
+ */
+
+#define LEDC_TIMER1_CNT 0x00003FFF
+#define LEDC_TIMER1_CNT_M (LEDC_TIMER1_CNT_V << LEDC_TIMER1_CNT_S)
+#define LEDC_TIMER1_CNT_V 0x00003FFF
+#define LEDC_TIMER1_CNT_S 0
+
+/* LEDC_TIMER2_CONF_REG register
+ * Timer 2 configuration
+ */
+
+#define LEDC_TIMER2_CONF_REG (DR_REG_LEDC_BASE + 0xb0)
+
+/* LEDC_TIMER2_DUTY_RES : R/W; bitpos: [3:0]; default: 0;
+ * This register is used to control the range of the counter in timer 2.
+ */
+
+#define LEDC_TIMER2_DUTY_RES 0x0000000F
+#define LEDC_TIMER2_DUTY_RES_M (LEDC_TIMER2_DUTY_RES_V << LEDC_TIMER2_DUTY_RES_S)
+#define LEDC_TIMER2_DUTY_RES_V 0x0000000F
+#define LEDC_TIMER2_DUTY_RES_S 0
+
+/* LEDC_CLK_DIV_TIMER2 : R/W; bitpos: [21:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer 2.
+ *
+ * The least significant eight bits represent the fractional part.
+ */
+
+#define LEDC_CLK_DIV_TIMER2 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER2_M (LEDC_CLK_DIV_TIMER2_V << LEDC_CLK_DIV_TIMER2_S)
+#define LEDC_CLK_DIV_TIMER2_V 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER2_S 4
+
+/* LEDC_TIMER2_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer 2.
+ */
+
+#define LEDC_TIMER2_PAUSE (BIT(22))
+#define LEDC_TIMER2_PAUSE_M (LEDC_TIMER2_PAUSE_V << LEDC_TIMER2_PAUSE_S)
+#define LEDC_TIMER2_PAUSE_V 0x00000001
+#define LEDC_TIMER2_PAUSE_S 22
+
+/* LEDC_TIMER2_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 2. The counter will show 0 after reset.
+ */
+
+#define LEDC_TIMER2_RST (BIT(23))
+#define LEDC_TIMER2_RST_M (LEDC_TIMER2_RST_V << LEDC_TIMER2_RST_S)
+#define LEDC_TIMER2_RST_V 0x00000001
+#define LEDC_TIMER2_RST_S 23
+
+/* LEDC_TICK_SEL_TIMER2 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 2. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ *
+ * 1'h0: SLOW_CLK 1'h1: REF_TICK
+ */
+
+#define LEDC_TICK_SEL_TIMER2 (BIT(24))
+#define LEDC_TICK_SEL_TIMER2_M (LEDC_TICK_SEL_TIMER2_V << LEDC_TICK_SEL_TIMER2_S)
+#define LEDC_TICK_SEL_TIMER2_V 0x00000001
+#define LEDC_TICK_SEL_TIMER2_S 24
+
+/* LEDC_TIMER2_PARA_UP : WO; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER2 and LEDC_TIMER2_DUTY_RES.
+ */
+
+#define LEDC_TIMER2_PARA_UP (BIT(25))
+#define LEDC_TIMER2_PARA_UP_M (LEDC_TIMER2_PARA_UP_V << LEDC_TIMER2_PARA_UP_S)
+#define LEDC_TIMER2_PARA_UP_V 0x00000001
+#define LEDC_TIMER2_PARA_UP_S 25
+
+/* LEDC_TIMER2_VALUE_REG register
+ * Timer 2 current counter value
+ */
+
+#define LEDC_TIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0xb4)
+
+/* LEDC_TIMER2_CNT : RO; bitpos: [13:0]; default: 0;
+ * This register stores the current counter value of timer 2.
+ */
+
+#define LEDC_TIMER2_CNT 0x00003FFF
+#define LEDC_TIMER2_CNT_M (LEDC_TIMER2_CNT_V << LEDC_TIMER2_CNT_S)
+#define LEDC_TIMER2_CNT_V 0x00003FFF
+#define LEDC_TIMER2_CNT_S 0
+
+/* LEDC_TIMER3_CONF_REG register
+ * Timer 3 configuration
+ */
+
+#define LEDC_TIMER3_CONF_REG (DR_REG_LEDC_BASE + 0xb8)
+
+/* LEDC_TIMER3_DUTY_RES : R/W; bitpos: [3:0]; default: 0;
+ * This register is used to control the range of the counter in timer 3.
+ */
+
+#define LEDC_TIMER3_DUTY_RES 0x0000000F
+#define LEDC_TIMER3_DUTY_RES_M (LEDC_TIMER3_DUTY_RES_V << LEDC_TIMER3_DUTY_RES_S)
+#define LEDC_TIMER3_DUTY_RES_V 0x0000000F
+#define LEDC_TIMER3_DUTY_RES_S 0
+
+/* LEDC_CLK_DIV_TIMER3 : R/W; bitpos: [21:4]; default: 0;
+ * This register is used to configure the divisor for the divider in timer 3.
+ *
+ * The least significant eight bits represent the fractional part.
+ */
+
+#define LEDC_CLK_DIV_TIMER3 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER3_M (LEDC_CLK_DIV_TIMER3_V << LEDC_CLK_DIV_TIMER3_S)
+#define LEDC_CLK_DIV_TIMER3_V 0x0003FFFF
+#define LEDC_CLK_DIV_TIMER3_S 4
+
+/* LEDC_TIMER3_PAUSE : R/W; bitpos: [22]; default: 0;
+ * This bit is used to suspend the counter in timer 3.
+ */
+
+#define LEDC_TIMER3_PAUSE (BIT(22))
+#define LEDC_TIMER3_PAUSE_M (LEDC_TIMER3_PAUSE_V << LEDC_TIMER3_PAUSE_S)
+#define LEDC_TIMER3_PAUSE_V 0x00000001
+#define LEDC_TIMER3_PAUSE_S 22
+
+/* LEDC_TIMER3_RST : R/W; bitpos: [23]; default: 1;
+ * This bit is used to reset timer 3. The counter will show 0 after reset.
+ */
+
+#define LEDC_TIMER3_RST (BIT(23))
+#define LEDC_TIMER3_RST_M (LEDC_TIMER3_RST_V << LEDC_TIMER3_RST_S)
+#define LEDC_TIMER3_RST_V 0x00000001
+#define LEDC_TIMER3_RST_S 23
+
+/* LEDC_TICK_SEL_TIMER3 : R/W; bitpos: [24]; default: 0;
+ * This bit is used to select clock for timer 3. When this bit is set to 1
+ * LEDC_APB_CLK_SEL[1:0] should be 1, otherwise the timer clock may be not
+ * accurate.
+ *
+ * 1'h0: SLOW_CLK 1'h1: REF_TICK
+ */
+
+#define LEDC_TICK_SEL_TIMER3 (BIT(24))
+#define LEDC_TICK_SEL_TIMER3_M (LEDC_TICK_SEL_TIMER3_V << LEDC_TICK_SEL_TIMER3_S)
+#define LEDC_TICK_SEL_TIMER3_V 0x00000001
+#define LEDC_TICK_SEL_TIMER3_S 24
+
+/* LEDC_TIMER3_PARA_UP : WO; bitpos: [25]; default: 0;
+ * Set this bit to update LEDC_CLK_DIV_TIMER3 and LEDC_TIMER3_DUTY_RES.
+ */
+
+#define LEDC_TIMER3_PARA_UP (BIT(25))
+#define LEDC_TIMER3_PARA_UP_M (LEDC_TIMER3_PARA_UP_V << LEDC_TIMER3_PARA_UP_S)
+#define LEDC_TIMER3_PARA_UP_V 0x00000001
+#define LEDC_TIMER3_PARA_UP_S 25
+
+/* LEDC_TIMER3_VALUE_REG register
+ * Timer 3 current counter value
+ */
+
+#define LEDC_TIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0xbc)
+
+/* LEDC_TIMER3_CNT : RO; bitpos: [13:0]; default: 0;
+ * This register stores the current counter value of timer 3.
+ */
+
+#define LEDC_TIMER3_CNT 0x00003FFF
+#define LEDC_TIMER3_CNT_M (LEDC_TIMER3_CNT_V << LEDC_TIMER3_CNT_S)
+#define LEDC_TIMER3_CNT_V 0x00003FFF
+#define LEDC_TIMER3_CNT_S 0
+
+/* LEDC_INT_RAW_REG register
+ * Raw interrupt status
+ */
+
+#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0xc0)
+
+/* LEDC_TIMER0_OVF_INT_RAW : RO; bitpos: [0]; default: 0;
+ * Triggered when the timer0 has reached its maximum counter value.
+ */
+
+#define LEDC_TIMER0_OVF_INT_RAW (BIT(0))
+#define LEDC_TIMER0_OVF_INT_RAW_M (LEDC_TIMER0_OVF_INT_RAW_V << LEDC_TIMER0_OVF_INT_RAW_S)
+#define LEDC_TIMER0_OVF_INT_RAW_V 0x00000001
+#define LEDC_TIMER0_OVF_INT_RAW_S 0
+
+/* LEDC_TIMER1_OVF_INT_RAW : RO; bitpos: [1]; default: 0;
+ * Triggered when the timer1 has reached its maximum counter value.
+ */
+
+#define LEDC_TIMER1_OVF_INT_RAW (BIT(1))
+#define LEDC_TIMER1_OVF_INT_RAW_M (LEDC_TIMER1_OVF_INT_RAW_V << LEDC_TIMER1_OVF_INT_RAW_S)
+#define LEDC_TIMER1_OVF_INT_RAW_V 0x00000001
+#define LEDC_TIMER1_OVF_INT_RAW_S 1
+
+/* LEDC_TIMER2_OVF_INT_RAW : RO; bitpos: [2]; default: 0;
+ * Triggered when the timer2 has reached its maximum counter value.
+ */
+
+#define LEDC_TIMER2_OVF_INT_RAW (BIT(2))
+#define LEDC_TIMER2_OVF_INT_RAW_M (LEDC_TIMER2_OVF_INT_RAW_V << LEDC_TIMER2_OVF_INT_RAW_S)
+#define LEDC_TIMER2_OVF_INT_RAW_V 0x00000001
+#define LEDC_TIMER2_OVF_INT_RAW_S 2
+
+/* LEDC_TIMER3_OVF_INT_RAW : RO; bitpos: [3]; default: 0;
+ * Triggered when the timer3 has reached its maximum counter value.
+ */
+
+#define LEDC_TIMER3_OVF_INT_RAW (BIT(3))
+#define LEDC_TIMER3_OVF_INT_RAW_M (LEDC_TIMER3_OVF_INT_RAW_V << LEDC_TIMER3_OVF_INT_RAW_S)
+#define LEDC_TIMER3_OVF_INT_RAW_V 0x00000001
+#define LEDC_TIMER3_OVF_INT_RAW_S 3
+
+/* LEDC_DUTY_CHNG_END_CH0_INT_RAW : RO; bitpos: [4]; default: 0;
+ * Interrupt raw bit for channel 0. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_M (LEDC_DUTY_CHNG_END_CH0_INT_RAW_V << LEDC_DUTY_CHNG_END_CH0_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_RAW_S 4
+
+/* LEDC_DUTY_CHNG_END_CH1_INT_RAW : RO; bitpos: [5]; default: 0;
+ * Interrupt raw bit for channel 1. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_M (LEDC_DUTY_CHNG_END_CH1_INT_RAW_V << LEDC_DUTY_CHNG_END_CH1_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_RAW_S 5
+
+/* LEDC_DUTY_CHNG_END_CH2_INT_RAW : RO; bitpos: [6]; default: 0;
+ * Interrupt raw bit for channel 2. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_M (LEDC_DUTY_CHNG_END_CH2_INT_RAW_V << LEDC_DUTY_CHNG_END_CH2_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_RAW_S 6
+
+/* LEDC_DUTY_CHNG_END_CH3_INT_RAW : RO; bitpos: [7]; default: 0;
+ * Interrupt raw bit for channel 3. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_M (LEDC_DUTY_CHNG_END_CH3_INT_RAW_V << LEDC_DUTY_CHNG_END_CH3_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_RAW_S 7
+
+/* LEDC_DUTY_CHNG_END_CH4_INT_RAW : RO; bitpos: [8]; default: 0;
+ * Interrupt raw bit for channel 4. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_M (LEDC_DUTY_CHNG_END_CH4_INT_RAW_V << LEDC_DUTY_CHNG_END_CH4_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_RAW_S 8
+
+/* LEDC_DUTY_CHNG_END_CH5_INT_RAW : RO; bitpos: [9]; default: 0;
+ * Interrupt raw bit for channel 5. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_M (LEDC_DUTY_CHNG_END_CH5_INT_RAW_V << LEDC_DUTY_CHNG_END_CH5_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_RAW_S 9
+
+/* LEDC_DUTY_CHNG_END_CH6_INT_RAW : RO; bitpos: [10]; default: 0;
+ * Interrupt raw bit for channel 6. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_M (LEDC_DUTY_CHNG_END_CH6_INT_RAW_V << LEDC_DUTY_CHNG_END_CH6_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH6_INT_RAW_S 10
+
+/* LEDC_DUTY_CHNG_END_CH7_INT_RAW : RO; bitpos: [11]; default: 0;
+ * Interrupt raw bit for channel 7. Triggered when the gradual change of
+ * duty has finished.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_M (LEDC_DUTY_CHNG_END_CH7_INT_RAW_V << LEDC_DUTY_CHNG_END_CH7_INT_RAW_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH7_INT_RAW_S 11
+
+/* LEDC_OVF_CNT_CH0_INT_RAW : RO; bitpos: [12]; default: 0;
+ * Interrupt raw bit for channel 0. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH0.
+ */
+
+#define LEDC_OVF_CNT_CH0_INT_RAW (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_RAW_M (LEDC_OVF_CNT_CH0_INT_RAW_V << LEDC_OVF_CNT_CH0_INT_RAW_S)
+#define LEDC_OVF_CNT_CH0_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH0_INT_RAW_S 12
+
+/* LEDC_OVF_CNT_CH1_INT_RAW : RO; bitpos: [13]; default: 0;
+ * Interrupt raw bit for channel 1. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH1.
+ */
+
+#define LEDC_OVF_CNT_CH1_INT_RAW (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_RAW_M (LEDC_OVF_CNT_CH1_INT_RAW_V << LEDC_OVF_CNT_CH1_INT_RAW_S)
+#define LEDC_OVF_CNT_CH1_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH1_INT_RAW_S 13
+
+/* LEDC_OVF_CNT_CH2_INT_RAW : RO; bitpos: [14]; default: 0;
+ * Interrupt raw bit for channel 2. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH2.
+ */
+
+#define LEDC_OVF_CNT_CH2_INT_RAW (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_RAW_M (LEDC_OVF_CNT_CH2_INT_RAW_V << LEDC_OVF_CNT_CH2_INT_RAW_S)
+#define LEDC_OVF_CNT_CH2_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH2_INT_RAW_S 14
+
+/* LEDC_OVF_CNT_CH3_INT_RAW : RO; bitpos: [15]; default: 0;
+ * Interrupt raw bit for channel 3. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH3.
+ */
+
+#define LEDC_OVF_CNT_CH3_INT_RAW (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_RAW_M (LEDC_OVF_CNT_CH3_INT_RAW_V << LEDC_OVF_CNT_CH3_INT_RAW_S)
+#define LEDC_OVF_CNT_CH3_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH3_INT_RAW_S 15
+
+/* LEDC_OVF_CNT_CH4_INT_RAW : RO; bitpos: [16]; default: 0;
+ * Interrupt raw bit for channel 4. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH4.
+ */
+
+#define LEDC_OVF_CNT_CH4_INT_RAW (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_RAW_M (LEDC_OVF_CNT_CH4_INT_RAW_V << LEDC_OVF_CNT_CH4_INT_RAW_S)
+#define LEDC_OVF_CNT_CH4_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH4_INT_RAW_S 16
+
+/* LEDC_OVF_CNT_CH5_INT_RAW : RO; bitpos: [17]; default: 0;
+ * Interrupt raw bit for channel 5. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH5.
+ */
+
+#define LEDC_OVF_CNT_CH5_INT_RAW (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_RAW_M (LEDC_OVF_CNT_CH5_INT_RAW_V << LEDC_OVF_CNT_CH5_INT_RAW_S)
+#define LEDC_OVF_CNT_CH5_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH5_INT_RAW_S 17
+
+/* LEDC_OVF_CNT_CH6_INT_RAW : RO; bitpos: [18]; default: 0;
+ * Interrupt raw bit for channel 6. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH6.
+ */
+
+#define LEDC_OVF_CNT_CH6_INT_RAW (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_RAW_M (LEDC_OVF_CNT_CH6_INT_RAW_V << LEDC_OVF_CNT_CH6_INT_RAW_S)
+#define LEDC_OVF_CNT_CH6_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH6_INT_RAW_S 18
+
+/* LEDC_OVF_CNT_CH7_INT_RAW : RO; bitpos: [19]; default: 0;
+ * Interrupt raw bit for channel 7. Triggered when the ovf_cnt has reached
+ * the value specified by LEDC_OVF_NUM_CH7.
+ */
+
+#define LEDC_OVF_CNT_CH7_INT_RAW (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_RAW_M (LEDC_OVF_CNT_CH7_INT_RAW_V << LEDC_OVF_CNT_CH7_INT_RAW_S)
+#define LEDC_OVF_CNT_CH7_INT_RAW_V 0x00000001
+#define LEDC_OVF_CNT_CH7_INT_RAW_S 19
+
+/* LEDC_INT_ST_REG register
+ * Masked interrupt status
+ */
+
+#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0xc4)
+
+/* LEDC_TIMER0_OVF_INT_ST : RO; bitpos: [0]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER0_OVF_INT
+ * interrupt when LEDC_TIMER0_OVF_INT_ENA is set to 1.
+ */
+
+#define LEDC_TIMER0_OVF_INT_ST (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ST_M (LEDC_TIMER0_OVF_INT_ST_V << LEDC_TIMER0_OVF_INT_ST_S)
+#define LEDC_TIMER0_OVF_INT_ST_V 0x00000001
+#define LEDC_TIMER0_OVF_INT_ST_S 0
+
+/* LEDC_TIMER1_OVF_INT_ST : RO; bitpos: [1]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER1_OVF_INT
+ * interrupt when LEDC_TIMER1_OVF_INT_ENA is set to 1.
+ */
+
+#define LEDC_TIMER1_OVF_INT_ST (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ST_M (LEDC_TIMER1_OVF_INT_ST_V << LEDC_TIMER1_OVF_INT_ST_S)
+#define LEDC_TIMER1_OVF_INT_ST_V 0x00000001
+#define LEDC_TIMER1_OVF_INT_ST_S 1
+
+/* LEDC_TIMER2_OVF_INT_ST : RO; bitpos: [2]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER2_OVF_INT
+ * interrupt when LEDC_TIMER2_OVF_INT_ENA is set to 1.
+ */
+
+#define LEDC_TIMER2_OVF_INT_ST (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ST_M (LEDC_TIMER2_OVF_INT_ST_V << LEDC_TIMER2_OVF_INT_ST_S)
+#define LEDC_TIMER2_OVF_INT_ST_V 0x00000001
+#define LEDC_TIMER2_OVF_INT_ST_S 2
+
+/* LEDC_TIMER3_OVF_INT_ST : RO; bitpos: [3]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_TIMER3_OVF_INT
+ * interrupt when LEDC_TIMER3_OVF_INT_ENA is set to 1.
+ */
+
+#define LEDC_TIMER3_OVF_INT_ST (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ST_M (LEDC_TIMER3_OVF_INT_ST_V << LEDC_TIMER3_OVF_INT_ST_S)
+#define LEDC_TIMER3_OVF_INT_ST_V 0x00000001
+#define LEDC_TIMER3_OVF_INT_ST_S 3
+
+/* LEDC_DUTY_CHNG_END_CH0_INT_ST : RO; bitpos: [4]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH0_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH0_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_M (LEDC_DUTY_CHNG_END_CH0_INT_ST_V << LEDC_DUTY_CHNG_END_CH0_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_ST_S 4
+
+/* LEDC_DUTY_CHNG_END_CH1_INT_ST : RO; bitpos: [5]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH1_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH1_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_M (LEDC_DUTY_CHNG_END_CH1_INT_ST_V << LEDC_DUTY_CHNG_END_CH1_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_ST_S 5
+
+/* LEDC_DUTY_CHNG_END_CH2_INT_ST : RO; bitpos: [6]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH2_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH2_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_M (LEDC_DUTY_CHNG_END_CH2_INT_ST_V << LEDC_DUTY_CHNG_END_CH2_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_ST_S 6
+
+/* LEDC_DUTY_CHNG_END_CH3_INT_ST : RO; bitpos: [7]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH3_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH3_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_M (LEDC_DUTY_CHNG_END_CH3_INT_ST_V << LEDC_DUTY_CHNG_END_CH3_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_ST_S 7
+
+/* LEDC_DUTY_CHNG_END_CH4_INT_ST : RO; bitpos: [8]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH4_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH4_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_M (LEDC_DUTY_CHNG_END_CH4_INT_ST_V << LEDC_DUTY_CHNG_END_CH4_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_ST_S 8
+
+/* LEDC_DUTY_CHNG_END_CH5_INT_ST : RO; bitpos: [9]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH5_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH5_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_M (LEDC_DUTY_CHNG_END_CH5_INT_ST_V << LEDC_DUTY_CHNG_END_CH5_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_ST_S 9
+
+/* LEDC_DUTY_CHNG_END_CH6_INT_ST : RO; bitpos: [10]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH6_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH6_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_M (LEDC_DUTY_CHNG_END_CH6_INT_ST_V << LEDC_DUTY_CHNG_END_CH6_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH6_INT_ST_S 10
+
+/* LEDC_DUTY_CHNG_END_CH7_INT_ST : RO; bitpos: [11]; default: 0;
+ * This is the masked interrupt status bit for the
+ * LEDC_DUTY_CHNG_END_CH7_INT interrupt when
+ * LEDC_DUTY_CHNG_END_CH7_INT_ENAIS set to 1.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_M (LEDC_DUTY_CHNG_END_CH7_INT_ST_V << LEDC_DUTY_CHNG_END_CH7_INT_ST_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH7_INT_ST_S 11
+
+/* LEDC_OVF_CNT_CH0_INT_ST : RO; bitpos: [12]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH0_INT
+ * interrupt when LEDC_OVF_CNT_CH0_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH0_INT_ST (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_ST_M (LEDC_OVF_CNT_CH0_INT_ST_V << LEDC_OVF_CNT_CH0_INT_ST_S)
+#define LEDC_OVF_CNT_CH0_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH0_INT_ST_S 12
+
+/* LEDC_OVF_CNT_CH1_INT_ST : RO; bitpos: [13]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH1_INT
+ * interrupt when LEDC_OVF_CNT_CH1_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH1_INT_ST (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_ST_M (LEDC_OVF_CNT_CH1_INT_ST_V << LEDC_OVF_CNT_CH1_INT_ST_S)
+#define LEDC_OVF_CNT_CH1_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH1_INT_ST_S 13
+
+/* LEDC_OVF_CNT_CH2_INT_ST : RO; bitpos: [14]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH2_INT
+ * interrupt when LEDC_OVF_CNT_CH2_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH2_INT_ST (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_ST_M (LEDC_OVF_CNT_CH2_INT_ST_V << LEDC_OVF_CNT_CH2_INT_ST_S)
+#define LEDC_OVF_CNT_CH2_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH2_INT_ST_S 14
+
+/* LEDC_OVF_CNT_CH3_INT_ST : RO; bitpos: [15]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH3_INT
+ * interrupt when LEDC_OVF_CNT_CH3_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH3_INT_ST (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_ST_M (LEDC_OVF_CNT_CH3_INT_ST_V << LEDC_OVF_CNT_CH3_INT_ST_S)
+#define LEDC_OVF_CNT_CH3_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH3_INT_ST_S 15
+
+/* LEDC_OVF_CNT_CH4_INT_ST : RO; bitpos: [16]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH4_INT
+ * interrupt when LEDC_OVF_CNT_CH4_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH4_INT_ST (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_ST_M (LEDC_OVF_CNT_CH4_INT_ST_V << LEDC_OVF_CNT_CH4_INT_ST_S)
+#define LEDC_OVF_CNT_CH4_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH4_INT_ST_S 16
+
+/* LEDC_OVF_CNT_CH5_INT_ST : RO; bitpos: [17]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH5_INT
+ * interrupt when LEDC_OVF_CNT_CH5_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH5_INT_ST (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_ST_M (LEDC_OVF_CNT_CH5_INT_ST_V << LEDC_OVF_CNT_CH5_INT_ST_S)
+#define LEDC_OVF_CNT_CH5_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH5_INT_ST_S 17
+
+/* LEDC_OVF_CNT_CH6_INT_ST : RO; bitpos: [18]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH6_INT
+ * interrupt when LEDC_OVF_CNT_CH6_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH6_INT_ST (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_ST_M (LEDC_OVF_CNT_CH6_INT_ST_V << LEDC_OVF_CNT_CH6_INT_ST_S)
+#define LEDC_OVF_CNT_CH6_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH6_INT_ST_S 18
+
+/* LEDC_OVF_CNT_CH7_INT_ST : RO; bitpos: [19]; default: 0;
+ * This is the masked interrupt status bit for the LEDC_OVF_CNT_CH7_INT
+ * interrupt when LEDC_OVF_CNT_CH7_INT_ENA is set to 1.
+ */
+
+#define LEDC_OVF_CNT_CH7_INT_ST (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_ST_M (LEDC_OVF_CNT_CH7_INT_ST_V << LEDC_OVF_CNT_CH7_INT_ST_S)
+#define LEDC_OVF_CNT_CH7_INT_ST_V 0x00000001
+#define LEDC_OVF_CNT_CH7_INT_ST_S 19
+
+/* LEDC_INT_ENA_REG register
+ * Interrupt enable bits
+ */
+
+#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0xc8)
+
+/* LEDC_TIMER0_OVF_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER0_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER0_OVF_INT_ENA (BIT(0))
+#define LEDC_TIMER0_OVF_INT_ENA_M (LEDC_TIMER0_OVF_INT_ENA_V << LEDC_TIMER0_OVF_INT_ENA_S)
+#define LEDC_TIMER0_OVF_INT_ENA_V 0x00000001
+#define LEDC_TIMER0_OVF_INT_ENA_S 0
+
+/* LEDC_TIMER1_OVF_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER1_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER1_OVF_INT_ENA (BIT(1))
+#define LEDC_TIMER1_OVF_INT_ENA_M (LEDC_TIMER1_OVF_INT_ENA_V << LEDC_TIMER1_OVF_INT_ENA_S)
+#define LEDC_TIMER1_OVF_INT_ENA_V 0x00000001
+#define LEDC_TIMER1_OVF_INT_ENA_S 1
+
+/* LEDC_TIMER2_OVF_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER2_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER2_OVF_INT_ENA (BIT(2))
+#define LEDC_TIMER2_OVF_INT_ENA_M (LEDC_TIMER2_OVF_INT_ENA_V << LEDC_TIMER2_OVF_INT_ENA_S)
+#define LEDC_TIMER2_OVF_INT_ENA_V 0x00000001
+#define LEDC_TIMER2_OVF_INT_ENA_S 2
+
+/* LEDC_TIMER3_OVF_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The interrupt enable bit for the LEDC_TIMER3_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER3_OVF_INT_ENA (BIT(3))
+#define LEDC_TIMER3_OVF_INT_ENA_M (LEDC_TIMER3_OVF_INT_ENA_V << LEDC_TIMER3_OVF_INT_ENA_S)
+#define LEDC_TIMER3_OVF_INT_ENA_V 0x00000001
+#define LEDC_TIMER3_OVF_INT_ENA_S 3
+
+/* LEDC_DUTY_CHNG_END_CH0_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH0_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_M (LEDC_DUTY_CHNG_END_CH0_INT_ENA_V << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_ENA_S 4
+
+/* LEDC_DUTY_CHNG_END_CH1_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH1_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_M (LEDC_DUTY_CHNG_END_CH1_INT_ENA_V << LEDC_DUTY_CHNG_END_CH1_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_ENA_S 5
+
+/* LEDC_DUTY_CHNG_END_CH2_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH2_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_M (LEDC_DUTY_CHNG_END_CH2_INT_ENA_V << LEDC_DUTY_CHNG_END_CH2_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_ENA_S 6
+
+/* LEDC_DUTY_CHNG_END_CH3_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH3_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_M (LEDC_DUTY_CHNG_END_CH3_INT_ENA_V << LEDC_DUTY_CHNG_END_CH3_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_ENA_S 7
+
+/* LEDC_DUTY_CHNG_END_CH4_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH4_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_M (LEDC_DUTY_CHNG_END_CH4_INT_ENA_V << LEDC_DUTY_CHNG_END_CH4_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_ENA_S 8
+
+/* LEDC_DUTY_CHNG_END_CH5_INT_ENA : R/W; bitpos: [9]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH5_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_M (LEDC_DUTY_CHNG_END_CH5_INT_ENA_V << LEDC_DUTY_CHNG_END_CH5_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_ENA_S 9
+
+/* LEDC_DUTY_CHNG_END_CH6_INT_ENA : R/W; bitpos: [10]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH6_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_M (LEDC_DUTY_CHNG_END_CH6_INT_ENA_V << LEDC_DUTY_CHNG_END_CH6_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH6_INT_ENA_S 10
+
+/* LEDC_DUTY_CHNG_END_CH7_INT_ENA : R/W; bitpos: [11]; default: 0;
+ * The interrupt enable bit for the LEDC_DUTY_CHNG_END_CH7_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_M (LEDC_DUTY_CHNG_END_CH7_INT_ENA_V << LEDC_DUTY_CHNG_END_CH7_INT_ENA_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH7_INT_ENA_S 11
+
+/* LEDC_OVF_CNT_CH0_INT_ENA : R/W; bitpos: [12]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH0_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH0_INT_ENA (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_ENA_M (LEDC_OVF_CNT_CH0_INT_ENA_V << LEDC_OVF_CNT_CH0_INT_ENA_S)
+#define LEDC_OVF_CNT_CH0_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH0_INT_ENA_S 12
+
+/* LEDC_OVF_CNT_CH1_INT_ENA : R/W; bitpos: [13]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH1_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH1_INT_ENA (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_ENA_M (LEDC_OVF_CNT_CH1_INT_ENA_V << LEDC_OVF_CNT_CH1_INT_ENA_S)
+#define LEDC_OVF_CNT_CH1_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH1_INT_ENA_S 13
+
+/* LEDC_OVF_CNT_CH2_INT_ENA : R/W; bitpos: [14]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH2_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH2_INT_ENA (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_ENA_M (LEDC_OVF_CNT_CH2_INT_ENA_V << LEDC_OVF_CNT_CH2_INT_ENA_S)
+#define LEDC_OVF_CNT_CH2_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH2_INT_ENA_S 14
+
+/* LEDC_OVF_CNT_CH3_INT_ENA : R/W; bitpos: [15]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH3_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH3_INT_ENA (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_ENA_M (LEDC_OVF_CNT_CH3_INT_ENA_V << LEDC_OVF_CNT_CH3_INT_ENA_S)
+#define LEDC_OVF_CNT_CH3_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH3_INT_ENA_S 15
+
+/* LEDC_OVF_CNT_CH4_INT_ENA : R/W; bitpos: [16]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH4_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH4_INT_ENA (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_ENA_M (LEDC_OVF_CNT_CH4_INT_ENA_V << LEDC_OVF_CNT_CH4_INT_ENA_S)
+#define LEDC_OVF_CNT_CH4_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH4_INT_ENA_S 16
+
+/* LEDC_OVF_CNT_CH5_INT_ENA : R/W; bitpos: [17]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH5_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH5_INT_ENA (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_ENA_M (LEDC_OVF_CNT_CH5_INT_ENA_V << LEDC_OVF_CNT_CH5_INT_ENA_S)
+#define LEDC_OVF_CNT_CH5_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH5_INT_ENA_S 17
+
+/* LEDC_OVF_CNT_CH6_INT_ENA : R/W; bitpos: [18]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH6_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH6_INT_ENA (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_ENA_M (LEDC_OVF_CNT_CH6_INT_ENA_V << LEDC_OVF_CNT_CH6_INT_ENA_S)
+#define LEDC_OVF_CNT_CH6_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH6_INT_ENA_S 18
+
+/* LEDC_OVF_CNT_CH7_INT_ENA : R/W; bitpos: [19]; default: 0;
+ * The interrupt enable bit for the LEDC_OVF_CNT_CH7_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH7_INT_ENA (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_ENA_M (LEDC_OVF_CNT_CH7_INT_ENA_V << LEDC_OVF_CNT_CH7_INT_ENA_S)
+#define LEDC_OVF_CNT_CH7_INT_ENA_V 0x00000001
+#define LEDC_OVF_CNT_CH7_INT_ENA_S 19
+
+/* LEDC_INT_CLR_REG register
+ * Interrupt clear bits
+ */
+
+#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0xcc)
+
+/* LEDC_TIMER0_OVF_INT_CLR : WO; bitpos: [0]; default: 0;
+ * Set this bit to clear the LEDC_TIMER0_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER0_OVF_INT_CLR (BIT(0))
+#define LEDC_TIMER0_OVF_INT_CLR_M (LEDC_TIMER0_OVF_INT_CLR_V << LEDC_TIMER0_OVF_INT_CLR_S)
+#define LEDC_TIMER0_OVF_INT_CLR_V 0x00000001
+#define LEDC_TIMER0_OVF_INT_CLR_S 0
+
+/* LEDC_TIMER1_OVF_INT_CLR : WO; bitpos: [1]; default: 0;
+ * Set this bit to clear the LEDC_TIMER1_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER1_OVF_INT_CLR (BIT(1))
+#define LEDC_TIMER1_OVF_INT_CLR_M (LEDC_TIMER1_OVF_INT_CLR_V << LEDC_TIMER1_OVF_INT_CLR_S)
+#define LEDC_TIMER1_OVF_INT_CLR_V 0x00000001
+#define LEDC_TIMER1_OVF_INT_CLR_S 1
+
+/* LEDC_TIMER2_OVF_INT_CLR : WO; bitpos: [2]; default: 0;
+ * Set this bit to clear the LEDC_TIMER2_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER2_OVF_INT_CLR (BIT(2))
+#define LEDC_TIMER2_OVF_INT_CLR_M (LEDC_TIMER2_OVF_INT_CLR_V << LEDC_TIMER2_OVF_INT_CLR_S)
+#define LEDC_TIMER2_OVF_INT_CLR_V 0x00000001
+#define LEDC_TIMER2_OVF_INT_CLR_S 2
+
+/* LEDC_TIMER3_OVF_INT_CLR : WO; bitpos: [3]; default: 0;
+ * Set this bit to clear the LEDC_TIMER3_OVF_INT interrupt.
+ */
+
+#define LEDC_TIMER3_OVF_INT_CLR (BIT(3))
+#define LEDC_TIMER3_OVF_INT_CLR_M (LEDC_TIMER3_OVF_INT_CLR_V << LEDC_TIMER3_OVF_INT_CLR_S)
+#define LEDC_TIMER3_OVF_INT_CLR_V 0x00000001
+#define LEDC_TIMER3_OVF_INT_CLR_S 3
+
+/* LEDC_DUTY_CHNG_END_CH0_INT_CLR : WO; bitpos: [4]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH0_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR (BIT(4))
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_M (LEDC_DUTY_CHNG_END_CH0_INT_CLR_V << LEDC_DUTY_CHNG_END_CH0_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH0_INT_CLR_S 4
+
+/* LEDC_DUTY_CHNG_END_CH1_INT_CLR : WO; bitpos: [5]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH1_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR (BIT(5))
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_M (LEDC_DUTY_CHNG_END_CH1_INT_CLR_V << LEDC_DUTY_CHNG_END_CH1_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH1_INT_CLR_S 5
+
+/* LEDC_DUTY_CHNG_END_CH2_INT_CLR : WO; bitpos: [6]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH2_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR (BIT(6))
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_M (LEDC_DUTY_CHNG_END_CH2_INT_CLR_V << LEDC_DUTY_CHNG_END_CH2_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH2_INT_CLR_S 6
+
+/* LEDC_DUTY_CHNG_END_CH3_INT_CLR : WO; bitpos: [7]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH3_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR (BIT(7))
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_M (LEDC_DUTY_CHNG_END_CH3_INT_CLR_V << LEDC_DUTY_CHNG_END_CH3_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH3_INT_CLR_S 7
+
+/* LEDC_DUTY_CHNG_END_CH4_INT_CLR : WO; bitpos: [8]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH4_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR (BIT(8))
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_M (LEDC_DUTY_CHNG_END_CH4_INT_CLR_V << LEDC_DUTY_CHNG_END_CH4_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH4_INT_CLR_S 8
+
+/* LEDC_DUTY_CHNG_END_CH5_INT_CLR : WO; bitpos: [9]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH5_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR (BIT(9))
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_M (LEDC_DUTY_CHNG_END_CH5_INT_CLR_V << LEDC_DUTY_CHNG_END_CH5_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH5_INT_CLR_S 9
+
+/* LEDC_DUTY_CHNG_END_CH6_INT_CLR : WO; bitpos: [10]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH6_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR (BIT(10))
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_M (LEDC_DUTY_CHNG_END_CH6_INT_CLR_V << LEDC_DUTY_CHNG_END_CH6_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH6_INT_CLR_S 10
+
+/* LEDC_DUTY_CHNG_END_CH7_INT_CLR : WO; bitpos: [11]; default: 0;
+ * Set this bit to clear the LEDC_DUTY_CHNG_END_CH7_INT interrupt.
+ */
+
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR (BIT(11))
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_M (LEDC_DUTY_CHNG_END_CH7_INT_CLR_V << LEDC_DUTY_CHNG_END_CH7_INT_CLR_S)
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_V 0x00000001
+#define LEDC_DUTY_CHNG_END_CH7_INT_CLR_S 11
+
+/* LEDC_OVF_CNT_CH0_INT_CLR : WO; bitpos: [12]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH0_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH0_INT_CLR (BIT(12))
+#define LEDC_OVF_CNT_CH0_INT_CLR_M (LEDC_OVF_CNT_CH0_INT_CLR_V << LEDC_OVF_CNT_CH0_INT_CLR_S)
+#define LEDC_OVF_CNT_CH0_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH0_INT_CLR_S 12
+
+/* LEDC_OVF_CNT_CH1_INT_CLR : WO; bitpos: [13]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH1_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH1_INT_CLR (BIT(13))
+#define LEDC_OVF_CNT_CH1_INT_CLR_M (LEDC_OVF_CNT_CH1_INT_CLR_V << LEDC_OVF_CNT_CH1_INT_CLR_S)
+#define LEDC_OVF_CNT_CH1_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH1_INT_CLR_S 13
+
+/* LEDC_OVF_CNT_CH2_INT_CLR : WO; bitpos: [14]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH2_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH2_INT_CLR (BIT(14))
+#define LEDC_OVF_CNT_CH2_INT_CLR_M (LEDC_OVF_CNT_CH2_INT_CLR_V << LEDC_OVF_CNT_CH2_INT_CLR_S)
+#define LEDC_OVF_CNT_CH2_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH2_INT_CLR_S 14
+
+/* LEDC_OVF_CNT_CH3_INT_CLR : WO; bitpos: [15]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH3_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH3_INT_CLR (BIT(15))
+#define LEDC_OVF_CNT_CH3_INT_CLR_M (LEDC_OVF_CNT_CH3_INT_CLR_V << LEDC_OVF_CNT_CH3_INT_CLR_S)
+#define LEDC_OVF_CNT_CH3_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH3_INT_CLR_S 15
+
+/* LEDC_OVF_CNT_CH4_INT_CLR : WO; bitpos: [16]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH4_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH4_INT_CLR (BIT(16))
+#define LEDC_OVF_CNT_CH4_INT_CLR_M (LEDC_OVF_CNT_CH4_INT_CLR_V << LEDC_OVF_CNT_CH4_INT_CLR_S)
+#define LEDC_OVF_CNT_CH4_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH4_INT_CLR_S 16
+
+/* LEDC_OVF_CNT_CH5_INT_CLR : WO; bitpos: [17]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH5_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH5_INT_CLR (BIT(17))
+#define LEDC_OVF_CNT_CH5_INT_CLR_M (LEDC_OVF_CNT_CH5_INT_CLR_V << LEDC_OVF_CNT_CH5_INT_CLR_S)
+#define LEDC_OVF_CNT_CH5_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH5_INT_CLR_S 17
+
+/* LEDC_OVF_CNT_CH6_INT_CLR : WO; bitpos: [18]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH6_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH6_INT_CLR (BIT(18))
+#define LEDC_OVF_CNT_CH6_INT_CLR_M (LEDC_OVF_CNT_CH6_INT_CLR_V << LEDC_OVF_CNT_CH6_INT_CLR_S)
+#define LEDC_OVF_CNT_CH6_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH6_INT_CLR_S 18
+
+/* LEDC_OVF_CNT_CH7_INT_CLR : WO; bitpos: [19]; default: 0;
+ * Set this bit to clear the LEDC_OVF_CNT_CH7_INT interrupt.
+ */
+
+#define LEDC_OVF_CNT_CH7_INT_CLR (BIT(19))
+#define LEDC_OVF_CNT_CH7_INT_CLR_M (LEDC_OVF_CNT_CH7_INT_CLR_V << LEDC_OVF_CNT_CH7_INT_CLR_S)
+#define LEDC_OVF_CNT_CH7_INT_CLR_V 0x00000001
+#define LEDC_OVF_CNT_CH7_INT_CLR_S 19
+
+/* LEDC_CONF_REG register
+ * Global ledc configuration register
+ */
+
+#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0xd0)
+
+/* LEDC_APB_CLK_SEL : R/W; bitpos: [1:0]; default: 0;
+ * This bit is used to select clock source for the 4 timers .
+ *
+ * 2'd1: APB_CLK 2'd2: RTC8M_CLK 2'd3: XTAL_CLK
+ */
+
+#define LEDC_APB_CLK_SEL 0x00000003
+#define LEDC_APB_CLK_SEL_M (LEDC_APB_CLK_SEL_V << LEDC_APB_CLK_SEL_S)
+#define LEDC_APB_CLK_SEL_V 0x00000003
+#define LEDC_APB_CLK_SEL_S 0
+
+/* LEDC_CLK_EN : R/W; bitpos: [31]; default: 0;
+ * This bit is used to control clock.
+ *
+ * 1'b1: Force clock on for register. 1'h0: Support clock only when
+ * application writes registers.
+ */
+
+#define LEDC_CLK_EN (BIT(31))
+#define LEDC_CLK_EN_M (LEDC_CLK_EN_V << LEDC_CLK_EN_S)
+#define LEDC_CLK_EN_V 0x00000001
+#define LEDC_CLK_EN_S 31
+
+/* LEDC_DATE_REG register
+ * Version control register
+ */
+
+#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0xfc)
+
+/* LEDC_DATE : R/W; bitpos: [31:0]; default: 419898881;
+ * This is the version control register.
+ */
+
+#define LEDC_DATE 0xFFFFFFFF
+#define LEDC_DATE_M (LEDC_DATE_V << LEDC_DATE_S)
+#define LEDC_DATE_V 0xFFFFFFFF
+#define LEDC_DATE_S 0
+
+#endif /* __ARCH_RISCV_SRC_ESP32C3_HARDWARE_ESP32C3_LEDC_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig
new file mode 100644
index 0000000..f17d773
--- /dev/null
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/configs/pwm/defconfig
@@ -0,0 +1,47 @@
+#
+# This file is autogenerated: PLEASE DO NOT EDIT IT.
+#
+# You can use "make menuconfig" to make any modifications to the installed .config file.
+# You can then do "make savedefconfig" to generate a new defconfig file that includes your
+# modifications.
+#
+# CONFIG_NSH_ARGCAT is not set
+# CONFIG_NSH_CMDOPT_HEXDUMP is not set
+# CONFIG_NSH_CMDPARMS is not set
+CONFIG_ARCH="risc-v"
+CONFIG_ARCH_BOARD="esp32c3-devkit"
+CONFIG_ARCH_BOARD_ESP32C3_DEVKIT=y
+CONFIG_ARCH_CHIP="esp32c3"
+CONFIG_ARCH_CHIP_ESP32C3=y
+CONFIG_ARCH_CHIP_ESP32C3WROOM02=y
+CONFIG_ARCH_INTERRUPTSTACK=1536
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_BOARD_LOOPSPERMSEC=15000
+CONFIG_BUILTIN=y
+CONFIG_DEV_ZERO=y
+CONFIG_ESP32C3_LEDC=y
+CONFIG_ESP32C3_LEDC_TIM0=y
+CONFIG_EXAMPLES_PWM=y
+CONFIG_FS_PROCFS=y
+CONFIG_IDLETHREAD_STACKSIZE=2048
+CONFIG_INTELHEX_BINARY=y
+CONFIG_LIBC_PERROR_STDOUT=y
+CONFIG_LIBC_STRERROR=y
+CONFIG_MAX_TASKS=8
+CONFIG_NFILE_DESCRIPTORS_PER_BLOCK=6
+CONFIG_NSH_ARCHINIT=y
+CONFIG_NSH_BUILTIN_APPS=y
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_READLINE=y
+CONFIG_NSH_STRERROR=y
+CONFIG_PREALLOC_TIMERS=0
+CONFIG_RAW_BINARY=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_WAITPID=y
+CONFIG_START_DAY=29
+CONFIG_START_MONTH=11
+CONFIG_START_YEAR=2019
+CONFIG_SYSTEM_NSH=y
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_USER_ENTRYPOINT="nsh_main"
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
index f91d709..de96dd4 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/Makefile
@@ -66,6 +66,10 @@ ifeq ($(CONFIG_ONESHOT),y)
CSRCS += esp32c3_oneshot.c
endif
+ifeq ($(CONFIG_PWM),y)
+CSRCS += esp32c3_ledc.c
+endif
+
SCRIPTIN = $(SCRIPTDIR)$(DELIM)esp32c3.template.ld
SCRIPTOUT = $(SCRIPTDIR)$(DELIM)esp32c3_out.ld
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
index c55776b..86da6bc 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3-devkit.h
@@ -181,5 +181,17 @@ int board_bmp180_initialize(int devno, int busno);
int esp32c3_spiflash_init(void);
#endif
+/****************************************************************************
+ * Name: esp32c3_ledc_setup
+ *
+ * Description:
+ * Initialize LEDC PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32C3_LEDC
+int esp32c3_pwm_setup(void);
+#endif
+
#endif /* __ASSEMBLY__ */
#endif /* __BOARDS_RISCV_ESP32C3_ESP32C3_DEVKIT_SRC_ESP32C3_DEVKIT_H */
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
index e914603..b913de6 100644
--- a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_bringup.c
@@ -283,6 +283,14 @@ int esp32c3_bringup(void)
#endif
+#ifdef CONFIG_ESP32C3_LEDC
+ ret = esp32c3_pwm_setup();
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: esp32c3_pwm_setup() failed: %d\n", ret);
+ }
+#endif /* CONFIG_ESP32C3_LEDC */
+
/* If we got here then perhaps not all initialization was successful, but
* at least enough succeeded to bring-up NSH with perhaps reduced
* capabilities.
diff --git a/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c
new file mode 100644
index 0000000..5771aeb
--- /dev/null
+++ b/boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c
@@ -0,0 +1,116 @@
+/****************************************************************************
+ * boards/risc-v/esp32c3/esp32c3-devkit/src/esp32c3_ledc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/timers/pwm.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "esp32c3_ledc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32c3_pwm_setup
+ *
+ * Description:
+ * Initialize LEDC PWM and register the PWM device.
+ *
+ ****************************************************************************/
+
+int esp32c3_pwm_setup(void)
+{
+ int ret;
+ struct pwm_lowerhalf_s *pwm;
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM0
+ pwm = esp32c3_ledc_init(0);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 0 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm0" */
+
+ ret = pwm_register("/dev/pwm0", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM1
+ pwm = esp32c3_ledc_init(1);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 1 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm1" */
+
+ ret = pwm_register("/dev/pwm1", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+#ifdef CONFIG_ESP32C3_LEDC_TIM2
+ pwm = esp32c3_ledc_init(2);
+ if (!pwm)
+ {
+ syslog(LOG_ERR, "ERROR: Failed to get the LEDC PWM 2 lower half\n");
+ return -ENODEV;
+ }
+
+ /* Register the PWM driver at "/dev/pwm2" */
+
+ ret = pwm_register("/dev/pwm2", pwm);
+ if (ret < 0)
+ {
+ syslog(LOG_ERR, "ERROR: pwm_register failed: %d\n", ret);
+ return ret;
+ }
+#endif
+
+ return OK;
+}
+