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Posted to commits@nuttx.apache.org by ac...@apache.org on 2024/04/28 01:09:29 UTC
(nuttx) 01/05: arch/risc-v: unfiy IPI access
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 1ef3767f85a3e5e85b85edaa23d692d001099949
Author: Inochi Amaoto <in...@outlook.com>
AuthorDate: Fri Apr 12 17:27:00 2024 +0800
arch/risc-v: unfiy IPI access
Add ipi process abstract function support.
Signed-off-by: Inochi Amaoto <in...@outlook.com>
---
arch/risc-v/include/csr.h | 2 ++
arch/risc-v/include/mode.h | 14 +++++++++
arch/risc-v/src/bl808/bl808_irq.c | 5 ++--
arch/risc-v/src/common/riscv_cpupause.c | 5 ++--
arch/risc-v/src/common/riscv_cpustart.c | 7 +++--
arch/risc-v/src/common/riscv_ipi.h | 52 +++++++++++++++++++++++++++++++++
arch/risc-v/src/jh7110/jh7110_irq.c | 5 ++--
arch/risc-v/src/k210/k210_irq.c | 5 ++--
arch/risc-v/src/k230/k230_irq.c | 5 ++--
arch/risc-v/src/qemu-rv/qemu_rv_irq.c | 5 ++--
10 files changed, 90 insertions(+), 15 deletions(-)
diff --git a/arch/risc-v/include/csr.h b/arch/risc-v/include/csr.h
index 6102b620e5..4cbf24fd8d 100644
--- a/arch/risc-v/include/csr.h
+++ b/arch/risc-v/include/csr.h
@@ -366,9 +366,11 @@
/* In mip (machine interrupt pending) register */
#define MIP_SSIP (0x1 << 1)
+#define MIP_MSIP (0x1 << 3)
#define MIP_STIP (0x1 << 5)
#define MIP_MTIP (0x1 << 7)
#define MIP_SEIP (0x1 << 9)
+#define MIP_MEIP (0x1 << 11)
/* In sstatus register (which is a view of mstatus) */
diff --git a/arch/risc-v/include/mode.h b/arch/risc-v/include/mode.h
index f5060c35e0..e16c93bc95 100644
--- a/arch/risc-v/include/mode.h
+++ b/arch/risc-v/include/mode.h
@@ -40,6 +40,7 @@
# define CSR_SCRATCH CSR_SSCRATCH /* Scratch register */
# define CSR_EPC CSR_SEPC /* Exception program counter */
# define CSR_IE CSR_SIE /* Interrupt enable register */
+# define CSR_IP CSR_SIP /* Interrupt pending register */
# define CSR_CAUSE CSR_SCAUSE /* Interrupt cause register */
# define CSR_TVAL CSR_STVAL /* Trap value register */
# define CSR_TVEC CSR_STVEC /* Trap vector base addr register */
@@ -57,6 +58,12 @@
# define IE_SIE SIE_SSIE /* Software interrupt enable */
# define IE_TIE SIE_STIE /* Timer interrupt enable */
+/* Interrupt pending bits */
+
+# define IP_EIP SIP_SEIP /* External interrupt pending */
+# define IP_SIP SIP_SSIP /* Software interrupt pending */
+# define IP_TIP SIP_STIP /* Timer interrupt pending */
+
/* External, timer and software interrupt */
# define RISCV_IRQ_EXT RISCV_IRQ_SEXT /* PLIC IRQ */
@@ -75,6 +82,7 @@
# define CSR_SCRATCH CSR_MSCRATCH /* Scratch register */
# define CSR_EPC CSR_MEPC /* Exception program counter */
# define CSR_IE CSR_MIE /* Interrupt enable register */
+# define CSR_IP CSR_MIP /* Interrupt pending register */
# define CSR_CAUSE CSR_MCAUSE /* Interrupt cause register */
# define CSR_TVAL CSR_MTVAL /* Trap value register */
# define CSR_TVEC CSR_MTVEC /* Trap vector base addr register */
@@ -92,6 +100,12 @@
# define IE_SIE MIE_MSIE /* Software interrupt enable */
# define IE_TIE MIE_MTIE /* Timer interrupt enable */
+/* Interrupt pending bits */
+
+# define IP_EIP MIP_MEIP /* External interrupt pending */
+# define IP_SIP MIP_MSIP /* Software interrupt pending */
+# define IP_TIP MIP_MTIP /* Timer interrupt pending */
+
/* External, timer and software interrupt */
# define RISCV_IRQ_EXT RISCV_IRQ_MEXT /* PLIC IRQ */
diff --git a/arch/risc-v/src/bl808/bl808_irq.c b/arch/risc-v/src/bl808/bl808_irq.c
index 1e52f1580d..841c1c82ad 100644
--- a/arch/risc-v/src/bl808/bl808_irq.c
+++ b/arch/risc-v/src/bl808/bl808_irq.c
@@ -33,6 +33,7 @@
#include <nuttx/irq.h>
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#include "chip.h"
/****************************************************************************
@@ -86,9 +87,9 @@ void up_irqinitialize(void)
putreg32(0, BL808_PLIC_THRESHOLD);
#ifdef CONFIG_SMP
- /* Clear RISCV_IPI for CPU0 */
+ /* Clear IPI for CPU0 */
- putreg32(0, RISCV_IPI);
+ riscv_ipi_clear(0);
up_enable_irq(RISCV_IRQ_SOFT);
#endif
diff --git a/arch/risc-v/src/common/riscv_cpupause.c b/arch/risc-v/src/common/riscv_cpupause.c
index 730fc55170..be6708edbd 100644
--- a/arch/risc-v/src/common/riscv_cpupause.c
+++ b/arch/risc-v/src/common/riscv_cpupause.c
@@ -36,6 +36,7 @@
#include "sched/sched.h"
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#include "chip.h"
/****************************************************************************
@@ -230,7 +231,7 @@ int riscv_pause_handler(int irq, void *c, void *arg)
/* Clear IPI (Inter-Processor-Interrupt) */
- putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
+ riscv_ipi_clear(cpu);
/* Check for false alarms. Such false could occur as a consequence of
* some deadlock breaking logic that might have already serviced the SG2
@@ -306,7 +307,7 @@ int up_cpu_pause(int cpu)
/* Execute Pause IRQ to CPU(cpu) */
- putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu));
+ riscv_ipi_send(cpu);
/* Wait for the other CPU to unlock g_cpu_paused meaning that
* it is fully paused and ready for up_cpu_resume();
diff --git a/arch/risc-v/src/common/riscv_cpustart.c b/arch/risc-v/src/common/riscv_cpustart.c
index 332cd2e858..244b9caa89 100644
--- a/arch/risc-v/src/common/riscv_cpustart.c
+++ b/arch/risc-v/src/common/riscv_cpustart.c
@@ -38,6 +38,7 @@
#include "sched/sched.h"
#include "init/init.h"
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#ifdef CONFIG_BUILD_KERNEL
# include "riscv_mmu.h"
@@ -67,7 +68,7 @@ void riscv_cpu_boot(int cpu)
{
/* Clear IPI for CPU(cpu) */
- putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
+ riscv_ipi_clear(cpu);
/* Enable machine software interrupt for IPI to boot */
@@ -107,7 +108,7 @@ void riscv_cpu_boot(int cpu)
/* Clear machine software interrupt for CPU(cpu) */
- putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
+ riscv_ipi_clear(cpu);
#ifdef CONFIG_SCHED_INSTRUMENTATION
/* Notify that this CPU has started */
@@ -161,7 +162,7 @@ int up_cpu_start(int cpu)
/* Send IPI to CPU(cpu) */
- putreg32(1, (uintptr_t)RISCV_IPI + (cpu * 4));
+ riscv_ipi_send(cpu);
return 0;
}
diff --git a/arch/risc-v/src/common/riscv_ipi.h b/arch/risc-v/src/common/riscv_ipi.h
new file mode 100644
index 0000000000..425260d484
--- /dev/null
+++ b/arch/risc-v/src/common/riscv_ipi.h
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/risc-v/src/common/riscv_ipi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H
+#define __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "riscv_internal.h"
+#include "chip.h"
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+static inline void riscv_ipi_send(int cpu)
+{
+#if defined(RISCV_IPI)
+ putreg32(1, (uintptr_t)RISCV_IPI + (4 * cpu));
+#else
+ PANIC();
+#endif
+}
+
+static inline void riscv_ipi_clear(int cpu)
+{
+#if defined(RISCV_IPI)
+ putreg32(0, (uintptr_t)RISCV_IPI + (4 * cpu));
+#endif
+ CLEAR_CSR(CSR_IP, IP_SIP);
+}
+
+#endif /* __ARCH_RISCV_SRC_COMMON_RISCV_IPI_H */
diff --git a/arch/risc-v/src/jh7110/jh7110_irq.c b/arch/risc-v/src/jh7110/jh7110_irq.c
index 6bb4fe3f8a..ec30dbf417 100644
--- a/arch/risc-v/src/jh7110/jh7110_irq.c
+++ b/arch/risc-v/src/jh7110/jh7110_irq.c
@@ -33,6 +33,7 @@
#include <nuttx/irq.h>
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#include "chip.h"
/****************************************************************************
@@ -79,9 +80,9 @@ void up_irqinitialize(void)
riscv_exception_attach();
#ifdef CONFIG_SMP
- /* Clear RISCV_IPI for CPU0 */
+ /* Clear IPI for CPU0 */
- putreg32(0, RISCV_IPI);
+ riscv_ipi_clear(0);
up_enable_irq(RISCV_IRQ_SOFT);
#endif
diff --git a/arch/risc-v/src/k210/k210_irq.c b/arch/risc-v/src/k210/k210_irq.c
index 98369e30d1..2a4e8f3f1c 100644
--- a/arch/risc-v/src/k210/k210_irq.c
+++ b/arch/risc-v/src/k210/k210_irq.c
@@ -33,6 +33,7 @@
#include <nuttx/irq.h>
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#include "k210.h"
/****************************************************************************
@@ -85,9 +86,9 @@ void up_irqinitialize(void)
riscv_exception_attach();
#ifdef CONFIG_SMP
- /* Clear RISCV_IPI for CPU0 */
+ /* Clear IPI for CPU0 */
- putreg32(0, RISCV_IPI);
+ riscv_ipi_clear(0);
up_enable_irq(RISCV_IRQ_SOFT);
#endif
diff --git a/arch/risc-v/src/k230/k230_irq.c b/arch/risc-v/src/k230/k230_irq.c
index 8e6bd3c0ac..0a6ea357d0 100644
--- a/arch/risc-v/src/k230/k230_irq.c
+++ b/arch/risc-v/src/k230/k230_irq.c
@@ -33,6 +33,7 @@
#include <nuttx/irq.h>
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#include "chip.h"
#define STATUS_LOW (READ_CSR(CSR_STATUS) & 0xffffffff) /* STATUS low part */
@@ -83,9 +84,9 @@ void up_irqinitialize(void)
riscv_exception_attach();
#ifdef CONFIG_SMP
- /* Clear RISCV_IPI for CPU0 */
+ /* Clear IPI for CPU0 */
- putreg32(0, RISCV_IPI);
+ riscv_ipi_clear(0);
up_enable_irq(RISCV_IRQ_SOFT);
#endif
diff --git a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
index aa5fb31577..0db0804660 100644
--- a/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
+++ b/arch/risc-v/src/qemu-rv/qemu_rv_irq.c
@@ -33,6 +33,7 @@
#include <nuttx/irq.h>
#include "riscv_internal.h"
+#include "riscv_ipi.h"
#include "chip.h"
/****************************************************************************
@@ -79,9 +80,9 @@ void up_irqinitialize(void)
riscv_exception_attach();
#ifdef CONFIG_SMP
- /* Clear RISCV_IPI for CPU0 */
+ /* Clear IPI for CPU0 */
- putreg32(0, RISCV_IPI);
+ riscv_ipi_clear(0);
up_enable_irq(RISCV_IRQ_SOFT);
#endif