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Posted to commits@nuttx.apache.org by ac...@apache.org on 2022/01/27 16:47:06 UTC
[incubator-nuttx] branch master updated: xtensa: Add initial support for ESP32-S3
This is an automated email from the ASF dual-hosted git repository.
acassis pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
The following commit(s) were added to refs/heads/master by this push:
new b0d24f5 xtensa: Add initial support for ESP32-S3
b0d24f5 is described below
commit b0d24f53c4be391f2e0081ef4bba4f5058e54f9e
Author: Gustavo Henrique Nihei <gu...@espressif.com>
AuthorDate: Fri Jan 7 14:44:06 2022 -0300
xtensa: Add initial support for ESP32-S3
Co-authored-by: Alan Carvalho de Assis <al...@espressif.com>
Signed-off-by: Gustavo Henrique Nihei <gu...@espressif.com>
---
arch/xtensa/Kconfig | 39 +-
arch/xtensa/include/esp32s3/chip.h | 66 +
arch/xtensa/include/esp32s3/core-isa.h | 695 +
arch/xtensa/include/esp32s3/irq.h | 463 +
arch/xtensa/include/esp32s3/tie-asm.h | 433 +
arch/xtensa/include/esp32s3/tie.h | 209 +
arch/xtensa/include/lx7/chip.h | 62 +
arch/xtensa/src/esp32s3/.gitignore | 1 +
arch/xtensa/src/esp32s3/Bootloader.mk | 88 +
arch/xtensa/src/esp32s3/Kconfig | 461 +
arch/xtensa/src/esp32s3/Make.defs | 74 +
arch/xtensa/src/esp32s3/chip.h | 61 +
arch/xtensa/src/esp32s3/chip_macros.h | 91 +
arch/xtensa/src/esp32s3/chip_memory.h | 73 +
arch/xtensa/src/esp32s3/esp32s3_allocateheap.c | 84 +
arch/xtensa/src/esp32s3/esp32s3_clockconfig.c | 312 +
arch/xtensa/src/esp32s3/esp32s3_clockconfig.h | 120 +
arch/xtensa/src/esp32s3/esp32s3_config.h | 64 +
arch/xtensa/src/esp32s3/esp32s3_gpio.c | 205 +
arch/xtensa/src/esp32s3/esp32s3_gpio.h | 163 +
arch/xtensa/src/esp32s3/esp32s3_idle.c | 83 +
arch/xtensa/src/esp32s3/esp32s3_irq.c | 686 +
arch/xtensa/src/esp32s3/esp32s3_irq.h | 123 +
arch/xtensa/src/esp32s3/esp32s3_lowputc.c | 846 +
arch/xtensa/src/esp32s3/esp32s3_lowputc.h | 485 +
arch/xtensa/src/esp32s3/esp32s3_region.c | 102 +
arch/xtensa/src/esp32s3/esp32s3_region.h | 52 +
arch/xtensa/src/esp32s3/esp32s3_serial.c | 1166 ++
arch/xtensa/src/esp32s3/esp32s3_start.c | 324 +
arch/xtensa/src/esp32s3/esp32s3_start.h | 54 +
arch/xtensa/src/esp32s3/esp32s3_systemreset.c | 54 +
arch/xtensa/src/esp32s3/esp32s3_timerisr.c | 143 +
arch/xtensa/src/esp32s3/esp32s3_user.c | 71 +
arch/xtensa/src/esp32s3/esp32s3_wdt.c | 50 +
arch/xtensa/src/esp32s3/esp32s3_wdt.h | 34 +
.../src/esp32s3/hardware/esp32s3_cache_memory.h | 118 +
arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h | 2761 ++++
arch/xtensa/src/esp32s3/hardware/esp32s3_gpio.h | 15717 +++++++++++++++++++
.../src/esp32s3/hardware/esp32s3_gpio_sigmap.h | 447 +
.../src/esp32s3/hardware/esp32s3_interrupt_core0.h | 1727 ++
.../src/esp32s3/hardware/esp32s3_interrupt_core1.h | 1726 ++
arch/xtensa/src/esp32s3/hardware/esp32s3_iomux.h | 467 +
.../src/esp32s3/hardware/esp32s3_rom_layout.h | 95 +
arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h | 5795 +++++++
arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h | 487 +
arch/xtensa/src/esp32s3/hardware/esp32s3_system.h | 1757 +++
.../xtensa/src/esp32s3/hardware/esp32s3_systimer.h | 808 +
arch/xtensa/src/esp32s3/hardware/esp32s3_uart.h | 1961 +++
arch/xtensa/src/lx7/Toolchain.defs | 2 +-
boards/Kconfig | 18 +
boards/xtensa/esp32s3/common/Kconfig | 13 +
boards/xtensa/esp32s3/common/Makefile | 33 +
boards/xtensa/esp32s3/common/src/Make.defs | 23 +
boards/xtensa/esp32s3/esp32s3-devkit/Kconfig | 8 +
.../esp32s3/esp32s3-devkit/configs/nsh/defconfig | 48 +
.../xtensa/esp32s3/esp32s3-devkit/include/board.h | 73 +
.../esp32s3/esp32s3-devkit/scripts/.gitignore | 1 +
.../esp32s3/esp32s3-devkit/scripts/Make.defs | 92 +
.../esp32s3/esp32s3-devkit/scripts/esp32s3.ld | 269 +
.../esp32s3-devkit/scripts/esp32s3.template.ld | 113 +
.../esp32s3-devkit/scripts/esp32s3_peripherals.ld | 47 +
.../esp32s3/esp32s3-devkit/scripts/esp32s3_rom.ld | 2522 +++
boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs | 52 +
.../esp32s3/esp32s3-devkit/src/esp32s3-devkit.h | 67 +
.../esp32s3/esp32s3-devkit/src/esp32s3_appinit.c | 80 +
.../esp32s3/esp32s3-devkit/src/esp32s3_boot.c | 83 +
.../esp32s3/esp32s3-devkit/src/esp32s3_bringup.c | 93 +
.../esp32s3/esp32s3-devkit/src/esp32s3_reset.c | 63 +
tools/esp32s3/Config.mk | 140 +
69 files changed, 45740 insertions(+), 3 deletions(-)
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 88a1fc9..0b16b9c 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -70,6 +70,34 @@ config ARCH_CHIP_ESP32S2
Based on an Xtensa single-core 32-bit LX7 processor, it can be clocked
at up to 240 MHz.
+config ARCH_CHIP_ESP32S3
+ bool "Espressif ESP32-S3"
+ select ARCH_FAMILY_LX7
+ select XTENSA_HAVE_INTERRUPTS
+ select ARCH_HAVE_MULTICPU
+ select ARCH_HAVE_TEXT_HEAP
+ select ARCH_HAVE_SDRAM
+ select ARCH_HAVE_RESET
+ select ARCH_HAVE_BOOTLOADER
+ select ARCH_VECNOTIRQ
+ select LIBC_ARCH_MEMCPY
+ select LIBC_ARCH_MEMCHR
+ select LIBC_ARCH_MEMCMP
+ select LIBC_ARCH_MEMMOVE
+ select LIBC_ARCH_MEMSET
+ select LIBC_ARCH_STRCHR
+ select LIBC_ARCH_STRCMP
+ select LIBC_ARCH_STRCPY
+ select LIBC_ARCH_STRLCPY
+ select LIBC_ARCH_STRNCPY
+ select LIBC_ARCH_STRLEN
+ select LIBC_ARCH_STRNLEN
+ ---help---
+ ESP32-S3 is a dual-core Xtensa LX7 MCU, capable of running at 240 MHz.
+ Apart from its 512 KB of internal SRAM, it also comes with integrated 2.4 GHz,
+ 802.11 b/g/n Wi-Fi and Bluetooth 5 (LE) connectivity that provides long-range
+ support.
+
config ARCH_CHIP_XTENSA_CUSTOM
bool "Custom XTENSA chip"
select ARCH_CHIP_CUSTOM
@@ -145,8 +173,9 @@ config ARCH_FAMILY_LX7
config ARCH_CHIP
string
- default "esp32" if ARCH_CHIP_ESP32
- default "esp32s2" if ARCH_CHIP_ESP32S2
+ default "esp32" if ARCH_CHIP_ESP32
+ default "esp32s2" if ARCH_CHIP_ESP32S2
+ default "esp32s3" if ARCH_CHIP_ESP32S3
config XTENSA_CP_LAZY
bool "Lazy co-processor state restoration"
@@ -267,13 +296,19 @@ config XTENSA_TOOLCHAIN_ESP
endchoice
source "arch/xtensa/src/lx6/Kconfig"
+
if ARCH_CHIP_ESP32
source "arch/xtensa/src/esp32/Kconfig"
endif
source "arch/xtensa/src/lx7/Kconfig"
+
if ARCH_CHIP_ESP32S2
source "arch/xtensa/src/esp32s2/Kconfig"
endif
+if ARCH_CHIP_ESP32S3
+source "arch/xtensa/src/esp32s3/Kconfig"
+endif
+
endif # ARCH_XTENSA
diff --git a/arch/xtensa/include/esp32s3/chip.h b/arch/xtensa/include/esp32s3/chip.h
new file mode 100644
index 0000000..c347369
--- /dev/null
+++ b/arch/xtensa/include/esp32s3/chip.h
@@ -0,0 +1,66 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_CHIP_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32S3_NGPIOS 45 /* GPIO0-44 */
+
+/* Characterize each supported ESP32-S3 part */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_CHIP_H */
diff --git a/arch/xtensa/include/esp32s3/core-isa.h b/arch/xtensa/include/esp32s3/core-isa.h
new file mode 100644
index 0000000..4120440
--- /dev/null
+++ b/arch/xtensa/include/esp32s3/core-isa.h
@@ -0,0 +1,695 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/core-isa.h
+ * Xtensa processor core configuration information.
+ *
+ * Customer ID=15128; Build=0x90f1f; Copyright (c) 1999-2021 Tensilica Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Parameters Useful for Any Code, USER or PRIVILEGED
+ ****************************************************************************/
+
+/* Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option
+ * is configured, and a value of 0 otherwise. These macros are always
+ * defined.
+ */
+
+/****************************************************************************
+ * ISA
+ ****************************************************************************/
+
+#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
+#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
+#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
+#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
+#define XCHAL_MAX_INSTRUCTION_SIZE 4 /* max instr bytes (3..8) */
+#define XCHAL_HAVE_DEBUG 1 /* debug option */
+#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
+#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
+#define XCHAL_LOOP_BUFFER_SIZE 256 /* zero-ov. loop instr buffer size */
+#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
+#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
+#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
+#define XCHAL_HAVE_DEPBITS 0 /* DEPBITS instruction */
+#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
+#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
+#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
+#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
+#define XCHAL_HAVE_DIV32 1 /* QUOS/QUOU/REMS/REMU instructions */
+#define XCHAL_HAVE_L32R 1 /* L32R instruction */
+#define XCHAL_HAVE_ABSOLUTE_LITERALS 0 /* non-PC-rel (extended) L32R */
+#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
+#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
+#define XCHAL_HAVE_EXCLUSIVE 0 /* L32EX/S32EX instructions */
+#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
+#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
+#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
+#define XCHAL_HAVE_ABS 1 /* ABS instruction */
+
+/* #define XCHAL_HAVE_POPC 0 */ /* POPC instruction */
+
+/* #define XCHAL_HAVE_CRC 0 */ /* CRC instruction */
+
+#define XCHAL_HAVE_RELEASE_SYNC 1 /* L32AI/S32RI instructions */
+#define XCHAL_HAVE_S32C1I 1 /* S32C1I instruction */
+#define XCHAL_HAVE_SPECULATION 0 /* speculation */
+#define XCHAL_HAVE_FULL_RESET 1 /* all regs/state reset */
+#define XCHAL_NUM_CONTEXTS 1 /* */
+#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
+#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
+#define XCHAL_HAVE_PRID 1 /* processor ID register */
+#define XCHAL_HAVE_EXTERN_REGS 1 /* WER/RER instructions */
+#define XCHAL_HAVE_MX 0 /* MX core (Tensilica internal) */
+#define XCHAL_HAVE_MP_INTERRUPTS 0 /* interrupt distributor port */
+#define XCHAL_HAVE_MP_RUNSTALL 0 /* core RunStall control port */
+#define XCHAL_HAVE_PSO 0 /* Power Shut-Off */
+#define XCHAL_HAVE_PSO_CDM 0 /* core/debug/mem pwr domains */
+#define XCHAL_HAVE_PSO_FULL_RETENTION 0 /* all regs preserved on PSO */
+#define XCHAL_HAVE_THREADPTR 1 /* THREADPTR register */
+#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
+#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
+#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
+#define XCHAL_HAVE_MAC16 1 /* MAC16 package */
+#define XCHAL_HAVE_FUSION 0 /* Fusion*/
+#define XCHAL_HAVE_FUSION_FP 0 /* Fusion FP option */
+#define XCHAL_HAVE_FUSION_LOW_POWER 0 /* Fusion Low Power option */
+#define XCHAL_HAVE_FUSION_AES 0 /* Fusion BLE/Wifi AES-128 CCM option */
+#define XCHAL_HAVE_FUSION_CONVENC 0 /* Fusion Conv Encode option */
+#define XCHAL_HAVE_FUSION_LFSR_CRC 0 /* Fusion LFSR-CRC option */
+#define XCHAL_HAVE_FUSION_BITOPS 0 /* Fusion Bit Operations Support option */
+#define XCHAL_HAVE_FUSION_AVS 0 /* Fusion AVS option */
+#define XCHAL_HAVE_FUSION_16BIT_BASEBAND 0 /* Fusion 16-bit Baseband option */
+#define XCHAL_HAVE_FUSION_VITERBI 0 /* Fusion Viterbi option */
+#define XCHAL_HAVE_FUSION_SOFTDEMAP 0 /* Fusion Soft Bit Demap option */
+#define XCHAL_HAVE_HIFIPRO 0 /* HiFiPro Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5 0 /* HiFi5 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI5_NN_MAC 0 /* HiFi5 Audio Engine NN-MAC option */
+#define XCHAL_HAVE_HIFI5_VFPU 0 /* HiFi5 Audio Engine Single-Precision VFPU option */
+#define XCHAL_HAVE_HIFI5_HP_VFPU 0 /* HiFi5 Audio Engine Half-Precision VFPU option */
+#define XCHAL_HAVE_HIFI4 0 /* HiFi4 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI4_VFPU 0 /* HiFi4 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3 0 /* HiFi3 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3_VFPU 0 /* HiFi3 Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI3Z 0 /* HiFi3Z Audio Engine pkg */
+#define XCHAL_HAVE_HIFI3Z_VFPU 0 /* HiFi3Z Audio Engine VFPU option */
+#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
+#define XCHAL_HAVE_HIFI2EP 0 /* HiFi2EP */
+#define XCHAL_HAVE_HIFI_MINI 0
+#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
+#define XCHAL_HAVE_USER_DPFPU 0 /* user DP floating-point pkg */
+#define XCHAL_HAVE_USER_SPFPU 0 /* user SP floating-point pkg */
+#define XCHAL_HAVE_FP 1 /* single prec floating point */
+#define XCHAL_HAVE_FP_DIV 1 /* FP with DIV instructions */
+#define XCHAL_HAVE_FP_RECIP 1 /* FP with RECIP instructions */
+#define XCHAL_HAVE_FP_SQRT 1 /* FP with SQRT instructions */
+#define XCHAL_HAVE_FP_RSQRT 1 /* FP with RSQRT instructions */
+#define XCHAL_HAVE_DFP 0 /* double precision FP pkg */
+#define XCHAL_HAVE_DFP_DIV 0 /* DFP with DIV instructions */
+#define XCHAL_HAVE_DFP_RECIP 0 /* DFP with RECIP instructions*/
+#define XCHAL_HAVE_DFP_SQRT 0 /* DFP with SQRT instructions */
+#define XCHAL_HAVE_DFP_RSQRT 0 /* DFP with RSQRT instructions*/
+#define XCHAL_HAVE_DFP_ACCEL 0 /* double precision FP acceleration pkg */
+
+#define XCHAL_HAVE_DFP_accel XCHAL_HAVE_DFP_ACCEL /* for backward compatibility */
+
+#define XCHAL_HAVE_DFPU_SINGLE_ONLY 1 /* DFPU Coprocessor, single precision only */
+#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE 0 /* DFPU Coprocessor, single and double precision */
+#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
+#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
+#define XCHAL_HAVE_FUSIONG 0 /* FusionG */
+#define XCHAL_HAVE_FUSIONG3 0 /* FusionG3 */
+#define XCHAL_HAVE_FUSIONG6 0 /* FusionG6 */
+#define XCHAL_HAVE_FUSIONG_SP_VFPU 0 /* sp_vfpu option on FusionG */
+#define XCHAL_HAVE_FUSIONG_DP_VFPU 0 /* dp_vfpu option on FusionG */
+#define XCHAL_FUSIONG_SIMD32 0 /* simd32 for FusionG */
+#define XCHAL_HAVE_PDX 0 /* PDX */
+#define XCHAL_PDX_SIMD32 0 /* simd32 for PDX */
+#define XCHAL_HAVE_PDX4 0 /* PDX4 */
+#define XCHAL_HAVE_PDX8 0 /* PDX8 */
+#define XCHAL_HAVE_PDX16 0 /* PDX16 */
+#define XCHAL_HAVE_CONNXD2 0 /* ConnX D2 pkg */
+#define XCHAL_HAVE_CONNXD2_DUALLSFLIX 0 /* ConnX D2 Dual LoadStore Flix */
+#define XCHAL_HAVE_BBE16 0 /* ConnX BBE16 pkg */
+#define XCHAL_HAVE_BBE16_RSQRT 0 /* BBE16 vector recip sqrt */
+#define XCHAL_HAVE_BBE16_VECDIV 0 /* BBE16 vector divide */
+#define XCHAL_HAVE_BBE16_DESPREAD 0 /* BBE16 despread */
+#define XCHAL_HAVE_BBENEP 0 /* ConnX BBENEP pkgs */
+#define XCHAL_HAVE_BBENEP_SP_VFPU 0 /* sp_vfpu option on BBE-EP */
+#define XCHAL_HAVE_BSP3 0 /* ConnX BSP3 pkg */
+#define XCHAL_HAVE_BSP3_TRANSPOSE 0 /* BSP3 transpose32x32 */
+#define XCHAL_HAVE_SSP16 0 /* ConnX SSP16 pkg */
+#define XCHAL_HAVE_SSP16_VITERBI 0 /* SSP16 viterbi */
+#define XCHAL_HAVE_TURBO16 0 /* ConnX Turbo16 pkg */
+#define XCHAL_HAVE_BBP16 0 /* ConnX BBP16 pkg */
+#define XCHAL_HAVE_FLIX3 0 /* basic 3-way FLIX option */
+#define XCHAL_HAVE_GRIVPEP 0 /* General Release of IVPEP */
+#define XCHAL_HAVE_GRIVPEP_HISTOGRAM 0 /* Histogram option on GRIVPEP */
+#define XCHAL_HAVE_VISION 0 /* Vision P5/P6 */
+#define XCHAL_VISION_SIMD16 0 /* simd16 for Vision P5/P6 */
+#define XCHAL_VISION_TYPE 0 /* Vision P5, P6, or P3 */
+#define XCHAL_VISION_QUAD_MAC_TYPE 0 /* quad_mac option on Vision P6 */
+#define XCHAL_HAVE_VISION_HISTOGRAM 0 /* histogram option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_SP_VFPU 0 /* sp_vfpu option on Vision P5/P6 */
+#define XCHAL_HAVE_VISION_HP_VFPU 0 /* hp_vfpu option on Vision P6 */
+#define XCHAL_HAVE_VISIONC 0 /* Vision C */
+
+/****************************************************************************
+ * MISC
+ ****************************************************************************/
+
+#define XCHAL_NUM_LOADSTORE_UNITS 1 /* load/store units */
+#define XCHAL_NUM_WRITEBUFFER_ENTRIES 4 /* size of write buffer */
+#define XCHAL_INST_FETCH_WIDTH 4 /* instr-fetch width in bytes */
+#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
+#define XCHAL_DATA_PIPE_DELAY 1 /* d-side pipeline delay (1 = 5-stage, 2 = 7-stage) */
+#define XCHAL_CLOCK_GATING_GLOBAL 1 /* global clock gating */
+#define XCHAL_CLOCK_GATING_FUNCUNIT 1 /* funct. unit clock gating */
+ /* In T1050, applies to selected core load
+ * and store instructions (see ISA)
+ */
+
+#define XCHAL_UNALIGNED_LOAD_EXCEPTION 0 /* unaligned loads cause exc. */
+#define XCHAL_UNALIGNED_STORE_EXCEPTION 0 /* unaligned stores cause exc.*/
+#define XCHAL_UNALIGNED_LOAD_HW 1 /* unaligned loads work in hw */
+#define XCHAL_UNALIGNED_STORE_HW 1 /* unaligned stores work in hw*/
+#define XCHAL_SW_VERSION 1200012 /* sw version of this header */
+#define XCHAL_CORE_ID "LX7_ESP32_S3_MP" /* alphanum core name
+ * (CoreID) set in the Xtensa
+ * Processor Generator
+ */
+
+#define XCHAL_BUILD_UNIQUE_ID 0x00090F1F /* 22-bit sw build ID */
+
+/* These definitions describe the hardware targeted by this software. */
+
+#define XCHAL_HW_CONFIGID0 0xC2F0FFFE /* ConfigID hi 32 bits*/
+#define XCHAL_HW_CONFIGID1 0x23090F1F /* ConfigID lo 32 bits*/
+#define XCHAL_HW_VERSION_NAME "LX7.0.12" /* full version name */
+#define XCHAL_HW_VERSION_MAJOR 2700 /* major ver# of targeted hw */
+#define XCHAL_HW_VERSION_MINOR 12 /* minor ver# of targeted hw */
+#define XCHAL_HW_VERSION 270012 /* major*100+minor */
+#define XCHAL_HW_REL_LX7 1
+#define XCHAL_HW_REL_LX7_0 1
+#define XCHAL_HW_REL_LX7_0_12 1
+#define XCHAL_HW_CONFIGID_RELIABLE 1
+
+/* If software targets a range of hardware versions, these are the bounds: */
+
+#define XCHAL_HW_MIN_VERSION_MAJOR 2700 /* major v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION_MINOR 12 /* minor v of earliest tgt hw */
+#define XCHAL_HW_MIN_VERSION 270012 /* earliest targeted hw */
+#define XCHAL_HW_MAX_VERSION_MAJOR 2700 /* major v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION_MINOR 12 /* minor v of latest tgt hw */
+#define XCHAL_HW_MAX_VERSION 270012 /* latest targeted hw */
+
+/****************************************************************************
+ * CACHE
+ ****************************************************************************/
+
+#define XCHAL_ICACHE_LINESIZE 4 /* I-cache line size in bytes */
+#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
+#define XCHAL_ICACHE_LINEWIDTH 2 /* log2(I line size in bytes) */
+#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
+
+#define XCHAL_ICACHE_SIZE 0 /* I-cache size in bytes or 0 */
+#define XCHAL_DCACHE_SIZE 0 /* D-cache size in bytes or 0 */
+
+#define XCHAL_DCACHE_IS_WRITEBACK 0 /* writeback feature */
+#define XCHAL_DCACHE_IS_COHERENT 0 /* MP coherence feature */
+
+#define XCHAL_HAVE_PREFETCH 0 /* PREFCTL register */
+#define XCHAL_HAVE_PREFETCH_L1 0 /* prefetch to L1 dcache */
+#define XCHAL_PREFETCH_CASTOUT_LINES 0 /* dcache pref. castout bufsz */
+#define XCHAL_PREFETCH_ENTRIES 0 /* cache prefetch entries */
+#define XCHAL_PREFETCH_BLOCK_ENTRIES 0 /* prefetch block streams */
+#define XCHAL_HAVE_CACHE_BLOCKOPS 0 /* block prefetch for caches */
+#define XCHAL_HAVE_ICACHE_TEST 0 /* Icache test instructions */
+#define XCHAL_HAVE_DCACHE_TEST 0 /* Dcache test instructions */
+#define XCHAL_HAVE_ICACHE_DYN_WAYS 0 /* Icache dynamic way support */
+#define XCHAL_HAVE_DCACHE_DYN_WAYS 0 /* Dcache dynamic way support */
+
+/****************************************************************************
+ * Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
+ ****************************************************************************/
+
+#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
+
+/****************************************************************************
+ * CACHE
+ ****************************************************************************/
+
+#define XCHAL_HAVE_PIF 1 /* any outbound bus present */
+
+#define XCHAL_HAVE_AXI 0 /* AXI bus */
+#define XCHAL_HAVE_AXI_ECC 0 /* ECC on AXI bus */
+#define XCHAL_HAVE_ACELITE 0 /* ACELite bus */
+
+#define XCHAL_HAVE_PIF_WR_RESP 0 /* pif write response */
+#define XCHAL_HAVE_PIF_REQ_ATTR 1 /* pif attribute */
+
+/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
+
+/* Number of cache sets in log2(lines per way): */
+
+#define XCHAL_ICACHE_SETWIDTH 0
+#define XCHAL_DCACHE_SETWIDTH 0
+
+/* Cache set associativity (number of ways): */
+
+#define XCHAL_ICACHE_WAYS 1
+#define XCHAL_DCACHE_WAYS 1
+
+/* Cache features: */
+
+#define XCHAL_ICACHE_LINE_LOCKABLE 0
+#define XCHAL_DCACHE_LINE_LOCKABLE 0
+#define XCHAL_ICACHE_ECC_PARITY 0
+#define XCHAL_DCACHE_ECC_PARITY 0
+#define XCHAL_ICACHE_ECC_WIDTH 1
+#define XCHAL_DCACHE_ECC_WIDTH 1
+
+/* Cache access size in bytes (affects operation of SICW instruction): */
+
+#define XCHAL_ICACHE_ACCESS_SIZE 1
+#define XCHAL_DCACHE_ACCESS_SIZE 1
+
+#define XCHAL_DCACHE_BANKS 0 /* number of banks */
+
+/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits) */
+
+#define XCHAL_CA_BITS 4
+
+/****************************************************************************
+ * INTERNAL I/D RAM/ROMs and XLMI
+ ****************************************************************************/
+
+#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
+#define XCHAL_NUM_INSTRAM 1 /* number of core instr. RAMs */
+#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
+#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
+#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
+#define XCHAL_NUM_XLMI 0 /* number of core XLMI ports */
+
+/* Instruction RAM 0: */
+
+#define XCHAL_INSTRAM0_VADDR 0x40000000 /* virtual address */
+#define XCHAL_INSTRAM0_PADDR 0x40000000 /* physical address */
+#define XCHAL_INSTRAM0_SIZE 67108864 /* size in bytes */
+#define XCHAL_INSTRAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_HAVE_INSTRAM0 1
+#define XCHAL_INSTRAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+/* Data RAM 0: */
+
+#define XCHAL_DATARAM0_VADDR 0x3C000000 /* virtual address */
+#define XCHAL_DATARAM0_PADDR 0x3C000000 /* physical address */
+#define XCHAL_DATARAM0_SIZE 67108864 /* size in bytes */
+#define XCHAL_DATARAM0_ECC_PARITY 0 /* ECC/parity type, 0=none */
+#define XCHAL_DATARAM0_BANKS 1 /* number of banks */
+#define XCHAL_HAVE_DATARAM0 1
+#define XCHAL_DATARAM0_HAVE_IDMA 0 /* idma supported by this local memory */
+
+#define XCHAL_HAVE_IDMA 0
+#define XCHAL_HAVE_IDMA_TRANSPOSE 0
+
+#define XCHAL_HAVE_IMEM_LOADSTORE 1 /* can load/store to IROM/IRAM */
+
+/****************************************************************************
+ * INTERRUPTS and TIMERS
+ ****************************************************************************/
+
+#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
+#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
+#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
+#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
+#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
+#define XCHAL_NUM_INTERRUPTS 32 /* number of interrupts */
+#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
+#define XCHAL_NUM_EXTINTERRUPTS 26 /* num of external interrupts */
+#define XCHAL_NUM_INTLEVELS 6 /* number of interrupt levels
+ * (not including level zero)
+ */
+
+#define XCHAL_EXCM_LEVEL 3 /* level masked by PS.EXCM */
+
+/* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
+
+/* Masks of interrupts at each interrupt level: */
+
+#define XCHAL_INTLEVEL1_MASK 0x000637FF
+#define XCHAL_INTLEVEL2_MASK 0x00380000
+#define XCHAL_INTLEVEL3_MASK 0x28C08800
+#define XCHAL_INTLEVEL4_MASK 0x53000000
+#define XCHAL_INTLEVEL5_MASK 0x84010000
+#define XCHAL_INTLEVEL6_MASK 0x00000000
+#define XCHAL_INTLEVEL7_MASK 0x00004000
+
+/* Masks of interrupts at each range 1..n of interrupt levels: */
+
+#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x000637FF
+#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x003E37FF
+#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x28FEBFFF
+#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x7BFEBFFF
+#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0xFFFFBFFF
+#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0xFFFFBFFF
+#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0xFFFFFFFF
+
+/* Level of each interrupt: */
+
+#define XCHAL_INT0_LEVEL 1
+#define XCHAL_INT1_LEVEL 1
+#define XCHAL_INT2_LEVEL 1
+#define XCHAL_INT3_LEVEL 1
+#define XCHAL_INT4_LEVEL 1
+#define XCHAL_INT5_LEVEL 1
+#define XCHAL_INT6_LEVEL 1
+#define XCHAL_INT7_LEVEL 1
+#define XCHAL_INT8_LEVEL 1
+#define XCHAL_INT9_LEVEL 1
+#define XCHAL_INT10_LEVEL 1
+#define XCHAL_INT11_LEVEL 3
+#define XCHAL_INT12_LEVEL 1
+#define XCHAL_INT13_LEVEL 1
+#define XCHAL_INT14_LEVEL 7
+#define XCHAL_INT15_LEVEL 3
+#define XCHAL_INT16_LEVEL 5
+#define XCHAL_INT17_LEVEL 1
+#define XCHAL_INT18_LEVEL 1
+#define XCHAL_INT19_LEVEL 2
+#define XCHAL_INT20_LEVEL 2
+#define XCHAL_INT21_LEVEL 2
+#define XCHAL_INT22_LEVEL 3
+#define XCHAL_INT23_LEVEL 3
+#define XCHAL_INT24_LEVEL 4
+#define XCHAL_INT25_LEVEL 4
+#define XCHAL_INT26_LEVEL 5
+#define XCHAL_INT27_LEVEL 3
+#define XCHAL_INT28_LEVEL 4
+#define XCHAL_INT29_LEVEL 3
+#define XCHAL_INT30_LEVEL 4
+#define XCHAL_INT31_LEVEL 5
+#define XCHAL_DEBUGLEVEL 6 /* debug interrupt level */
+#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
+#define XCHAL_NMILEVEL 7 /* NMI "level" (for use with
+ * EXCSAVE/EPS/EPC_n, RFI n)
+ */
+
+/* Type of each interrupt: */
+
+#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT6_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT7_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT11_TYPE XTHAL_INTTYPE_PROFILING
+#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT14_TYPE XTHAL_INTTYPE_NMI
+#define XCHAL_INT15_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT16_TYPE XTHAL_INTTYPE_TIMER
+#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT19_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT20_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT21_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT22_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT23_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT24_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT25_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT26_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT27_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+#define XCHAL_INT28_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT29_TYPE XTHAL_INTTYPE_SOFTWARE
+#define XCHAL_INT30_TYPE XTHAL_INTTYPE_EXTERN_EDGE
+#define XCHAL_INT31_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
+
+/* Masks of interrupts for each type of interrupt: */
+
+#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0x00000000
+#define XCHAL_INTTYPE_MASK_SOFTWARE 0x20000080
+#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x50400400
+#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x8FBE333F
+#define XCHAL_INTTYPE_MASK_TIMER 0x00018040
+#define XCHAL_INTTYPE_MASK_NMI 0x00004000
+#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
+#define XCHAL_INTTYPE_MASK_PROFILING 0x00000800
+#define XCHAL_INTTYPE_MASK_IDMA_DONE 0x00000000
+#define XCHAL_INTTYPE_MASK_IDMA_ERR 0x00000000
+#define XCHAL_INTTYPE_MASK_GS_ERR 0x00000000
+
+/* Interrupt numbers assigned to specific interrupt sources: */
+
+#define XTHAL_TIMER_UNCONFIGURED -1
+#define XCHAL_TIMER0_INTERRUPT 6 /* CCOMPARE0 */
+#define XCHAL_TIMER1_INTERRUPT 15 /* CCOMPARE1 */
+#define XCHAL_TIMER2_INTERRUPT 16 /* CCOMPARE2 */
+#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
+#define XCHAL_NMI_INTERRUPT 14 /* non-maskable interrupt */
+#define XCHAL_PROFILING_INTERRUPT 11
+
+/* Interrupt numbers for levels at which only one interrupt is configured: */
+
+#define XCHAL_INTLEVEL7_NUM 14
+
+/* (There are many interrupts each at level(s) 1, 2, 3, 4, 5.) */
+
+/* External interrupt mapping.
+ * These macros describe how Xtensa processor interrupt numbers
+ * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
+ * map to external BInterrupt<n> pins, for those interrupts
+ * configured as external (level-triggered, edge-triggered, or NMI).
+ * See the Xtensa processor databook for more details.
+ */
+
+/* Core interrupt numbers mapped to each EXTERNAL BInterrupt pin number: */
+
+#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
+#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
+#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
+#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
+#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
+#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
+#define XCHAL_EXTINT6_NUM 8 /* (intlevel 1) */
+#define XCHAL_EXTINT7_NUM 9 /* (intlevel 1) */
+#define XCHAL_EXTINT8_NUM 10 /* (intlevel 1) */
+#define XCHAL_EXTINT9_NUM 12 /* (intlevel 1) */
+#define XCHAL_EXTINT10_NUM 13 /* (intlevel 1) */
+#define XCHAL_EXTINT11_NUM 14 /* (intlevel 7) */
+#define XCHAL_EXTINT12_NUM 17 /* (intlevel 1) */
+#define XCHAL_EXTINT13_NUM 18 /* (intlevel 1) */
+#define XCHAL_EXTINT14_NUM 19 /* (intlevel 2) */
+#define XCHAL_EXTINT15_NUM 20 /* (intlevel 2) */
+#define XCHAL_EXTINT16_NUM 21 /* (intlevel 2) */
+#define XCHAL_EXTINT17_NUM 22 /* (intlevel 3) */
+#define XCHAL_EXTINT18_NUM 23 /* (intlevel 3) */
+#define XCHAL_EXTINT19_NUM 24 /* (intlevel 4) */
+#define XCHAL_EXTINT20_NUM 25 /* (intlevel 4) */
+#define XCHAL_EXTINT21_NUM 26 /* (intlevel 5) */
+#define XCHAL_EXTINT22_NUM 27 /* (intlevel 3) */
+#define XCHAL_EXTINT23_NUM 28 /* (intlevel 4) */
+#define XCHAL_EXTINT24_NUM 30 /* (intlevel 4) */
+#define XCHAL_EXTINT25_NUM 31 /* (intlevel 5) */
+
+/* EXTERNAL BInterrupt pin numbers mapped to each core interrupt number: */
+
+#define XCHAL_INT0_EXTNUM 0 /* (intlevel 1) */
+#define XCHAL_INT1_EXTNUM 1 /* (intlevel 1) */
+#define XCHAL_INT2_EXTNUM 2 /* (intlevel 1) */
+#define XCHAL_INT3_EXTNUM 3 /* (intlevel 1) */
+#define XCHAL_INT4_EXTNUM 4 /* (intlevel 1) */
+#define XCHAL_INT5_EXTNUM 5 /* (intlevel 1) */
+#define XCHAL_INT8_EXTNUM 6 /* (intlevel 1) */
+#define XCHAL_INT9_EXTNUM 7 /* (intlevel 1) */
+#define XCHAL_INT10_EXTNUM 8 /* (intlevel 1) */
+#define XCHAL_INT12_EXTNUM 9 /* (intlevel 1) */
+#define XCHAL_INT13_EXTNUM 10 /* (intlevel 1) */
+#define XCHAL_INT14_EXTNUM 11 /* (intlevel 7) */
+#define XCHAL_INT17_EXTNUM 12 /* (intlevel 1) */
+#define XCHAL_INT18_EXTNUM 13 /* (intlevel 1) */
+#define XCHAL_INT19_EXTNUM 14 /* (intlevel 2) */
+#define XCHAL_INT20_EXTNUM 15 /* (intlevel 2) */
+#define XCHAL_INT21_EXTNUM 16 /* (intlevel 2) */
+#define XCHAL_INT22_EXTNUM 17 /* (intlevel 3) */
+#define XCHAL_INT23_EXTNUM 18 /* (intlevel 3) */
+#define XCHAL_INT24_EXTNUM 19 /* (intlevel 4) */
+#define XCHAL_INT25_EXTNUM 20 /* (intlevel 4) */
+#define XCHAL_INT26_EXTNUM 21 /* (intlevel 5) */
+#define XCHAL_INT27_EXTNUM 22 /* (intlevel 3) */
+#define XCHAL_INT28_EXTNUM 23 /* (intlevel 4) */
+#define XCHAL_INT30_EXTNUM 24 /* (intlevel 4) */
+#define XCHAL_INT31_EXTNUM 25 /* (intlevel 5) */
+
+/****************************************************************************
+ * EXCEPTIONS and VECTORS
+ ****************************************************************************/
+
+#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
+ * number: 1 == XEA1 (old)
+ * 2 == XEA2 (new)
+ * 0 == XEAX (extern) or TX
+ */
+
+#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
+#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
+#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
+#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
+#define XCHAL_HAVE_HALT 0 /* halt architecture option */
+#define XCHAL_HAVE_BOOTLOADER 0 /* boot loader (for TX) */
+#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
+#define XCHAL_HAVE_VECTOR_SELECT 1 /* relocatable vectors */
+#define XCHAL_HAVE_VECBASE 1 /* relocatable vectors */
+#define XCHAL_VECBASE_RESET_VADDR 0x40000000 /* VECBASE reset value */
+#define XCHAL_VECBASE_RESET_PADDR 0x40000000
+#define XCHAL_RESET_VECBASE_OVERLAP 0
+
+#define XCHAL_RESET_VECTOR0_VADDR 0x50000000
+#define XCHAL_RESET_VECTOR0_PADDR 0x50000000
+#define XCHAL_RESET_VECTOR1_VADDR 0x40000400
+#define XCHAL_RESET_VECTOR1_PADDR 0x40000400
+#define XCHAL_RESET_VECTOR_VADDR 0x40000400
+#define XCHAL_RESET_VECTOR_PADDR 0x40000400
+#define XCHAL_USER_VECOFS 0x00000340
+#define XCHAL_USER_VECTOR_VADDR 0x40000340
+#define XCHAL_USER_VECTOR_PADDR 0x40000340
+#define XCHAL_KERNEL_VECOFS 0x00000300
+#define XCHAL_KERNEL_VECTOR_VADDR 0x40000300
+#define XCHAL_KERNEL_VECTOR_PADDR 0x40000300
+#define XCHAL_DOUBLEEXC_VECOFS 0x000003C0
+#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400003C0
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400003C0
+#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
+#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
+#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
+#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
+#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
+#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
+#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
+#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
+#define XCHAL_INTLEVEL2_VECOFS 0x00000180
+#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000180
+#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000180
+#define XCHAL_INTLEVEL3_VECOFS 0x000001C0
+#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x400001C0
+#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x400001C0
+#define XCHAL_INTLEVEL4_VECOFS 0x00000200
+#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000200
+#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000200
+#define XCHAL_INTLEVEL5_VECOFS 0x00000240
+#define XCHAL_INTLEVEL5_VECTOR_VADDR 0x40000240
+#define XCHAL_INTLEVEL5_VECTOR_PADDR 0x40000240
+#define XCHAL_INTLEVEL6_VECOFS 0x00000280
+#define XCHAL_INTLEVEL6_VECTOR_VADDR 0x40000280
+#define XCHAL_INTLEVEL6_VECTOR_PADDR 0x40000280
+#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL6_VECOFS
+#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL6_VECTOR_VADDR
+#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL6_VECTOR_PADDR
+#define XCHAL_NMI_VECOFS 0x000002C0
+#define XCHAL_NMI_VECTOR_VADDR 0x400002C0
+#define XCHAL_NMI_VECTOR_PADDR 0x400002C0
+#define XCHAL_INTLEVEL7_VECOFS XCHAL_NMI_VECOFS
+#define XCHAL_INTLEVEL7_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
+
+/****************************************************************************
+ * DEBUG MODULE
+ ****************************************************************************/
+
+/* Misc */
+
+#define XCHAL_HAVE_DEBUG_ERI 1 /* ERI to debug module */
+#define XCHAL_HAVE_DEBUG_APB 0 /* APB to debug module */
+#define XCHAL_HAVE_DEBUG_JTAG 1 /* JTAG to debug module */
+
+/* On-Chip Debug (OCD) */
+
+#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
+#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
+#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
+#define XCHAL_HAVE_OCD_DIR_ARRAY 0 /* faster OCD option (to LX4) */
+#define XCHAL_HAVE_OCD_LS32DDR 1 /* L32DDR/S32DDR (faster OCD) */
+
+/* TRAX (in core) */
+#define XCHAL_HAVE_TRAX 1 /* TRAX in debug module */
+#define XCHAL_TRAX_MEM_SIZE 16384 /* TRAX memory size in bytes */
+#define XCHAL_TRAX_MEM_SHAREABLE 1 /* start/end regs; ready sig. */
+#define XCHAL_TRAX_ATB_WIDTH 0 /* ATB width (bits), 0=no ATB */
+#define XCHAL_TRAX_TIME_WIDTH 0 /* timestamp bitwidth, 0=none */
+
+/* Perf counters */
+
+#define XCHAL_NUM_PERF_COUNTERS 2 /* performance counters */
+
+/****************************************************************************
+ * MMU
+ ****************************************************************************/
+
+/* See core-matmap.h header file for more details. */
+
+#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
+#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
+#define XCHAL_SPANNING_WAY 0 /* TLB spanning way number */
+#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
+#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
+#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
+#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
+#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
+ * [autorefill] and protection)
+ * usable for an MMU-based OS
+ */
+
+/* If none of the above last 5 are set, it's a custom TLB configuration. */
+
+#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
+#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
+#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
+
+/****************************************************************************
+ * MPU
+ ****************************************************************************/
+
+#define XCHAL_HAVE_MPU 0
+#define XCHAL_MPU_ENTRIES 0
+
+#define XCHAL_MPU_ALIGN_REQ 1 /* MPU requires alignment of entries to background map */
+#define XCHAL_MPU_BACKGROUND_ENTRIES 0 /* number of entries in bg map*/
+#define XCHAL_MPU_BG_CACHEADRDIS 0 /* default CACHEADRDIS for bg */
+
+#define XCHAL_MPU_ALIGN_BITS 0
+#define XCHAL_MPU_ALIGN 0
+
+#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
+
+#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_CORE_ISA_H */
diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h
new file mode 100644
index 0000000..864010f
--- /dev/null
+++ b/arch/xtensa/include/esp32s3/irq.h
@@ -0,0 +1,463 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32S3_INT_PRIO_DEF 1
+
+/* Interrupt Matrix
+ *
+ * The Interrupt Matrix embedded in the ESP32-S3 independently allocates
+ * peripheral interrupt sources to the two CPUs’ peripheral interrupts, to
+ * timely inform CPU0 or CPU1 to process the interrupts once the interrupt
+ * signals are generated.
+ * Peripheral interrupt sources must be routed to CPU0/CPU1 peripheral
+ * interrupts via this interrupt matrix due to the following considerations:
+ * - ESP32-S3 has 99 peripheral interrupt sources. To map them to 32 CPU0
+ * interrupts or 32 CPU1 interrupts, this matrix is needed.
+ * - Through this matrix, one peripheral interrupt source can be mapped to
+ * multiple CPU0 interrupts or CPU1 interrupts according to application
+ * requirements.
+ *
+ * Features:
+ * - Accept 99 peripheral interrupt sources as input.
+ * - Generate 26 peripheral interrupts to CPU0 and 26 peripheral interrupts
+ * to CPU1 as output. Note that the remaining 6 CPU0 interrupts and 6 CPU1
+ * interrupts are internal interrupts.
+ * - Support disabling CPU non-maskable interrupt (NMI) sources.
+ * - Support querying current interrupt status of peripheral interrupt
+ * sources.
+ */
+
+#define ESP32S3_PERIPH_MAC 0
+#define ESP32S3_PERIPH_MAC_NMI 1
+#define ESP32S3_PERIPH_PWR 2
+#define ESP32S3_PERIPH_BB 3
+#define ESP32S3_PERIPH_BT_MAC 4
+#define ESP32S3_PERIPH_BT_BB 5
+#define ESP32S3_PERIPH_BT_BB_NMI 6
+#define ESP32S3_PERIPH_RWBT 7
+#define ESP32S3_PERIPH_RWBLE 8
+#define ESP32S3_PERIPH_RWBT_NMI 9
+
+/* RESERVED interrupts: 12, 13, 15, 18, 19 */
+
+#define ESP32S3_PERIPH_RWBLE_NMI 10
+#define ESP32S3_PERIPH_I2C_MST 11
+#define ESP32S3_PERIPH_UHCI0 14
+#define ESP32S3_PERIPH_GPIO_INT_CPU 16
+#define ESP32S3_PERIPH_GPIO_INT_CPU_NMI 17
+
+/* RESERVED interrupts: 23 */
+
+#define ESP32S3_PERIPH_SPI1 20
+#define ESP32S3_PERIPH_SPI2 21
+#define ESP32S3_PERIPH_SPI3 22
+#define ESP32S3_PERIPH_LCD_CAM 24
+#define ESP32S3_PERIPH_I2S0 25
+#define ESP32S3_PERIPH_I2S1 26
+#define ESP32S3_PERIPH_UART0 27
+#define ESP32S3_PERIPH_UART1 28
+#define ESP32S3_PERIPH_UART2 29
+
+/* RESERVED interrupts: 33, 34 */
+
+#define ESP32S3_PERIPH_SDIO_HOST 30
+#define ESP32S3_PERIPH_PWM0 31
+#define ESP32S3_PERIPH_PWM1 32
+#define ESP32S3_PERIPH_LEDC 35
+#define ESP32S3_PERIPH_EFUSE 36
+#define ESP32S3_PERIPH_CAN 37
+#define ESP32S3_PERIPH_USB 38
+#define ESP32S3_PERIPH_RTC_CORE 39
+
+/* RESERVED interrupts: 44, 45, 46, 47, 48, 49 */
+
+#define ESP32S3_PERIPH_RMT 40
+#define ESP32S3_PERIPH_PCNT 41
+#define ESP32S3_PERIPH_I2C_EXT0 42
+#define ESP32S3_PERIPH_I2C_EXT1 43
+
+#define ESP32S3_PERIPH_TG_T0_LEVEL 50
+#define ESP32S3_PERIPH_TG_T1_LEVEL 51
+#define ESP32S3_PERIPH_TG_WDT_LEVEL 52
+#define ESP32S3_PERIPH_TG1_T0_LEVEL 53
+#define ESP32S3_PERIPH_TG1_T1_LEVEL 54
+#define ESP32S3_PERIPH_TG1_WDT_LEVEL 55
+#define ESP32S3_PERIPH_CACHE_IA 56
+#define ESP32S3_PERIPH_SYSTIMER_TARGET0 57
+#define ESP32S3_PERIPH_SYSTIMER_TARGET1 58
+#define ESP32S3_PERIPH_SYSTIMER_TARGET2 59
+
+#define ESP32S3_PERIPH_SPI_MEM_REJECT 60
+#define ESP32S3_PERIPH_DCACHE_PRELOAD 61
+#define ESP32S3_PERIPH_ICACHE_PRELOAD 62
+#define ESP32S3_PERIPH_DCACHE_SYNC 63
+#define ESP32S3_PERIPH_ICACHE_SYNC 64
+#define ESP32S3_PERIPH_APB_ADC 65
+#define ESP32S3_PERIPH_DMA_IN_CH0 66
+#define ESP32S3_PERIPH_DMA_IN_CH1 67
+#define ESP32S3_PERIPH_DMA_IN_CH2 68
+#define ESP32S3_PERIPH_DMA_IN_CH3 69
+
+#define ESP32S3_PERIPH_DMA_IN_CH4 70
+#define ESP32S3_PERIPH_DMA_OUT_CH0 71
+#define ESP32S3_PERIPH_DMA_OUT_CH1 72
+#define ESP32S3_PERIPH_DMA_OUT_CH2 73
+#define ESP32S3_PERIPH_DMA_OUT_CH3 74
+#define ESP32S3_PERIPH_DMA_OUT_CH4 75
+#define ESP32S3_PERIPH_RSA 76
+#define ESP32S3_PERIPH_AES 77
+#define ESP32S3_PERIPH_SHA 78
+#define ESP32S3_PERIPH_INT_FROM_CPU0 79
+
+#define ESP32S3_PERIPH_INT_FROM_CPU1 80
+#define ESP32S3_PERIPH_INT_FROM_CPU2 81
+#define ESP32S3_PERIPH_INT_FROM_CPU3 82
+#define ESP32S3_PERIPH_ASSIST_DEBUG 83
+#define ESP32S3_PERIPH_DMA_APB_PMS_MONITOR_VIOLATE 84
+#define ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE 85
+#define ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE 86
+#define ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE 87
+#define ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE 88
+#define ESP32S3_PERIPH_CORE_1_IRAM0_PMS_MONITOR_VIOLATE 89
+
+#define ESP32S3_PERIPH_CORE_1_DRAM0_PMS_MONITOR_VIOLATE 90
+#define ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE 91
+#define ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE 92
+#define ESP32S3_PERIPH_BACKUP_PMS_VIOLATE 93
+#define ESP32S3_PERIPH_CACHE_CORE0_ACS 94
+#define ESP32S3_PERIPH_CACHE_CORE1_ACS 95
+#define ESP32S3_PERIPH_USB_DEVICE 96
+#define ESP32S3_PERIPH_PERIPH_BACKUP 97
+#define ESP32S3_PERIPH_DMA_EXTMEM_REJECT 98
+
+/* Total number of peripherals */
+
+#define ESP32S3_NPERIPHERALS 99
+
+/* Exceptions
+ *
+ * IRAM Offset Description
+ * 0x0000 Windows
+ * 0x0180 Level 2 interrupt
+ * 0x01c0 Level 3 interrupt
+ * 0x0200 Level 4 interrupt
+ * 0x0240 Level 5 interrupt
+ * 0x0280 Debug exception
+ * 0x02c0 NMI exception
+ * 0x0300 Kernel exception
+ * 0x0340 User exception
+ * 0x03c0 Double exception
+ */
+
+/* IRQ numbers for internal interrupts that are dispatched like peripheral
+ * interrupts.
+ */
+
+#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */
+#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */
+#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */
+#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */
+
+#define XTENSA_NIRQ_INTERNAL 4 /* Number of dispatch internal interrupts */
+#define XTENSA_IRQ_FIRSTPERIPH 4 /* First peripheral IRQ number */
+
+/* IRQ numbers for peripheral interrupts coming through the Interrupt
+ * Matrix.
+ */
+
+#define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH)
+#define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH)
+
+#define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC)
+#define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI)
+#define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR)
+#define ESP32S3_IRQ_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
+#define ESP32S3_IRQ_BT_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BT_MAC)
+#define ESP32S3_IRQ_BT_BB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB)
+#define ESP32S3_IRQ_BT_BB_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BB_NMI)
+#define ESP32S3_IRQ_RWBT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT)
+#define ESP32S3_IRQ_RWBLE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE)
+#define ESP32S3_IRQ_RWBT_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBT_NMI)
+
+#define ESP32S3_IRQ_RWBLE_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RWBLE_NMI)
+#define ESP32S3_IRQ_I2C_MST (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_MST)
+#define ESP32S3_IRQ_UHCI0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UHCI0)
+#define ESP32S3_IRQ_GPIO_INT_CPU (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_GPIO_INT_CPU)
+#define ESP32S3_IRQ_GPIO_INT_CPU_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_GPIO_INT_CPU_NMI)
+
+#define ESP32S3_IRQ_SPI1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI1)
+#define ESP32S3_IRQ_SPI2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI2)
+#define ESP32S3_IRQ_SPI3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI3)
+#define ESP32S3_IRQ_LCD_CAM (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_LCD_CAM)
+#define ESP32S3_IRQ_I2S0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2S0)
+#define ESP32S3_IRQ_I2S1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2S1)
+#define ESP32S3_IRQ_UART0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART0)
+#define ESP32S3_IRQ_UART1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART1)
+#define ESP32S3_IRQ_UART2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_UART2)
+
+#define ESP32S3_IRQ_SDIO_HOST (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SDIO_HOST)
+#define ESP32S3_IRQ_PWM0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWM0)
+
+#define ESP32S3_IRQ_SREG0 ESP32S3_IRQ_MAC
+#define ESP32S3_NIRQS_SREG0 32
+
+#define ESP32S3_IRQ_PWM1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWM1)
+#define ESP32S3_IRQ_LEDC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_LEDC)
+#define ESP32S3_IRQ_EFUSE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_EFUSE)
+#define ESP32S3_IRQ_CAN (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CAN)
+#define ESP32S3_IRQ_USB (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_USB)
+#define ESP32S3_IRQ_RTC_CORE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RTC_CORE)
+
+#define ESP32S3_IRQ_RMT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RMT)
+#define ESP32S3_IRQ_PCNT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PCNT)
+#define ESP32S3_IRQ_I2C_EXT0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_EXT0)
+#define ESP32S3_IRQ_I2C_EXT1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_I2C_EXT1)
+
+#define ESP32S3_IRQ_TG_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_T0_LEVEL)
+#define ESP32S3_IRQ_TG_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_T1_LEVEL)
+#define ESP32S3_IRQ_TG_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG_WDT_LEVEL)
+#define ESP32S3_IRQ_TG1_T0_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_T0_LEVEL)
+#define ESP32S3_IRQ_TG1_T1_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_T1_LEVEL)
+#define ESP32S3_IRQ_TG1_WDT_LEVEL (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_TG1_WDT_LEVEL)
+#define ESP32S3_IRQ_CACHE_IA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_IA)
+#define ESP32S3_IRQ_SYSTIMER_TARGET0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET0)
+#define ESP32S3_IRQ_SYSTIMER_TARGET1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET1)
+#define ESP32S3_IRQ_SYSTIMER_TARGET2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SYSTIMER_TARGET2)
+
+#define ESP32S3_IRQ_SPI_MEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SPI_MEM_REJECT)
+#define ESP32S3_IRQ_DCACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DCACHE_PRELOAD)
+#define ESP32S3_IRQ_ICACHE_PRELOAD (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ICACHE_PRELOAD)
+#define ESP32S3_IRQ_DCACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DCACHE_SYNC)
+
+#define ESP32S3_IRQ_SREG1 ESP32S3_IRQ_PWM1
+#define ESP32S3_NIRQS_SREG1 32
+
+#define ESP32S3_IRQ_ICACHE_SYNC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ICACHE_SYNC)
+#define ESP32S3_IRQ_APB_ADC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_APB_ADC)
+#define ESP32S3_IRQ_DMA_IN_CH0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH0)
+#define ESP32S3_IRQ_DMA_IN_CH1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH1)
+#define ESP32S3_IRQ_DMA_IN_CH2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH2)
+#define ESP32S3_IRQ_DMA_IN_CH3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH3)
+
+#define ESP32S3_IRQ_DMA_IN_CH4 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_IN_CH4)
+#define ESP32S3_IRQ_DMA_OUT_CH0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH0)
+#define ESP32S3_IRQ_DMA_OUT_CH1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH1)
+#define ESP32S3_IRQ_DMA_OUT_CH2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH2)
+#define ESP32S3_IRQ_DMA_OUT_CH3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH3)
+#define ESP32S3_IRQ_DMA_OUT_CH4 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_OUT_CH4)
+#define ESP32S3_IRQ_RSA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_RSA)
+#define ESP32S3_IRQ_AES (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_AES)
+#define ESP32S3_IRQ_SHA (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_SHA)
+#define ESP32S3_IRQ_INT_FROM_CPU0 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU0)
+
+#define ESP32S3_IRQ_INT_FROM_CPU1 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU1)
+#define ESP32S3_IRQ_INT_FROM_CPU2 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU2)
+#define ESP32S3_IRQ_INT_FROM_CPU3 (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_INT_FROM_CPU3)
+#define ESP32S3_IRQ_ASSIST_DEBUG (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_ASSIST_DEBUG)
+#define ESP32S3_IRQ_DMA_APB_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_APB_PMS_MONITOR_VIOLATE)
+#define ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE)
+#define ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE)
+#define ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE)
+#define ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE)
+#define ESP32S3_IRQ_CORE_1_IRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_IRAM0_PMS_MONITOR_VIOLATE)
+
+#define ESP32S3_IRQ_CORE_1_DRAM0_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_DRAM0_PMS_MONITOR_VIOLATE)
+#define ESP32S3_IRQ_CORE_1_PIF_PMS_MONITOR_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE)
+#define ESP32S3_IRQ_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE)
+#define ESP32S3_IRQ_BACKUP_PMS_VIOLATE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_BACKUP_PMS_VIOLATE)
+#define ESP32S3_IRQ_CACHE_CORE0_ACS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_CORE0_ACS)
+#define ESP32S3_IRQ_CACHE_CORE1_ACS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_CACHE_CORE1_ACS)
+
+#define ESP32S3_IRQ_SREG2 ESP32S3_IRQ_ICACHE_SYNC
+#define ESP32S3_NIRQS_SREG2 32
+
+#define ESP32S3_IRQ_USB_DEVICE (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_USB_DEVICE)
+#define ESP32S3_IRQ_PERIPH_BACKUP (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PERIPH_BACKUP)
+#define ESP32S3_IRQ_DMA_EXTMEM_REJECT (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_DMA_EXTMEM_REJECT)
+
+#define ESP32S3_IRQ_SREG3 ESP32S3_IRQ_USB_DEVICE
+#define ESP32S3_NIRQS_SREG3 3
+
+#define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS
+
+/* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched
+ * as a second level of decoding: The first level dispatches to the GPIO
+ * interrupt handler. The second to the decoded GPIO interrupt handler.
+ */
+
+#ifdef CONFIG_ESP32S3_GPIO_IRQ
+# define ESP32S3_NIRQ_GPIO 40
+# define ESP32S3_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH)
+# define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1)
+# define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ)
+# define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ)
+#else
+# define ESP32S3_NIRQ_GPIO 0
+#endif
+
+/* Total number of interrupts */
+
+#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO)
+
+/* Xtensa CPU Interrupts.
+ *
+ * Each of the two CPUs (PRO and APP) have 32 interrupts each, of which
+ * 26 can be mapped to peripheral interrupts:
+ *
+ * Level triggered peripherals (21 total):
+ * 0-5, 8-9, 12-13, 17-18 - Priority 1
+ * 19-21 - Priority 2
+ * 23, 27 - Priority 3
+ * 24-25 - Priority 4
+ * 26, 31 - Priority 5
+ * Edge triggered peripherals (4 total):
+ * 10 - Priority 1
+ * 22 - Priority 3
+ * 28, 30 - Priority 4
+ * NMI (1 total):
+ * 14 - NMI
+ *
+ * CPU peripheral interrupts can be a assigned to a CPU interrupt using the
+ * PRO_*_MAP_REG or APP_*_MAP_REG. There are a pair of these registers for
+ * each peripheral source. Multiple peripheral interrupt sources can be
+ * mapped to the same CPU interrupt.
+ *
+ * The remaining, six, internal CPU interrupts are:
+ *
+ * 6 Timer0 - Priority 1
+ * 7 Software - Priority 1
+ * 11 Profiling - Priority 3
+ * 15 Timer1 - Priority 3
+ * 16 Timer2 - Priority 5
+ * 29 Software - Priority 3
+ *
+ * A peripheral interrupt can be disabled
+ */
+
+#define ESP32S3_CPUINT_LEVELPERIPH_0 0
+#define ESP32S3_CPUINT_LEVELPERIPH_1 1
+#define ESP32S3_CPUINT_LEVELPERIPH_2 2
+#define ESP32S3_CPUINT_LEVELPERIPH_3 3
+#define ESP32S3_CPUINT_LEVELPERIPH_4 4
+#define ESP32S3_CPUINT_LEVELPERIPH_5 5
+#define ESP32S3_CPUINT_LEVELPERIPH_6 8
+#define ESP32S3_CPUINT_LEVELPERIPH_7 9
+#define ESP32S3_CPUINT_LEVELPERIPH_8 12
+#define ESP32S3_CPUINT_LEVELPERIPH_9 13
+#define ESP32S3_CPUINT_LEVELPERIPH_10 17
+#define ESP32S3_CPUINT_LEVELPERIPH_11 18
+#define ESP32S3_CPUINT_LEVELPERIPH_12 19
+#define ESP32S3_CPUINT_LEVELPERIPH_13 20
+#define ESP32S3_CPUINT_LEVELPERIPH_14 21
+#define ESP32S3_CPUINT_LEVELPERIPH_15 23
+#define ESP32S3_CPUINT_LEVELPERIPH_16 24
+#define ESP32S3_CPUINT_LEVELPERIPH_17 25
+#define ESP32S3_CPUINT_LEVELPERIPH_18 26
+#define ESP32S3_CPUINT_LEVELPERIPH_19 27
+#define ESP32S3_CPUINT_LEVELPERIPH_20 31
+
+#define ESP32S3_CPUINT_NLEVELPERIPHS 21
+#define ESP32S3_CPUINT_LEVELSET 0x8fbe333f
+
+#define ESP32S3_CPUINT_EDGEPERIPH_0 10
+#define ESP32S3_CPUINT_EDGEPERIPH_1 22
+#define ESP32S3_CPUINT_EDGEPERIPH_2 28
+#define ESP32S3_CPUINT_EDGEPERIPH_3 30
+
+#define ESP32S3_CPUINT_NEDGEPERIPHS 4
+#define ESP32S3_CPUINT_EDGESET 0x50400400
+
+#define ESP32S3_CPUINT_NNMIPERIPHS 1
+#define ESP32S3_CPUINT_NMISET 0x00004000
+
+#define ESP32S3_CPUINT_MAC 0
+#define ESP32S3_CPUINT_TIMER0 6
+#define ESP32S3_CPUINT_SOFTWARE0 7
+#define ESP32S3_CPUINT_PROFILING 11
+#define ESP32S3_CPUINT_TIMER1 15
+#define ESP32S3_CPUINT_TIMER2 16
+#define ESP32S3_CPUINT_SOFTWARE1 29
+
+#define ESP32S3_CPUINT_NINTERNAL 6
+
+#define ESP32S3_NCPUINTS 32
+#define ESP32S3_CPUINT_MAX (ESP32S3_NCPUINTS - 1)
+#define ESP32S3_CPUINT_PERIPHSET 0xdffe773f
+#define ESP32S3_CPUINT_INTERNALSET 0x200188c0
+
+/* Priority 1: 0-10, 12-13, 17-18 (15)
+ * Priority 2: 19-21 (3)
+ * Priority 3: 11, 15, 22-23, 27, 29 (6)
+ * Priority 4: 24-25, 28, 30 (4)
+ * Priority 5: 16, 26, 31 (3)
+ * Priority NMI: 14 (1)
+ */
+
+#define ESP32S3_INTPRI1_MASK 0x000637ff
+#define ESP32S3_INTPRI2_MASK 0x00380000
+#define ESP32S3_INTPRI3_MASK 0x28c08800
+#define ESP32S3_INTPRI4_MASK 0x53000000
+#define ESP32S3_INTPRI5_MASK 0x84010000
+#define ESP32S3_INTNMI_MASK 0x00004000
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_IRQ_H */
diff --git a/arch/xtensa/include/esp32s3/tie-asm.h b/arch/xtensa/include/esp32s3/tie-asm.h
new file mode 100644
index 0000000..86305f9
--- /dev/null
+++ b/arch/xtensa/include/esp32s3/tie-asm.h
@@ -0,0 +1,433 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie-asm.h
+ * Compile-time HAL assembler definitions dependent on CORE & TIE
+ * configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file contains assembly-language definitions (assembly
+ * macros, etc.) for this specific Xtensa processor's TIE extensions
+ * and options. It is customized to this Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H
+
+/* Selection parameter values for save-area save/restore macros: */
+/* Option vs. TIE: */
+#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
+#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
+#define XTHAL_SAS_ANYOT 0x0003 /* both of the above */
+/* Whether used automatically by compiler: */
+#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
+#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
+#define XTHAL_SAS_ANYCC 0x000C /* both of the above */
+/* ABI handling across function calls: */
+#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
+#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
+#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
+#define XTHAL_SAS_ANYABI 0x0070 /* all of the above three */
+/* Misc */
+#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
+#define XTHAL_SAS3(optie,ccuse,abi) ( ((optie) & XTHAL_SAS_ANYOT) \
+ | ((ccuse) & XTHAL_SAS_ANYCC) \
+ | ((abi) & XTHAL_SAS_ANYABI) )
+
+
+ /*
+ * Macro to store all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters:
+ * continue If macro invoked as part of a larger store sequence, set to 1
+ * if this is not the first in the sequence. Defaults to 0.
+ * ofs Offset from start of larger sequence (from value of first ptr
+ * in sequence) at which to store. Defaults to next available space
+ * (or 0 if <continue> is 0).
+ * select Select what category(ies) of registers to store, as a bitmask
+ * (see XTHAL_SAS_xxx constants). Defaults to all registers.
+ * alloc Select what category(ies) of registers to allocate; if any
+ * category is selected here that is not in <select>, space for
+ * the corresponding registers is skipped without doing any store.
+ */
+ .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Optional global registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ rur.THREADPTR \at1 // threadptr option
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .endif
+ // Optional caller-saved registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ rsr.ACCLO \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rsr.ACCHI \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .endif
+ // Optional caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ rsr.BR \at1 // boolean option
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rsr.SCOMPARE1 \at1 // conditional store option
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ rsr.M0 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+8
+ rsr.M1 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+12
+ rsr.M2 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+16
+ rsr.M3 \at1 // MAC16 option
+ s32i \at1, \ptr, .Lxchal_ofs_+20
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .endif
+ .endm // xchal_ncp_store
+
+ /*
+ * Macro to load all non-coprocessor (extra) custom TIE and optional state
+ * (not including zero-overhead loop registers).
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_NCP_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters:
+ * continue If macro invoked as part of a larger load sequence, set to 1
+ * if this is not the first in the sequence. Defaults to 0.
+ * ofs Offset from start of larger sequence (from value of first ptr
+ * in sequence) at which to load. Defaults to next available space
+ * (or 0 if <continue> is 0).
+ * select Select what category(ies) of registers to load, as a bitmask
+ * (see XTHAL_SAS_xxx constants). Defaults to all registers.
+ * alloc Select what category(ies) of registers to allocate; if any
+ * category is selected here that is not in <select>, space for
+ * the corresponding registers is skipped without doing any load.
+ */
+ .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Optional global registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\select)
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wur.THREADPTR \at1 // threadptr option
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1016, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
+ .endif
+ // Optional caller-saved registers used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wsr.ACCLO \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wsr.ACCHI \at1 // MAC16 option
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 1012, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 8
+ .endif
+ // Optional caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wsr.BR \at1 // boolean option
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wsr.SCOMPARE1 \at1 // conditional store option
+ l32i \at1, \ptr, .Lxchal_ofs_+8
+ wsr.M0 \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+12
+ wsr.M1 \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+16
+ wsr.M2 \at1 // MAC16 option
+ l32i \at1, \ptr, .Lxchal_ofs_+20
+ wsr.M3 \at1 // MAC16 option
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .elseif ((XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 996, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 24
+ .endif
+ .endm // xchal_ncp_load
+
+
+#define XCHAL_NCP_NUM_ATMPS 1
+
+ /*
+ * Macro to store the state of TIE coprocessor FPU.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_store.
+ */
+#define xchal_cp_FPU_store xchal_cp0_store
+ .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ rur.FCR \at1 // ureg 232
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rur.FSR \at1 // ureg 233
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ ssi f0, \ptr, .Lxchal_ofs_+8
+ ssi f1, \ptr, .Lxchal_ofs_+12
+ ssi f2, \ptr, .Lxchal_ofs_+16
+ ssi f3, \ptr, .Lxchal_ofs_+20
+ ssi f4, \ptr, .Lxchal_ofs_+24
+ ssi f5, \ptr, .Lxchal_ofs_+28
+ ssi f6, \ptr, .Lxchal_ofs_+32
+ ssi f7, \ptr, .Lxchal_ofs_+36
+ ssi f8, \ptr, .Lxchal_ofs_+40
+ ssi f9, \ptr, .Lxchal_ofs_+44
+ ssi f10, \ptr, .Lxchal_ofs_+48
+ ssi f11, \ptr, .Lxchal_ofs_+52
+ ssi f12, \ptr, .Lxchal_ofs_+56
+ ssi f13, \ptr, .Lxchal_ofs_+60
+ ssi f14, \ptr, .Lxchal_ofs_+64
+ ssi f15, \ptr, .Lxchal_ofs_+68
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .endif
+ .endm // xchal_cp0_store
+
+ /*
+ * Macro to load the state of TIE coprocessor FPU.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 4 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP0_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_load.
+ */
+#define xchal_cp_FPU_load xchal_cp0_load
+ .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wur.FCR \at1 // ureg 232
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wur.FSR \at1 // ureg 233
+ lsi f0, \ptr, .Lxchal_ofs_+8
+ lsi f1, \ptr, .Lxchal_ofs_+12
+ lsi f2, \ptr, .Lxchal_ofs_+16
+ lsi f3, \ptr, .Lxchal_ofs_+20
+ lsi f4, \ptr, .Lxchal_ofs_+24
+ lsi f5, \ptr, .Lxchal_ofs_+28
+ lsi f6, \ptr, .Lxchal_ofs_+32
+ lsi f7, \ptr, .Lxchal_ofs_+36
+ lsi f8, \ptr, .Lxchal_ofs_+40
+ lsi f9, \ptr, .Lxchal_ofs_+44
+ lsi f10, \ptr, .Lxchal_ofs_+48
+ lsi f11, \ptr, .Lxchal_ofs_+52
+ lsi f12, \ptr, .Lxchal_ofs_+56
+ lsi f13, \ptr, .Lxchal_ofs_+60
+ lsi f14, \ptr, .Lxchal_ofs_+64
+ lsi f15, \ptr, .Lxchal_ofs_+68
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 948, 4, 4
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
+ .endif
+ .endm // xchal_cp0_load
+
+#define XCHAL_CP0_NUM_ATMPS 1
+ /*
+ * Macro to store the state of TIE coprocessor cop_ai.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 16 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_store.
+ */
+#define xchal_cp_cop_ai_store xchal_cp3_store
+ .macro xchal_cp3_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ rur.ACCX_0 \at1 // ureg 0
+ s32i \at1, \ptr, .Lxchal_ofs_+0
+ rur.ACCX_1 \at1 // ureg 1
+ s32i \at1, \ptr, .Lxchal_ofs_+4
+ rur.QACC_H_0 \at1 // ureg 2
+ s32i \at1, \ptr, .Lxchal_ofs_+8
+ rur.QACC_H_1 \at1 // ureg 3
+ s32i \at1, \ptr, .Lxchal_ofs_+12
+ rur.QACC_H_2 \at1 // ureg 4
+ s32i \at1, \ptr, .Lxchal_ofs_+16
+ rur.QACC_H_3 \at1 // ureg 5
+ s32i \at1, \ptr, .Lxchal_ofs_+20
+ rur.QACC_H_4 \at1 // ureg 6
+ s32i \at1, \ptr, .Lxchal_ofs_+24
+ rur.QACC_L_0 \at1 // ureg 7
+ s32i \at1, \ptr, .Lxchal_ofs_+28
+ rur.QACC_L_1 \at1 // ureg 8
+ s32i \at1, \ptr, .Lxchal_ofs_+32
+ rur.QACC_L_2 \at1 // ureg 9
+ s32i \at1, \ptr, .Lxchal_ofs_+36
+ rur.QACC_L_3 \at1 // ureg 10
+ s32i \at1, \ptr, .Lxchal_ofs_+40
+ rur.QACC_L_4 \at1 // ureg 11
+ s32i \at1, \ptr, .Lxchal_ofs_+44
+ rur.SAR_BYTE \at1 // ureg 13
+ s32i \at1, \ptr, .Lxchal_ofs_+48
+ rur.FFT_BIT_WIDTH \at1 // ureg 14
+ s32i \at1, \ptr, .Lxchal_ofs_+52
+ rur.UA_STATE_0 \at1 // ureg 15
+ s32i \at1, \ptr, .Lxchal_ofs_+56
+ rur.UA_STATE_1 \at1 // ureg 16
+ s32i \at1, \ptr, .Lxchal_ofs_+60
+ rur.UA_STATE_2 \at1 // ureg 17
+ s32i \at1, \ptr, .Lxchal_ofs_+64
+ rur.UA_STATE_3 \at1 // ureg 18
+ s32i \at1, \ptr, .Lxchal_ofs_+68
+ st.qr q0, \ptr, .Lxchal_ofs_+80
+ st.qr q1, \ptr, .Lxchal_ofs_+96
+ st.qr q2, \ptr, .Lxchal_ofs_+112
+ addi \ptr, \ptr, 128
+ st.qr q3, \ptr, .Lxchal_ofs_+0
+ st.qr q4, \ptr, .Lxchal_ofs_+16
+ st.qr q5, \ptr, .Lxchal_ofs_+32
+ st.qr q6, \ptr, .Lxchal_ofs_+48
+ st.qr q7, \ptr, .Lxchal_ofs_+64
+ .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 80
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 208
+ .endif
+ .endm // xchal_cp3_store
+
+ /*
+ * Macro to load the state of TIE coprocessor cop_ai.
+ * Required parameters:
+ * ptr Save area pointer address register (clobbered)
+ * (register must contain a 16 byte aligned address).
+ * at1..at4 Four temporary address registers (first XCHAL_CP3_NUM_ATMPS
+ * registers are clobbered, the remaining are unused).
+ * Optional parameters are the same as for xchal_ncp_load.
+ */
+#define xchal_cp_cop_ai_load xchal_cp3_load
+ .macro xchal_cp3_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL alloc=0
+ xchal_sa_start \continue, \ofs
+ // Custom caller-saved registers not used by default by the compiler:
+ .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\select)
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ l32i \at1, \ptr, .Lxchal_ofs_+0
+ wur.ACCX_0 \at1 // ureg 0
+ l32i \at1, \ptr, .Lxchal_ofs_+4
+ wur.ACCX_1 \at1 // ureg 1
+ l32i \at1, \ptr, .Lxchal_ofs_+8
+ wur.QACC_H_0 \at1 // ureg 2
+ l32i \at1, \ptr, .Lxchal_ofs_+12
+ wur.QACC_H_1 \at1 // ureg 3
+ l32i \at1, \ptr, .Lxchal_ofs_+16
+ wur.QACC_H_2 \at1 // ureg 4
+ l32i \at1, \ptr, .Lxchal_ofs_+20
+ wur.QACC_H_3 \at1 // ureg 5
+ l32i \at1, \ptr, .Lxchal_ofs_+24
+ wur.QACC_H_4 \at1 // ureg 6
+ l32i \at1, \ptr, .Lxchal_ofs_+28
+ wur.QACC_L_0 \at1 // ureg 7
+ l32i \at1, \ptr, .Lxchal_ofs_+32
+ wur.QACC_L_1 \at1 // ureg 8
+ l32i \at1, \ptr, .Lxchal_ofs_+36
+ wur.QACC_L_2 \at1 // ureg 9
+ l32i \at1, \ptr, .Lxchal_ofs_+40
+ wur.QACC_L_3 \at1 // ureg 10
+ l32i \at1, \ptr, .Lxchal_ofs_+44
+ wur.QACC_L_4 \at1 // ureg 11
+ l32i \at1, \ptr, .Lxchal_ofs_+48
+ wur.SAR_BYTE \at1 // ureg 13
+ l32i \at1, \ptr, .Lxchal_ofs_+52
+ wur.FFT_BIT_WIDTH \at1 // ureg 14
+ l32i \at1, \ptr, .Lxchal_ofs_+56
+ wur.UA_STATE_0 \at1 // ureg 15
+ l32i \at1, \ptr, .Lxchal_ofs_+60
+ wur.UA_STATE_1 \at1 // ureg 16
+ l32i \at1, \ptr, .Lxchal_ofs_+64
+ wur.UA_STATE_2 \at1 // ureg 17
+ l32i \at1, \ptr, .Lxchal_ofs_+68
+ wur.UA_STATE_3 \at1 // ureg 18
+ ld.qr q0, \ptr, .Lxchal_ofs_+80
+ ld.qr q1, \ptr, .Lxchal_ofs_+96
+ ld.qr q2, \ptr, .Lxchal_ofs_+112
+ addi \ptr, \ptr, 128
+ ld.qr q3, \ptr, .Lxchal_ofs_+0
+ ld.qr q4, \ptr, .Lxchal_ofs_+16
+ ld.qr q5, \ptr, .Lxchal_ofs_+32
+ ld.qr q6, \ptr, .Lxchal_ofs_+48
+ ld.qr q7, \ptr, .Lxchal_ofs_+64
+ .set .Lxchal_pofs_, .Lxchal_pofs_ + 128
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 80
+ .elseif ((XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~(\alloc)) == 0
+ xchal_sa_align \ptr, 0, 0, 16, 16
+ .set .Lxchal_ofs_, .Lxchal_ofs_ + 208
+ .endif
+ .endm // xchal_cp3_load
+
+#define XCHAL_CP3_NUM_ATMPS 1
+#define XCHAL_SA_NUM_ATMPS 1
+
+ /* Empty macros for unconfigured coprocessors: */
+ .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp6_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp6_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
+ .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
+
+#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_ASM_H */
diff --git a/arch/xtensa/include/esp32s3/tie.h b/arch/xtensa/include/esp32s3/tie.h
new file mode 100644
index 0000000..2bfd92c
--- /dev/null
+++ b/arch/xtensa/include/esp32s3/tie.h
@@ -0,0 +1,209 @@
+/****************************************************************************
+ * arch/xtensa/include/esp32s3/tie.h
+ * Compile-time HAL definitions dependent on CORE & TIE configuration
+ *
+ * NOTE: This header file is not meant to be included directly.
+ *
+ * This header file describes this specific Xtensa processor's TIE extensions
+ * that extend basic Xtensa core functionality. It is customized to this
+ * Xtensa processor configuration.
+ *
+ * Customer ID=15128; Build=0x90f1f;
+ * Copyright (c) 1999-2021 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+#define __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H
+
+#define XCHAL_CP_NUM 2 /* number of coprocessors */
+#define XCHAL_CP_MAX 4 /* max CP ID + 1 (0 if none) */
+#define XCHAL_CP_MASK 0x09 /* bitmask of all CPs by ID */
+#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
+
+/* Basic parameters of each coprocessor: */
+#define XCHAL_CP0_NAME "FPU"
+#define XCHAL_CP0_IDENT FPU
+#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
+#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
+#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
+#define XCHAL_CP3_NAME "cop_ai"
+#define XCHAL_CP3_IDENT cop_ai
+#define XCHAL_CP3_SA_SIZE 208 /* size of state save area */
+#define XCHAL_CP3_SA_ALIGN 16 /* min alignment of save area */
+#define XCHAL_CP_ID_COP_AI 3 /* coprocessor ID (0..7) */
+
+/* Filler info for unassigned coprocessors, to simplify arrays etc: */
+#define XCHAL_CP1_SA_SIZE 0
+#define XCHAL_CP1_SA_ALIGN 1
+#define XCHAL_CP2_SA_SIZE 0
+#define XCHAL_CP2_SA_ALIGN 1
+#define XCHAL_CP4_SA_SIZE 0
+#define XCHAL_CP4_SA_ALIGN 1
+#define XCHAL_CP5_SA_SIZE 0
+#define XCHAL_CP5_SA_ALIGN 1
+#define XCHAL_CP6_SA_SIZE 0
+#define XCHAL_CP6_SA_ALIGN 1
+#define XCHAL_CP7_SA_SIZE 0
+#define XCHAL_CP7_SA_ALIGN 1
+
+/* Save area for non-coprocessor optional and custom (TIE) state: */
+#define XCHAL_NCP_SA_SIZE 36
+#define XCHAL_NCP_SA_ALIGN 4
+
+/* Total save area for optional and custom state (NCP + CPn): */
+#define XCHAL_TOTAL_SA_SIZE 336 /* with 16-byte align padding */
+#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
+
+/* Detailed contents of save areas.
+ * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
+ * before expanding the XCHAL_xxx_SA_LIST() macros.
+ *
+ * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
+ * dbnum,base,regnum,bitsz,gapsz,reset,x...)
+ *
+ * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
+ * ccused = set if used by compiler without special options or code
+ * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
+ * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
+ * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
+ * name = lowercase reg name (no quotes)
+ * galign = group byte alignment (power of 2) (galign >= align)
+ * align = register byte alignment (power of 2)
+ * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
+ * (not including any pad bytes required to galign this or next reg)
+ * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
+ * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
+ * regnum = reg index in regfile, or special/TIE-user reg number
+ * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
+ * gapsz = intervening bits, if bitsz bits not stored contiguously
+ * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
+ * reset = register reset value (or 0 if undefined at reset)
+ * x = reserved for future use (0 until then)
+ *
+ * To filter out certain registers, e.g. to expand only the non-global
+ * registers used by the compiler, you can do something like this:
+ *
+ * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
+ * #define SELCC0(p...)
+ * #define SELCC1(abikind,p...) SELAK##abikind(p)
+ * #define SELAK0(p...) REG(p)
+ * #define SELAK1(p...) REG(p)
+ * #define SELAK2(p...)
+ * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
+ * ...what you want to expand...
+ */
+
+#define XCHAL_NCP_SA_NUM 9
+#define XCHAL_NCP_SA_LIST(s) \
+ XCHAL_SA_REG(s,1,2,1,1, threadptr, 4, 4, 4,0x03E7, ur,231, 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1, acclo, 4, 4, 4,0x0210, sr,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,1,0,0,1, acchi, 4, 4, 4,0x0211, sr,17 , 8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, scompare1, 4, 4, 4,0x020C, sr,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m0, 4, 4, 4,0x0220, sr,32 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m1, 4, 4, 4,0x0221, sr,33 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m2, 4, 4, 4,0x0222, sr,34 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,0,1, m3, 4, 4, 4,0x0223, sr,35 , 32,0,0,0)
+
+#define XCHAL_CP0_SA_NUM 18
+#define XCHAL_CP0_SA_LIST(s) \
+ XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
+
+#define XCHAL_CP1_SA_NUM 0
+#define XCHAL_CP1_SA_LIST(s) /* empty */
+
+#define XCHAL_CP2_SA_NUM 0
+#define XCHAL_CP2_SA_LIST(s) /* empty */
+
+#define XCHAL_CP3_SA_NUM 26
+#define XCHAL_CP3_SA_LIST(s) \
+ XCHAL_SA_REG(s,0,0,1,0, accx_0,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, accx_1, 4, 4, 4,0x0301, ur,1 , 8,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_0, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_1, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_2, 4, 4, 4,0x0304, ur,4 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_3, 4, 4, 4,0x0305, ur,5 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_h_4, 4, 4, 4,0x0306, ur,6 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_0, 4, 4, 4,0x0307, ur,7 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_1, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_2, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_3, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, qacc_l_4, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, sar_byte, 4, 4, 4,0x030D, ur,13 , 4,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, fft_bit_width, 4, 4, 4,0x030E, ur,14 , 4,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_0, 4, 4, 4,0x030F, ur,15 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_1, 4, 4, 4,0x0310, ur,16 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_2, 4, 4, 4,0x0311, ur,17 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,1,0, ua_state_3, 4, 4, 4,0x0312, ur,18 , 32,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q0,16,16,16,0x1008, q,0 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q1,16,16,16,0x1009, q,1 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q2,16,16,16,0x100A, q,2 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q3,16,16,16,0x100B, q,3 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q4,16,16,16,0x100C, q,4 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q5,16,16,16,0x100D, q,5 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q6,16,16,16,0x100E, q,6 ,128,0,0,0) \
+ XCHAL_SA_REG(s,0,0,2,0, q7,16,16,16,0x100F, q,7 ,128,0,0,0)
+
+#define XCHAL_CP4_SA_NUM 0
+#define XCHAL_CP4_SA_LIST(s) /* empty */
+
+#define XCHAL_CP5_SA_NUM 0
+#define XCHAL_CP5_SA_LIST(s) /* empty */
+
+#define XCHAL_CP6_SA_NUM 0
+#define XCHAL_CP6_SA_LIST(s) /* empty */
+
+#define XCHAL_CP7_SA_NUM 0
+#define XCHAL_CP7_SA_LIST(s) /* empty */
+
+/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
+#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
+/* Byte length of instruction from its first byte, per FLIX. */
+#define XCHAL_BYTE0_FORMAT_LENGTHS \
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4,\
+ 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4, 3,3,3,3,3,3,3,3,2,2,2,2,2,2,4,4
+
+#endif /* __ARCH_XTENSA_INCLUDE_ESP32S3_TIE_H */
diff --git a/arch/xtensa/include/lx7/chip.h b/arch/xtensa/include/lx7/chip.h
new file mode 100644
index 0000000..ae85aa7
--- /dev/null
+++ b/arch/xtensa/include/lx7/chip.h
@@ -0,0 +1,62 @@
+/****************************************************************************
+ * arch/xtensa/include/lx7/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_INCLUDE_LX7_CHIP_H
+#define __ARCH_XTENSA_INCLUDE_LX7_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_INCLUDE_LX7_CHIP_H */
diff --git a/arch/xtensa/src/esp32s3/.gitignore b/arch/xtensa/src/esp32s3/.gitignore
new file mode 100644
index 0000000..2d7ab9d
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/.gitignore
@@ -0,0 +1 @@
+/esp-nuttx-bootloader
diff --git a/arch/xtensa/src/esp32s3/Bootloader.mk b/arch/xtensa/src/esp32s3/Bootloader.mk
new file mode 100644
index 0000000..7de5162
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/Bootloader.mk
@@ -0,0 +1,88 @@
+############################################################################
+# arch/xtensa/src/esp32s3/Bootloader.mk
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+ifeq ($(CONFIG_ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE),y)
+
+CHIPDIR = $(TOPDIR)/arch/xtensa/src/chip
+
+BOOTLOADER_SRCDIR = $(CHIPDIR)/esp-nuttx-bootloader
+BOOTLOADER_VERSION = main
+BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader
+BOOTLOADER_OUTDIR = out
+BOOTLOADER_CONFIG = $(CHIPDIR)/bootloader.conf
+
+$(BOOTLOADER_SRCDIR):
+ $(Q) git clone $(BOOTLOADER_URL) $(BOOTLOADER_SRCDIR) -b $(BOOTLOADER_VERSION)
+
+# Helpers for creating the configuration file
+
+cfg_en = echo "$(1)=y";
+cfg_val = echo "$(1)=$(2)";
+
+$(BOOTLOADER_CONFIG): $(TOPDIR)/.config
+ $(Q) echo "Creating Bootloader configuration"
+ $(Q) { \
+ $(if $(CONFIG_ESP32S3_FLASH_4M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_4MB)) \
+ $(if $(CONFIG_ESP32S3_FLASH_8M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_8MB)) \
+ $(if $(CONFIG_ESP32S3_FLASH_16M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHSIZE_16MB)) \
+ $(if $(CONFIG_ESP32S3_FLASH_MODE_DIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DIO)) \
+ $(if $(CONFIG_ESP32S3_FLASH_MODE_DOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_DOUT)) \
+ $(if $(CONFIG_ESP32S3_FLASH_MODE_QIO),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QIO)) \
+ $(if $(CONFIG_ESP32S3_FLASH_MODE_QOUT),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHMODE_QOUT)) \
+ $(if $(CONFIG_ESP32S3_FLASH_FREQ_120M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_120M)) \
+ $(if $(CONFIG_ESP32S3_FLASH_FREQ_80M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_80M)) \
+ $(if $(CONFIG_ESP32S3_FLASH_FREQ_40M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_40M)) \
+ $(if $(CONFIG_ESP32S3_FLASH_FREQ_20M),$(call cfg_en,CONFIG_ESPTOOLPY_FLASHFREQ_20M)) \
+ } > $(BOOTLOADER_CONFIG)
+ifeq ($(CONFIG_ESP32S3_APP_FORMAT_LEGACY),y)
+ $(Q) { \
+ $(call cfg_en,CONFIG_PARTITION_TABLE_CUSTOM) \
+ $(call cfg_val,CONFIG_PARTITION_TABLE_CUSTOM_FILENAME,\"partitions.csv\") \
+ $(call cfg_val,CONFIG_PARTITION_TABLE_OFFSET,$(CONFIG_ESP32S3_PARTITION_TABLE_OFFSET)) \
+ } >> $(BOOTLOADER_CONFIG)
+endif
+
+bootloader: $(BOOTLOADER_SRCDIR) $(BOOTLOADER_CONFIG)
+ $(Q) echo "Building Bootloader binaries"
+ $(Q) $(BOOTLOADER_SRCDIR)/build_idfboot.sh -c esp32s3 -s -f $(BOOTLOADER_CONFIG)
+ $(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/bootloader-esp32s3.bin,$(TOPDIR))
+ $(call COPYFILE,$(BOOTLOADER_SRCDIR)/$(BOOTLOADER_OUTDIR)/partition-table-esp32s3.bin,$(TOPDIR))
+
+clean_bootloader:
+ $(call DELDIR,$(BOOTLOADER_SRCDIR))
+ $(call DELFILE,$(BOOTLOADER_CONFIG))
+ $(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin)
+ $(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin)
+
+else ifeq ($(CONFIG_ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT),y)
+
+BOOTLOADER_VERSION = latest
+BOOTLOADER_URL = https://github.com/espressif/esp-nuttx-bootloader/releases/download/$(BOOTLOADER_VERSION)
+
+bootloader:
+ $(Q) echo "Downloading Bootloader binaries"
+ $(Q) curl -L $(BOOTLOADER_URL)/bootloader-esp32s3.bin -o $(TOPDIR)/bootloader-esp32s3.bin
+ $(Q) curl -L $(BOOTLOADER_URL)/partition-table-esp32s3.bin -o $(TOPDIR)/partition-table-esp32s3.bin
+
+clean_bootloader:
+ $(call DELFILE,$(TOPDIR)/bootloader-esp32s3.bin)
+ $(call DELFILE,$(TOPDIR)/partition-table-esp32s3.bin)
+
+endif
diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig
new file mode 100644
index 0000000..5753d57
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/Kconfig
@@ -0,0 +1,461 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_CHIP_ESP32S3
+
+comment "ESP32-S3 Configuration Options"
+
+choice
+ prompt "ESP32-S3 Chip Selection"
+ default ARCH_CHIP_ESP32S3WROOM1
+
+config ARCH_CHIP_ESP32S3WROOM1
+ bool "ESP32-S3-WROOM-1"
+ select ESP32S3_FLASH_4M
+ ---help---
+ Generic module with an embedded ESP32-S3.
+
+config ARCH_CHIP_ESP32S3WROOM2
+ bool "ESP32-S3-WROOM-2"
+ select ESP32S3_FLASH_16M
+ select ESP32S3_PSRAM_8M
+ ---help---
+ Generic module with an embedded ESP32-S3.
+
+config ARCH_CHIP_ESP32S3MINI1
+ bool "ESP32-S3-MINI-1"
+ select ESP32S3_FLASH_8M
+ ---help---
+ Generic module with an embedded ESP32-S3.
+
+endchoice # ESP32-S3 Chip Selection
+
+choice ESP32S3_DEFAULT_CPU_FREQ
+ prompt "CPU frequency"
+ default ESP32S3_DEFAULT_CPU_FREQ_240
+ ---help---
+ CPU frequency to be set on application startup.
+
+ config ESP32S3_DEFAULT_CPU_FREQ_80
+ bool "80 MHz"
+
+ config ESP32S3_DEFAULT_CPU_FREQ_160
+ bool "160 MHz"
+
+ config ESP32S3_DEFAULT_CPU_FREQ_240
+ bool "240 MHz"
+
+endchoice # CPU frequency
+
+config ESP32S3_DEFAULT_CPU_FREQ_MHZ
+ int
+ default 80 if ESP32S3_DEFAULT_CPU_FREQ_80
+ default 160 if ESP32S3_DEFAULT_CPU_FREQ_160
+ default 240 if ESP32S3_DEFAULT_CPU_FREQ_240
+
+menu "Cache config"
+
+choice
+ prompt "Instruction cache size"
+ default ESP32S3_INSTRUCTION_CACHE_16KB
+ ---help---
+ Instruction cache size to be set on application startup.
+ If you use 16KB instruction cache rather than 32KB instruction cache,
+ then the other 16KB will be managed by heap allocator.
+
+config ESP32S3_INSTRUCTION_CACHE_16KB
+ bool "16KB"
+ ---help---
+ Use 16KB of SRAM as Instruction Cache
+
+config ESP32S3_INSTRUCTION_CACHE_32KB
+ bool "32KB"
+ ---help---
+ Use 32KB of SRAM as Instruction Cache
+
+endchoice # Instruction cache size
+
+config ESP32S3_INSTRUCTION_CACHE_SIZE
+ hex
+ default 0x4000 if ESP32S3_INSTRUCTION_CACHE_16KB
+ default 0x8000 if ESP32S3_INSTRUCTION_CACHE_32KB
+
+choice ESP32S3_ICACHE_ASSOCIATED_WAYS
+ prompt "Instruction cache associated ways"
+ default ESP32S3_INSTRUCTION_CACHE_8WAYS
+ ---help---
+ Instruction cache associated ways to be set on application startup.
+
+ config ESP32S3_INSTRUCTION_CACHE_4WAYS
+ bool "4 ways"
+
+ config ESP32S3_INSTRUCTION_CACHE_8WAYS
+ bool "8 ways"
+
+endchoice
+
+config ESP32S3_ICACHE_ASSOCIATED_WAYS
+ int
+ default 4 if ESP32S3_INSTRUCTION_CACHE_4WAYS
+ default 8 if ESP32S3_INSTRUCTION_CACHE_8WAYS
+
+choice ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
+ prompt "Instruction cache line size"
+ default ESP32S3_INSTRUCTION_CACHE_LINE_32B
+ ---help---
+ Instruction cache line size to be set on application startup.
+
+ config ESP32S3_INSTRUCTION_CACHE_LINE_16B
+ bool "16 Bytes"
+ depends on ESP32S3_INSTRUCTION_CACHE_16KB
+
+ config ESP32S3_INSTRUCTION_CACHE_LINE_32B
+ bool "32 Bytes"
+
+endchoice
+
+config ESP32S3_INSTRUCTION_CACHE_LINE_SIZE
+ int
+ default 16 if ESP32S3_INSTRUCTION_CACHE_LINE_16B
+ default 32 if ESP32S3_INSTRUCTION_CACHE_LINE_32B
+
+choice
+ prompt "Data cache size"
+ default ESP32S3_DATA_CACHE_32KB
+ ---help---
+ Data cache size to be set on application startup.
+ If you use 32KB data cache rather than 64KB data cache,
+ the other 32KB will be added to the heap.
+
+config ESP32S3_DATA_CACHE_16KB
+ bool "16KB"
+ ---help---
+ Use 16KB of SRAM as Data Cache
+
+config ESP32S3_DATA_CACHE_32KB
+ bool "32KB"
+ ---help---
+ Use 32KB of SRAM as Data Cache
+
+config ESP32S3_DATA_CACHE_64KB
+ bool "64KB"
+ ---help---
+ Use 64KB of SRAM as Data Cache
+
+endchoice # Data cache size
+
+config ESP32S3_DATA_CACHE_SIZE
+ hex
+ # For 16KB the actual configuration is 32kb cache, but 16kb will be reserved for heap at startup
+ default 0x8000 if ESP32S3_DATA_CACHE_16KB
+ default 0x8000 if ESP32S3_DATA_CACHE_32KB
+ default 0x10000 if ESP32S3_DATA_CACHE_64KB
+
+choice ESP32S3_DCACHE_ASSOCIATED_WAYS
+ prompt "Data cache associated ways"
+ default ESP32S3_DATA_CACHE_8WAYS
+ ---help---
+ Data cache associated ways to be set on application startup.
+
+ config ESP32S3_DATA_CACHE_4WAYS
+ bool "4 ways"
+
+ config ESP32S3_DATA_CACHE_8WAYS
+ bool "8 ways"
+
+endchoice
+
+config ESP32S3_DCACHE_ASSOCIATED_WAYS
+ int
+ default 4 if ESP32S3_DATA_CACHE_4WAYS
+ default 8 if ESP32S3_DATA_CACHE_8WAYS
+
+choice ESP32S3_DATA_CACHE_LINE_SIZE
+ prompt "Data cache line size"
+ default ESP32S3_DATA_CACHE_LINE_32B
+ ---help---
+ Data cache line size to be set on application startup.
+
+ config ESP32S3_DATA_CACHE_LINE_16B
+ bool "16 Bytes"
+ depends on ESP32S3_DATA_CACHE_16KB || ESP32S3_DATA_CACHE_32KB
+
+ config ESP32S3_DATA_CACHE_LINE_32B
+ bool "32 Bytes"
+
+ config ESP32S3_DATA_CACHE_LINE_64B
+ bool "64 Bytes"
+
+endchoice
+
+config ESP32S3_DATA_CACHE_LINE_SIZE
+ int
+ default 16 if ESP32S3_DATA_CACHE_LINE_16B
+ default 32 if ESP32S3_DATA_CACHE_LINE_32B
+ default 64 if ESP32S3_DATA_CACHE_LINE_64B
+
+endmenu # Cache config
+
+config ESP32S3_ULP_COPROC_ENABLED
+ bool "Enable Ultra Low Power (ULP) Coprocessor"
+ default n
+ ---help---
+ Set to 'y' if you plan to load a firmware for the coprocessor.
+
+config ESP32S3_ULP_COPROC_RESERVE_MEM
+ int
+ prompt "RTC slow memory reserved for coprocessor" if ESP32S3_ULP_COPROC_ENABLED
+ default 512 if ESP32S3_ULP_COPROC_ENABLED
+ range 32 8176 if ESP32S3_ULP_COPROC_ENABLED
+ default 0 if !ESP32S3_ULP_COPROC_ENABLED
+ range 0 0 if !ESP32S3_ULP_COPROC_ENABLED
+ help
+ Bytes of memory to reserve for ULP coprocessor firmware & data.
+ Data is reserved at the beginning of RTC slow memory.
+
+config ESP32S3_FLASH_4M
+ bool
+ default n
+
+config ESP32S3_FLASH_8M
+ bool
+ default n
+
+config ESP32S3_FLASH_16M
+ bool
+ default n
+
+config ESP32S3_ESPTOOLPY_NO_STUB
+ bool "Disable download stub"
+ default n
+ ---help---
+ The flasher tool sends a precompiled download stub first by default.
+ That stub allows things like compressed downloads and more.
+ Usually you should not need to disable that feature.
+ It is only required to be disabled in certain scenarios when either
+ Secure Boot V2 or Flash Encryption is enabled.
+
+config ESP32S3_FLASH_DETECT
+ bool "Auto-detect FLASH size"
+ default y
+ ---help---
+ Auto detect flash size when flashing.
+
+config ESP32S3_PSRAM_8M
+ bool
+ default n
+
+choice ESP32S3_FLASH_MODE
+ prompt "SPI FLASH mode"
+ default ESP32S3_FLASH_MODE_DIO
+ ---help---
+ These options control how many I/O pins are used for communication
+ with the attached SPI flash chip.
+ The option selected here is then used by esptool when flashing.
+
+ config ESP32S3_FLASH_MODE_DIO
+ bool "Dual IO (DIO)"
+
+ config ESP32S3_FLASH_MODE_DOUT
+ bool "Dual Output (DOUT)"
+
+ config ESP32S3_FLASH_MODE_QIO
+ bool "Quad IO (QIO)"
+
+ config ESP32S3_FLASH_MODE_QOUT
+ bool "Quad Output (QOUT)"
+
+endchoice # ESP32S3_FLASH_MODE
+
+choice ESP32S3_FLASH_FREQ
+ prompt "SPI FLASH frequency"
+ default ESP32S3_FLASH_FREQ_40M
+ ---help---
+ SPI FLASH frequency
+
+ config ESP32S3_FLASH_FREQ_120M
+ bool "120 MHz"
+
+ config ESP32S3_FLASH_FREQ_80M
+ bool "80 MHz"
+
+ config ESP32S3_FLASH_FREQ_40M
+ bool "40 MHz"
+
+ config ESP32S3_FLASH_FREQ_20M
+ bool "20 MHz"
+
+endchoice # ESP32S3_FLASH_FREQ
+
+config ESP32S3_RUN_IRAM
+ bool "Run from IRAM"
+ default n
+ ---help---
+ This loads all of NuttX inside IRAM. Used to test somewhat small
+ images that can fit entirely in IRAM.
+
+menu "ESP32-S3 Peripheral Selection"
+
+config ESP32S3_UART
+ bool
+ default n
+
+config ESP32S3_UART0
+ bool "UART 0"
+ default n
+ select ESP32S3_UART
+ select UART0_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+config ESP32S3_UART1
+ bool "UART 1"
+ default n
+ select ESP32S3_UART
+ select UART1_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+config ESP32S3_UART2
+ bool "UART 2"
+ default n
+ select ESP32S3_UART
+ select UART2_SERIALDRIVER
+ select ARCH_HAVE_SERIAL_TERMIOS
+
+endmenu # ESP32S3 Peripheral Selection
+
+menu "UART configuration"
+ depends on ESP32S3_UART
+
+if ESP32S3_UART0
+
+config ESP32S3_UART0_TXPIN
+ int "UART0 Tx Pin"
+ default 43
+ range 0 48
+
+config ESP32S3_UART0_RXPIN
+ int "UART0 Rx Pin"
+ default 44
+ range 0 48
+
+config ESP32S3_UART0_RTSPIN
+ int "UART0 RTS Pin"
+ depends on SERIAL_IFLOWCONTROL
+ default 15
+ range 0 48
+
+config ESP32S3_UART0_CTSPIN
+ int "UART0 CTS Pin"
+ depends on SERIAL_OFLOWCONTROL
+ default 16
+ range 0 48
+
+endif # ESP32S3_UART0
+
+if ESP32S3_UART1
+
+config ESP32S3_UART1_TXPIN
+ int "UART1 Tx Pin"
+ default 17
+ range 0 48
+
+config ESP32S3_UART1_RXPIN
+ int "UART1 Rx Pin"
+ default 18
+ range 0 48
+
+config ESP32S3_UART1_RTSPIN
+ int "UART1 RTS Pin"
+ depends on SERIAL_IFLOWCONTROL
+ default 19
+ range 0 48
+
+config ESP32S3_UART1_CTSPIN
+ int "UART1 CTS Pin"
+ depends on SERIAL_OFLOWCONTROL
+ default 20
+ range 0 48
+
+endif # ESP32S3_UART1
+
+if ESP32S3_UART2
+
+config ESP32S3_UART2_TXPIN
+ int "UART2 Tx Pin"
+ default 17
+ range 0 48
+
+config ESP32S3_UART2_RXPIN
+ int "UART2 Rx Pin"
+ default 16
+ range 0 48
+
+config ESP32S3_UART2_RTSPIN
+ int "UART2 RTS Pin"
+ depends on SERIAL_IFLOWCONTROL
+ default 35
+ range 0 48
+
+config ESP32S3_UART2_CTSPIN
+ int "UART2 CTS Pin"
+ depends on SERIAL_OFLOWCONTROL
+ default 36
+ range 0 48
+
+endif # ESP32S3_UART2
+
+endmenu # UART configuration
+
+menu "Application Image Configuration"
+
+choice
+ prompt "Application Image Format"
+ default ESP32S3_APP_FORMAT_LEGACY
+ ---help---
+ Depending on the chosen 2nd stage bootloader, the application may
+ be required to be perform a specific startup routine. Furthermore,
+ the image binary must be formatted according to the definition from
+ the 2nd stage bootloader.
+
+config ESP32S3_APP_FORMAT_LEGACY
+ bool "Legacy format"
+ ---help---
+ This is the legacy application image format, as supported by the ESP-IDF
+ 2nd stage bootloader.
+
+endchoice # Application Image Format
+
+choice
+ prompt "Source for bootloader binaries"
+ default ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
+ ---help---
+ Select the action to be taken by the build system for the
+ "make bootloader" target.
+
+config ESP32S3_BOOTLOADER_DOWNLOAD_PREBUILT
+ bool "Download prebuilt binaries"
+ ---help---
+ The build system will download the prebuilt binaries from
+ https://github.com/espressif/esp-nuttx-bootloader according to the chosen
+ Application Image Format (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT)
+
+config ESP32S3_BOOTLOADER_BUILD_FROM_SOURCE
+ bool "Build binaries from source"
+ ---help---
+ The build system will build all the required binaries from source. It will clone
+ the https://github.com/espressif/esp-nuttx-bootloader repository and build a
+ custom bootloader according to the chosen Application Image Format
+ (ESP32S3_APP_FORMAT_LEGACY or ESP32S3_APP_FORMAT_MCUBOOT) and partition information.
+
+endchoice
+
+config ESP32S3_PARTITION_TABLE_OFFSET
+ hex "Partition Table offset"
+ default 0x8000
+ depends on ESP32S3_APP_FORMAT_LEGACY
+
+endmenu # Application Image Configuration
+
+endif # ARCH_CHIP_ESP32S3
diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs
new file mode 100644
index 0000000..1bc77eb
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/Make.defs
@@ -0,0 +1,74 @@
+############################################################################
+# arch/xtensa/src/esp32s3/Make.defs
+#
+# Licensed to the Apache Software Foundation (ASF) under one or more
+# contributor license agreements. See the NOTICE file distributed with
+# this work for additional information regarding copyright ownership. The
+# ASF licenses this file to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance with the
+# License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+# License for the specific language governing permissions and limitations
+# under the License.
+#
+############################################################################
+
+include chip/Bootloader.mk
+
+# The start-up, "head", file. May be either a .S or a .c file.
+
+HEAD_ASRC = xtensa_vectors.S xtensa_window_vector.S xtensa_windowspill.S
+HEAD_ASRC += xtensa_int_handlers.S xtensa_user_handler.S
+HEAD_CSRC = esp32s3_start.c
+
+# Common XTENSA files (arch/xtensa/src/common)
+
+CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S xtensa_panic.S
+CMN_ASRCS += xtensa_sigtramp.S
+
+CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
+CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c
+CMN_CSRCS += xtensa_initialize.c xtensa_initialstate.c xtensa_interruptcontext.c
+CMN_CSRCS += xtensa_irqdispatch.c xtensa_lowputs.c xtensa_mdelay.c
+CMN_CSRCS += xtensa_modifyreg8.c xtensa_modifyreg16.c xtensa_modifyreg32.c
+CMN_CSRCS += xtensa_puts.c xtensa_releasepending.c xtensa_releasestack.c
+CMN_CSRCS += xtensa_reprioritizertr.c xtensa_schedsigaction.c
+CMN_CSRCS += xtensa_sigdeliver.c xtensa_stackframe.c xtensa_udelay.c
+CMN_CSRCS += xtensa_unblocktask.c xtensa_usestack.c
+
+# Configuration-dependent common XTENSA files
+
+ifeq ($(CONFIG_DEBUG_ALERT),y)
+ CMN_CSRCS += xtensa_dumpstate.c
+endif
+
+ifeq ($(CONFIG_SPINLOCK),y)
+ CMN_CSRCS += xtensa_testset.c
+endif
+
+ifeq ($(CONFIG_STACK_COLORATION),y)
+ CMN_CSRCS += xtensa_checkstack.c
+endif
+
+ifeq ($(CONFIG_XTENSA_SEMIHOSTING_HOSTFS),y)
+ CMN_ASRCS += xtensa_simcall.S
+ CMN_CSRCS += xtensa_hostfs.c
+endif
+
+# Required ESP32-S3 files (arch/xtensa/src/esp32s3)
+
+CHIP_CSRCS = esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c
+CHIP_CSRCS += esp32s3_timerisr.c esp32s3_user.c esp32s3_allocateheap.c
+CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c
+CHIP_CSRCS += esp32s3_systemreset.c
+
+# Configuration-dependent ESP32-S3 files
+
+ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
+CHIP_CSRCS += esp32s3_idle.c
+endif
diff --git a/arch/xtensa/src/esp32s3/chip.h b/arch/xtensa/src/esp32s3/chip.h
new file mode 100644
index 0000000..725c54d
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/chip.h
@@ -0,0 +1,61 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/chip.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_H
+#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip_macros.h"
+#include "chip_memory.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_CHIP_H */
diff --git a/arch/xtensa/src/esp32s3/chip_macros.h b/arch/xtensa/src/esp32s3/chip_macros.h
new file mode 100644
index 0000000..c4e1d3f
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/chip_macros.h
@@ -0,0 +1,91 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/chip_macros.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H
+#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* This is the name of the section containing the Xtensa low level handlers
+ * that is used by the board linker scripts.
+ */
+
+#define HANDLER_SECTION .iram1
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Assembly Language Macros
+ ****************************************************************************/
+
+#ifdef __ASSEMBLY__
+
+/* Macro to get the current core ID. Only uses the reg given as an argument.
+ * Reading PRID on the ESP108 architecture gives us 0xcdcd on the PRO
+ * processor and 0xabab on the APP CPU. We distinguish between the two by
+ * simply checking bit 1: it's 1 on the APP and 0 on the PRO processor.
+ */
+
+ .macro getcoreid reg
+ rsr.prid \reg
+ bbci \reg, 1, 1f
+ movi \reg, 1
+ j 2f
+1:
+ movi \reg, 0
+2:
+ .endm
+
+#endif /* __ASSEMBLY */
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_CHIP_MACROS_H */
diff --git a/arch/xtensa/src/esp32s3/chip_memory.h b/arch/xtensa/src/esp32s3/chip_memory.h
new file mode 100644
index 0000000..4df97a4
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/chip_memory.h
@@ -0,0 +1,73 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/chip_memory.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_CHIP_MEMORY_H
+#define __ARCH_XTENSA_SRC_ESP32S3_CHIP_MEMORY_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "hardware/esp32s3_soc.h"
+#endif
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: xtensa_sp_sane
+ ****************************************************************************/
+
+static inline bool xtensa_sp_sane(uint32_t sp)
+{
+ return (esp32s3_sp_dram(sp) && ((sp & 0x0f) == 0));
+}
+
+/****************************************************************************
+ * Name: xtensa_ptr_extram
+ ****************************************************************************/
+
+static inline bool xtensa_ptr_exec(const void *p)
+{
+ return esp32s3_ptr_exec(p);
+}
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_CHIP_MEMORY_H */
+
diff --git a/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c b/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
new file mode 100644
index 0000000..48acae1
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
@@ -0,0 +1,84 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_allocateheap.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/mm/mm.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_rom_layout.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * This function will be called to dynamically set aside the heap region.
+ *
+ * For the kernel build (CONFIG_BUILD_KERNEL=y) with both kernel- and
+ * user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
+ * size of the unprotected, user-space heap.
+ *
+ * If a protected kernel-space heap is provided, the kernel heap must be
+ * allocated (and protected) by an analogous up_allocate_kheap().
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(void **heap_start, size_t *heap_size)
+{
+ board_autoled_on(LED_HEAPALLOCATE);
+
+ *heap_start = (void *)&_sheap;
+ *heap_size = (size_t)(ets_rom_layout_p->dram0_rtos_reserved_start -
+ (uintptr_t)&_sheap);
+}
+
+/****************************************************************************
+ * Name: xtensa_add_region
+ *
+ * Description:
+ * RAM may be added in non-contiguous chunks. This routine adds all chunks
+ * that may be used for heap.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+void xtensa_add_region(void)
+{
+}
+#endif
diff --git a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
new file mode 100644
index 0000000..2a218d7
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
@@ -0,0 +1,312 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef MIN
+ #define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#define DEFAULT_CPU_FREQ 80
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+enum cpu_freq_e
+{
+ CPU_80M = 0,
+ CPU_160M = 1,
+ CPU_240M = 2,
+};
+
+enum cpu_clksrc_e
+{
+ XTAL_CLK,
+ PLL_CLK,
+ FOSC_CLK
+};
+
+enum pll_freq_e
+{
+ PLL_320,
+ PLL_480
+};
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: ets_update_cpu_frequency
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us will be
+ * accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+extern void ets_update_cpu_frequency(uint32_t ticks_per_us);
+
+/****************************************************************************
+ * Name: ets_get_cpu_frequency
+ *
+ * Description:
+ * Get the real CPU ticks per us to the ets.
+ * This function do not return real CPU ticks per us, just the record in
+ * ets. It can be used to check with the real CPU frequency.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * CPU ticks per us record in ets.
+ *
+ ****************************************************************************/
+
+extern uint32_t ets_get_cpu_frequency(void);
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_cpuclksrc
+ *
+ * Description:
+ * Select a clock source for CPU clock.
+ *
+ * Input Parameters:
+ * src - Any source from cpu_clksrc_e.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void esp32s3_cpuclksrc(enum cpu_clksrc_e src)
+{
+ uint32_t value;
+ value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL);
+ modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value);
+}
+
+/****************************************************************************
+ * Name: esp32s3_cpudiv
+ *
+ * Description:
+ * Select a divider for the CPU clk.
+ * NOTE: The divider is not necessarily the real divisor. See TRM for the
+ * equivalences.
+ *
+ * Input Parameters:
+ * divider - A value between 0 to 2.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void esp32s3_cpudiv(uint8_t divider)
+{
+ uint32_t value;
+ value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL);
+ modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value);
+}
+
+/****************************************************************************
+ * Name: esp32s3_pllfreqsel
+ *
+ * Description:
+ * Select the PLL frequency.
+ *
+ * Input Parameters:
+ * freq - Any clock from enum pll_freq_e
+ *
+ * Returned Value:
+ * None
+ ****************************************************************************/
+
+static inline void esp32s3_pllfreqsel(enum pll_freq_e freq)
+{
+ uint32_t value;
+ value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL);
+ modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_update_cpu_freq
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us
+ * will be accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32s3_update_cpu_freq(uint32_t ticks_per_us)
+{
+ /* Update scale factors used by esp_rom_delay_us */
+
+ ets_update_cpu_frequency(ticks_per_us);
+}
+
+/****************************************************************************
+ * Name: esp32s3_set_cpu_freq
+ *
+ * Description:
+ * Switch to one of PLL-based frequencies.
+ *
+ * Input Parameters:
+ * cpu_freq_mhz - Target CPU frequency
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR esp32s3_set_cpu_freq(int cpu_freq_mhz)
+{
+ switch (cpu_freq_mhz)
+ {
+ case 80:
+ /* 80 MHz is obtained from the 480 MHz PLL.
+ * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz
+ * with a 6 divider and set the source clock as PLL_CLK.
+ */
+
+ esp32s3_cpudiv(0);
+ break;
+
+ case 160:
+ /* 160 MHz is obtained from the 480 MHz PLL.
+ * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz
+ * with a 3 divider and set the source clock as PLL_CLK.
+ */
+
+ esp32s3_cpudiv(1);
+ break;
+
+ case 240:
+ /* 240 MHz is obtained from the 480 MHz PLL.
+ * In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz
+ * with a 2 divider and set the source clock as PLL_CLK.
+ */
+
+ esp32s3_cpudiv(2);
+ break;
+
+ default:
+
+ /* Unsupported clock config. */
+
+ return;
+ }
+
+ esp32s3_pllfreqsel(PLL_480);
+ esp32s3_cpuclksrc(PLL_CLK);
+ esp32s3_update_cpu_freq(cpu_freq_mhz);
+}
+
+/****************************************************************************
+ * Name: esp32s3_clockconfig
+ *
+ * Description:
+ * Called to initialize the ESP32-S3. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ ****************************************************************************/
+
+void esp32s3_clockconfig(void)
+{
+ /* Configure the CPU frequency */
+
+ esp32s3_set_cpu_freq(CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ);
+}
+
+/****************************************************************************
+ * Name: esp_clk_cpu_freq
+ *
+ * Description:
+ * Get CPU frequency
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * CPU frequency
+ *
+ ****************************************************************************/
+
+int IRAM_ATTR esp_clk_cpu_freq(void)
+{
+ return (int)ets_get_cpu_frequency() * MHZ;
+}
+
+/****************************************************************************
+ * Name: esp_clk_apb_freq
+ *
+ * Description:
+ * Return current APB clock frequency.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * APB clock frequency, in Hz
+ *
+ ****************************************************************************/
+
+int IRAM_ATTR esp_clk_apb_freq(void)
+{
+ return MIN(ets_get_cpu_frequency(), 80) * MHZ;
+}
+
diff --git a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.h b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.h
new file mode 100644
index 0000000..5cae742
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.h
@@ -0,0 +1,120 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_clockconfig.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_update_cpu_freq
+ *
+ * Description:
+ * Set the real CPU ticks per us to the ets, so that ets_delay_us
+ * will be accurate. Call this function when CPU frequency is changed.
+ *
+ * Input Parameters:
+ * ticks_per_us - CPU ticks per us
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32s3_update_cpu_freq(uint32_t ticks_per_us);
+
+/****************************************************************************
+ * Name: esp32s3_set_cpu_freq
+ *
+ * Description:
+ * Switch to one of PLL-based frequencies.
+ * Current frequency can be XTAL or PLL.
+ *
+ * Input Parameters:
+ * cpu_freq_mhz - new CPU frequency
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32s3_set_cpu_freq(int cpu_freq_mhz);
+
+/****************************************************************************
+ * Name: esp32s3_clockconfig
+ *
+ * Description:
+ * Called to initialize the ESP32-S3. This does whatever setup is needed to
+ * put the SoC in a usable state. This includes the initialization of
+ * clocking using the settings in board.h.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void esp32s3_clockconfig(void);
+
+/****************************************************************************
+ * Name: esp_clk_cpu_freq
+ *
+ * Description:
+ * Get the current CPU frequency.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * CPU frequency in Hz.
+ *
+ ****************************************************************************/
+
+int esp_clk_cpu_freq(void);
+
+/****************************************************************************
+ * Name: esp_clk_apb_freq
+ *
+ * Description:
+ * Return current APB clock frequency.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * APB clock frequency in Hz.
+ *
+ ****************************************************************************/
+
+int esp_clk_apb_freq(void);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_config.h b/arch/xtensa/src/esp32s3/esp32s3_config.h
new file mode 100644
index 0000000..ea510fd
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_config.h
@@ -0,0 +1,64 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_config.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/chip/chip.h>
+#include <arch/board/board.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* UARTs ********************************************************************/
+
+/* Are any UARTs enabled? */
+
+#undef HAVE_UART_DEVICE
+#ifdef CONFIG_ESP32S3_UART
+# define HAVE_UART_DEVICE 1
+#endif
+
+/* Serial Console ***********************************************************/
+
+/* Is there a serial console? There should be no more than one defined. It
+ * could be on any UARTn. n E {0,1}
+ */
+
+#undef CONSOLE_UART
+#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_ESP32S3_UART0)
+# undef CONFIG_UART1_SERIAL_CONSOLE
+# define CONSOLE_UART 1
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE) && defined(CONFIG_ESP32S3_UART1)
+# undef CONFIG_UART0_SERIAL_CONSOLE
+# define CONSOLE_UART 1
+#else
+# undef CONFIG_UART0_SERIAL_CONSOLE
+# undef CONFIG_UART1_SERIAL_CONSOLE
+#endif
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CONFIG_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.c b/arch/xtensa/src/esp32s3/esp32s3_gpio.c
new file mode 100644
index 0000000..7992341
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_gpio.c
@@ -0,0 +1,205 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_gpio.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <assert.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <arch/irq.h>
+#include <arch/esp32s3/chip.h>
+
+#include "xtensa.h"
+#include "esp32s3_irq.h"
+#include "hardware/esp32s3_iomux.h"
+#include "hardware/esp32s3_gpio.h"
+
+#include "esp32s3_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on encoded pin attributes.
+ *
+ ****************************************************************************/
+
+int esp32s3_configgpio(int pin, gpio_pinattr_t attr)
+{
+ uintptr_t regaddr;
+ uint32_t func;
+ uint32_t cntrl;
+ uint32_t pin2func;
+
+ DEBUGASSERT(pin >= 0 && pin <= ESP32S3_NGPIOS);
+
+ func = 0;
+ cntrl = 0;
+
+ /* Handle input pins */
+
+ if ((attr & INPUT) != 0)
+ {
+ putreg32((1ul << pin), GPIO_ENABLE_W1TC_REG);
+
+ /* Input enable */
+
+ func |= FUN_IE;
+
+ if ((attr & PULLUP) != 0)
+ {
+ func |= FUN_PU;
+ }
+ else if ((attr & PULLDOWN) != 0)
+ {
+ func |= FUN_PD;
+ }
+ }
+
+ /* Handle output pins */
+
+ if ((attr & OUTPUT) != 0)
+ {
+ putreg32((1ul << pin), GPIO_ENABLE_W1TS_REG);
+ }
+
+ /* Add drivers */
+
+ func |= (uint32_t)(2ul << FUN_DRV_S);
+
+ /* Select the pad's function. If no function was given, consider it a
+ * normal input or output (i.e. function1).
+ */
+
+ if ((attr & FUNCTION_MASK) != 0)
+ {
+ func |= (uint32_t)(((attr >> FUNCTION_SHIFT) - 1) << MCU_SEL_S);
+ }
+ else
+ {
+ func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S);
+ }
+
+ if ((attr & OPEN_DRAIN) != 0)
+ {
+ cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S);
+ }
+
+ /* Set the pin function to its register */
+
+ pin2func = (pin + 1) * 4;
+ regaddr = REG_IO_MUX_BASE + pin2func;
+ putreg32(func, regaddr);
+
+ regaddr = GPIO_REG(pin);
+ putreg32(cntrl, regaddr);
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_gpio_matrix_in
+ *
+ * Description:
+ * Set gpio input to a signal
+ * NOTE: one gpio can input to several signals
+ * If gpio == 0x3c, cancel input to the signal, input 0 to signal.
+ * If gpio == 0x3a, input nothing to signal.
+ * If gpio == 0x38, cancel input to the signal, input 1 to signal.
+ *
+ ****************************************************************************/
+
+void esp32s3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv)
+{
+ uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4);
+ uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S);
+
+ if (inv)
+ {
+ regval |= GPIO_FUNC0_IN_INV_SEL;
+ }
+
+ if (gpio != 0x3a)
+ {
+ regval |= GPIO_SIG0_IN_SEL;
+ }
+
+ putreg32(regval, regaddr);
+}
+
+/****************************************************************************
+ * Name: esp32s3_gpio_matrix_out
+ *
+ * Description:
+ * Set signal output to gpio
+ * NOTE: one signal can output to several gpios
+ * If signal_idx == 0x100, cancel output put to the gpio
+ *
+ ****************************************************************************/
+
+void esp32s3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
+ bool out_inv, bool oen_inv)
+{
+ uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4);
+ uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S;
+
+ if (gpio >= ESP32S3_NGPIOS)
+ {
+ return;
+ }
+
+ putreg32(1ul << gpio, GPIO_ENABLE_W1TS_REG);
+
+ if (out_inv)
+ {
+ regval |= GPIO_FUNC0_OUT_INV_SEL;
+ }
+
+ if (oen_inv)
+ {
+ regval |= GPIO_FUNC0_OEN_INV_SEL;
+ }
+
+ putreg32(regval, regaddr);
+}
+
diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.h b/arch/xtensa/src/esp32s3/esp32s3_gpio.h
new file mode 100644
index 0000000..b254dd3
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_gpio.h
@@ -0,0 +1,163 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_gpio.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */
+#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */
+#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */
+
+/* Bit-encoded input to esp32s3_configgpio() ********************************/
+
+/* Encoded pin attributes used with esp32s3_configgpio()
+ *
+ * 8 7 6 5 4 3 2 1 0
+ * -- -- -- -- -- -- -- -- --
+ * FN FN FN OD PD PU F O I
+ */
+
+#define PINMODE_SHIFT 0
+#define PINMODE_MASK (7 << PINMODE_SHIFT)
+# define INPUT (1 << 0)
+# define OUTPUT (1 << 1)
+# define FUNCTION (1 << 2)
+
+#define PULLUP (1 << 3)
+#define PULLDOWN (1 << 4)
+#define OPEN_DRAIN (1 << 5)
+#define FUNCTION_SHIFT 6
+#define FUNCTION_MASK (7 << FUNCTION_SHIFT)
+# define FUNCTION_0 (1 << FUNCTION_SHIFT)
+# define FUNCTION_1 (2 << FUNCTION_SHIFT)
+# define FUNCTION_2 (3 << FUNCTION_SHIFT)
+# define FUNCTION_3 (4 << FUNCTION_SHIFT)
+# define FUNCTION_4 (5 << FUNCTION_SHIFT)
+
+#define INPUT_PULLUP (INPUT | PULLUP)
+#define INPUT_PULLDOWN (INPUT | PULLDOWN)
+#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN)
+#define INPUT_FUNCTION (INPUT | FUNCTION)
+# define INPUT_FUNCTION_0 (INPUT_FUNCTION | FUNCTION_0)
+# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1)
+# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2)
+# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3)
+# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4)
+#define OUTPUT_FUNCTION (OUTPUT | FUNCTION)
+# define OUTPUT_FUNCTION_0 (OUTPUT_FUNCTION | FUNCTION_0)
+# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1)
+# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2)
+# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3)
+# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4)
+
+/* Interrupt type used with esp32s3_gpioirqenable() */
+
+#define DISABLED 0x00
+#define RISING 0x01
+#define FALLING 0x02
+#define CHANGE 0x03
+#define ONLOW 0x04
+#define ONHIGH 0x05
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/* Must be big enough to hold the above encodings */
+
+typedef uint16_t gpio_pinattr_t;
+typedef uint8_t gpio_intrtype_t;
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on encoded pin attributes.
+ *
+ ****************************************************************************/
+
+int esp32s3_configgpio(int pin, gpio_pinattr_t attr);
+
+/****************************************************************************
+ * Name: esp32s3_gpio_matrix_in
+ *
+ * Description:
+ * Set gpio input to a signal
+ * NOTE: one gpio can input to several signals
+ * If gpio == 0x3c, cancel input to the signal, input 0 to signal.
+ * If gpio == 0x3a, input nothing to signal.
+ * If gpio == 0x38, cancel input to the signal, input 1 to signal.
+ *
+ ****************************************************************************/
+
+void esp32s3_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv);
+
+/****************************************************************************
+ * Name: esp32s3_gpio_matrix_out
+ *
+ * Description:
+ * Set signal output to gpio
+ * NOTE: one signal can output to several gpios
+ * If signal_idx == 0x100, cancel output put to the gpio
+ *
+ ****************************************************************************/
+
+void esp32s3_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx,
+ bool out_inv, bool oen_inv);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_idle.c b/arch/xtensa/src/esp32s3/esp32s3_idle.c
new file mode 100644
index 0000000..d3c4167
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_idle.c
@@ -0,0 +1,83 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_idle.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/board/board.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#include "xtensa.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_idle
+ *
+ * Description:
+ * up_idle() is the logic that will be executed when their is no other
+ * ready-to-run task. This is processor idle time and will continue until
+ * some interrupt occurs to cause a context switch from the idle task.
+ *
+ * Processing in this state may be processor-specific. e.g., this is where
+ * power management operations might be performed.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_idle(void)
+{
+#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
+ /* If the system is idle and there are no timer interrupts, then process
+ * "fake" timer interrupts. Hopefully, something will wake up.
+ */
+
+ nxsched_process_timer();
+#else
+
+ /* This would be an appropriate place to put some MCU-specific logic to
+ * sleep in a reduced power mode until an interrupt occurs to save power
+ */
+
+#if XCHAL_HAVE_INTERRUPTS
+ __asm__ __volatile__ ("waiti 0");
+#endif
+
+#endif
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c
new file mode 100644
index 0000000..75163d1
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_irq.c
@@ -0,0 +1,686 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "xtensa.h"
+
+#include "hardware/esp32s3_soc.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_interrupt_core0.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ to CPU and CPU interrupts mapping:
+ *
+ * Encoding: CIIIIIII
+ * C: CPU that enabled the interrupt (0 = PRO, 1 = APP).
+ * I: Associated CPU interrupt.
+ */
+
+#define IRQ_UNMAPPED 0xff
+#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07)
+#define IRQ_GETCPUINT(m) ((m) & 0x7f)
+#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i))
+
+/* CPU interrupts to peripheral mapping:
+ *
+ * Encoding: EPPPPPPP
+ * E: CPU interrupt status (0 = Disabled, 1 = Enabled).
+ * P: Attached peripheral.
+ */
+
+#define CPUINT_UNASSIGNED 0x7f
+#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07)
+#define CPUINT_GETIRQ(m) ((m) & 0x7f)
+#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80)
+#define CPUINT_DISABLE(m) ((m) & 0x7f)
+#define CPUINT_ENABLE(m) ((m) | 0x80)
+
+/* Mapping Peripheral IDs to map register addresses. */
+
+#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2))
+
+/* CPU interrupts can be detached from any peripheral source by setting the
+ * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
+ */
+
+#define NO_CPUINT ESP32S3_CPUINT_TIMER0
+
+/* Priority range is 1-5 */
+
+#define ESP32S3_MIN_PRIORITY 1
+#define ESP32S3_MAX_PRIORITY 5
+#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY)
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* g_current_regs[] holds a reference to the current interrupt level
+ * register storage structure. It is non-NULL only during interrupt
+ * processing. Access to g_current_regs[] must be through the macro
+ * CURRENT_REGS for portability.
+ */
+
+volatile uint32_t *g_current_regs[1];
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */
+
+static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS];
+
+static volatile uint8_t g_irqmap[NR_IRQS];
+
+/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
+ * content.
+ */
+
+static uint32_t g_intenable[1];
+
+/* Bitsets for free, unallocated CPU interrupts available to peripheral
+ * devices.
+ */
+
+static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET;
+
+/* Bitsets for each interrupt priority 1-5 */
+
+static const uint32_t g_priority[5] =
+{
+ ESP32S3_INTPRI1_MASK,
+ ESP32S3_INTPRI2_MASK,
+ ESP32S3_INTPRI3_MASK,
+ ESP32S3_INTPRI4_MASK,
+ ESP32S3_INTPRI5_MASK
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_intinfo
+ *
+ * Description:
+ * Return the CPU interrupt map of the given CPU and the register map
+ * of the given peripheral.
+ *
+ ****************************************************************************/
+
+static void esp32s3_intinfo(int cpu, int periphid,
+ uintptr_t *regaddr, uint8_t **intmap)
+{
+ *regaddr = CORE0_MAP_REGADDR(periphid);
+ *intmap = g_cpu0_intmap;
+}
+
+/****************************************************************************
+ * Name: esp32s3_getcpuint
+ *
+ * Description:
+ * Get a free CPU interrupt for a peripheral device. This function will
+ * not ignore all of the pre-allocated CPU interrupts for internal
+ * devices.
+ *
+ * Input Parameters:
+ * intmask - mask of candidate CPU interrupts. The CPU interrupt will be
+ * be allocated from free interrupts within this set
+ *
+ * Returned Value:
+ * On success, a CPU interrupt number is returned.
+ * A negated errno is returned on failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_getcpuint(uint32_t intmask)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+ uint32_t intset;
+ int cpuint;
+ int ret = -ENOMEM;
+ int cpu = 0;
+
+ /* Check if there are CPU interrupts with the requested properties
+ * available.
+ */
+
+ cpu = up_cpu_index();
+ freeints = &g_cpu0_freeints;
+
+ intset = *freeints & intmask;
+ if (intset != 0)
+ {
+ /* Skip over initial unavailable CPU interrupts quickly in groups
+ * of 8 interrupt.
+ */
+
+ for (cpuint = 0, bitmask = 0xff;
+ cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0;
+ cpuint += 8, bitmask <<= 8);
+
+ /* Search for an unallocated CPU interrupt number in the remaining
+ * intset.
+ */
+
+ for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++)
+ {
+ /* If the bit corresponding to the CPU interrupt is '1', then
+ * that CPU interrupt is available.
+ */
+
+ bitmask = 1ul << cpuint;
+ if ((intset & bitmask) != 0)
+ {
+ /* Got it! */
+
+ *freeints &= ~bitmask;
+ ret = cpuint;
+ break;
+ }
+ }
+ }
+
+ /* Enable the CPU interrupt now. The interrupt is still not attached
+ * to any peripheral and thus has no effect.
+ */
+
+ if (ret >= 0)
+ {
+ xtensa_enable_cpuint(&g_intenable[cpu], 1ul << ret);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_alloc_cpuint
+ *
+ * Description:
+ * Allocate a level CPU interrupt
+ *
+ * Input Parameters:
+ * priority - Priority of the CPU interrupt (1-5)
+ * type - Interrupt type (level or edge).
+ *
+ * Returned Value:
+ * On success, the allocated CPU interrupt number is returned.
+ * A negated errno is returned on failure. The only possible failure
+ * is that all CPU interrupts of the requested type have already been
+ * allocated.
+ *
+ ****************************************************************************/
+
+static int esp32s3_alloc_cpuint(int priority, int type)
+{
+ uint32_t mask;
+
+ DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY &&
+ priority <= ESP32S3_MAX_PRIORITY);
+ DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL ||
+ type == ESP32S3_CPUINT_EDGE);
+
+ if (type == ESP32S3_CPUINT_LEVEL)
+ {
+ /* Check if there are any level CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_LEVELSET;
+ }
+ else
+ {
+ /* Check if there are any edge CPU interrupts available at the
+ * requested interrupt priority.
+ */
+
+ mask = g_priority[ESP32S3_PRIO_INDEX(priority)] &
+ ESP32S3_CPUINT_EDGESET;
+ }
+
+ return esp32s3_getcpuint(mask);
+}
+
+/****************************************************************************
+ * Name: esp32s3_free_cpuint
+ *
+ * Description:
+ * Free a previously allocated CPU interrupt
+ *
+ * Input Parameters:
+ * The CPU interrupt number to be freed
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static void esp32s3_free_cpuint(int cpuint)
+{
+ uint32_t *freeints;
+ uint32_t bitmask;
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ /* Mark the CPU interrupt as available */
+
+ bitmask = 1ul << cpuint;
+
+ freeints = &g_cpu0_freeints;
+
+ DEBUGASSERT((*freeints & bitmask) == 0);
+ *freeints |= bitmask;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+ int i;
+ for (i = 0; i < NR_IRQS; i++)
+ {
+ g_irqmap[i] = IRQ_UNMAPPED;
+ }
+
+ /* Hard code special cases. */
+
+ g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0);
+
+ /* Initialize CPU interrupts */
+
+ esp32s3_cpuint_initialize();
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ /* And finally, enable interrupts. Also clears PS.EXCM */
+
+ up_irq_enable();
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ * Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ if (g_irqmap[irq] == IRQ_UNMAPPED)
+ {
+ /* This interrupt is already disabled. */
+
+ return;
+ }
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* This is an internal CPU interrupt, it cannot be disabled using
+ * the Interrupt Matrix.
+ */
+
+ xtensa_disable_cpuint(&g_intenable[cpu], 1ul << cpuint);
+ }
+ else
+ {
+ /* A peripheral interrupt, use the Interrupt Matrix to disable it. */
+
+ int periph = ESP32S3_IRQ2PERIPH(irq);
+ uintptr_t regaddr;
+ uint8_t *intmap;
+
+ DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
+ esp32s3_intinfo(cpu, periph, ®addr, &intmap);
+
+ intmap[cpuint] = CPUINT_DISABLE(intmap[cpuint]);
+ putreg32(NO_CPUINT, regaddr);
+ }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ * Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+ int cpu = IRQ_GETCPU(g_irqmap[irq]);
+ int cpuint = IRQ_GETCPUINT(g_irqmap[irq]);
+
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+ DEBUGASSERT(cpu == 0);
+
+ if (irq < XTENSA_NIRQ_INTERNAL)
+ {
+ /* Enable the CPU interrupt now for internal CPU. */
+
+ xtensa_enable_cpuint(&g_intenable[cpu], 1ul << cpuint);
+ }
+ else
+ {
+ /* For peripheral interrupts, attach the interrupt to the peripheral;
+ * the CPU interrupt was already enabled when allocated.
+ */
+
+ int periph = ESP32S3_IRQ2PERIPH(irq);
+ uintptr_t regaddr;
+ uint8_t *intmap;
+
+ DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS);
+
+ esp32s3_intinfo(cpu, periph, ®addr, &intmap);
+
+ intmap[cpuint] = CPUINT_ENABLE(intmap[cpuint]);
+ putreg32(cpuint, regaddr);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_cpuint_initialize
+ *
+ * Description:
+ * Initialize CPU interrupts
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_cpuint_initialize(void)
+{
+ uintptr_t regaddr;
+ uint8_t *intmap;
+ int i;
+
+ /* Disable all CPU interrupts on this CPU */
+
+ xtensa_disable_all();
+
+ /* Detach all peripheral sources PRO CPU interrupts */
+
+ for (i = 0; i < ESP32S3_NPERIPHERALS; i++)
+ {
+ regaddr = CORE0_MAP_REGADDR(i);
+
+ putreg32(NO_CPUINT, regaddr);
+ }
+
+ /* Initialize CPU interrupt-to-IRQ mapping table */
+
+ intmap = g_cpu0_intmap;
+
+ /* Indicate that no peripheral interrupts are assigned to CPU interrupts */
+
+ memset(intmap, CPUINT_UNASSIGNED, ESP32S3_NCPUINTS);
+
+ /* Special case the 6 internal interrupts.
+ *
+ * CPU interrupt bit IRQ number
+ * --------------------------- ---------------------
+ * ESP32S3_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0
+ * ESP32S3_CPUINT_SOFTWARE0 7 Not yet defined
+ * ESP32S3_CPUINT_PROFILING 11 Not yet defined
+ * ESP32S3_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1
+ * ESP32S3_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2
+ * ESP32S3_CPUINT_SOFTWARE1 29 Not yet defined
+ */
+
+ intmap[ESP32S3_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0);
+ intmap[ESP32S3_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1);
+ intmap[ESP32S3_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup_irq
+ *
+ * Description:
+ * This function sets up the IRQ. It allocates a CPU interrupt of the given
+ * priority and type and attaches it to the given peripheral.
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * periphid - The peripheral number from irq.h to be assigned to
+ * a CPU interrupt.
+ * priority - Interrupt's priority (1 - 5).
+ * type - Interrupt's type (level or edge).
+ *
+ * Returned Value:
+ * The allocated CPU interrupt on success, a negated errno value on
+ * failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_setup_irq(int cpu, int periphid, int priority, int type)
+{
+ irqstate_t irqstate;
+ uintptr_t regaddr;
+ uint8_t *intmap;
+ int irq;
+ int cpuint;
+
+ irqstate = enter_critical_section();
+
+ /* Setting up an IRQ includes the following steps:
+ * 1. Allocate a CPU interrupt.
+ * 2. Attach that CPU interrupt to the peripheral.
+ * 3. Map the CPU interrupt to the IRQ to ease searching later.
+ */
+
+ cpuint = esp32s3_alloc_cpuint(priority, type);
+ if (cpuint < 0)
+ {
+ irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d",
+ priority, type);
+ leave_critical_section(irqstate);
+
+ return cpuint;
+ }
+
+ irq = ESP32S3_PERIPH2IRQ(periphid);
+
+ DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS);
+ DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX);
+
+ esp32s3_intinfo(cpu, periphid, ®addr, &intmap);
+
+ DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED);
+
+ intmap[cpuint] = CPUINT_ASSIGN(periphid + XTENSA_IRQ_FIRSTPERIPH);
+ g_irqmap[irq] = IRQ_MKMAP(cpu, cpuint);
+
+ putreg32(cpuint, regaddr);
+
+ leave_critical_section(irqstate);
+
+ return cpuint;
+}
+
+/****************************************************************************
+ * Name: esp32s3_teardown_irq
+ *
+ * Description:
+ * This function undoes the operations done by esp32s3_setup_irq.
+ * It detaches a peripheral interrupt from a CPU interrupt and frees the
+ * CPU interrupt.
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * periphid - The peripheral number from irq.h to be detached from the
+ * CPU interrupt.
+ * cpuint - The CPU interrupt from which the peripheral interrupt will
+ * be detached.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_teardown_irq(int cpu, int periphid, int cpuint)
+{
+ irqstate_t irqstate;
+ uintptr_t regaddr;
+ uint8_t *intmap;
+ int irq;
+
+ irqstate = enter_critical_section();
+
+ /* Tearing down an IRQ includes the following steps:
+ * 1. Free the previously allocated CPU interrupt.
+ * 2. Detach the interrupt from the peripheral.
+ * 3. Unmap the IRQ from the IRQ-to-cpuint map.
+ */
+
+ esp32s3_free_cpuint(cpuint);
+
+ irq = ESP32S3_PERIPH2IRQ(periphid);
+
+ DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS);
+
+ esp32s3_intinfo(cpu, periphid, ®addr, &intmap);
+
+ DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED);
+ intmap[cpuint] = CPUINT_UNASSIGNED;
+ g_irqmap[irq] = IRQ_UNMAPPED;
+
+ putreg32(NO_CPUINT, regaddr);
+
+ leave_critical_section(irqstate);
+}
+
+/****************************************************************************
+ * Name: xtensa_int_decode
+ *
+ * Description:
+ * Determine the peripheral that generated the interrupt and dispatch
+ * handling to the registered interrupt handler via xtensa_irq_dispatch().
+ *
+ * Input Parameters:
+ * cpuints - Set of pending interrupts valid for this level
+ * regs - Saves processor state on the stack
+ *
+ * Returned Value:
+ * Normally the same value as regs is returned. But, in the event of an
+ * interrupt level context switch, the returned value will, instead point
+ * to the saved processor state in the TCB of the newly started task.
+ *
+ ****************************************************************************/
+
+uint32_t *xtensa_int_decode(uint32_t cpuints, uint32_t *regs)
+{
+ uint8_t *intmap;
+ uint32_t mask;
+ int bit;
+
+#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY
+ board_autoled_on(LED_CPU);
+#endif
+
+ intmap = g_cpu0_intmap;
+
+ /* Skip over zero bits, eight at a time */
+
+ for (bit = 0, mask = 0xff;
+ bit < ESP32S3_NCPUINTS && (cpuints & mask) == 0;
+ bit += 8, mask <<= 8);
+
+ /* Process each pending CPU interrupt */
+
+ for (; bit < ESP32S3_NCPUINTS && cpuints != 0; bit++)
+ {
+ mask = 1 << bit;
+ if ((cpuints & mask) != 0)
+ {
+ /* Extract the IRQ number from the mapping table */
+
+ uint8_t irq = CPUINT_GETIRQ(intmap[bit]);
+
+ DEBUGASSERT(CPUINT_GETEN(intmap[bit]));
+ DEBUGASSERT(irq != CPUINT_UNASSIGNED);
+
+ /* Clear software or edge-triggered interrupt */
+
+ xtensa_intclear(mask);
+
+ /* Dispatch the CPU interrupt.
+ *
+ * NOTE that regs may be altered in the case of an interrupt
+ * level context switch.
+ */
+
+ regs = xtensa_irq_dispatch((int)irq, regs);
+
+ /* Clear the bit in the pending interrupt so that perhaps
+ * we can exit the look early.
+ */
+
+ cpuints &= ~mask;
+ }
+ }
+
+ return regs;
+}
+
diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.h b/arch/xtensa/src/esp32s3/esp32s3_irq.h
new file mode 100644
index 0000000..2ef8f26
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_irq.h
@@ -0,0 +1,123 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_irq.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <arch/irq.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/* CPU interrupt types. */
+
+#define ESP32S3_CPUINT_LEVEL 0
+#define ESP32S3_CPUINT_EDGE 1
+
+/****************************************************************************
+ * Public Functions Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_cpuint_initialize
+ *
+ * Description:
+ * Initialize CPU interrupts
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success; A negated errno value is returned on
+ * any failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_cpuint_initialize(void);
+
+/****************************************************************************
+ * Name: esp32s3_setup_irq
+ *
+ * Description:
+ * This function sets up the IRQ. It allocates a CPU interrupt of the given
+ * priority and type and attaches it to the given peripheral.
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * periphid - The peripheral number from irq.h to be assigned to
+ * a CPU interrupt.
+ * priority - Interrupt's priority (1 - 5).
+ * type - Interrupt's type (level or edge).
+ *
+ * Returned Value:
+ * The allocated CPU interrupt on success, a negated errno value on
+ * failure.
+ *
+ ****************************************************************************/
+
+int esp32s3_setup_irq(int cpu, int periphid, int priority, int type);
+
+/****************************************************************************
+ * Name: esp32s3_teardown_irq
+ *
+ * Description:
+ * This function undoes the operations done by esp32s3_setup_irq.
+ * It detaches a peripheral interrupt from a CPU interrupt and frees the
+ * CPU interrupt.
+ *
+ * Input Parameters:
+ * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
+ * periphid - The peripheral number from irq.h to be detached from the
+ * CPU interrupt.
+ * cpuint - The CPU interrupt from which the peripheral interrupt will
+ * be detached.
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_teardown_irq(int cpu, int periphid, int cpuint);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_lowputc.c b/arch/xtensa/src/esp32s3/esp32s3_lowputc.c
new file mode 100644
index 0000000..a1a8650
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_lowputc.c
@@ -0,0 +1,846 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <arch/irq.h>
+
+#include "chip.h"
+#include "xtensa.h"
+
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_soc.h"
+
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_config.h"
+#include "esp32s3_gpio.h"
+
+#include "esp32s3_lowputc.h"
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef HAVE_UART_DEVICE
+
+#ifdef CONFIG_ESP32S3_UART0
+
+struct esp32s3_uart_s g_uart0_config =
+{
+ .periph = ESP32S3_PERIPH_UART0,
+ .id = 0,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART0,
+ .baud = CONFIG_UART0_BAUD,
+ .bits = CONFIG_UART0_BITS,
+ .parity = CONFIG_UART0_PARITY,
+ .stop_b2 = CONFIG_UART0_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART0_TXPIN,
+ .txsig = U0TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART0_RXPIN,
+ .rxsig = U0RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART0_RTSPIN,
+ .rtssig = U0RTS_OUT_IDX,
+#ifdef CONFIG_UART0_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART0_CTSPIN,
+ .ctssig = U0CTS_IN_IDX,
+#ifdef CONFIG_UART0_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART0 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+struct esp32s3_uart_s g_uart1_config =
+{
+ .periph = ESP32S3_PERIPH_UART1,
+ .id = 1,
+ .cpuint = -ENOMEM,
+ .irq = ESP32S3_IRQ_UART1,
+ .baud = CONFIG_UART1_BAUD,
+ .bits = CONFIG_UART1_BITS,
+ .parity = CONFIG_UART1_PARITY,
+ .stop_b2 = CONFIG_UART1_2STOP,
+ .int_pri = ESP32S3_INT_PRIO_DEF,
+ .txpin = CONFIG_ESP32S3_UART1_TXPIN,
+ .txsig = U1TXD_OUT_IDX,
+ .rxpin = CONFIG_ESP32S3_UART1_RXPIN,
+ .rxsig = U1RXD_IN_IDX,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rtspin = CONFIG_ESP32S3_UART1_RTSPIN,
+ .rtssig = U1RTS_OUT_IDX,
+#ifdef CONFIG_UART1_IFLOWCONTROL
+ .iflow = true, /* input flow control (RTS) enabled */
+#else
+ .iflow = false, /* input flow control (RTS) disabled */
+#endif
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ .ctspin = CONFIG_ESP32S3_UART1_CTSPIN,
+ .ctssig = U1CTS_IN_IDX,
+#ifdef CONFIG_UART1_OFLOWCONTROL
+ .oflow = true, /* output flow control (CTS) enabled */
+#else
+ .oflow = false, /* output flow control (CTS) disabled */
+#endif
+#endif
+};
+
+#endif /* CONFIG_ESP32S3_UART1 */
+#endif /* HAVE_UART_DEVICE */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable)
+{
+ uint32_t mask;
+ if (enable)
+ {
+ /* Enable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), 0, UART_RX_FLOW_EN);
+
+ /* Configure the threshold */
+
+ mask = VALUE_TO_FIELD(threshold, UART_RX_FLOW_THRHD);
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_RX_FLOW_THRHD_M, mask);
+ }
+ else
+ {
+ /* Disable RX flow control */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable)
+{
+ if (enable)
+ {
+ /* Enable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), 0, UART_TX_FLOW_EN);
+ }
+ else
+ {
+ /* Disable TX flow control */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TX_FLOW_EN, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RST_CORE_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_TX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv)
+{
+ uint32_t set_bit = 1 << UART_RX_RST_CORE_S;
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, set_bit);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_RST_CORE_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M,
+ 1 << UART_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M,
+ 1 << UART_RX_SCLK_EN_S);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M,
+ 1 << UART_TX_SCLK_EN_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_RX_SCLK_EN_M, 0);
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_TX_SCLK_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source)
+{
+ uint32_t clk = (uint32_t)source << UART_SCLK_SEL_S;
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_SEL_M, clk);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s * priv)
+{
+ uint32_t clk_conf_reg;
+ uint32_t ret = -ENODATA;
+ clk_conf_reg = getreg32(UART_CLK_CONF_REG(priv->id));
+ clk_conf_reg &= UART_SCLK_SEL_M;
+ clk_conf_reg >>= UART_SCLK_SEL_S;
+ switch (clk_conf_reg)
+ {
+ case 1:
+ ret = esp_clk_apb_freq();
+ break;
+ case 2:
+ ret = RTC_CLK_FREQ;
+ break;
+ case 3:
+ ret = XTAL_CLK_FREQ;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s * priv)
+{
+ int sclk_div;
+ uint32_t sclk_freq;
+ uint32_t clk_div;
+ uint32_t int_part;
+ uint32_t frag_part;
+
+ /* Get serial clock */
+
+ sclk_freq = esp32s3_lowputc_get_sclk(priv);
+
+ /* Calculate integral part of the frequency divider factor.
+ * For low baud rates, the sclk must be less than half.
+ * For high baud rates, the sclk must be the higher.
+ */
+
+ sclk_div = DIV_UP(sclk_freq, MAX_UART_CLKDIV * priv->baud);
+
+ /* Calculate the clock divisor to achieve the baud rate.
+ * baud = f/clk_div
+ * f = sclk_freq/sclk_div
+ * clk_div = 16*int_part + frag_part
+ * 16*int_part + frag_part = 16*(sclk_freq/sclk_div)/baud
+ */
+
+ clk_div = (sclk_freq << 4) / (priv->baud * sclk_div);
+
+ /* Get the integer part of it. */
+
+ int_part = clk_div >> 4;
+
+ /* Get the frag part of it. */
+
+ frag_part = clk_div & 0xf;
+
+ /* Set integer part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_M, int_part);
+
+ /* Set decimal part of the clock divisor for baud rate. */
+
+ modifyreg32(UART_CLKDIV_REG(priv->id), UART_CLKDIV_FRAG_M,
+ (frag_part & UART_CLKDIV_FRAG_V) << UART_CLKDIV_FRAG_S);
+
+ /* Set the the integral part of the frequency divider factor. */
+
+ modifyreg32(UART_CLK_CONF_REG(priv->id), UART_SCLK_DIV_NUM_M,
+ (sclk_div - 1) << UART_SCLK_DIV_NUM_S);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s * priv)
+{
+ /* Disable RS485 mode */
+
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485TX_RX_EN_M, 0);
+ modifyreg32(UART_RS485_CONF_REG(priv->id), UART_RS485RXBY_TX_EN_M, 0);
+
+ /* Disable IRDA mode */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_IRDA_EN_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s * priv)
+{
+ if (priv->parity == UART_PARITY_DISABLE)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M, 0);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_M,
+ (priv->parity & 0x1) << UART_PARITY_S);
+ modifyreg32(UART_CONF0_REG(priv->id), UART_PARITY_EN_M,
+ 1 << UART_PARITY_EN_S);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_data_length
+ *
+ * Description:
+ * Set the data bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+int esp32s3_lowputc_data_length(const struct esp32s3_uart_s * priv)
+{
+ int ret = OK;
+ uint32_t length = priv->bits - 5;
+
+ /* If it is the allowed range */
+
+ if (length >= UART_DATA_5_BITS && length <= UART_DATA_8_BITS)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_BIT_NUM_M,
+ length << UART_BIT_NUM_S);
+ }
+ else
+ {
+ ret = -EINVAL;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_stop_length
+ *
+ * Description:
+ * Set the stop bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_stop_length(const struct esp32s3_uart_s *priv)
+{
+ if (priv->stop_b2 == 0)
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
+ UART_STOP_BITS_1 << UART_STOP_BIT_NUM_S);
+ }
+ else
+ {
+ modifyreg32(UART_CONF0_REG(priv->id), UART_STOP_BIT_NUM_M,
+ UART_STOP_BITS_2 << UART_STOP_BIT_NUM_S);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_tx_idle_time
+ *
+ * Description:
+ * Set the idle time between transfers.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * time - Desired time interval between the transfers.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_tx_idle_time(const struct esp32s3_uart_s *priv,
+ uint32_t time)
+{
+ time = time << UART_TX_IDLE_NUM_S;
+ time = time & UART_TX_IDLE_NUM_M; /* Just in case value overloads */
+ modifyreg32(UART_IDLE_CONF_REG(priv->id), UART_TX_IDLE_NUM_M,
+ time);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_send_byte
+ *
+ * Description:
+ * Send one byte.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * byte - Byte to be sent.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s * priv,
+ char byte)
+{
+ putreg32((uint32_t) byte, UART_FIFO_REG(priv->id));
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_is_tx_fifo_full
+ *
+ * Description:
+ * Verify if TX FIFO is full.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * True if it is full, otherwise false.
+ *
+ ****************************************************************************/
+
+bool esp32s3_lowputc_is_tx_fifo_full(const struct esp32s3_uart_s *priv)
+{
+ uint32_t reg;
+
+ reg = getreg32(UART_STATUS_REG(priv->id));
+ reg = reg >> UART_TXFIFO_CNT_S;
+ reg = reg & UART_TXFIFO_CNT_V;
+
+ return !(reg < (UART_TX_FIFO_SIZE - 1));
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_peripheral
+ *
+ * Description:
+ * Reset the UART peripheral by using System reg.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_peripheral(const struct esp32s3_uart_s *priv)
+{
+ if (priv->id == 0)
+ {
+ modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M,
+ SYSTEM_UART_RST_M);
+ modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART_RST_M, 0);
+ }
+ else
+ {
+ modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M,
+ SYSTEM_UART1_RST_M);
+ modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_UART1_RST_M, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_txfifo
+ *
+ * Description:
+ * Reset TX FIFO.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_txfifo(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M,
+ UART_TXFIFO_RST_M);
+ modifyreg32(UART_CONF0_REG(priv->id), UART_TXFIFO_RST_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rxfifo
+ *
+ * Description:
+ * Reset RX FIFO.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rxfifo(const struct esp32s3_uart_s *priv)
+{
+ modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M,
+ UART_RXFIFO_RST_M);
+ modifyreg32(UART_CONF0_REG(priv->id), UART_RXFIFO_RST_M, 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_all_uart_int
+ *
+ * Description:
+ * Disable all UART interrupts.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * current_status - Pointer to a variable to store the current status of
+ * the interrupt enable register before disabling
+ * UART interrupts.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_all_uart_int(const struct esp32s3_uart_s *priv,
+ uint32_t *current_status)
+{
+ irqstate_t flags;
+
+ flags = enter_critical_section();
+
+ if (current_status != NULL)
+ {
+ /* Save current status */
+
+ *current_status = getreg32(UART_INT_ENA_REG(priv->id));
+ }
+
+ /* Disable all UART int */
+
+ putreg32(0, UART_INT_ENA_REG(priv->id));
+
+ /* Clear all ints */
+
+ putreg32(0xffffffff, UART_INT_CLR_REG(priv->id));
+
+ leave_critical_section(flags);
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_restore_all_uart_int
+ *
+ * Description:
+ * Restore all UART interrupts.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * last_status - Pointer to a variable that stored the last state of the
+ * interrupt enable register.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_restore_all_uart_int(const struct esp32s3_uart_s *priv,
+ uint32_t *last_status)
+{
+ /* Restore the previous behaviour */
+
+ putreg32(*last_status, UART_INT_ENA_REG(priv->id));
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_config_pins
+ *
+ * Description:
+ * Configure TX and RX UART pins.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_config_pins(const struct esp32s3_uart_s *priv)
+{
+ /* Configure the pins */
+
+ esp32s3_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0);
+ esp32s3_configgpio(priv->txpin, OUTPUT_FUNCTION_1);
+
+ esp32s3_configgpio(priv->rxpin, INPUT_FUNCTION_1);
+ esp32s3_gpio_matrix_in(priv->rxpin, priv->rxsig, 0);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ if (priv->iflow)
+ {
+ esp32s3_configgpio(priv->rtspin, OUTPUT_FUNCTION_1);
+ esp32s3_gpio_matrix_out(priv->rtspin, priv->rtssig,
+ 0, 0);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ if (priv->oflow)
+ {
+ esp32s3_configgpio(priv->ctspin, INPUT_FUNCTION_1);
+ esp32s3_gpio_matrix_in(priv->ctspin, priv->ctssig, 0);
+ }
+#endif
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_restore_pins
+ *
+ * Description:
+ * Configure both pins back to INPUT mode and detach the TX pin from the
+ * output signal and the RX pin from the input signal.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_restore_pins(const struct esp32s3_uart_s *priv)
+{
+ /* Configure the pins */
+
+ esp32s3_configgpio(priv->txpin, INPUT);
+ esp32s3_gpio_matrix_out(priv->txpin, MATRIX_DETACH_OUT_SIG, false, false);
+
+ esp32s3_configgpio(priv->rxpin, INPUT);
+ esp32s3_gpio_matrix_in(priv->rxpin, MATRIX_DETACH_IN_LOW_PIN, false);
+}
+
+/****************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ * Output one byte on the serial console.
+ *
+ * Parameters:
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+void up_lowputc(char ch)
+{
+#ifdef CONSOLE_UART
+
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+ struct esp32s3_uart_s *priv = &g_uart0_config;
+#elif defined (CONFIG_UART1_SERIAL_CONSOLE)
+ struct esp32s3_uart_s *priv = &g_uart1_config;
+#endif
+
+ /* Wait until the TX FIFO has space to insert new char */
+
+ while (esp32s3_lowputc_is_tx_fifo_full(priv));
+
+ /* Then send the character */
+
+ esp32s3_lowputc_send_byte(priv, ch);
+
+#elif defined (CONFIG_ESP32S3_USBSERIAL)
+ esp32s3_usbserial_write(ch);
+#endif /* CONSOLE_UART */
+}
+
+/****************************************************************************
+ * Name: esp32s3_lowsetup
+ *
+ * Description:
+ * This performs only the basic configuration for UART pins.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowsetup(void)
+{
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+
+#ifdef CONFIG_ESP32S3_UART0
+
+ esp32s3_lowputc_config_pins(&g_uart0_config);
+
+#endif
+
+#ifdef CONFIG_ESP32S3_UART1
+
+ esp32s3_lowputc_config_pins(&g_uart1_config);
+
+#endif
+
+#endif /* !CONFIG_SUPPRESS_UART_CONFIG */
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_lowputc.h b/arch/xtensa/src/esp32s3/esp32s3_lowputc.h
new file mode 100644
index 0000000..226fa7b
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_lowputc.h
@@ -0,0 +1,485 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_lowputc.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_gpio_sigmap.h"
+
+#include "esp32s3_irq.h"
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+enum uart_sclk
+{
+ APB_CLK = 1, /* 80 MHz */
+ CLK_8, /* 8 MHz */
+ XTAL_CLK
+};
+
+enum uart_parity
+{
+ UART_PARITY_DISABLE,
+ UART_PARITY_ODD,
+ UART_PARITY_EVEN
+};
+
+enum uart_data_length
+{
+ UART_DATA_5_BITS,
+ UART_DATA_6_BITS,
+ UART_DATA_7_BITS,
+ UART_DATA_8_BITS
+};
+
+enum uart_stop_length
+{
+ UART_STOP_BITS_1 = 0x1, /* Stop bit: 1 bit */
+ UART_STOP_BITS_2 = 0x3, /* Stop bit: 2 bits */
+};
+
+/* Default FIFOs size */
+
+#define UART_TX_FIFO_SIZE 128
+#define UART_RX_FIFO_SIZE 128
+
+/* Maximum serial clock divisor for integer part */
+
+#define MAX_UART_CLKDIV (BIT(12) - 1)
+#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
+
+/* Struct used to store uart driver information and to
+ * manipulate uart driver
+ */
+
+struct esp32s3_uart_s
+{
+ uint8_t periph; /* UART peripheral ID */
+ int cpuint; /* CPU interrupt assigned to this UART */
+ uint8_t id; /* UART ID */
+ uint8_t irq; /* IRQ associated with this UART */
+ uint8_t cpu; /* CPU ID */
+ uint32_t baud; /* Configured baud rate */
+ uint8_t bits; /* Data length (5 to 8 bits). */
+ uint8_t parity; /* 0=no parity, 1=odd parity, 2=even parity */
+ uint8_t stop_b2; /* Use 2 stop bits? 0 = no (use 1) 1 = yes (use 2) */
+ uint8_t int_pri; /* UART Interrupt Priority */
+ uint8_t txpin; /* TX pin */
+ uint8_t txsig; /* TX signal */
+ uint8_t rxpin; /* RX pin */
+ uint8_t rxsig; /* RX signal */
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ uint8_t rtspin; /* RTS pin number */
+ uint8_t rtssig; /* RTS signal */
+ bool iflow; /* Input flow control (RTS) enabled */
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ uint8_t ctspin; /* CTS pin number */
+ uint8_t ctssig; /* CTS signal */
+ bool oflow; /* Output flow control (CTS) enabled */
+#endif
+};
+
+extern struct esp32s3_uart_s g_uart0_config;
+extern struct esp32s3_uart_s g_uart1_config;
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_iflow
+ *
+ * Description:
+ * Configure the input hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * threshold - RX FIFO value from which RST will automatically be
+ * asserted.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_iflow(const struct esp32s3_uart_s *priv,
+ uint8_t threshold, bool enable);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_oflow
+ *
+ * Description:
+ * Configure the output hardware flow control.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * enable - true = enable, false = disable
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_oflow(const struct esp32s3_uart_s *priv,
+ bool enable);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_reset_core
+ *
+ * Description:
+ * Reset both TX and RX cores.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_reset_cores(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_tx
+ *
+ * Description:
+ * Reset TX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_tx(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rx
+ *
+ * Description:
+ * Reset RX core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rx(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_enable_sclk
+ *
+ * Description:
+ * Enable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_enable_sclk(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_sclk
+ *
+ * Description:
+ * Disable clock for whole core.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_sclk(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_sclk
+ *
+ * Description:
+ * Set a source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * source - APB_CLK = 1 80 MHz
+ * CLK_8 = 2 8 MHz
+ * XTAL_CLK = 3
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_sclk(const struct esp32s3_uart_s *priv,
+ enum uart_sclk source);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_get_sclk
+ *
+ * Description:
+ * Get the source clock for UART.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * The frequency of the clock in Hz.
+ *
+ ****************************************************************************/
+
+uint32_t esp32s3_lowputc_get_sclk(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_baud
+ *
+ * Description:
+ * Set the baud rate according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_baud(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_normal_mode
+ *
+ * Description:
+ * Set the UART to operate in normal mode, i.e., disable the RS485 mode and
+ * IRDA mode.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_normal_mode(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_parity
+ *
+ * Description:
+ * Set the parity, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_parity(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_data_length
+ *
+ * Description:
+ * Set the data bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+int esp32s3_lowputc_data_length(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_stop_length
+ *
+ * Description:
+ * Set the stop bits length, according to the value in the private driver
+ * struct.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_stop_length(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_set_tx_idle_time
+ *
+ * Description:
+ * Set the idle time between transfers.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * time - Desired time interval between the transfers.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_set_tx_idle_time(const struct esp32s3_uart_s *priv,
+ uint32_t time);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_send_byte
+ *
+ * Description:
+ * Send one byte.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * byte - Byte to be sent.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s *priv,
+ char byte);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_is_tx_fifo_full
+ *
+ * Description:
+ * Verify if TX FIFO is full.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ * Returned Value:
+ * True if it is full, otherwise false.
+ *
+ ****************************************************************************/
+
+bool esp32s3_lowputc_is_tx_fifo_full(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_peripheral
+ *
+ * Description:
+ * Reset the UART peripheral by using System reg.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_peripheral(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_txfifo
+ *
+ * Description:
+ * Reset TX FIFO.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_txfifo(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_rst_rxfifo
+ *
+ * Description:
+ * Reset RX FIFO.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_rst_rxfifo(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_disable_all_uart_int
+ *
+ * Description:
+ * Disable all UART interrupts.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * current_status - Pointer to a variable to store the current status of
+ * the interrupt enable register before disabling
+ * UART interrupts.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_disable_all_uart_int(const struct esp32s3_uart_s *priv,
+ uint32_t *current_status);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_restore_all_uart_int
+ *
+ * Description:
+ * Restore all UART interrupts.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ * last_status - Pointer to a variable that stored the last state of the
+ * interrupt enable register.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_restore_all_uart_int(const struct esp32s3_uart_s *priv,
+ uint32_t * last_status);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_config_pins
+ *
+ * Description:
+ * Configure TX and RX UART pins.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_config_pins(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowputc_restore_pins
+ *
+ * Description:
+ * Configure both pins back to INPUT mode and detach the TX pin from the
+ * output signal and the RX pin from the input signal.
+ *
+ * Parameters:
+ * priv - Pointer to the private driver struct.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowputc_restore_pins(const struct esp32s3_uart_s *priv);
+
+/****************************************************************************
+ * Name: esp32s3_lowsetup
+ *
+ * Description:
+ * This performs basic initialization of the UART used for the serial
+ * console. Its purpose is to get the console output available as soon
+ * as possible.
+ *
+ ****************************************************************************/
+
+void esp32s3_lowsetup(void);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_LOWPUTC_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_region.c b/arch/xtensa/src/esp32s3/esp32s3_region.c
new file mode 100644
index 0000000..fd1382d
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_region.c
@@ -0,0 +1,102 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_region.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const uint32_t g_protected_pages[] =
+{
+ 0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000
+};
+
+#define NPROTECTED_PAGES (sizeof(g_protected_pages)/sizeof(uint32_t))
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: xtensa_write_dtlb and xtensa_write_itlb
+ *
+ * Description:
+ * Functions to set page attributes for Region Protection option in the
+ * CPU. See Xtensa ISA Reference manual for explanation of arguments
+ * (section 4.6.3.2).
+ *
+ ****************************************************************************/
+
+static inline void xtensa_write_dtlb(uint32_t vpn, uint32_t attr)
+{
+ __asm__ __volatile__
+ (
+ "wdtlb %1, %0\n"
+ "dsync\n"
+ : : "r" (vpn), "r" (attr)
+ );
+}
+
+static inline void xtensa_write_itlb(uint32_t vpn, uint32_t attr)
+{
+ __asm__ __volatile__
+ (
+ "witlb %1, %0\n"
+ "isync\n"
+ : : "r" (vpn), "r" (attr)
+ );
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_region_protection
+ *
+ * Description:
+ * Make page 0 access raise an exception. Also protect some other unused
+ * pages so we can catch weirdness.
+ *
+ * Useful attribute values:
+ * 0 — cached, RW
+ * 2 — bypass cache, RWX (default value after CPU reset)
+ * 15 — no access, raise exception
+ *
+ ****************************************************************************/
+
+void esp32s3_region_protection(void)
+{
+ int i;
+
+ for (i = 0; i < NPROTECTED_PAGES; ++i)
+ {
+ xtensa_write_dtlb(g_protected_pages[i], 0xf);
+ xtensa_write_itlb(g_protected_pages[i], 0xf);
+ }
+
+ xtensa_write_dtlb(0x20000000, 0);
+ xtensa_write_itlb(0x20000000, 0);
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_region.h b/arch/xtensa/src/esp32s3/esp32s3_region.h
new file mode 100644
index 0000000..279a888
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_region.h
@@ -0,0 +1,52 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_region.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_REGION_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_REGION_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_region_protection
+ *
+ * Description:
+ * Make page 0 access raise an exception. Also protect some other unused
+ * pages so we can catch weirdness.
+ *
+ * Useful attribute values:
+ * 0 — cached, RW
+ * 2 — bypass cache, RWX (default value after CPU reset)
+ * 15 — no access, raise exception
+ *
+ ****************************************************************************/
+
+void esp32s3_region_protection(void);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_REGION_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_serial.c b/arch/xtensa/src/esp32s3/esp32s3_serial.c
new file mode 100644
index 0000000..18dadff
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_serial.c
@@ -0,0 +1,1166 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_serial.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/serial/serial.h>
+#include <nuttx/fs/ioctl.h>
+
+#include <sys/types.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <string.h>
+#include <assert.h>
+#include <errno.h>
+#include <debug.h>
+
+#ifdef CONFIG_SERIAL_TERMIOS
+# include <termios.h>
+#endif
+
+#include "xtensa.h"
+#include "chip.h"
+
+#include "hardware/esp32s3_uart.h"
+#include "hardware/esp32s3_system.h"
+
+#include "esp32s3_config.h"
+#include "esp32s3_irq.h"
+#include "esp32s3_lowputc.h"
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# include "esp32s3_usbserial.h"
+#endif
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* The console is enabled, and it's not the syslog device,
+ * so, it should be a serial device.
+ */
+
+#ifdef USE_SERIALDRIVER
+
+/* Which UART with be tty0/console and which tty1? */
+
+/* First pick the console and ttys0.
+ * Console can be UART0 or UART1, but will always be ttys0.
+ */
+
+/* In case a UART was assigned to be
+ * the console and the corresponding peripheral was also selected.
+ */
+
+#ifdef CONSOLE_UART
+# if defined(CONFIG_UART0_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart0_dev /* UART0 is console */
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+# define CONSOLE_DEV g_uart1_dev /* UART1 is console */
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif /* CONFIG_UART0_SERIAL_CONSOLE */
+#else /* No UART console */
+# undef CONSOLE_DEV
+# if defined(CONFIG_ESP32S3_UART0)
+# define TTYS0_DEV g_uart0_dev /* UART0 is ttyS0 */
+# define UART0_ASSIGNED 1
+# elif defined(CONFIG_ESP32S3_UART1)
+# define TTYS0_DEV g_uart1_dev /* UART1 is ttyS0 */
+# define UART1_ASSIGNED 1
+# endif
+#endif /* CONSOLE_UART */
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+# define CONSOLE_DEV g_uart_usbserial
+# define TTYACM0_DEV g_uart_usbserial
+#endif
+
+/* Pick ttys1 */
+
+#if defined(CONFIG_ESP32S3_UART0) && !defined(UART0_ASSIGNED)
+# define TTYS1_DEV g_uart0_dev /* UART0 is ttyS1 */
+# define UART0_ASSIGNED 1
+#elif defined(CONFIG_ESP32S3_UART1) && !defined(UART1_ASSIGNED)
+# define TTYS1_DEV g_uart1_dev /* UART1 is ttyS1 */
+# define UART1_ASSIGNED 1
+#endif
+
+#ifdef HAVE_UART_DEVICE
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Serial driver methods */
+
+static int esp32s3_setup(struct uart_dev_s *dev);
+static void esp32s3_shutdown(struct uart_dev_s *dev);
+static int esp32s3_attach(struct uart_dev_s *dev);
+static void esp32s3_detach(struct uart_dev_s *dev);
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable);
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable);
+static bool esp32s3_rxavailable(struct uart_dev_s *dev);
+static bool esp32s3_txready(struct uart_dev_s *dev);
+static bool esp32s3_txempty(struct uart_dev_s *dev);
+static void esp32s3_send(struct uart_dev_s *dev, int ch);
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status);
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg);
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper);
+#endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/* Operations */
+
+static struct uart_ops_s g_uart_ops =
+{
+ .setup = esp32s3_setup,
+ .shutdown = esp32s3_shutdown,
+ .attach = esp32s3_attach,
+ .detach = esp32s3_detach,
+ .txint = esp32s3_txint,
+ .rxint = esp32s3_rxint,
+ .rxavailable = esp32s3_rxavailable,
+ .txready = esp32s3_txready,
+ .txempty = esp32s3_txempty,
+ .send = esp32s3_send,
+ .receive = esp32s3_receive,
+ .ioctl = esp32s3_ioctl,
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ .rxflowcontrol = esp32s3_rxflowcontrol,
+#endif
+};
+
+/* UART 0 */
+
+#ifdef CONFIG_ESP32S3_UART0
+
+static char g_uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
+static char g_uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart0_dev =
+{
+#ifdef CONFIG_UART0_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART0_TXBUFSIZE,
+ .buffer = g_uart0_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART0_RXBUFSIZE,
+ .buffer = g_uart0_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart0_config
+};
+
+#endif
+
+/* UART 1 */
+
+#ifdef CONFIG_ESP32S3_UART1
+
+static char g_uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
+static char g_uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
+
+/* Fill only the requested fields */
+
+static uart_dev_t g_uart1_dev =
+{
+#ifdef CONFIG_UART1_SERIAL_CONSOLE
+ .isconsole = true,
+#else
+ .isconsole = false,
+#endif
+ .xmit =
+ {
+ .size = CONFIG_UART1_TXBUFSIZE,
+ .buffer = g_uart1_txbuffer,
+ },
+ .recv =
+ {
+ .size = CONFIG_UART1_RXBUFSIZE,
+ .buffer = g_uart1_rxbuffer,
+ },
+
+ .ops = &g_uart_ops,
+ .priv = &g_uart1_config
+};
+
+#endif
+
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_UART
+
+/****************************************************************************
+ * Name: uart_interrupt
+ *
+ * Description:
+ * This is the UART interrupt handler. It will be invoked when an
+ * interrupt is received on the 'irq' It should call uart_xmitchars or
+ * uart_recvchars to perform the appropriate data transfers. The
+ * interrupt handling logic must be able to map the 'irq' number into the
+ * appropriate uart_dev_s structure in order to call these functions.
+ *
+ ****************************************************************************/
+
+static int uart_handler(int irq, void *context, void *arg)
+{
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t tx_mask = UART_TXFIFO_EMPTY_INT_ST_M | UART_TX_DONE_INT_ST_M;
+ uint32_t rx_mask = UART_RXFIFO_TOUT_INT_ST_M | UART_RXFIFO_FULL_INT_ST_M;
+ uint32_t int_status;
+
+ int_status = getreg32(UART_INT_ST_REG(priv->id));
+
+ /* Tx fifo empty interrupt or UART tx done int */
+
+ if ((int_status & tx_mask) != 0)
+ {
+ uart_xmitchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), tx_mask, tx_mask);
+ }
+
+ /* Rx fifo timeout interrupt or rx fifo full interrupt */
+
+ if ((int_status & rx_mask) != 0)
+ {
+ uart_recvchars(dev);
+ modifyreg32(UART_INT_CLR_REG(priv->id), rx_mask, rx_mask);
+ }
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_setup
+ *
+ * Description:
+ * Configure the UART baud, bits, parity, fifos, etc. This method is
+ * called the first time that the serial port is opened.
+ * For the serial console, this will occur very early in initialization,
+ * for other serial ports this will occur when the port is first opened.
+ * This setup does not include attaching or enabling interrupts.
+ * That portion of the UART setup is performed when the attach() method
+ * is called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned.
+ *
+ ****************************************************************************/
+
+static int esp32s3_setup(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Initialize UART module */
+
+ /* Discard corrupt RX data and
+ * disable UART memory clock gate enable signal.
+ */
+
+ modifyreg32(UART_CONF0_REG(priv->id), UART_ERR_WR_MASK_M |
+ UART_MEM_CLK_EN_M, UART_ERR_WR_MASK_M);
+
+ /* Define 0 as the threshold that means TX FIFO buffer is empty. */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_TXFIFO_EMPTY_THRHD_M, 0);
+
+ /* Define a threshold to trigger an RX FIFO FULL interrupt.
+ * Define just one byte to read data immediately.
+ */
+
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RXFIFO_FULL_THRHD_M,
+ 1 << UART_RXFIFO_FULL_THRHD_S);
+
+ /* Define the maximum FIFO size for RX and TX FIFO.
+ * That means, 1 block = 128 bytes.
+ * As a consequence, software serial FIFO can unload the bytes and
+ * not wait too much on polling activity.
+ */
+
+ modifyreg32(UART_MEM_CONF_REG(priv->id), UART_TX_SIZE_M | UART_RX_SIZE_M,
+ (1 << UART_TX_SIZE_S) | (1 << UART_RX_SIZE_S));
+
+ /* Configure the UART Baud Rate */
+
+ esp32s3_lowputc_baud(priv);
+
+ /* Set a mode */
+
+ esp32s3_lowputc_normal_mode(priv);
+
+ /* Parity */
+
+ esp32s3_lowputc_parity(priv);
+
+ /* Data Frame size */
+
+ esp32s3_lowputc_data_length(priv);
+
+ /* Stop bit */
+
+ esp32s3_lowputc_stop_length(priv);
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ /* Configure the input flow control */
+
+ if (priv->iflow)
+ {
+ /* Enable input flow control and set the RX FIFO threshold
+ * to assert the RTS line to half the RX FIFO buffer.
+ * It will then save some space on the hardware fifo to
+ * remaining bytes that may arrive after RTS be asserted
+ * and before the transmitter stops sending data.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ }
+ else
+ {
+ /* Just disable input flow control, threshold parameter
+ * will be discarded.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , false);
+ }
+
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ /* Configure the ouput flow control */
+
+ if (priv->oflow)
+ {
+ esp32s3_lowputc_set_oflow(priv, true);
+ }
+ else
+ {
+ esp32s3_lowputc_set_oflow(priv, false);
+ }
+#endif
+
+ /* No Tx idle interval */
+
+ esp32s3_lowputc_set_tx_idle_time(priv, 0);
+
+ /* Enable cores */
+
+ esp32s3_lowputc_enable_sclk(priv);
+
+ /* Clear FIFOs */
+
+ esp32s3_lowputc_rst_txfifo(priv);
+ esp32s3_lowputc_rst_rxfifo(priv);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: esp32s3_shutdown
+ *
+ * Description:
+ * Disable the UART. This method is called when the serial port is closed.
+ * This method reverses the operation the setup method. NOTE that the serial
+ * console is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_shutdown(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ /* Disable ints */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, NULL);
+}
+
+/****************************************************************************
+ * Name: esp32s3_attach
+ *
+ * Description:
+ * Configure the UART to operation in interrupt driven mode. This method
+ * is called when the serial port is opened. Normally, this is just after
+ * the the setup() method is called, however, the serial console may
+ * operate in a non-interrupt driven mode during the boot phase.
+ *
+ * RX and TX interrupts are not enabled when by the attach method (unless
+ * the hardware supports multiple levels of interrupt enabling). The RX
+ * and TX interrupts are not enabled until the txint() and rxint() methods
+ * are called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Zero (OK) is returned on success; A negated errno value is returned
+ * to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+
+static int esp32s3_attach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ int ret;
+
+ DEBUGASSERT(priv->cpuint == -ENOMEM);
+
+ /* Set up to receive peripheral interrupts on the current CPU */
+
+ priv->cpu = up_cpu_index();
+ priv->cpuint = esp32s3_setup_irq(0, priv->periph, priv->int_pri,
+ ESP32S3_CPUINT_LEVEL);
+ if (priv->cpuint < 0)
+ {
+ /* Failed to allocate a CPU interrupt of this type */
+
+ return priv->cpuint;
+ }
+
+ /* Attach and enable the IRQ */
+
+ ret = irq_attach(priv->irq, uart_handler, dev);
+ if (ret == OK)
+ {
+ /* Enable the CPU interrupt (RX and TX interrupts are still disabled
+ * in the UART
+ */
+
+ up_enable_irq(priv->irq);
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_detach
+ *
+ * Description:
+ * Detach UART interrupts. This method is called when the serial port is
+ * closed normally just before the shutdown method is called. The
+ * exception is the serial console which is never shutdown.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ ****************************************************************************/
+
+static void esp32s3_detach(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ DEBUGASSERT(priv->cpuint != -ENOMEM);
+
+ /* Disable and detach the CPU interrupt */
+
+ up_disable_irq(priv->irq);
+ irq_detach(priv->irq);
+
+ /* Disassociate the peripheral interrupt from the CPU interrupt */
+
+ esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint);
+ priv->cpuint = -ENOMEM;
+}
+
+/****************************************************************************
+ * Name: esp32s3_txint
+ *
+ * Description:
+ * Enable or disable TX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the TX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_txint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_TXFIFO_EMPTY_INT_ENA_M | UART_TX_DONE_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Set to receive an interrupt when the TX holding register register
+ * is empty
+ */
+
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ /* Disable the TX interrupt */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxint
+ *
+ * Description:
+ * Enable or disable RX interrupts.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * enable - If true enables the RX interrupt, if false disables it.
+ *
+ ****************************************************************************/
+
+static void esp32s3_rxint(struct uart_dev_s *dev, bool enable)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t ints_mask = UART_RXFIFO_TOUT_INT_ENA_M |
+ UART_RXFIFO_FULL_INT_ENA_M;
+
+ if (enable)
+ {
+ /* Receive an interrupt when there is anything in the RX data register
+ * (or an RX timeout occurs).
+ * NOTE: RX timeout feature needs to be enabled.
+ */
+#ifndef CONFIG_SUPPRESS_SERIAL_INTS
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M,
+ UART_RX_TOUT_EN_M);
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, ints_mask);
+#endif
+ }
+ else
+ {
+ modifyreg32(UART_CONF1_REG(priv->id), UART_RX_TOUT_EN_M, 0);
+
+ /* Disable the RX interrupts */
+
+ modifyreg32(UART_INT_ENA_REG(priv->id), ints_mask, 0);
+ }
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxavailable
+ *
+ * Description:
+ * Check if there is any data available to be read.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the RX FIFO is not empty and false if RX FIFO is empty.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_rxavailable(struct uart_dev_s *dev)
+{
+ struct esp32s3_uart_s *priv = dev->priv;
+ uint32_t status_reg;
+ uint32_t bytes;
+
+ status_reg = getreg32(UART_STATUS_REG(priv->id));
+ bytes = status_reg & UART_RXFIFO_CNT_M;
+
+ return (bytes > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txready
+ *
+ * Description:
+ * Check if the transmit hardware is ready to send another byte.
+ * This is used to determine if send() method can be called.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the transmit hardware is ready to send another byte,
+ * false otherwise.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txready(struct uart_dev_s *dev)
+{
+ return !esp32s3_lowputc_is_tx_fifo_full(dev->priv);
+}
+
+/****************************************************************************
+ * Name: esp32s3_txempty
+ *
+ * Description:
+ * Verify if all characters have been sent. If for example, the UART
+ * hardware implements FIFOs, then this would mean the transmit FIFO is
+ * empty. This method is called when the driver needs to make sure that
+ * all characters are "drained" from the TX hardware.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ *
+ * Returned Values:
+ * Return true if the TX FIFO is empty, false if it is not.
+ *
+ ****************************************************************************/
+
+static bool esp32s3_txempty(struct uart_dev_s *dev)
+{
+ uint32_t reg;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ reg = getreg32(UART_INT_RAW_REG(priv->id));
+ reg = reg & UART_TXFIFO_EMPTY_INT_RAW_M;
+
+ return (reg > 0);
+}
+
+/****************************************************************************
+ * Name: esp32s3_send
+ *
+ * Description:
+ * Send a unique character
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * ch - Byte to be sent.
+ *
+ ****************************************************************************/
+
+static void esp32s3_send(struct uart_dev_s *dev, int ch)
+{
+ esp32s3_lowputc_send_byte(dev->priv, ch);
+}
+
+/****************************************************************************
+ * Name: esp32s3_receive
+ *
+ * Description:
+ * Called (usually) from the interrupt level to receive one
+ * character from the UART. Error bits associated with the
+ * receipt are provided in the return 'status'.
+ *
+ * Parameters:
+ * dev - Pointer to the serial driver struct.
+ * status - Pointer to a variable to store eventual error bits.
+ *
+ * Returned Values:
+ * Return the byte read from the RX FIFO.
+ *
+ ****************************************************************************/
+
+static int esp32s3_receive(struct uart_dev_s *dev, unsigned int *status)
+{
+ uint32_t rx_fifo;
+ struct esp32s3_uart_s *priv = dev->priv;
+
+ rx_fifo = getreg32(UART_FIFO_REG(priv->id));
+ rx_fifo = rx_fifo & UART_RXFIFO_RD_BYTE_M;
+
+ /* Since we don't have error bits associated with receipt, we set zero */
+
+ *status = 0;
+
+ return (int)rx_fifo;
+}
+
+/****************************************************************************
+ * Name: esp32s3_ioctl
+ *
+ * Description:
+ * All ioctl calls will be routed through this method.
+ * Here it's employed to implement the TERMIOS ioctls and TIOCSERGSTRUCT.
+ *
+ * Parameters:
+ * filep Pointer to a file structure instance.
+ * cmd The ioctl command.
+ * arg The argument of the ioctl cmd.
+ *
+ * Returned Value:
+ * Returns a non-negative number on success; A negated errno value is
+ * returned on any failure (see comments ioctl() for a list of appropriate
+ * errno values).
+ *
+ ****************************************************************************/
+
+static int esp32s3_ioctl(struct file *filep, int cmd, unsigned long arg)
+{
+ /* Get access to the internal instance of the driver through the file
+ * pointer.
+ */
+
+#if defined(CONFIG_SERIAL_TERMIOS) || defined(CONFIG_SERIAL_TIOCSERGSTRUCT)
+ struct inode *inode = filep->f_inode;
+ struct uart_dev_s *dev = inode->i_private;
+#endif
+ int ret = OK;
+
+ /* Run the requested ioctl command. */
+
+ switch (cmd)
+ {
+#ifdef CONFIG_SERIAL_TIOCSERGSTRUCT
+
+ /* Get the internal driver data structure for debug purposes. */
+
+ case TIOCSERGSTRUCT:
+ {
+ struct esp32s3_uart_s *user = (struct esp32s3_uart_s *)arg;
+ if (user == NULL)
+ {
+ ret = -EINVAL;
+ }
+ else
+ {
+ memcpy(user, dev->priv, sizeof(struct esp32s3_uart_s));
+ }
+ }
+ break;
+#endif
+
+#ifdef CONFIG_SERIAL_TERMIOS
+
+ /* Fill a termios structure with the required information. */
+
+ case TCGETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ if (termiosp == NULL)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Return parity (0 = no parity, 1 = odd parity, 2 = even parity). */
+
+ termiosp->c_cflag = (priv->parity != 0 ? PARENB : 0) |
+ (priv->parity == 1 ? PARODD : 0);
+
+ /* Return stop bits */
+
+ termiosp->c_cflag |= priv->stop_b2 != 0 ? CSTOPB : 0;
+
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ termiosp->c_cflag |= priv->oflow != 0 ? CCTS_OFLOW : 0;
+#endif
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ termiosp->c_cflag |= priv->iflow != 0 ? CRTS_IFLOW : 0;
+#endif
+
+ /* Set the baud rate in ther termiosp using the
+ * cfsetispeed interface.
+ */
+
+ cfsetispeed(termiosp, priv->baud);
+
+ /* Return number of bits. */
+
+ switch (priv->bits)
+ {
+ case 5:
+ termiosp->c_cflag |= CS5;
+ break;
+
+ case 6:
+ termiosp->c_cflag |= CS6;
+ break;
+
+ case 7:
+ termiosp->c_cflag |= CS7;
+ break;
+
+ default:
+ case 8:
+ termiosp->c_cflag |= CS8;
+ break;
+ }
+ }
+ break;
+
+ case TCSETS:
+ {
+ struct termios *termiosp = (struct termios *)arg;
+ struct esp32s3_uart_s *priv = (struct esp32s3_uart_s *)dev->priv;
+ uint32_t baud;
+ uint32_t current_int_sts;
+ uint8_t parity;
+ uint8_t bits;
+ uint8_t stop2;
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ bool iflow;
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ bool oflow;
+#endif
+
+ if (termiosp == NULL)
+ {
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Get the target baud rate to change. */
+
+ baud = cfgetispeed(termiosp);
+
+ /* Decode number of bits. */
+
+ switch (termiosp->c_cflag & CSIZE)
+ {
+ case CS5:
+ bits = 5;
+ break;
+
+ case CS6:
+ bits = 6;
+ break;
+
+ case CS7:
+ bits = 7;
+ break;
+
+ case CS8:
+ bits = 8;
+ break;
+
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ /* Decode parity. */
+
+ if ((termiosp->c_cflag & PARENB) != 0)
+ {
+ parity = (termiosp->c_cflag & PARODD) != 0 ? 1 : 2;
+ }
+ else
+ {
+ parity = 0;
+ }
+
+ /* Decode stop bits. */
+
+ stop2 = (termiosp->c_cflag & CSTOPB) != 0 ? 1 : 0;
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ iflow = (termiosp->c_cflag & CRTS_IFLOW) != 0;
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ oflow = (termiosp->c_cflag & CCTS_OFLOW) != 0;
+#endif
+
+ /* Verify that all settings are valid before
+ * performing the changes.
+ */
+
+ if (ret == OK)
+ {
+ /* Fill the private struct fields. */
+
+ priv->baud = baud;
+ priv->parity = parity;
+ priv->bits = bits;
+ priv->stop_b2 = stop2;
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+ priv->iflow = iflow;
+#endif
+#ifdef CONFIG_SERIAL_OFLOWCONTROL
+ priv->oflow = oflow;
+#endif
+
+ /* Effect the changes immediately - note that we do not
+ * implement TCSADRAIN or TCSAFLUSH, only TCSANOW option.
+ * See nuttx/libs/libc/termios/lib_tcsetattr.c
+ */
+
+ esp32s3_lowputc_disable_all_uart_int(priv, ¤t_int_sts);
+ ret = esp32s3_setup(dev);
+
+ /* Restore the interrupt state */
+
+ esp32s3_lowputc_restore_all_uart_int(priv, ¤t_int_sts);
+ }
+ }
+ break;
+#endif /* CONFIG_SERIAL_TERMIOS */
+
+ default:
+ ret = -ENOTTY;
+ break;
+ }
+
+ return ret;
+}
+
+/****************************************************************************
+ * Name: esp32s3_rxflowcontrol
+ *
+ * Description:
+ * Called when upper half RX buffer is full (or exceeds configured
+ * watermark levels if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is defined).
+ * Return true if UART activated RX flow control to block more incoming
+ * data.
+ * NOTE: ESP32-S3 has a hardware RX FIFO threshold mechanism to control
+ * RTS line and to stop receiving data. This is very similar to the concept
+ * behind upper watermark level. The hardware threshold is used here
+ * to control the RTS line. When setting the threshold to zero, RTS will
+ * immediately be asserted. If nbuffered = 0 or the lower watermark is
+ * crossed and the serial driver decides to disable RX flow control, the
+ * threshold will be changed to UART_RX_FLOW_THRHD_VALUE, which is almost
+ * half the HW RX FIFO capacity. It keeps some space to keep the data
+ * received between the RTS assertion and the stop by the sender.
+ *
+ * Input Parameters:
+ * dev - UART device instance
+ * nbuffered - the number of characters currently buffered
+ * (if CONFIG_SERIAL_IFLOWCONTROL_WATERMARKS is
+ * not defined the value will be 0 for an empty buffer or the
+ * defined buffer size for a full buffer)
+ * upper - true indicates the upper watermark was crossed where
+ * false indicates the lower watermark has been crossed
+ *
+ * Returned Value:
+ * true if RX flow control activated.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_SERIAL_IFLOWCONTROL
+static bool esp32s3_rxflowcontrol(struct uart_dev_s *dev,
+ unsigned int nbuffered, bool upper)
+{
+ bool ret = false;
+ struct esp32s3_uart_s *priv = dev->priv;
+ if (priv->iflow)
+ {
+ if (nbuffered == 0 || upper == false)
+ {
+ /* Empty buffer, RTS should be de-asserted and logic in above
+ * layers should re-enable RX interrupt.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, (uint8_t)(UART_RX_FIFO_SIZE / 2),
+ true);
+ esp32s3_rxint(dev, true);
+ ret = false;
+ }
+ else
+ {
+ /* If the RX buffer is not zero and watermarks are not enabled,
+ * then this function is called to announce RX buffer is full.
+ * The first thing it should do is to immediately assert RTS.
+ * Software RX FIFO is full, so besides asserting RTS, it's
+ * necessary to disable RX interrupts to prevent remaining bytes
+ * (that arrive after asserting RTS) to be pushed to the
+ * SW RX FIFO.
+ */
+
+ esp32s3_lowputc_set_iflow(priv, 0 , true);
+ esp32s3_rxint(dev, false);
+ ret = true;
+ }
+ }
+
+ return ret;
+}
+#endif
+#endif /* CONFIG_ESP32S3_UART */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#ifdef USE_EARLYSERIALINIT
+
+/****************************************************************************
+ * Name: xtensa_earlyserialinit
+ *
+ * Description:
+ * Performs the low level UART initialization early in debug so that the
+ * serial console will be available during bootup. This must be called
+ * before xtensa_serialinit. NOTE: This function depends on GPIO pin
+ * configuration performed in up_consoleinit() and main clock
+ * initialization performed in up_clkinitialize().
+ *
+ ****************************************************************************/
+
+void xtensa_earlyserialinit(void)
+{
+ /* NOTE: All GPIO configuration for the UARTs was performed in
+ * esp32s3_lowsetup
+ */
+
+ /* Disable all UARTS interrupts */
+
+#ifdef TTYS0_DEV
+ esp32s3_lowputc_disable_all_uart_int(TTYS0_DEV.priv, NULL);
+#endif
+
+#ifdef TTYS1_DEV
+ esp32s3_lowputc_disable_all_uart_int(TTYS1_DEV.priv, NULL);
+#endif
+
+ /* Configure console in early step.
+ * Setup for other serials will be perfomed when the serial driver is
+ * open.
+ */
+
+#ifdef CONSOLE_UART
+ esp32s3_setup(&CONSOLE_DEV);
+#endif
+}
+
+#endif /* USE_EARLYSERIALINIT */
+
+/****************************************************************************
+ * Name: xtensa_serialinit
+ *
+ * Description:
+ * Register serial console and serial ports. This assumes
+ * that xtensa_earlyserialinit was called previously.
+ *
+ ****************************************************************************/
+
+void xtensa_serialinit(void)
+{
+#ifdef CONSOLE_UART
+ uart_register("/dev/console", &CONSOLE_DEV);
+#endif
+
+#ifdef TTYS0_DEV
+ uart_register("/dev/ttyS0", &TTYS0_DEV);
+#endif
+
+#ifdef TTYS1_DEV
+ uart_register("/dev/ttyS1", &TTYS1_DEV);
+#endif
+
+#ifdef CONFIG_ESP32S3_USBSERIAL
+ uart_register("/dev/ttyACM0", &TTYACM0_DEV);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef CONSOLE_UART
+ uint32_t int_status;
+
+ esp32s3_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+
+ /* Check for LF */
+
+ if (ch == '\n')
+ {
+ /* Add CR */
+
+ up_lowputc('\r');
+ }
+
+ up_lowputc(ch);
+
+#ifdef CONSOLE_UART
+ esp32s3_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+ return ch;
+}
+
+#endif /* HAVE_UART_DEVICE */
+
+#else /* USE_SERIALDRIVER */
+
+/****************************************************************************
+ * Name: up_putc
+ *
+ * Description:
+ * Provide priority, low-level access to support OS debug writes
+ *
+ ****************************************************************************/
+
+int up_putc(int ch)
+{
+#ifdef CONSOLE_UART
+ uint32_t int_status;
+
+ esp32s3_lowputc_disable_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+
+ /* Check for LF */
+
+ if (ch == '\n')
+ {
+ /* Add CR */
+
+ up_lowputc('\r');
+ }
+
+ up_lowputc(ch);
+
+#ifdef CONSOLE_UART
+ esp32s3_lowputc_restore_all_uart_int(CONSOLE_DEV.priv, &int_status);
+#endif
+ return ch;
+}
+
+#endif /* USE_SERIALDRIVER */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c
new file mode 100644
index 0000000..5bec851
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_start.c
@@ -0,0 +1,324 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_start.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <string.h>
+
+#include <nuttx/init.h>
+#include <nuttx/irq.h>
+
+#include "xtensa.h"
+#include "xtensa_attr.h"
+
+#include "esp32s3_start.h"
+#include "esp32s3_lowputc.h"
+#include "esp32s3_clockconfig.h"
+#include "esp32s3_region.h"
+#include "esp32s3_wdt.h"
+#include "hardware/esp32s3_cache_memory.h"
+#include "hardware/esp32s3_system.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_DEBUG_FEATURES
+# define showprogress(c) up_lowputc(c)
+#else
+# define showprogress(c)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * ROM Function Prototypes
+ ****************************************************************************/
+
+extern void rom_config_instruction_cache_mode(uint32_t cfg_cache_size,
+ uint8_t cfg_cache_ways,
+ uint8_t cfg_cache_line_size);
+extern void rom_config_data_cache_mode(uint32_t cfg_cache_size,
+ uint8_t cfg_cache_ways,
+ uint8_t cfg_cache_line_size);
+extern uint32_t cache_suspend_dcache(void);
+extern void cache_resume_dcache(uint32_t val);
+extern uint32_t cache_set_idrom_mmu_size(uint32_t irom_size,
+ uint32_t drom_size);
+extern void cache_set_idrom_mmu_info(uint32_t instr_page_num,
+ uint32_t rodata_page_num,
+ uint32_t rodata_start,
+ uint32_t rodata_end,
+ int i_off,
+ int ro_off);
+#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
+extern void cache_invalidate_dcache_all(void);
+extern int cache_occupy_addr(uint32_t addr, uint32_t size);
+#endif
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+extern int _rodata_reserved_start;
+extern int _rodata_reserved_end;
+
+/* Address of the CPU0 IDLE thread */
+
+uint32_t g_idlestack[IDLETHREAD_STACKWORDS]
+ aligned_data(16) locate_data(".noinit");
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: configure_cpu_caches
+ *
+ * Description:
+ * Configure the Instruction and Data CPU caches.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR configure_cpu_caches(void)
+{
+ int s_instr_flash2spiram_off = 0;
+ int s_rodata_flash2spiram_off = 0;
+
+ /* Configure the mode of instruction cache: cache size, cache line size. */
+
+ rom_config_instruction_cache_mode(CONFIG_ESP32S3_INSTRUCTION_CACHE_SIZE,
+ CONFIG_ESP32S3_ICACHE_ASSOCIATED_WAYS,
+ CONFIG_ESP32S3_INSTRUCTION_CACHE_LINE_SIZE);
+
+ /* If we need to use SPIRAM, we should use data cache.
+ * Configure the mode of data cache: cache size, cache line size.
+ */
+
+ cache_suspend_dcache();
+ rom_config_data_cache_mode(CONFIG_ESP32S3_DATA_CACHE_SIZE,
+ CONFIG_ESP32S3_DCACHE_ASSOCIATED_WAYS,
+ CONFIG_ESP32S3_DATA_CACHE_LINE_SIZE);
+ cache_resume_dcache(0);
+
+ /* Configure the Cache MMU size for instruction and rodata in flash. */
+
+ uint32_t rodata_reserved_start_align =
+ (uint32_t)&_rodata_reserved_start & ~(MMU_PAGE_SIZE - 1);
+ uint32_t cache_mmu_irom_size =
+ ((rodata_reserved_start_align - SOC_DROM_LOW) / MMU_PAGE_SIZE) *
+ sizeof(uint32_t);
+
+ uint32_t cache_mmu_drom_size =
+ (((uint32_t)&_rodata_reserved_end - rodata_reserved_start_align +
+ MMU_PAGE_SIZE - 1) /
+ MMU_PAGE_SIZE) * sizeof(uint32_t);
+
+ cache_set_idrom_mmu_size(cache_mmu_irom_size,
+ CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
+
+ cache_set_idrom_mmu_info(cache_mmu_irom_size / sizeof(uint32_t),
+ cache_mmu_drom_size / sizeof(uint32_t),
+ (uint32_t)&_rodata_reserved_start,
+ (uint32_t)&_rodata_reserved_end,
+ s_instr_flash2spiram_off,
+ s_rodata_flash2spiram_off);
+
+#ifdef CONFIG_ESP32S3_DATA_CACHE_16KB
+ cache_invalidate_dcache_all();
+ cache_occupy_addr(SOC_DROM_LOW, 0x4000);
+#endif
+}
+
+/****************************************************************************
+ * Name: disable_app_cpu
+ *
+ * Description:
+ * Disable the APP CPU (Core 1).
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+static void IRAM_ATTR disable_app_cpu(void)
+{
+ uint32_t regval;
+
+ regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
+ regval &= ~SYSTEM_CONTROL_CORE_1_CLKGATE_EN;
+ putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
+
+ /* The clock gating signal of the App core is invalid.
+ * We use RUNSTALL and RESETING signals to ensure that the App core stops
+ * running in single-core mode.
+ */
+
+ regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
+ regval |= SYSTEM_CONTROL_CORE_1_RUNSTALL;
+ putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
+
+ regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG);
+ regval &= ~SYSTEM_CONTROL_CORE_1_RESETING;
+ putreg32(regval, SYSTEM_CORE_1_CONTROL_0_REG);
+}
+
+/****************************************************************************
+ * Name: __esp32s3_start
+ *
+ * Description:
+ * Perform base configuration of the chip for code execution.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void noreturn_function IRAM_ATTR __esp32s3_start(void)
+{
+ uint32_t sp;
+
+ /* Make sure that normal interrupts are disabled. This is really only an
+ * issue when we are started in un-usual ways (such as from IRAM). In this
+ * case, we can at least defer some unexpected interrupts left over from
+ * the last program execution.
+ */
+
+ up_irq_disable();
+
+ /* Move the stack to a known location. Although we were given a stack
+ * pointer at start-up, we don't know where that stack pointer is
+ * positioned with respect to our memory map. The only safe option is to
+ * switch to a well-known IDLE thread stack.
+ */
+
+ sp = (uint32_t)g_idlestack + IDLETHREAD_STACKSIZE;
+ __asm__ __volatile__("mov sp, %0\n" : : "r"(sp));
+
+ /* Raise an exception in case page 0 is accessed */
+
+ esp32s3_region_protection();
+
+ /* Move CPU0 exception vectors to IRAM */
+
+ __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (&_init_start));
+
+ /* Clear .bss. We'll do this inline (vs. calling memset) just to be
+ * certain that there are no issues with the state of global variables.
+ */
+
+ for (uint32_t *dest = &_sbss; dest < &_ebss; dest++)
+ {
+ *dest = 0;
+ }
+
+ /* Make sure that the APP_CPU is disabled for now */
+
+ disable_app_cpu();
+
+ /* The 2nd stage bootloader enables RTC WDT to check on startup sequence
+ * related issues in application. Hence disable that as we are about to
+ * start the NuttX environment.
+ */
+
+ esp32s3_wdt_early_deinit();
+
+ /* Set CPU frequency configured in board.h */
+
+ esp32s3_clockconfig();
+
+#ifndef CONFIG_SUPPRESS_UART_CONFIG
+ /* Configure the UART so we can get debug output */
+
+ esp32s3_lowsetup();
+#endif
+
+#ifdef USE_EARLYSERIALINIT
+ /* Perform early serial initialization */
+
+ xtensa_earlyserialinit();
+#endif
+
+ showprogress('A');
+
+ /* Initialize onboard resources */
+
+ esp32s3_board_initialize();
+
+ showprogress('B');
+
+ /* Bring up NuttX */
+
+ nx_start();
+ for (; ; ); /* Should not return */
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: __start
+ *
+ * Description:
+ * We arrive here after the bootloader finished loading the program from
+ * flash. The hardware is mostly uninitialized, and the app CPU is in
+ * reset. We do have a stack, so we can do the initialization in C.
+ *
+ * The app CPU will remain in reset unless CONFIG_SMP is selected and
+ * up_cpu_start() is called later in the bring-up sequence.
+ *
+ ****************************************************************************/
+
+void IRAM_ATTR __start(void)
+{
+ configure_cpu_caches();
+
+ __esp32s3_start();
+
+ while (true); /* Should not return */
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.h b/arch/xtensa/src/esp32s3/esp32s3_start.h
new file mode 100644
index 0000000..306da94
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_start.h
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_start.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_START_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_START_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_board_initialize
+ *
+ * Description:
+ * Board-specific logic is initialized by calling this function. This
+ * entry point is called early in the initialization -- after all memory
+ * has been configured but before any devices have been initialized.
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+void esp32s3_board_initialize(void);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_START_H */
diff --git a/arch/xtensa/src/esp32s3/esp32s3_systemreset.c b/arch/xtensa/src/esp32s3/esp32s3_systemreset.c
new file mode 100644
index 0000000..9d71639
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_systemreset.c
@@ -0,0 +1,54 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_systemreset.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+
+#include "xtensa.h"
+#include "hardware/esp32s3_rtccntl.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_systemreset
+ *
+ * Description:
+ * Internal reset logic.
+ *
+ ****************************************************************************/
+
+void up_systemreset(void)
+{
+ putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_RTC_OPTIONS0_REG);
+
+ /* Wait for the reset */
+
+ for (; ; );
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
new file mode 100644
index 0000000..30896f0
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c
@@ -0,0 +1,143 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_timerisr.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <assert.h>
+#include <time.h>
+
+#include <arch/board/board.h>
+#include <arch/irq.h>
+#include <nuttx/arch.h>
+
+#include "chip.h"
+#include "esp32s3_irq.h"
+#include "hardware/esp32s3_system.h"
+#include "hardware/esp32s3_systimer.h"
+#include "xtensa.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define ESP32S3_SYSTIMER_TICKS_PER_SEC (16 * 1000 * 1000)
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: systimer_isr
+ *
+ * Description:
+ * The timer ISR will perform a variety of services for various portions
+ * of the systems.
+ *
+ * Input Parameters:
+ * irq - CPU interrupt index.
+ * context - Context data from the ISR.
+ * arg - Opaque pointer to the internal driver state structure.
+ *
+ * Returned Value:
+ * Zero (OK) is returned on success. A negated errno value is returned on
+ * failure.
+ *
+ ****************************************************************************/
+
+static int systimer_isr(int irq, void *context, void *arg)
+{
+ modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
+
+ /* Process timer interrupt */
+
+ nxsched_process_timer();
+
+ return OK;
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_timer_initialize
+ *
+ * Description:
+ * This function is called during start-up to initialize the timer
+ * interrupt.
+ *
+ * Input Parameters:
+ * None.
+ *
+ * Returned Value:
+ * None.
+ *
+ ****************************************************************************/
+
+void up_timer_initialize(void)
+{
+ uint32_t regval;
+ int cpuint;
+
+ cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_SYSTIMER_TARGET0, 1,
+ ESP32S3_CPUINT_LEVEL);
+ DEBUGASSERT(cpuint >= 0);
+
+ /* Attach the timer interrupt. */
+
+ irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET0, systimer_isr, NULL);
+
+ /* Enable the allocated CPU interrupt. */
+
+ up_enable_irq(ESP32S3_IRQ_SYSTIMER_TARGET0);
+
+ /* Enable timer clock */
+
+ modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_SYSTIMER_CLK_EN);
+ modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_SYSTIMER_RST, 0);
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_CLK_EN);
+
+ /* Configure alarm0 (Comparator 0) */
+
+ regval = SYSTIMER_TARGET0_PERIOD_MODE |
+ ((ESP32S3_SYSTIMER_TICKS_PER_SEC / CLOCKS_PER_SEC) <<
+ SYSTIMER_TARGET0_PERIOD_S);
+ putreg32(regval, SYSTIMER_TARGET0_CONF_REG);
+ putreg32(SYSTIMER_TIMER_COMP0_LOAD, SYSTIMER_COMP0_LOAD_REG);
+
+ /* Stall systimer 0 when CPU stalls, e.g., when using JTAG to debug */
+
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN);
+
+ /* Enable interrupt */
+
+ modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET0_INT_CLR);
+ modifyreg32(SYSTIMER_INT_ENA_REG, 0, SYSTIMER_TARGET0_INT_ENA);
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TARGET0_WORK_EN);
+
+ /* Start alarm0 counter0 */
+
+ modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT0_WORK_EN);
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_user.c b/arch/xtensa/src/esp32s3/esp32s3_user.c
new file mode 100644
index 0000000..d263bee
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_user.c
@@ -0,0 +1,71 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_user.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include "xtensa.h"
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: xtensa_user
+ *
+ * Description:
+ * ESP32-S3-specific user exception handler.
+ *
+ * Input Parameters:
+ * exccause - Identifies the EXCCAUSE of the user exception.
+ * regs - The register save are at the time of the interrupt.
+ *
+ * Returned Value:
+ * Does not return.
+ *
+ ****************************************************************************/
+
+uint32_t *xtensa_user(int exccause, uint32_t *regs)
+{
+ /* xtensa_user_panic never returns. */
+
+ xtensa_user_panic(exccause, regs);
+
+ while (1)
+ {
+ }
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.c b/arch/xtensa/src/esp32s3/esp32s3_wdt.c
new file mode 100644
index 0000000..8592acd
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.c
@@ -0,0 +1,50 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_wdt.c
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "xtensa.h"
+
+#include "esp32s3_wdt.h"
+#include "hardware/esp32s3_rtccntl.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp32s3_wdt_early_deinit
+ *
+ * Description:
+ * Disable the WDT(s) that was/were enabled by the bootloader.
+ *
+ ****************************************************************************/
+
+void esp32s3_wdt_early_deinit(void)
+{
+ uint32_t regval;
+ putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_RTC_WDTWPROTECT_REG);
+ regval = getreg32(RTC_CNTL_RTC_WDTCONFIG0_REG);
+ regval &= ~RTC_CNTL_WDT_EN;
+ putreg32(regval, RTC_CNTL_RTC_WDTCONFIG0_REG);
+ putreg32(0, RTC_CNTL_RTC_WDTWPROTECT_REG);
+}
diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.h b/arch/xtensa/src/esp32s3/esp32s3_wdt.h
new file mode 100644
index 0000000..ee8f4e9
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.h
@@ -0,0 +1,34 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_wdt.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+void esp32s3_wdt_early_deinit(void);
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_WDT_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
new file mode 100644
index 0000000..7e41044
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
@@ -0,0 +1,118 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_cache_memory.h
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdint.h>
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRAM0 is connected with Cache IBUS0 */
+
+#define IRAM0_ADDRESS_LOW 0x40000000
+#define IRAM0_ADDRESS_HIGH 0x44000000
+#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
+#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
+
+/* DRAM0 is connected with Cache DBUS0 */
+
+#define DRAM0_ADDRESS_LOW 0x3c000000
+#define DRAM0_ADDRESS_HIGH 0x40000000
+#define DRAM0_CACHE_ADDRESS_LOW 0x3c000000
+#define DRAM0_CACHE_ADDRESS_HIGH 0x3e000000
+#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
+#define ESP_CACHE_TEMP_ADDR 0x3c800000
+
+#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - \
+ bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW \
+ && (vaddr) < \
+ bus_name##_ADDRESS_HIGH)
+
+#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
+#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
+
+#define CACHE_IBUS 0
+#define CACHE_IBUS_MMU_START 0
+#define CACHE_IBUS_MMU_END 0x800
+
+#define CACHE_DBUS 1
+#define CACHE_DBUS_MMU_START 0
+#define CACHE_DBUS_MMU_END 0x800
+
+#define CACHE_IROM_MMU_START 0
+#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
+#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
+
+#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
+#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
+#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
+
+#define CACHE_DROM_MMU_MAX_END 0x400
+
+#define ICACHE_MMU_SIZE 0x800
+#define DCACHE_MMU_SIZE 0x800
+
+#define MMU_BUS_START(i) 0
+#define MMU_BUS_SIZE(i) 0x800
+
+#define MMU_INVALID BIT(14)
+#define MMU_TYPE BIT(15)
+#define MMU_ACCESS_FLASH 0
+#define MMU_ACCESS_SPIRAM BIT(15)
+
+#define CACHE_MAX_SYNC_NUM 0x400000
+#define CACHE_MAX_LOCK_NUM 0x8000
+
+#define FLASH_MMU_TABLE ((volatile uint32_t *)DR_REG_MMU_TABLE)
+#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE / sizeof(uint32_t))
+
+#define MMU_TABLE_INVALID_VAL 0x4000
+#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
+#define MMU_ADDRESS_MASK 0x3fff
+#define MMU_PAGE_SIZE 0x10000
+#define INVALID_PHY_PAGE 0xffff
+
+#define BUS_ADDR_SIZE 0x200000
+#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
+
+#define CACHE_ICACHE_LOW_SHIFT 0
+#define CACHE_ICACHE_HIGH_SHIFT 2
+#define CACHE_DCACHE_LOW_SHIFT 4
+#define CACHE_DCACHE_HIGH_SHIFT 6
+
+#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
+#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
+
+#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
+#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
+
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_CACHE_MEMORY_H */
diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h
new file mode 100644
index 0000000..8d19cfb
--- /dev/null
+++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h
@@ -0,0 +1,2761 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/hardware/esp32s3_extmem.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H
+#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EXTMEM_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "esp32s3_soc.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* EXTMEM_DCACHE_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0)
+
+/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W; bitpos: [4:3]; default: 0;
+ * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes,2:
+ * 64 bytes
+ */
+
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE 0x00000003
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (EXTMEM_DCACHE_BLOCKSIZE_MODE_V << EXTMEM_DCACHE_BLOCKSIZE_MODE_S)
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x00000003
+#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3
+
+/* EXTMEM_DCACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0;
+ * The bit is used to configure cache memory size.0: 32KB, 1: 64KB
+ */
+
+#define EXTMEM_DCACHE_SIZE_MODE (BIT(2))
+#define EXTMEM_DCACHE_SIZE_MODE_M (EXTMEM_DCACHE_SIZE_MODE_V << EXTMEM_DCACHE_SIZE_MODE_S)
+#define EXTMEM_DCACHE_SIZE_MODE_V 0x00000001
+#define EXTMEM_DCACHE_SIZE_MODE_S 2
+
+/* EXTMEM_DCACHE_ENABLE : R/W; bitpos: [0]; default: 0;
+ * The bit is used to activate the data cache. 0: disable, 1: enable
+ */
+
+#define EXTMEM_DCACHE_ENABLE (BIT(0))
+#define EXTMEM_DCACHE_ENABLE_M (EXTMEM_DCACHE_ENABLE_V << EXTMEM_DCACHE_ENABLE_S)
+#define EXTMEM_DCACHE_ENABLE_V 0x00000001
+#define EXTMEM_DCACHE_ENABLE_S 0
+
+/* EXTMEM_DCACHE_CTRL1_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x4)
+
+/* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W; bitpos: [1]; default: 1;
+ * The bit is used to disable core1 dbus, 0: enable, 1: disable
+ */
+
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1))
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (EXTMEM_DCACHE_SHUT_CORE1_BUS_V << EXTMEM_DCACHE_SHUT_CORE1_BUS_S)
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x00000001
+#define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1
+
+/* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W; bitpos: [0]; default: 1;
+ * The bit is used to disable core0 dbus, 0: enable, 1: disable
+ */
+
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0))
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (EXTMEM_DCACHE_SHUT_CORE0_BUS_V << EXTMEM_DCACHE_SHUT_CORE0_BUS_S)
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x00000001
+#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0
+
+/* EXTMEM_DCACHE_TAG_POWER_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x8)
+
+/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ * The bit is used to power dcache tag memory up, 0: follow rtc_lslp_pd, 1:
+ * power up
+ */
+
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V << EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S)
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x00000001
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2
+
+/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ * The bit is used to power dcache tag memory down, 0: follow rtc_lslp_pd,
+ * 1: power down
+ */
+
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V << EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S)
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x00000001
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1
+
+/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ * The bit is used to close clock gating of dcache tag memory. 1: close
+ * gating, 0: open clock gating.
+ */
+
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0))
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V << EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S)
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x00000001
+#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0
+
+/* EXTMEM_DCACHE_PRELOCK_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0xc)
+
+/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ * The bit is used to enable the second section of prelock function.
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1))
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (EXTMEM_DCACHE_PRELOCK_SCT1_EN_V << EXTMEM_DCACHE_PRELOCK_SCT1_EN_S)
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x00000001
+#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1
+
+/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable the first section of prelock function.
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0))
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (EXTMEM_DCACHE_PRELOCK_SCT0_EN_V << EXTMEM_DCACHE_PRELOCK_SCT0_EN_S)
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x00000001
+#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0
+
+/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x10)
+
+/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the first start virtual address of data
+ * prelock, which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xffffffff
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M (EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V << EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0
+
+/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x14)
+
+/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the second start virtual address of data
+ * prelock, which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xffffffff
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M (EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V << EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0
+
+/* EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x18)
+
+/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [31:16]; default: 0;
+ * The bits are used to configure the first length of data locking, which is
+ * combined with DCACHE_PRELOCK_SCT0_ADDR_REG
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000ffff
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M (EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V << EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0x0000ffff
+#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16
+
+/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the second length of data locking, which
+ * is combined with DCACHE_PRELOCK_SCT1_ADDR_REG
+ */
+
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000ffff
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M (EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V << EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0x0000ffff
+#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0
+
+/* EXTMEM_DCACHE_LOCK_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x1c)
+
+/* EXTMEM_DCACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ * The bit is used to indicate unlock/lock operation is finished.
+ */
+
+#define EXTMEM_DCACHE_LOCK_DONE (BIT(2))
+#define EXTMEM_DCACHE_LOCK_DONE_M (EXTMEM_DCACHE_LOCK_DONE_V << EXTMEM_DCACHE_LOCK_DONE_S)
+#define EXTMEM_DCACHE_LOCK_DONE_V 0x00000001
+#define EXTMEM_DCACHE_LOCK_DONE_S 2
+
+/* EXTMEM_DCACHE_UNLOCK_ENA : R/W; bitpos: [1]; default: 0;
+ * The bit is used to enable unlock operation. It will be cleared by
+ * hardware after unlock operation done.
+ */
+
+#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1))
+#define EXTMEM_DCACHE_UNLOCK_ENA_M (EXTMEM_DCACHE_UNLOCK_ENA_V << EXTMEM_DCACHE_UNLOCK_ENA_S)
+#define EXTMEM_DCACHE_UNLOCK_ENA_V 0x00000001
+#define EXTMEM_DCACHE_UNLOCK_ENA_S 1
+
+/* EXTMEM_DCACHE_LOCK_ENA : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable lock operation. It will be cleared by hardware
+ * after lock operation done.
+ */
+
+#define EXTMEM_DCACHE_LOCK_ENA (BIT(0))
+#define EXTMEM_DCACHE_LOCK_ENA_M (EXTMEM_DCACHE_LOCK_ENA_V << EXTMEM_DCACHE_LOCK_ENA_S)
+#define EXTMEM_DCACHE_LOCK_ENA_V 0x00000001
+#define EXTMEM_DCACHE_LOCK_ENA_S 0
+
+/* EXTMEM_DCACHE_LOCK_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x20)
+
+/* EXTMEM_DCACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for lock
+ * operations. It should be combined with DCACHE_LOCK_SIZE_REG.
+ */
+
+#define EXTMEM_DCACHE_LOCK_ADDR 0xffffffff
+#define EXTMEM_DCACHE_LOCK_ADDR_M (EXTMEM_DCACHE_LOCK_ADDR_V << EXTMEM_DCACHE_LOCK_ADDR_S)
+#define EXTMEM_DCACHE_LOCK_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_LOCK_ADDR_S 0
+
+/* EXTMEM_DCACHE_LOCK_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x24)
+
+/* EXTMEM_DCACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the length for lock operations. The bits
+ * are the counts of cache block. It should be combined with
+ * DCACHE_LOCK_ADDR_REG.
+ */
+
+#define EXTMEM_DCACHE_LOCK_SIZE 0x0000ffff
+#define EXTMEM_DCACHE_LOCK_SIZE_M (EXTMEM_DCACHE_LOCK_SIZE_V << EXTMEM_DCACHE_LOCK_SIZE_S)
+#define EXTMEM_DCACHE_LOCK_SIZE_V 0x0000ffff
+#define EXTMEM_DCACHE_LOCK_SIZE_S 0
+
+/* EXTMEM_DCACHE_SYNC_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x28)
+
+/* EXTMEM_DCACHE_SYNC_DONE : RO; bitpos: [3]; default: 0;
+ * The bit is used to indicate clean/writeback/invalidate operation is
+ * finished.
+ */
+
+#define EXTMEM_DCACHE_SYNC_DONE (BIT(3))
+#define EXTMEM_DCACHE_SYNC_DONE_M (EXTMEM_DCACHE_SYNC_DONE_V << EXTMEM_DCACHE_SYNC_DONE_S)
+#define EXTMEM_DCACHE_SYNC_DONE_V 0x00000001
+#define EXTMEM_DCACHE_SYNC_DONE_S 3
+
+/* EXTMEM_DCACHE_CLEAN_ENA : R/W; bitpos: [2]; default: 0;
+ * The bit is used to enable clean operation. It will be cleared by hardware
+ * after clean operation done.
+ */
+
+#define EXTMEM_DCACHE_CLEAN_ENA (BIT(2))
+#define EXTMEM_DCACHE_CLEAN_ENA_M (EXTMEM_DCACHE_CLEAN_ENA_V << EXTMEM_DCACHE_CLEAN_ENA_S)
+#define EXTMEM_DCACHE_CLEAN_ENA_V 0x00000001
+#define EXTMEM_DCACHE_CLEAN_ENA_S 2
+
+/* EXTMEM_DCACHE_WRITEBACK_ENA : R/W; bitpos: [1]; default: 0;
+ * The bit is used to enable writeback operation. It will be cleared by
+ * hardware after writeback operation done.
+ */
+
+#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1))
+#define EXTMEM_DCACHE_WRITEBACK_ENA_M (EXTMEM_DCACHE_WRITEBACK_ENA_V << EXTMEM_DCACHE_WRITEBACK_ENA_S)
+#define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x00000001
+#define EXTMEM_DCACHE_WRITEBACK_ENA_S 1
+
+/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W; bitpos: [0]; default: 1;
+ * The bit is used to enable invalidate operation. It will be cleared by
+ * hardware after invalidate operation done.
+ */
+
+#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0))
+#define EXTMEM_DCACHE_INVALIDATE_ENA_M (EXTMEM_DCACHE_INVALIDATE_ENA_V << EXTMEM_DCACHE_INVALIDATE_ENA_S)
+#define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x00000001
+#define EXTMEM_DCACHE_INVALIDATE_ENA_S 0
+
+/* EXTMEM_DCACHE_SYNC_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x2c)
+
+/* EXTMEM_DCACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for clean
+ * operations. It should be combined with DCACHE_SYNC_SIZE_REG.
+ */
+
+#define EXTMEM_DCACHE_SYNC_ADDR 0xffffffff
+#define EXTMEM_DCACHE_SYNC_ADDR_M (EXTMEM_DCACHE_SYNC_ADDR_V << EXTMEM_DCACHE_SYNC_ADDR_S)
+#define EXTMEM_DCACHE_SYNC_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_SYNC_ADDR_S 0
+
+/* EXTMEM_DCACHE_SYNC_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x30)
+
+/* EXTMEM_DCACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0;
+ * The bits are used to configure the length for sync operations. The bits
+ * are the counts of cache block. It should be combined with
+ * DCACHE_SYNC_ADDR_REG.
+ */
+
+#define EXTMEM_DCACHE_SYNC_SIZE 0x007fffff
+#define EXTMEM_DCACHE_SYNC_SIZE_M (EXTMEM_DCACHE_SYNC_SIZE_V << EXTMEM_DCACHE_SYNC_SIZE_S)
+#define EXTMEM_DCACHE_SYNC_SIZE_V 0x007fffff
+#define EXTMEM_DCACHE_SYNC_SIZE_S 0
+
+/* EXTMEM_DCACHE_OCCUPY_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x34)
+
+/* EXTMEM_DCACHE_OCCUPY_DONE : RO; bitpos: [1]; default: 1;
+ * The bit is used to indicate occupy operation is finished.
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1))
+#define EXTMEM_DCACHE_OCCUPY_DONE_M (EXTMEM_DCACHE_OCCUPY_DONE_V << EXTMEM_DCACHE_OCCUPY_DONE_S)
+#define EXTMEM_DCACHE_OCCUPY_DONE_V 0x00000001
+#define EXTMEM_DCACHE_OCCUPY_DONE_S 1
+
+/* EXTMEM_DCACHE_OCCUPY_ENA : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable occupy operation. It will be cleared by
+ * hardware after issuing Auot-Invalidate Operation.
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0))
+#define EXTMEM_DCACHE_OCCUPY_ENA_M (EXTMEM_DCACHE_OCCUPY_ENA_V << EXTMEM_DCACHE_OCCUPY_ENA_S)
+#define EXTMEM_DCACHE_OCCUPY_ENA_V 0x00000001
+#define EXTMEM_DCACHE_OCCUPY_ENA_S 0
+
+/* EXTMEM_DCACHE_OCCUPY_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x38)
+
+/* EXTMEM_DCACHE_OCCUPY_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for occupy
+ * operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_ADDR 0xffffffff
+#define EXTMEM_DCACHE_OCCUPY_ADDR_M (EXTMEM_DCACHE_OCCUPY_ADDR_V << EXTMEM_DCACHE_OCCUPY_ADDR_S)
+#define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_OCCUPY_ADDR_S 0
+
+/* EXTMEM_DCACHE_OCCUPY_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x3c)
+
+/* EXTMEM_DCACHE_OCCUPY_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the length for occupy operation. The bits
+ * are the counts of cache block. It should be combined with
+ * DCACHE_OCCUPY_ADDR_REG.
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000ffff
+#define EXTMEM_DCACHE_OCCUPY_SIZE_M (EXTMEM_DCACHE_OCCUPY_SIZE_V << EXTMEM_DCACHE_OCCUPY_SIZE_S)
+#define EXTMEM_DCACHE_OCCUPY_SIZE_V 0x0000ffff
+#define EXTMEM_DCACHE_OCCUPY_SIZE_S 0
+
+/* EXTMEM_DCACHE_PRELOAD_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x40)
+
+/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ * The bit is used to configure the direction of preload operation. 1:
+ * descending, 0: ascending.
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2))
+#define EXTMEM_DCACHE_PRELOAD_ORDER_M (EXTMEM_DCACHE_PRELOAD_ORDER_V << EXTMEM_DCACHE_PRELOAD_ORDER_S)
+#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x00000001
+#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2
+
+/* EXTMEM_DCACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ * The bit is used to indicate preload operation is finished.
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1))
+#define EXTMEM_DCACHE_PRELOAD_DONE_M (EXTMEM_DCACHE_PRELOAD_DONE_V << EXTMEM_DCACHE_PRELOAD_DONE_S)
+#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x00000001
+#define EXTMEM_DCACHE_PRELOAD_DONE_S 1
+
+/* EXTMEM_DCACHE_PRELOAD_ENA : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable preload operation. It will be cleared by
+ * hardware after preload operation done.
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0))
+#define EXTMEM_DCACHE_PRELOAD_ENA_M (EXTMEM_DCACHE_PRELOAD_ENA_V << EXTMEM_DCACHE_PRELOAD_ENA_S)
+#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x00000001
+#define EXTMEM_DCACHE_PRELOAD_ENA_S 0
+
+/* EXTMEM_DCACHE_PRELOAD_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x44)
+
+/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for preload
+ * operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_ADDR 0xffffffff
+#define EXTMEM_DCACHE_PRELOAD_ADDR_M (EXTMEM_DCACHE_PRELOAD_ADDR_V << EXTMEM_DCACHE_PRELOAD_ADDR_S)
+#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0
+
+/* EXTMEM_DCACHE_PRELOAD_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x48)
+
+/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the length for preload operation. The bits
+ * are the counts of cache block. It should be combined with
+ * DCACHE_PRELOAD_ADDR_REG..
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000ffff
+#define EXTMEM_DCACHE_PRELOAD_SIZE_M (EXTMEM_DCACHE_PRELOAD_SIZE_V << EXTMEM_DCACHE_PRELOAD_SIZE_S)
+#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0x0000ffff
+#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0
+
+/* EXTMEM_DCACHE_AUTOLOAD_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x4c)
+
+/* EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR : R/W; bitpos: [9]; default: 0;
+ * The bit is used to clear autoload buffer in dcache.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9))
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_M (EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V << EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S)
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_V 0x00000001
+#define EXTMEM_DCACHE_AUTOLOAD_BUFFER_CLEAR_S 9
+
+/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W; bitpos: [8:7]; default: 0;
+ * The bits are used to configure the numbers of the cache block for the
+ * issuing autoload operation.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SIZE_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x00000003
+#define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7
+
+/* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W; bitpos: [6:5]; default: 0;
+ * The bits are used to configure trigger conditions for autoload. 0/3:
+ * cache miss, 1: cache hit, 2: both cache miss and hit.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003
+#define EXTMEM_DCACHE_AUTOLOAD_RQST_M (EXTMEM_DCACHE_AUTOLOAD_RQST_V << EXTMEM_DCACHE_AUTOLOAD_RQST_S)
+#define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x00000003
+#define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5
+
+/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W; bitpos: [4]; default: 0;
+ * The bits are used to configure the direction of autoload. 1: descending,
+ * 0: ascending.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4))
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (EXTMEM_DCACHE_AUTOLOAD_ORDER_V << EXTMEM_DCACHE_AUTOLOAD_ORDER_S)
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x00000001
+#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4
+
+/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO; bitpos: [3]; default: 1;
+ * The bit is used to indicate autoload operation is finished.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3))
+#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (EXTMEM_DCACHE_AUTOLOAD_DONE_V << EXTMEM_DCACHE_AUTOLOAD_DONE_S)
+#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x00000001
+#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3
+
+/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W; bitpos: [2]; default: 0;
+ * The bit is used to enable and disable autoload operation. It is combined
+ * with dcache_autoload_done. 1: enable, 0: disable.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2))
+#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (EXTMEM_DCACHE_AUTOLOAD_ENA_V << EXTMEM_DCACHE_AUTOLOAD_ENA_S)
+#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x00000001
+#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [1]; default: 0;
+ * The bits are used to enable the second section for autoload operation.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x00000001
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [0]; default: 0;
+ * The bits are used to enable the first section for autoload operation.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0))
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x00000001
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x50)
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address of the first
+ * section for autoload operation. It should be combined with
+ * dcache_autoload_sct0_ena.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xffffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x54)
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [26:0]; default: 0;
+ * The bits are used to configure the length of the first section for
+ * autoload operation. It should be combined with dcache_autoload_sct0_ena.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07ffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x07ffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x58)
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address of the second
+ * section for autoload operation. It should be combined with
+ * dcache_autoload_sct1_ena.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xffffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x5c)
+
+/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [26:0]; default: 0;
+ * The bits are used to configure the length of the second section for
+ * autoload operation. It should be combined with dcache_autoload_sct1_ena.
+ */
+
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07ffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x07ffffff
+#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0
+
+/* EXTMEM_ICACHE_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x60)
+
+/* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W; bitpos: [3]; default: 0;
+ * The bit is used to configure cache block size.0: 16 bytes, 1: 32 bytes
+ */
+
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3))
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (EXTMEM_ICACHE_BLOCKSIZE_MODE_V << EXTMEM_ICACHE_BLOCKSIZE_MODE_S)
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x00000001
+#define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3
+
+/* EXTMEM_ICACHE_SIZE_MODE : R/W; bitpos: [2]; default: 0;
+ * The bit is used to configure cache memory size.0: 16KB, 1: 32KB
+ */
+
+#define EXTMEM_ICACHE_SIZE_MODE (BIT(2))
+#define EXTMEM_ICACHE_SIZE_MODE_M (EXTMEM_ICACHE_SIZE_MODE_V << EXTMEM_ICACHE_SIZE_MODE_S)
+#define EXTMEM_ICACHE_SIZE_MODE_V 0x00000001
+#define EXTMEM_ICACHE_SIZE_MODE_S 2
+
+/* EXTMEM_ICACHE_WAY_MODE : R/W; bitpos: [1]; default: 0;
+ * The bit is used to configure cache way mode.0: 4-way, 1: 8-way
+ */
+
+#define EXTMEM_ICACHE_WAY_MODE (BIT(1))
+#define EXTMEM_ICACHE_WAY_MODE_M (EXTMEM_ICACHE_WAY_MODE_V << EXTMEM_ICACHE_WAY_MODE_S)
+#define EXTMEM_ICACHE_WAY_MODE_V 0x00000001
+#define EXTMEM_ICACHE_WAY_MODE_S 1
+
+/* EXTMEM_ICACHE_ENABLE : R/W; bitpos: [0]; default: 0;
+ * The bit is used to activate the data cache. 0: disable, 1: enable
+ */
+
+#define EXTMEM_ICACHE_ENABLE (BIT(0))
+#define EXTMEM_ICACHE_ENABLE_M (EXTMEM_ICACHE_ENABLE_V << EXTMEM_ICACHE_ENABLE_S)
+#define EXTMEM_ICACHE_ENABLE_V 0x00000001
+#define EXTMEM_ICACHE_ENABLE_S 0
+
+/* EXTMEM_ICACHE_CTRL1_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x64)
+
+/* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W; bitpos: [1]; default: 1;
+ * The bit is used to disable core1 ibus, 0: enable, 1: disable
+ */
+
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1))
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (EXTMEM_ICACHE_SHUT_CORE1_BUS_V << EXTMEM_ICACHE_SHUT_CORE1_BUS_S)
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x00000001
+#define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1
+
+/* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W; bitpos: [0]; default: 1;
+ * The bit is used to disable core0 ibus, 0: enable, 1: disable
+ */
+
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0))
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (EXTMEM_ICACHE_SHUT_CORE0_BUS_V << EXTMEM_ICACHE_SHUT_CORE0_BUS_S)
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x00000001
+#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0
+
+/* EXTMEM_ICACHE_TAG_POWER_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x68)
+
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W; bitpos: [2]; default: 1;
+ * The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1:
+ * power up
+ */
+
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S)
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x00000001
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2
+
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W; bitpos: [1]; default: 0;
+ * The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1:
+ * power down
+ */
+
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V << EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S)
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x00000001
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1
+
+/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W; bitpos: [0]; default: 1;
+ * The bit is used to close clock gating of icache tag memory. 1: close
+ * gating, 0: open clock gating.
+ */
+
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0))
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V << EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S)
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x00000001
+#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0
+
+/* EXTMEM_ICACHE_PRELOCK_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x6c)
+
+/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W; bitpos: [1]; default: 0;
+ * The bit is used to enable the second section of prelock function.
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1))
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (EXTMEM_ICACHE_PRELOCK_SCT1_EN_V << EXTMEM_ICACHE_PRELOCK_SCT1_EN_S)
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x00000001
+#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1
+
+/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable the first section of prelock function.
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0))
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (EXTMEM_ICACHE_PRELOCK_SCT0_EN_V << EXTMEM_ICACHE_PRELOCK_SCT0_EN_S)
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x00000001
+#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0
+
+/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x70)
+
+/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the first start virtual address of data
+ * prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xffffffff
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M (EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V << EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0
+
+/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x74)
+
+/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the second start virtual address of data
+ * prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xffffffff
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M (EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V << EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0
+
+/* EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x78)
+
+/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W; bitpos: [31:16]; default: 0;
+ * The bits are used to configure the first length of data locking, which is
+ * combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000ffff
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M (EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V << EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0x0000ffff
+#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16
+
+/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the second length of data locking, which
+ * is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+ */
+
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000ffff
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M (EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V << EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0x0000ffff
+#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0
+
+/* EXTMEM_ICACHE_LOCK_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x7c)
+
+/* EXTMEM_ICACHE_LOCK_DONE : RO; bitpos: [2]; default: 1;
+ * The bit is used to indicate unlock/lock operation is finished.
+ */
+
+#define EXTMEM_ICACHE_LOCK_DONE (BIT(2))
+#define EXTMEM_ICACHE_LOCK_DONE_M (EXTMEM_ICACHE_LOCK_DONE_V << EXTMEM_ICACHE_LOCK_DONE_S)
+#define EXTMEM_ICACHE_LOCK_DONE_V 0x00000001
+#define EXTMEM_ICACHE_LOCK_DONE_S 2
+
+/* EXTMEM_ICACHE_UNLOCK_ENA : R/W; bitpos: [1]; default: 0;
+ * The bit is used to enable unlock operation. It will be cleared by
+ * hardware after unlock operation done.
+ */
+
+#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1))
+#define EXTMEM_ICACHE_UNLOCK_ENA_M (EXTMEM_ICACHE_UNLOCK_ENA_V << EXTMEM_ICACHE_UNLOCK_ENA_S)
+#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x00000001
+#define EXTMEM_ICACHE_UNLOCK_ENA_S 1
+
+/* EXTMEM_ICACHE_LOCK_ENA : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable lock operation. It will be cleared by hardware
+ * after lock operation done.
+ */
+
+#define EXTMEM_ICACHE_LOCK_ENA (BIT(0))
+#define EXTMEM_ICACHE_LOCK_ENA_M (EXTMEM_ICACHE_LOCK_ENA_V << EXTMEM_ICACHE_LOCK_ENA_S)
+#define EXTMEM_ICACHE_LOCK_ENA_V 0x00000001
+#define EXTMEM_ICACHE_LOCK_ENA_S 0
+
+/* EXTMEM_ICACHE_LOCK_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x80)
+
+/* EXTMEM_ICACHE_LOCK_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for lock
+ * operations. It should be combined with ICACHE_LOCK_SIZE_REG.
+ */
+
+#define EXTMEM_ICACHE_LOCK_ADDR 0xffffffff
+#define EXTMEM_ICACHE_LOCK_ADDR_M (EXTMEM_ICACHE_LOCK_ADDR_V << EXTMEM_ICACHE_LOCK_ADDR_S)
+#define EXTMEM_ICACHE_LOCK_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_LOCK_ADDR_S 0
+
+/* EXTMEM_ICACHE_LOCK_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x84)
+
+/* EXTMEM_ICACHE_LOCK_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the length for lock operations. The bits
+ * are the counts of cache block. It should be combined with
+ * ICACHE_LOCK_ADDR_REG.
+ */
+
+#define EXTMEM_ICACHE_LOCK_SIZE 0x0000ffff
+#define EXTMEM_ICACHE_LOCK_SIZE_M (EXTMEM_ICACHE_LOCK_SIZE_V << EXTMEM_ICACHE_LOCK_SIZE_S)
+#define EXTMEM_ICACHE_LOCK_SIZE_V 0x0000ffff
+#define EXTMEM_ICACHE_LOCK_SIZE_S 0
+
+/* EXTMEM_ICACHE_SYNC_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x88)
+
+/* EXTMEM_ICACHE_SYNC_DONE : RO; bitpos: [1]; default: 0;
+ * The bit is used to indicate invalidate operation is finished.
+ */
+
+#define EXTMEM_ICACHE_SYNC_DONE (BIT(1))
+#define EXTMEM_ICACHE_SYNC_DONE_M (EXTMEM_ICACHE_SYNC_DONE_V << EXTMEM_ICACHE_SYNC_DONE_S)
+#define EXTMEM_ICACHE_SYNC_DONE_V 0x00000001
+#define EXTMEM_ICACHE_SYNC_DONE_S 1
+
+/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W; bitpos: [0]; default: 1;
+ * The bit is used to enable invalidate operation. It will be cleared by
+ * hardware after invalidate operation done.
+ */
+
+#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0))
+#define EXTMEM_ICACHE_INVALIDATE_ENA_M (EXTMEM_ICACHE_INVALIDATE_ENA_V << EXTMEM_ICACHE_INVALIDATE_ENA_S)
+#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x00000001
+#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0
+
+/* EXTMEM_ICACHE_SYNC_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x8c)
+
+/* EXTMEM_ICACHE_SYNC_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for clean
+ * operations. It should be combined with ICACHE_SYNC_SIZE_REG.
+ */
+
+#define EXTMEM_ICACHE_SYNC_ADDR 0xffffffff
+#define EXTMEM_ICACHE_SYNC_ADDR_M (EXTMEM_ICACHE_SYNC_ADDR_V << EXTMEM_ICACHE_SYNC_ADDR_S)
+#define EXTMEM_ICACHE_SYNC_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_SYNC_ADDR_S 0
+
+/* EXTMEM_ICACHE_SYNC_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x90)
+
+/* EXTMEM_ICACHE_SYNC_SIZE : R/W; bitpos: [22:0]; default: 0;
+ * The bits are used to configure the length for sync operations. The bits
+ * are the counts of cache block. It should be combined with
+ * ICACHE_SYNC_ADDR_REG.
+ */
+
+#define EXTMEM_ICACHE_SYNC_SIZE 0x007fffff
+#define EXTMEM_ICACHE_SYNC_SIZE_M (EXTMEM_ICACHE_SYNC_SIZE_V << EXTMEM_ICACHE_SYNC_SIZE_S)
+#define EXTMEM_ICACHE_SYNC_SIZE_V 0x007fffff
+#define EXTMEM_ICACHE_SYNC_SIZE_S 0
+
+/* EXTMEM_ICACHE_PRELOAD_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x94)
+
+/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W; bitpos: [2]; default: 0;
+ * The bit is used to configure the direction of preload operation. 1:
+ * descending, 0: ascending.
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2))
+#define EXTMEM_ICACHE_PRELOAD_ORDER_M (EXTMEM_ICACHE_PRELOAD_ORDER_V << EXTMEM_ICACHE_PRELOAD_ORDER_S)
+#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x00000001
+#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2
+
+/* EXTMEM_ICACHE_PRELOAD_DONE : RO; bitpos: [1]; default: 1;
+ * The bit is used to indicate preload operation is finished.
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_DONE_M (EXTMEM_ICACHE_PRELOAD_DONE_V << EXTMEM_ICACHE_PRELOAD_DONE_S)
+#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x00000001
+#define EXTMEM_ICACHE_PRELOAD_DONE_S 1
+
+/* EXTMEM_ICACHE_PRELOAD_ENA : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable preload operation. It will be cleared by
+ * hardware after preload operation done.
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0))
+#define EXTMEM_ICACHE_PRELOAD_ENA_M (EXTMEM_ICACHE_PRELOAD_ENA_V << EXTMEM_ICACHE_PRELOAD_ENA_S)
+#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x00000001
+#define EXTMEM_ICACHE_PRELOAD_ENA_S 0
+
+/* EXTMEM_ICACHE_PRELOAD_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x98)
+
+/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address for preload
+ * operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_ADDR 0xffffffff
+#define EXTMEM_ICACHE_PRELOAD_ADDR_M (EXTMEM_ICACHE_PRELOAD_ADDR_V << EXTMEM_ICACHE_PRELOAD_ADDR_S)
+#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0
+
+/* EXTMEM_ICACHE_PRELOAD_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x9c)
+
+/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W; bitpos: [15:0]; default: 0;
+ * The bits are used to configure the length for preload operation. The bits
+ * are the counts of cache block. It should be combined with
+ * ICACHE_PRELOAD_ADDR_REG..
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000ffff
+#define EXTMEM_ICACHE_PRELOAD_SIZE_M (EXTMEM_ICACHE_PRELOAD_SIZE_V << EXTMEM_ICACHE_PRELOAD_SIZE_S)
+#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0x0000ffff
+#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0
+
+/* EXTMEM_ICACHE_AUTOLOAD_CTRL_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0xa0)
+
+/* EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR : R/W; bitpos: [9]; default: 0;
+ * The bit is used to clear autoload buffer in icache.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR (BIT(9))
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_M (EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V << EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S)
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_V 0x00000001
+#define EXTMEM_ICACHE_AUTOLOAD_BUFFER_CLEAR_S 9
+
+/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W; bitpos: [8:7]; default: 0;
+ * The bits are used to configure the numbers of the cache block for the
+ * issuing autoload operation.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SIZE_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7
+
+/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W; bitpos: [6:5]; default: 0;
+ * The bits are used to configure trigger conditions for autoload. 0/3:
+ * cache miss, 1: cache hit, 2: both cache miss and hit.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_M (EXTMEM_ICACHE_AUTOLOAD_RQST_V << EXTMEM_ICACHE_AUTOLOAD_RQST_S)
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x00000003
+#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5
+
+/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W; bitpos: [4]; default: 0;
+ * The bits are used to configure the direction of autoload. 1: descending,
+ * 0: ascending.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4))
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (EXTMEM_ICACHE_AUTOLOAD_ORDER_V << EXTMEM_ICACHE_AUTOLOAD_ORDER_S)
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x00000001
+#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4
+
+/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO; bitpos: [3]; default: 1;
+ * The bit is used to indicate autoload operation is finished.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3))
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (EXTMEM_ICACHE_AUTOLOAD_DONE_V << EXTMEM_ICACHE_AUTOLOAD_DONE_S)
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x00000001
+#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3
+
+/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W; bitpos: [2]; default: 0;
+ * The bit is used to enable and disable autoload operation. It is combined
+ * with icache_autoload_done. 1: enable, 0: disable.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2))
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (EXTMEM_ICACHE_AUTOLOAD_ENA_V << EXTMEM_ICACHE_AUTOLOAD_ENA_S)
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x00000001
+#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W; bitpos: [1]; default: 0;
+ * The bits are used to enable the second section for autoload operation.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x00000001
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W; bitpos: [0]; default: 0;
+ * The bits are used to enable the first section for autoload operation.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0))
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x00000001
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0xa4)
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address of the first
+ * section for autoload operation. It should be combined with
+ * icache_autoload_sct0_ena.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xffffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0xa8)
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W; bitpos: [26:0]; default: 0;
+ * The bits are used to configure the length of the first section for
+ * autoload operation. It should be combined with icache_autoload_sct0_ena.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07ffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x07ffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0xac)
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address of the second
+ * section for autoload operation. It should be combined with
+ * icache_autoload_sct1_ena.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xffffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xffffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0xb0)
+
+/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W; bitpos: [26:0]; default: 0;
+ * The bits are used to configure the length of the second section for
+ * autoload operation. It should be combined with icache_autoload_sct1_ena.
+ */
+
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07ffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M (EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V << EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x07ffffff
+#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0
+
+/* EXTMEM_IBUS_TO_FLASH_START_VADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xb4)
+
+/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default:
+ * 1140850688;
+ * The bits are used to configure the start virtual address of ibus to
+ * access flash. The register is used to give constraints to ibus access
+ * counter.
+ */
+
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xffffffff
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M (EXTMEM_IBUS_TO_FLASH_START_VADDR_V << EXTMEM_IBUS_TO_FLASH_START_VADDR_S)
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xffffffff
+#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0
+
+/* EXTMEM_IBUS_TO_FLASH_END_VADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xb8)
+
+/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 1207959551;
+ * The bits are used to configure the end virtual address of ibus to access
+ * flash. The register is used to give constraints to ibus access counter.
+ */
+
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xffffffff
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M (EXTMEM_IBUS_TO_FLASH_END_VADDR_V << EXTMEM_IBUS_TO_FLASH_END_VADDR_S)
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xffffffff
+#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0
+
+/* EXTMEM_DBUS_TO_FLASH_START_VADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0xbc)
+
+/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the start virtual address of dbus to
+ * access flash. The register is used to give constraints to dbus access
+ * counter.
+ */
+
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xffffffff
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M (EXTMEM_DBUS_TO_FLASH_START_VADDR_V << EXTMEM_DBUS_TO_FLASH_START_VADDR_S)
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xffffffff
+#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0
+
+/* EXTMEM_DBUS_TO_FLASH_END_VADDR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0xc0)
+
+/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W; bitpos: [31:0]; default: 0;
+ * The bits are used to configure the end virtual address of dbus to access
+ * flash. The register is used to give constraints to dbus access counter.
+ */
+
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xffffffff
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M (EXTMEM_DBUS_TO_FLASH_END_VADDR_V << EXTMEM_DBUS_TO_FLASH_END_VADDR_S)
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xffffffff
+#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0
+
+/* EXTMEM_CACHE_ACS_CNT_CLR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0xc4)
+
+/* EXTMEM_ICACHE_ACS_CNT_CLR : WOD; bitpos: [1]; default: 0;
+ * The bit is used to clear icache counter.
+ */
+
+#define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1))
+#define EXTMEM_ICACHE_ACS_CNT_CLR_M (EXTMEM_ICACHE_ACS_CNT_CLR_V << EXTMEM_ICACHE_ACS_CNT_CLR_S)
+#define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x00000001
+#define EXTMEM_ICACHE_ACS_CNT_CLR_S 1
+
+/* EXTMEM_DCACHE_ACS_CNT_CLR : WOD; bitpos: [0]; default: 0;
+ * The bit is used to clear dcache counter.
+ */
+
+#define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0))
+#define EXTMEM_DCACHE_ACS_CNT_CLR_M (EXTMEM_DCACHE_ACS_CNT_CLR_V << EXTMEM_DCACHE_ACS_CNT_CLR_S)
+#define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x00000001
+#define EXTMEM_DCACHE_ACS_CNT_CLR_S 0
+
+/* EXTMEM_IBUS_ACS_MISS_CNT_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xc8)
+
+/* EXTMEM_IBUS_ACS_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ * The bits are used to count the number of the cache miss caused by ibus
+ * access flash/spiram.
+ */
+
+#define EXTMEM_IBUS_ACS_MISS_CNT 0xffffffff
+#define EXTMEM_IBUS_ACS_MISS_CNT_M (EXTMEM_IBUS_ACS_MISS_CNT_V << EXTMEM_IBUS_ACS_MISS_CNT_S)
+#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xffffffff
+#define EXTMEM_IBUS_ACS_MISS_CNT_S 0
+
+/* EXTMEM_IBUS_ACS_CNT_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xcc)
+
+/* EXTMEM_IBUS_ACS_CNT : RO; bitpos: [31:0]; default: 0;
+ * The bits are used to count the number of ibus access flash/spiram through
+ * icache.
+ */
+
+#define EXTMEM_IBUS_ACS_CNT 0xffffffff
+#define EXTMEM_IBUS_ACS_CNT_M (EXTMEM_IBUS_ACS_CNT_V << EXTMEM_IBUS_ACS_CNT_S)
+#define EXTMEM_IBUS_ACS_CNT_V 0xffffffff
+#define EXTMEM_IBUS_ACS_CNT_S 0
+
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd0)
+
+/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ * The bits are used to count the number of the cache miss caused by dbus
+ * access flash.
+ */
+
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xffffffff
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M (EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V << EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xffffffff
+#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0
+
+/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd4)
+
+/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO; bitpos: [31:0]; default: 0;
+ * The bits are used to count the number of the cache miss caused by dbus
+ * access spiram.
+ */
+
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xffffffff
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M (EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V << EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S)
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xffffffff
+#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0
+
+/* EXTMEM_DBUS_ACS_CNT_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0xd8)
+
+/* EXTMEM_DBUS_ACS_CNT : RO; bitpos: [31:0]; default: 0;
+ * The bits are used to count the number of dbus access flash/spiram through
+ * dcache.
+ */
+
+#define EXTMEM_DBUS_ACS_CNT 0xffffffff
+#define EXTMEM_DBUS_ACS_CNT_M (EXTMEM_DBUS_ACS_CNT_V << EXTMEM_DBUS_ACS_CNT_S)
+#define EXTMEM_DBUS_ACS_CNT_V 0xffffffff
+#define EXTMEM_DBUS_ACS_CNT_S 0
+
+/* EXTMEM_CACHE_ILG_INT_ENA_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0xdc)
+
+/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W; bitpos: [8]; default: 0;
+ * The bit is used to enable interrupt by dbus counter overflow.
+ */
+
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (EXTMEM_DBUS_CNT_OVF_INT_ENA_V << EXTMEM_DBUS_CNT_OVF_INT_ENA_S)
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x00000001
+#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8
+
+/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W; bitpos: [7]; default: 0;
+ * The bit is used to enable interrupt by ibus counter overflow.
+ */
+
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (EXTMEM_IBUS_CNT_OVF_INT_ENA_V << EXTMEM_IBUS_CNT_OVF_INT_ENA_S)
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x00000001
+#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7
+
+/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W; bitpos: [6]; default: 0;
+ * The bit is used to enable interrupt by dcache trying to replace a line
+ * whose blocks all have been occupied by occupy-mode.
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V << EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S)
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x00000001
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6
+
+/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W; bitpos: [5]; default: 0;
+ * The bit is used to enable interrupt by mmu entry fault.
+ */
+
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V << EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S)
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x00000001
+#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5
+
+/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W; bitpos: [4]; default: 0;
+ * The bit is used to enable interrupt by dcache trying to write flash.
+ */
+
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V << EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S)
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x00000001
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4
+
+/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [3]; default: 0;
+ * The bit is used to enable interrupt by preload configurations fault.
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S)
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3
+
+/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [2]; default: 0;
+ * The bit is used to enable interrupt by sync configurations fault.
+ */
+
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S)
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2
+
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W; bitpos: [1]; default: 0;
+ * The bit is used to enable interrupt by preload configurations fault.
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S)
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x00000001
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1
+
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W; bitpos: [0]; default: 0;
+ * The bit is used to enable interrupt by sync configurations fault.
+ */
+
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S)
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x00000001
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0
+
+/* EXTMEM_CACHE_ILG_INT_CLR_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0xe0)
+
+/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD; bitpos: [8]; default: 0;
+ * The bit is used to clear interrupt by dbus counter overflow.
+ */
+
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8))
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (EXTMEM_DBUS_CNT_OVF_INT_CLR_V << EXTMEM_DBUS_CNT_OVF_INT_CLR_S)
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x00000001
+#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8
+
+/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD; bitpos: [7]; default: 0;
+ * The bit is used to clear interrupt by ibus counter overflow.
+ */
+
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7))
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (EXTMEM_IBUS_CNT_OVF_INT_CLR_V << EXTMEM_IBUS_CNT_OVF_INT_CLR_S)
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x00000001
+#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7
+
+/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD; bitpos: [6]; default: 0;
+ * The bit is used to clear interrupt by dcache trying to replace a line
+ * whose blocks all have been occupied by occupy-mode.
+ */
+
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6))
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V << EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S)
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x00000001
+#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6
+
+/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD; bitpos: [5]; default: 0;
+ * The bit is used to clear interrupt by mmu entry fault.
+ */
+
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5))
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V << EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S)
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x00000001
+#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5
+
+/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD; bitpos: [4]; default: 0;
+ * The bit is used to clear interrupt by dcache trying to write flash.
+ */
+
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4))
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V << EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S)
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x00000001
+#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4
+
+/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [3]; default: 0;
+ * The bit is used to clear interrupt by preload configurations fault.
+ */
+
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3))
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S)
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001
+#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3
+
+/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [2]; default: 0;
+ * The bit is used to clear interrupt by sync configurations fault.
+ */
+
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2))
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S)
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001
+#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2
+
+/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD; bitpos: [1]; default: 0;
+ * The bit is used to clear interrupt by preload configurations fault.
+ */
+
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1))
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S)
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x00000001
+#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1
+
+/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD; bitpos: [0]; default: 0;
+ * The bit is used to clear interrupt by sync configurations fault.
+ */
+
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0))
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V << EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S)
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x00000001
+#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0
+
+/* EXTMEM_CACHE_ILG_INT_ST_REG register
+ * ******* Description ***********
+ */
+
+#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0xe4)
+
+/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO; bitpos: [11]; default: 0;
+ * The bit is used to indicate interrupt by dbus access spiram miss counter
+ * overflow.
+ */
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