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Posted to commits@nuttx.apache.org by xi...@apache.org on 2024/02/24 02:16:16 UTC
(nuttx) branch master updated (1b7ddab317 -> 8c4612be50)
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
from 1b7ddab317 cmake:adapt the header file symbolic link to the common directory
new f76017ca8a arch/intel64: format asm files, remove unused debug macros
new b4b96a6435 arch/intel64: convert __nxstart to C function and move appropriate functions there
new 8a43bf1b50 arch/intel64: clear BSS in __nxstart
new 8c4612be50 arch/intel64: add g_ prefix to global data
The 4 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/x86_64/include/intel64/arch.h | 24 +-
arch/x86_64/src/intel64/CMakeLists.txt | 1 +
arch/x86_64/src/intel64/Make.defs | 3 +-
arch/x86_64/src/intel64/intel64.h | 2 +-
.../src/intel64/intel64_fullcontextrestore.S | 197 +++----
arch/x86_64/src/intel64/intel64_head.S | 576 ++++++++++-----------
arch/x86_64/src/intel64/intel64_irq.c | 24 +-
arch/x86_64/src/intel64/intel64_lowsetup.c | 112 +---
arch/x86_64/src/intel64/intel64_map_region.c | 2 +-
arch/x86_64/src/intel64/intel64_saveusercontext.S | 157 +++---
.../{intel64_lowsetup.c => intel64_start.c} | 86 ++-
arch/x86_64/src/intel64/intel64_vectors.S | 436 ++++++++--------
12 files changed, 712 insertions(+), 908 deletions(-)
copy arch/x86_64/src/intel64/{intel64_lowsetup.c => intel64_start.c} (63%)
(nuttx) 02/04: arch/intel64: convert __nxstart to C function and move appropriate functions there
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit b4b96a6435a3a1f2c16183da7d8048dccfed6e6f
Author: p-szafonimateusz <p-...@xiaomi.com>
AuthorDate: Tue Feb 20 14:43:55 2024 +0100
arch/intel64: convert __nxstart to C function and move appropriate functions there
to follow the approach in other architectures
Signed-off-by: p-szafonimateusz <p-...@xiaomi.com>
---
arch/x86_64/src/intel64/CMakeLists.txt | 1 +
arch/x86_64/src/intel64/Make.defs | 3 +-
arch/x86_64/src/intel64/intel64.h | 2 +-
arch/x86_64/src/intel64/intel64_head.S | 49 ++++---------
arch/x86_64/src/intel64/intel64_lowsetup.c | 84 +---------------------
.../{intel64_lowsetup.c => intel64_start.c} | 70 +++++-------------
6 files changed, 37 insertions(+), 172 deletions(-)
diff --git a/arch/x86_64/src/intel64/CMakeLists.txt b/arch/x86_64/src/intel64/CMakeLists.txt
index 3e7e4c8a26..7df5c87300 100644
--- a/arch/x86_64/src/intel64/CMakeLists.txt
+++ b/arch/x86_64/src/intel64/CMakeLists.txt
@@ -36,6 +36,7 @@ set(SRCS
intel64_schedulesigaction.c
intel64_sigdeliver.c
intel64_usestack.c
+ intel64_start.c
intel64_handlers.c
intel64_idle.c
intel64_lowsetup.c
diff --git a/arch/x86_64/src/intel64/Make.defs b/arch/x86_64/src/intel64/Make.defs
index 7274d01e6b..a7c1436e96 100644
--- a/arch/x86_64/src/intel64/Make.defs
+++ b/arch/x86_64/src/intel64/Make.defs
@@ -24,6 +24,7 @@ CMN_CSRCS += x86_64_allocateheap.c x86_64_copystate.c x86_64_exit.c
CMN_CSRCS += x86_64_getintstack.c x86_64_mdelay.c x86_64_initialize.c
CMN_CSRCS += x86_64_modifyreg8.c x86_64_modifyreg16.c x86_64_modifyreg32.c
CMN_CSRCS += x86_64_nputs.c x86_64_switchcontext.c x86_64_udelay.c
+
CMN_CSRCS += intel64_createstack.c intel64_initialstate.c intel64_irq.c
CMN_CSRCS += intel64_map_region.c intel64_regdump.c intel64_releasestack.c
CMN_CSRCS += intel64_rtc.c intel64_restore_auxstate.c intel64_savestate.c
@@ -33,7 +34,7 @@ CMN_CSRCS += intel64_sigdeliver.c intel64_usestack.c x86_64_tcbinfo.c
# Required Intel64 files
CHIP_ASRCS = intel64_saveusercontext.S intel64_fullcontextrestore.S intel64_vectors.S intel64_head.S
-CHIP_CSRCS = intel64_handlers.c intel64_idle.c intel64_lowsetup.c
+CHIP_CSRCS = intel64_start.c intel64_handlers.c intel64_idle.c intel64_lowsetup.c
CHIP_CSRCS += intel64_serial.c intel64_rng.c intel64_check_capability.c
# Configuration-dependent intel64 files
diff --git a/arch/x86_64/src/intel64/intel64.h b/arch/x86_64/src/intel64/intel64.h
index b8d644038e..c07f688424 100644
--- a/arch/x86_64/src/intel64/intel64.h
+++ b/arch/x86_64/src/intel64/intel64.h
@@ -72,7 +72,7 @@ extern "C"
* Name: intel64_lowsetup
*
* Description:
- * Called at the very beginning of _start.
+ * Called at the very beginning of _nxstart.
* Performs low level initializationincluding setup of the console UART.
* This UART done early so that the serial console is available for
* debugging very early in the boot sequence.
diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S
index 62782345ca..e462bdc279 100644
--- a/arch/x86_64/src/intel64/intel64_head.S
+++ b/arch/x86_64/src/intel64/intel64_head.S
@@ -45,12 +45,11 @@
****************************************************************************/
.global __pmode_entry /* The 32bit protected mode entry */
- .global __nxstart
.global __enable_sse_avx
.global __enable_pcid
.global __revoke_low_memory
+ .global __nxstart /* __nxstart is defined elsewhere */
.global nx_start /* nx_start is defined elsewhere */
- .global up_lowsetup /* up_lowsetup is defined elsewhere */
.global g_idle_topstack /* The end of the idle stack, the start of the heap */
.global mb_info_struct
.global mb_magic
@@ -267,28 +266,7 @@ start64:
mov %ax, %fs
mov %ax, %gs
- /* Finally, we can start the OS */
- movabs $__nxstart, %rbx
- jmp *%rbx
- .size __pmode_entry, . - __pmode_entry
-
-/****************************************************************************
- * Name: __nxstart
- *
- * Description:
- * Do low-level initialization and call nx_start
- *
- ****************************************************************************/
-
- .section .text, "ax"
- .type __nxstart, @function
-
-__nxstart:
- /* We are now in high memory, will revoke the lower 128MB memory mapping
- * in lowsetup
- */
-
- /* clear out bss section */
+ /* Clear out bss section */
movabs $_sbss, %rbx
movabs $_ebss, %rdx
clear_bss:
@@ -301,20 +279,16 @@ clear_bss:
movabs $g_idle_topstack, %rbx
mov (%rbx), %rsp
- /* Initialize and start NuttX */
- call up_lowsetup /* Low-level, pre-OS initialization */
-
- call nx_start /* Start NuttX */
-
- /* NuttX will not return */
- /* We should never end up here */
- /* If we really do, then we are doomed, halting the processor for ever */
+ /* We use jmp instruction below which doesn't push 1 byte on stack, so we
+ * have to push a dummy value here, otherwise SSE instructions calledd
+ * during initialization will fail.
+ */
+ pushq $0
- cli
-hang:
- hlt /* Halt machine should NuttX return */
- jmp hang
- .size __nxstart, . - __nxstart
+ /* Finally, we can start the OS */
+ movabs $__nxstart, %rbx
+ jmp *%rbx
+ .size __pmode_entry, . - __pmode_entry
/****************************************************************************
* Name: __revoke_low_memory
@@ -324,6 +298,7 @@ hang:
*
****************************************************************************/
+ .section .text, "ax"
.type __revoke_low_memory, @function
__revoke_low_memory:
diff --git a/arch/x86_64/src/intel64/intel64_lowsetup.c b/arch/x86_64/src/intel64/intel64_lowsetup.c
index c61864f6cb..9718afd845 100644
--- a/arch/x86_64/src/intel64/intel64_lowsetup.c
+++ b/arch/x86_64/src/intel64/intel64_lowsetup.c
@@ -25,8 +25,6 @@
#include <nuttx/config.h>
#include <nuttx/arch.h>
-#include <arch/board/board.h>
-#include <arch/multiboot2.h>
#include "x86_64_internal.h"
@@ -53,77 +51,24 @@ volatile uint64_t *pt;
volatile struct ist_s *ist64;
volatile struct gdt_entry_s *gdt64;
-/* This holds information passed by the multiboot2 bootloader */
-
-uint32_t mb_magic __attribute__((section(".loader.bss")));
-uint32_t mb_info_struct __attribute__((section(".loader.bss")));
-
/****************************************************************************
* Private Functions
****************************************************************************/
-#ifdef CONFIG_ARCH_MULTIBOOT2
-/****************************************************************************
- * Name: x86_64_mb2_config
- *
- * Description:
- * Parse multiboot2 info.
- *
- ****************************************************************************/
-
-static void x86_64_mb2_config(void)
-{
- struct multiboot_tag *tag;
-
- /* Check that we were actually booted by a mulitboot2 bootloader */
-
- if (mb_magic != MULTIBOOT2_BOOTLOADER_MAGIC)
- {
- return;
- }
-
- for (tag = (struct multiboot_tag *)(uintptr_t)(mb_info_struct + 8);
- tag->type != MULTIBOOT_TAG_TYPE_END;
- tag = (struct multiboot_tag *)((uint8_t *)tag +
- ((tag->size + 7) & ~7)))
- {
- switch (tag->type)
- {
- case MULTIBOOT_TAG_TYPE_EFI64:
- {
- break;
- }
-
-#ifdef CONFIG_MULTBOOT2_FB_TERM
- case MULTIBOOT_TAG_TYPE_FRAMEBUFFER:
- {
- x86_64_mb2_fbinitialize(
- (struct multiboot_tag_framebuffer *)tag);
- break;
- }
-#endif
-
- default:
- break;
- }
- }
-}
-#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: up_lowsetup
+ * Name: intel64_lowsetup
*
* Description:
- * Called from intel64_head BEFORE starting the operating system in order
+ * Called from __nxstart BEFORE starting the operating system in order
* perform any necessary, early initialization.
*
****************************************************************************/
-void up_lowsetup(void)
+void intel64_lowsetup(void)
{
/* we should be in long mode at this point */
@@ -148,30 +93,7 @@ void up_lowsetup(void)
x86_64_check_and_enable_capability();
-#ifdef CONFIG_ARCH_MULTIBOOT2
- /* Handle multiboot2 info */
-
- x86_64_mb2_config();
-#endif
-
/* Revoke the lower memory */
__revoke_low_memory();
-
- /* perform board-specific initializations */
-
- x86_64_boardinitialize();
-
-#ifdef USE_EARLYSERIALINIT
- /* Early serial driver initialization */
-
- x86_64_earlyserialinit();
-#endif
-
- x86_64_timer_calibrate_freq();
-
-#ifdef CONFIG_LIB_SYSCALL
- enable_syscall();
-#endif
}
-
diff --git a/arch/x86_64/src/intel64/intel64_lowsetup.c b/arch/x86_64/src/intel64/intel64_start.c
similarity index 67%
copy from arch/x86_64/src/intel64/intel64_lowsetup.c
copy to arch/x86_64/src/intel64/intel64_start.c
index c61864f6cb..89e3e9960b 100644
--- a/arch/x86_64/src/intel64/intel64_lowsetup.c
+++ b/arch/x86_64/src/intel64/intel64_start.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/x86_64/src/intel64/intel64_lowsetup.c
+ * arch/x86_64/src/intel64/intel64_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
@@ -24,35 +24,18 @@
#include <nuttx/config.h>
-#include <nuttx/arch.h>
+#include <nuttx/init.h>
+
#include <arch/board/board.h>
#include <arch/multiboot2.h>
#include "x86_64_internal.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
+#include "intel64.h"
/****************************************************************************
* Public Data
****************************************************************************/
-/* The actual address of the page table and gdt/ist after mapping the kernel
- * in high address.
- */
-
-volatile uint64_t *pdpt;
-volatile uint64_t *pd;
-volatile uint64_t *pt;
-
-volatile struct ist_s *ist64;
-volatile struct gdt_entry_s *gdt64;
-
/* This holds information passed by the multiboot2 bootloader */
uint32_t mb_magic __attribute__((section(".loader.bss")));
@@ -75,7 +58,7 @@ static void x86_64_mb2_config(void)
{
struct multiboot_tag *tag;
- /* Check that we were actually booted by a mulitboot2 bootloader */
+ /* Check that we were actually booted by a multiboot2 bootloader */
if (mb_magic != MULTIBOOT2_BOOTLOADER_MAGIC)
{
@@ -115,38 +98,18 @@ static void x86_64_mb2_config(void)
****************************************************************************/
/****************************************************************************
- * Name: up_lowsetup
+ * Name: __nxstart
*
* Description:
- * Called from intel64_head BEFORE starting the operating system in order
- * perform any necessary, early initialization.
+ * Do low-level initialization and call nx_start.
*
****************************************************************************/
-void up_lowsetup(void)
+void __nxstart(void)
{
- /* we should be in long mode at this point */
-
- /* GDT is loaded with 64bit GDT */
-
- /* Paging is enabled */
-
- /* Setup pointers for accessing Page table and GDT in high address */
+ /* Low-level, pre-OS initialization */
- pdpt = (uint64_t *)((uintptr_t)&pdpt_low + X86_64_LOAD_OFFSET);
- pd = (uint64_t *)((uintptr_t)&pd_low + X86_64_LOAD_OFFSET);
- pt = (uint64_t *)((uintptr_t)&pt_low + X86_64_LOAD_OFFSET);
-
- ist64 = (struct ist_s *)((uintptr_t)&ist64_low + X86_64_LOAD_OFFSET);
- gdt64 = (struct gdt_entry_s *)((uintptr_t)&gdt64_low + X86_64_LOAD_OFFSET);
-
- /* reload the GDTR with mapped high memory address */
-
- setgdt((void *)gdt64, (uintptr_t)(&gdt64_low_end - &gdt64_low) - 1);
-
- /* Do some checking on CPU compatibilities */
-
- x86_64_check_and_enable_capability();
+ intel64_lowsetup();
#ifdef CONFIG_ARCH_MULTIBOOT2
/* Handle multiboot2 info */
@@ -154,10 +117,6 @@ void up_lowsetup(void)
x86_64_mb2_config();
#endif
- /* Revoke the lower memory */
-
- __revoke_low_memory();
-
/* perform board-specific initializations */
x86_64_boardinitialize();
@@ -173,5 +132,12 @@ void up_lowsetup(void)
#ifdef CONFIG_LIB_SYSCALL
enable_syscall();
#endif
-}
+ /* Start NuttX */
+
+ nx_start();
+
+ /* Shouldn't get here */
+
+ for (; ; );
+}
(nuttx) 04/04: arch/intel64: add g_ prefix to global data
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 8c4612be508fc65ce0e2c958c5b471ad13fa5b32
Author: p-szafonimateusz <p-...@xiaomi.com>
AuthorDate: Tue Feb 20 14:45:47 2024 +0100
arch/intel64: add g_ prefix to global data
to follow NuttX coding standard
Signed-off-by: p-szafonimateusz <p-...@xiaomi.com>
---
arch/x86_64/include/intel64/arch.h | 24 ++++++------
arch/x86_64/src/intel64/intel64_head.S | 56 ++++++++++++++--------------
arch/x86_64/src/intel64/intel64_irq.c | 24 ++++++------
arch/x86_64/src/intel64/intel64_lowsetup.c | 24 ++++++------
arch/x86_64/src/intel64/intel64_map_region.c | 2 +-
arch/x86_64/src/intel64/intel64_start.c | 8 ++--
6 files changed, 70 insertions(+), 68 deletions(-)
diff --git a/arch/x86_64/include/intel64/arch.h b/arch/x86_64/include/intel64/arch.h
index e685551822..ff2dfd6d09 100644
--- a/arch/x86_64/include/intel64/arch.h
+++ b/arch/x86_64/include/intel64/arch.h
@@ -357,25 +357,25 @@ begin_packed_struct struct ist_s
/* These are defined in intel64_head.S */
-extern volatile uint8_t pdpt_low;
-extern volatile uint8_t pd_low;
-extern volatile uint8_t pt_low;
+extern volatile uint8_t g_pdpt_low;
+extern volatile uint8_t g_pd_low;
+extern volatile uint8_t g_pt_low;
-extern volatile uint8_t ist64_low;
-extern volatile uint8_t gdt64_low;
-extern volatile uint8_t gdt64_ist_low;
-extern volatile uint8_t gdt64_low_end;
+extern volatile uint8_t g_ist64_low;
+extern volatile uint8_t g_gdt64_low;
+extern volatile uint8_t g_gdt64_ist_low;
+extern volatile uint8_t g_gdt64_low_end;
/* The actual address of the page table and gdt/ist after mapping the kernel
* in high address
*/
-extern volatile uint64_t *pdpt;
-extern volatile uint64_t *pd;
-extern volatile uint64_t *pt;
+extern volatile uint64_t *g_pdpt;
+extern volatile uint64_t *g_pd;
+extern volatile uint64_t *g_pt;
-extern volatile struct ist_s *ist64;
-extern volatile struct gdt_entry_s *gdt64;
+extern volatile struct ist_s *g_ist64;
+extern volatile struct gdt_entry_s *g_gdt64;
/****************************************************************************
* Public Function Prototypes
diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S
index 51b0bda484..50ea7c3f9a 100644
--- a/arch/x86_64/src/intel64/intel64_head.S
+++ b/arch/x86_64/src/intel64/intel64_head.S
@@ -51,20 +51,20 @@
.global __nxstart /* __nxstart is defined elsewhere */
.global nx_start /* nx_start is defined elsewhere */
.global g_idle_topstack /* The end of the idle stack, the start of the heap */
- .global mb_info_struct
- .global mb_magic
+ .global g_mb_info_struct
+ .global g_mb_magic
/* These are the page tables */
- .global pdpt_low
- .global pd_low
- .global pt_low
+ .global g_pdpt_low
+ .global g_pd_low
+ .global g_pt_low
/* These are the GDT */
- .global gdt64_low
- .global gdt64_ist_low
- .global gdt64_low_end
+ .global g_gdt64_low
+ .global g_gdt64_ist_low
+ .global g_gdt64_low_end
- .global ist64_low
+ .global g_ist64_low
/****************************************************************************
* The multiboot2 header
@@ -162,13 +162,13 @@ start32_0:
__pmode_entry:
start32:
#ifdef CONFIG_ARCH_MULTIBOOT2
- movl %ebx, mb_info_struct
- movl %eax, mb_magic
+ movl %ebx, g_mb_info_struct
+ movl %eax, g_mb_magic
#endif
/* initialize rest of the page directory */
- lea pd_low, %edi
- lea pt_low, %esi
+ lea g_pd_low, %edi
+ lea g_pt_low, %esi
/* Popluate the lower 4GB as non-present
* for ecx = 0...512 * 4 : Loop and setup the page directories
@@ -195,7 +195,7 @@ ept_loop:
jnz epd_loop
/* Temporary populate the lower 128MB on 1:1 mapping */
- lea pd_low, %edi
+ lea g_pd_low, %edi
mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax
/* for ecx = 0...64 : Loop and setup 64x 2MB page directories */
@@ -212,7 +212,7 @@ pd_loop:
/* Populate the 1GB after 4GB boundary with Global mapping to kernel code.
* This creates maps the lower 1GB to 4GB~5GB
*/
- lea pdpt_low, %edi
+ lea g_pdpt_low, %edi
mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax
mov $0x4, %ecx
@@ -294,8 +294,8 @@ start64:
__revoke_low_memory:
/* Revoke the lower 128MB memory mapping */
- lea pd_low, %edi
- lea pt_low, %esi
+ lea g_pd_low, %edi
+ lea g_pt_low, %esi
/* for ecx = 0...64 : Loop and setup 64x 2MB page directories */
mov $64, %ecx
@@ -373,7 +373,7 @@ __enable_pcid:
/* IST for 64 bit long mode will be filled in up_irq */
.align(16)
-ist64_low:
+g_ist64_low:
.long 0
.quad 0xdeadbeefdeadbee0
.quad 0xdeadbeefdeadbee1
@@ -391,32 +391,32 @@ ist64_low:
/* GDT for 64 bit long mode */
.align(16)
-gdt64_low:
+g_gdt64_low:
.quad 0
.quad X86_GDT_CODE64_ENTRY
.quad X86_GDT_DATA_ENTRY
.quad X86_GDT_CODE32_ENTRY
.quad X86_GDT_DATA_ENTRY
.quad X86_GDT_CODE64_ENTRY
-gdt64_ist_low:
+g_gdt64_ist_low:
.quad 0x0 /* TSS segment low */
.quad 0x0 /* TSS segment high */
-gdt64_low_end:
+g_gdt64_low_end:
gdt64_ptr:
- .short gdt64_low_end - gdt64_low - 1
- .long gdt64_low
+ .short g_gdt64_low_end - g_gdt64_low - 1
+ .long g_gdt64_low
mxcsr_mem:
.long 0x00001f80
.align(PAGE_SIZE)
pml4:
- .quad pdpt_low + X86_PAGE_PRESENT + X86_PAGE_WR
+ .quad g_pdpt_low + X86_PAGE_PRESENT + X86_PAGE_WR
.align(PAGE_SIZE)
-pdpt_low:
- .quad pd_low + X86_PAGE_PRESENT + X86_PAGE_WR
+g_pdpt_low:
+ .quad g_pd_low + X86_PAGE_PRESENT + X86_PAGE_WR
.quad pd_2_low + X86_PAGE_PRESENT + X86_PAGE_WR
.quad pd_3_low + X86_PAGE_PRESENT + X86_PAGE_WR
.quad pd_4_low + X86_PAGE_PRESENT + X86_PAGE_WR
@@ -424,7 +424,7 @@ pdpt_low:
.fill X86_NUM_PAGE_ENTRY - 4, X86_PAGE_ENTRY_SIZE, 0
.align(PAGE_SIZE)
-pd_low:
+g_pd_low:
.fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
.align(PAGE_SIZE)
@@ -440,7 +440,7 @@ pd_4_low:
.fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
.align(PAGE_SIZE)
-pt_low:
+g_pt_low:
.fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
.fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
.fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
diff --git a/arch/x86_64/src/intel64/intel64_irq.c b/arch/x86_64/src/intel64/intel64_irq.c
index 3e9494e5f8..42ca3dc3f3 100644
--- a/arch/x86_64/src/intel64/intel64_irq.c
+++ b/arch/x86_64/src/intel64/intel64_irq.c
@@ -72,7 +72,7 @@ uint8_t *g_isr_stack_end = g_isr_stack + IRQ_STACK_SIZE - 16;
* Private Data
****************************************************************************/
-static struct idt_entry_s idt_entries[256];
+static struct idt_entry_s g_idt_entries[256];
/****************************************************************************
* Private Functions
@@ -176,8 +176,8 @@ static void up_ist_init(void)
tss_l.limit_low = (((104 - 1) & 0xffff)); /* Segment limit = TSS size - 1 */
- tss_l.base_low = ((uintptr_t)ist64 & 0x00ffffff); /* Low address 1 */
- tss_l.base_high = (((uintptr_t)ist64 & 0xff000000) >> 24); /* Low address 2 */
+ tss_l.base_low = ((uintptr_t)g_ist64 & 0x00ffffff); /* Low address 1 */
+ tss_l.base_high = (((uintptr_t)g_ist64 & 0xff000000) >> 24); /* Low address 2 */
tss_l.P = 1;
@@ -186,17 +186,17 @@ static void up_ist_init(void)
tss_l.AC = 1;
tss_l.EX = 1;
- tss_h = (((uintptr_t)ist64 >> 32) & 0xffffffff); /* High address */
+ tss_h = (((uintptr_t)g_ist64 >> 32) & 0xffffffff); /* High address */
- gdt64[X86_GDT_ISTL_SEL_NUM] = tss_l;
+ g_gdt64[X86_GDT_ISTL_SEL_NUM] = tss_l;
/* memcpy used to handle type punning compiler warning */
- memcpy((void *)&gdt64[X86_GDT_ISTH_SEL_NUM],
- (void *)&tss_h, sizeof(gdt64[0]));
+ memcpy((void *)&g_gdt64[X86_GDT_ISTH_SEL_NUM],
+ (void *)&tss_h, sizeof(g_gdt64[0]));
- ist64->IST1 = (uintptr_t)g_interrupt_stack_end;
- ist64->IST2 = (uintptr_t)g_isr_stack_end;
+ g_ist64->IST1 = (uintptr_t)g_interrupt_stack_end;
+ g_ist64->IST2 = (uintptr_t)g_isr_stack_end;
asm volatile ("mov $0x30, %%ax; ltr %%ax":::"memory", "rax");
}
@@ -373,7 +373,7 @@ static void up_ioapic_init(void)
static void up_idtentry(unsigned int index, uint64_t base, uint16_t sel,
uint8_t flags, uint8_t ist)
{
- struct idt_entry_s *entry = &idt_entries[index];
+ struct idt_entry_s *entry = &g_idt_entries[index];
entry->lobase = base & 0xffff;
entry->hibase = (base >> 16) & 0xffff;
@@ -404,7 +404,7 @@ struct idt_ptr_s idt_ptr;
static inline void up_idtinit(void)
{
- memset(&idt_entries, 0, sizeof(struct idt_entry_s)*256);
+ memset(&g_idt_entries, 0, sizeof(struct idt_entry_s)*256);
/* Set each ISR/IRQ to the appropriate vector with selector=8 and with
* 32-bit interrupt gate. Interrupt gate (vs. trap gate) will leave
@@ -463,7 +463,7 @@ static inline void up_idtinit(void)
/* Then program the IDT */
- setidt(&idt_entries, sizeof(struct idt_entry_s) * NR_IRQS - 1);
+ setidt(&g_idt_entries, sizeof(struct idt_entry_s) * NR_IRQS - 1);
}
/****************************************************************************
diff --git a/arch/x86_64/src/intel64/intel64_lowsetup.c b/arch/x86_64/src/intel64/intel64_lowsetup.c
index e437644083..ac544e970d 100644
--- a/arch/x86_64/src/intel64/intel64_lowsetup.c
+++ b/arch/x86_64/src/intel64/intel64_lowsetup.c
@@ -44,12 +44,12 @@
* in high address.
*/
-volatile uint64_t *pdpt;
-volatile uint64_t *pd;
-volatile uint64_t *pt;
+volatile uint64_t *g_pdpt;
+volatile uint64_t *g_pd;
+volatile uint64_t *g_pt;
-volatile struct ist_s *ist64;
-volatile struct gdt_entry_s *gdt64;
+volatile struct ist_s *g_ist64;
+volatile struct gdt_entry_s *g_gdt64;
/****************************************************************************
* Private Functions
@@ -78,16 +78,18 @@ void intel64_lowsetup(void)
/* Setup pointers for accessing Page table and GDT in high address */
- pdpt = (uint64_t *)((uintptr_t)&pdpt_low + X86_64_LOAD_OFFSET);
- pd = (uint64_t *)((uintptr_t)&pd_low + X86_64_LOAD_OFFSET);
- pt = (uint64_t *)((uintptr_t)&pt_low + X86_64_LOAD_OFFSET);
+ g_pdpt = (uint64_t *)((uintptr_t)&g_pdpt_low + X86_64_LOAD_OFFSET);
+ g_pd = (uint64_t *)((uintptr_t)&g_pd_low + X86_64_LOAD_OFFSET);
+ g_pt = (uint64_t *)((uintptr_t)&g_pt_low + X86_64_LOAD_OFFSET);
- ist64 = (struct ist_s *)((uintptr_t)&ist64_low + X86_64_LOAD_OFFSET);
- gdt64 = (struct gdt_entry_s *)((uintptr_t)&gdt64_low + X86_64_LOAD_OFFSET);
+ g_ist64 = (struct ist_s *)((uintptr_t)&g_ist64_low +
+ X86_64_LOAD_OFFSET);
+ g_gdt64 = (struct gdt_entry_s *)((uintptr_t)&g_gdt64_low +
+ X86_64_LOAD_OFFSET);
/* reload the GDTR with mapped high memory address */
- setgdt((void *)gdt64, (uintptr_t)(&gdt64_low_end - &gdt64_low) - 1);
+ setgdt((void *)g_gdt64, (uintptr_t)(&g_gdt64_low_end - &g_gdt64_low) - 1);
/* Revoke the lower memory */
diff --git a/arch/x86_64/src/intel64/intel64_map_region.c b/arch/x86_64/src/intel64/intel64_map_region.c
index 789f382da7..69fd2ce8b8 100644
--- a/arch/x86_64/src/intel64/intel64_map_region.c
+++ b/arch/x86_64/src/intel64/intel64_map_region.c
@@ -68,7 +68,7 @@ int up_map_region(void *base, int size, int flags)
{
entry = (curr >> 12) & 0x7ffffff;
- pt[entry] = curr | flags;
+ g_pt[entry] = curr | flags;
curr += PAGE_SIZE;
}
diff --git a/arch/x86_64/src/intel64/intel64_start.c b/arch/x86_64/src/intel64/intel64_start.c
index 9a37998e2b..b19117bfa5 100644
--- a/arch/x86_64/src/intel64/intel64_start.c
+++ b/arch/x86_64/src/intel64/intel64_start.c
@@ -38,8 +38,8 @@
/* This holds information passed by the multiboot2 bootloader */
-uint32_t mb_magic __attribute__((section(".loader.bss")));
-uint32_t mb_info_struct __attribute__((section(".loader.bss")));
+uint32_t g_mb_magic __attribute__((section(".loader.bss")));
+uint32_t g_mb_info_struct __attribute__((section(".loader.bss")));
/****************************************************************************
* Private Functions
@@ -60,12 +60,12 @@ static void x86_64_mb2_config(void)
/* Check that we were actually booted by a multiboot2 bootloader */
- if (mb_magic != MULTIBOOT2_BOOTLOADER_MAGIC)
+ if (g_mb_magic != MULTIBOOT2_BOOTLOADER_MAGIC)
{
return;
}
- for (tag = (struct multiboot_tag *)(uintptr_t)(mb_info_struct + 8);
+ for (tag = (struct multiboot_tag *)(uintptr_t)(g_mb_info_struct + 8);
tag->type != MULTIBOOT_TAG_TYPE_END;
tag = (struct multiboot_tag *)((uint8_t *)tag +
((tag->size + 7) & ~7)))
(nuttx) 01/04: arch/intel64: format asm files, remove unused debug macros
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit f76017ca8a9c9c0ecbbbf598f96e608d1813a309
Author: p-szafonimateusz <p-...@xiaomi.com>
AuthorDate: Wed Feb 7 14:48:04 2024 +0100
arch/intel64: format asm files, remove unused debug macros
use tab at the beginning of lines, remove C++ comments, fix some tabs to spaces
Signed-off-by: p-szafonimateusz <p-...@xiaomi.com>
---
.../src/intel64/intel64_fullcontextrestore.S | 197 ++++----
arch/x86_64/src/intel64/intel64_head.S | 532 +++++++++++----------
arch/x86_64/src/intel64/intel64_saveusercontext.S | 157 +++---
arch/x86_64/src/intel64/intel64_vectors.S | 436 ++++++++---------
4 files changed, 627 insertions(+), 695 deletions(-)
diff --git a/arch/x86_64/src/intel64/intel64_fullcontextrestore.S b/arch/x86_64/src/intel64/intel64_fullcontextrestore.S
index 03c73797f7..545bb3bdd0 100644
--- a/arch/x86_64/src/intel64/intel64_fullcontextrestore.S
+++ b/arch/x86_64/src/intel64/intel64_fullcontextrestore.S
@@ -26,45 +26,13 @@
#include <arch/irq.h>
#include "x86_64_internal.h"
- .file "intel64_fullcontextrestore.S"
-
-/**************************************************************************
- * Pre-processor Definitions
- **************************************************************************/
-
-/**************************************************************************
- * Public Data
- **************************************************************************/
-
-/****************************************************************************
- * Macros
- ****************************************************************************/
-
-/* Trace macros, use like trace 'i' to print char to serial port. */
-
- .macro chout, addr, ch
-#ifdef CONFIG_DEBUG_FEATURES
- mov $\addr, %dx
- mov $\ch, %al
- out %al, %dx
-#endif
- .endm
-
- .macro trace, ch
-#ifdef CONFIG_DEBUG_FEATURES
- push %eax
- push %edx
- chout 0x3f8, \ch
- pop %edx
- pop %eax
-#endif
- .endm
+ .file "intel64_fullcontextrestore.S"
/**************************************************************************
* Public Functions
**************************************************************************/
- .text
+ .text
/**************************************************************************
* Name: x86_64_fullcontextrestore
@@ -74,84 +42,85 @@
*
**************************************************************************/
- .globl x86_64_fullcontextrestore
- .type x86_64_fullcontextrestore, @function
+ .globl x86_64_fullcontextrestore
+ .type x86_64_fullcontextrestore, @function
x86_64_fullcontextrestore:
- /* The pointer to the register save array in RDI. */
-
- /* Disable interrupts now (the correct RFLAGS will be restored before we
- * return
- */
-
- cli
-
- /* Create an interrupt stack frame for the final iret.
- *
- *
- * IRET STACK
- * ---------------
- * RSP Before ->
- * SS
- * RSP
- * RFLAGS
- * CS
- * RSP After -> RIP
- *
- */
-
- movq (8*REG_SS)(%rdi), %rbx
- push %rbx
- movq (8*REG_RSP)(%rdi), %rbx
- push %rbx
-
- movq (8*REG_RFLAGS)(%rdi), %rbx
- push %rbx
- movq (8*REG_CS)(%rdi), %rbx
- push %rbx
- movq (8*REG_RIP)(%rdi), %rbx
- push %rbx
-
- /* Save the value of RDI on the stack too */
-
- movq (8*REG_RDI)(%rdi), %rbx
- push %rbx
-
- /* Now restore the remaining registers */
- movq (8*REG_RSI)(%rdi), %rsi
- movq (8*REG_RDX)(%rdi), %rdx
- movq (8*REG_RCX)(%rdi), %rcx
- movq (8*REG_R8 )(%rdi), %r8
- movq (8*REG_R9 )(%rdi), %r9
-
- movq (8*REG_R15)(%rdi), %r15
- movq (8*REG_R14)(%rdi), %r14
- movq (8*REG_R13)(%rdi), %r13
- movq (8*REG_R12)(%rdi), %r12
- movq (8*REG_R11)(%rdi), %r11
- movq (8*REG_R10)(%rdi), %r10
- movq (8*REG_RBP)(%rdi), %rbp
- movq (8*REG_RBX)(%rdi), %rbx
- movq (8*REG_RAX)(%rdi), %rax
-
- /* Restore the data segment register. I think there is an issue that will
- * need to be address here at some time: If the register save area is in
- * one data segment and the stack is in another, then the above would not
- * work (and, conversely, if they are in the same data segment, the
- * following is unnecessary and redundant).
- */
-
- mov (8*REG_DS)(%rdi), %ds
- // mov (8*REG_ES)(%rdi), %es // Not used in 64 bit
- // mov (8*REG_GS)(%rdi), %gs // Disabled, otherwise we will destroy MSR_GS_BASE
- // mov (8*REG_FS)(%rdi), %fs // Disabled, otherwise we will destroy MSR_FS_BASE
- // XXX: Should use wrgsbase and wrfsbase to restore the gs and fs register
-
- /* restore xmm registers */
- fxrstorq (%rdi)
-
- /* Restore the correct value of EAX and then return */
-
- popq %rdi
- iretq
- .size x86_64_fullcontextrestore, . - x86_64_fullcontextrestore
- .end
+ /* The pointer to the register save array in RDI. */
+
+ /* Disable interrupts now (the correct RFLAGS will be restored before we
+ * return
+ */
+
+ cli
+
+ /* Create an interrupt stack frame for the final iret.
+ *
+ *
+ * IRET STACK
+ * ---------------
+ * RSP Before ->
+ * SS
+ * RSP
+ * RFLAGS
+ * CS
+ * RSP After -> RIP
+ *
+ */
+
+ movq (8*REG_SS)(%rdi), %rbx
+ push %rbx
+ movq (8*REG_RSP)(%rdi), %rbx
+ push %rbx
+
+ movq (8*REG_RFLAGS)(%rdi), %rbx
+ push %rbx
+ movq (8*REG_CS)(%rdi), %rbx
+ push %rbx
+ movq (8*REG_RIP)(%rdi), %rbx
+ push %rbx
+
+ /* Save the value of RDI on the stack too */
+
+ movq (8*REG_RDI)(%rdi), %rbx
+ push %rbx
+
+ /* Now restore the remaining registers */
+ movq (8*REG_RSI)(%rdi), %rsi
+ movq (8*REG_RDX)(%rdi), %rdx
+ movq (8*REG_RCX)(%rdi), %rcx
+ movq (8*REG_R8 )(%rdi), %r8
+ movq (8*REG_R9 )(%rdi), %r9
+
+ movq (8*REG_R15)(%rdi), %r15
+ movq (8*REG_R14)(%rdi), %r14
+ movq (8*REG_R13)(%rdi), %r13
+ movq (8*REG_R12)(%rdi), %r12
+ movq (8*REG_R11)(%rdi), %r11
+ movq (8*REG_R10)(%rdi), %r10
+ movq (8*REG_RBP)(%rdi), %rbp
+ movq (8*REG_RBX)(%rdi), %rbx
+ movq (8*REG_RAX)(%rdi), %rax
+
+ /* Restore the data segment register. I think there is an issue that will
+ * need to be address here at some time: If the register save area is in
+ * one data segment and the stack is in another, then the above would not
+ * work (and, conversely, if they are in the same data segment, the
+ * following is unnecessary and redundant).
+ */
+
+ mov (8*REG_DS)(%rdi), %ds
+ /* mov (8*REG_ES)(%rdi), %es // Not used in 64 bit
+ * mov (8*REG_GS)(%rdi), %gs // Disabled, otherwise we will destroy MSR_GS_BASE
+ * mov (8*REG_FS)(%rdi), %fs // Disabled, otherwise we will destroy MSR_FS_BASE
+ * XXX: Should use wrgsbase and wrfsbase to restore the gs and fs register
+ */
+
+ /* restore xmm registers */
+ fxrstorq (%rdi)
+
+ /* Restore the correct value of EAX and then return */
+
+ popq %rdi
+ iretq
+ .size x86_64_fullcontextrestore, . - x86_64_fullcontextrestore
+ .end
diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S
index f22b8eb322..62782345ca 100644
--- a/arch/x86_64/src/intel64/intel64_head.S
+++ b/arch/x86_64/src/intel64/intel64_head.S
@@ -26,7 +26,7 @@
#include <arch/arch.h>
#include <arch/multiboot2.h>
- .file "intel64_head.S"
+ .file "intel64_head.S"
/****************************************************************************
* Pre-processor definitions
@@ -40,115 +40,114 @@
* heap continues from there until the end of memory. See g_idle_topstack below.
*/
-/****************************************************************************
- * Macros
- ****************************************************************************/
-
-/* Trace macros, use like trace 'i' to print char to serial port. */
-
- .macro trace, ch
-#ifdef CONFIG_DEBUG_FEATURES
- mov $0x3f8, %dx
- mov $\ch, %al
- out %al, %dx
-#endif
- .endm
-
/****************************************************************************
* Public Symbols
****************************************************************************/
- .global __pmode_entry /* The 32bit protected mode entry */
- .global __nxstart
- .global __enable_sse_avx
- .global __enable_pcid
- .global __revoke_low_memory
- .global nx_start /* nx_start is defined elsewhere */
- .global up_lowsetup /* up_lowsetup is defined elsewhere */
- .global g_idle_topstack /* The end of the idle stack, the start of the heap */
- .global mb_info_struct
- .global mb_magic
-
- /* These are the page tables */
- .global pdpt_low
- .global pd_low
- .global pt_low
-
- /* These are the GDT */
- .global gdt64_low
- .global gdt64_ist_low
- .global gdt64_low_end
-
- .global ist64_low
+
+ .global __pmode_entry /* The 32bit protected mode entry */
+ .global __nxstart
+ .global __enable_sse_avx
+ .global __enable_pcid
+ .global __revoke_low_memory
+ .global nx_start /* nx_start is defined elsewhere */
+ .global up_lowsetup /* up_lowsetup is defined elsewhere */
+ .global g_idle_topstack /* The end of the idle stack, the start of the heap */
+ .global mb_info_struct
+ .global mb_magic
+
+ /* These are the page tables */
+ .global pdpt_low
+ .global pd_low
+ .global pt_low
+
+ /* These are the GDT */
+ .global gdt64_low
+ .global gdt64_ist_low
+ .global gdt64_low_end
+
+ .global ist64_low
/****************************************************************************
* The multiboot2 header
****************************************************************************/
- .set HEADER_LENGTH, header_end - header_start
- .set CHECKSUM, -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + HEADER_LENGTH)
+ .set HEADER_LENGTH, header_end - header_start
+ .set CHECKSUM, -(MULTIBOOT2_HEADER_MAGIC + MULTIBOOT_ARCHITECTURE_I386 + HEADER_LENGTH)
- .section ".multiboot", "a"
- .align 8
+ .section ".multiboot", "a"
+ .align 8
header_start:
#ifdef CONFIG_ARCH_MULTIBOOT2
- .long MULTIBOOT2_HEADER_MAGIC
- .long MULTIBOOT_ARCHITECTURE_I386
- .long HEADER_LENGTH
- .long CHECKSUM
-
- // multiboot tags go here
-
- .short MULTIBOOT_HEADER_TAG_INFORMATION_REQUEST
- .short 0 // flags, none set
- .long 16 // size, including itself (short + short + long)
- .long MULTIBOOT_TAG_TYPE_EFI64
- .long MULTIBOOT_TAG_TYPE_FRAMEBUFFER
-
- .short MULTIBOOT_HEADER_TAG_END
- .short 0 // flags, none set
- .long 8 // size, including itself (short + short + long)
+ .long MULTIBOOT2_HEADER_MAGIC
+ .long MULTIBOOT_ARCHITECTURE_I386
+ .long HEADER_LENGTH
+ .long CHECKSUM
+
+ /* multiboot tags go here */
+
+ .short MULTIBOOT_HEADER_TAG_INFORMATION_REQUEST
+ .short 0 /* flags, none set */
+ .long 16 /* size, including itself (short + short + long) */
+ .long MULTIBOOT_TAG_TYPE_EFI64
+ .long MULTIBOOT_TAG_TYPE_FRAMEBUFFER
+
+ .short MULTIBOOT_HEADER_TAG_END
+ .short 0 /* flags, none set */
+ .long 8 /* size, including itself (short + short + long) */
#endif
header_end:
.code16
.section ".realmode", "ax"
- .type __reset_entry, @function
+/****************************************************************************
+ * Name: __reset_entry
+ *
+ * Description:
+ * Real mode entry point.
+ *
+ ****************************************************************************/
+
+ .type __reset_entry, @function
+
__reset_entry:
- // Load a GDT for protected mode
- movl $loader_gdt_ptr, %ebx
- lgdtl (%ebx)
+ /* Load a GDT for protected mode */
+ movl $loader_gdt_ptr, %ebx
+ lgdtl (%ebx)
- // enable protected mode in CR0
- mov %cr0,%eax
- or $X86_CR0_PE,%al
- mov %eax,%cr0
+ /* enable protected mode in CR0 */
+ mov %cr0, %eax
+ or $X86_CR0_PE, %al
+ mov %eax, %cr0
- // Long jump into protected mode
- // Hardcode the address
- ljmpl $0x8,$0x100000
+ /* Long jump into protected mode. Hardcode the address. */
+ ljmpl $0x8, $0x100000
- // Loader GDT and GDTR
+ /* Loader GDT and GDTR */
.align(16)
.global loader_gdt
loader_gdt:
- .quad 0
- .quad 0x00cf9a000000ffff
- .quad 0x00cf92000000ffff
-
+ .quad 0
+ .quad 0x00cf9a000000ffff
+ .quad 0x00cf92000000ffff
loader_gdt_ptr:
.short loader_gdt_ptr - loader_gdt - 1
- .long loader_gdt
+ .long loader_gdt
- .size __reset_entry, . - __reset_entry
+ .size __reset_entry, . - __reset_entry
/****************************************************************************
* .text
****************************************************************************/
- .code32
- .section ".loader.text", "ax"
+ .code32
+ .section ".loader.text", "ax"
+
+start32_0:
+ mov $0x10, %ax
+ mov %ax, %ss
+ mov %ax, %ds
/****************************************************************************
* Name: __pmode_entry
@@ -159,111 +158,108 @@ loader_gdt_ptr:
*
****************************************************************************/
-start32_0:
- mov $0x10, %ax
- mov %ax, %ss
- mov %ax, %ds
+ .type __pmode_entry, @function
- .type __pmode_entry, @function
__pmode_entry:
start32:
#ifdef CONFIG_ARCH_MULTIBOOT2
- movl %ebx, mb_info_struct
- movl %eax, mb_magic
+ movl %ebx, mb_info_struct
+ movl %eax, mb_magic
#endif
- // initialize rest of the page directory
- lea pd_low, %edi
- lea pt_low, %esi
+ /* initialize rest of the page directory */
+ lea pd_low, %edi
+ lea pt_low, %esi
- // Popluate the lower 4GB as non-present
- // for ecx = 0...512 * 4 : Loop and setup the page directories
- mov $0x800, %ecx // 512 * 4
+ /* Popluate the lower 4GB as non-present
+ * for ecx = 0...512 * 4 : Loop and setup the page directories
+ */
+ mov $0x800, %ecx /* 512 * 4 */
epd_loop:
- mov %esi, %edx
- or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx
- mov %edx, 0(%edi)
- add $(X86_PAGE_ENTRY_SIZE), %edi
+ mov %esi, %edx
+ or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx
+ mov %edx, 0(%edi)
+ add $(X86_PAGE_ENTRY_SIZE), %edi
- // for ebx = 0...1024: Loop and clear the page table of each page directory
- mov $1024, %ebx
+ /* for ebx = 0...1024: Loop and clear the page table of each page directory */
+ mov $1024, %ebx
ept_loop:
- movl $0x0, 0(%esi)
- add $4, %esi
+ movl $0x0, 0(%esi)
+ add $4, %esi
- // end for ebx
- dec %ebx
- jnz ept_loop
+ /* end for ebx */
+ dec %ebx
+ jnz ept_loop
- // end for ecx
- dec %ecx
- jnz epd_loop
+ /* end for ecx */
+ dec %ecx
+ jnz epd_loop
- // Temporary populate the lower 128MB on 1:1 mapping
- lea pd_low, %edi
- mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax
+ /* Temporary populate the lower 128MB on 1:1 mapping */
+ lea pd_low, %edi
+ mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax
- // for ecx = 0...64 : Loop and setup 64x 2MB page directories
- mov $64, %ecx
+ /* for ecx = 0...64 : Loop and setup 64x 2MB page directories */
+ mov $64, %ecx
pd_loop:
- mov %eax, 0(%edi)
- add $(HUGE_PAGE_SIZE), %eax
- add $(X86_PAGE_ENTRY_SIZE), %edi
-
- // end for ecx
- dec %ecx
- jnz pd_loop
-
- // Populate the 1GB after 4GB boundary with Global mapping to kernel code
- // This creates maps the lower 1GB to 4GB~5GB
- lea pdpt_low, %edi
- mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax
-
- mov $0x4, %ecx
- mov %eax, 0(%edi, %ecx, X86_PAGE_ENTRY_SIZE)
-
- // Enable PAE
- mov %cr4, %eax
- or $(X86_CR4_PAE | X86_CR4_PGE), %eax
- mov %eax, %cr4
-
- // Load the 4 level page table
- // Level 1 and 2 were preset at build time in assembly for this loading
- // process
- // 4KiB page table is used
- // Kernel mapped to 1GB HiMem
- lea pml4, %eax
- mov %eax, %cr3
-
- movl $MSR_MTRR_DEF_TYPE, %ecx
- rdmsr
- or $MTRR_ENABLE, %eax
- wrmsr
-
- movl $MSR_EFER, %ecx
- rdmsr
- or $EFER_LME, %eax
- wrmsr
-
- // Enable paging related bits in CR0
- mov $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax
- mov %eax, %cr0
-
- // Enable FGSBASE
- mov %cr4, %eax
- or $X86_CR4_FGSBASE, %eax
- mov %eax, %cr4
-
- // Load a GDT with 64bits mode set
- lgdt gdt64_ptr
-
- // Long jump into 64 bit mode, updating cs to new GDT
- ljmpl $(X86_GDT_CODE_SEL), $start64
-
- .code64
+ mov %eax, 0(%edi)
+ add $(HUGE_PAGE_SIZE), %eax
+ add $(X86_PAGE_ENTRY_SIZE), %edi
+
+ /* end for ecx */
+ dec %ecx
+ jnz pd_loop
+
+ /* Populate the 1GB after 4GB boundary with Global mapping to kernel code.
+ * This creates maps the lower 1GB to 4GB~5GB
+ */
+ lea pdpt_low, %edi
+ mov $(X86_PAGE_GLOBAL | X86_PAGE_WR | X86_PAGE_PRESENT | X86_PAGE_HUGE), %eax
+
+ mov $0x4, %ecx
+ mov %eax, 0(%edi, %ecx, X86_PAGE_ENTRY_SIZE)
+
+ /* Enable PAE */
+ mov %cr4, %eax
+ or $(X86_CR4_PAE | X86_CR4_PGE), %eax
+ mov %eax, %cr4
+
+ /* Load the 4 level page table.
+ * Level 1 and 2 were preset at build time in assembly for this loading process.
+ * 4KiB page table is used.
+ * Kernel mapped to 1GB HiMem
+ */
+ lea pml4, %eax
+ mov %eax, %cr3
+
+ movl $MSR_MTRR_DEF_TYPE, %ecx
+ rdmsr
+ or $MTRR_ENABLE, %eax
+ wrmsr
+
+ movl $MSR_EFER, %ecx
+ rdmsr
+ or $EFER_LME, %eax
+ wrmsr
+
+ /* Enable paging related bits in CR0 */
+ mov $(X86_CR0_PG | X86_CR0_WP | X86_CR0_PE), %eax
+ mov %eax, %cr0
+
+ /* Enable FGSBASE */
+ mov %cr4, %eax
+ or $X86_CR4_FGSBASE, %eax
+ mov %eax, %cr4
+
+ /* Load a GDT with 64bits mode set */
+ lgdt gdt64_ptr
+
+ /* Long jump into 64 bit mode, updating cs to new GDT */
+ ljmpl $(X86_GDT_CODE_SEL), $start64
+
+ .code64
start64:
-
- // Set Segement Registers for proper iret, etc. operation
+ /* Set Segement Registers for proper iret, etc. operation */
mov $(X86_GDT_DATA_SEL), %ax
mov %ax, %ss
mov %ax, %ds
@@ -271,7 +267,7 @@ start64:
mov %ax, %fs
mov %ax, %gs
- // Finally, we can start the OS
+ /* Finally, we can start the OS */
movabs $__nxstart, %rbx
jmp *%rbx
.size __pmode_entry, . - __pmode_entry
@@ -288,9 +284,11 @@ start64:
.type __nxstart, @function
__nxstart:
- /* We are now in high memory, will revoke the lower 128MB memory mapping in lowsetup*/
+ /* We are now in high memory, will revoke the lower 128MB memory mapping
+ * in lowsetup
+ */
- //clear out bss section
+ /* clear out bss section */
movabs $_sbss, %rbx
movabs $_ebss, %rdx
clear_bss:
@@ -299,7 +297,7 @@ clear_bss:
cmp %rbx, %rdx
jne clear_bss
- // Properly setup RSP to idle stack
+ /* Properly setup RSP to idle stack */
movabs $g_idle_topstack, %rbx
mov (%rbx), %rsp
@@ -318,29 +316,37 @@ hang:
jmp hang
.size __nxstart, . - __nxstart
- .type __revoke_low_memory, @function
-__revoke_low_memory:
+/****************************************************************************
+ * Name: __revoke_low_memory
+ *
+ * Description:
+ * Revoke the lower 128MB memory mapping
+ *
+ ****************************************************************************/
- /* Revoke the lower 128MB memory mapping */
- lea pd_low, %edi
- lea pt_low, %esi
+ .type __revoke_low_memory, @function
+
+__revoke_low_memory:
+ /* Revoke the lower 128MB memory mapping */
+ lea pd_low, %edi
+ lea pt_low, %esi
- // for ecx = 0...64 : Loop and setup 64x 2MB page directories
- mov $64, %ecx
+ /* for ecx = 0...64 : Loop and setup 64x 2MB page directories */
+ mov $64, %ecx
npd_loop:
- mov %esi, %edx
- or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx
- mov %edx, 0(%edi)
- add $(PAGE_SIZE), %esi
- add $(X86_PAGE_ENTRY_SIZE), %edi
+ mov %esi, %edx
+ or $(X86_PAGE_WR | X86_PAGE_PRESENT), %edx
+ mov %edx, 0(%edi)
+ add $(PAGE_SIZE), %esi
+ add $(X86_PAGE_ENTRY_SIZE), %edi
- // end for ecx
- dec %ecx
- jnz npd_loop
+ /* end for ecx */
+ dec %ecx
+ jnz npd_loop
- ret
+ ret
- .size __revoke_low_memory, . - __revoke_low_memory
+ .size __revoke_low_memory, . - __revoke_low_memory
/****************************************************************************
* Name: __enable_sse_avx
@@ -350,28 +356,28 @@ npd_loop:
*
****************************************************************************/
- .type __enable_sse_avx, @function
+ .type __enable_sse_avx, @function
__enable_sse_avx:
- // Enable SSE
- mov %cr0, %rax
- mov $(X86_CR0_EM), %rbx
- not %rbx
- and %rbx, %rax
- or $(X86_CR0_MP), %rax
- mov %rax, %cr0
+ /* Enable SSE */
+ mov %cr0, %rax
+ mov $(X86_CR0_EM), %rbx
+ not %rbx
+ and %rbx, %rax
+ or $(X86_CR0_MP), %rax
+ mov %rax, %cr0
- // Enable Saving XMM context
- mov %cr4, %rax
- or $(X86_CR4_OSXFSR | X86_CR4_XMMEXCPT), %rax
- mov %rax, %cr4
+ /* Enable Saving XMM context */
+ mov %cr4, %rax
+ or $(X86_CR4_OSXFSR | X86_CR4_XMMEXCPT), %rax
+ mov %rax, %cr4
- // Setup MXCSR, masking all SSE precision exception
- ldmxcsr mxcsr_mem
+ /* Setup MXCSR, masking all SSE precision exception */
+ ldmxcsr mxcsr_mem
- ret
+ ret
- .size __enable_sse_avx, . - __enable_sse_avx
+ .size __enable_sse_avx, . - __enable_sse_avx
/****************************************************************************
* Name: __enable_pcid
@@ -381,97 +387,95 @@ __enable_sse_avx:
*
****************************************************************************/
- .type __enable_pcid, @function
+ .type __enable_pcid, @function
__enable_pcid:
- // Enable PCID and FGSBASE
- mov %cr4, %rax
- or $X86_CR4_PCIDE, %rax
- mov %rax, %cr4
+ /* Enable PCID and FGSBASE */
+ mov %cr4, %rax
+ or $X86_CR4_PCIDE, %rax
+ mov %rax, %cr4
- ret
+ ret
- .size __enable_pcid, . - __enable_pcid
+ .size __enable_pcid, . - __enable_pcid
/****************************************************************************
* .data
****************************************************************************/
- .section ".loader.data", "ax"
+ .section ".loader.data", "ax"
- // IST for 64 bit long mode
- // will be filled in up_irq
- .align(16)
+ /* IST for 64 bit long mode will be filled in up_irq */
+ .align(16)
ist64_low:
- .long 0
- .quad 0xdeadbeefdeadbee0
- .quad 0xdeadbeefdeadbee1
- .quad 0xdeadbeefdeadbee2
- .quad 0
- .quad 0
- .quad 0
- .quad 0
- .quad 0
- .quad 0
- .quad 0
- .quad 0
- .quad 0
- .word 0
-
- // GDT for 64 bit long mode
- .align(16)
+ .long 0
+ .quad 0xdeadbeefdeadbee0
+ .quad 0xdeadbeefdeadbee1
+ .quad 0xdeadbeefdeadbee2
+ .quad 0
+ .quad 0
+ .quad 0
+ .quad 0
+ .quad 0
+ .quad 0
+ .quad 0
+ .quad 0
+ .quad 0
+ .word 0
+
+ /* GDT for 64 bit long mode */
+ .align(16)
gdt64_low:
- .quad 0
- .quad X86_GDT_CODE64_ENTRY
- .quad X86_GDT_DATA_ENTRY
- .quad X86_GDT_CODE32_ENTRY
- .quad X86_GDT_DATA_ENTRY
- .quad X86_GDT_CODE64_ENTRY
+ .quad 0
+ .quad X86_GDT_CODE64_ENTRY
+ .quad X86_GDT_DATA_ENTRY
+ .quad X86_GDT_CODE32_ENTRY
+ .quad X86_GDT_DATA_ENTRY
+ .quad X86_GDT_CODE64_ENTRY
gdt64_ist_low:
- .quad 0x0 // TSS segment low
- .quad 0x0 // TSS segment high
+ .quad 0x0 /* TSS segment low */
+ .quad 0x0 /* TSS segment high */
gdt64_low_end:
gdt64_ptr:
- .short gdt64_low_end - gdt64_low - 1
- .long gdt64_low
+ .short gdt64_low_end - gdt64_low - 1
+ .long gdt64_low
mxcsr_mem:
- .long 0x00001f80
+ .long 0x00001f80
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pml4:
- .quad pdpt_low + X86_PAGE_PRESENT + X86_PAGE_WR
+ .quad pdpt_low + X86_PAGE_PRESENT + X86_PAGE_WR
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pdpt_low:
- .quad pd_low + X86_PAGE_PRESENT + X86_PAGE_WR
- .quad pd_2_low + X86_PAGE_PRESENT + X86_PAGE_WR
- .quad pd_3_low + X86_PAGE_PRESENT + X86_PAGE_WR
- .quad pd_4_low + X86_PAGE_PRESENT + X86_PAGE_WR
+ .quad pd_low + X86_PAGE_PRESENT + X86_PAGE_WR
+ .quad pd_2_low + X86_PAGE_PRESENT + X86_PAGE_WR
+ .quad pd_3_low + X86_PAGE_PRESENT + X86_PAGE_WR
+ .quad pd_4_low + X86_PAGE_PRESENT + X86_PAGE_WR
- .fill X86_NUM_PAGE_ENTRY - 4, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY - 4, X86_PAGE_ENTRY_SIZE, 0
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pd_low:
- .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pd_2_low:
- .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pd_3_low:
- .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pd_4_low:
- .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .align(PAGE_SIZE)
+ .align(PAGE_SIZE)
pt_low:
- .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
- .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
-
+ .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
+ .fill X86_NUM_PAGE_ENTRY * X86_NUM_PAGE_ENTRY, X86_PAGE_ENTRY_SIZE, 0
diff --git a/arch/x86_64/src/intel64/intel64_saveusercontext.S b/arch/x86_64/src/intel64/intel64_saveusercontext.S
index 17d2d2733f..1c5a14a9f5 100644
--- a/arch/x86_64/src/intel64/intel64_saveusercontext.S
+++ b/arch/x86_64/src/intel64/intel64_saveusercontext.S
@@ -26,42 +26,15 @@
#include <arch/irq.h>
#include "x86_64_internal.h"
- .file "intel64_saveusercontext.S"
-
-/**************************************************************************
- * Pre-processor Definitions
- **************************************************************************/
-
-/****************************************************************************
- * Macros
- ****************************************************************************/
-
-/* Trace macros, use like trace 'i' to print char to serial port. */
-
- .macro chout, addr, ch
-#ifdef CONFIG_DEBUG_FEATURES
- mov $\addr, %dx
- mov $\ch, %al
- out %al, %dx
-#endif
- .endm
-
- .macro trace, ch
-#ifdef CONFIG_DEBUG_FEATURES
- push %eax
- push %edx
- chout 0x3f8, \ch
- pop %edx
- pop %eax
-#endif
- .endm
+ .file "intel64_saveusercontext.S"
/**************************************************************************
* .text
**************************************************************************/
- .text
-.code64
+ .text
+ .code64
+
/**************************************************************************
* Name: up_saveusercontext
*
@@ -84,66 +57,66 @@
*
**************************************************************************/
- .globl up_saveusercontext
- .type up_saveusercontext, @function
+ .globl up_saveusercontext
+ .type up_saveusercontext, @function
up_saveusercontext:
- // callee saved regs
- movq %rbx, (8*REG_RBX)(%rdi)
- movq %r12, (8*REG_R12)(%rdi)
- movq %r13, (8*REG_R13)(%rdi)
- movq %r14, (8*REG_R14)(%rdi)
- movq %r15, (8*REG_R15)(%rdi)
-
- // save xmm registers
- fxsaveq (%rdi)
-
- /* Save the value of SP as will be at the time of the IRET that will
- * appear to be the return from this function.
- *
- * CURRENT STACK IRET STACK
- * ------------------------------ -----------------
- * RIP
- * CS
- * RFLAGS
- * RSP
- * ESP->Return address SS
- * Argument Alignment (16bytes)
- *
- */
-
- leaq 8(%rsp), %rcx
- movq %rcx, (8*REG_RSP)(%rdi)
-
- /* Fetch the PC from the stack and save it in the save block */
-
- movq 0(%rsp), %rcx
- movq %rcx, (8*REG_RIP)(%rdi)
-
- /* Save the framepointer */
-
- movq %rbp, (8*REG_RBP)(%rdi)
-
- /* Save EAX=1. This will be the "apparent" return value from this
- * function when context is switch back to this thread. The non-zero
- * return value is the indication that we have been resumed.
- */
-
- movq $1, (8*REG_RAX)(%rdi)
-
- /* Get and save the interrupt state */
-
- pushf
- pop %rcx
- movq %rcx, (8*REG_RFLAGS)(%rdi)
-
- /* And return 0 -- The zero return value is the indication that that
- * this is the original, "true" return from the function.
- *
- * 'ret' will remove the RIP from the top of the stack.
- */
-
- xor %rax, %rax
- ret
- .size up_saveusercontext, . - up_saveusercontext
- .end
+ /* callee saved regs */
+ movq %rbx, (8*REG_RBX)(%rdi)
+ movq %r12, (8*REG_R12)(%rdi)
+ movq %r13, (8*REG_R13)(%rdi)
+ movq %r14, (8*REG_R14)(%rdi)
+ movq %r15, (8*REG_R15)(%rdi)
+
+ /* save xmm registers */
+ fxsaveq (%rdi)
+
+ /* Save the value of SP as will be at the time of the IRET that will
+ * appear to be the return from this function.
+ *
+ * CURRENT STACK IRET STACK
+ * ------------------------------ -----------------
+ * RIP
+ * CS
+ * RFLAGS
+ * RSP
+ * ESP->Return address SS
+ * Argument Alignment (16bytes)
+ *
+ */
+
+ leaq 8(%rsp), %rcx
+ movq %rcx, (8*REG_RSP)(%rdi)
+
+ /* Fetch the PC from the stack and save it in the save block */
+
+ movq 0(%rsp), %rcx
+ movq %rcx, (8*REG_RIP)(%rdi)
+
+ /* Save the framepointer */
+
+ movq %rbp, (8*REG_RBP)(%rdi)
+
+ /* Save EAX=1. This will be the "apparent" return value from this
+ * function when context is switch back to this thread. The non-zero
+ * return value is the indication that we have been resumed.
+ */
+
+ movq $1, (8*REG_RAX)(%rdi)
+
+ /* Get and save the interrupt state */
+
+ pushf
+ pop %rcx
+ movq %rcx, (8*REG_RFLAGS)(%rdi)
+
+ /* And return 0 -- The zero return value is the indication that that
+ * this is the original, "true" return from the function.
+ *
+ * 'ret' will remove the RIP from the top of the stack.
+ */
+
+ xor %rax, %rax
+ ret
+ .size up_saveusercontext, . - up_saveusercontext
+ .end
diff --git a/arch/x86_64/src/intel64/intel64_vectors.S b/arch/x86_64/src/intel64/intel64_vectors.S
index efcf6dd783..f88658b8f4 100644
--- a/arch/x86_64/src/intel64/intel64_vectors.S
+++ b/arch/x86_64/src/intel64/intel64_vectors.S
@@ -25,200 +25,188 @@
#include <nuttx/config.h>
#include <arch/irq.h>
- .file "broadwell_vectors.S"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
+ .file "intel64_vectors.S"
/****************************************************************************
* .text
****************************************************************************/
.text
- .code64
+ .code64
/****************************************************************************
* Public Symbols
****************************************************************************/
- .globl irq_handler
- .globl isr_handler
- .globl g_interrupt_stack
- .globl g_interrupt_stack_end
- .globl g_isr_stack
- .globl g_isr_stack_end
+ .globl irq_handler
+ .globl isr_handler
+ .globl g_interrupt_stack
+ .globl g_interrupt_stack_end
+ .globl g_isr_stack
+ .globl g_isr_stack_end
/****************************************************************************
* Macros
****************************************************************************/
-/* Trace macros, use like trace 'i' to print char to serial port. */
-
- .macro trace, ch
- mov $0x3f8, %dx
- mov $\ch, %al
- out %al, %dx
- .endm
-
-/* This macro creates a stub for an ISR which does NOT pass it's own
- * error code (adds a dummy errcode byte).
- */
+ /* This macro creates a stub for an ISR which does NOT pass it's own
+ * error code (adds a dummy errcode byte).
+ */
.macro ISR_NOERRCODE, intno
- .globl vector_isr\intno
+ .globl vector_isr\intno
vector_isr\intno:
- cli /* Disable interrupts firstly. */
+ cli /* Disable interrupts firstly. */
- // CPU has sawitched to the ISR stack using IST
+ /* CPU has sawitched to the ISR stack using IST */
- pushq $0 /* Push a dummy error code. */
+ pushq $0 /* Push a dummy error code. */
- // Save rdi, rsi
- pushq %rdi
- pushq %rsi
- movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
- jmp isr_common /* Go to the common ISR handler code. */
+ /* Save rdi, rsi */
+ pushq %rdi
+ pushq %rsi
+ movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
+ jmp isr_common /* Go to the common ISR handler code. */
.endm
-/* This macro creates a stub for an ISR which passes it's own
- * error code.
- */
+ /* This macro creates a stub for an ISR which passes it's own
+ * error code.
+ */
- .macro ISR_ERRCODE, intno
- .globl vector_isr\intno
+ .macro ISR_ERRCODE, intno
+ .globl vector_isr\intno
vector_isr\intno:
- cli /* Disable interrupts firstly. */
+ cli /* Disable interrupts firstly. */
- // CPU has sawitched to the ISR stack using IST
+ /* CPU has sawitched to the ISR stack using IST */
- // Save rdi, rsi
- pushq %rdi
- pushq %rsi
- movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
- jmp isr_common /* Go to the common ISR handler code. */
+ /* Save rdi, rsi */
+ pushq %rdi
+ pushq %rsi
+ movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
+ jmp isr_common /* Go to the common ISR handler code. */
.endm
-/* This macro creates a stub for an IRQ - the first parameter is
- * the IRQ number, the second is the ISR number it is remapped to.
- */
+ /* This macro creates a stub for an IRQ - the first parameter is
+ * the IRQ number, the second is the ISR number it is remapped to.
+ */
- .macro IRQ, irqno, intno
- .globl vector_irq\irqno
-vector_irq\irqno:
- cli /* Disable interrupts firstly. */
+ .macro IRQ, irqno, intno
+ .globl vector_irq\irqno
+ vector_irq\irqno:
+ cli /* Disable interrupts firstly. */
- // CPU has switched to the IRQ stack using IST
+ /* CPU has switched to the IRQ stack using IST */
- pushq $0 /* Push a dummy error code. */
+ pushq $0 /* Push a dummy error code. */
- // Save rdi, rsi
- pushq %rdi
- pushq %rsi
- movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
- jmp irq_common /* Go to the common IRQ handler code. */
+ /* Save rdi, rsi */
+ pushq %rdi
+ pushq %rsi
+ movq $\intno, %rsi /* INT Number is saved to 2nd parameter of function call */
+ jmp irq_common /* Go to the common IRQ handler code. */
.endm
/****************************************************************************
* IDT Vectors
****************************************************************************/
-/* The following will be the vector addresses programmed into the IDT */
+ /* The following will be the vector addresses programmed into the IDT */
- ISR_NOERRCODE ISR0
+ ISR_NOERRCODE ISR0
.balign 16
- ISR_NOERRCODE ISR1
+ ISR_NOERRCODE ISR1
.balign 16
- ISR_NOERRCODE ISR2
+ ISR_NOERRCODE ISR2
.balign 16
- ISR_NOERRCODE ISR3
+ ISR_NOERRCODE ISR3
.balign 16
- ISR_NOERRCODE ISR4
+ ISR_NOERRCODE ISR4
.balign 16
- ISR_NOERRCODE ISR5
+ ISR_NOERRCODE ISR5
.balign 16
- ISR_NOERRCODE ISR6
+ ISR_NOERRCODE ISR6
.balign 16
- ISR_NOERRCODE ISR7
+ ISR_NOERRCODE ISR7
.balign 16
- ISR_ERRCODE ISR8
+ ISR_ERRCODE ISR8
.balign 16
- ISR_NOERRCODE ISR9
+ ISR_NOERRCODE ISR9
.balign 16
- ISR_ERRCODE ISR10
+ ISR_ERRCODE ISR10
.balign 16
- ISR_ERRCODE ISR11
+ ISR_ERRCODE ISR11
.balign 16
- ISR_ERRCODE ISR12
+ ISR_ERRCODE ISR12
.balign 16
- ISR_ERRCODE ISR13
+ ISR_ERRCODE ISR13
.balign 16
- ISR_ERRCODE ISR14
+ ISR_ERRCODE ISR14
.balign 16
- ISR_NOERRCODE ISR15
+ ISR_NOERRCODE ISR15
.balign 16
- ISR_NOERRCODE ISR16
+ ISR_NOERRCODE ISR16
.balign 16
- ISR_NOERRCODE ISR17
+ ISR_NOERRCODE ISR17
.balign 16
- ISR_NOERRCODE ISR18
+ ISR_NOERRCODE ISR18
.balign 16
- ISR_NOERRCODE ISR19
+ ISR_NOERRCODE ISR19
.balign 16
- ISR_NOERRCODE ISR20
+ ISR_NOERRCODE ISR20
.balign 16
- ISR_NOERRCODE ISR21
+ ISR_NOERRCODE ISR21
.balign 16
- ISR_NOERRCODE ISR22
+ ISR_NOERRCODE ISR22
.balign 16
- ISR_NOERRCODE ISR23
+ ISR_NOERRCODE ISR23
.balign 16
- ISR_NOERRCODE ISR24
+ ISR_NOERRCODE ISR24
.balign 16
- ISR_NOERRCODE ISR25
+ ISR_NOERRCODE ISR25
.balign 16
- ISR_NOERRCODE ISR26
+ ISR_NOERRCODE ISR26
.balign 16
- ISR_NOERRCODE ISR27
+ ISR_NOERRCODE ISR27
.balign 16
- ISR_NOERRCODE ISR28
+ ISR_NOERRCODE ISR28
.balign 16
- ISR_NOERRCODE ISR29
+ ISR_NOERRCODE ISR29
.balign 16
- ISR_NOERRCODE ISR30
+ ISR_NOERRCODE ISR30
.balign 16
- ISR_NOERRCODE ISR31
+ ISR_NOERRCODE ISR31
.balign 16
- IRQ 0, IRQ0
+ IRQ 0, IRQ0
.balign 16
- IRQ 1, IRQ1
+ IRQ 1, IRQ1
.balign 16
- IRQ 2, IRQ2
+ IRQ 2, IRQ2
.balign 16
- IRQ 3, IRQ3
+ IRQ 3, IRQ3
.balign 16
- IRQ 4, IRQ4
+ IRQ 4, IRQ4
.balign 16
- IRQ 5, IRQ5
+ IRQ 5, IRQ5
.balign 16
- IRQ 6, IRQ6
+ IRQ 6, IRQ6
.balign 16
- IRQ 7, IRQ7
+ IRQ 7, IRQ7
.balign 16
- IRQ 8, IRQ8
+ IRQ 8, IRQ8
.balign 16
- IRQ 9, IRQ9
+ IRQ 9, IRQ9
.balign 16
- IRQ 10, IRQ10
+ IRQ 10, IRQ10
.balign 16
- IRQ 11, IRQ11
+ IRQ 11, IRQ11
.balign 16
- IRQ 12, IRQ12
+ IRQ 12, IRQ12
.balign 16
- IRQ 13, IRQ13
+ IRQ 13, IRQ13
.balign 16
- IRQ 14, IRQ14
+ IRQ 14, IRQ14
.balign 16
- IRQ 15, IRQ15
+ IRQ 15, IRQ15
.balign 16
/****************************************************************************
@@ -232,51 +220,50 @@ vector_irq\irqno:
****************************************************************************/
isr_common:
-/* trace 'S' */
- /* Already swap to the interrupt stack */
- /* stack is automatically recovered by iretq using task state */
-
- /* x86_64 don't have pusha, we have to do things manually */
- /* RDI and RSI are pushed above for handling IRQ no */
- pushq %rdx
- pushq %rcx
- pushq %r8
- pushq %r9
-
- pushq %r15
- pushq %r14
- pushq %r13
- pushq %r12
- pushq %r11
- pushq %r10
- pushq %rbp
- pushq %rbx
- pushq %rax
-
- mov %ds, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
- mov %es, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
- mov %gs, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
- mov %fs, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
-
- /* align to 16-bytes boundary */
- leaq -8(%rsp), %rsp
-
- /* save xmm registers */
- leaq -512(%rsp), %rsp
- fxsaveq (%rsp)
+ /* Already swap to the interrupt stack */
+ /* stack is automatically recovered by iretq using task state */
+
+ /* x86_64 don't have pusha, we have to do things manually */
+ /* RDI and RSI are pushed above for handling IRQ no */
+ pushq %rdx
+ pushq %rcx
+ pushq %r8
+ pushq %r9
+
+ pushq %r15
+ pushq %r14
+ pushq %r13
+ pushq %r12
+ pushq %r11
+ pushq %r10
+ pushq %rbp
+ pushq %rbx
+ pushq %rax
+
+ mov %ds, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+ mov %es, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+ mov %gs, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+ mov %fs, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+
+ /* align to 16-bytes boundary */
+ leaq -8(%rsp), %rsp
+
+ /* save xmm registers */
+ leaq -512(%rsp), %rsp
+ fxsaveq (%rsp)
/* The current value of the SP points to the beginning of the state save
* structure. Save that in RDI as the input parameter to isr_handler.
*/
- mov %rsp, %rdi
- call isr_handler
- jmp .Lreturn
- .size isr_common, . - isr_common
+ mov %rsp, %rdi
+ call isr_handler
+ jmp .Lreturn
+ .size isr_common, . - isr_common
/****************************************************************************
* Name: irq_common
@@ -288,51 +275,50 @@ isr_common:
*
****************************************************************************/
- .type irq_common, @function
+ .type irq_common, @function
irq_common:
-/* trace 'R' */
- /* Already swap to the interrupt stack */
- /* stack is automatically recovered by iretq using task state */
-
- /* x86_64 don't have pusha, we have to do things manually */
- /* RDI and RSI are pushed above for handling IRQ no */
- pushq %rdx
- pushq %rcx
- pushq %r8
- pushq %r9
-
- pushq %r15
- pushq %r14
- pushq %r13
- pushq %r12
- pushq %r11
- pushq %r10
- pushq %rbp
- pushq %rbx
- pushq %rax
-
- mov %ds, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
- mov %es, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
- mov %gs, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
- mov %fs, %ax /* Lower 16-bits of rax. */
- pushq %rax /* Save the data segment descriptor */
-
- /* align to 16-bytes boundary */
- leaq -8(%rsp), %rsp
-
- /* save xmm registers */
- leaq -512(%rsp), %rsp
- fxsaveq (%rsp)
+ /* Already swap to the interrupt stack */
+ /* stack is automatically recovered by iretq using task state */
+
+ /* x86_64 don't have pusha, we have to do things manually */
+ /* RDI and RSI are pushed above for handling IRQ no */
+ pushq %rdx
+ pushq %rcx
+ pushq %r8
+ pushq %r9
+
+ pushq %r15
+ pushq %r14
+ pushq %r13
+ pushq %r12
+ pushq %r11
+ pushq %r10
+ pushq %rbp
+ pushq %rbx
+ pushq %rax
+
+ mov %ds, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+ mov %es, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+ mov %gs, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+ mov %fs, %ax /* Lower 16-bits of rax. */
+ pushq %rax /* Save the data segment descriptor */
+
+ /* align to 16-bytes boundary */
+ leaq -8(%rsp), %rsp
+
+ /* save xmm registers */
+ leaq -512(%rsp), %rsp
+ fxsaveq (%rsp)
/* The current value of the SP points to the beginning of the state save
* structure. Save that in RDI as the input parameter to irq_handler.
*/
- mov %rsp, %rdi
- call irq_handler
+ mov %rsp, %rdi
+ call irq_handler
/* The common return point for both isr_handler and irq_handler */
@@ -341,55 +327,55 @@ irq_common:
* return. Are we switching to a new context?
*/
- cmp %rax, %rsp
- je .Lnoswitch
+ cmp %rax, %rsp
+ je .Lnoswitch
/* A context swith will be performed. EAX holds the address of the new
- * register save structure.
+ * register save structure.
*
* Jump to x86_64_fullcontextrestore(). We perform a call here, but that function
* never returns. The address of the new register save block is the argument
* to the x86_64_fullcontextrestore().
- */
+ */
mov %rax, %rdi
- call x86_64_fullcontextrestore
+ call x86_64_fullcontextrestore
.Lnoswitch:
- fxrstorq (%rsp)
- leaq 512(%rsp), %rsp
- leaq 8(%rsp), %rsp
-
- popq %rax
- mov %fs, %ax
- popq %rax
- mov %gs, %ax
- popq %rax
- mov %es, %ax
- popq %rax
- mov %ds, %ax
-
- popq %rax
- popq %rbx
- popq %rbp
- popq %r10
- popq %r11
- popq %r12
- popq %r13
- popq %r14
- popq %r15
-
- popq %r9
- popq %r8
- popq %rcx
- popq %rdx
-
- popq %rsi
- popq %rdi
-
- add $8, %rsp /* Cleans up the pushed error code */
-
- iretq /* Pops 5 things at once: CS, RIP, RFLAGS and SS and RSP */
+ fxrstorq (%rsp)
+ leaq 512(%rsp), %rsp
+ leaq 8(%rsp), %rsp
+
+ popq %rax
+ mov %fs, %ax
+ popq %rax
+ mov %gs, %ax
+ popq %rax
+ mov %es, %ax
+ popq %rax
+ mov %ds, %ax
+
+ popq %rax
+ popq %rbx
+ popq %rbp
+ popq %r10
+ popq %r11
+ popq %r12
+ popq %r13
+ popq %r14
+ popq %r15
+
+ popq %r9
+ popq %r8
+ popq %rcx
+ popq %rdx
+
+ popq %rsi
+ popq %rdi
+
+ add $8, %rsp /* Cleans up the pushed error code */
+
+ iretq /* Pops 5 things at once: CS, RIP, RFLAGS and SS and RSP */
.size irq_common, . - irq_common
.end
(nuttx) 03/04: arch/intel64: clear BSS in __nxstart
Posted by xi...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
xiaoxiang pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/nuttx.git
commit 8a43bf1b50f90b8eedbf732bfbb7b708b0e4d893
Author: p-szafonimateusz <p-...@xiaomi.com>
AuthorDate: Tue Feb 20 14:45:34 2024 +0100
arch/intel64: clear BSS in __nxstart
BSS nulling can now be optimized by the compiler, so it is necessary
to enable SSE instructions early in __nxstart
Signed-off-by: p-szafonimateusz <p-...@xiaomi.com>
---
arch/x86_64/src/intel64/intel64_head.S | 9 ---------
arch/x86_64/src/intel64/intel64_lowsetup.c | 4 ----
arch/x86_64/src/intel64/intel64_start.c | 18 ++++++++++++++++++
3 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/x86_64/src/intel64/intel64_head.S b/arch/x86_64/src/intel64/intel64_head.S
index e462bdc279..51b0bda484 100644
--- a/arch/x86_64/src/intel64/intel64_head.S
+++ b/arch/x86_64/src/intel64/intel64_head.S
@@ -266,15 +266,6 @@ start64:
mov %ax, %fs
mov %ax, %gs
- /* Clear out bss section */
- movabs $_sbss, %rbx
- movabs $_ebss, %rdx
-clear_bss:
- movb $0, (%rbx)
- inc %rbx
- cmp %rbx, %rdx
- jne clear_bss
-
/* Properly setup RSP to idle stack */
movabs $g_idle_topstack, %rbx
mov (%rbx), %rsp
diff --git a/arch/x86_64/src/intel64/intel64_lowsetup.c b/arch/x86_64/src/intel64/intel64_lowsetup.c
index 9718afd845..e437644083 100644
--- a/arch/x86_64/src/intel64/intel64_lowsetup.c
+++ b/arch/x86_64/src/intel64/intel64_lowsetup.c
@@ -89,10 +89,6 @@ void intel64_lowsetup(void)
setgdt((void *)gdt64, (uintptr_t)(&gdt64_low_end - &gdt64_low) - 1);
- /* Do some checking on CPU compatibilities */
-
- x86_64_check_and_enable_capability();
-
/* Revoke the lower memory */
__revoke_low_memory();
diff --git a/arch/x86_64/src/intel64/intel64_start.c b/arch/x86_64/src/intel64/intel64_start.c
index 89e3e9960b..9a37998e2b 100644
--- a/arch/x86_64/src/intel64/intel64_start.c
+++ b/arch/x86_64/src/intel64/intel64_start.c
@@ -107,6 +107,24 @@ static void x86_64_mb2_config(void)
void __nxstart(void)
{
+ uint64_t *dest = NULL;
+
+ /* Do some checking on CPU compatibilities at the top of this function.
+ * BSS cleanup can be optimized with vector instructions, so we need to
+ * enable SSE at this point.
+ */
+
+ x86_64_check_and_enable_capability();
+
+ /* Clear .bss. The compiler can optimize this with vector instructions,
+ * so this *must be* called after enabling SSE instructions.
+ */
+
+ for (dest = (uint64_t *)_sbss; dest < (uint64_t *)_ebss; )
+ {
+ *dest++ = 0;
+ }
+
/* Low-level, pre-OS initialization */
intel64_lowsetup();