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Posted to commits@mynewt.apache.org by ma...@apache.org on 2017/03/10 19:51:09 UTC
[04/52] [partial] incubator-mynewt-core git commit: Add support for
STM32F7xx and NUCLEO-F767
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h
new file mode 100644
index 0000000..071b033
--- /dev/null
+++ b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mdios.h
@@ -0,0 +1,537 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_mdios.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 30-December-2016
+ * @brief Header file of MDIOS HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_MDIOS_H
+#define __STM32F7xx_HAL_MDIOS_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+#if defined (MDIOS)
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MDIOS
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
+ * @{
+ */
+
+/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
+ * @{
+ */
+
+typedef enum
+{
+ HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
+ HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
+ HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
+ HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
+}HAL_MDIOS_StateTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
+ * @{
+ */
+
+typedef struct
+{
+ uint32_t PortAddress; /*!< Specifies the MDIOS port address.
+ This parameter can be a value from 0 to 31 */
+ uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
+ This parameter can be a value of @ref MDIOS_Preamble_Check */
+}MDIOS_InitTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
+ * @{
+ */
+
+typedef struct
+{
+ MDIOS_TypeDef *Instance; /*!< Register base address */
+
+ MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */
+
+ __IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
+
+ HAL_LockTypeDef Lock; /*!< MDIOS Lock */
+}MDIOS_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
+ * @{
+ */
+
+/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check
+ * @{
+ */
+#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
+#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
+/**
+ * @}
+ */
+
+/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
+ * @{
+ */
+#define MDIOS_REG0 ((uint32_t)0x00000000U)
+#define MDIOS_REG1 ((uint32_t)0x00000001U)
+#define MDIOS_REG2 ((uint32_t)0x00000002U)
+#define MDIOS_REG3 ((uint32_t)0x00000003U)
+#define MDIOS_REG4 ((uint32_t)0x00000004U)
+#define MDIOS_REG5 ((uint32_t)0x00000005U)
+#define MDIOS_REG6 ((uint32_t)0x00000006U)
+#define MDIOS_REG7 ((uint32_t)0x00000007U)
+#define MDIOS_REG8 ((uint32_t)0x00000008U)
+#define MDIOS_REG9 ((uint32_t)0x00000009U)
+#define MDIOS_REG10 ((uint32_t)0x0000000AU)
+#define MDIOS_REG11 ((uint32_t)0x0000000BU)
+#define MDIOS_REG12 ((uint32_t)0x0000000CU)
+#define MDIOS_REG13 ((uint32_t)0x0000000DU)
+#define MDIOS_REG14 ((uint32_t)0x0000000EU)
+#define MDIOS_REG15 ((uint32_t)0x0000000FU)
+#define MDIOS_REG16 ((uint32_t)0x00000010U)
+#define MDIOS_REG17 ((uint32_t)0x00000011U)
+#define MDIOS_REG18 ((uint32_t)0x00000012U)
+#define MDIOS_REG19 ((uint32_t)0x00000013U)
+#define MDIOS_REG20 ((uint32_t)0x00000014U)
+#define MDIOS_REG21 ((uint32_t)0x00000015U)
+#define MDIOS_REG22 ((uint32_t)0x00000016U)
+#define MDIOS_REG23 ((uint32_t)0x00000017U)
+#define MDIOS_REG24 ((uint32_t)0x00000018U)
+#define MDIOS_REG25 ((uint32_t)0x00000019U)
+#define MDIOS_REG26 ((uint32_t)0x0000001AU)
+#define MDIOS_REG27 ((uint32_t)0x0000001BU)
+#define MDIOS_REG28 ((uint32_t)0x0000001CU)
+#define MDIOS_REG29 ((uint32_t)0x0000001DU)
+#define MDIOS_REG30 ((uint32_t)0x0000001EU)
+#define MDIOS_REG31 ((uint32_t)0x0000001FU)
+/**
+ * @}
+ */
+
+/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags
+ * @{
+ */
+#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
+#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
+#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
+#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
+#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
+#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
+#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
+#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
+#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
+#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
+#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
+#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
+#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
+#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
+#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
+#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
+#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
+#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
+#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
+#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
+#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
+#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
+#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
+#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
+#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
+#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
+#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
+#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
+#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
+#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
+#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
+#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
+#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
+/**
+ * @}
+ */
+
+/** @defgroup MDIOS_Interrupt_sources Interrupt Sources
+ * @{
+ */
+#define MDIOS_IT_WRITE MDIOS_CR_WRIE
+#define MDIOS_IT_READ MDIOS_CR_RDIE
+#define MDIOS_IT_ERROR MDIOS_CR_EIE
+/**
+ * @}
+ */
+
+/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags
+ * @{
+ */
+#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
+#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
+#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
+/**
+ * @}
+ */
+
+ /** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line
+ * @{
+ */
+#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x01000000) /* !< EXTI Line 24 */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
+ * @{
+ */
+
+/** @brief Reset MDIOS handle state
+ * @param __HANDLE__: MDIOS handle.
+ * @retval None
+ */
+#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
+
+/**
+ * @brief Enable/Disable the MDIOS peripheral.
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @retval None
+ */
+#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
+#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
+
+
+/**
+ * @brief Enable the MDIOS device interrupt.
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg MDIOS_IT_WRITE: Register write interrupt
+ * @arg MDIOS_IT_READ: Register read interrupt
+ * @arg MDIOS_IT_ERROR: Error interrupt
+ * @retval None
+ */
+#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the MDIOS device interrupt.
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg MDIOS_IT_WRITE: Register write interrupt
+ * @arg MDIOS_IT_READ: Register read interrupt
+ * @arg MDIOS_IT_ERROR: Error interrupt
+ * @retval None
+ */
+#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
+
+/** @brief Set MDIOS slave get write register flag
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __FLAG__: specifies the write register flag
+ * @retval The state of write flag
+ */
+#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
+
+/** @brief MDIOS slave get read register flag
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __FLAG__: specifies the read register flag
+ * @retval The state of read flag
+ */
+#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
+
+/** @brief MDIOS slave get interrupt
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __FLAG__ : specifies the Error flag.
+ * This parameter can be one or a combination of the following values:
+ * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
+ * @arg MDIOS_START_ERROR_FLAG: Register read interrupt
+ * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
+ * @retval The state of the error flag
+ */
+#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
+
+/** @brief MDIOS slave clear interrupt
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __FLAG__ : specifies the Error flag.
+ * This parameter can be one or a combination of the following values:
+ * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
+ * @arg MDIOS_START_ERROR_FLAG: Register read interrupt
+ * @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
+ * @retval none
+ */
+#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
+
+/**
+ * @brief Checks whether the specified MDIOS interrupt is set or not.
+ * @param __HANDLE__: specifies the MDIOS handle.
+ * @param __INTERRUPT__ : specifies the MDIOS interrupt sources
+ * This parameter can be one or a combination of the following values:
+ * @arg MDIOS_IT_WRITE: Register write interrupt
+ * @arg MDIOS_IT_READ: Register read interrupt
+ * @arg MDIOS_IT_ERROR: Error interrupt
+ * @retval The state of the interrupt source
+ */
+#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
+
+/**
+ * @brief Enable the MDIOS WAKEUP Exti Line.
+ * @retval None.
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @brief Disable the MDIOS WAKEUP Exti Line.
+ * @retval None.
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @brief Enable event on MDIOS WAKEUP Exti Line.
+ * @retval None.
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT() (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @brief Disable event on MDIOS WAKEUP Exti Line.
+ * @retval None.
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
+ * @retval EXTI MDIOS WAKEUP Line Status.
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @brief Clear the MDIOS WAKEUP Exti flag.
+ * @retval None.
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @brief Enables rising edge trigger to the MDIOS External interrupt line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE
+
+/**
+ * @brief Disables the rising edge trigger to the MDIOS External interrupt line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
+
+/**
+ * @brief Enables falling edge trigger to the MDIOS External interrupt line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE)
+
+/**
+ * @brief Disables falling edge trigger to the MDIOS External interrupt line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
+
+/**
+ * @brief Enables rising/falling edge trigger to the MDIOS External interrupt line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE
+
+/**
+ * @brief Disables rising/falling edge trigger to the MDIOS External interrupt line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @retval None
+ */
+#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
+ * @{
+ */
+
+/** @addtogroup MDIOS_Exported_Functions_Group1
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
+HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
+/**
+ * @}
+ */
+
+/** @addtogroup MDIOS_Exported_Functions_Group2
+ * @{
+ */
+HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data);
+HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData);
+
+uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
+uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
+HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
+HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
+
+HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
+void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
+/**
+ * @}
+ */
+
+/** @addtogroup MDIOS_Exported_Functions_Group3
+ * @{
+ */
+uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
+HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Types MDIOS Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Constants MDIOS Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Macros MDIOS Private Macros
+ * @{
+ */
+
+#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
+
+#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
+
+#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
+ ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
+
+ /**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#endif /* MDIOS */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_MDIOS_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h
new file mode 100644
index 0000000..4b9f664
--- /dev/null
+++ b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_mmc.h
@@ -0,0 +1,695 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_mmc.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 30-December-2016
+ * @brief Header file of MMC HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_MMC_H
+#define __STM32F7xx_HAL_MMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_sdmmc.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup MMC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_Types MMC Exported Types
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_STATE_RESET = ((uint32_t)0x00000000U), /*!< MMC not yet initialized or disabled */
+ HAL_MMC_STATE_READY = ((uint32_t)0x00000001U), /*!< MMC initialized and ready for use */
+ HAL_MMC_STATE_TIMEOUT = ((uint32_t)0x00000002U), /*!< MMC Timeout state */
+ HAL_MMC_STATE_BUSY = ((uint32_t)0x00000003U), /*!< MMC process ongoing */
+ HAL_MMC_STATE_PROGRAMMING = ((uint32_t)0x00000004U), /*!< MMC Programming State */
+ HAL_MMC_STATE_RECEIVING = ((uint32_t)0x00000005U), /*!< MMC Receinving State */
+ HAL_MMC_STATE_TRANSFER = ((uint32_t)0x00000006U), /*!< MMC Transfert State */
+ HAL_MMC_STATE_ERROR = ((uint32_t)0x0000000FU) /*!< MMC is in error state */
+}HAL_MMC_StateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure
+ * @{
+ */
+typedef enum
+{
+ HAL_MMC_CARD_READY = ((uint32_t)0x00000001U), /*!< Card state is ready */
+ HAL_MMC_CARD_IDENTIFICATION = ((uint32_t)0x00000002U), /*!< Card is in identification state */
+ HAL_MMC_CARD_STANDBY = ((uint32_t)0x00000003U), /*!< Card is in standby state */
+ HAL_MMC_CARD_TRANSFER = ((uint32_t)0x00000004U), /*!< Card is in transfer state */
+ HAL_MMC_CARD_SENDING = ((uint32_t)0x00000005U), /*!< Card is sending an operation */
+ HAL_MMC_CARD_RECEIVING = ((uint32_t)0x00000006U), /*!< Card is receiving operation information */
+ HAL_MMC_CARD_PROGRAMMING = ((uint32_t)0x00000007U), /*!< Card is in programming state */
+ HAL_MMC_CARD_DISCONNECTED = ((uint32_t)0x00000008U), /*!< Card is disconnected */
+ HAL_MMC_CARD_ERROR = ((uint32_t)0x000000FFU) /*!< Card response Error */
+}HAL_MMC_CardStateTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition
+ * @{
+ */
+#define MMC_InitTypeDef SDMMC_InitTypeDef
+#define MMC_TypeDef SDMMC_TypeDef
+
+/**
+ * @brief MMC Card Information Structure definition
+ */
+typedef struct
+{
+ uint32_t CardType; /*!< Specifies the card Type */
+
+ uint32_t Class; /*!< Specifies the class of the card class */
+
+ uint32_t RelCardAdd; /*!< Specifies the Relative Card Address */
+
+ uint32_t BlockNbr; /*!< Specifies the Card Capacity in blocks */
+
+ uint32_t BlockSize; /*!< Specifies one block size in bytes */
+
+ uint32_t LogBlockNbr; /*!< Specifies the Card logical Capacity in blocks */
+
+ uint32_t LogBlockSize; /*!< Specifies logical block size in bytes */
+
+}HAL_MMC_CardInfoTypeDef;
+
+/**
+ * @brief MMC handle Structure definition
+ */
+typedef struct
+{
+ MMC_TypeDef *Instance; /*!< MMC registers base address */
+
+ MMC_InitTypeDef Init; /*!< MMC required parameters */
+
+ HAL_LockTypeDef Lock; /*!< MMC locking object */
+
+ uint32_t *pTxBuffPtr; /*!< Pointer to MMC Tx transfer Buffer */
+
+ uint32_t TxXferSize; /*!< MMC Tx Transfer size */
+
+ uint32_t *pRxBuffPtr; /*!< Pointer to MMC Rx transfer Buffer */
+
+ uint32_t RxXferSize; /*!< MMC Rx Transfer size */
+
+ __IO uint32_t Context; /*!< MMC transfer context */
+
+ __IO HAL_MMC_StateTypeDef State; /*!< MMC card State */
+
+ __IO uint32_t ErrorCode; /*!< MMC Card Error codes */
+
+ DMA_HandleTypeDef *hdmarx; /*!< MMC Rx DMA handle parameters */
+
+ DMA_HandleTypeDef *hdmatx; /*!< MMC Tx DMA handle parameters */
+
+ HAL_MMC_CardInfoTypeDef MmcCard; /*!< MMC Card information */
+
+ uint32_t CSD[4]; /*!< MMC card specific data table */
+
+ uint32_t CID[4]; /*!< MMC card identification number table */
+
+}MMC_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t CSDStruct; /*!< CSD structure */
+ __IO uint8_t SysSpecVersion; /*!< System specification version */
+ __IO uint8_t Reserved1; /*!< Reserved */
+ __IO uint8_t TAAC; /*!< Data read access time 1 */
+ __IO uint8_t NSAC; /*!< Data read access time 2 in CLK cycles */
+ __IO uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */
+ __IO uint16_t CardComdClasses; /*!< Card command classes */
+ __IO uint8_t RdBlockLen; /*!< Max. read data block length */
+ __IO uint8_t PartBlockRead; /*!< Partial blocks for read allowed */
+ __IO uint8_t WrBlockMisalign; /*!< Write block misalignment */
+ __IO uint8_t RdBlockMisalign; /*!< Read block misalignment */
+ __IO uint8_t DSRImpl; /*!< DSR implemented */
+ __IO uint8_t Reserved2; /*!< Reserved */
+ __IO uint32_t DeviceSize; /*!< Device Size */
+ __IO uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */
+ __IO uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */
+ __IO uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */
+ __IO uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */
+ __IO uint8_t DeviceSizeMul; /*!< Device size multiplier */
+ __IO uint8_t EraseGrSize; /*!< Erase group size */
+ __IO uint8_t EraseGrMul; /*!< Erase group size multiplier */
+ __IO uint8_t WrProtectGrSize; /*!< Write protect group size */
+ __IO uint8_t WrProtectGrEnable; /*!< Write protect group enable */
+ __IO uint8_t ManDeflECC; /*!< Manufacturer default ECC */
+ __IO uint8_t WrSpeedFact; /*!< Write speed factor */
+ __IO uint8_t MaxWrBlockLen; /*!< Max. write data block length */
+ __IO uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */
+ __IO uint8_t Reserved3; /*!< Reserved */
+ __IO uint8_t ContentProtectAppli; /*!< Content protection application */
+ __IO uint8_t FileFormatGrouop; /*!< File format group */
+ __IO uint8_t CopyFlag; /*!< Copy flag (OTP) */
+ __IO uint8_t PermWrProtect; /*!< Permanent write protection */
+ __IO uint8_t TempWrProtect; /*!< Temporary write protection */
+ __IO uint8_t FileFormat; /*!< File format */
+ __IO uint8_t ECC; /*!< ECC code */
+ __IO uint8_t CSD_CRC; /*!< CSD CRC */
+ __IO uint8_t Reserved4; /*!< Always 1 */
+
+}HAL_MMC_CardCSDTypeDef;
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register
+ * @{
+ */
+typedef struct
+{
+ __IO uint8_t ManufacturerID; /*!< Manufacturer ID */
+ __IO uint16_t OEM_AppliID; /*!< OEM/Application ID */
+ __IO uint32_t ProdName1; /*!< Product Name part1 */
+ __IO uint8_t ProdName2; /*!< Product Name part2 */
+ __IO uint8_t ProdRev; /*!< Product Revision */
+ __IO uint32_t ProdSN; /*!< Product Serial Number */
+ __IO uint8_t Reserved1; /*!< Reserved1 */
+ __IO uint16_t ManufactDate; /*!< Manufacturing Date */
+ __IO uint8_t CID_CRC; /*!< CID CRC */
+ __IO uint8_t Reserved2; /*!< Always 1 */
+
+}HAL_MMC_CardCIDTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Constants Exported Constants
+ * @{
+ */
+
+#define BLOCKSIZE ((uint32_t)512U) /*!< Block size is 512 bytes */
+#define CAPACITY ((uint32_t)0x80000000U) /*!< 2 G bytes constant */
+
+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition
+ * @{
+ */
+#define HAL_MMC_ERROR_NONE SDMMC_ERROR_NONE /*!< No error */
+#define HAL_MMC_ERROR_CMD_CRC_FAIL SDMMC_ERROR_CMD_CRC_FAIL /*!< Command response received (but CRC check failed) */
+#define HAL_MMC_ERROR_DATA_CRC_FAIL SDMMC_ERROR_DATA_CRC_FAIL /*!< Data block sent/received (CRC check failed) */
+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT SDMMC_ERROR_CMD_RSP_TIMEOUT /*!< Command response timeout */
+#define HAL_MMC_ERROR_DATA_TIMEOUT SDMMC_ERROR_DATA_TIMEOUT /*!< Data timeout */
+#define HAL_MMC_ERROR_TX_UNDERRUN SDMMC_ERROR_TX_UNDERRUN /*!< Transmit FIFO underrun */
+#define HAL_MMC_ERROR_RX_OVERRUN SDMMC_ERROR_RX_OVERRUN /*!< Receive FIFO overrun */
+#define HAL_MMC_ERROR_ADDR_MISALIGNED SDMMC_ERROR_ADDR_MISALIGNED /*!< Misaligned address */
+#define HAL_MMC_ERROR_BLOCK_LEN_ERR SDMMC_ERROR_BLOCK_LEN_ERR /*!< Transferred block length is not allowed for the card or the
+ number of transferred bytes does not match the block length */
+#define HAL_MMC_ERROR_ERASE_SEQ_ERR SDMMC_ERROR_ERASE_SEQ_ERR /*!< An error in the sequence of erase command occurs */
+#define HAL_MMC_ERROR_BAD_ERASE_PARAM SDMMC_ERROR_BAD_ERASE_PARAM /*!< An invalid selection for erase groups */
+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION SDMMC_ERROR_WRITE_PROT_VIOLATION /*!< Attempt to program a write protect block */
+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED SDMMC_ERROR_LOCK_UNLOCK_FAILED /*!< Sequence or password error has been detected in unlock
+ command or if there was an attempt to access a locked card */
+#define HAL_MMC_ERROR_COM_CRC_FAILED SDMMC_ERROR_COM_CRC_FAILED /*!< CRC check of the previous command failed */
+#define HAL_MMC_ERROR_ILLEGAL_CMD SDMMC_ERROR_ILLEGAL_CMD /*!< Command is not legal for the card state */
+#define HAL_MMC_ERROR_CARD_ECC_FAILED SDMMC_ERROR_CARD_ECC_FAILED /*!< Card internal ECC was applied but failed to correct the data */
+#define HAL_MMC_ERROR_CC_ERR SDMMC_ERROR_CC_ERR /*!< Internal card controller error */
+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR SDMMC_ERROR_GENERAL_UNKNOWN_ERR /*!< General or unknown error */
+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN SDMMC_ERROR_STREAM_READ_UNDERRUN /*!< The card could not sustain data reading in stream rmode */
+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN SDMMC_ERROR_STREAM_WRITE_OVERRUN /*!< The card could not sustain data programming in stream mode */
+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE SDMMC_ERROR_CID_CSD_OVERWRITE /*!< CID/CSD overwrite error */
+#define HAL_MMC_ERROR_WP_ERASE_SKIP SDMMC_ERROR_WP_ERASE_SKIP /*!< Only partial address space was erased */
+#define HAL_MMC_ERROR_CARD_ECC_DISABLED SDMMC_ERROR_CARD_ECC_DISABLED /*!< Command has been executed without using internal ECC */
+#define HAL_MMC_ERROR_ERASE_RESET SDMMC_ERROR_ERASE_RESET /*!< Erase sequence was cleared before executing because an out
+ of erase sequence command was received */
+#define HAL_MMC_ERROR_AKE_SEQ_ERR SDMMC_ERROR_AKE_SEQ_ERR /*!< Error in sequence of authentication */
+#define HAL_MMC_ERROR_INVALID_VOLTRANGE SDMMC_ERROR_INVALID_VOLTRANGE /*!< Error in case of invalid voltage range */
+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE SDMMC_ERROR_ADDR_OUT_OF_RANGE /*!< Error when addressed block is out of range */
+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE SDMMC_ERROR_REQUEST_NOT_APPLICABLE /*!< Error when command request is not applicable */
+#define HAL_MMC_ERROR_PARAM SDMMC_ERROR_INVALID_PARAMETER /*!< the used parameter is not valid */
+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE SDMMC_ERROR_UNSUPPORTED_FEATURE /*!< Error when feature is not insupported */
+#define HAL_MMC_ERROR_BUSY SDMMC_ERROR_BUSY /*!< Error when transfer process is busy */
+#define HAL_MMC_ERROR_DMA SDMMC_ERROR_DMA /*!< Error while DMA transfer */
+#define HAL_MMC_ERROR_TIMEOUT SDMMC_ERROR_TIMEOUT /*!< Timeout error */
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration
+ * @{
+ */
+#define MMC_CONTEXT_NONE ((uint32_t)0x00000000U) /*!< None */
+#define MMC_CONTEXT_READ_SINGLE_BLOCK ((uint32_t)0x00000001U) /*!< Read single block operation */
+#define MMC_CONTEXT_READ_MULTIPLE_BLOCK ((uint32_t)0x00000002U) /*!< Read multiple blocks operation */
+#define MMC_CONTEXT_WRITE_SINGLE_BLOCK ((uint32_t)0x00000010U) /*!< Write single block operation */
+#define MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U) /*!< Write multiple blocks operation */
+#define MMC_CONTEXT_IT ((uint32_t)0x00000008U) /*!< Process in Interrupt mode */
+#define MMC_CONTEXT_DMA ((uint32_t)0x00000080U) /*!< Process in DMA mode */
+
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode
+ * @{
+ */
+/**
+ * @brief
+ */
+#define MMC_HIGH_VOLTAGE_RANGE 0x80FF8000U /*!< VALUE OF ARGUMENT */
+#define MMC_DUAL_VOLTAGE_RANGE 0x80FF8080U /*!< VALUE OF ARGUMENT */
+#define eMMC_HIGH_VOLTAGE_RANGE 0xC0FF8000U /*!< for eMMC > 2Gb sector mode */
+#define eMMC_DUAL_VOLTAGE_RANGE 0xC0FF8080U /*!< for eMMC > 2Gb sector mode */
+#define MMC_INVALID_VOLTAGE_RANGE 0x0001FF01U
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards
+ * @{
+ */
+#define MMC_HIGH_VOLTAGE_CARD ((uint32_t)0x00000000U)
+#define MMC_DUAL_VOLTAGE_CARD ((uint32_t)0x00000001U)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup MMC_Exported_macros MMC Exported Macros
+ * @brief macros to handle interrupts and specific clock configurations
+ * @{
+ */
+
+/**
+ * @brief Enable the MMC device.
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE(__HANDLE__) __SDMMC_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the MMC device.
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE(__HANDLE__) __SDMMC_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_MMC_DMA_ENABLE(__HANDLE__) __SDMMC_DMA_ENABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Disable the SDMMC DMA transfer.
+ * @retval None
+ */
+#define __HAL_MMC_DMA_DISABLE(__HANDLE__) __SDMMC_DMA_DISABLE((__HANDLE__)->Instance)
+
+/**
+ * @brief Enable the MMC device interrupt.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Disable the MMC device interrupt.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Check whether the specified MMC flag is set or not.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
+ * @arg SDMMC_FLAG_TXACT: Data transmit in progress
+ * @arg SDMMC_FLAG_RXACT: Data receive in progress
+ * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+ * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
+ * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
+ * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
+ * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
+ * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
+ * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
+ * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
+ * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval The new state of MMC FLAG (SET or RESET).
+ */
+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Clear the MMC's pending flags.
+ * @param __HANDLE__: MMC Handle
+ * @param __FLAG__: specifies the flag to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
+ * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+ * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
+ * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
+ * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
+ * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
+ * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
+ * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
+ * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
+ * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
+ * @arg SDMMC_FLAG_SDIOIT: SD I/O interrupt received
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
+
+/**
+ * @brief Check whether the specified MMC interrupt has occurred or not.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
+ * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
+ * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
+ * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+ * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+ * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
+ * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
+ * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
+ * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
+ * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
+ * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval The new state of SD IT (SET or RESET).
+ */
+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @brief Clear the MMC's interrupt pending bits.
+ * @param __HANDLE__: MMC Handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one or a combination of the following values:
+ * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+ * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+ * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
+ * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
+ * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+ * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
+ * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
+ * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
+ * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
+ * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
+ * @retval None
+ */
+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup MMC_Exported_Functions MMC Exported Functions
+ * @{
+ */
+
+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions
+ * @{
+ */
+/* Blocking mode: Polling */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);
+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);
+/* Non-Blocking mode: IT */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+/* Non-Blocking mode: DMA */
+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);
+
+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);
+
+/* Callback in non blocking modes (DMA) */
+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);
+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions
+ * @{
+ */
+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);
+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);
+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions
+ * @{
+ */
+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);
+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management
+ * @{
+ */
+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);
+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup MMC_Private_Types MMC Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private defines -----------------------------------------------------------*/
+/** @defgroup MMC_Private_Defines MMC Private Defines
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Variables MMC Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Constants MMC Private Constants
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup MMC_Private_Macros MMC Private Macros
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions prototypes ----------------------------------------------*/
+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup MMC_Private_Functions MMC Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __STM32F7xx_HAL_MMC_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h
new file mode 100644
index 0000000..500594d
--- /dev/null
+++ b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h
@@ -0,0 +1,336 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_nand.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 30-December-2016
+ * @brief Header file of NAND HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_NAND_H
+#define __STM32F7xx_HAL_NAND_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_fmc.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NAND
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Types NAND Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL NAND State structures definition
+ */
+typedef enum
+{
+ HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
+ HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
+ HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
+ HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
+}HAL_NAND_StateTypeDef;
+
+/**
+ * @brief NAND Memory electronic signature Structure definition
+ */
+typedef struct
+{
+ /*<! NAND memory electronic signature maker and device IDs */
+
+ uint8_t Maker_Id;
+
+ uint8_t Device_Id;
+
+ uint8_t Third_Id;
+
+ uint8_t Fourth_Id;
+}NAND_IDTypeDef;
+
+/**
+ * @brief NAND Memory address Structure definition
+ */
+typedef struct
+{
+ uint16_t Page; /*!< NAND memory Page address */
+
+ uint16_t Plane; /*!< NAND memory Zone address */
+
+ uint16_t Block; /*!< NAND memory Block address */
+
+}NAND_AddressTypeDef;
+
+/**
+ * @brief NAND Memory info Structure definition
+ */
+typedef struct
+{
+ uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes
+ for 8 bits adressing or words for 16 bits addressing */
+
+ uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */
+
+ uint32_t BlockNbr; /*!< NAND memory number of total blocks */
+
+ uint32_t PlaneNbr; /*!< NAND memory number of planes */
+
+ uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */
+
+ FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This
+ parameter is mandatory for some NAND parts after the read
+ command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
+ Example: Toshiba THTH58BYG3S0HBAI6.
+ This parameter could be ENABLE or DISABLE
+ Please check the Read Mode sequnece in the NAND device datasheet */
+}NAND_DeviceConfigTypeDef;
+
+/**
+ * @brief NAND handle Structure definition
+ */
+typedef struct
+{
+ FMC_NAND_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NAND locking object */
+
+ __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
+
+ NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */
+
+}NAND_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NAND_Exported_Macros NAND Exported Macros
+ * @{
+ */
+
+/** @brief Reset NAND handle state
+ * @param __HANDLE__: specifies the NAND handle.
+ * @retval None
+ */
+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NAND_Exported_Functions NAND Exported Functions
+ * @{
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
+HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
+void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
+void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
+void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* IO operation functions ****************************************************/
+
+HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
+ * @{
+ */
+
+/* NAND Control functions ****************************************************/
+HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
+HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
+
+/**
+ * @}
+ */
+
+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
+ * @{
+ */
+/* NAND State functions *******************************************************/
+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
+uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+ * @{
+ */
+#define NAND_DEVICE ((uint32_t)0x80000000U)
+#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
+
+#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
+#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A ((uint8_t)0x00U)
+#define NAND_CMD_AREA_B ((uint8_t)0x01U)
+#define NAND_CMD_AREA_C ((uint8_t)0x50U)
+#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
+
+#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
+#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
+#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
+#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
+#define NAND_CMD_READID ((uint8_t)0x90U)
+#define NAND_CMD_STATUS ((uint8_t)0x70U)
+#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
+#define NAND_CMD_RESET ((uint8_t)0xFFU)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
+#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
+#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
+#define NAND_BUSY ((uint32_t)0x00000000U)
+#define NAND_ERROR ((uint32_t)0x00000001U)
+#define NAND_READY ((uint32_t)0x00000040U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+ * @{
+ */
+
+/**
+ * @brief NAND memory address computation.
+ * @param __ADDRESS__: NAND memory address.
+ * @param __HANDLE__ : NAND handle.
+ * @retval NAND Raw address value
+ */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+ (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+ * @brief NAND memory address cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND address cycling value.
+ */
+#define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */
+
+/**
+ * @brief NAND memory Columns cycling.
+ * @param __ADDRESS__: NAND memory address.
+ * @retval NAND Column address cycling value.
+ */
+#define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_NAND_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-core/blob/35529b95/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h
----------------------------------------------------------------------
diff --git a/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h
new file mode 100644
index 0000000..e2cf980
--- /dev/null
+++ b/hw/mcu/stm/stm32f7xx/src/ext/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nor.h
@@ -0,0 +1,299 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_nor.h
+ * @author MCD Application Team
+ * @version V1.2.0
+ * @date 30-December-2016
+ * @brief Header file of NOR HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_NOR_H
+#define __STM32F7xx_HAL_NOR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_ll_fmc.h"
+
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup NOR
+ * @{
+ */
+
+/* Exported typedef ----------------------------------------------------------*/
+/** @defgroup NOR_Exported_Types NOR Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL SRAM State structures definition
+ */
+typedef enum
+{
+ HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
+ HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
+ HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
+ HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
+ HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
+}HAL_NOR_StateTypeDef;
+
+/**
+ * @brief FMC NOR Status typedef
+ */
+typedef enum
+{
+ HAL_NOR_STATUS_SUCCESS = 0U,
+ HAL_NOR_STATUS_ONGOING,
+ HAL_NOR_STATUS_ERROR,
+ HAL_NOR_STATUS_TIMEOUT
+}HAL_NOR_StatusTypeDef;
+
+/**
+ * @brief FMC NOR ID typedef
+ */
+typedef struct
+{
+ uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
+
+ uint16_t Device_Code1;
+
+ uint16_t Device_Code2;
+
+ uint16_t Device_Code3; /*!< Defines the device's codes used to identify the memory.
+ These codes can be accessed by performing read operations with specific
+ control signals and addresses set.They can also be accessed by issuing
+ an Auto Select command */
+}NOR_IDTypeDef;
+
+/**
+ * @brief FMC NOR CFI typedef
+ */
+typedef struct
+{
+ /*!< Defines the information stored in the memory's Common flash interface
+ which contains a description of various electrical and timing parameters,
+ density information and functions supported by the memory */
+
+ uint16_t CFI_1;
+
+ uint16_t CFI_2;
+
+ uint16_t CFI_3;
+
+ uint16_t CFI_4;
+}NOR_CFITypeDef;
+
+/**
+ * @brief NOR handle Structure definition
+ */
+typedef struct
+{
+ FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
+
+ FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
+
+ FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
+
+ HAL_LockTypeDef Lock; /*!< NOR locking object */
+
+ __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
+
+}NOR_HandleTypeDef;
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup NOR_Exported_Macros NOR Exported Macros
+ * @{
+ */
+/** @brief Reset NOR handle state
+ * @param __HANDLE__: specifies the NOR handle.
+ * @retval None
+ */
+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup NOR_Exported_Functions NOR Exported Functions
+ * @{
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @{
+ */
+
+/* Initialization/de-initialization functions ********************************/
+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
+ * @{
+ */
+
+/* I/O operation functions ***************************************************/
+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
+
+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
+
+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions
+ * @{
+ */
+
+/* NOR Control functions *****************************************************/
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
+/**
+ * @}
+ */
+
+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions
+ * @{
+ */
+
+/* NOR State functions ********************************************************/
+HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NOR_Private_Constants NOR Private Constants
+ * @{
+ */
+/* NOR device IDs addresses */
+#define MC_ADDRESS ((uint16_t)0x0000U)
+#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
+#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
+#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
+
+/* NOR CFI IDs addresses */
+#define CFI1_ADDRESS ((uint16_t)0x61U)
+#define CFI2_ADDRESS ((uint16_t)0x62U)
+#define CFI3_ADDRESS ((uint16_t)0x63U)
+#define CFI4_ADDRESS ((uint16_t)0x64U)
+
+/* NOR operation wait timeout */
+#define NOR_TMEOUT ((uint16_t)0xFFFFU)
+
+/* NOR memory data width */
+#define NOR_MEMORY_8B ((uint8_t)0x0U)
+#define NOR_MEMORY_16B ((uint8_t)0x1U)
+
+/* NOR memory device read/write start address */
+#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
+#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
+#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
+#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NOR_Private_Macros NOR Private Macros
+ * @{
+ */
+/**
+ * @brief NOR memory address shifting.
+ * @param __NOR_ADDRESS: NOR base address
+ * @param __NOR_MEMORY_WIDTH_: NOR memory width
+ * @param __ADDRESS__: NOR memory address
+ * @retval NOR shifted address value
+ */
+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
+ ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
+ ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
+ ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
+
+/**
+ * @brief NOR memory write data to specified address.
+ * @param __ADDRESS__: NOR memory address
+ * @param __DATA__: Data to write
+ * @retval None
+ */
+#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
+ (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \
+ __DSB(); \
+ } while(0)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_NOR_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/