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Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:04:31 UTC
[48/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/itmdump.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/itmdump.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/itmdump.c
new file mode 100755
index 0000000..8963894
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/itmdump.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright (C) 2010 by David Brownell
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or (at
+ * your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * Simple utility to parse and dump ARM Cortex-M3 SWO trace output. Once the
+ * mechanisms work right, this information can be used for various purposes
+ * including profiling (particularly easy for flat PC-sample profiles) and
+ * for debugging.
+ *
+ * SWO is the Single Wire Output found on some ARM cores, most notably on the
+ * Cortex-M3. It combines data from several sources:
+ *
+ * - Software trace (ITM): so-called "printf-style" application messaging
+ * using "ITM stimulus ports"; and differential timestamps.
+ * - Hardware trace (DWT): for profiling counters and comparator matches.
+ * - TPIU may issue sync packets.
+ *
+ * The trace data format is defined in Appendix E, "Debug ITM and DWT packet
+ * protocol", of the ARMv7-M Architecture Reference Manual (DDI 0403C). It
+ * is a superset of the ITM data format from the Coresight TRM.
+ *
+ * The trace data has two encodings. The working assumption is that data
+ * gets into this program using the UART encoding.
+ */
+
+#include <errno.h>
+#include <libgen.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <string.h>
+#include <unistd.h>
+
+unsigned int dump_swit;
+
+/* Example ITM trace word (0xWWXXYYZZ) parsing for task events, sent
+ * on port 31 (Reserved for "the" RTOS in CMSIS v1.30)
+ * WWXX: event code (0..3 pre-assigned, 4..15 reserved)
+ * YY: task priority
+ * ZZ: task number
+ *
+ * NOTE that this specific encoding could be space-optimized; and that
+ * trace data streams could also be history-sensitive.
+ */
+static void show_task(int port, unsigned data)
+{
+ unsigned code = data >> 16;
+ char buf[16];
+
+ if (dump_swit)
+ return;
+
+ switch (code) {
+ case 0:
+ strcpy(buf, "run");
+ break;
+ case 1:
+ strcpy(buf, "block");
+ break;
+ case 2:
+ strcpy(buf, "create");
+ break;
+ case 3:
+ strcpy(buf, "destroy");
+ break;
+ /* 4..15 reserved for other infrastructure ops */
+ default:
+ sprintf(buf, "code %d", code);
+ break;
+ }
+ printf("TASK %d, pri %d: %s",
+ (data >> 0) & 0xff,
+ (data >> 8) & 0xff,
+ buf);
+}
+
+static void show_reserved(FILE *f, char *label, int c)
+{
+ unsigned i;
+
+ if (dump_swit)
+ return;
+
+ printf("%s - %#02x", label, c);
+
+ for (i = 0; (c & 0x80) && i < 4; i++) {
+ c = fgetc(f);
+ if (c == EOF) {
+ printf("(ERROR %d - %s) ", errno, strerror(errno));
+ break;
+ }
+ printf(" %#02x", c);
+ }
+
+ printf("\n");
+}
+
+static bool read_varlen(FILE *f, int c, unsigned *value)
+{
+ unsigned size;
+ unsigned char buf[4];
+
+ *value = 0;
+
+ switch (c & 3) {
+ case 3:
+ size = 4;
+ break;
+ case 2:
+ size = 2;
+ break;
+ case 1:
+ size = 1;
+ break;
+ default:
+ printf("INVALID SIZE\n");
+ return false;
+ }
+
+ memset(buf, 0, sizeof buf);
+ if (fread(buf, 1, size, f) != size)
+ goto err;
+
+ *value = (buf[3] << 24)
+ + (buf[2] << 16)
+ + (buf[1] << 8)
+ + (buf[0] << 0);
+ return true;
+
+err:
+ printf("(ERROR %d - %s)\n", errno, strerror(errno));
+ return false;
+}
+
+static void show_hard(FILE *f, int c)
+{
+ unsigned type = c >> 3;
+ unsigned value;
+ char *label;
+
+ if (dump_swit)
+ return;
+
+ printf("DWT - ");
+
+ if (!read_varlen(f, c, &value))
+ return;
+ printf("%#x", value);
+
+ switch (type) {
+ case 0: /* event counter wrapping */
+ printf("overflow %s%s%s%s%s%s",
+ (value & (1 << 5)) ? "cyc " : "",
+ (value & (1 << 4)) ? "fold " : "",
+ (value & (1 << 3)) ? "lsu " : "",
+ (value & (1 << 2)) ? "slp " : "",
+ (value & (1 << 1)) ? "exc " : "",
+ (value & (1 << 0)) ? "cpi " : "");
+ break;
+ case 1: /* exception tracing */
+ switch (value >> 12) {
+ case 1:
+ label = "entry to";
+ break;
+ case 2:
+ label = "exit from";
+ break;
+ case 3:
+ label = "return to";
+ break;
+ default:
+ label = "?";
+ break;
+ }
+ printf("%s exception %d", label, value & 0x1ff);
+ break;
+ case 2: /* PC sampling */
+ if (c == 0x15)
+ printf("PC - sleep");
+ else
+ printf("PC - %#08x", value);
+ break;
+ case 8: /* data tracing, pc value */
+ case 10:
+ case 12:
+ case 14:
+ printf("Data trace %d, PC %#08x", (c >> 4) & 3, value);
+ /* optionally followed by data value */
+ break;
+ case 9: /* data tracing, address offset */
+ case 11:
+ case 13:
+ case 15:
+ printf("Data trace %d, address offset %#04x",
+ (c >> 4) & 3, value);
+ /* always followed by data value */
+ break;
+ case 16 ... 23: /* data tracing, data value */
+ printf("Data trace %d, ", (c >> 4) & 3);
+ label = (c & 0x8) ? "write" : "read";
+ switch (c & 3) {
+ case 3:
+ printf("word %s, value %#08x", label, value);
+ break;
+ case 2:
+ printf("halfword %s, value %#04x", label, value);
+ break;
+ case 1:
+ printf("byte %s, value %#02x", label, value);
+ break;
+ }
+ break;
+ default:
+ printf("UNDEFINED, rawtype: %x", type);
+ break;
+ }
+
+ printf("\n");
+ return;
+}
+
+/*
+ * Table of SWIT (SoftWare InstrumentTation) message dump formats, for
+ * ITM port 0..31 application data.
+ *
+ * Eventually this should be customizable; all usage is application defined.
+ *
+ * REVISIT there can be up to 256 trace ports, via "ITM Extension" packets
+ */
+struct {
+ int port;
+ void (*show)(int port, unsigned data);
+} format[] = {
+ { .port = 31, .show = show_task, },
+};
+
+static void show_swit(FILE *f, int c)
+{
+ unsigned port = c >> 3;
+ unsigned value = 0;
+ unsigned i;
+
+ if (port + 1 == dump_swit) {
+ if (!read_varlen(f, c, &value))
+ return;
+ printf("%c", value);
+ return;
+ }
+
+ if (!read_varlen(f, c, &value))
+ return;
+
+ if (dump_swit)
+ return;
+
+ printf("SWIT %u - ", port);
+
+ printf("%#08x", value);
+
+ for (i = 0; i < sizeof(format) / sizeof(format[0]); i++) {
+ if (format[i].port == port) {
+ printf(", ");
+ format[i].show(port, value);
+ break;
+ }
+ }
+
+ printf("\n");
+ return;
+}
+
+static void show_timestamp(FILE *f, int c)
+{
+ unsigned counter = 0;
+ char *label = "";
+ bool delayed = false;
+
+ if (dump_swit)
+ return;
+
+ printf("TIMESTAMP - ");
+
+ /* Format 2: header only */
+ if (!(c & 0x80)) {
+ switch (c) {
+ case 0: /* sync packet -- coding error! */
+ case 0x70: /* overflow -- ditto! */
+ printf("ERROR - %#02x\n", c);
+ break;
+ default:
+ /* synchronous to ITM */
+ counter = c >> 4;
+ goto done;
+ }
+ return;
+ }
+
+ /* Format 1: one to four bytes of data too */
+ switch (c >> 4) {
+ default:
+ label = ", reserved control\n";
+ break;
+ case 0xc:
+ /* synchronous to ITM */
+ break;
+ case 0xd:
+ label = ", timestamp delayed";
+ delayed = true;
+ break;
+ case 0xe:
+ label = ", packet delayed";
+ delayed = true;
+ break;
+ case 0xf:
+ label = ", packet and timetamp delayed";
+ delayed = true;
+ break;
+ }
+
+ c = fgetc(f);
+ if (c == EOF)
+ goto err;
+ counter = c & 0x7f;
+ if (!(c & 0x80))
+ goto done;
+
+ c = fgetc(f);
+ if (c == EOF)
+ goto err;
+ counter |= (c & 0x7f) << 7;
+ if (!(c & 0x80))
+ goto done;
+
+ c = fgetc(f);
+ if (c == EOF)
+ goto err;
+ counter |= (c & 0x7f) << 14;
+ if (!(c & 0x80))
+ goto done;
+
+ c = fgetc(f);
+ if (c == EOF)
+ goto err;
+ counter |= (c & 0x7f) << 21;
+
+done:
+ /* REVISIT should we try to convert from delta values? */
+ printf("+%u%s\n", counter, label);
+ return;
+
+err:
+ printf("(ERROR %d - %s) ", errno, strerror(errno));
+ goto done;
+}
+
+int main(int argc, char **argv)
+{
+ FILE *f = stdin;
+ int c;
+
+ /* parse arguments */
+ while ((c = getopt(argc, argv, "f:d:")) != EOF) {
+ switch (c) {
+ case 'f':
+ /* e.g. from UART connected to /dev/ttyUSB0 */
+ f = fopen(optarg, "r");
+ if (!f) {
+ perror(optarg);
+ return 1;
+ }
+ break;
+ case 'd':
+ dump_swit = atoi(optarg);
+ break;
+ default:
+ fprintf(stderr, "usage: %s [-f input]",
+ basename(argv[0]));
+ return 1;
+ }
+ }
+
+ /* Parse data ... records have a header then data bytes.
+ * NOTE: we assume getc() deals in 8-bit bytes.
+ */
+ bool overflow = false;
+
+ while ((c = getc(f)) != EOF) {
+
+ /* Sync packet ... 7 zeroes, 0x80 */
+ if (c == 0) {
+ int i;
+
+ for (i = 0; i < 6; i++) {
+ c = fgetc(f);
+ if (c == EOF)
+ break;
+ if (c != 0)
+ goto bad_sync;
+ }
+ c = fgetc(f);
+ if (c == 0x80) {
+ printf("SYNC\n");
+ continue;
+ }
+bad_sync:
+ printf("BAD SYNC\n");
+ continue;
+ }
+
+ /* Overflow packet */
+ if (c == 0x70) {
+ /* REVISIT later, report just what overflowed!
+ * Timestamp and SWIT can happen. Non-ITM too?
+ */
+ overflow = true;
+ printf("OVERFLOW ...\n");
+ continue;
+ }
+ overflow = false;
+
+ switch (c & 0x0f) {
+ case 0x00: /* Timestamp */
+ show_timestamp(f, c);
+ break;
+ case 0x04: /* "Reserved" */
+ show_reserved(f, "RESERVED", c);
+ break;
+ case 0x08: /* ITM Extension */
+ /* FIXME someday, handle these ... */
+ show_reserved(f, "ITM EXT", c);
+ break;
+ case 0x0c: /* DWT Extension */
+ show_reserved(f, "DWT EXT", c);
+ break;
+ default:
+ if (c & 4)
+ show_hard(f, c);
+ else
+ show_swit(f, c);
+ break;
+ }
+
+ }
+
+ return 0;
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/README
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/README b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/README
new file mode 100755
index 0000000..d67ccce
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/README
@@ -0,0 +1,19 @@
+This code is an example of using the openocd debug message system.
+
+Before the message output is seen in the debug window, the functionality
+will need enabling:
+
+From the gdb prompt:
+monitor target_request debugmsgs enable
+monitor trace point 1
+
+From the Telnet prompt:
+target_request debugmsgs enable
+trace point 1
+
+To see how many times the trace point was hit:
+(monitor) trace point 1
+
+Spen
+spen@spen-soft.co.uk
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.c
new file mode 100755
index 0000000..5a457e7
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.c
@@ -0,0 +1,157 @@
+/***************************************************************************
+ * Copyright (C) 2008 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * Copyright (C) 2008 by Frederik Kriewtz *
+ * frederik@kriewitz.eu *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#include "dcc_stdio.h"
+
+#define TARGET_REQ_TRACEMSG 0x00
+#define TARGET_REQ_DEBUGMSG_ASCII 0x01
+#define TARGET_REQ_DEBUGMSG_HEXMSG(size) (0x01 | ((size & 0xff) << 8))
+#define TARGET_REQ_DEBUGCHAR 0x02
+
+#if defined(__ARM_ARCH_7M__) || defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_6SM__)
+
+/* we use the System Control Block DCRDR reg to simulate a arm7_9 dcc channel
+ * DCRDR[7:0] is used by target for status
+ * DCRDR[15:8] is used by target for write buffer
+ * DCRDR[23:16] is used for by host for status
+ * DCRDR[31:24] is used for by host for write buffer */
+
+#define NVIC_DBG_DATA_R (*((volatile unsigned short *)0xE000EDF8))
+
+#define BUSY 1
+
+void dbg_write(unsigned long dcc_data)
+{
+ int len = 4;
+
+ while (len--)
+ {
+ /* wait for data ready */
+ while (NVIC_DBG_DATA_R & BUSY);
+
+ /* write our data and set write flag - tell host there is data*/
+ NVIC_DBG_DATA_R = (unsigned short)(((dcc_data & 0xff) << 8) | BUSY);
+ dcc_data >>= 8;
+ }
+}
+
+#elif defined(__ARM_ARCH_4T__) || defined(__ARM_ARCH_5TE__) || defined(__ARM_ARCH_5T__)
+
+void dbg_write(unsigned long dcc_data)
+{
+ unsigned long dcc_status;
+
+ do {
+ asm volatile("mrc p14, 0, %0, c0, c0" : "=r" (dcc_status));
+ } while (dcc_status & 0x2);
+
+ asm volatile("mcr p14, 0, %0, c1, c0" : : "r" (dcc_data));
+}
+
+#else
+ #error unsupported target
+#endif
+
+void dbg_trace_point(unsigned long number)
+{
+ dbg_write(TARGET_REQ_TRACEMSG | (number << 8));
+}
+
+void dbg_write_u32(const unsigned long *val, long len)
+{
+ dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(4) | ((len & 0xffff) << 16));
+
+ while (len > 0)
+ {
+ dbg_write(*val);
+
+ val++;
+ len--;
+ }
+}
+
+void dbg_write_u16(const unsigned short *val, long len)
+{
+ unsigned long dcc_data;
+
+ dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(2) | ((len & 0xffff) << 16));
+
+ while (len > 0)
+ {
+ dcc_data = val[0]
+ | ((len > 1) ? val[1] << 16: 0x0000);
+
+ dbg_write(dcc_data);
+
+ val += 2;
+ len -= 2;
+ }
+}
+
+void dbg_write_u8(const unsigned char *val, long len)
+{
+ unsigned long dcc_data;
+
+ dbg_write(TARGET_REQ_DEBUGMSG_HEXMSG(1) | ((len & 0xffff) << 16));
+
+ while (len > 0)
+ {
+ dcc_data = val[0]
+ | ((len > 1) ? val[1] << 8 : 0x00)
+ | ((len > 2) ? val[2] << 16 : 0x00)
+ | ((len > 3) ? val[3] << 24 : 0x00);
+
+ dbg_write(dcc_data);
+
+ val += 4;
+ len -= 4;
+ }
+}
+
+void dbg_write_str(const char *msg)
+{
+ long len;
+ unsigned long dcc_data;
+
+ for (len = 0; msg[len] && (len < 65536); len++);
+
+ dbg_write(TARGET_REQ_DEBUGMSG_ASCII | ((len & 0xffff) << 16));
+
+ while (len > 0)
+ {
+ dcc_data = msg[0]
+ | ((len > 1) ? msg[1] << 8 : 0x00)
+ | ((len > 2) ? msg[2] << 16 : 0x00)
+ | ((len > 3) ? msg[3] << 24 : 0x00);
+ dbg_write(dcc_data);
+
+ msg += 4;
+ len -= 4;
+ }
+}
+
+void dbg_write_char(char msg)
+{
+ dbg_write(TARGET_REQ_DEBUGCHAR | ((msg & 0xff) << 16));
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.h
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.h b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.h
new file mode 100755
index 0000000..cb87ab3
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/dcc_stdio.h
@@ -0,0 +1,35 @@
+/***************************************************************************
+ * Copyright (C) 2008 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifndef DCC_STDIO_H
+#define DCC_STDIO_H
+
+void dbg_trace_point(unsigned long number);
+
+void dbg_write_u32(const unsigned long *val, long len);
+void dbg_write_u16(const unsigned short *val, long len);
+void dbg_write_u8(const unsigned char *val, long len);
+
+void dbg_write_str(const char *msg);
+void dbg_write_char(char msg);
+
+#endif /* DCC_STDIO_H */
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/example.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/example.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/example.c
new file mode 100755
index 0000000..2cbef20
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/libdcc/example.c
@@ -0,0 +1,58 @@
+/***************************************************************************
+ * Copyright (C) 2008 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * Copyright (C) 2008 by Frederik Kriewtz *
+ * frederik@kriewitz.eu *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#include "dcc_stdio.h"
+
+/* enable openocd debugmsg at the gdb prompt:
+ * monitor target_request debugmsgs enable
+ *
+ * create a trace point:
+ * monitor trace point 1
+ *
+ * to show how often the trace point was hit:
+ * monitor trace point
+*/
+
+int main(void)
+{
+ dbg_write_str("hello world");
+
+ dbg_write_char('t');
+ dbg_write_char('e');
+ dbg_write_char('s');
+ dbg_write_char('t');
+ dbg_write_char('\n');
+
+ unsigned long test_u32 = 0x01234567;
+ dbg_write_u32(&test_u32, 1);
+
+ static const unsigned short test_u16[] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x0123, 0x4567, 0x89AB, 0xCDEF};
+ dbg_write_u16(test_u16, 8);
+
+ static const unsigned char test_u8[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC, 0XDD, 0xEE, 0xFF};
+ dbg_write_u8(test_u8, 16);
+
+ while(1)
+ {
+ dbg_trace_point(0);
+ }
+}
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/README
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/README b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/README
new file mode 100755
index 0000000..41236ef
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/README
@@ -0,0 +1,33 @@
+Included in these directories are the src to the various ram loaders used
+within openocd.
+
+** target checksum loaders **
+
+checksum/armv4_5_crc.s :
+ - ARMv4 and ARMv5 checksum loader : see target/arm_crc_code.c:arm_crc_code
+
+checksum/armv7m_crc.s :
+ - ARMv7m checksum loader : see target/armv7m.c:cortex_m_crc_code
+
+checksum/mips32.s :
+ - MIPS32 checksum loader : see target/mips32.c:mips_crc_code
+
+** target flash loaders **
+
+flash/pic32mx.s :
+ - Microchip PIC32 flash loader : see flash/nor/pic32mx.c:pic32mx_flash_write_code
+
+flash/stellaris.s :
+ - TI Stellaris flash loader : see flash/nor/stellaris.c:stellaris_write_code
+
+flash/stm32x.s :
+ - ST STM32 flash loader : see flash/nor/stm32x.c:stm32x_flash_write_code
+
+flash/str7x.s :
+ - ST STR7 flash loader : see flash/nor/str7x.c:str7x_flash_write_code
+
+flash/str9x.s :
+ - ST STR9 flash loader : see flash/nor/str9x.c:str9x_flash_write_code
+
+Spencer Oliver
+spen@spen-soft.co.uk
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv4_5_crc.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv4_5_crc.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv4_5_crc.s
new file mode 100755
index 0000000..8f62dc8
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv4_5_crc.s
@@ -0,0 +1,58 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+/*
+ r0 - address in - crc out
+ r1 - char count
+*/
+
+ .text
+ .arm
+
+_start:
+main:
+ mov r2, r0
+ mov r0, #0xffffffff /* crc */
+ mov r3, r1
+ mov r4, #0
+ b ncomp
+nbyte:
+ ldrb r1, [r2, r4]
+ ldr r7, CRC32XOR
+ eor r0, r0, r1, asl #24
+ mov r5, #0
+loop:
+ cmp r0, #0
+ mov r6, r0, asl #1
+ add r5, r5, #1
+ mov r0, r6
+ eorlt r0, r6, r7
+ cmp r5, #8
+ bne loop
+ add r4, r4, #1
+ncomp:
+ cmp r4, r3
+ bne nbyte
+end:
+ bkpt #0
+
+CRC32XOR: .word 0x04c11db7
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv7m_crc.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv7m_crc.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv7m_crc.s
new file mode 100755
index 0000000..923875a
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/armv7m_crc.s
@@ -0,0 +1,71 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+/*
+ parameters:
+ r0 - address in - crc out
+ r1 - char count
+*/
+
+ .text
+ .syntax unified
+ .cpu cortex-m0
+ .thumb
+ .thumb_func
+
+ .align 2
+
+_start:
+main:
+ mov r2, r0
+ movs r0, #0
+ mvns r0, r0
+ ldr r6, CRC32XOR
+ mov r3, r1
+ movs r4, #0
+ b ncomp
+nbyte:
+ ldrb r1, [r2, r4]
+ lsls r1, r1, #24
+ eors r0, r0, r1
+ movs r5, #0
+loop:
+ cmp r0, #0
+ bge notset
+ lsls r0, r0, #1
+ eors r0, r0, r6
+ b cont
+notset:
+ lsls r0, r0, #1
+cont:
+ adds r5, r5, #1
+ cmp r5, #8
+ bne loop
+ adds r4, r4, #1
+ncomp:
+ cmp r4, r3
+ bne nbyte
+ bkpt #0
+
+ .align 2
+
+CRC32XOR: .word 0x04c11db7
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/mips32.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/mips32.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/mips32.s
new file mode 100755
index 0000000..3073d87
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/checksum/mips32.s
@@ -0,0 +1,72 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .global main
+ .text
+ .set noreorder
+
+/* params:
+ * $a0 address in
+ * $a1 byte count
+ * vars
+ * $a0 crc
+ * $a1 crc data byte
+ * temps:
+ * t3 v0 a3 a2 t0 v1
+ */
+
+.ent main
+main:
+ addiu $t4, $a0, 0 /* address in */
+ addiu $t2, $a1, 0 /* count */
+
+ addiu $a0, $zero, 0xffffffff /* a0 crc - result */
+
+ beq $zero, $zero, ncomp
+ addiu $t3, $zero, 0 /* clear bytes read */
+
+nbyte:
+ lb $a1, ($t4) /* load byte from source address */
+ addi $t4, $t4, 1 /* inc byte count */
+
+crc:
+ sll $a1, $a1, 24
+ lui $v0, 0x04c1
+ xor $a0, $a0, $a1
+ ori $a3, $v0, 0x1db7
+ addu $a2, $zero, $zero /* clear bit count */
+loop:
+ sll $t0, $a0, 1
+ addiu $a2, $a2, 1 /* inc bit count */
+ slti $a0, $a0, 0
+ xor $t1, $t0, $a3
+ movn $t0, $t1, $a0
+ slti $v1, $a2, 8 /* 8bits processed */
+ bne $v1, $zero, loop
+ addu $a0, $t0, $zero
+
+ncomp:
+ bne $t2, $t3, nbyte /* all bytes processed */
+ addiu $t3, $t3, 1
+
+wait:
+ sdbbp
+
+.end main
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv4_5_erase_check.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv4_5_erase_check.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv4_5_erase_check.s
new file mode 100755
index 0000000..6d075a9
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv4_5_erase_check.s
@@ -0,0 +1,41 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+/*
+ parameters:
+ r0 - address in
+ r1 - byte count
+ r2 - mask - result out
+*/
+
+ .text
+ .arm
+
+loop:
+ ldrb r3, [r0], #1
+ and r2, r2, r3
+ subs r1, r1, #1
+ bne loop
+end:
+ bkpt #0
+
+CRC32XOR: .word 0x04c11db7
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.inc
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.inc b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.inc
new file mode 100755
index 0000000..76115ec
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.inc
@@ -0,0 +1,2 @@
+/* Autogenerated with ../../../src/helper/bin2char.sh */
+0x03,0x78,0x01,0x30,0x1a,0x43,0x01,0x39,0xfa,0xd1,0x00,0xbe,
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.s
new file mode 100755
index 0000000..6b1e92a
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_0_erase_check.s
@@ -0,0 +1,45 @@
+/***************************************************************************
+ * Copyright (C) 2014 by Jeff Ciesielski *
+ * jeffciesielski@gmail.com *
+ * *
+ * Based on the armv7m erase checker by: *
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ ***************************************************************************/
+
+/*
+ parameters:
+ r0 - address in
+ r1 - byte count
+ r2 - mask - result out
+*/
+
+ .text
+ .syntax unified
+ .cpu cortex-m0
+ .thumb
+ .thumb_func
+
+ .align 2
+
+loop:
+ ldrb r3, [r0]
+ adds r0, #1
+ orrs r2, r2, r3
+ subs r1, r1, #1
+ bne loop
+end:
+ bkpt #0
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.inc
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.inc b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.inc
new file mode 100755
index 0000000..1fe25cd
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.inc
@@ -0,0 +1,2 @@
+/* Autogenerated with ../../../src/helper/bin2char.sh */
+0x03,0x78,0x01,0x30,0x1a,0x40,0x01,0x39,0xfa,0xd1,0x00,0xbe,
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.s
new file mode 100755
index 0000000..886e3e2
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/erase_check/armv7m_erase_check.s
@@ -0,0 +1,45 @@
+/***************************************************************************
+ * Copyright (C) 2010 by Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+/*
+ parameters:
+ r0 - address in
+ r1 - byte count
+ r2 - mask - result out
+*/
+
+ .text
+ .syntax unified
+ .cpu cortex-m0
+ .thumb
+ .thumb_func
+
+ .align 2
+
+loop:
+ ldrb r3, [r0]
+ adds r0, #1
+ ands r2, r2, r3
+ subs r1, r1, #1
+ bne loop
+end:
+ bkpt #0
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_16.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_16.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_16.s
new file mode 100755
index 0000000..c35b651
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_16.s
@@ -0,0 +1,57 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* algorithm register usage:
+ * r0: source address (in RAM)
+ * r1: target address (in Flash)
+ * r2: count
+ * r3: flash write command
+ * r4: status byte (returned to host)
+ * r5: busy test pattern
+ * r6: error test pattern
+ */
+
+loop:
+ ldrh r4, [r0], #2
+ strh r3, [r1]
+ strh r4, [r1]
+busy:
+ ldrh r4, [r1]
+ and r7, r4, r5
+ cmp r7, r5
+ bne busy
+ tst r4, r6
+ bne done
+ subs r2, r2, #1
+ beq done
+ add r1, r1, #2
+ b loop
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_32.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_32.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_32.s
new file mode 100755
index 0000000..db47717
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_32.s
@@ -0,0 +1,57 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* algorithm register usage:
+ * r0: source address (in RAM)
+ * r1: target address (in Flash)
+ * r2: count
+ * r3: flash write command
+ * r4: status byte (returned to host)
+ * r5: busy test pattern
+ * r6: error test pattern
+ */
+
+loop:
+ ldr r4, [r0], #4
+ str r3, [r1]
+ str r4, [r1]
+busy:
+ ldr r4, [r1]
+ and r7, r4, r5
+ cmp r7, r5
+ bne busy
+ tst r4, r6
+ bne done
+ subs r2, r2, #1
+ beq done
+ add r1, r1, #4
+ b loop
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_8.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_8.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_8.s
new file mode 100755
index 0000000..d50acd2
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_intel_8.s
@@ -0,0 +1,57 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* algorithm register usage:
+ * r0: source address (in RAM)
+ * r1: target address (in Flash)
+ * r2: count
+ * r3: flash write command
+ * r4: status byte (returned to host)
+ * r5: busy test pattern
+ * r6: error test pattern
+ */
+
+loop:
+ ldrb r4, [r0], #1
+ strb r3, [r1]
+ strb r4, [r1]
+busy:
+ ldrb r4, [r1]
+ and r7, r4, r5
+ cmp r7, r5
+ bne busy
+ tst r4, r6
+ bne done
+ subs r2, r2, #1
+ beq done
+ add r1, r1, #1
+ b loop
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16.s
new file mode 100755
index 0000000..5327271
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16.s
@@ -0,0 +1,75 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* input parameters - */
+/* R0 = source address */
+/* R1 = destination address */
+/* R2 = number of writes */
+/* R3 = flash write command */
+/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/* R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/* R6 = value read from flash to test status */
+/* R7 = holding register */
+/* unlock registers - */
+/* R8 = unlock1_addr */
+/* R9 = unlock1_cmd */
+/* R10 = unlock2_addr */
+/* R11 = unlock2_cmd */
+
+code:
+ ldrh r5, [r0], #2
+ strh r9, [r8]
+ strh r11, [r10]
+ strh r3, [r8]
+ strh r5, [r1]
+ nop
+busy:
+ ldrh r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ ands r6, r6, r4, lsr #2
+ beq busy /* b if DQ5 low */
+ ldrh r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ mov r5, #0 /* 0x0 - return 0x00, error */
+ bne done
+cont:
+ subs r2, r2, #1 /* 0x1 */
+ moveq r5, #128 /* 0x80 */
+ beq done
+ add r1, r1, #2 /* 0x2 */
+ b code
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
new file mode 100755
index 0000000..919f6e1
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_16_dq7.s
@@ -0,0 +1,66 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* input parameters - */
+/* R0 = source address */
+/* R1 = destination address */
+/* R2 = number of writes */
+/* R3 = flash write command */
+/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/* R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/* R6 = value read from flash to test status */
+/* R7 = holding register */
+/* unlock registers - */
+/* R8 = unlock1_addr */
+/* R9 = unlock1_cmd */
+/* R10 = unlock2_addr */
+/* R11 = unlock2_cmd */
+
+code:
+ ldrh r5, [r0], #2
+ strh r9, [r8]
+ strh r11, [r10]
+ strh r3, [r8]
+ strh r5, [r1]
+ nop
+busy:
+ ldrh r6, [r1]
+ eor r7, r5, r6
+ ands r7, #0x80
+ bne busy
+ subs r2, r2, #1 /* 0x1 */
+ moveq r5, #128 /* 0x80 */
+ beq done
+ add r1, r1, #2 /* 0x2 */
+ b code
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_32.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_32.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_32.s
new file mode 100755
index 0000000..c8f87b1
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_32.s
@@ -0,0 +1,75 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* input parameters - */
+/* R0 = source address */
+/* R1 = destination address */
+/* R2 = number of writes */
+/* R3 = flash write command */
+/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/* R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/* R6 = value read from flash to test status */
+/* R7 = holding register */
+/* unlock registers - */
+/* R8 = unlock1_addr */
+/* R9 = unlock1_cmd */
+/* R10 = unlock2_addr */
+/* R11 = unlock2_cmd */
+
+code:
+ ldr r5, [r0], #4
+ str r9, [r8]
+ str r11, [r10]
+ str r3, [r8]
+ str r5, [r1]
+ nop
+busy:
+ ldr r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ ands r6, r6, r4, lsr #2
+ beq busy /* b if DQ5 low */
+ ldr r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ mov r5, #0 /* 0x0 - return 0x00, error */
+ bne done
+cont:
+ subs r2, r2, #1 /* 0x1 */
+ moveq r5, #128 /* 0x80 */
+ beq done
+ add r1, r1, #4 /* 0x4 */
+ b code
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_8.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_8.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_8.s
new file mode 100755
index 0000000..46018e1
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv4_5_cfi_span_8.s
@@ -0,0 +1,75 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .arm
+ .arch armv4
+
+ .section .init
+
+/* input parameters - */
+/* R0 = source address */
+/* R1 = destination address */
+/* R2 = number of writes */
+/* R3 = flash write command */
+/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/* R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/* R6 = value read from flash to test status */
+/* R7 = holding register */
+/* unlock registers - */
+/* R8 = unlock1_addr */
+/* R9 = unlock1_cmd */
+/* R10 = unlock2_addr */
+/* R11 = unlock2_cmd */
+
+code:
+ ldrb r5, [r0], #1
+ strb r9, [r8]
+ strb r11, [r10]
+ strb r3, [r8]
+ strb r5, [r1]
+ nop
+busy:
+ ldrb r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ ands r6, r6, r4, lsr #2
+ beq busy /* b if DQ5 low */
+ ldrb r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ mov r5, #0 /* 0x0 - return 0x00, error */
+ bne done
+cont:
+ subs r2, r2, #1 /* 0x1 */
+ moveq r5, #128 /* 0x80 */
+ beq done
+ add r1, r1, #1 /* 0x1 */
+ b code
+done:
+ b done
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16.s
new file mode 100755
index 0000000..d4915a7
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16.s
@@ -0,0 +1,81 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .syntax unified
+ .arch armv7-m
+ .thumb
+ .thumb_func
+
+ .align 2
+
+/* input parameters - */
+/* R0 = source address */
+/* R1 = destination address */
+/* R2 = number of writes */
+/* R3 = flash write command */
+/* R4 = constant to mask DQ7 bits (also used for Dq5 with shift) */
+/* output parameters - */
+/* R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/* R6 = value read from flash to test status */
+/* R7 = holding register */
+/* unlock registers - */
+/* R8 = unlock1_addr */
+/* R9 = unlock1_cmd */
+/* R10 = unlock2_addr */
+/* R11 = unlock2_cmd */
+
+code:
+ ldrh r5, [r0], #2
+ strh r9, [r8]
+ strh r11, [r10]
+ strh r3, [r8]
+ strh r5, [r1]
+ nop
+busy:
+ ldrh r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ ands r6, r6, r4, lsr #2
+ beq busy /* b if DQ5 low */
+ ldrh r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ beq cont /* b if DQ7 == Data7 */
+ mov r5, #0 /* 0x0 - return 0x00, error */
+ bne done
+cont:
+ subs r2, r2, #1 /* 0x1 */
+ beq success
+ add r1, r1, #2 /* 0x2 */
+ b code
+
+success:
+ mov r5, #128 /* 0x80 */
+ b done
+
+done:
+ bkpt #0
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
new file mode 100755
index 0000000..5b29a3b
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_cfi_span_16_dq7.s
@@ -0,0 +1,72 @@
+/***************************************************************************
+ * Copyright (C) 2005, 2007 by Dominic Rath *
+ * Dominic.Rath@gmx.de *
+ * Copyright (C) 2010 Spencer Oliver *
+ * spen@spen-soft.co.uk *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .syntax unified
+ .arch armv7-m
+ .thumb
+ .thumb_func
+
+ .align 2
+
+/* input parameters - */
+/* R0 = source address */
+/* R1 = destination address */
+/* R2 = number of writes */
+/* R3 = flash write command */
+/* R4 = constant to mask DQ7 bits */
+/* output parameters - */
+/* R5 = 0x80 ok 0x00 bad */
+/* temp registers - */
+/* R6 = value read from flash to test status */
+/* R7 = holding register */
+/* unlock registers - */
+/* R8 = unlock1_addr */
+/* R9 = unlock1_cmd */
+/* R10 = unlock2_addr */
+/* R11 = unlock2_cmd */
+
+code:
+ ldrh r5, [r0], #2
+ strh r9, [r8]
+ strh r11, [r10]
+ strh r3, [r8]
+ strh r5, [r1]
+ nop
+busy:
+ ldrh r6, [r1]
+ eor r7, r5, r6
+ ands r7, r4, r7
+ bne busy
+ subs r2, r2, #1 /* 0x1 */
+ beq success
+ add r1, r1, #2 /* 0x2 */
+ b code
+
+success:
+ mov r5, #128 /* 0x80 */
+ b done
+
+done:
+ bkpt #0
+
+ .end
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_io.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_io.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_io.s
new file mode 100755
index 0000000..797981c
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/armv7m_io.s
@@ -0,0 +1,60 @@
+/***************************************************************************
+ * Copyright (C) 2013 by Henrik Nilsson *
+ * henrik.nilsson@bytequest.se *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+ .text
+ .syntax unified
+ .arch armv7-m
+ .thumb
+ .thumb_func
+
+ .align 4
+
+/* Inputs:
+ * r0 buffer address
+ * r1 NAND data address (byte wide)
+ * r2 buffer length
+ */
+read:
+ ldrb r3, [r1]
+ strb r3, [r0], #1
+ subs r2, r2, #1
+ bne read
+
+done_read:
+ bkpt #0
+
+ .align 4
+
+/* Inputs:
+ * r0 NAND data address (byte wide)
+ * r1 buffer address
+ * r2 buffer length
+ */
+write:
+ ldrb r3, [r1], #1
+ strb r3, [r0]
+ subs r2, r2, #1
+ bne write
+
+done_write:
+ bkpt #0
+
+ .end
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script
new file mode 100755
index 0000000..85450c1
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ocl_flash.script
@@ -0,0 +1,4 @@
+soft_reset_halt
+load_image at91sam7x_ocl.bin 0x200000
+resume 0x200000
+flash probe 0
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
new file mode 100755
index 0000000..ea06931
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/at91sam7x_ram.ld
@@ -0,0 +1,132 @@
+/****************************************************************************
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* SUCH DAMAGE.
+*
+****************************************************************************
+*
+* History:
+*
+* 30.03.06 mifi First Version
+****************************************************************************/
+
+
+ENTRY(ResetHandler)
+SEARCH_DIR(.)
+
+/*
+ * Define stack size here
+ */
+FIQ_STACK_SIZE = 0x0100;
+IRQ_STACK_SIZE = 0x0100;
+ABT_STACK_SIZE = 0x0100;
+UND_STACK_SIZE = 0x0100;
+SVC_STACK_SIZE = 0x0100;
+
+
+MEMORY
+{
+ ram : org = 0x00200000, len = 64k
+}
+
+/*
+ * Do not change the next code
+ */
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors);
+ . = ALIGN(4);
+ *(.init);
+ . = ALIGN(4);
+ *(.text);
+ . = ALIGN(4);
+ *(.rodata);
+ . = ALIGN(4);
+ *(.rodata*);
+ . = ALIGN(4);
+ *(.glue_7t);
+ . = ALIGN(4);
+ *(.glue_7);
+ . = ALIGN(4);
+ etext = .;
+ } > ram
+
+ .data :
+ {
+ PROVIDE (__data_start = .);
+ *(.data)
+ . = ALIGN(4);
+ edata = .;
+ _edata = .;
+ PROVIDE (__data_end = .);
+ } > ram
+
+ .bss :
+ {
+ PROVIDE (__bss_start = .);
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE (__bss_end = .);
+
+ . = ALIGN(256);
+
+ PROVIDE (__stack_start = .);
+
+ PROVIDE (__stack_fiq_start = .);
+ . += FIQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_fiq_end = .);
+
+ PROVIDE (__stack_irq_start = .);
+ . += IRQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_irq_end = .);
+
+ PROVIDE (__stack_abt_start = .);
+ . += ABT_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_abt_end = .);
+
+ PROVIDE (__stack_und_start = .);
+ . += UND_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_und_end = .);
+
+ PROVIDE (__stack_svc_start = .);
+ . += SVC_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_svc_end = .);
+ PROVIDE (__stack_end = .);
+ PROVIDE (__heap_start = .);
+ } > ram
+
+}
+/*** EOF ***/
+
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/crt.s
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/crt.s b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/crt.s
new file mode 100755
index 0000000..2e434bb
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/contrib/loaders/flash/at91sam7x/crt.s
@@ -0,0 +1,223 @@
+/****************************************************************************
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* SUCH DAMAGE.
+*
+****************************************************************************
+*
+* History:
+*
+* 18.12.06 mifi First Version
+* The hardware initialization is based on the startup file
+* crtat91sam7x256_rom.S from NutOS 4.2.1.
+* Therefore partial copyright by egnite Software GmbH.
+****************************************************************************/
+
+/*
+ * Some defines for the program status registers
+ */
+ ARM_MODE_USER = 0x10 /* Normal User Mode */
+ ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
+ ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
+ ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
+ ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
+ ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
+ ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
+ ARM_MODE_MASK = 0x1F
+
+ I_BIT = 0x80 /* disable IRQ when I bit is set */
+ F_BIT = 0x40 /* disable IRQ when I bit is set */
+
+/*
+ * Register Base Address
+ */
+ AIC_BASE = 0xFFFFF000
+ AIC_EOICR_OFF = 0x130
+ AIC_IDCR_OFF = 0x124
+
+ RSTC_MR = 0xFFFFFD08
+ RSTC_KEY = 0xA5000000
+ RSTC_URSTEN = 0x00000001
+
+ WDT_BASE = 0xFFFFFD40
+ WDT_MR_OFF = 0x00000004
+ WDT_WDDIS = 0x00008000
+
+ MC_BASE = 0xFFFFFF00
+ MC_FMR_OFF = 0x00000060
+ MC_FWS_1FWS = 0x00480100
+
+ .section .vectors,"ax"
+ .code 32
+
+/****************************************************************************/
+/* Vector table and reset entry */
+/****************************************************************************/
+_vectors:
+ ldr pc, ResetAddr /* Reset */
+ ldr pc, UndefAddr /* Undefined instruction */
+ ldr pc, SWIAddr /* Software interrupt */
+ ldr pc, PAbortAddr /* Prefetch abort */
+ ldr pc, DAbortAddr /* Data abort */
+ ldr pc, ReservedAddr /* Reserved */
+ ldr pc, IRQAddr /* IRQ interrupt */
+ ldr pc, FIQAddr /* FIQ interrupt */
+
+
+ResetAddr: .word ResetHandler
+UndefAddr: .word UndefHandler
+SWIAddr: .word SWIHandler
+PAbortAddr: .word PAbortHandler
+DAbortAddr: .word DAbortHandler
+ReservedAddr: .word 0
+IRQAddr: .word IRQHandler
+FIQAddr: .word FIQHandler
+
+ .ltorg
+
+ .section .init, "ax"
+ .code 32
+
+ .global ResetHandler
+ .global ExitFunction
+ .extern main
+/****************************************************************************/
+/* Reset handler */
+/****************************************************************************/
+ResetHandler:
+ /*
+ * The watchdog is enabled after processor reset. Disable it.
+ */
+ ldr r1, =WDT_BASE
+ ldr r0, =WDT_WDDIS
+ str r0, [r1, #WDT_MR_OFF]
+
+
+ /*
+ * Enable user reset: assertion length programmed to 1ms
+ */
+ ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
+ ldr r1, =RSTC_MR
+ str r0, [r1, #0]
+
+
+ /*
+ * Use 2 cycles for flash access.
+ */
+ ldr r1, =MC_BASE
+ ldr r0, =MC_FWS_1FWS
+ str r0, [r1, #MC_FMR_OFF]
+
+
+ /*
+ * Disable all interrupts. Useful for debugging w/o target reset.
+ */
+ ldr r1, =AIC_BASE
+ mvn r0, #0
+ str r0, [r1, #AIC_EOICR_OFF]
+ str r0, [r1, #AIC_IDCR_OFF]
+
+
+ /*
+ * Setup a stack for each mode
+ */
+ msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
+ ldr sp, =__stack_und_end
+
+ msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
+ ldr sp, =__stack_abt_end
+
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
+ ldr sp, =__stack_fiq_end
+
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
+ ldr sp, =__stack_irq_end
+
+ msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
+ ldr sp, =__stack_svc_end
+
+
+ /*
+ * Clear .bss section
+ */
+ ldr r1, =__bss_start
+ ldr r2, =__bss_end
+ ldr r3, =0
+bss_clear_loop:
+ cmp r1, r2
+ strne r3, [r1], #+4
+ bne bss_clear_loop
+
+
+ /*
+ * Jump to main
+ */
+ mrs r0, cpsr
+ bic r0, r0, #I_BIT | F_BIT /* Enable FIQ and IRQ interrupt */
+ msr cpsr, r0
+
+ mov r0, #0 /* No arguments */
+ mov r1, #0 /* No arguments */
+ ldr r2, =main
+ mov lr, pc
+ bx r2 /* And jump... */
+
+ExitFunction:
+ nop
+ nop
+ nop
+ b ExitFunction
+
+
+/****************************************************************************/
+/* Default interrupt handler */
+/****************************************************************************/
+
+UndefHandler:
+ b UndefHandler
+
+SWIHandler:
+ b SWIHandler
+
+PAbortHandler:
+ b PAbortHandler
+
+DAbortHandler:
+ b DAbortHandler
+
+IRQHandler:
+ b IRQHandler
+
+FIQHandler:
+ b FIQHandler
+
+ .weak ExitFunction
+ .weak UndefHandler, PAbortHandler, DAbortHandler
+ .weak IRQHandler, FIQHandler
+
+ .ltorg
+/*** EOF ***/