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Posted to commits@nuttx.apache.org by pk...@apache.org on 2022/04/03 20:20:08 UTC
[incubator-nuttx] branch master updated (e9648d8a73 -> 747da36eae)
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from e9648d8a73 net:fix coverity warning
new e3926ecb16 stm32u5: stm32_stdclockconfig fixes
new 9d07559906 b-u585i-iot02a: Fix stdclock initialization
new 747da36eae b-u585i-iot02a:nsh: Drop TrustedFirmware-M dependency
The 3 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h | 49 ++++
arch/arm/src/stm32u5/stm32u585xx_rcc.c | 293 +++++++--------------
boards/arm/stm32u5/b-u585i-iot02a/README.txt | 7 +-
.../stm32u5/b-u585i-iot02a/configs/nsh/defconfig | 3 +-
boards/arm/stm32u5/b-u585i-iot02a/include/board.h | 77 ++----
.../arm/stm32u5/b-u585i-iot02a/scripts/Make.defs | 2 +-
.../b-u585i-iot02a}/scripts/flash.ld | 15 +-
7 files changed, 182 insertions(+), 264 deletions(-)
copy boards/arm/{tiva/launchxl-cc1312r1 => stm32u5/b-u585i-iot02a}/scripts/flash.ld (84%)
[incubator-nuttx] 02/03: b-u585i-iot02a: Fix stdclock initialization
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 9d075599063a2cdb493b977d553c4782db3e74b3
Author: Michael Jung <mi...@secore.ly>
AuthorDate: Sun Apr 3 11:58:00 2022 +0200
b-u585i-iot02a: Fix stdclock initialization
Correct the respective defines to initialize the B-U585I-IOT02A clock
tree correctly by means of stm32_stdclockconfig().
---
boards/arm/stm32u5/b-u585i-iot02a/include/board.h | 77 ++++++++---------------
1 file changed, 27 insertions(+), 50 deletions(-)
diff --git a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h
index 81a6972498..3882eb0b48 100644
--- a/boards/arm/stm32u5/b-u585i-iot02a/include/board.h
+++ b/boards/arm/stm32u5/b-u585i-iot02a/include/board.h
@@ -43,14 +43,14 @@
*
* System Clock source : PLL (MSIS)
* SYSCLK(Hz) : 160000000 Determined by PLL configuration
- * HCLK(Hz) : 160000000 (STM32_RCC_CFGR_HPRE) (Max 160MHz)
- * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 160MHz)
- * APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 160MHz)
- * APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 160MHz)
- * APB3 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 160MHz)
+ * HCLK(Hz) : 160000000
+ * AHB Prescaler : 1 (STM32_RCC_CFGR2_HPRE) (160MHz)
+ * APB1 Prescaler : 1 (STM32_RCC_CFGR2_PPRE1) (160MHz)
+ * APB2 Prescaler : 1 (STM32_RCC_CFGR2_PPRE2) (160MHz)
+ * APB3 Prescaler : 1 (STM32_RCC_CFGR3_PPRE3) (160MHz)
* MSIS Frequency(Hz) : 4000000 (nominal)
* MSIK Frequency(Hz) : 4000000 (nominal)
- * PLL_MBOOST : 1
+ * PLL_MBOOST : 1 (Embedded power distribution booster)
* PLLM : 1 (STM32_PLLCFG_PLLM)
* PLLN : 80 (STM32_PLLCFG_PLLN)
* PLLP : 2 (STM32_PLLCFG_PLLP)
@@ -70,63 +70,35 @@
#define STM32_LSI_FREQUENCY 32000
#define STM32_LSE_FREQUENCY 32768
-#define STM32_BOARD_USEMSI 1
-#define STM32_BOARD_MSIRANGE RCC_CR_MSIRANGE_4M
+#define STM32_BOARD_USEMSIS 1
+#define STM32_BOARD_MSISRANGE RCC_ICSCR1_MSISRANGE_4MHZ
+#define STM32_BOARD_MSIKRANGE RCC_ICSCR1_MSIKRANGE_4MHZ
-/* prescaler common to all PLL inputs */
+/* PLL1 config; we use this to generate our system clock */
-#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(1)
-
-/* 'main' PLL config; we use this to generate our system clock */
-
-#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(55)
-#define STM32_PLLCFG_PLLP 0
-#undef STM32_PLLCFG_PLLP_ENABLED
-#define STM32_PLLCFG_PLLQ 0
-#undef STM32_PLLCFG_PLLQ_ENABLED
-#define STM32_PLLCFG_PLLR RCC_PLLCFG_PLLR_2
-#define STM32_PLLCFG_PLLR_ENABLED
-
-/* 'SAIPLL1' is not used in this application */
-
-#define STM32_PLLSAI1CFG_PLLN RCC_PLLSAI1CFG_PLLN(24)
-#define STM32_PLLSAI1CFG_PLLP 0
-#undef STM32_PLLSAI1CFG_PLLP_ENABLED
-#define STM32_PLLSAI1CFG_PLLQ 0
-#undef STM32_PLLSAI1CFG_PLLQ_ENABLED
-#define STM32_PLLSAI1CFG_PLLR 0
-#undef STM32_PLLSAI1CFG_PLLR_ENABLED
-
-/* 'SAIPLL2' is not used in this application */
-
-#define STM32_PLLSAI2CFG_PLLN RCC_PLLSAI2CFG_PLLN(8)
-#define STM32_PLLSAI2CFG_PLLP 0
-#undef STM32_PLLSAI2CFG_PLLP_ENABLED
-#define STM32_PLLSAI2CFG_PLLR 0
-#undef STM32_PLLSAI2CFG_PLLR_ENABLED
+#define STM32_RCC_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(1)
+#define STM32_RCC_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(80)
+#define STM32_RCC_PLL1DIVR_PLL1P 0
+#undef STM32_RCC_PLL1CFGR_PLL1P_ENABLED
+#define STM32_RCC_PLL1DIVR_PLL1Q 0
+#undef STM32_RCC_PLL1CFGR_PLL1Q_ENABLED
+#define STM32_RCC_PLL1DIVR_PLL1R RCC_PLL1DIVR_PLL1R(2)
+#define STM32_RCC_PLL1CFGR_PLL1R_ENABLED
#define STM32_SYSCLK_FREQUENCY 160000000ul
-/* Enable CLK48; get it from HSI48 */
-
-#if defined(CONFIG_STM32U5_USBFS) || defined(CONFIG_STM32U5_RNG)
-# define STM32_USE_CLK48 1
-# define STM32_CLK48_SEL RCC_CCIPR_CLK48SEL_HSI48
-# define STM32_HSI48_SYNCSRC SYNCSRC_NONE
-#endif
-
-/* Enable LSE (for the RTC and for MSI autotrimming) */
+/* Enable LSE (for the RTC and for MSIS autotrimming) */
#define STM32_USE_LSE 1
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
-#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
+#define STM32_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
/* Configure the APB1 prescaler */
-#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
+#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK /* PCLK1 = HCLK / 1 */
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
@@ -138,13 +110,18 @@
/* Configure the APB2 prescaler */
-#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
+#define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK /* PCLK2 = HCLK / 1 */
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
+/* Configure the APB3 prescaler */
+
+#define STM32_RCC_CFGR3_PPRE3 RCC_CFGR3_PPRE3_HCLK /* PCLK3 = HCLK / 1 */
+#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
+
/* The timer clock frequencies are automatically defined by hardware. If the
* APB prescaler equals 1, the timer clock frequencies are set to the same
* frequency as that of the APB domain. Otherwise they are set to twice.
[incubator-nuttx] 01/03: stm32u5: stm32_stdclockconfig fixes
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit e3926ecb16a5a777315782bab362fa0cab0dda55
Author: Michael Jung <mi...@secore.ly>
AuthorDate: Sun Apr 3 11:55:00 2022 +0200
stm32u5: stm32_stdclockconfig fixes
Fix stm32_stdclockconfig for stm32u585xx to the extend that the
B-U585I-IOT02A board's clock tree can be configured. This board uses
the MSIS as PLL1's input clock and the LSE to autotrim the MSIS.
---
arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h | 49 ++++
arch/arm/src/stm32u5/stm32u585xx_rcc.c | 293 ++++++++----------------
2 files changed, 142 insertions(+), 200 deletions(-)
diff --git a/arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h b/arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h
index 7f7c200ad1..d299821624 100644
--- a/arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h
+++ b/arch/arm/src/stm32u5/hardware/stm32u585xx_rcc.h
@@ -278,6 +278,55 @@
# define RCC_CFGR1_MCOPRE_DIV8 (3 << RCC_CFGR1_MCOPRE_SHIFT) /* 011: division by 8 */
# define RCC_CFGR1_MCOPRE_DIV16 (4 << RCC_CFGR1_MCOPRE_SHIFT) /* 100: division by 16 */
+/* RCC clock configuration register 2 */
+
+#define RCC_CFGR2_HPRE_SHIFT (0) /* Bits 0-3: AHB prescaler */
+#define RCC_CFGR2_HPRE_MASK (0xf << RCC_CFGR2_HPRE_SHIFT)
+# define RCC_CFGR2_HPRE_SYSCLK ( 0 << RCC_CFGR2_HPRE_SHIFT) /* 0xxx: SYSCLK not divided */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV2 ( 8 << RCC_CFGR2_HPRE_SHIFT) /* 1000: SYSCLK divided by 2 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV4 ( 9 << RCC_CFGR2_HPRE_SHIFT) /* 1001: SYSCLK divided by 4 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV8 (10 << RCC_CFGR2_HPRE_SHIFT) /* 1010: SYSCLK divided by 8 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV16 (11 << RCC_CFGR2_HPRE_SHIFT) /* 1011: SYSCLK divided by 16 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV64 (12 << RCC_CFGR2_HPRE_SHIFT) /* 1100: SYSCLK divided by 64 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV128 (13 << RCC_CFGR2_HPRE_SHIFT) /* 1101: SYSCLK divided by 128 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV256 (14 << RCC_CFGR2_HPRE_SHIFT) /* 1110: SYSCLK divided by 256 */
+# define RCC_CFGR2_HPRE_SYSCLK_DIV512 (15 << RCC_CFGR2_HPRE_SHIFT) /* 1111: SYSCLK divided by 512 */
+
+#define RCC_CFGR2_PPRE1_SHIFT (4) /* Bits 4-6: APB1 prescaler */
+#define RCC_CFGR2_PPRE1_MASK (0x7 << RCC_CFGR2_HPRE_SHIFT)
+# define RCC_CFGR2_PPRE1_HCLK (0 << RCC_CFGR2_HPRE_SHIFT) /* 0xxx: HCLK not divided */
+# define RCC_CFGR2_PPRE1_HCLK_DIV2 (4 << RCC_CFGR2_HPRE_SHIFT) /* 1000: HCLK divided by 2 */
+# define RCC_CFGR2_PPRE1_HCLK_DIV4 (5 << RCC_CFGR2_HPRE_SHIFT) /* 1001: HCLK divided by 4 */
+# define RCC_CFGR2_PPRE1_HCLK_DIV8 (6 << RCC_CFGR2_HPRE_SHIFT) /* 1010: HCLK divided by 8 */
+# define RCC_CFGR2_PPRE1_HCLK_DIV16 (7 << RCC_CFGR2_HPRE_SHIFT) /* 1011: HCLK divided by 16 */
+
+#define RCC_CFGR2_PPRE2_SHIFT (8) /* Bits 8-10: APB2 prescaler */
+#define RCC_CFGR2_PPRE2_MASK (0x7 << RCC_CFGR2_PPRE2_SHIFT)
+# define RCC_CFGR2_PPRE2_HCLK (0 << RCC_CFGR2_PPRE2_SHIFT) /* 0xxx: HCLK not divided */
+# define RCC_CFGR2_PPRE2_HCLK_DIV2 (4 << RCC_CFGR2_PPRE2_SHIFT) /* 1000: HCLK divided by 2 */
+# define RCC_CFGR2_PPRE2_HCLK_DIV4 (5 << RCC_CFGR2_PPRE2_SHIFT) /* 1001: HCLK divided by 4 */
+# define RCC_CFGR2_PPRE2_HCLK_DIV8 (6 << RCC_CFGR2_PPRE2_SHIFT) /* 1010: HCLK divided by 8 */
+# define RCC_CFGR2_PPRE2_HCLK_DIV16 (7 << RCC_CFGR2_PPRE2_SHIFT) /* 1011: HCLK divided by 16 */
+
+#define RCC_CFGR2_AHB1DIS (1 << 16) /* Bit 16: AHB1 clock disable */
+#define RCC_CFGR2_AHB2DIS1 (1 << 17) /* Bit 17: AHB2_1 clock disable */
+#define RCC_CFGR2_AHB2DIS2 (1 << 18) /* Bit 18: AHB2_2 clock disable */
+#define RCC_CFGR2_APB1DIS (1 << 19) /* Bit 19: APB1 clock disable */
+#define RCC_CFGR2_APB2DIS (1 << 20) /* Bit 20: APB2 clock disable */
+
+/* RCC clock configuration register 3 */
+
+#define RCC_CFGR3_PPRE3_SHIFT (4) /* Bits 4-6: APB3 prescaler */
+#define RCC_CFGR3_PPRE3_MASK (0x7 << RCC_CFGR3_PPRE3_SHIFT)
+# define RCC_CFGR3_PPRE3_HCLK (0 << RCC_CFGR3_PPRE3_SHIFT) /* 0xxx: HCLK not divided */
+# define RCC_CFGR3_PPRE3_HCLK_DIV2 (4 << RCC_CFGR3_PPRE3_SHIFT) /* 1000: HCLK divided by 2 */
+# define RCC_CFGR3_PPRE3_HCLK_DIV4 (5 << RCC_CFGR3_PPRE3_SHIFT) /* 1001: HCLK divided by 4 */
+# define RCC_CFGR3_PPRE3_HCLK_DIV8 (6 << RCC_CFGR3_PPRE3_SHIFT) /* 1010: HCLK divided by 8 */
+# define RCC_CFGR3_PPRE3_HCLK_DIV16 (7 << RCC_CFGR3_PPRE3_SHIFT) /* 1011: HCLK divided by 16 */
+
+#define RCC_CFGR3_AHB3DIS (1 << 16) /* Bit 16: AHB3 clock disable */
+#define RCC_CFGR3_APB3DIS (1 << 17) /* Bit 17: APB3 clock disable */
+
/* RCC PLL1 configuration register */
#define RCC_PLL1CFGR_PLL1SRC_SHIFT (0) /* Bits 0-1: PLL1 entry clock source */
diff --git a/arch/arm/src/stm32u5/stm32u585xx_rcc.c b/arch/arm/src/stm32u5/stm32u585xx_rcc.c
index 68a25ceec2..ea988b07e0 100644
--- a/arch/arm/src/stm32u5/stm32u585xx_rcc.c
+++ b/arch/arm/src/stm32u5/stm32u585xx_rcc.c
@@ -45,7 +45,7 @@
/* Same for HSI and MSI */
#define HSIRDY_TIMEOUT HSERDY_TIMEOUT
-#define MSIRDY_TIMEOUT HSERDY_TIMEOUT
+#define MSISRDY_TIMEOUT HSERDY_TIMEOUT
/* HSE divisor to yield ~1MHz RTC clock */
@@ -595,42 +595,15 @@ void stm32_stdclockconfig(void)
uint32_t regval;
volatile int32_t timeout;
- /* Enable Internal Multi-Speed System (MSIS) and Kernel (MSIK) Clock */
+#if defined(STM32_BOARD_USEMSIS)
+ /* Enable Internal Multi-Speed Clock (MSIS) */
-#if defined(STM32_BOARD_USEHSI) || defined(STM32_I2C_USE_HSI16)
- /* Enable Internal High-Speed Clock (HSI) */
+ /* Wait until the MSIS is either off or ready (or until timeout elapses) */
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_HSION; /* Enable HSI */
- putreg32(regval, STM32_RCC_CR);
-
- /* Wait until the HSI is ready (or until a timeout elapsed) */
-
- for (timeout = HSIRDY_TIMEOUT; timeout > 0; timeout--)
- {
- /* Check if the HSIRDY flag is the set in the CR */
-
- if ((getreg32(STM32_RCC_CR) & RCC_CR_HSIRDY) != 0)
- {
- /* If so, then break-out with timeout > 0 */
-
- break;
- }
- }
-#endif
-
-#if defined(STM32_BOARD_USEHSI)
- /* Already set above */
-
-#elif defined(STM32_BOARD_USEMSI)
- /* Enable Internal Multi-Speed Clock (MSI) */
-
- /* Wait until the MSI is either off or ready (or until a timeout elapsed) */
-
- for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+ for (timeout = MSISRDY_TIMEOUT; timeout > 0; timeout--)
{
if ((regval = getreg32(STM32_RCC_CR)),
- (regval & RCC_CR_MSIRDY) || ~(regval & RCC_CR_MSION))
+ (regval & RCC_CR_MSISRDY) || ~(regval & RCC_CR_MSISON))
{
/* If so, then break-out with timeout > 0 */
@@ -638,19 +611,24 @@ void stm32_stdclockconfig(void)
}
}
- /* setting MSIRANGE */
+ /* setting MSISRANGE */
+
+ putreg32((STM32_BOARD_MSISRANGE |
+ STM32_BOARD_MSIKRANGE |
+ RCC_ICSCR1_MSIRGSEL_ICSCR1),
+ STM32_RCC_ICSCR1);
regval = getreg32(STM32_RCC_CR);
- regval |= (STM32_BOARD_MSIRANGE | RCC_CR_MSION); /* Enable MSI and frequency */
+ regval |= RCC_CR_MSISON;
putreg32(regval, STM32_RCC_CR);
/* Wait until the MSI is ready (or until a timeout elapsed) */
- for (timeout = MSIRDY_TIMEOUT; timeout > 0; timeout--)
+ for (timeout = MSISRDY_TIMEOUT; timeout > 0; timeout--)
{
/* Check if the MSIRDY flag is the set in the CR */
- if ((getreg32(STM32_RCC_CR) & RCC_CR_MSIRDY) != 0)
+ if ((getreg32(STM32_RCC_CR) & RCC_CR_MSISRDY) != 0)
{
/* If so, then break-out with timeout > 0 */
@@ -658,29 +636,9 @@ void stm32_stdclockconfig(void)
}
}
-#elif defined(STM32_BOARD_USEHSE)
- /* Enable External High-Speed Clock (HSE) */
-
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_HSEON; /* Enable HSE */
- putreg32(regval, STM32_RCC_CR);
-
- /* Wait until the HSE is ready (or until a timeout elapsed) */
-
- for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
- {
- /* Check if the HSERDY flag is the set in the CR */
-
- if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
- {
- /* If so, then break-out with timeout > 0 */
-
- break;
- }
- }
#else
-# error stm32_stdclockconfig(), must have one of STM32_BOARD_USEHSI, STM32_BOARD_USEMSI, STM32_BOARD_USEHSE defined
+# error stm32_stdclockconfig() currently only supports STM32_BOARD_USEMSIS
#endif
@@ -699,195 +657,130 @@ void stm32_stdclockconfig(void)
stm32_pwr_enableclk(true);
+ /* Generate an EPOD booster clock frequency of 4 MHz. FIXME: This must
+ * be computed based on the MSIS clock to yield a frequency between 4
+ * and 16 MHz. Also, the EPOD booster clock is required only for
+ * SYSCLK frequencies greater than 55MHz.
+ */
+
+ regval = getreg32(STM32_RCC_PLL1CFGR);
+ regval &= ~(RCC_PLL1CFGR_PLL1SRC_MASK | RCC_PLL1CFGR_PLL1MBOOST_MASK);
+ regval |= RCC_PLL1CFGR_PLL1SRC_MSIS | RCC_PLL1CFGR_PLL1MBOOST_DIV_1;
+ putreg32(regval, STM32_RCC_PLL1CFGR);
+
/* Select correct main regulator range */
- regval = getreg32(STM32_PWR_CR1);
- regval &= ~PWR_CR1_VOS_MASK;
+ regval = getreg32(STM32_PWR_VOSR);
+ regval &= ~PWR_VOSR_VOS_MASK;
- if (STM32_SYSCLK_FREQUENCY > 80000000)
+ if (STM32_SYSCLK_FREQUENCY > 110000000)
+ {
+ regval |= PWR_VOSR_VOS_RANGE1;
+ }
+ else if (STM32_SYSCLK_FREQUENCY > 55000000)
{
- regval |= PWR_CR1_VOS_RANGE0;
+ regval |= PWR_VOSR_VOS_RANGE2;
}
- else if (STM32_SYSCLK_FREQUENCY > 26000000)
+ else if (STM32_SYSCLK_FREQUENCY > 25000000)
{
- regval |= PWR_CR1_VOS_RANGE1;
+ regval |= PWR_VOSR_VOS_RANGE3;
}
else
{
- regval |= PWR_CR1_VOS_RANGE0;
+ regval |= PWR_VOSR_VOS_RANGE4;
}
- putreg32(regval, STM32_PWR_CR1);
+ regval |= PWR_VOSR_BOOSTEN;
+
+ putreg32(regval, STM32_PWR_VOSR);
/* Wait for voltage regulator to stabilize */
- while (getreg32(STM32_PWR_SR2) & PWR_SR2_VOSF)
+ while ((getreg32(STM32_PWR_VOSR) &
+ (PWR_VOSR_VOSRDY | PWR_VOSR_BOOSTRDY)) !=
+ (PWR_VOSR_VOSRDY | PWR_VOSR_BOOSTRDY))
{
}
- /* Set the HCLK source/divider */
-
- regval = getreg32(STM32_RCC_CFGR);
- regval &= ~RCC_CFGR_HPRE_MASK;
- regval |= STM32_RCC_CFGR_HPRE;
- putreg32(regval, STM32_RCC_CFGR);
-
- /* Set the PCLK2 divider */
-
- regval = getreg32(STM32_RCC_CFGR);
- regval &= ~RCC_CFGR_PPRE2_MASK;
- regval |= STM32_RCC_CFGR_PPRE2;
- putreg32(regval, STM32_RCC_CFGR);
-
- /* Set the PCLK1 divider */
-
- regval = getreg32(STM32_RCC_CFGR);
- regval &= ~RCC_CFGR_PPRE1_MASK;
- regval |= STM32_RCC_CFGR_PPRE1;
- putreg32(regval, STM32_RCC_CFGR);
-
-#ifdef CONFIG_STM32U5_RTC_HSECLOCK
- /* Set the RTC clock divisor */
-
- regval = getreg32(STM32_RCC_CFGR);
- regval &= ~RCC_CFGR_RTCPRE_MASK;
- regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
- putreg32(regval, STM32_RCC_CFGR);
-#endif
-
- /* Set the PLL source and main divider */
-
- regval = getreg32(STM32_RCC_PLLCFG);
-
- /* Configure Main PLL */
-
- /* Set the PLL dividers and multipliers to configure the main PLL */
-
- regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |
- STM32_PLLCFG_PLLP | STM32_PLLCFG_PLLQ |
- STM32_PLLCFG_PLLR);
-
-#ifdef STM32_PLLCFG_PLLP_ENABLED
- regval |= RCC_PLLCFG_PLLPEN;
-#endif
-#ifdef STM32_PLLCFG_PLLQ_ENABLED
- regval |= RCC_PLLCFG_PLLQEN;
-#endif
-#ifdef STM32_PLLCFG_PLLR_ENABLED
- regval |= RCC_PLLCFG_PLLREN;
-#endif
-
- /* XXX The choice of clock source to PLL (all three) is independent
- * of the sys clock source choice, review the STM32_BOARD_USEHSI
- * name; probably split it into two, one for PLL source and one
- * for sys clock source.
+ /* Configure 4 wait states and prefetch for FLASH access. FIXME: Flash
+ * wait states must be computed based on SYSCLK frequency.
*/
-#ifdef STM32_BOARD_USEHSI
- regval |= RCC_PLLCFG_PLLSRC_HSI16;
-#elif defined(STM32_BOARD_USEMSI)
- regval |= RCC_PLLCFG_PLLSRC_MSI;
-#else /* if STM32_BOARD_USEHSE */
- regval |= RCC_PLLCFG_PLLSRC_HSE;
-#endif
-
- putreg32(regval, STM32_RCC_PLLCFG);
-
- /* Enable the main PLL */
-
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_PLLON;
- putreg32(regval, STM32_RCC_CR);
+ regval = FLASH_ACR_LATENCY_4 | FLASH_ACR_PRFTEN;
+ putreg32(regval, STM32_FLASH_ACR);
- /* Wait until the PLL is ready */
+ /* Set the HCLK, PCLK1 and PCLK2 dividers */
- while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0)
- {
- }
+ regval = getreg32(STM32_RCC_CFGR2);
+ regval &= ~(RCC_CFGR2_HPRE_MASK |
+ RCC_CFGR2_PPRE1_MASK |
+ RCC_CFGR2_PPRE2_MASK);
+ regval |= STM32_RCC_CFGR2_HPRE |
+ STM32_RCC_CFGR2_PPRE1 |
+ STM32_RCC_CFGR2_PPRE2;
+ putreg32(regval, STM32_RCC_CFGR2);
-#ifdef CONFIG_STM32U5_SAI1PLL
- /* Configure SAI1 PLL */
+ /* Set the PCLK3 divider */
- regval = getreg32(STM32_RCC_PLLSAI1CFG);
+ regval = getreg32(STM32_RCC_CFGR3);
+ regval &= ~RCC_CFGR3_PPRE3_MASK;
+ regval |= STM32_RCC_CFGR3_PPRE3;
+ putreg32(regval, STM32_RCC_CFGR3);
- /* Set the PLL dividers and multipliers to configure the SAI1 PLL */
+#ifdef CONFIG_STM32U5_RTC_HSECLOCK
- regval = (STM32_PLLSAI1CFG_PLLN | STM32_PLLSAI1CFG_PLLP
- | STM32_PLLSAI1CFG_PLLQ | STM32_PLLSAI1CFG_PLLR);
+# error stm32_stdclockconfig() currently doesn not support CONFIG_STM32U5_RTC_HSECLOCK
-#ifdef STM32_PLLSAI1CFG_PLLP_ENABLED
- regval |= RCC_PLLSAI1CFG_PLLPEN;
-#endif
-#ifdef STM32_PLLSAI1CFG_PLLQ_ENABLED
- regval |= RCC_PLLSAI1CFG_PLLQEN;
-#endif
-#ifdef STM32_PLLSAI1CFG_PLLR_ENABLED
- regval |= RCC_PLLSAI1CFG_PLLREN;
#endif
- putreg32(regval, STM32_RCC_PLLSAI1CFG);
+ /* Set the PLL1 source, dividers and multipliers */
- /* Enable the SAI1 PLL */
+ regval = STM32_RCC_PLL1DIVR_PLL1N |
+ STM32_RCC_PLL1DIVR_PLL1P |
+ STM32_RCC_PLL1DIVR_PLL1Q |
+ STM32_RCC_PLL1DIVR_PLL1R;
- regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_PLLSAI1ON;
- putreg32(regval, STM32_RCC_CR);
+ putreg32(regval, STM32_RCC_PLL1DIVR);
- /* Wait until the PLL is ready */
-
- while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI1RDY) == 0)
- {
- }
+ regval = RCC_PLL1CFGR_PLL1SRC_MSIS |
+ RCC_PLL1CFGR_PLL1RGE_4_TO_8MHZ |
+ STM32_RCC_PLL1CFGR_PLL1M |
+ RCC_PLL1CFGR_PLL1MBOOST_DIV_1;
+#ifdef STM32_RCC_PLL1CFGR_PLL1P_ENABLED
+ regval |= RCC_PLL1CFGR_PLL1PEN;
#endif
-
-#ifdef CONFIG_STM32U5_SAI2PLL
- /* Configure SAI2 PLL */
-
- regval = getreg32(STM32_RCC_PLLSAI2CFG);
-
- /* Set the PLL dividers and multipliers to configure the SAI2 PLL */
-
- regval = (STM32_PLLSAI2CFG_PLLN | STM32_PLLSAI2CFG_PLLP |
- STM32_PLLSAI2CFG_PLLR);
-
-#ifdef STM32_PLLSAI2CFG_PLLP_ENABLED
- regval |= RCC_PLLSAI2CFG_PLLPEN;
+#ifdef STM32_RCC_PLL1CFGR_PLL1Q_ENABLED
+ regval |= RCC_PLL1CFGR_PLL1QEN;
#endif
-#ifdef STM32_PLLSAI2CFG_PLLR_ENABLED
- regval |= RCC_PLLSAI2CFG_PLLREN;
+#ifdef STM32_RCC_PLL1CFGR_PLL1R_ENABLED
+ regval |= RCC_PLL1CFGR_PLL1REN;
#endif
- putreg32(regval, STM32_RCC_PLLSAI2CFG);
+ putreg32(regval, STM32_RCC_PLL1CFGR);
- /* Enable the SAI2 PLL */
+ /* Enable PLL1 */
regval = getreg32(STM32_RCC_CR);
- regval |= RCC_CR_PLLSAI2ON;
+ regval |= RCC_CR_PLL1ON;
putreg32(regval, STM32_RCC_CR);
- /* Wait until the PLL is ready */
+ /* Wait until PLL1 is ready */
- while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLSAI2RDY) == 0)
+ while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0)
{
}
-#endif
-
- /* Enable FLASH 5 wait states */
-
- regval = FLASH_ACR_LATENCY_5;
- putreg32(regval, STM32_FLASH_ACR);
- /* Select the main PLL as system clock source */
+ /* Select the PLL1 as system clock source */
- regval = getreg32(STM32_RCC_CFGR);
- regval &= ~RCC_CFGR_SW_MASK;
- regval |= RCC_CFGR_SW_PLL;
- putreg32(regval, STM32_RCC_CFGR);
+ regval = getreg32(STM32_RCC_CFGR1);
+ regval &= ~RCC_CFGR1_SW_MASK;
+ regval |= RCC_CFGR1_SW_PLL;
+ putreg32(regval, STM32_RCC_CFGR1);
- /* Wait until the PLL source is used as the system clock source */
+ /* Wait until PLL1 source is used as the system clock source */
- while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) !=
- RCC_CFGR_SWS_PLL)
+ while ((getreg32(STM32_RCC_CFGR1) & RCC_CFGR1_SWS_MASK) !=
+ RCC_CFGR1_SWS_PLL)
{
}
[incubator-nuttx] 03/03: b-u585i-iot02a:nsh: Drop TrustedFirmware-M dependency
Posted by pk...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
pkarashchenko pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 747da36eaea14b78e189bb54fd546dea2882af17
Author: Michael Jung <mi...@secore.ly>
AuthorDate: Sun Apr 3 12:01:58 2022 +0200
b-u585i-iot02a:nsh: Drop TrustedFirmware-M dependency
Make the nsh defconfig for the b-u585i-iot02a run stand-alone (i.e. not
as a companion that relies on TF-M doing low-level board
initialization).
---
boards/arm/stm32u5/b-u585i-iot02a/README.txt | 7 +-
.../stm32u5/b-u585i-iot02a/configs/nsh/defconfig | 3 +-
.../arm/stm32u5/b-u585i-iot02a/scripts/Make.defs | 2 +-
boards/arm/stm32u5/b-u585i-iot02a/scripts/flash.ld | 103 +++++++++++++++++++++
4 files changed, 108 insertions(+), 7 deletions(-)
diff --git a/boards/arm/stm32u5/b-u585i-iot02a/README.txt b/boards/arm/stm32u5/b-u585i-iot02a/README.txt
index 8a3765951f..7b92118240 100644
--- a/boards/arm/stm32u5/b-u585i-iot02a/README.txt
+++ b/boards/arm/stm32u5/b-u585i-iot02a/README.txt
@@ -5,10 +5,6 @@ B-U585I-IOT02A README
B-U585I-IOT02A board. That board features the STM32U585AII6QU MCU with 2MiB
of Flash and 768KiB of SRAM.
- This port is a proof-of-concept to demonstrate running NuttX in the Non-
- Secure TrustZone domain as a companion to TrustedFirmware-M (TFM). Running
- NuttX on the B-U585I-IOT02A without TFM is currently not supported.
-
Contents
========
@@ -23,6 +19,9 @@ Status
basic NSH configuration works with Apache NuttX as the OS running in the
non-secure world.
+ 2022-04-03: The dependency on TrustedFirmware-M was dropped. I.e. the
+ b-u585i-iot02a:nsh configuration now runs standalone.
+
Clock Source
============
diff --git a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig
index 7a6f93ff28..33dffe75c8 100644
--- a/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig
+++ b/boards/arm/stm32u5/b-u585i-iot02a/configs/nsh/defconfig
@@ -5,13 +5,13 @@
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
# modifications.
#
+# CONFIG_ARCH_LEDS is not set
# CONFIG_NSH_ARGCAT is not set
# CONFIG_NSH_CMDPARMS is not set
# CONFIG_STANDARD_SERIAL is not set
CONFIG_ARCH="arm"
CONFIG_ARCH_BOARD="b-u585i-iot02a"
CONFIG_ARCH_BOARD_B_U585I_IOT02A=y
-CONFIG_ARCH_BOARD_STM32U5_CUSTOM_CLOCKCONFIG=y
CONFIG_ARCH_CHIP="stm32u5"
CONFIG_ARCH_CHIP_STM32U585AI=y
CONFIG_ARCH_CHIP_STM32U5=y
@@ -19,7 +19,6 @@ CONFIG_ARCH_INTERRUPTSTACK=2048
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_TRUSTZONE_NONSECURE=y
CONFIG_ARMV8M_LAZYFPU=y
-CONFIG_ARMV8M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARMV8M_USEBASEPRI=y
CONFIG_BOARD_LOOPSPERMSEC=4230
CONFIG_BUILTIN=y
diff --git a/boards/arm/stm32u5/b-u585i-iot02a/scripts/Make.defs b/boards/arm/stm32u5/b-u585i-iot02a/scripts/Make.defs
index db632f9d2a..39da14f7ca 100644
--- a/boards/arm/stm32u5/b-u585i-iot02a/scripts/Make.defs
+++ b/boards/arm/stm32u5/b-u585i-iot02a/scripts/Make.defs
@@ -22,7 +22,7 @@ include ${TOPDIR}/.config
include ${TOPDIR}/tools/Config.mk
include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs
-ARCHSCRIPT = $(BOARD_DIR)$(DELIM)scripts$(DELIM)tfm-ns.ld
+ARCHSCRIPT = $(BOARD_DIR)$(DELIM)scripts$(DELIM)flash.ld
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
ARCHOPTIMIZATION = -g
diff --git a/boards/arm/stm32u5/b-u585i-iot02a/scripts/flash.ld b/boards/arm/stm32u5/b-u585i-iot02a/scripts/flash.ld
new file mode 100644
index 0000000000..a211bc4f4b
--- /dev/null
+++ b/boards/arm/stm32u5/b-u585i-iot02a/scripts/flash.ld
@@ -0,0 +1,103 @@
+/****************************************************************************
+ * boards/arm/stm32u5/b-u585i-iot02a/scripts/flash.ld
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements. See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership. The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* The STM32Uxx has 2 MiB of FLASH beginning at address 0x0800:0000 and
+ * 192 KiB of SRAM beginning at address 0x2000:0000. When booting from
+ * FLASH, FLASH memory is aliased to address 0x0000:0000 where the code
+ * expects to begin execution by jumping to the entry point in the
+ * 0x0800:0000 address range.
+ */
+
+MEMORY
+{
+ flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
+ sram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+ .text : {
+ _stext = ABSOLUTE(.);
+ *(.vectors)
+ *(.text .text.*)
+ *(.fixup)
+ *(.gnu.warning)
+ *(.rodata .rodata.*)
+ *(.gnu.linkonce.t.*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.got)
+ *(.gcc_except_table)
+ *(.gnu.linkonce.r.*)
+ _etext = ABSOLUTE(.);
+ } > flash
+
+ .init_section : {
+ _sinit = ABSOLUTE(.);
+ *(.init_array .init_array.*)
+ _einit = ABSOLUTE(.);
+ } > flash
+
+ .ARM.extab : {
+ *(.ARM.extab*)
+ } > flash
+
+ __exidx_start = ABSOLUTE(.);
+ .ARM.exidx : {
+ *(.ARM.exidx*)
+ } > flash
+ __exidx_end = ABSOLUTE(.);
+
+ _eronly = ABSOLUTE(.);
+
+ .data : {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ CONSTRUCTORS
+ . = ALIGN(4);
+ _edata = ABSOLUTE(.);
+ } > sram AT > flash
+
+ .bss : {
+ _sbss = ABSOLUTE(.);
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ . = ALIGN(4);
+ _ebss = ABSOLUTE(.);
+ } > sram
+
+ /* Stabs debugging sections. */
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_info 0 : { *(.debug_info) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+ .debug_aranges 0 : { *(.debug_aranges) }
+}