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Posted to commits@nuttx.apache.org by GitBox <gi...@apache.org> on 2021/08/20 04:40:42 UTC
[GitHub] [incubator-nuttx] anchao opened a new pull request #4381: arch/riscv/assert: enhance the assert dump
anchao opened a new pull request #4381:
URL: https://github.com/apache/incubator-nuttx/pull/4381
## Summary
arch/riscv/assert: enhance the assert dump
enhance the assert dump to show the all tasks info including backtrace and registers
## Impact
assert dump
## Testing
```
[ 4.649000] [ EMERG] riscv_exception: PANIC!!! Exception = 00000005
[ 4.649000] [ EMERG] up_assert: Assertion failed at file:rv32im/riscv_exception.c line: 94 task: init
[ 4.649000] [ EMERG] riscv_dumpstate: Call Trace:
[ 4.649000] [ INFO] [BackTrace| 3|0]: 0x42020026 0x42007cbc 0x42005782 0x42000fe2 0x403801e2 0x403800e2 0x4200bdd8 0x4200989c
[ 4.649000] [ INFO] [BackTrace| 3|1]: 0x4200a636 0x42008e92 0x42008426 0x42008328 0x42005ad0 0x42001a56
[ 4.649000] [ EMERG] riscv_registerdump: EPC:4200bdd8
[ 4.649000] [ EMERG] riscv_registerdump: A0:ffffffff A1:00000010 A2:3fc9a95c A3:00000031 A4:00000009 A5:00000002 A6:00000001 A7:00000074
[ 4.649000] [ EMERG] riscv_registerdump: T0:7f7fffff T1:4200bd3a T2:ffffffff T3:0000006c T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc9a9b0 S1:3fca3eb0 S2:ffffffff S3:00000000 S4:00000001 S5:00000000 S6:00000000 S7:ffffffff
[ 4.649000] [ EMERG] riscv_registerdump: S8:3c102000 S9:3c102000 S10:3c10f000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc9a980 FP:3fc9a9b0 TP:00000000 RA:4200bd86
[ 4.649000] [ EMERG] riscv_dumpstate: sp: 3fc94b80
[ 4.649000] [ EMERG] riscv_dumpstate: IRQ stack:
[ 4.649000] [ EMERG] riscv_dumpstate: base: 3fc94600
[ 4.649000] [ EMERG] riscv_dumpstate: size: 00000600
[ 4.649000] [ EMERG] riscv_stackdump: 3fc94b80: 00000001 3fc9aa70 3c100824 0000005e 00004002 3c102000 3c102000 ffffffff
[ 4.649000] [ EMERG] riscv_stackdump: 3fc94ba0: 00000000 00000000 00000001 00000000 3fc93000 3fc9a8fc 3fc94bd0 42005782
[ 4.649000] [ EMERG] riscv_stackdump: 3fc94bc0: 0000000b 00000002 3fc94be0 42000fe2 deadbeef 3fca3eb0 3fc94c00 403801e2
[ 4.649000] [ EMERG] riscv_stackdump: 3fc94be0: deadbeef deadbeef deadbeef 00000000 ffffffff 3fca3eb0 4200bdd8 403800e2
[ 4.649000] [ EMERG] riscv_dumpstate: sp: 3fc94c00
[ 4.649000] [ EMERG] riscv_dumpstate: User stack:
[ 4.649000] [ EMERG] riscv_dumpstate: base: 3fc9a3c0
[ 4.649000] [ EMERG] riscv_dumpstate: size: 000007e0
[ 4.649000] [ EMERG] riscv_dumpstate: ERROR: Stack pointer is not within allocated stack
[ 4.649000] [ EMERG] riscv_stackdump: 3fc9a3c0: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef
...
[ 4.649000] [ EMERG] riscv_showtasks: Tasks status:
[ 4.649000] [ EMERG] riscv_taskdump: Idle Task: PID=0
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=580 of 976
[ 4.649000] [ INFO] [BackTrace| 0|0]: 0x4200787e 0x3fc94ff0
[ 4.649000] [ EMERG] riscv_registerdump: EPC:4200787e
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000032 A1:3c1008fa A2:3fc94fa8 A3:00000000 A4:00000101 A5:00000032 A6:00000001 A7:00000074
[ 4.649000] [ EMERG] riscv_registerdump: T0:0000002e T1:0000006a T2:000001ff T3:0000006c T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc94fc0 S1:3fc82fe4 S2:3fc83000 S3:3fc94000 S4:00000003 S5:3fc83100 S6:3fc94000 S7:3fcd7000
[ 4.649000] [ EMERG] riscv_registerdump: S8:3c100020 S9:00010020 S10:00000005 S11:3fcde3c4
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc94fb0 FP:3fc94fc0 TP:00000000 RA:420013cc
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: hpwork: PID=1
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=292 of 2016
[ 4.649000] [ INFO] [BackTrace| 1|0]: 0x420082ae 0x4200328c 0x42001ab4 0x42001a42
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc98718 A2:3fc8307c A3:00000002 A4:00000000 A5:00000000 A6:00000000 A7:00000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:4005890e T1:0000000f T2:00000000 T3:00000000 T4:00000000 T5:00000000 T6:00000000
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc991e0 S1:3fc98680 S2:00020000 S3:00000080 S4:00000000 S5:3fc991ec S6:3fc83000 S7:00000001
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000008 S9:00000000 S10:00000000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc991a0 FP:3fc991e0 TP:00000000 RA:42004332
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: lpwork: PID=2
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=788 of 2016
[ 4.649000] [ INFO] [BackTrace| 2|0]: 0x420082ae 0x4200486c 0x42004468 0x42003302 0x42001b38 0x42001a42
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc993c8 A2:3fca6708 A3:3fcbec84 A4:3fc98680 A5:00000000 A6:0000139f A7:3c1000a7
[ 4.649000] [ EMERG] riscv_registerdump: T0:df7ce2b4 T1:f423f000 T2:b2f9de92 T3:000000fd T4:04060008 T5:01000608 T6:604276a1
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc99e40 S1:3fc99330 S2:3fc99354 S3:00000080 S4:00000000 S5:3fc99e48 S6:000f423f S7:000011e7
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000008 S9:00000000 S10:00000000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc99e00 FP:3fc99e40 TP:00000000 RA:420042ea
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: init: PID=3
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=1780 of 2016
[ 4.649000] [ INFO] [BackTrace| 3|0]: 0x42020026 0x42007c0e 0x4201da2e 0x42007dba 0x42005782 0x42000fe2 0x403801e2 0x403800e2
[ 4.649000] [ INFO] [BackTrace| 3|1]: 0x4200bdd8 0x4200989c 0x4200a636 0x42008e92 0x42008426 0x42008328 0x42005ad0 0x42001a56
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc9a078 A2:3fc8307c A3:00000064 A4:00000064 A5:00000000 A6:00000001 A7:00000074
[ 4.649000] [ EMERG] riscv_registerdump: T0:42009f7e T1:42004c92 T2:000001ff T3:0000006c T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc9a9e0 S1:3fc99fe0 S2:3fc95048 S3:00000080 S4:3fc9aa6f S5:3fc95058 S6:00000001 S7:00000008
[ 4.649000] [ EMERG] riscv_registerdump: S8:3fc95048 S9:0000000a S10:0000000d S11:00000088
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc9a9c0 FP:3fc9a9e0 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: rt_timer: PID=4
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=484 of 2000
[ 4.649000] [ INFO] [BackTrace| 4|0]: 0x420082ae 0x4209c198 0x42001a42
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc9b068 A2:3fc8307c A3:000000e6 A4:00000000 A5:00000000 A6:00000002 A7:00000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:4005890e T1:4209dc78 T2:00000000 T3:000000fd T4:00000000 T5:00000000 T6:00000000
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc9c5d0 S1:3fc9afd0 S2:3fc8a758 S3:00000088 S4:3fc8a750 S5:00000008 S6:00000002 S7:3fc8a000
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000003 S9:00000003 S10:00000000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc9c5b0 FP:3fc9c5d0 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: wifi: PID=5
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=1360 of 6624
[ 4.649000] [ INFO] [BackTrace| 5|0]: 0x420082ae 0x42097868 0x4209da7a 0x400407be
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fc9cf18 A2:3fc8307c A3:00000064 A4:00000000 A5:00000000 A6:00000000 A7:c8000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:013a00d0 T1:400018cc T2:00025025 T3:00004cf2 T4:00400000 T5:00000002 T6:76a1df7c
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc9ebd0 S1:3fc9ce20 S2:3fc9ce80 S3:3fc9ebec S4:00000000 S5:3fc9ce24 S6:3fc94000 S7:3fce0000
[ 4.649000] [ EMERG] riscv_registerdump: S8:3ff1b000 S9:3fce0000 S10:3fcdf934 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc9ebb0 FP:3fc9ebd0 TP:00000000 RA:42097ad0
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: miio_client: PID=7
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=2148 of 4048
[ 4.649000] [ INFO] [BackTrace| 7|0]: 0x420082ae 0x42098270 0x42076a78 0x42076bfe 0x42036fa4 0x42005ad0 0x42001a56
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fca6708 A2:3fc8307c A3:00000064 A4:00000064 A5:00000000 A6:00000017 A7:00000074
[ 4.649000] [ EMERG] riscv_registerdump: T0:4200e09c T1:0000000f T2:000001ff T3:0000006c T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fca7980 S1:3fca6670 S2:3fca79ac S3:00000088 S4:3fca79ac S5:00000064 S6:000011e7 S7:00000004
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000064 S9:00000040 S10:00000080 S11:3c107000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fca7960 FP:3fca7980 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: BT TX: PID=8
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=724 of 928
[ 4.649000] [ INFO] [BackTrace| 8|0]: 0x420082ae 0x42003b1a 0x42035d90 0x42035888 0x42029212 0x4203619c 0x42001a42
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fca7b88 A2:3fcb9688 A3:00000064 A4:3fcb0ab0 A5:00000000 A6:00000001 A7:3c1000a2
[ 4.649000] [ EMERG] riscv_registerdump: T0:0000002e T1:20000000 T2:000001ff T3:00000000 T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc87370 S1:3fca7af0 S2:3fc873b0 S3:00000088 S4:00000002 S5:3fc9574c S6:ffffffff S7:00000002
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000f00 S9:00000400 S10:00000100 S11:00000200
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc87350 FP:3fc87370 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: BT RX: PID=9
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=532 of 1216
[ 4.649000] [ INFO] [BackTrace| 9|0]: 0x420082ae 0x42003b1a 0x42035d90 0x42035888 0x420360bc 0x42036550 0x420274e0 0x4203619c
[ 4.649000] [ INFO] [BackTrace| 9|1]: 0x42001a42
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fca8028 A2:3fca4808 A3:000000e3 A4:3fc9afd0 A5:00000000 A6:00000000 A7:00000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:4005890e T1:0000000f T2:00000000 T3:00000000 T4:00000000 T5:00000000 T6:00000000
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc86f00 S1:3fca7f90 S2:3fc86f40 S3:00000088 S4:00000001 S5:3fc86f9c S6:ffffffff S7:00000001
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000f00 S9:00000400 S10:00000100 S11:00000200
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc86ee0 FP:3fc86f00 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: btController: PID=10
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=500 of 4048
[ 4.649000] [ INFO] [BackTrace|10|0]: 0x420082ae 0x42003b1a 0x4209f852 0x40381d14
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fcad858 A2:3fcb0b48 A3:000000e4 A4:3fc9afd0 A5:00000000 A6:f4240000 A7:00000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:4005890e T1:f423f000 T2:1e77feb4 T3:00000000 T4:00d988a5 T5:32d7c84b T6:00de6cd7
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fcaeb70 S1:3fcad7c0 S2:3fcad7a0 S3:00000000 S4:3c1006f8 S5:3fce0000 S6:3fc93000 S7:3fce0000
[ 4.649000] [ EMERG] riscv_registerdump: S8:3fce0000 S9:00000001 S10:00000000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fcaeb50 FP:3fcaeb70 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: BT Driver: PID=11
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=452 of 1216
[ 4.649000] [ INFO] [BackTrace|11|0]: 0x420082ae 0x42003afc 0x420fccc4 0x42036a90 0x42036ace 0x4203619c 0x42001a42
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fcb0b48 A2:3fca7b88 A3:00000064 A4:3fca7f90 A5:00000000 A6:00000000 A7:00000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:4005890e T1:420fcc64 T2:00000000 T3:00000000 T4:00000000 T5:00000000 T6:00000000
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fc88560 S1:3fcb0ab0 S2:3fc9b4b8 S3:00000080 S4:3fc8814c S5:3fc885be S6:00000001 S7:0000003e
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000000 S9:00000000 S10:00000000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fc88540 FP:3fc88560 TP:00000000 RA:42003ad8
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: httpc_task: PID=12
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=740 of 5104
[ 4.649000] [ INFO] [BackTrace|12|0]: 0x420082ae 0x42097868 0x4203d5ec 0x4208ab0c 0x4201d338
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fca4a98 A2:3fca6708 A3:000000fd A4:00000064 A5:00000000 A6:00000001 A7:00000074
[ 4.649000] [ EMERG] riscv_registerdump: T0:0000002e T1:0000006a T2:000001ff T3:0000006c T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fcb4cf0 S1:3fca49a0 S2:3fca4a00 S3:3fcb4d0c S4:00000000 S5:3fca49a4 S6:3fc94000 S7:00000000
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000000 S9:00000000 S10:00000000 S11:00000000
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fcb4cd0 FP:3fcb4cf0 TP:00000000 RA:42097ad0
[ 4.649000] [ EMERG] riscv_taskdump:
[ 4.649000] [ EMERG] riscv_taskdump: otu_task: PID=13
[ 4.649000] [ EMERG] riscv_taskdump: Stack Used=916 of 4080
[ 4.649000] [ INFO] [BackTrace|13|0]: 0x420082ae 0x42098270 0x42076a78 0x420a9298 0x4208d66a 0x420864d0 0x4201d338
[ 4.649000] [ EMERG] riscv_registerdump: EPC:420082ae
[ 4.649000] [ EMERG] riscv_registerdump: A0:00000002 A1:3fca4ce8 A2:3fc8307c A3:00000064 A4:00000064 A5:00000000 A6:00000126 A7:fa000000
[ 4.649000] [ EMERG] riscv_registerdump: T0:4005890e T1:0000000f T2:000001ff T3:00000004 T4:00000068 T5:00000009 T6:0000002a
[ 4.649000] [ EMERG] riscv_registerdump: S0:3fcb5bf0 S1:3fca4c50 S2:3fcb5c1c S3:00000088 S4:3fcb5c1c S5:00000064 S6:00001214 S7:00000001
[ 4.649000] [ EMERG] riscv_registerdump: S8:00000064 S9:00000040 S10:00000080 S11:3fcb172c
[ 4.649000] [ EMERG] riscv_registerdump: SP:3fcb5bd0 FP:3fcb5bf0 TP:00000000 RA:42003ad8
```
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #4381: arch/riscv/assert: enhance the assert dump
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #4381:
URL: https://github.com/apache/incubator-nuttx/pull/4381#discussion_r692677224
##########
File path: arch/risc-v/src/rv32im/riscv_assert.c
##########
@@ -185,9 +188,16 @@ static void riscv_dumpstate(void)
uint32_t istacksize;
#endif
+ /* Show back trace */
+
+#ifdef CONFIG_ARCH_HAVE_BACKTRACE
Review comment:
change to CONFIG_SCHED_BACKTRACE
##########
File path: arch/risc-v/src/rv32im/riscv_assert.c
##########
@@ -85,88 +85,91 @@ static void riscv_stackdump(uint32_t sp, uint32_t stack_top)
#endif
/****************************************************************************
- * Name: riscv_taskdump
+ * Name: riscv_registerdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
-static void riscv_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
+#ifdef CONFIG_ARCH_STACKDUMP
+static inline void riscv_registerdump(FAR volatile uint32_t *regs)
{
- /* Dump interesting properties of this task */
+ /* Are user registers available from interrupt processing? */
-#if CONFIG_TASK_NAME_SIZE > 0
- _alert("%s: PID=%d Stack Used=%lu of %lu\n",
- tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("EPC:%08x \n", regs[REG_EPC]);
+ _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x "
+ "A6:%08x A7:%08x\n",
+ regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3],
+ regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
+ _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n",
+ regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
+ regs[REG_T4], regs[REG_T5], regs[REG_T6]);
+ _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
+ "S6:%08x S7:%08x\n",
+ regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
+ regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+ _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n",
+ regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
+#ifdef RISCV_SAVE_GP
+ _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n",
+ regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP],
+ regs[REG_RA]);
#else
- _alert("PID: %d Stack Used=%lu of %lu\n",
- tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n",
+ regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
#endif
}
+#else
+# define riscv_registerdump(reg)
#endif
/****************************************************************************
- * Name: riscv_showtasks
+ * Name: riscv_taskdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
-static inline void riscv_showtasks(void)
+#if defined(CONFIG_STACK_COLORATION) || defined(CONFIG_ARCH_HAVE_BACKTRACE)
+static void riscv_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
- /* Dump interesting properties of each task in the crash environment */
+ /* Dump interesting properties of this task */
- nxsched_foreach(riscv_taskdump, NULL);
-}
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d\n", tcb->name, tcb->pid);
#else
-# define riscv_showtasks()
+ _alert("PID: %d\n", tcb->pid);
+#endif
+
+ /* Show stack info */
+
+#ifdef CONFIG_STACK_COLORATION
+ _alert("Stack Used=%lu of %lu\n", (unsigned long)up_check_tcbstack(tcb),
+ (unsigned long)tcb->adj_stack_size);
#endif
+ /* Show back trace */
+
+#ifdef CONFIG_ARCH_HAVE_BACKTRACE
Review comment:
change to CONFIG_SCHED_BACKTRACE
##########
File path: arch/risc-v/src/rv64gc/riscv_assert.c
##########
@@ -86,104 +86,99 @@ static void up_stackdump(uint64_t sp, uintptr_t stack_top)
}
}
+/****************************************************************************
+ * Name: up_registerdump
+ ****************************************************************************/
+
+static inline void up_registerdump(FAR volatile uintptr_t *regs)
+{
+ /* Are user registers available from interrupt processing? */
+
+ _alert("EPC:%016" PRIx64 " \n", regs[REG_EPC]);
+ _alert("A0:%016" PRIx64 " A1:%01" PRIx64 "6 A2:%016" PRIx64
+ " A3:%016" PRIx64 " \n",
+ regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3]);
+ _alert("A4:%016" PRIx64 " A5:%016" PRIx64 "A6:%016" PRIx64
+ " A7:%016" PRIx64 " \n",
+ regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
+ _alert("T0:%016" PRIx64 " T1:%016" PRIx64 " T2:%016" PRIx64
+ " T3:%016" PRIx64 " \n",
+ regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3]);
+ _alert("T4:%016" PRIx64 " T5:%016" PRIx64 " T6:%016" PRIx64 " \n",
+ regs[REG_T4], regs[REG_T5], regs[REG_T6]);
+ _alert("S0:%016" PRIx64 " S1:%016" PRIx64 " S2:%016" PRIx64
+ " S3:%016" PRIx64 " \n",
+ regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3]);
+ _alert("S4:%016" PRIx64 " S5:%016" PRIx64 " S6:%016" PRIx64
+ " S7:%016" PRIx64 " \n",
+ regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+ _alert("S8:%016" PRIx64 " S9:%016" PRIx64 " S10:%016" PRIx64
+ " S11:%016" PRIx64 " \n",
+ regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
+#ifdef RISCV_SAVE_GP
+ _alert("GP:%016" PRIx64 " SP:%016" PRIx64 " FP:%016" PRIx64
+ " TP:%016" PRIx64 " RA:%016" PRIx64 " \n",
+ regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP],
+ regs[REG_RA]);
+#else
+ _alert("SP:%016" PRIx64 " FP:%016" PRIx64 " TP:%016" PRIx64
+ " RA:%016" PRIx64 " \n",
+ regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
+#endif
+}
+
/****************************************************************************
* Name: up_taskdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
+#if defined(CONFIG_STACK_COLORATION) || defined(CONFIG_ARCH_HAVE_BACKTRACE)
static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
#if CONFIG_TASK_NAME_SIZE > 0
- _alert("%s: PID=%d Stack Used=%lu of %lu\n",
- tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("%s: PID=%d\n", tcb->name, tcb->pid);
#else
- _alert("PID: %d Stack Used=%lu of %lu\n",
- tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("PID: %d\n", tcb->pid);
#endif
-}
+
+ /* Show stack info */
+
+#ifdef CONFIG_STACK_COLORATION
+ _alert("Stack Used=%lu of %lu\n", (unsigned long)up_check_tcbstack(tcb),
+ (unsigned long)tcb->adj_stack_size);
#endif
+ /* Show back trace */
+
+#ifdef CONFIG_ARCH_HAVE_BACKTRACE
+ sched_dumpstack(tcb->pid);
+#endif
+
+ /* Dump the registers */
+
+ up_registerdump(tcb->xcp.regs);
+
+ /* Add a blank line */
+
+ _alert("\n");
Review comment:
remove
##########
File path: arch/risc-v/src/rv64gc/riscv_assert.c
##########
@@ -199,9 +194,16 @@ static void up_dumpstate(void)
uintptr_t istacksize;
#endif
+ /* Show back trace */
+
+#ifdef CONFIG_ARCH_HAVE_BACKTRACE
Review comment:
CONFIG_SCED_BACKTRACE
##########
File path: arch/risc-v/src/rv32im/riscv_assert.c
##########
@@ -85,88 +85,91 @@ static void riscv_stackdump(uint32_t sp, uint32_t stack_top)
#endif
/****************************************************************************
- * Name: riscv_taskdump
+ * Name: riscv_registerdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
-static void riscv_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
+#ifdef CONFIG_ARCH_STACKDUMP
+static inline void riscv_registerdump(FAR volatile uint32_t *regs)
{
- /* Dump interesting properties of this task */
+ /* Are user registers available from interrupt processing? */
-#if CONFIG_TASK_NAME_SIZE > 0
- _alert("%s: PID=%d Stack Used=%lu of %lu\n",
- tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("EPC:%08x \n", regs[REG_EPC]);
+ _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x "
+ "A6:%08x A7:%08x\n",
+ regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3],
+ regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
+ _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n",
+ regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
+ regs[REG_T4], regs[REG_T5], regs[REG_T6]);
+ _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
+ "S6:%08x S7:%08x\n",
+ regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
+ regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+ _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n",
+ regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
+#ifdef RISCV_SAVE_GP
+ _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n",
+ regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP],
+ regs[REG_RA]);
#else
- _alert("PID: %d Stack Used=%lu of %lu\n",
- tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n",
+ regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
#endif
}
+#else
+# define riscv_registerdump(reg)
#endif
/****************************************************************************
- * Name: riscv_showtasks
+ * Name: riscv_taskdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
-static inline void riscv_showtasks(void)
+#if defined(CONFIG_STACK_COLORATION) || defined(CONFIG_ARCH_HAVE_BACKTRACE)
Review comment:
change to CONFIG_SCHED_BACKTRACE
##########
File path: arch/risc-v/src/rv64gc/riscv_assert.c
##########
@@ -199,9 +194,16 @@ static void up_dumpstate(void)
uintptr_t istacksize;
#endif
+ /* Show back trace */
+
+#ifdef CONFIG_ARCH_HAVE_BACKTRACE
+ _alert("Call Trace:\n");
Review comment:
remove
##########
File path: arch/risc-v/src/rv64gc/riscv_assert.c
##########
@@ -86,104 +86,99 @@ static void up_stackdump(uint64_t sp, uintptr_t stack_top)
}
}
+/****************************************************************************
+ * Name: up_registerdump
+ ****************************************************************************/
+
+static inline void up_registerdump(FAR volatile uintptr_t *regs)
+{
+ /* Are user registers available from interrupt processing? */
+
+ _alert("EPC:%016" PRIx64 " \n", regs[REG_EPC]);
+ _alert("A0:%016" PRIx64 " A1:%01" PRIx64 "6 A2:%016" PRIx64
+ " A3:%016" PRIx64 " \n",
+ regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3]);
+ _alert("A4:%016" PRIx64 " A5:%016" PRIx64 "A6:%016" PRIx64
+ " A7:%016" PRIx64 " \n",
+ regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
+ _alert("T0:%016" PRIx64 " T1:%016" PRIx64 " T2:%016" PRIx64
+ " T3:%016" PRIx64 " \n",
+ regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3]);
+ _alert("T4:%016" PRIx64 " T5:%016" PRIx64 " T6:%016" PRIx64 " \n",
+ regs[REG_T4], regs[REG_T5], regs[REG_T6]);
+ _alert("S0:%016" PRIx64 " S1:%016" PRIx64 " S2:%016" PRIx64
+ " S3:%016" PRIx64 " \n",
+ regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3]);
+ _alert("S4:%016" PRIx64 " S5:%016" PRIx64 " S6:%016" PRIx64
+ " S7:%016" PRIx64 " \n",
+ regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+ _alert("S8:%016" PRIx64 " S9:%016" PRIx64 " S10:%016" PRIx64
+ " S11:%016" PRIx64 " \n",
+ regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
+#ifdef RISCV_SAVE_GP
+ _alert("GP:%016" PRIx64 " SP:%016" PRIx64 " FP:%016" PRIx64
+ " TP:%016" PRIx64 " RA:%016" PRIx64 " \n",
+ regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP],
+ regs[REG_RA]);
+#else
+ _alert("SP:%016" PRIx64 " FP:%016" PRIx64 " TP:%016" PRIx64
+ " RA:%016" PRIx64 " \n",
+ regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
+#endif
+}
+
/****************************************************************************
* Name: up_taskdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
+#if defined(CONFIG_STACK_COLORATION) || defined(CONFIG_ARCH_HAVE_BACKTRACE)
static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
#if CONFIG_TASK_NAME_SIZE > 0
- _alert("%s: PID=%d Stack Used=%lu of %lu\n",
- tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("%s: PID=%d\n", tcb->name, tcb->pid);
#else
- _alert("PID: %d Stack Used=%lu of %lu\n",
- tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("PID: %d\n", tcb->pid);
Review comment:
wh not put stack info in the same line.
##########
File path: arch/risc-v/src/rv64gc/riscv_assert.c
##########
@@ -86,104 +86,99 @@ static void up_stackdump(uint64_t sp, uintptr_t stack_top)
}
}
+/****************************************************************************
+ * Name: up_registerdump
+ ****************************************************************************/
+
+static inline void up_registerdump(FAR volatile uintptr_t *regs)
+{
+ /* Are user registers available from interrupt processing? */
+
+ _alert("EPC:%016" PRIx64 " \n", regs[REG_EPC]);
+ _alert("A0:%016" PRIx64 " A1:%01" PRIx64 "6 A2:%016" PRIx64
+ " A3:%016" PRIx64 " \n",
+ regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3]);
+ _alert("A4:%016" PRIx64 " A5:%016" PRIx64 "A6:%016" PRIx64
+ " A7:%016" PRIx64 " \n",
+ regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
+ _alert("T0:%016" PRIx64 " T1:%016" PRIx64 " T2:%016" PRIx64
+ " T3:%016" PRIx64 " \n",
+ regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3]);
+ _alert("T4:%016" PRIx64 " T5:%016" PRIx64 " T6:%016" PRIx64 " \n",
+ regs[REG_T4], regs[REG_T5], regs[REG_T6]);
+ _alert("S0:%016" PRIx64 " S1:%016" PRIx64 " S2:%016" PRIx64
+ " S3:%016" PRIx64 " \n",
+ regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3]);
+ _alert("S4:%016" PRIx64 " S5:%016" PRIx64 " S6:%016" PRIx64
+ " S7:%016" PRIx64 " \n",
+ regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+ _alert("S8:%016" PRIx64 " S9:%016" PRIx64 " S10:%016" PRIx64
+ " S11:%016" PRIx64 " \n",
+ regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
+#ifdef RISCV_SAVE_GP
+ _alert("GP:%016" PRIx64 " SP:%016" PRIx64 " FP:%016" PRIx64
+ " TP:%016" PRIx64 " RA:%016" PRIx64 " \n",
+ regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP],
+ regs[REG_RA]);
+#else
+ _alert("SP:%016" PRIx64 " FP:%016" PRIx64 " TP:%016" PRIx64
+ " RA:%016" PRIx64 " \n",
+ regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
+#endif
+}
+
/****************************************************************************
* Name: up_taskdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
+#if defined(CONFIG_STACK_COLORATION) || defined(CONFIG_ARCH_HAVE_BACKTRACE)
static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
#if CONFIG_TASK_NAME_SIZE > 0
- _alert("%s: PID=%d Stack Used=%lu of %lu\n",
- tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("%s: PID=%d\n", tcb->name, tcb->pid);
#else
- _alert("PID: %d Stack Used=%lu of %lu\n",
- tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("PID: %d\n", tcb->pid);
#endif
-}
+
+ /* Show stack info */
+
+#ifdef CONFIG_STACK_COLORATION
+ _alert("Stack Used=%lu of %lu\n", (unsigned long)up_check_tcbstack(tcb),
+ (unsigned long)tcb->adj_stack_size);
#endif
+ /* Show back trace */
+
+#ifdef CONFIG_ARCH_HAVE_BACKTRACE
+ sched_dumpstack(tcb->pid);
+#endif
+
+ /* Dump the registers */
+
+ up_registerdump(tcb->xcp.regs);
+
+ /* Add a blank line */
+
+ _alert("\n");
+}
+
/****************************************************************************
* Name: up_showtasks
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
static inline void up_showtasks(void)
{
/* Dump interesting properties of each task in the crash environment */
+ _alert("Tasks status:\n");
Review comment:
remove
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[GitHub] [incubator-nuttx] xiaoxiang781216 merged pull request #4381: arch/riscv/assert: enhance the assert dump
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 merged pull request #4381:
URL: https://github.com/apache/incubator-nuttx/pull/4381
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[GitHub] [incubator-nuttx] xiaoxiang781216 commented on a change in pull request #4381: arch/riscv/assert: enhance the assert dump
Posted by GitBox <gi...@apache.org>.
xiaoxiang781216 commented on a change in pull request #4381:
URL: https://github.com/apache/incubator-nuttx/pull/4381#discussion_r693005378
##########
File path: arch/risc-v/src/rv32im/riscv_assert.c
##########
@@ -85,88 +85,92 @@ static void riscv_stackdump(uint32_t sp, uint32_t stack_top)
#endif
/****************************************************************************
- * Name: riscv_taskdump
+ * Name: riscv_registerdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
-static void riscv_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
+#ifdef CONFIG_ARCH_STACKDUMP
+static inline void riscv_registerdump(FAR volatile uint32_t *regs)
{
- /* Dump interesting properties of this task */
+ /* Are user registers available from interrupt processing? */
-#if CONFIG_TASK_NAME_SIZE > 0
- _alert("%s: PID=%d Stack Used=%lu of %lu\n",
- tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("EPC:%08x \n", regs[REG_EPC]);
+ _alert("A0:%08x A1:%08x A2:%08x A3:%08x A4:%08x A5:%08x "
+ "A6:%08x A7:%08x\n",
+ regs[REG_A0], regs[REG_A1], regs[REG_A2], regs[REG_A3],
+ regs[REG_A4], regs[REG_A5], regs[REG_A6], regs[REG_A7]);
+ _alert("T0:%08x T1:%08x T2:%08x T3:%08x T4:%08x T5:%08x T6:%08x\n",
+ regs[REG_T0], regs[REG_T1], regs[REG_T2], regs[REG_T3],
+ regs[REG_T4], regs[REG_T5], regs[REG_T6]);
+ _alert("S0:%08x S1:%08x S2:%08x S3:%08x S4:%08x S5:%08x "
+ "S6:%08x S7:%08x\n",
+ regs[REG_S0], regs[REG_S1], regs[REG_S2], regs[REG_S3],
+ regs[REG_S4], regs[REG_S5], regs[REG_S6], regs[REG_S7]);
+ _alert("S8:%08x S9:%08x S10:%08x S11:%08x\n",
+ regs[REG_S8], regs[REG_S9], regs[REG_S10], regs[REG_S11]);
+#ifdef RISCV_SAVE_GP
+ _alert("GP:%08x SP:%08x FP:%08x TP:%08x RA:%08x\n",
+ regs[REG_GP], regs[REG_SP], regs[REG_FP], regs[REG_TP],
+ regs[REG_RA]);
#else
- _alert("PID: %d Stack Used=%lu of %lu\n",
- tcb->pid, (unsigned long)up_check_tcbstack(tcb),
- (unsigned long)tcb->adj_stack_size);
+ _alert("SP:%08x FP:%08x TP:%08x RA:%08x\n",
+ regs[REG_SP], regs[REG_FP], regs[REG_TP], regs[REG_RA]);
#endif
}
+#else
+# define riscv_registerdump(reg)
#endif
/****************************************************************************
- * Name: riscv_showtasks
+ * Name: riscv_taskdump
****************************************************************************/
-#ifdef CONFIG_STACK_COLORATION
-static inline void riscv_showtasks(void)
+#if defined(CONFIG_STACK_COLORATION) || defined(CONFIG_SCHED_BACKTRACE)
+static void riscv_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
- /* Dump interesting properties of each task in the crash environment */
+ /* Dump interesting properties of this task */
- nxsched_foreach(riscv_taskdump, NULL);
-}
-#else
-# define riscv_showtasks()
+ _alert(
+#if CONFIG_TASK_NAME_SIZE > 0
+ "%s: "
+#endif
+ "PID=%d"
+#ifdef CONFIG_STACK_COLORATION
+ " Stack Used=%lu of %lu"
+#endif
+ "\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ tcb->name,
+#endif
+ tcb->pid,
+#ifdef CONFIG_STACK_COLORATION
+ (unsigned long)up_check_tcbstack(tcb),
+ (unsigned long)tcb->adj_stack_size
Review comment:
should we always print the stack size?
```
_alert(
#if CONFIG_TASK_NAME_SIZE > 0
"%s: "
#endif
"PID=%d "
#ifdef CONFIG_STACK_COLORATION
"Stack Used=%lu of %lu\n",
#else
"Stack=%lu\n",
#endif
#if CONFIG_TASK_NAME_SIZE > 0
tcb->name,
#endif
tcb->pid,
#ifdef CONFIG_STACK_COLORATION
(unsigned long)up_check_tcbstack(tcb),
#endif
(unsigned long)tcb->adj_stack_size
);
```
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