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Posted to commits@nuttx.apache.org by da...@apache.org on 2022/08/12 14:30:55 UTC
[incubator-nuttx] branch master updated (5d12e350da -> 690c178e4b)
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a change to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
from 5d12e350da pic32mx: add option to disable JTAG at runtime
new 4e4ebba306 arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (1/4)
new b317e9058f boards: sabre-6quad: Add CONFIG_NET_GUARDSIZE=4 to defconfigs
new 6dfd01885d arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (2/4)
new fb8562763a arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (3/4)
new 690c178e4b arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (4/4)
The 5 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails. The revisions
listed as "add" were already present in the repository and have only
been added to this reference.
Summary of changes:
arch/arm/src/imx6/imx_enet.c | 422 ++++++++++++---------
.../arm/imx6/sabre-6quad/configs/netknsh/defconfig | 1 +
.../arm/imx6/sabre-6quad/configs/netnsh/defconfig | 1 +
.../imx6/sabre-6quad/configs/netnsh_smp/defconfig | 1 +
4 files changed, 256 insertions(+), 169 deletions(-)
[incubator-nuttx] 02/05: boards: sabre-6quad: Add CONFIG_NET_GUARDSIZE=4 to defconfigs
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit b317e9058f625629769b8c01b4455befa0ebbbab
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Fri Aug 12 21:27:21 2022 +0900
boards: sabre-6quad: Add CONFIG_NET_GUARDSIZE=4 to defconfigs
Summary:
- This commit adds CONFIG_NET_GUARDSIZE=4 to defconfigs
Impact:
- None
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
boards/arm/imx6/sabre-6quad/configs/netknsh/defconfig | 1 +
boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig | 1 +
boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig | 1 +
3 files changed, 3 insertions(+)
diff --git a/boards/arm/imx6/sabre-6quad/configs/netknsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/netknsh/defconfig
index 32513f5145..1d9aee774c 100644
--- a/boards/arm/imx6/sabre-6quad/configs/netknsh/defconfig
+++ b/boards/arm/imx6/sabre-6quad/configs/netknsh/defconfig
@@ -87,6 +87,7 @@ CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ETH_PKTSIZE=1514
+CONFIG_NET_GUARDSIZE=4
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=8
diff --git a/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig b/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig
index c869f8b1d0..b6494913b9 100644
--- a/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig
+++ b/boards/arm/imx6/sabre-6quad/configs/netnsh/defconfig
@@ -78,6 +78,7 @@ CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ETH_PKTSIZE=1514
+CONFIG_NET_GUARDSIZE=4
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=8
diff --git a/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig b/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig
index b20e949a85..18b2b18d0a 100644
--- a/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig
+++ b/boards/arm/imx6/sabre-6quad/configs/netnsh_smp/defconfig
@@ -61,6 +61,7 @@ CONFIG_NETUTILS_TFTPC=y
CONFIG_NETUTILS_WEBCLIENT=y
CONFIG_NET_BROADCAST=y
CONFIG_NET_ETH_PKTSIZE=1514
+CONFIG_NET_GUARDSIZE=4
CONFIG_NET_ICMP=y
CONFIG_NET_ICMP_SOCKET=y
CONFIG_NET_MAX_LISTENPORTS=8
[incubator-nuttx] 05/05: arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (4/4)
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 690c178e4bdc1459fb0353d85cf5df6371e787a3
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Fri Aug 12 21:31:07 2022 +0900
arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (4/4)
Summary:
- This commit applies the following imxrt_enet.c changes to imx_enet.c
commit 0628019c2cb08dce06a128eef162bbe3e9ba0c8b
Author: David Sidrane <Da...@NscDg.com>
Date: Wed Jul 13 11:01:49 2022 -0700
imxrt:Enet ensure proper dcache for Writeback mode
Impact:
- imx_enet.c
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
arch/arm/src/imx6/imx_enet.c | 99 ++++++++++++++++++++++----------------------
1 file changed, 50 insertions(+), 49 deletions(-)
diff --git a/arch/arm/src/imx6/imx_enet.c b/arch/arm/src/imx6/imx_enet.c
index 33f962792b..f420663ea2 100644
--- a/arch/arm/src/imx6/imx_enet.c
+++ b/arch/arm/src/imx6/imx_enet.c
@@ -112,30 +112,6 @@
# error "Need at least one RX buffer"
#endif
-#define NENET_NBUFFERS \
- (CONFIG_IMX_ENET_NTXBUFFERS + CONFIG_IMX_ENET_NRXBUFFERS)
-
-/* Normally you would clean the cache after writing new values to the DMA
- * memory so assure that the dirty cache lines are flushed to memory
- * before the DMA occurs. And you would invalid the cache after a data is
- * received via DMA so that you fetch the actual content of the data from
- * the cache.
- *
- * These conditions are not fully supported here. If the write-throuch
- * D-Cache is enabled, however, then many of these issues go away: The
- * cache clean operation does nothing (because there are not dirty cache
- * lines) and the cache invalid operation is innocuous (because there are
- * never dirty cache lines to be lost; valid data will always be reloaded).
- *
- * At present, we simply insist that write through cache be enabled.
- */
-
-#if 0
-#if defined(CONFIG_ARMV7M_DCACHE) && !defined(CONFIG_ARMV7M_DCACHE_WRITETHROUGH)
-# error Write back D-Cache not yet supported
-#endif
-#endif
-
/* Align assuming that the D-Cache is enabled (probably 32-bytes).
*
* REVISIT: The size of descriptors and buffers must also be in even units
@@ -150,6 +126,14 @@
#define ENET_ALIGN_MASK (ENET_ALIGN - 1)
#define ENET_ALIGN_UP(n) (((n) + ENET_ALIGN_MASK) & ~ENET_ALIGN_MASK)
+#define DESC_SIZE sizeof(struct enet_desc_s)
+#define DESC_PADSIZE ENET_ALIGN_UP(DESC_SIZE)
+
+#define ALIGNED_BUFSIZE ENET_ALIGN_UP(CONFIG_NET_ETH_PKTSIZE + \
+ CONFIG_NET_GUARDSIZE)
+#define NENET_NBUFFERS \
+ (CONFIG_IMX_ENET_NTXBUFFERS + CONFIG_IMX_ENET_NRXBUFFERS)
+
/* TX timeout = 1 minute */
#define IMX_TXTIMEOUT (60 * CLK_TCK)
@@ -256,9 +240,6 @@
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
-#define IMX_BUF_SIZE ENET_ALIGN_UP(CONFIG_NET_ETH_PKTSIZE + \
- CONFIG_NET_GUARDSIZE)
-
/****************************************************************************
* Private Types
****************************************************************************/
@@ -290,27 +271,31 @@ struct imx_driver_s
struct net_driver_s dev; /* Interface understood by the network */
};
+/* This union type forces the allocated size of TX&RX descriptors to be
+ * padded to a exact multiple of the Cortex-M7 D-Cache line size.
+ */
+
+union enet_desc_u
+{
+ uint8_t pad[DESC_PADSIZE];
+ struct enet_desc_s desc;
+};
+
/****************************************************************************
* Private Data
****************************************************************************/
static struct imx_driver_s g_enet[CONFIG_IMX_ENET_NETHIFS];
-/* The DMA descriptors. A unaligned uint8_t is used to allocate the
- * memory; 16 is added to assure that we can meet the descriptor alignment
- * requirements.
- */
+/* The DMA descriptors */
-static uint8_t g_desc_pool[NENET_NBUFFERS * sizeof(struct enet_desc_s)]
- aligned_data(ENET_ALIGN);
+static union enet_desc_u g_desc_pool[NENET_NBUFFERS]
+ aligned_data(ENET_ALIGN);
-/* The DMA buffers. Again, A unaligned uint8_t is used to allocate the
- * memory; 16 is added to assure that we can meet the descriptor alignment
- * requirements.
- */
+/* The DMA buffers */
-static uint8_t g_buffer_pool[NENET_NBUFFERS * IMX_BUF_SIZE]
- aligned_data(ENET_ALIGN);
+static uint8_t g_buffer_pool[NENET_NBUFFERS][ALIGNED_BUFSIZE]
+ aligned_data(ENET_ALIGN);
/****************************************************************************
* Private Function Prototypes
@@ -641,21 +626,33 @@ static int imx_transmit(struct imx_driver_s *priv)
txdesc->status1 |= (TXDESC_R | TXDESC_L | TXDESC_TC);
buf = (uint8_t *)imx_swap32((uint32_t)priv->dev.d_buf);
- if (priv->rxdesc[priv->rxtail].data == buf)
- {
- struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
+ struct enet_desc_s *rxdesc = &priv->rxdesc[priv->rxtail];
+
+ up_invalidate_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc + sizeof(struct enet_desc_s));
+
+ if (rxdesc->data == buf)
+ {
/* Data was written into the RX buffer, so swap the TX and RX buffers */
DEBUGASSERT((rxdesc->status1 & RXDESC_E) == 0);
rxdesc->data = txdesc->data;
txdesc->data = buf;
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc + sizeof(struct enet_desc_s));
}
else
{
DEBUGASSERT(txdesc->data == buf);
}
+ up_clean_dcache((uintptr_t)txdesc,
+ (uintptr_t)txdesc + sizeof(struct enet_desc_s));
+
+ up_clean_dcache((uintptr_t)priv->dev.d_buf,
+ (uintptr_t)priv->dev.d_buf + priv->dev.d_len);
+
/* Start the TX transfer (if it was not already waiting for buffers) */
imx_enet_putreg32(priv, ENET_TDAR, IMX_ENET_TDAR_OFFSET);
@@ -976,6 +973,9 @@ static void imx_receive(struct imx_driver_s *priv)
imx_swap32((uint32_t)priv->txdesc[priv->txhead].data);
rxdesc->status1 |= RXDESC_E;
+ up_clean_dcache((uintptr_t)rxdesc,
+ (uintptr_t)rxdesc + sizeof(struct enet_desc_s));
+
/* Update the index to the next descriptor */
priv->rxtail++;
@@ -1380,7 +1380,7 @@ static int imx_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Set the RX buffer size */
- imx_enet_putreg32(priv, IMX_BUF_SIZE, IMX_ENET_MRBR_OFFSET);
+ imx_enet_putreg32(priv, ALIGNED_BUFSIZE, IMX_ENET_MRBR_OFFSET);
/* Point to the start of the circular RX buffer descriptor queue */
@@ -2411,13 +2411,11 @@ static void imx_initbuffers(struct imx_driver_s *priv)
/* Get an aligned TX descriptor (array) address */
- addr = (uintptr_t)g_desc_pool;
- priv->txdesc = (struct enet_desc_s *)addr;
+ priv->txdesc = &g_desc_pool[0].desc;
/* Get an aligned RX descriptor (array) address */
- addr += CONFIG_IMX_ENET_NTXBUFFERS * sizeof(struct enet_desc_s);
- priv->rxdesc = (struct enet_desc_s *)addr;
+ priv->rxdesc = &g_desc_pool[CONFIG_IMX_ENET_NTXBUFFERS].desc;
/* Get the beginning of the first aligned buffer */
@@ -2433,7 +2431,7 @@ static void imx_initbuffers(struct imx_driver_s *priv)
#ifdef CONFIG_IMX_ENETENHANCEDBD
priv->txdesc[i].status2 = TXDESC_IINS | TXDESC_PINS;
#endif
- addr += IMX_BUF_SIZE;
+ addr += ALIGNED_BUFSIZE;
}
/* Then fill in the RX descriptors */
@@ -2447,7 +2445,7 @@ static void imx_initbuffers(struct imx_driver_s *priv)
priv->rxdesc[i].bdu = 0;
priv->rxdesc[i].status2 = RXDESC_INT;
#endif
- addr += IMX_BUF_SIZE;
+ addr += ALIGNED_BUFSIZE;
}
/* Set the wrap bit in the last descriptors to form a ring */
@@ -2455,6 +2453,9 @@ static void imx_initbuffers(struct imx_driver_s *priv)
priv->txdesc[CONFIG_IMX_ENET_NTXBUFFERS - 1].status1 |= TXDESC_W;
priv->rxdesc[CONFIG_IMX_ENET_NRXBUFFERS - 1].status1 |= RXDESC_W;
+ up_clean_dcache((uintptr_t)g_desc_pool,
+ (uintptr_t)g_desc_pool + sizeof(g_desc_pool));
+
/* We start with RX descriptor 0 and with no TX descriptors in use */
priv->txtail = 0;
[incubator-nuttx] 04/05: arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (3/4)
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit fb8562763a08fee925ddb47ca4fce2fb597da53f
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Fri Aug 12 19:09:17 2022 +0900
arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (3/4)
Summary:
- This commit applies the following imxrt_enet.c changes to imx_enet.c
commit 522a949ed5b377a8a00c409da9bf1dd032fed939
Author: David Sidrane <Da...@NscDg.com>
Date: Wed Jul 13 11:00:11 2022 -0700
imxrt:enet Better interrupt state handeling
- NOTE: I also fixed typo and compile error in the above commit
Impact:
- imx_enet.c
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
arch/arm/src/imx6/imx_enet.c | 98 ++++++++++++++++++++++++++------------------
1 file changed, 58 insertions(+), 40 deletions(-)
diff --git a/arch/arm/src/imx6/imx_enet.c b/arch/arm/src/imx6/imx_enet.c
index 907202509f..33f962792b 100644
--- a/arch/arm/src/imx6/imx_enet.c
+++ b/arch/arm/src/imx6/imx_enet.c
@@ -279,6 +279,7 @@ struct imx_driver_s
uint8_t rxtail; /* The next RX descriptor to use */
uint8_t phyaddr; /* Selected PHY address */
struct wdog_s txtimeout; /* TX timeout timer */
+ uint32_t ints; /* Enabled interrupts */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
struct enet_desc_s *txdesc; /* A pointer to the list of TX descriptor */
@@ -322,6 +323,11 @@ static inline uint32_t imx_enet_getreg32(struct imx_driver_s *priv,
static inline void imx_enet_putreg32(struct imx_driver_s *priv,
uint32_t value, uint32_t offset);
+static inline void imx_enet_modifyreg32(struct imx_driver_s *priv,
+ unsigned int offset,
+ uint32_t clearbits,
+ uint32_t setbits);
+
#ifndef IMXRT_BUFFERS_SWAP
# define imx_swap32(value) (value)
# define imx_swap16(value) (value)
@@ -424,6 +430,31 @@ static inline uint32_t imx_enet_getreg32(struct imx_driver_s *priv,
return getreg32(priv->base + offset);
}
+/****************************************************************************
+ * Name: imx_enet_modifyreg32
+ *
+ * Description:
+ * Atomically modify the specified bits in a memory mapped register
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * offset - offset to the register of interest
+ * clearbits - the 32-bit value to be written as 0s
+ * setbits - the 32-bit value to be written as 1s
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void imx_enet_modifyreg32(struct imx_driver_s *priv,
+ unsigned int offset,
+ uint32_t clearbits,
+ uint32_t setbits)
+{
+ modifyreg32(priv->base + offset, clearbits, setbits);
+}
+
/****************************************************************************
* Name: imx_enet_putreg32
*
@@ -552,8 +583,6 @@ static bool imx_txringfull(struct imx_driver_s *priv)
static int imx_transmit(struct imx_driver_s *priv)
{
struct enet_desc_s *txdesc;
- irqstate_t flags;
- uint32_t regval;
uint8_t *buf;
/* Since this can be called from imx_receive, it is possible that
@@ -627,27 +656,20 @@ static int imx_transmit(struct imx_driver_s *priv)
DEBUGASSERT(txdesc->data == buf);
}
- /* Make the following operations atomic */
+ /* Start the TX transfer (if it was not already waiting for buffers) */
- flags = spin_lock_irqsave(NULL);
+ imx_enet_putreg32(priv, ENET_TDAR, IMX_ENET_TDAR_OFFSET);
/* Enable TX interrupts */
- regval = imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
- regval |= TX_INTERRUPTS;
- imx_enet_putreg32(priv, regval, IMX_ENET_EIMR_OFFSET);
+ priv->ints |= TX_INTERRUPTS;
+ imx_enet_modifyreg32(priv, IMX_ENET_EIMR_OFFSET, 0, TX_INTERRUPTS);
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
wd_start(&priv->txtimeout, IMX_TXTIMEOUT,
imx_txtimeout_expiry, (wdparm_t)priv);
- /* Start the TX transfer (if it was not already waiting for buffers) */
-
- imx_enet_putreg32(priv, ENET_TDAR, IMX_ENET_TDAR_OFFSET);
-
- spin_unlock_irqrestore(NULL, flags);
-
#if CONFIG_IMX_ENET_NTXBUFFERS == 1
priv->txbusy = false;
#endif
@@ -991,7 +1013,6 @@ static void imx_receive(struct imx_driver_s *priv)
static void imx_txdone(struct imx_driver_s *priv)
{
struct enet_desc_s *txdesc;
- uint32_t regval;
bool txdone;
/* We are here because a transmission completed, so the watchdog can be
@@ -1042,9 +1063,9 @@ static void imx_txdone(struct imx_driver_s *priv)
wd_cancel(&priv->txtimeout);
- regval = imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
- regval &= ~TX_INTERRUPTS;
- imx_enet_putreg32(priv, regval, IMX_ENET_EIMR_OFFSET);
+ priv->ints &= ~TX_INTERRUPTS;
+ imx_enet_modifyreg32(priv, IMX_ENET_EIMR_OFFSET, TX_INTERRUPTS,
+ priv->ints);
}
/* There should be space for a new TX in any event. Poll the network for
@@ -1086,8 +1107,7 @@ static void imx_enet_interrupt_work(void *arg)
/* Get the set of unmasked, pending interrupt. */
- pending = imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) &
- imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
+ pending = imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) & priv->ints;
/* Clear the pending interrupts */
@@ -1101,8 +1121,7 @@ static void imx_enet_interrupt_work(void *arg)
NETDEV_ERRORS(&priv->dev);
- nerr("ERROR: Network interface error occurred (0x%08" PRIX32 ")\n",
- (pending & ERROR_INTERRUPTS));
+ nerr("pending %" PRIx32 " ints %" PRIx32 "\n", pending, priv->ints);
}
if (pending & CRITICAL_ERROR)
@@ -1166,10 +1185,7 @@ static void imx_enet_interrupt_work(void *arg)
/* Re-enable Ethernet interrupts */
-#if 0
- up_enable_irq(IMX_IRQ_ENET0TMR);
-#endif
- up_enable_irq(IMX_IRQ_ENET0);
+ imx_enet_putreg32(priv, priv->ints, IMX_ENET_EIMR_OFFSET);
}
/****************************************************************************
@@ -1202,7 +1218,7 @@ static int imx_enet_interrupt(int irq, void *context, void *arg)
* condition here.
*/
- up_disable_irq(IMX_IRQ_ENET0);
+ imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
/* Schedule to perform the interrupt processing on the worker thread. */
@@ -1277,7 +1293,8 @@ static void imx_txtimeout_expiry(wdparm_t arg)
* condition with interrupt work that is already queued and in progress.
*/
- up_disable_irq(IMX_IRQ_ENET0);
+ imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
+ priv->ints = 0;
/* Schedule to perform the TX timeout processing on the worker thread,
* canceling any pending interrupt work.
@@ -1387,26 +1404,26 @@ static int imx_ifup_action(struct net_driver_s *dev, bool resetphy)
imx_enet_putreg32(priv, ENET_RDAR, IMX_ENET_RDAR_OFFSET);
+ imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
+
/* Clear all pending ENET interrupt */
- imx_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS,
- IMX_ENET_EIR_OFFSET);
+ imx_enet_putreg32(priv, 0xffffffff, IMX_ENET_EIR_OFFSET);
+
+ /* Mark the interrupt "up" and enable interrupts at the NVIC */
+
+ up_enable_irq(IMX_IRQ_ENET0);
+
+ priv->bifup = true;
/* Enable RX and error interrupts at the controller (TX interrupts are
* still disabled).
*/
- imx_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS,
- IMX_ENET_EIMR_OFFSET);
-
- /* Mark the interrupt "up" and enable interrupts at the NVIC */
-
- priv->bifup = true;
+ priv->ints = RX_INTERRUPTS | ERROR_INTERRUPTS;
+ imx_enet_modifyreg32(priv, IMX_ENET_EIMR_OFFSET, TX_INTERRUPTS,
+ priv->ints);
-#if 0
- up_enable_irq(IMX_IRQ_ENET0TMR);
-#endif
- up_enable_irq(IMX_IRQ_ENET0);
return OK;
}
@@ -1466,8 +1483,9 @@ static int imx_ifdown(struct net_driver_s *dev)
flags = enter_critical_section();
+ priv->ints = 0;
+ imx_enet_putreg32(priv, priv->ints, IMX_ENET_EIMR_OFFSET);
up_disable_irq(IMX_IRQ_ENET0);
- imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
/* Cancel the TX timeout timers */
[incubator-nuttx] 01/05: arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (1/4)
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 4e4ebba30682e5da8ee6e644f1ba234942284890
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Fri Aug 12 21:22:25 2022 +0900
arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (1/4)
Summary:
- This commit applies the following imxrt_enet.c changes to imx_enet.c
commit 12a515ebb639992c749e823d90ad3530fa764492
Author: Masayuki Ishikawa <ma...@gmail.com>
Date: Thu Feb 4 11:27:09 2021 +0900
arch: imxrt: Introduce CONFIG_NET_GUARDSIZE to imxrt_enet.c
Impact:
- imx_enet.c
Testing:
- Tested with qemu-6.2 (defconfig will be updated later)
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
arch/arm/src/imx6/imx_enet.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/src/imx6/imx_enet.c b/arch/arm/src/imx6/imx_enet.c
index 9d89f13552..f6c4064195 100644
--- a/arch/arm/src/imx6/imx_enet.c
+++ b/arch/arm/src/imx6/imx_enet.c
@@ -256,7 +256,8 @@
#define BUF ((struct eth_hdr_s *)priv->dev.d_buf)
-#define IMX_BUF_SIZE ENET_ALIGN_UP(CONFIG_NET_ETH_PKTSIZE)
+#define IMX_BUF_SIZE ENET_ALIGN_UP(CONFIG_NET_ETH_PKTSIZE + \
+ CONFIG_NET_GUARDSIZE)
/****************************************************************************
* Private Types
@@ -2244,11 +2245,13 @@ static inline int imx_initphy(struct imx_driver_s *priv, bool renogphy)
#ifdef CONFIG_IMX_ENETUSEMII
rcr = ENET_RCR_CRCFWD |
- CONFIG_NET_ETH_PKTSIZE << ENET_RCR_MAX_FL_SHIFT |
+ (CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE)
+ << ENET_RCR_MAX_FL_SHIFT |
ENET_RCR_MII_MODE;
#else
rcr = ENET_RCR_RMII_MODE | ENET_RCR_CRCFWD |
- CONFIG_NET_ETH_PKTSIZE << ENET_RCR_MAX_FL_SHIFT |
+ (CONFIG_NET_ETH_PKTSIZE + CONFIG_NET_GUARDSIZE)
+ << ENET_RCR_MAX_FL_SHIFT |
ENET_RCR_MII_MODE;
#endif
tcr = 0;
[incubator-nuttx] 03/05: arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (2/4)
Posted by da...@apache.org.
This is an automated email from the ASF dual-hosted git repository.
davids5 pushed a commit to branch master
in repository https://gitbox.apache.org/repos/asf/incubator-nuttx.git
commit 6dfd01885d642752500a9fff15c32d93ab5b81fd
Author: Masayuki Ishikawa <ma...@gmail.com>
AuthorDate: Fri Aug 12 16:54:29 2022 +0900
arch: imx6: Apply the imxrt_enet.c changes to imx_enet.c (2/4)
Summary:
- This commit applies the following imxrt_enet.c changes to imx_enet.c
commit 81f03a91517904e1bde3eaf0cd7b23bd33b6d3f6
Author: David Sidrane <Da...@NscDg.com>
Date: Tue Mar 15 14:27:51 2022 -0700
imxrt:ETH Add Support for ETH2
Impact:
- imx_enet.c
Testing:
- Tested with qemu-6.2
Signed-off-by: Masayuki Ishikawa <Ma...@jp.sony.com>
---
arch/arm/src/imx6/imx_enet.c | 246 +++++++++++++++++++++++++++----------------
1 file changed, 154 insertions(+), 92 deletions(-)
diff --git a/arch/arm/src/imx6/imx_enet.c b/arch/arm/src/imx6/imx_enet.c
index f6c4064195..907202509f 100644
--- a/arch/arm/src/imx6/imx_enet.c
+++ b/arch/arm/src/imx6/imx_enet.c
@@ -269,14 +269,15 @@
struct imx_driver_s
{
- bool bifup; /* true:ifup false:ifdown */
+ uint32_t base; /* Base address of ENET controller */
+ bool bifup; /* true:ifup false:ifdown */
#if CONFIG_IMX_ENET_NTXBUFFERS == 1
- bool txbusy;
+ bool txbusy;
#endif
- uint8_t txtail; /* The oldest busy TX descriptor */
- uint8_t txhead; /* The next TX descriptor to use */
- uint8_t rxtail; /* The next RX descriptor to use */
- uint8_t phyaddr; /* Selected PHY address */
+ uint8_t txtail; /* The oldest busy TX descriptor */
+ uint8_t txhead; /* The next TX descriptor to use */
+ uint8_t rxtail; /* The next RX descriptor to use */
+ uint8_t phyaddr; /* Selected PHY address */
struct wdog_s txtimeout; /* TX timeout timer */
struct work_s irqwork; /* For deferring interrupt work to the work queue */
struct work_s pollwork; /* For deferring poll work to the work queue */
@@ -316,6 +317,11 @@ static uint8_t g_buffer_pool[NENET_NBUFFERS * IMX_BUF_SIZE]
/* Utility functions */
+static inline uint32_t imx_enet_getreg32(struct imx_driver_s *priv,
+ uint32_t offset);
+static inline void imx_enet_putreg32(struct imx_driver_s *priv,
+ uint32_t value, uint32_t offset);
+
#ifndef IMXRT_BUFFERS_SWAP
# define imx_swap32(value) (value)
# define imx_swap16(value) (value)
@@ -397,6 +403,49 @@ static void imx_reset(struct imx_driver_s *priv);
* Private Functions
****************************************************************************/
+/****************************************************************************
+ * Name: imx_enet_getreg32
+ *
+ * Description:
+ * Get the contents of the ENET register at offset
+ *
+ * Input Parameters:
+ * priv - private ENET device structure
+ * offset - offset to the register of interest
+ *
+ * Returned Value:
+ * The contents of the 32-bit register
+ *
+ ****************************************************************************/
+
+static inline uint32_t imx_enet_getreg32(struct imx_driver_s *priv,
+ uint32_t offset)
+{
+ return getreg32(priv->base + offset);
+}
+
+/****************************************************************************
+ * Name: imx_enet_putreg32
+ *
+ * Description:
+ * Write a 16-bit value to the ENET register at offset
+ *
+ * Input Parameters:
+ * priv - private SPI device structure
+ * value - the 32-bit value to be written
+ * offset - offset to the register of interest
+ *
+ * Returned Value:
+ * The contents of the 32-bit register
+ *
+ ****************************************************************************/
+
+static inline void imx_enet_putreg32(struct imx_driver_s *priv,
+ uint32_t value, uint32_t offset)
+{
+ putreg32(value, priv->base + offset);
+}
+
/****************************************************************************
* Function: imx_swap16/32
*
@@ -584,9 +633,9 @@ static int imx_transmit(struct imx_driver_s *priv)
/* Enable TX interrupts */
- regval = getreg32(IMX_ENET_EIMR);
+ regval = imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
regval |= TX_INTERRUPTS;
- putreg32(regval, IMX_ENET_EIMR);
+ imx_enet_putreg32(priv, regval, IMX_ENET_EIMR_OFFSET);
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
@@ -595,7 +644,7 @@ static int imx_transmit(struct imx_driver_s *priv)
/* Start the TX transfer (if it was not already waiting for buffers) */
- putreg32(ENET_TDAR, IMX_ENET_TDAR);
+ imx_enet_putreg32(priv, ENET_TDAR, IMX_ENET_TDAR_OFFSET);
spin_unlock_irqrestore(NULL, flags);
@@ -915,7 +964,7 @@ static void imx_receive(struct imx_driver_s *priv)
/* Indicate that there have been empty receive buffers produced */
- putreg32(ENET_RDAR, IMX_ENET_RDAR);
+ imx_enet_putreg32(priv, ENET_RDAR, IMX_ENET_RDAR_OFFSET);
}
}
while (received);
@@ -993,9 +1042,9 @@ static void imx_txdone(struct imx_driver_s *priv)
wd_cancel(&priv->txtimeout);
- regval = getreg32(IMX_ENET_EIMR);
+ regval = imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
regval &= ~TX_INTERRUPTS;
- putreg32(regval, IMX_ENET_EIMR);
+ imx_enet_putreg32(priv, regval, IMX_ENET_EIMR_OFFSET);
}
/* There should be space for a new TX in any event. Poll the network for
@@ -1037,11 +1086,12 @@ static void imx_enet_interrupt_work(void *arg)
/* Get the set of unmasked, pending interrupt. */
- pending = getreg32(IMX_ENET_EIR) & getreg32(IMX_ENET_EIMR);
+ pending = imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) &
+ imx_enet_getreg32(priv, IMX_ENET_EIMR_OFFSET);
/* Clear the pending interrupts */
- putreg32(pending, IMX_ENET_EIR);
+ imx_enet_putreg32(priv, pending, IMX_ENET_EIR_OFFSET);
/* Check for errors */
@@ -1068,8 +1118,8 @@ static void imx_enet_interrupt_work(void *arg)
* multicast hash table.
*/
- gaurstore = getreg32(IMX_ENET_GAUR);
- galrstore = getreg32(IMX_ENET_GALR);
+ gaurstore = imx_enet_getreg32(priv, IMX_ENET_GAUR_OFFSET);
+ galrstore = imx_enet_getreg32(priv, IMX_ENET_GALR_OFFSET);
#endif
imx_ifdown(&priv->dev);
@@ -1078,8 +1128,8 @@ static void imx_enet_interrupt_work(void *arg)
#ifdef CONFIG_NET_MCASTGROUP
/* Now write the multicast table back */
- putreg32(gaurstore, IMX_ENET_GAUR);
- putreg32(galrstore, IMX_ENET_GALR);
+ imx_enet_putreg32(priv, gaurstore, IMX_ENET_GAUR_OFFSET);
+ imx_enet_putreg32(priv, galrstore, IMX_ENET_GALR_OFFSET);
#endif
/* Then poll the network for new XMIT data */
@@ -1144,7 +1194,8 @@ static void imx_enet_interrupt_work(void *arg)
static int imx_enet_interrupt(int irq, void *context, void *arg)
{
- register struct imx_driver_s *priv = &g_enet[0];
+ register struct imx_driver_s *priv =
+ (struct imx_driver_s *)arg;
/* Disable further Ethernet interrupts. Because Ethernet interrupts are
* also disabled if the TX timeout event occurs, there can be no race
@@ -1280,9 +1331,10 @@ static int imx_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Set the MAC address */
- putreg32((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
- IMX_ENET_PALR);
- putreg32((mac[4] << 24) | (mac[5] << 16), IMX_ENET_PAUR);
+ imx_enet_putreg32(priv, (mac[0] << 24) | (mac[1] << 16) |
+ (mac[2] << 8) | mac[3], IMX_ENET_PALR_OFFSET);
+ imx_enet_putreg32(priv, (mac[4] << 24) | (mac[5] << 16),
+ IMX_ENET_PAUR_OFFSET);
/* Configure the PHY */
@@ -1296,55 +1348,56 @@ static int imx_ifup_action(struct net_driver_s *dev, bool resetphy)
/* Handle promiscuous mode */
#ifdef CONFIG_NET_PROMISCUOUS
- regval = getreg32(IMX_ENET_RCR);
+ regval = imx_enet_getreg32(priv, IMX_ENET_RCR_OFFSET);
regval |= ENET_RCR_PROM;
- putreg32(regval, IMX_ENET_RCR);
+ imx_enet_putreg32(priv, regval, IMX_ENET_RCR_OFFSET);
#endif
/* Select legacy of enhanced buffer descriptor format */
#ifdef CONFIG_IMX_ENETENHANCEDBD
- putreg32(ENET_ECR_EN1588, IMX_ENET_ECR);
+ imx_enet_putreg32(priv, ENET_ECR_EN1588, IMX_ENET_ECR_OFFSET);
#else
- putreg32(0, IMX_ENET_ECR);
+ imx_enet_putreg32(priv, 0, IMX_ENET_ECR_OFFSET);
#endif
/* Set the RX buffer size */
- putreg32(IMX_BUF_SIZE, IMX_ENET_MRBR);
+ imx_enet_putreg32(priv, IMX_BUF_SIZE, IMX_ENET_MRBR_OFFSET);
/* Point to the start of the circular RX buffer descriptor queue */
- putreg32((uint32_t)priv->rxdesc, IMX_ENET_RDSR);
+ imx_enet_putreg32(priv, (uint32_t)priv->rxdesc, IMX_ENET_RDSR_OFFSET);
/* Point to the start of the circular TX buffer descriptor queue */
- putreg32((uint32_t)priv->txdesc, IMX_ENET_TDSR);
+ imx_enet_putreg32(priv, (uint32_t)priv->txdesc, IMX_ENET_TDSR_OFFSET);
/* And enable the MAC itself */
- regval = getreg32(IMX_ENET_ECR);
+ regval = imx_enet_getreg32(priv, IMX_ENET_ECR_OFFSET);
regval |= ENET_ECR_ETHEREN
#ifdef IMX_USE_DBSWAP
| ENET_ECR_DBSWP
#endif
;
- putreg32(regval, IMX_ENET_ECR);
+ imx_enet_putreg32(priv, regval, IMX_ENET_ECR_OFFSET);
/* Indicate that there have been empty receive buffers produced */
- putreg32(ENET_RDAR, IMX_ENET_RDAR);
+ imx_enet_putreg32(priv, ENET_RDAR, IMX_ENET_RDAR_OFFSET);
/* Clear all pending ENET interrupt */
- putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS, IMX_ENET_EIR);
+ imx_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS | TX_INTERRUPTS,
+ IMX_ENET_EIR_OFFSET);
/* Enable RX and error interrupts at the controller (TX interrupts are
* still disabled).
*/
- putreg32(RX_INTERRUPTS | ERROR_INTERRUPTS,
- IMX_ENET_EIMR);
+ imx_enet_putreg32(priv, RX_INTERRUPTS | ERROR_INTERRUPTS,
+ IMX_ENET_EIMR_OFFSET);
/* Mark the interrupt "up" and enable interrupts at the NVIC */
@@ -1414,7 +1467,7 @@ static int imx_ifdown(struct net_driver_s *dev)
flags = enter_critical_section();
up_disable_irq(IMX_IRQ_ENET0);
- putreg32(0, IMX_ENET_EIMR);
+ imx_enet_putreg32(priv, 0, IMX_ENET_EIMR_OFFSET);
/* Cancel the TX timeout timers */
@@ -1622,6 +1675,7 @@ static int imx_addmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t hashindex;
uint32_t temp;
uint32_t registeraddress;
+ struct imx_driver_s *priv = (struct imx_driver_s *)dev->d_private;
hashindex = imx_enet_hash_index(mac);
@@ -1629,17 +1683,17 @@ static int imx_addmac(struct net_driver_s *dev, const uint8_t *mac)
if (hashindex > 31)
{
- registeraddress = IMX_ENET_GAUR;
+ registeraddress = IMX_ENET_GAUR_OFFSET;
hashindex -= 32;
}
else
{
- registeraddress = IMX_ENET_GALR;
+ registeraddress = IMX_ENET_GALR_OFFSET;
}
- temp = getreg32(registeraddress);
+ temp = imx_enet_getreg32(priv, registeraddress);
temp |= 1 << hashindex;
- putreg32(temp, registeraddress);
+ imx_rt_enet_putreg32(priv, temp, registeraddress);
return OK;
}
@@ -1669,6 +1723,7 @@ static int imx_rmmac(struct net_driver_s *dev, const uint8_t *mac)
uint32_t hashindex;
uint32_t temp;
uint32_t registeraddress;
+ struct imx_driver_s *priv = (struct imx_driver_s *)dev->d_private;
/* Remove the MAC address from the hardware multicast routing table */
@@ -1676,17 +1731,17 @@ static int imx_rmmac(struct net_driver_s *dev, const uint8_t *mac)
if (hashindex > 31)
{
- registeraddress = IMX_ENET_GAUR;
+ registeraddress = IMX_ENET_GAUR_OFFSET;
hashindex -= 32;
}
else
{
- registeraddress = IMX_ENET_GALR;
+ registeraddress = IMX_ENET_GALR_OFFSET;
}
- temp = getreg32(registeraddress);
+ temp = imx_enet_getreg32(priv, registeraddress);
temp &= ~(1 << hashindex);
- putreg32(temp, registeraddress);
+ imx_enet_putreg32(priv, temp, registeraddress);
return OK;
}
@@ -1844,9 +1899,9 @@ static void imx_initmii(struct imx_driver_s *priv)
* clock. This hold time value may need to be increased on some platforms
*/
- putreg32(ENET_MSCR_HOLDTIME_2CYCLES |
- IMX_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT,
- IMX_ENET_MSCR);
+ imx_enet_putreg32(priv, ENET_MSCR_HOLDTIME_2CYCLES |
+ IMX_MII_SPEED << ENET_MSCR_MII_SPEED_SHIFT,
+ IMX_ENET_MSCR_OFFSET);
}
/****************************************************************************
@@ -1874,23 +1929,24 @@ static int imx_writemii(struct imx_driver_s *priv, uint8_t phyaddr,
/* Clear the MII interrupt bit */
- putreg32(ENET_INT_MII, IMX_ENET_EIR);
+ imx_enet_putreg32(priv, ENET_INT_MII, IMX_ENET_EIR_OFFSET);
/* Initiate the MII Management write */
- putreg32(data |
- 2 << ENET_MMFR_TA_SHIFT |
- (uint32_t)regaddr << ENET_MMFR_RA_SHIFT |
- (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT |
- ENET_MMFR_OP_WRMII |
- 1 << ENET_MMFR_ST_SHIFT,
- IMX_ENET_MMFR);
+ imx_enet_putreg32(priv, data |
+ 2 << ENET_MMFR_TA_SHIFT |
+ (uint32_t)regaddr << ENET_MMFR_RA_SHIFT |
+ (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT |
+ ENET_MMFR_OP_WRMII |
+ 1 << ENET_MMFR_ST_SHIFT,
+ IMX_ENET_MMFR_OFFSET);
/* Wait for the transfer to complete */
for (timeout = 0; timeout < MII_MAXPOLLS; timeout++)
{
- if ((getreg32(IMX_ENET_EIR) & ENET_INT_MII) != 0)
+ if ((imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) &
+ ENET_INT_MII) != 0)
{
break;
}
@@ -1905,7 +1961,7 @@ static int imx_writemii(struct imx_driver_s *priv, uint8_t phyaddr,
/* Clear the MII interrupt bit */
- putreg32(ENET_INT_MII, IMX_ENET_EIR);
+ imx_enet_putreg32(priv, ENET_INT_MII, IMX_ENET_EIR_OFFSET);
return OK;
}
#endif
@@ -1935,22 +1991,23 @@ static int imx_readmii(struct imx_driver_s *priv, uint8_t phyaddr,
/* Clear the MII interrupt bit */
- putreg32(ENET_INT_MII, IMX_ENET_EIR);
+ imx_enet_putreg32(priv, ENET_INT_MII, IMX_ENET_EIR_OFFSET);
/* Initiate the MII Management read */
- putreg32(2 << ENET_MMFR_TA_SHIFT |
- (uint32_t)regaddr << ENET_MMFR_RA_SHIFT |
- (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT |
- ENET_MMFR_OP_RDMII |
- 1 << ENET_MMFR_ST_SHIFT,
- IMX_ENET_MMFR);
+ imx_enet_putreg32(priv, 2 << ENET_MMFR_TA_SHIFT |
+ (uint32_t)regaddr << ENET_MMFR_RA_SHIFT |
+ (uint32_t)phyaddr << ENET_MMFR_PA_SHIFT |
+ ENET_MMFR_OP_RDMII |
+ 1 << ENET_MMFR_ST_SHIFT,
+ IMX_ENET_MMFR_OFFSET);
/* Wait for the transfer to complete */
for (timeout = 0; timeout < MII_MAXPOLLS; timeout++)
{
- if ((getreg32(IMX_ENET_EIR) & ENET_INT_MII) != 0)
+ if ((imx_enet_getreg32(priv, IMX_ENET_EIR_OFFSET) &
+ ENET_INT_MII) != 0)
{
break;
}
@@ -1966,11 +2023,12 @@ static int imx_readmii(struct imx_driver_s *priv, uint8_t phyaddr,
/* Clear the MII interrupt bit */
- putreg32(ENET_INT_MII, IMX_ENET_EIR);
+ imx_enet_putreg32(priv, ENET_INT_MII, IMX_ENET_EIR_OFFSET);
/* And return the MII data */
- *data = (uint16_t)(getreg32(IMX_ENET_MMFR) & ENET_MMFR_DATA_MASK);
+ *data = (uint16_t)(imx_enet_getreg32(priv, IMX_ENET_MMFR_OFFSET) &
+ ENET_MMFR_DATA_MASK);
return OK;
}
#endif
@@ -2256,8 +2314,8 @@ static inline int imx_initphy(struct imx_driver_s *priv, bool renogphy)
#endif
tcr = 0;
- putreg32(rcr, IMX_ENET_RCR);
- putreg32(tcr, IMX_ENET_TCR);
+ imx_enet_putreg32(priv, rcr, IMX_ENET_RCR_OFFSET);
+ imx_enet_putreg32(priv, tcr, IMX_ENET_TCR_OFFSET);
/* Enable Discard Of Frames With MAC Layer Errors.
* Enable Discard Of Frames With Wrong Protocol Checksum.
@@ -2265,7 +2323,7 @@ static inline int imx_initphy(struct imx_driver_s *priv, bool renogphy)
*/
racc = ENET_RACC_PRODIS | ENET_RACC_LINEDIS | ENET_RACC_IPDIS;
- putreg32(racc, IMX_ENET_RACC);
+ imx_enet_putreg32(priv, racc, IMX_ENET_RACC_OFFSET);
/* Setup half or full duplex */
@@ -2306,8 +2364,8 @@ static inline int imx_initphy(struct imx_driver_s *priv, bool renogphy)
return -EIO;
}
- putreg32(rcr, IMX_ENET_RCR);
- putreg32(tcr, IMX_ENET_TCR);
+ imx_enet_putreg32(priv, rcr, IMX_ENET_RCR_OFFSET);
+ imx_enet_putreg32(priv, tcr, IMX_ENET_TCR_OFFSET);
#endif
return OK;
}
@@ -2413,7 +2471,7 @@ static void imx_reset(struct imx_driver_s *priv)
/* Set the reset bit and clear the enable bit */
- putreg32(ENET_ECR_RESET, IMX_ENET_ECR);
+ imx_enet_putreg32(priv, ENET_ECR_RESET, IMX_ENET_ECR_OFFSET);
/* Wait at least 8 clock cycles */
@@ -2459,13 +2517,32 @@ int imx_netinitialize(int intf)
DEBUGASSERT(intf < CONFIG_IMX_ENET_NETHIFS);
priv = &g_enet[intf];
+ /* Initialize the driver structure */
+
+ memset(priv, 0, sizeof(struct imx_driver_s));
+
+ priv->base = IMX_ENET_VBASE; /* Assigne base address */
+
+ priv->dev.d_ifup = imx_ifup; /* I/F up (new IP address) callback */
+ priv->dev.d_ifdown = imx_ifdown; /* I/F down callback */
+ priv->dev.d_txavail = imx_txavail; /* New TX data callback */
+#ifdef CONFIG_NET_MCASTGROUP
+ priv->dev.d_addmac = imx_addmac; /* Add multicast MAC address */
+ priv->dev.d_rmmac = imx_rmmac; /* Remove multicast MAC address */
+#endif
+#ifdef CONFIG_NETDEV_IOCTL
+ priv->dev.d_ioctl = imx_ioctl; /* Support PHY ioctl() calls */
+#endif
+ priv->dev.d_private = g_enet; /* Used to recover private state from dev */
+
#if 0 /* TODO */
uint32_t regval;
- /* Enable ENET1_TX_CLK_DIR (Provides 50MHz clk OUT to PHY) */
+ /* Configure ENET1_TX_CLK */
regval = getreg32(IMX_IOMUXC_GPR_GPR1);
- regval |= GPR_GPR1_ENET1_TX_CLK_OUT_EN;
+ regval &= ~GPR_GPR1_ENET_MASK;
+ regval |= (GPR_GPR1_ENET_TX_DIR | GPR_GPR1_ENET_CLK_SEL);
putreg32(regval, IMX_IOMUXC_GPR_GPR1);
/* Enable the ENET clock. Clock is on during all modes,
@@ -2494,7 +2571,7 @@ int imx_netinitialize(int intf)
/* Attach the Ethernet MAC IEEE 1588 timer interrupt handler */
#if 0
- if (irq_attach(IMX_IRQ_ENET0TMR, imx_tmrinterrupt, NULL))
+ if (irq_attach(IMX_IRQ_ENET0TMR, imx_tmrinterrupt, priv))
{
/* We could not attach the ISR to the interrupt */
@@ -2505,7 +2582,7 @@ int imx_netinitialize(int intf)
/* Attach the Ethernet interrupt handler */
- if (irq_attach(IMX_IRQ_ENET0, imx_enet_interrupt, NULL))
+ if (irq_attach(IMX_IRQ_ENET0, imx_enet_interrupt, priv))
{
/* We could not attach the ISR to the interrupt */
@@ -2517,21 +2594,6 @@ int imx_netinitialize(int intf)
arm_gic_irq_trigger(IMX_IRQ_ENET0, false);
- /* Initialize the driver structure */
-
- memset(priv, 0, sizeof(struct imx_driver_s));
- priv->dev.d_ifup = imx_ifup; /* I/F up (new IP address) callback */
- priv->dev.d_ifdown = imx_ifdown; /* I/F down callback */
- priv->dev.d_txavail = imx_txavail; /* New TX data callback */
-#ifdef CONFIG_NET_MCASTGROUP
- priv->dev.d_addmac = imx_addmac; /* Add multicast MAC address */
- priv->dev.d_rmmac = imx_rmmac; /* Remove multicast MAC address */
-#endif
-#ifdef CONFIG_NETDEV_IOCTL
- priv->dev.d_ioctl = imx_ioctl; /* Support PHY ioctl() calls */
-#endif
- priv->dev.d_private = g_enet; /* Used to recover private state from dev */
-
#ifdef CONFIG_NET_ETHERNET
/* Determine a semi-unique MAC address from MCU UID
* We use UID Low and Mid Low registers to get 64 bits, from which we keep