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Posted to commits@mynewt.apache.org by ad...@apache.org on 2016/06/15 22:04:14 UTC
[31/51] [partial] incubator-mynewt-site git commit: Fixed broken
Quick Start link and added OpenOCD option for Arduino Primo debugging
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/at91samd.c
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diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/at91samd.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/at91samd.c
new file mode 100755
index 0000000..62b3542
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/at91samd.c
@@ -0,0 +1,1116 @@
+/***************************************************************************
+ * Copyright (C) 2013 by Andrey Yurovsky *
+ * Andrey Yurovsky <yu...@gmail.com> *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include "helper/binarybuffer.h"
+
+#include <target/cortex_m.h>
+
+#define SAMD_NUM_SECTORS 16
+#define SAMD_PAGE_SIZE_MAX 1024
+
+#define SAMD_FLASH ((uint32_t)0x00000000) /* physical Flash memory */
+#define SAMD_USER_ROW ((uint32_t)0x00804000) /* User Row of Flash */
+#define SAMD_PAC1 0x41000000 /* Peripheral Access Control 1 */
+#define SAMD_DSU 0x41002000 /* Device Service Unit */
+#define SAMD_NVMCTRL 0x41004000 /* Non-volatile memory controller */
+
+#define SAMD_DSU_STATUSA 1 /* DSU status register */
+#define SAMD_DSU_DID 0x18 /* Device ID register */
+
+#define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
+#define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
+#define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
+#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
+#define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
+#define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
+#define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
+
+#define SAMD_CMDEX_KEY 0xA5UL
+#define SAMD_NVM_CMD(n) ((SAMD_CMDEX_KEY << 8) | (n & 0x7F))
+
+/* NVMCTRL commands. See Table 20-4 in 42129F\u2013SAM\u201310/2013 */
+#define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
+#define SAMD_NVM_CMD_WP 0x04 /* Write Page */
+#define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
+#define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
+#define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
+#define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
+#define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */
+#define SAMD_NVM_CMD_CPRM 0x43 /* Clear Power Reduction Mode */
+#define SAMD_NVM_CMD_PBC 0x44 /* Page Buffer Clear */
+#define SAMD_NVM_CMD_SSB 0x45 /* Set Security Bit */
+#define SAMD_NVM_CMD_INVALL 0x46 /* Invalidate all caches */
+
+/* NVMCTRL bits */
+#define SAMD_NVM_CTRLB_MANW 0x80
+
+/* Known identifiers */
+#define SAMD_PROCESSOR_M0 0x01
+#define SAMD_FAMILY_D 0x00
+#define SAMD_FAMILY_L 0x01
+#define SAMD_FAMILY_C 0x02
+#define SAMD_SERIES_20 0x00
+#define SAMD_SERIES_21 0x01
+#define SAMD_SERIES_22 0x02
+#define SAMD_SERIES_10 0x02
+#define SAMD_SERIES_11 0x03
+
+/* Device ID macros */
+#define SAMD_GET_PROCESSOR(id) (id >> 28)
+#define SAMD_GET_FAMILY(id) (((id >> 23) & 0x1F))
+#define SAMD_GET_SERIES(id) (((id >> 16) & 0x3F))
+#define SAMD_GET_DEVSEL(id) (id & 0xFF)
+
+struct samd_part {
+ uint8_t id;
+ const char *name;
+ uint32_t flash_kb;
+ uint32_t ram_kb;
+};
+
+/* Known SAMD10 parts */
+static const struct samd_part samd10_parts[] = {
+ { 0x0, "SAMD10D14AMU", 16, 4 },
+ { 0x1, "SAMD10D13AMU", 8, 4 },
+ { 0x2, "SAMD10D12AMU", 4, 4 },
+ { 0x3, "SAMD10D14ASU", 16, 4 },
+ { 0x4, "SAMD10D13ASU", 8, 4 },
+ { 0x5, "SAMD10D12ASU", 4, 4 },
+ { 0x6, "SAMD10C14A", 16, 4 },
+ { 0x7, "SAMD10C13A", 8, 4 },
+ { 0x8, "SAMD10C12A", 4, 4 },
+};
+
+/* Known SAMD11 parts */
+static const struct samd_part samd11_parts[] = {
+ { 0x0, "SAMD11D14AMU", 16, 4 },
+ { 0x1, "SAMD11D13AMU", 8, 4 },
+ { 0x2, "SAMD11D12AMU", 4, 4 },
+ { 0x3, "SAMD11D14ASU", 16, 4 },
+ { 0x4, "SAMD11D13ASU", 8, 4 },
+ { 0x5, "SAMD11D12ASU", 4, 4 },
+ { 0x6, "SAMD11C14A", 16, 4 },
+ { 0x7, "SAMD11C13A", 8, 4 },
+ { 0x8, "SAMD11C12A", 4, 4 },
+};
+
+/* Known SAMD20 parts. See Table 12-8 in 42129F\u2013SAM\u201310/2013 */
+static const struct samd_part samd20_parts[] = {
+ { 0x0, "SAMD20J18A", 256, 32 },
+ { 0x1, "SAMD20J17A", 128, 16 },
+ { 0x2, "SAMD20J16A", 64, 8 },
+ { 0x3, "SAMD20J15A", 32, 4 },
+ { 0x4, "SAMD20J14A", 16, 2 },
+ { 0x5, "SAMD20G18A", 256, 32 },
+ { 0x6, "SAMD20G17A", 128, 16 },
+ { 0x7, "SAMD20G16A", 64, 8 },
+ { 0x8, "SAMD20G15A", 32, 4 },
+ { 0x9, "SAMD20G14A", 16, 2 },
+ { 0xA, "SAMD20E18A", 256, 32 },
+ { 0xB, "SAMD20E17A", 128, 16 },
+ { 0xC, "SAMD20E16A", 64, 8 },
+ { 0xD, "SAMD20E15A", 32, 4 },
+ { 0xE, "SAMD20E14A", 16, 2 },
+};
+
+/* Known SAMD21 parts. */
+static const struct samd_part samd21_parts[] = {
+ { 0x0, "SAMD21J18A", 256, 32 },
+ { 0x1, "SAMD21J17A", 128, 16 },
+ { 0x2, "SAMD21J16A", 64, 8 },
+ { 0x3, "SAMD21J15A", 32, 4 },
+ { 0x4, "SAMD21J14A", 16, 2 },
+ { 0x5, "SAMD21G18A", 256, 32 },
+ { 0x6, "SAMD21G17A", 128, 16 },
+ { 0x7, "SAMD21G16A", 64, 8 },
+ { 0x8, "SAMD21G15A", 32, 4 },
+ { 0x9, "SAMD21G14A", 16, 2 },
+ { 0xA, "SAMD21E18A", 256, 32 },
+ { 0xB, "SAMD21E17A", 128, 16 },
+ { 0xC, "SAMD21E16A", 64, 8 },
+ { 0xD, "SAMD21E15A", 32, 4 },
+ { 0xE, "SAMD21E14A", 16, 2 },
+ /* Below are B Variants (Table 3-7 from rev I of datasheet) */
+ { 0x20, "SAMD21J16B", 64, 8 },
+ { 0x21, "SAMD21J15B", 32, 4 },
+ { 0x23, "SAMD21G16B", 64, 8 },
+ { 0x24, "SAMD21G15B", 32, 4 },
+ { 0x26, "SAMD21E16B", 64, 8 },
+ { 0x27, "SAMD21E15B", 32, 4 },
+};
+
+/* Known SAMR21 parts. */
+static const struct samd_part samr21_parts[] = {
+ { 0x19, "SAMR21G18A", 256, 32 },
+ { 0x1A, "SAMR21G17A", 128, 32 },
+ { 0x1B, "SAMR21G16A", 64, 32 },
+ { 0x1C, "SAMR21E18A", 256, 32 },
+ { 0x1D, "SAMR21E17A", 128, 32 },
+ { 0x1E, "SAMR21E16A", 64, 32 },
+};
+
+/* Known SAML21 parts. */
+static const struct samd_part saml21_parts[] = {
+ { 0x00, "SAML21J18A", 256, 32 },
+ { 0x01, "SAML21J17A", 128, 16 },
+ { 0x02, "SAML21J16A", 64, 8 },
+ { 0x05, "SAML21G18A", 256, 32 },
+ { 0x06, "SAML21G17A", 128, 16 },
+ { 0x07, "SAML21G16A", 64, 8 },
+ { 0x0A, "SAML21E18A", 256, 32 },
+ { 0x0B, "SAML21E17A", 128, 16 },
+ { 0x0C, "SAML21E16A", 64, 8 },
+ { 0x0D, "SAML21E15A", 32, 4 },
+ { 0x0F, "SAML21J18B", 256, 32 },
+ { 0x10, "SAML21J17B", 128, 16 },
+ { 0x11, "SAML21J16B", 64, 8 },
+ { 0x14, "SAML21G18B", 256, 32 },
+ { 0x15, "SAML21G17B", 128, 16 },
+ { 0x16, "SAML21G16B", 64, 8 },
+ { 0x19, "SAML21E18B", 256, 32 },
+ { 0x1A, "SAML21E17B", 128, 16 },
+ { 0x1B, "SAML21E16B", 64, 8 },
+ { 0x1C, "SAML21E15B", 32, 4 },
+};
+
+/* Known SAML22 parts. */
+static const struct samd_part saml22_parts[] = {
+ { 0x00, "SAML22N18A", 256, 32 },
+ { 0x01, "SAML22N17A", 128, 16 },
+ { 0x02, "SAML22N16A", 64, 8 },
+ { 0x05, "SAML22J18A", 256, 32 },
+ { 0x06, "SAML22J17A", 128, 16 },
+ { 0x07, "SAML22J16A", 64, 8 },
+ { 0x0A, "SAML22G18A", 256, 32 },
+ { 0x0B, "SAML22G17A", 128, 16 },
+ { 0x0C, "SAML22G16A", 64, 8 },
+};
+
+/* Known SAMC20 parts. */
+static const struct samd_part samc20_parts[] = {
+ { 0x00, "SAMC20J18A", 256, 32 },
+ { 0x01, "SAMC20J17A", 128, 16 },
+ { 0x02, "SAMC20J16A", 64, 8 },
+ { 0x03, "SAMC20J15A", 32, 4 },
+ { 0x05, "SAMC20G18A", 256, 32 },
+ { 0x06, "SAMC20G17A", 128, 16 },
+ { 0x07, "SAMC20G16A", 64, 8 },
+ { 0x08, "SAMC20G15A", 32, 4 },
+ { 0x0A, "SAMC20E18A", 256, 32 },
+ { 0x0B, "SAMC20E17A", 128, 16 },
+ { 0x0C, "SAMC20E16A", 64, 8 },
+ { 0x0D, "SAMC20E15A", 32, 4 },
+};
+
+/* Known SAMC21 parts. */
+static const struct samd_part samc21_parts[] = {
+ { 0x00, "SAMC21J18A", 256, 32 },
+ { 0x01, "SAMC21J17A", 128, 16 },
+ { 0x02, "SAMC21J16A", 64, 8 },
+ { 0x03, "SAMC21J15A", 32, 4 },
+ { 0x05, "SAMC21G18A", 256, 32 },
+ { 0x06, "SAMC21G17A", 128, 16 },
+ { 0x07, "SAMC21G16A", 64, 8 },
+ { 0x08, "SAMC21G15A", 32, 4 },
+ { 0x0A, "SAMC21E18A", 256, 32 },
+ { 0x0B, "SAMC21E17A", 128, 16 },
+ { 0x0C, "SAMC21E16A", 64, 8 },
+ { 0x0D, "SAMC21E15A", 32, 4 },
+};
+
+/* Each family of parts contains a parts table in the DEVSEL field of DID. The
+ * processor ID, family ID, and series ID are used to determine which exact
+ * family this is and then we can use the corresponding table. */
+struct samd_family {
+ uint8_t processor;
+ uint8_t family;
+ uint8_t series;
+ const struct samd_part *parts;
+ size_t num_parts;
+};
+
+/* Known SAMD families */
+static const struct samd_family samd_families[] = {
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_20,
+ samd20_parts, ARRAY_SIZE(samd20_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
+ samd21_parts, ARRAY_SIZE(samd21_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_21,
+ samr21_parts, ARRAY_SIZE(samr21_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_10,
+ samd10_parts, ARRAY_SIZE(samd10_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_D, SAMD_SERIES_11,
+ samd11_parts, ARRAY_SIZE(samd11_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_21,
+ saml21_parts, ARRAY_SIZE(saml21_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_L, SAMD_SERIES_22,
+ saml22_parts, ARRAY_SIZE(saml22_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_20,
+ samc20_parts, ARRAY_SIZE(samc20_parts) },
+ { SAMD_PROCESSOR_M0, SAMD_FAMILY_C, SAMD_SERIES_21,
+ samc21_parts, ARRAY_SIZE(samc21_parts) },
+};
+
+struct samd_info {
+ uint32_t page_size;
+ int num_pages;
+ int sector_size;
+
+ bool probed;
+ struct target *target;
+ struct samd_info *next;
+};
+
+static struct samd_info *samd_chips;
+
+
+
+static const struct samd_part *samd_find_part(uint32_t id)
+{
+ uint8_t processor = SAMD_GET_PROCESSOR(id);
+ uint8_t family = SAMD_GET_FAMILY(id);
+ uint8_t series = SAMD_GET_SERIES(id);
+ uint8_t devsel = SAMD_GET_DEVSEL(id);
+
+ for (unsigned i = 0; i < ARRAY_SIZE(samd_families); i++) {
+ if (samd_families[i].processor == processor &&
+ samd_families[i].series == series &&
+ samd_families[i].family == family) {
+ for (unsigned j = 0; j < samd_families[i].num_parts; j++) {
+ if (samd_families[i].parts[j].id == devsel)
+ return &samd_families[i].parts[j];
+ }
+ }
+ }
+
+ return NULL;
+}
+
+static int samd_protect_check(struct flash_bank *bank)
+{
+ int res;
+ uint16_t lock;
+
+ res = target_read_u16(bank->target,
+ SAMD_NVMCTRL + SAMD_NVMCTRL_LOCK, &lock);
+ if (res != ERROR_OK)
+ return res;
+
+ /* Lock bits are active-low */
+ for (int i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_protected = !(lock & (1<<i));
+
+ return ERROR_OK;
+}
+
+static int samd_get_flash_page_info(struct target *target,
+ uint32_t *sizep, int *nump)
+{
+ int res;
+ uint32_t param;
+
+ res = target_read_u32(target, SAMD_NVMCTRL + SAMD_NVMCTRL_PARAM, ¶m);
+ if (res == ERROR_OK) {
+ /* The PSZ field (bits 18:16) indicate the page size bytes as 2^(3+n)
+ * so 0 is 8KB and 7 is 1024KB. */
+ if (sizep)
+ *sizep = (8 << ((param >> 16) & 0x7));
+ /* The NVMP field (bits 15:0) indicates the total number of pages */
+ if (nump)
+ *nump = param & 0xFFFF;
+ } else {
+ LOG_ERROR("Couldn't read NVM Parameters register");
+ }
+
+ return res;
+}
+
+static int samd_probe(struct flash_bank *bank)
+{
+ uint32_t id;
+ int res;
+ struct samd_info *chip = (struct samd_info *)bank->driver_priv;
+ const struct samd_part *part;
+
+ if (chip->probed)
+ return ERROR_OK;
+
+ res = target_read_u32(bank->target, SAMD_DSU + SAMD_DSU_DID, &id);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't read Device ID register");
+ return res;
+ }
+
+ part = samd_find_part(id);
+ if (part == NULL) {
+ LOG_ERROR("Couldn't find part corresponding to DID %08" PRIx32, id);
+ return ERROR_FAIL;
+ }
+
+ bank->size = part->flash_kb * 1024;
+
+ chip->sector_size = bank->size / SAMD_NUM_SECTORS;
+
+ res = samd_get_flash_page_info(bank->target, &chip->page_size,
+ &chip->num_pages);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't determine Flash page size");
+ return res;
+ }
+
+ /* Sanity check: the total flash size in the DSU should match the page size
+ * multiplied by the number of pages. */
+ if (bank->size != chip->num_pages * chip->page_size) {
+ LOG_WARNING("SAMD: bank size doesn't match NVM parameters. "
+ "Identified %" PRIu32 "KB Flash but NVMCTRL reports %u %" PRIu32 "B pages",
+ part->flash_kb, chip->num_pages, chip->page_size);
+ }
+
+ /* Allocate the sector table */
+ bank->num_sectors = SAMD_NUM_SECTORS;
+ bank->sectors = calloc(bank->num_sectors, sizeof((bank->sectors)[0]));
+ if (!bank->sectors)
+ return ERROR_FAIL;
+
+ /* Fill out the sector information: all SAMD sectors are the same size and
+ * there is always a fixed number of them. */
+ for (int i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].size = chip->sector_size;
+ bank->sectors[i].offset = i * chip->sector_size;
+ /* mark as unknown */
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = -1;
+ }
+
+ samd_protect_check(bank);
+
+ /* Done */
+ chip->probed = true;
+
+ LOG_INFO("SAMD MCU: %s (%" PRIu32 "KB Flash, %" PRIu32 "KB RAM)", part->name,
+ part->flash_kb, part->ram_kb);
+
+ return ERROR_OK;
+}
+
+static bool samd_check_error(struct target *target)
+{
+ int ret;
+ bool error;
+ uint16_t status;
+
+ ret = target_read_u16(target,
+ SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, &status);
+ if (ret != ERROR_OK) {
+ LOG_ERROR("Can't read NVM status");
+ return true;
+ }
+
+ if (status & 0x001C) {
+ if (status & (1 << 4)) /* NVME */
+ LOG_ERROR("SAMD: NVM Error");
+ if (status & (1 << 3)) /* LOCKE */
+ LOG_ERROR("SAMD: NVM lock error");
+ if (status & (1 << 2)) /* PROGE */
+ LOG_ERROR("SAMD: NVM programming error");
+
+ error = true;
+ } else {
+ error = false;
+ }
+
+ /* Clear the error conditions by writing a one to them */
+ ret = target_write_u16(target,
+ SAMD_NVMCTRL + SAMD_NVMCTRL_STATUS, status);
+ if (ret != ERROR_OK)
+ LOG_ERROR("Can't clear NVM error conditions");
+
+ return error;
+}
+
+static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
+{
+ int res;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* Issue the NVM command */
+ res = target_write_u16(target,
+ SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
+ if (res != ERROR_OK)
+ return res;
+
+ /* Check to see if the NVM command resulted in an error condition. */
+ if (samd_check_error(target))
+ return ERROR_FAIL;
+
+ return ERROR_OK;
+}
+
+static int samd_erase_row(struct target *target, uint32_t address)
+{
+ int res;
+
+ /* Set an address contained in the row to be erased */
+ res = target_write_u32(target,
+ SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR, address >> 1);
+
+ /* Issue the Erase Row command to erase that row. */
+ if (res == ERROR_OK)
+ res = samd_issue_nvmctrl_command(target,
+ address == SAMD_USER_ROW ? SAMD_NVM_CMD_EAR : SAMD_NVM_CMD_ER);
+
+ if (res != ERROR_OK) {
+ LOG_ERROR("Failed to erase row containing %08" PRIx32, address);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static bool is_user_row_reserved_bit(uint8_t bit)
+{
+ /* See Table 9-3 in the SAMD20 datasheet for more information. */
+ switch (bit) {
+ /* Reserved bits */
+ case 3:
+ case 7:
+ /* Voltage regulator internal configuration with default value of 0x70,
+ * may not be changed. */
+ case 17 ... 24:
+ /* 41 is voltage regulator internal configuration and must not be
+ * changed. 42 through 47 are reserved. */
+ case 41 ... 47:
+ return true;
+ default:
+ break;
+ }
+
+ return false;
+}
+
+/* Modify the contents of the User Row in Flash. These are described in Table
+ * 9-3 of the SAMD20 datasheet. The User Row itself has a size of one page
+ * and contains a combination of "fuses" and calibration data in bits 24:17.
+ * We therefore try not to erase the row's contents unless we absolutely have
+ * to and we don't permit modifying reserved bits. */
+static int samd_modify_user_row(struct target *target, uint32_t value,
+ uint8_t startb, uint8_t endb)
+{
+ int res;
+
+ if (is_user_row_reserved_bit(startb) || is_user_row_reserved_bit(endb)) {
+ LOG_ERROR("Can't modify bits in the requested range");
+ return ERROR_FAIL;
+ }
+
+ /* Retrieve the MCU's page size, in bytes. This is also the size of the
+ * entire User Row. */
+ uint32_t page_size;
+ res = samd_get_flash_page_info(target, &page_size, NULL);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't determine Flash page size");
+ return res;
+ }
+
+ /* Make sure the size is sane before we allocate. */
+ assert(page_size > 0 && page_size <= SAMD_PAGE_SIZE_MAX);
+
+ /* Make sure we're within the single page that comprises the User Row. */
+ if (startb >= (page_size * 8) || endb >= (page_size * 8)) {
+ LOG_ERROR("Can't modify bits outside the User Row page range");
+ return ERROR_FAIL;
+ }
+
+ uint8_t *buf = malloc(page_size);
+ if (!buf)
+ return ERROR_FAIL;
+
+ /* Read the user row (comprising one page) by half-words. */
+ res = target_read_memory(target, SAMD_USER_ROW, 2, page_size / 2, buf);
+ if (res != ERROR_OK)
+ goto out_user_row;
+
+ /* We will need to erase before writing if the new value needs a '1' in any
+ * position for which the current value had a '0'. Otherwise we can avoid
+ * erasing. */
+ uint32_t cur = buf_get_u32(buf, startb, endb - startb + 1);
+ if ((~cur) & value) {
+ res = samd_erase_row(target, SAMD_USER_ROW);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't erase user row");
+ goto out_user_row;
+ }
+ }
+
+ /* Modify */
+ buf_set_u32(buf, startb, endb - startb + 1, value);
+
+ /* Write the page buffer back out to the target. A Flash write will be
+ * triggered automatically. */
+ res = target_write_memory(target, SAMD_USER_ROW, 4, page_size / 4, buf);
+ if (res != ERROR_OK)
+ goto out_user_row;
+
+ if (samd_check_error(target)) {
+ res = ERROR_FAIL;
+ goto out_user_row;
+ }
+
+ /* Success */
+ res = ERROR_OK;
+
+out_user_row:
+ free(buf);
+
+ return res;
+}
+
+static int samd_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ struct samd_info *chip = (struct samd_info *)bank->driver_priv;
+
+ /* We can issue lock/unlock region commands with the target running but
+ * the settings won't persist unless we're able to modify the LOCK regions
+ * and that requires the target to be halted. */
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int res = ERROR_OK;
+
+ for (int s = first; s <= last; s++) {
+ if (set != bank->sectors[s].is_protected) {
+ /* Load an address that is within this sector (we use offset 0) */
+ res = target_write_u32(bank->target,
+ SAMD_NVMCTRL + SAMD_NVMCTRL_ADDR,
+ ((s * chip->sector_size) >> 1));
+ if (res != ERROR_OK)
+ goto exit;
+
+ /* Tell the controller to lock that sector */
+ res = samd_issue_nvmctrl_command(bank->target,
+ set ? SAMD_NVM_CMD_LR : SAMD_NVM_CMD_UR);
+ if (res != ERROR_OK)
+ goto exit;
+ }
+ }
+
+ /* We've now applied our changes, however they will be undone by the next
+ * reset unless we also apply them to the LOCK bits in the User Page. The
+ * LOCK bits start at bit 48, corresponding to Sector 0 and end with bit 63,
+ * corresponding to Sector 15. A '1' means unlocked and a '0' means
+ * locked. See Table 9-3 in the SAMD20 datasheet for more details. */
+
+ res = samd_modify_user_row(bank->target, set ? 0x0000 : 0xFFFF,
+ 48 + first, 48 + last);
+ if (res != ERROR_OK)
+ LOG_WARNING("SAMD: protect settings were not made persistent!");
+
+ res = ERROR_OK;
+
+exit:
+ samd_protect_check(bank);
+
+ return res;
+}
+
+static int samd_erase(struct flash_bank *bank, int first, int last)
+{
+ int res;
+ int rows_in_sector;
+ struct samd_info *chip = (struct samd_info *)bank->driver_priv;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (!chip->probed) {
+ if (samd_probe(bank) != ERROR_OK)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+ }
+
+ /* The SAMD NVM has row erase granularity. There are four pages in a row
+ * and the number of rows in a sector depends on the sector size, which in
+ * turn depends on the Flash capacity as there is a fixed number of
+ * sectors. */
+ rows_in_sector = chip->sector_size / (chip->page_size * 4);
+
+ /* For each sector to be erased */
+ for (int s = first; s <= last; s++) {
+ if (bank->sectors[s].is_protected) {
+ LOG_ERROR("SAMD: failed to erase sector %d. That sector is write-protected", s);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* For each row in that sector */
+ for (int r = s * rows_in_sector; r < (s + 1) * rows_in_sector; r++) {
+ res = samd_erase_row(bank->target, r * chip->page_size * 4);
+ if (res != ERROR_OK) {
+ LOG_ERROR("SAMD: failed to erase sector %d", s);
+ return res;
+ }
+ }
+ }
+
+ return ERROR_OK;
+}
+
+
+static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ int res;
+ uint32_t nvm_ctrlb;
+ uint32_t address;
+ uint32_t pg_offset;
+ uint32_t nb;
+ uint32_t nw;
+ struct samd_info *chip = (struct samd_info *)bank->driver_priv;
+ uint8_t *pb = NULL;
+ bool manual_wp;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (!chip->probed) {
+ if (samd_probe(bank) != ERROR_OK)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+ }
+
+ /* Check if we need to do manual page write commands */
+ res = target_read_u32(bank->target, SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLB, &nvm_ctrlb);
+
+ if (res != ERROR_OK)
+ return res;
+
+ if (nvm_ctrlb & SAMD_NVM_CTRLB_MANW)
+ manual_wp = true;
+ else
+ manual_wp = false;
+
+ res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_PBC);
+ if (res != ERROR_OK) {
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ return res;
+ }
+
+ while (count) {
+ nb = chip->page_size - offset % chip->page_size;
+ if (count < nb)
+ nb = count;
+
+ address = bank->base + offset;
+ pg_offset = offset % chip->page_size;
+
+ if (offset % 4 || (offset + nb) % 4) {
+ /* Either start or end of write is not word aligned */
+ if (!pb) {
+ pb = malloc(chip->page_size);
+ if (!pb)
+ return ERROR_FAIL;
+ }
+
+ /* Set temporary page buffer to 0xff and overwrite the relevant part */
+ memset(pb, 0xff, chip->page_size);
+ memcpy(pb + pg_offset, buffer, nb);
+
+ /* Align start address to a word boundary */
+ address -= offset % 4;
+ pg_offset -= offset % 4;
+ assert(pg_offset % 4 == 0);
+
+ /* Extend length to whole words */
+ nw = (nb + offset % 4 + 3) / 4;
+ assert(pg_offset + 4 * nw <= chip->page_size);
+
+ /* Now we have original data extended by 0xff bytes
+ * to the nearest word boundary on both start and end */
+ res = target_write_memory(bank->target, address, 4, nw, pb + pg_offset);
+ } else {
+ assert(nb % 4 == 0);
+ nw = nb / 4;
+ assert(pg_offset + 4 * nw <= chip->page_size);
+
+ /* Word aligned data, use direct write from buffer */
+ res = target_write_memory(bank->target, address, 4, nw, buffer);
+ }
+ if (res != ERROR_OK) {
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ goto free_pb;
+ }
+
+ /* Devices with errata 13134 have automatic page write enabled by default
+ * For other devices issue a write page CMD to the NVM
+ * If the page has not been written up to the last word
+ * then issue CMD_WP always */
+ if (manual_wp || pg_offset + 4 * nw < chip->page_size) {
+ res = samd_issue_nvmctrl_command(bank->target, SAMD_NVM_CMD_WP);
+ if (res != ERROR_OK) {
+ LOG_ERROR("%s: %d", __func__, __LINE__);
+ goto free_pb;
+ }
+ }
+
+ /* Access through AHB is stalled while flash is being programmed */
+ usleep(200);
+
+ if (samd_check_error(bank->target)) {
+ LOG_ERROR("%s: write failed at address 0x%08" PRIx32, __func__, address);
+ res = ERROR_FAIL;
+ goto free_pb;
+ }
+
+ /* We're done with the page contents */
+ count -= nb;
+ offset += nb;
+ buffer += nb;
+ }
+
+free_pb:
+ if (pb)
+ free(pb);
+
+ return res;
+}
+
+FLASH_BANK_COMMAND_HANDLER(samd_flash_bank_command)
+{
+ struct samd_info *chip = samd_chips;
+
+ while (chip) {
+ if (chip->target == bank->target)
+ break;
+ chip = chip->next;
+ }
+
+ if (!chip) {
+ /* Create a new chip */
+ chip = calloc(1, sizeof(*chip));
+ if (!chip)
+ return ERROR_FAIL;
+
+ chip->target = bank->target;
+ chip->probed = false;
+
+ bank->driver_priv = chip;
+
+ /* Insert it into the chips list (at head) */
+ chip->next = samd_chips;
+ samd_chips = chip;
+ }
+
+ if (bank->base != SAMD_FLASH) {
+ LOG_ERROR("Address 0x%08" PRIx32 " invalid bank address (try 0x%08" PRIx32
+ "[at91samd series] )",
+ bank->base, SAMD_FLASH);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(samd_handle_info_command)
+{
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(samd_handle_chip_erase_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+
+ if (target) {
+ /* Enable access to the DSU by disabling the write protect bit */
+ target_write_u32(target, SAMD_PAC1, (1<<1));
+ /* Tell the DSU to perform a full chip erase. It takes about 240ms to
+ * perform the erase. */
+ target_write_u8(target, SAMD_DSU, (1<<4));
+
+ command_print(CMD_CTX, "chip erased");
+ }
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(samd_handle_set_security_command)
+{
+ int res = ERROR_OK;
+ struct target *target = get_current_target(CMD_CTX);
+
+ if (CMD_ARGC < 1 || (CMD_ARGC >= 1 && (strcmp(CMD_ARGV[0], "enable")))) {
+ command_print(CMD_CTX, "supply the \"enable\" argument to proceed.");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (target) {
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ res = samd_issue_nvmctrl_command(target, SAMD_NVM_CMD_SSB);
+
+ /* Check (and clear) error conditions */
+ if (res == ERROR_OK)
+ command_print(CMD_CTX, "chip secured on next power-cycle");
+ else
+ command_print(CMD_CTX, "failed to secure chip");
+ }
+
+ return res;
+}
+
+COMMAND_HANDLER(samd_handle_eeprom_command)
+{
+ int res = ERROR_OK;
+ struct target *target = get_current_target(CMD_CTX);
+
+ if (target) {
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (CMD_ARGC >= 1) {
+ int val = atoi(CMD_ARGV[0]);
+ uint32_t code;
+
+ if (val == 0)
+ code = 7;
+ else {
+ /* Try to match size in bytes with corresponding size code */
+ for (code = 0; code <= 6; code++) {
+ if (val == (2 << (13 - code)))
+ break;
+ }
+
+ if (code > 6) {
+ command_print(CMD_CTX, "Invalid EEPROM size. Please see "
+ "datasheet for a list valid sizes.");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ }
+
+ res = samd_modify_user_row(target, code, 4, 6);
+ } else {
+ uint16_t val;
+ res = target_read_u16(target, SAMD_USER_ROW, &val);
+ if (res == ERROR_OK) {
+ uint32_t size = ((val >> 4) & 0x7); /* grab size code */
+
+ if (size == 0x7)
+ command_print(CMD_CTX, "EEPROM is disabled");
+ else {
+ /* Otherwise, 6 is 256B, 0 is 16KB */
+ command_print(CMD_CTX, "EEPROM size is %u bytes",
+ (2 << (13 - size)));
+ }
+ }
+ }
+ }
+
+ return res;
+}
+
+COMMAND_HANDLER(samd_handle_bootloader_command)
+{
+ int res = ERROR_OK;
+ struct target *target = get_current_target(CMD_CTX);
+
+ if (target) {
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* Retrieve the MCU's page size, in bytes. */
+ uint32_t page_size;
+ res = samd_get_flash_page_info(target, &page_size, NULL);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Couldn't determine Flash page size");
+ return res;
+ }
+
+ if (CMD_ARGC >= 1) {
+ int val = atoi(CMD_ARGV[0]);
+ uint32_t code;
+
+ if (val == 0)
+ code = 7;
+ else {
+ /* Try to match size in bytes with corresponding size code */
+ for (code = 0; code <= 6; code++) {
+ if ((unsigned int)val == (2UL << (8UL - code)) * page_size)
+ break;
+ }
+
+ if (code > 6) {
+ command_print(CMD_CTX, "Invalid bootloader size. Please "
+ "see datasheet for a list valid sizes.");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ }
+
+ res = samd_modify_user_row(target, code, 0, 2);
+ } else {
+ uint16_t val;
+ res = target_read_u16(target, SAMD_USER_ROW, &val);
+ if (res == ERROR_OK) {
+ uint32_t size = (val & 0x7); /* grab size code */
+ uint32_t nb;
+
+ if (size == 0x7)
+ nb = 0;
+ else
+ nb = (2 << (8 - size)) * page_size;
+
+ /* There are 4 pages per row */
+ command_print(CMD_CTX, "Bootloader size is %" PRIu32 " bytes (%" PRIu32 " rows)",
+ nb, (uint32_t)(nb / (page_size * 4)));
+ }
+ }
+ }
+
+ return res;
+}
+
+
+
+COMMAND_HANDLER(samd_handle_reset_deassert)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ int retval = ERROR_OK;
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+ /* In case of sysresetreq, debug retains state set in cortex_m_assert_reset()
+ * so we just release reset held by DSU
+ *
+ * n_RESET (srst) clears the DP, so reenable debug and set vector catch here
+ *
+ * After vectreset DSU release is not needed however makes no harm
+ */
+ if (target->reset_halt && (jtag_reset_config & RESET_HAS_SRST)) {
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DHCSR, DBGKEY | C_HALT | C_DEBUGEN);
+ if (retval == ERROR_OK)
+ retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DEMCR,
+ TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ /* do not return on error here, releasing DSU reset is more important */
+ }
+
+ /* clear CPU Reset Phase Extension bit */
+ int retval2 = target_write_u8(target, SAMD_DSU + SAMD_DSU_STATUSA, (1<<1));
+ if (retval2 != ERROR_OK)
+ return retval2;
+
+ return retval;
+}
+
+static const struct command_registration at91samd_exec_command_handlers[] = {
+ {
+ .name = "dsu_reset_deassert",
+ .handler = samd_handle_reset_deassert,
+ .mode = COMMAND_EXEC,
+ .help = "deasert internal reset held by DSU"
+ },
+ {
+ .name = "info",
+ .handler = samd_handle_info_command,
+ .mode = COMMAND_EXEC,
+ .help = "Print information about the current at91samd chip"
+ "and its flash configuration.",
+ },
+ {
+ .name = "chip-erase",
+ .handler = samd_handle_chip_erase_command,
+ .mode = COMMAND_EXEC,
+ .help = "Erase the entire Flash by using the Chip"
+ "Erase feature in the Device Service Unit (DSU).",
+ },
+ {
+ .name = "set-security",
+ .handler = samd_handle_set_security_command,
+ .mode = COMMAND_EXEC,
+ .help = "Secure the chip's Flash by setting the Security Bit."
+ "This makes it impossible to read the Flash contents."
+ "The only way to undo this is to issue the chip-erase"
+ "command.",
+ },
+ {
+ .name = "eeprom",
+ .usage = "[size_in_bytes]",
+ .handler = samd_handle_eeprom_command,
+ .mode = COMMAND_EXEC,
+ .help = "Show or set the EEPROM size setting, stored in the User Row."
+ "Please see Table 20-3 of the SAMD20 datasheet for allowed values."
+ "Changes are stored immediately but take affect after the MCU is"
+ "reset.",
+ },
+ {
+ .name = "bootloader",
+ .usage = "[size_in_bytes]",
+ .handler = samd_handle_bootloader_command,
+ .mode = COMMAND_EXEC,
+ .help = "Show or set the bootloader size, stored in the User Row."
+ "Please see Table 20-2 of the SAMD20 datasheet for allowed values."
+ "Changes are stored immediately but take affect after the MCU is"
+ "reset.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration at91samd_command_handlers[] = {
+ {
+ .name = "at91samd",
+ .mode = COMMAND_ANY,
+ .help = "at91samd flash command group",
+ .usage = "",
+ .chain = at91samd_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver at91samd_flash = {
+ .name = "at91samd",
+ .commands = at91samd_command_handlers,
+ .flash_bank_command = samd_flash_bank_command,
+ .erase = samd_erase,
+ .protect = samd_protect,
+ .write = samd_write,
+ .read = default_flash_read,
+ .probe = samd_probe,
+ .auto_probe = samd_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = samd_protect_check,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/atsamv.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/atsamv.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/atsamv.c
new file mode 100755
index 0000000..08f8bb8
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/atsamv.c
@@ -0,0 +1,737 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Duane Ellis *
+ * openocd@duaneellis.com *
+ * *
+ * Copyright (C) 2010 by Olaf L�ke (at91sam3s* support) *
+ * olaf@uni-paderborn.de *
+ * *
+ * Copyright (C) 2011 by Olivier Schonken, Jim Norris *
+ * (at91sam3x* & at91sam4 support)* *
+ * *
+ * Copyright (C) 2015 Morgan Quigley *
+ * (atsamv, atsams, and atsame support) *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
+ * GNU General public License for more details. *
+ * *
+ ***************************************************************************/
+
+/* Some of the the lower level code was based on code supplied by
+ * ATMEL under this copyright. */
+
+/* BEGIN ATMEL COPYRIGHT */
+/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2009, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+/* END ATMEL COPYRIGHT */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/time_support.h>
+
+#define REG_NAME_WIDTH (12)
+
+#define SAMV_EFC_FCMD_GETD (0x0) /* (EFC) Get Flash Descriptor */
+#define SAMV_EFC_FCMD_WP (0x1) /* (EFC) Write Page */
+#define SAMV_EFC_FCMD_WPL (0x2) /* (EFC) Write Page and Lock */
+#define SAMV_EFC_FCMD_EWP (0x3) /* (EFC) Erase Page and Write Page */
+#define SAMV_EFC_FCMD_EWPL (0x4) /* (EFC) Erase Page, Write Page then Lock*/
+#define SAMV_EFC_FCMD_EA (0x5) /* (EFC) Erase All */
+#define SAMV_EFC_FCMD_EPA (0x7) /* (EFC) Erase pages */
+#define SAMV_EFC_FCMD_SLB (0x8) /* (EFC) Set Lock Bit */
+#define SAMV_EFC_FCMD_CLB (0x9) /* (EFC) Clear Lock Bit */
+#define SAMV_EFC_FCMD_GLB (0xA) /* (EFC) Get Lock Bit */
+#define SAMV_EFC_FCMD_SFB (0xB) /* (EFC) Set Fuse Bit */
+#define SAMV_EFC_FCMD_CFB (0xC) /* (EFC) Clear Fuse Bit */
+#define SAMV_EFC_FCMD_GFB (0xD) /* (EFC) Get Fuse Bit */
+
+#define OFFSET_EFC_FMR 0
+#define OFFSET_EFC_FCR 4
+#define OFFSET_EFC_FSR 8
+#define OFFSET_EFC_FRR 12
+
+#define SAMV_CHIPID_CIDR (0x400E0940)
+#define SAMV_NUM_GPNVM_BITS 9
+#define SAMV_CONTROLLER_ADDR (0x400e0c00)
+#define SAMV_SECTOR_SIZE 16384
+#define SAMV_PAGE_SIZE 512
+#define SAMV_FLASH_BASE 0x00400000
+
+extern struct flash_driver atsamv_flash;
+
+struct samv_flash_bank {
+ int probed;
+ unsigned size_bytes;
+ unsigned gpnvm[SAMV_NUM_GPNVM_BITS];
+};
+
+/* The actual sector size of the SAMV7 flash memory is 128K bytes.
+ * 16 sectors for a 2048KB device. The lock regions are 16KB per lock
+ * region, with a 2048KB device having 128 lock regions.
+ * For the best results, num_sectors is thus set to the number of lock
+ * regions, and the sector_size set to the lock region size. Page
+ * erases are used to erase 16KB sections when programming */
+
+static int samv_efc_get_status(struct target *target, uint32_t *v)
+{
+ int r = target_read_u32(target, SAMV_CONTROLLER_ADDR + OFFSET_EFC_FSR, v);
+ return r;
+}
+
+static int samv_efc_get_result(struct target *target, uint32_t *v)
+{
+ uint32_t rv;
+ int r = target_read_u32(target, SAMV_CONTROLLER_ADDR + OFFSET_EFC_FRR, &rv);
+ if (v)
+ *v = rv;
+ return r;
+}
+
+static int samv_efc_start_command(struct target *target,
+ unsigned command, unsigned argument)
+{
+ uint32_t v;
+ samv_efc_get_status(target, &v);
+ if (!(v & 1)) {
+ LOG_ERROR("flash controller is not ready");
+ return ERROR_FAIL;
+ }
+
+ v = (0x5A << 24) | (argument << 8) | command;
+ LOG_DEBUG("starting flash command: 0x%08x", (unsigned int)(v));
+ int r = target_write_u32(target, SAMV_CONTROLLER_ADDR + OFFSET_EFC_FCR, v);
+ if (r != ERROR_OK)
+ LOG_DEBUG("write failed");
+ return r;
+}
+
+static int samv_efc_perform_command(struct target *target,
+ unsigned command, unsigned argument, uint32_t *status)
+{
+ int r;
+ uint32_t v;
+ long long ms_now, ms_end;
+
+ if (status)
+ *status = 0;
+
+ r = samv_efc_start_command(target, command, argument);
+ if (r != ERROR_OK)
+ return r;
+
+ ms_end = 10000 + timeval_ms();
+
+ do {
+ r = samv_efc_get_status(target, &v);
+ if (r != ERROR_OK)
+ return r;
+ ms_now = timeval_ms();
+ if (ms_now > ms_end) {
+ /* error */
+ LOG_ERROR("Command timeout");
+ return ERROR_FAIL;
+ }
+ } while ((v & 1) == 0);
+
+ /* if requested, copy the flash controller error bits back to the caller */
+ if (status)
+ *status = (v & 0x6);
+ return ERROR_OK;
+}
+
+static int samv_erase_pages(struct target *target,
+ int first_page, int num_pages, uint32_t *status)
+{
+ uint8_t erase_pages;
+ switch (num_pages) {
+ case 4:
+ erase_pages = 0x00;
+ break;
+ case 8:
+ erase_pages = 0x01;
+ break;
+ case 16:
+ erase_pages = 0x02;
+ break;
+ case 32:
+ erase_pages = 0x03;
+ break;
+ default:
+ erase_pages = 0x00;
+ break;
+ }
+
+ /* SAMV_EFC_FCMD_EPA
+ * According to the datasheet FARG[15:2] defines the page from which
+ * the erase will start.This page must be modulo 4, 8, 16 or 32
+ * according to the number of pages to erase. FARG[1:0] defines the
+ * number of pages to be erased. Previously (firstpage << 2) was used
+ * to conform to this, seems it should not be shifted...
+ */
+ return samv_efc_perform_command(target, SAMV_EFC_FCMD_EPA,
+ first_page | erase_pages, status);
+}
+
+static int samv_get_gpnvm(struct target *target, unsigned gpnvm, unsigned *out)
+{
+ uint32_t v;
+ int r;
+
+ if (gpnvm >= SAMV_NUM_GPNVM_BITS) {
+ LOG_ERROR("invalid gpnvm %d, max: %d", gpnvm, SAMV_NUM_GPNVM_BITS);
+ return ERROR_FAIL;
+ }
+
+ r = samv_efc_perform_command(target, SAMV_EFC_FCMD_GFB, 0, NULL);
+ if (r != ERROR_OK) {
+ LOG_ERROR("samv_get_gpnvm failed");
+ return r;
+ }
+
+ r = samv_efc_get_result(target, &v);
+
+ if (out)
+ *out = (v >> gpnvm) & 1;
+
+ return r;
+}
+
+static int samv_clear_gpnvm(struct target *target, unsigned gpnvm)
+{
+ int r;
+ unsigned v;
+
+ if (gpnvm >= SAMV_NUM_GPNVM_BITS) {
+ LOG_ERROR("invalid gpnvm %d, max: %d", gpnvm, SAMV_NUM_GPNVM_BITS);
+ return ERROR_FAIL;
+ }
+ r = samv_get_gpnvm(target, gpnvm, &v);
+ if (r != ERROR_OK) {
+ LOG_DEBUG("get gpnvm failed: %d", r);
+ return r;
+ }
+ r = samv_efc_perform_command(target, SAMV_EFC_FCMD_CFB, gpnvm, NULL);
+ LOG_DEBUG("clear gpnvm result: %d", r);
+ return r;
+}
+
+static int samv_set_gpnvm(struct target *target, unsigned gpnvm)
+{
+ int r;
+ unsigned v;
+ if (gpnvm >= SAMV_NUM_GPNVM_BITS) {
+ LOG_ERROR("invalid gpnvm %d, max: %d", gpnvm, SAMV_NUM_GPNVM_BITS);
+ return ERROR_FAIL;
+ }
+
+ r = samv_get_gpnvm(target, gpnvm, &v);
+ if (r != ERROR_OK)
+ return r;
+ if (v) {
+ r = ERROR_OK; /* the gpnvm bit is already set */
+ } else {
+ /* we need to set it */
+ r = samv_efc_perform_command(target, SAMV_EFC_FCMD_SFB, gpnvm, NULL);
+ }
+ return r;
+}
+
+static int samv_flash_unlock(struct target *target,
+ unsigned start_sector, unsigned end_sector)
+{
+ int r;
+ uint32_t status;
+ uint32_t pg;
+ uint32_t pages_per_sector;
+
+ /* todo: look into this... i think this should be done on lock regions */
+ pages_per_sector = SAMV_SECTOR_SIZE / SAMV_PAGE_SIZE;
+ while (start_sector <= end_sector) {
+ pg = start_sector * pages_per_sector;
+ r = samv_efc_perform_command(target, SAMV_EFC_FCMD_CLB, pg, &status);
+ if (r != ERROR_OK)
+ return r;
+ start_sector++;
+ }
+ return ERROR_OK;
+}
+
+static int samv_flash_lock(struct target *target,
+ unsigned start_sector, unsigned end_sector)
+{
+ uint32_t status;
+ uint32_t pg;
+ uint32_t pages_per_sector;
+ int r;
+
+ /* todo: look into this... i think this should be done on lock regions */
+ pages_per_sector = SAMV_SECTOR_SIZE / SAMV_PAGE_SIZE;
+ while (start_sector <= end_sector) {
+ pg = start_sector * pages_per_sector;
+ r = samv_efc_perform_command(target, SAMV_EFC_FCMD_SLB, pg, &status);
+ if (r != ERROR_OK)
+ return r;
+ start_sector++;
+ }
+ return ERROR_OK;
+}
+
+static int samv_protect_check(struct flash_bank *bank)
+{
+ int r;
+ uint32_t v[4] = {0};
+
+ r = samv_efc_perform_command(bank->target, SAMV_EFC_FCMD_GLB, 0, NULL);
+ if (r == ERROR_OK) {
+ samv_efc_get_result(bank->target, &v[0]);
+ samv_efc_get_result(bank->target, &v[1]);
+ samv_efc_get_result(bank->target, &v[2]);
+ r = samv_efc_get_result(bank->target, &v[3]);
+ }
+ if (r != ERROR_OK)
+ return r;
+
+ for (int x = 0; x < bank->num_sectors; x++)
+ bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
+ return ERROR_OK;
+}
+
+FLASH_BANK_COMMAND_HANDLER(samv_flash_bank_command)
+{
+ LOG_INFO("flash bank command");
+ struct samv_flash_bank *samv_info;
+ samv_info = calloc(1, sizeof(struct samv_flash_bank));
+ bank->driver_priv = samv_info;
+ return ERROR_OK;
+}
+
+static int samv_get_device_id(struct flash_bank *bank, uint32_t *device_id)
+{
+ return target_read_u32(bank->target, SAMV_CHIPID_CIDR, device_id);
+}
+
+static int samv_probe(struct flash_bank *bank)
+{
+ uint32_t device_id;
+ int r = samv_get_device_id(bank, &device_id);
+ if (r != ERROR_OK)
+ return r;
+ LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+
+ uint8_t eproc = (device_id >> 5) & 0x7;
+ if (eproc != 0) {
+ LOG_ERROR("unexpected eproc code: %d was expecting 0 (cortex-m7)", eproc);
+ return ERROR_FAIL;
+ }
+
+ uint8_t nvm_size_code = (device_id >> 8) & 0xf;
+ switch (nvm_size_code) {
+ case 12:
+ bank->size = 1024 * 1024;
+ break;
+ case 14:
+ bank->size = 2048 * 1024;
+ break;
+ default:
+ LOG_ERROR("unrecognized flash size code: %d", nvm_size_code);
+ return ERROR_FAIL;
+ break;
+ }
+
+ struct samv_flash_bank *samv_info = bank->driver_priv;
+ samv_info->size_bytes = bank->size;
+ samv_info->probed = 1;
+
+ bank->base = SAMV_FLASH_BASE;
+ bank->num_sectors = bank->size / SAMV_SECTOR_SIZE;
+ bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
+ for (int s = 0; s < (int)bank->num_sectors; s++) {
+ bank->sectors[s].size = SAMV_SECTOR_SIZE;
+ bank->sectors[s].offset = s * SAMV_SECTOR_SIZE;
+ bank->sectors[s].is_erased = -1;
+ bank->sectors[s].is_protected = -1;
+ }
+
+ r = samv_protect_check(bank);
+ if (r != ERROR_OK)
+ return r;
+
+ return ERROR_OK;
+}
+
+static int samv_auto_probe(struct flash_bank *bank)
+{
+ struct samv_flash_bank *samv_info = bank->driver_priv;
+ if (samv_info->probed)
+ return ERROR_OK;
+ return samv_probe(bank);
+}
+
+static int samv_erase(struct flash_bank *bank, int first, int last)
+{
+ const int page_count = 32; /* 32 pages equals 16 KB lock region */
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int r = samv_auto_probe(bank);
+ if (r != ERROR_OK)
+ return r;
+
+ /* easy case: we've been requested to erase the entire flash */
+ if ((first == 0) && ((last + 1) == (int)(bank->num_sectors)))
+ return samv_efc_perform_command(bank->target, SAMV_EFC_FCMD_EA, 0, NULL);
+
+ LOG_INFO("erasing lock regions %d-%d...", first, last);
+
+ for (int i = first; i <= last; i++) {
+ uint32_t status;
+ r = samv_erase_pages(bank->target, (i * page_count), page_count, &status);
+ LOG_INFO("erasing lock region %d", i);
+ if (r != ERROR_OK)
+ LOG_ERROR("error performing erase page @ lock region number %d",
+ (unsigned int)(i));
+ if (status & (1 << 2)) {
+ LOG_ERROR("lock region %d is locked", (unsigned int)(i));
+ return ERROR_FAIL;
+ }
+ if (status & (1 << 1)) {
+ LOG_ERROR("flash command error @lock region %d", (unsigned int)(i));
+ return ERROR_FAIL;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int samv_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int r;
+ if (set)
+ r = samv_flash_lock(bank->target, (unsigned)(first), (unsigned)(last));
+ else
+ r = samv_flash_unlock(bank->target, (unsigned)(first), (unsigned)(last));
+
+ return r;
+}
+
+static int samv_page_read(struct target *target,
+ unsigned page_num, uint8_t *buf)
+{
+ uint32_t addr = SAMV_FLASH_BASE + page_num * SAMV_PAGE_SIZE;
+ int r = target_read_memory(target, addr, 4, SAMV_PAGE_SIZE / 4, buf);
+ if (r != ERROR_OK)
+ LOG_ERROR("flash program failed to read page @ 0x%08x",
+ (unsigned int)(addr));
+ return r;
+}
+
+static int samv_page_write(struct target *target,
+ unsigned pagenum, const uint8_t *buf)
+{
+ uint32_t status;
+ const uint32_t addr = SAMV_FLASH_BASE + pagenum * SAMV_PAGE_SIZE;
+ int r;
+
+ LOG_DEBUG("write page %u at address 0x%08x", pagenum, (unsigned int)addr);
+ r = target_write_memory(target, addr, 4, SAMV_PAGE_SIZE / 4, buf);
+ if (r != ERROR_OK) {
+ LOG_ERROR("failed to buffer page at 0x%08x", (unsigned int)addr);
+ return r;
+ }
+
+ r = samv_efc_perform_command(target, SAMV_EFC_FCMD_WP, pagenum, &status);
+ if (r != ERROR_OK)
+ LOG_ERROR("error performing write page at 0x%08x", (unsigned int)addr);
+ if (status & (1 << 2)) {
+ LOG_ERROR("page at 0x%08x is locked", (unsigned int)addr);
+ return ERROR_FAIL;
+ }
+ if (status & (1 << 1)) {
+ LOG_ERROR("flash command error at 0x%08x", (unsigned int)addr);
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static int samv_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (count == 0)
+ return ERROR_OK;
+
+ if ((offset + count) > bank->size) {
+ LOG_ERROR("flash write error - past end of bank");
+ LOG_ERROR(" offset: 0x%08x, count 0x%08x, bank end: 0x%08x",
+ (unsigned int)(offset),
+ (unsigned int)(count),
+ (unsigned int)(bank->size));
+ return ERROR_FAIL;
+ }
+
+ uint8_t pagebuffer[SAMV_PAGE_SIZE] = {0};
+ uint32_t page_cur = offset / SAMV_PAGE_SIZE;
+ uint32_t page_end = (offset + count - 1) / SAMV_PAGE_SIZE;
+
+ LOG_DEBUG("offset: 0x%08x, count: 0x%08x",
+ (unsigned int)(offset), (unsigned int)(count));
+ LOG_DEBUG("page start: %d, page end: %d", (int)(page_cur), (int)(page_end));
+
+ /* Special case: all one page */
+ /* Otherwise: */
+ /* (1) non-aligned start */
+ /* (2) body pages */
+ /* (3) non-aligned end. */
+
+ int r;
+ uint32_t page_offset;
+
+ /* handle special case - all one page. */
+ if (page_cur == page_end) {
+ LOG_DEBUG("special case, all in one page");
+ r = samv_page_read(bank->target, page_cur, pagebuffer);
+ if (r != ERROR_OK)
+ return r;
+
+ page_offset = offset & (SAMV_PAGE_SIZE-1);
+ memcpy(pagebuffer + page_offset, buffer, count);
+
+ r = samv_page_write(bank->target, page_cur, pagebuffer);
+ if (r != ERROR_OK)
+ return r;
+ return ERROR_OK;
+ }
+
+ /* step 1) handle the non-aligned starting address */
+ page_offset = offset & (SAMV_PAGE_SIZE - 1);
+ if (page_offset) {
+ LOG_DEBUG("non-aligned start");
+ /* read the partial page */
+ r = samv_page_read(bank->target, page_cur, pagebuffer);
+ if (r != ERROR_OK)
+ return r;
+
+ /* over-write with new data */
+ uint32_t n = SAMV_PAGE_SIZE - page_offset;
+ memcpy(pagebuffer + page_offset, buffer, n);
+
+ r = samv_page_write(bank->target, page_cur, pagebuffer);
+ if (r != ERROR_OK)
+ return r;
+
+ count -= n;
+ offset += n;
+ buffer += n;
+ page_cur++;
+ }
+
+ /* By checking that offset is correct here, we also fix a clang warning */
+ assert(offset % SAMV_PAGE_SIZE == 0);
+
+ /* step 2) handle the full pages */
+ LOG_DEBUG("full page loop: cur=%d, end=%d, count = 0x%08x",
+ (int)page_cur, (int)page_end, (unsigned int)(count));
+
+ while ((page_cur < page_end) && (count >= SAMV_PAGE_SIZE)) {
+ r = samv_page_write(bank->target, page_cur, buffer);
+ if (r != ERROR_OK)
+ return r;
+ count -= SAMV_PAGE_SIZE;
+ buffer += SAMV_PAGE_SIZE;
+ page_cur += 1;
+ }
+
+ /* step 3) write final page, if it's partial (otherwise it's already done) */
+ if (count) {
+ LOG_DEBUG("final partial page, count = 0x%08x", (unsigned int)(count));
+ /* we have a partial page */
+ r = samv_page_read(bank->target, page_cur, pagebuffer);
+ if (r != ERROR_OK)
+ return r;
+ memcpy(pagebuffer, buffer, count); /* data goes at start of page */
+ r = samv_page_write(bank->target, page_cur, pagebuffer);
+ if (r != ERROR_OK)
+ return r;
+ }
+ return ERROR_OK;
+}
+
+static int samv_get_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct samv_flash_bank *samv_info = bank->driver_priv;
+ if (!samv_info->probed) {
+ int r = samv_probe(bank);
+ if (ERROR_OK != r)
+ return r;
+ }
+ snprintf(buf, buf_size, "Cortex-M7 detected with %d kB flash",
+ bank->size / 1024);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(samv_handle_gpnvm_command)
+{
+ struct flash_bank *bank = get_flash_bank_by_num_noprobe(0);
+ if (!bank)
+ return ERROR_FAIL;
+ struct samv_flash_bank *samv_info = bank->driver_priv;
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int r;
+ if (!samv_info->probed) {
+ r = samv_auto_probe(bank);
+ if (r != ERROR_OK)
+ return r;
+ }
+
+ int who = 0;
+
+ switch (CMD_ARGC) {
+ case 0:
+ goto showall;
+ break;
+ case 1:
+ who = -1;
+ break;
+ case 2:
+ if (!strcmp(CMD_ARGV[0], "show") && !strcmp(CMD_ARGV[1], "all"))
+ who = -1;
+ else {
+ uint32_t v32;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], v32);
+ who = v32;
+ }
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ break;
+ }
+
+ uint32_t v;
+ if (!strcmp("show", CMD_ARGV[0])) {
+ if (who == -1) {
+showall:
+ r = ERROR_OK;
+ for (int x = 0; x < SAMV_NUM_GPNVM_BITS; x++) {
+ r = samv_get_gpnvm(target, x, &v);
+ if (r != ERROR_OK)
+ break;
+ command_print(CMD_CTX, "samv-gpnvm%u: %u", x, v);
+ }
+ return r;
+ }
+ if ((who >= 0) && (((unsigned)who) < SAMV_NUM_GPNVM_BITS)) {
+ r = samv_get_gpnvm(target, who, &v);
+ command_print(CMD_CTX, "samv-gpnvm%u: %u", who, v);
+ return r;
+ } else {
+ command_print(CMD_CTX, "invalid gpnvm: %u", who);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ }
+
+ if (who == -1) {
+ command_print(CMD_CTX, "missing gpnvm number");
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ if (!strcmp("set", CMD_ARGV[0]))
+ r = samv_set_gpnvm(target, who);
+ else if (!strcmp("clr", CMD_ARGV[0]) || !strcmp("clear", CMD_ARGV[0]))
+ r = samv_clear_gpnvm(target, who);
+ else {
+ command_print(CMD_CTX, "unknown command: %s", CMD_ARGV[0]);
+ r = ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ return r;
+}
+
+static const struct command_registration atsamv_exec_command_handlers[] = {
+ {
+ .name = "gpnvm",
+ .handler = samv_handle_gpnvm_command,
+ .mode = COMMAND_EXEC,
+ .usage = "[('clr'|'set'|'show') bitnum]",
+ .help = "Without arguments, shows all bits in the gpnvm "
+ "register. Otherwise, clears, sets, or shows one "
+ "General Purpose Non-Volatile Memory (gpnvm) bit.",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration atsamv_command_handlers[] = {
+ {
+ .name = "atsamv",
+ .mode = COMMAND_ANY,
+ .help = "atsamv flash command group",
+ .usage = "",
+ .chain = atsamv_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver atsamv_flash = {
+ .name = "atsamv",
+ .commands = atsamv_command_handlers,
+ .flash_bank_command = samv_flash_bank_command,
+ .erase = samv_erase,
+ .protect = samv_protect,
+ .write = samv_write,
+ .read = default_flash_read,
+ .probe = samv_probe,
+ .auto_probe = samv_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = samv_protect_check,
+ .info = samv_get_info,
+};
http://git-wip-us.apache.org/repos/asf/incubator-mynewt-site/blob/e302582d/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/avrf.c
----------------------------------------------------------------------
diff --git a/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/avrf.c b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/avrf.c
new file mode 100755
index 0000000..1984c9e
--- /dev/null
+++ b/docs/os/tutorials/downloads/openocd-code-89bf96ffe6ac66c80407af8383b9d5adc0dc35f4/src/flash/nor/avrf.c
@@ -0,0 +1,491 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * SimonQian@SimonQian.com *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <target/avrt.h>
+
+/* AVR_JTAG_Instructions */
+#define AVR_JTAG_INS_LEN 4
+/* Public Instructions: */
+#define AVR_JTAG_INS_EXTEST 0x00
+#define AVR_JTAG_INS_IDCODE 0x01
+#define AVR_JTAG_INS_SAMPLE_PRELOAD 0x02
+#define AVR_JTAG_INS_BYPASS 0x0F
+/* AVR Specified Public Instructions: */
+#define AVR_JTAG_INS_AVR_RESET 0x0C
+#define AVR_JTAG_INS_PROG_ENABLE 0x04
+#define AVR_JTAG_INS_PROG_COMMANDS 0x05
+#define AVR_JTAG_INS_PROG_PAGELOAD 0x06
+#define AVR_JTAG_INS_PROG_PAGEREAD 0x07
+
+/* Data Registers: */
+#define AVR_JTAG_REG_Bypass_Len 1
+#define AVR_JTAG_REG_DeviceID_Len 32
+
+#define AVR_JTAG_REG_Reset_Len 1
+#define AVR_JTAG_REG_JTAGID_Len 32
+#define AVR_JTAG_REG_ProgrammingEnable_Len 16
+#define AVR_JTAG_REG_ProgrammingCommand_Len 15
+#define AVR_JTAG_REG_FlashDataByte_Len 16
+
+struct avrf_type {
+ char name[15];
+ uint16_t chip_id;
+ int flash_page_size;
+ int flash_page_num;
+ int eeprom_page_size;
+ int eeprom_page_num;
+};
+
+struct avrf_flash_bank {
+ int ppage_size;
+ int probed;
+};
+
+static const struct avrf_type avft_chips_info[] = {
+/* name, chip_id, flash_page_size, flash_page_num,
+ * eeprom_page_size, eeprom_page_num
+ */
+ {"atmega128", 0x9702, 256, 512, 8, 512},
+ {"at90can128", 0x9781, 256, 512, 8, 512},
+ {"at90usb128", 0x9782, 256, 512, 8, 512},
+ {"atmega164p", 0x940a, 128, 128, 4, 128},
+ {"atmega324p", 0x9508, 128, 256, 4, 256},
+ {"atmega324pa", 0x9511, 128, 256, 4, 256},
+ {"atmega644p", 0x960a, 256, 256, 8, 256},
+ {"atmega1284p", 0x9705, 256, 512, 8, 512},
+};
+
+/* avr program functions */
+static int avr_jtag_reset(struct avr_common *avr, uint32_t reset)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, reset, AVR_JTAG_REG_Reset_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtag_read_jtagid(struct avr_common *avr, uint32_t *id)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
+ avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_enterprogmode(struct avr_common *avr)
+{
+ avr_jtag_reset(avr, 1);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_leaveprogmode(struct avr_common *avr)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ avr_jtag_reset(avr, 0);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_chiperase(struct avr_common *avr)
+{
+ uint32_t poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do {
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap,
+ &poll_value,
+ 0x3380,
+ AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ return ERROR_FAIL;
+ LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
+ } while (!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_writeflashpage(struct avr_common *avr,
+ const uint8_t *page_buf,
+ uint32_t buf_size,
+ uint32_t addr,
+ uint32_t page_size)
+{
+ uint32_t i, poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ /* load addr high byte */
+ avr_jtag_senddat(avr->jtag_info.tap,
+ NULL,
+ 0x0700 | ((addr >> 9) & 0xFF),
+ AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ /* load addr low byte */
+ avr_jtag_senddat(avr->jtag_info.tap,
+ NULL,
+ 0x0300 | ((addr >> 1) & 0xFF),
+ AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
+
+ for (i = 0; i < page_size; i++) {
+ if (i < buf_size)
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
+ else
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
+ }
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do {
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap,
+ &poll_value,
+ 0x3700,
+ AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ return ERROR_FAIL;
+ LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
+ } while (!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+FLASH_BANK_COMMAND_HANDLER(avrf_flash_bank_command)
+{
+ struct avrf_flash_bank *avrf_info;
+
+ if (CMD_ARGC < 6)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ avrf_info = malloc(sizeof(struct avrf_flash_bank));
+ bank->driver_priv = avrf_info;
+
+ avrf_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static int avrf_erase(struct flash_bank *bank, int first, int last)
+{
+ struct target *target = bank->target;
+ struct avr_common *avr = target->arch_info;
+ int status;
+
+ LOG_DEBUG("%s", __func__);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ status = avr_jtagprg_enterprogmode(avr);
+ if (status != ERROR_OK)
+ return status;
+
+ status = avr_jtagprg_chiperase(avr);
+ if (status != ERROR_OK)
+ return status;
+
+ return avr_jtagprg_leaveprogmode(avr);
+}
+
+static int avrf_protect(struct flash_bank *bank, int set, int first, int last)
+{
+ LOG_INFO("%s", __func__);
+ return ERROR_OK;
+}
+
+static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+ struct target *target = bank->target;
+ struct avr_common *avr = target->arch_info;
+ uint32_t cur_size, cur_buffer_size, page_size;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ page_size = bank->sectors[0].size;
+ if ((offset % page_size) != 0) {
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required %" PRIu32 "-byte alignment",
+ offset,
+ page_size);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
+ LOG_DEBUG("count is %" PRId32 "", count);
+
+ if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ return ERROR_FAIL;
+
+ cur_size = 0;
+ while (count > 0) {
+ if (count > page_size)
+ cur_buffer_size = page_size;
+ else
+ cur_buffer_size = count;
+ avr_jtagprg_writeflashpage(avr,
+ buffer + cur_size,
+ cur_buffer_size,
+ offset + cur_size,
+ page_size);
+ count -= cur_buffer_size;
+ cur_size += cur_buffer_size;
+
+ keep_alive();
+ }
+
+ return avr_jtagprg_leaveprogmode(avr);
+}
+
+#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
+#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
+#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
+
+static int avrf_probe(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct avrf_flash_bank *avrf_info = bank->driver_priv;
+ struct avr_common *avr = target->arch_info;
+ const struct avrf_type *avr_info = NULL;
+ int i;
+ uint32_t device_id;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avrf_info->probed = 0;
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ return ERROR_FAIL;
+
+ LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
+ EXTRACT_MFG(device_id),
+ 0x1F);
+
+ for (i = 0; i < (int)ARRAY_SIZE(avft_chips_info); i++) {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id)) {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+ break;
+ }
+ }
+
+ if (avr_info != NULL) {
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ /* chip found */
+ bank->base = 0x00000000;
+ bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
+ bank->num_sectors = avr_info->flash_page_num;
+ bank->sectors = malloc(sizeof(struct flash_sector) * avr_info->flash_page_num);
+
+ for (i = 0; i < avr_info->flash_page_num; i++) {
+ bank->sectors[i].offset = i * avr_info->flash_page_size;
+ bank->sectors[i].size = avr_info->flash_page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ avrf_info->probed = 1;
+ return ERROR_OK;
+ } else {
+ /* chip not supported */
+ LOG_ERROR("0x%" PRIx32 " is not support for avr", EXTRACT_PART(device_id));
+
+ avrf_info->probed = 1;
+ return ERROR_FAIL;
+ }
+}
+
+static int avrf_auto_probe(struct flash_bank *bank)
+{
+ struct avrf_flash_bank *avrf_info = bank->driver_priv;
+ if (avrf_info->probed)
+ return ERROR_OK;
+ return avrf_probe(bank);
+}
+
+static int avrf_protect_check(struct flash_bank *bank)
+{
+ LOG_INFO("%s", __func__);
+ return ERROR_OK;
+}
+
+static int avrf_info(struct flash_bank *bank, char *buf, int buf_size)
+{
+ struct target *target = bank->target;
+ struct avr_common *avr = target->arch_info;
+ const struct avrf_type *avr_info = NULL;
+ int i;
+ uint32_t device_id;
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ return ERROR_FAIL;
+
+ LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
+ EXTRACT_MFG(device_id),
+ 0x1F);
+
+ for (i = 0; i < (int)ARRAY_SIZE(avft_chips_info); i++) {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id)) {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+
+ break;
+ }
+ }
+
+ if (avr_info != NULL) {
+ /* chip found */
+ snprintf(buf, buf_size, "%s - Rev: 0x%" PRIx32 "", avr_info->name,
+ EXTRACT_VER(device_id));
+ return ERROR_OK;
+ } else {
+ /* chip not supported */
+ snprintf(buf, buf_size, "Cannot identify target as a avr\n");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+}
+
+static int avrf_mass_erase(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct avr_common *avr = target->arch_info;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ || (ERROR_OK != avr_jtagprg_chiperase(avr))
+ || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
+ return ERROR_FAIL;
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(avrf_handle_mass_erase_command)
+{
+ int i;
+
+ if (CMD_ARGC < 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (ERROR_OK != retval)
+ return retval;
+
+ if (avrf_mass_erase(bank) == ERROR_OK) {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_erased = 1;
+
+ command_print(CMD_CTX, "avr mass erase complete");
+ } else
+ command_print(CMD_CTX, "avr mass erase failed");
+
+ LOG_DEBUG("%s", __func__);
+ return ERROR_OK;
+}
+
+static const struct command_registration avrf_exec_command_handlers[] = {
+ {
+ .name = "mass_erase",
+ .usage = "<bank>",
+ .handler = avrf_handle_mass_erase_command,
+ .mode = COMMAND_EXEC,
+ .help = "erase entire device",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+static const struct command_registration avrf_command_handlers[] = {
+ {
+ .name = "avrf",
+ .mode = COMMAND_ANY,
+ .help = "AVR flash command group",
+ .usage = "",
+ .chain = avrf_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct flash_driver avr_flash = {
+ .name = "avr",
+ .commands = avrf_command_handlers,
+ .flash_bank_command = avrf_flash_bank_command,
+ .erase = avrf_erase,
+ .protect = avrf_protect,
+ .write = avrf_write,
+ .read = default_flash_read,
+ .probe = avrf_probe,
+ .auto_probe = avrf_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = avrf_protect_check,
+ .info = avrf_info,
+};